Merge "Asoc: msm: Volume and Mute support for Voip." into msm-3.0
diff --git a/Documentation/devicetree/bindings/tty/serial/msm_serial.txt b/Documentation/devicetree/bindings/tty/serial/msm_serial.txt
new file mode 100644
index 0000000..943c846
--- /dev/null
+++ b/Documentation/devicetree/bindings/tty/serial/msm_serial.txt
@@ -0,0 +1,15 @@
+* Qualcomm MSM HSUART
+
+Required properties:
+- compatible : one of:
+ - "qcom,msm-lsuart-v14"
+- reg : offset and length of the register set for the device.
+- interrupts : should contain the uart interrupt.
+
+Example:
+
+ serial@19c400000 {
+ compatible = "qcom,msm-lsuart-v14"
+ reg = <0x19c40000 0x1000">;
+ interrupts = <195>;
+ };
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2e7f3a3..f34719f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1606,8 +1606,8 @@
def_bool n
depends on MEMORY_HOTPLUG
-config DONT_RESERVE_FROM_MOVABLE_ZONE
- def_bool y
+config FIX_MOVABLE_ZONE
+ def_bool n
depends on MEMORY_HOTPLUG
config DONT_MAP_HOLE_AFTER_MEMBANK0
diff --git a/arch/arm/boot/dts/msmcopper.dts b/arch/arm/boot/dts/msmcopper.dts
index 4e3d66d..52c0b66 100644
--- a/arch/arm/boot/dts/msmcopper.dts
+++ b/arch/arm/boot/dts/msmcopper.dts
@@ -14,4 +14,10 @@
reg = <0xF9000000 0x1000>,
<0xF9002000 0x1000>;
};
+
+ serial@F9684000 {
+ compatible = "qcom,msm-lsuart-v14";
+ reg = <0xF9684000 0x1000>;
+ interrupts = <109>;
+ };
};
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 786f4fa..dbf3427 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -277,7 +277,8 @@
if (gic_arch_extn.irq_retrigger)
return gic_arch_extn.irq_retrigger(d);
- return -ENXIO;
+ /* the retrigger expects 0 for failure */
+ return 0;
}
#ifdef CONFIG_SMP
diff --git a/arch/arm/configs/msm7630-perf_defconfig b/arch/arm/configs/msm7630-perf_defconfig
index 5b52404..202d117 100644
--- a/arch/arm/configs/msm7630-perf_defconfig
+++ b/arch/arm/configs/msm7630-perf_defconfig
@@ -71,7 +71,7 @@
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
+CONFIG_INET_DIAG=y
CONFIG_IPV6=y
CONFIG_IPV6_PRIVACY=y
CONFIG_IPV6_ROUTER_PREF=y
@@ -175,7 +175,7 @@
CONFIG_MSM_BT_POWER=y
# CONFIG_WIRELESS_EXT_SYSFS is not set
CONFIG_RFKILL=y
-# CONFIG_RFKILL_PM is not set
+CONFIG_RFKILL_PM=y
CONFIG_MTD=y
CONFIG_MTD_TESTS=m
CONFIG_MTD_CMDLINE_PARTS=y
@@ -208,6 +208,8 @@
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
CONFIG_LIBRA_SDIOIF=m
+CONFIG_CFG80211=y
+CONFIG_CFG80211_WEXT=n
CONFIG_SLIP=y
CONFIG_SLIP_COMPRESSED=y
CONFIG_SLIP_MODE_SLIP6=y
diff --git a/arch/arm/configs/msm7630_defconfig b/arch/arm/configs/msm7630_defconfig
index 9ad0b5a..bc944d0 100644
--- a/arch/arm/configs/msm7630_defconfig
+++ b/arch/arm/configs/msm7630_defconfig
@@ -70,7 +70,7 @@
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
+CONFIG_INET_DIAG=y
CONFIG_IPV6=y
CONFIG_IPV6_PRIVACY=y
CONFIG_IPV6_ROUTER_PREF=y
@@ -174,7 +174,7 @@
CONFIG_MSM_BT_POWER=y
# CONFIG_WIRELESS_EXT_SYSFS is not set
CONFIG_RFKILL=y
-# CONFIG_RFKILL_PM is not set
+CONFIG_RFKILL_PM=y
CONFIG_MTD=y
CONFIG_MTD_TESTS=m
CONFIG_MTD_CMDLINE_PARTS=y
@@ -207,6 +207,8 @@
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
CONFIG_LIBRA_SDIOIF=m
+CONFIG_CFG80211=y
+CONFIG_CFG80211_WEXT=n
CONFIG_SLIP=y
CONFIG_SLIP_COMPRESSED=y
CONFIG_SLIP_MODE_SLIP6=y
diff --git a/arch/arm/configs/msm8660-perf_defconfig b/arch/arm/configs/msm8660-perf_defconfig
index 0f41c0a..d377460 100644
--- a/arch/arm/configs/msm8660-perf_defconfig
+++ b/arch/arm/configs/msm8660-perf_defconfig
@@ -104,7 +104,7 @@
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
+CONFIG_INET_DIAG=y
CONFIG_IPV6=y
CONFIG_IPV6_PRIVACY=y
CONFIG_IPV6_ROUTER_PREF=y
@@ -315,6 +315,8 @@
CONFIG_MT9E013=y
CONFIG_MSM_GEMINI=y
CONFIG_RADIO_TAVARUA=y
+CONFIG_ION=y
+CONFIG_ION_MSM=y
CONFIG_MSM_KGSL=y
CONFIG_KGSL_PER_PROCESS_PAGE_TABLE=y
CONFIG_VIDEO_OUTPUT_CONTROL=y
diff --git a/arch/arm/configs/msm8660_defconfig b/arch/arm/configs/msm8660_defconfig
index e900062..2569f82 100644
--- a/arch/arm/configs/msm8660_defconfig
+++ b/arch/arm/configs/msm8660_defconfig
@@ -95,7 +95,7 @@
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
+CONFIG_INET_DIAG=y
CONFIG_IPV6=y
CONFIG_IPV6_PRIVACY=y
CONFIG_IPV6_ROUTER_PREF=y
diff --git a/arch/arm/configs/msm8960_defconfig b/arch/arm/configs/msm8960_defconfig
index 73d0756..b3e0b3c 100755
--- a/arch/arm/configs/msm8960_defconfig
+++ b/arch/arm/configs/msm8960_defconfig
@@ -32,6 +32,7 @@
CONFIG_MODVERSIONS=y
CONFIG_ARCH_MSM=y
CONFIG_ARCH_MSM8960=y
+CONFIG_ARCH_MSM8930=y
CONFIG_ARCH_APQ8064=y
CONFIG_MSM_KRAIT_TBB_ABORT_HANDLER=y
CONFIG_MACH_MSM8960_SIM=y
@@ -40,6 +41,9 @@
CONFIG_MACH_MSM8960_MTP=y
CONFIG_MACH_MSM8960_FLUID=y
CONFIG_MACH_MSM8960_LIQUID=y
+CONFIG_MACH_MSM8930_CDP=y
+CONFIG_MACH_MSM8930_MTP=y
+CONFIG_MACH_MSM8930_FLUID=y
CONFIG_MACH_APQ8064_SIM=y
CONFIG_MACH_APQ8064_RUMI3=y
# CONFIG_MSM_STACKED_MEMORY is not set
@@ -97,7 +101,7 @@
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
+CONFIG_INET_DIAG=y
CONFIG_IPV6=y
CONFIG_IPV6_PRIVACY=y
CONFIG_IPV6_ROUTER_PREF=y
@@ -311,6 +315,7 @@
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_EHSET=y
CONFIG_USB_EHCI_MSM=y
+CONFIG_USB_EHCI_MSM_HSIC=y
CONFIG_USB_ACM=y
CONFIG_USB_STORAGE=y
CONFIG_USB_STORAGE_DEBUG=y
@@ -335,6 +340,7 @@
CONFIG_MMC=y
CONFIG_MMC_PERF_PROFILING=y
CONFIG_MMC_UNSAFE_RESUME=y
+CONFIG_MMC_CLKGATE=y
CONFIG_MMC_PARANOID_SD_INIT=y
CONFIG_MMC_BLOCK_MINORS=32
CONFIG_MMC_MSM=y
@@ -383,11 +389,18 @@
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
+CONFIG_LOCKUP_DETECTOR=y
# CONFIG_SCHED_DEBUG is not set
CONFIG_TIMER_STATS=y
+CONFIG_SLUB_DEBUG_ON=y
# CONFIG_DEBUG_PREEMPT is not set
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_MUTEXES=y
+CONFIG_DEBUG_SPINLOCK_SLEEP=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DEBUG_LIST=y
+CONFIG_DEBUG_PAGEALLOC=y
CONFIG_DYNAMIC_DEBUG=y
CONFIG_DEBUG_USER=y
CONFIG_CRYPTO_SHA256=y
diff --git a/arch/arm/configs/msm9615_defconfig b/arch/arm/configs/msm9615_defconfig
index 7ef47c8..714e630 100644
--- a/arch/arm/configs/msm9615_defconfig
+++ b/arch/arm/configs/msm9615_defconfig
@@ -104,8 +104,13 @@
CONFIG_THERMAL=y
CONFIG_THERMAL_TSENS8960=y
CONFIG_MFD_PM8018_CORE=y
-# CONFIG_MFD_PM8XXX_PWM is not set
+CONFIG_MFD_PM8XXX_PWM=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_PM8XXX=y
+# CONFIG_LEDS_MSM_PMIC is not set
CONFIG_REGULATOR=y
+CONFIG_REGULATOR_GPIO=y
# CONFIG_HID_SUPPORT is not set
CONFIG_USB=y
CONFIG_USB_GADGET=y
@@ -113,6 +118,7 @@
CONFIG_USB_G_ANDROID=y
CONFIG_SWITCH=y
CONFIG_NET=y
+CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
@@ -205,3 +211,23 @@
CONFIG_CRYPTO_DEV_QCEDEV=m
CONFIG_CRC_CCITT=y
CONFIG_LIBCRC32C=y
+
+CONFIG_WIRELESS=y
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_CFG80211=y
+CONFIG_CFG80211_WEXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_LIB80211=m
+CONFIG_NETDEVICES=y
+CONFIG_WLAN=y
+# CONFIG_MSM_RMNET is not set
+CONFIG_MSM_BAM_DMUX=y
+CONFIG_MSM_RMNET_BAM=y
+CONFIG_HOSTAP=m
+CONFIG_WIRELESS_EXT=y
+CONFIG_WEXT_SPY=y
+CONFIG_WEXT_PRIV=y
+CONFIG_LIB80211_CRYPT_WEP=m
+CONFIG_LIB80211_CRYPT_CCMP=m
+CONFIG_LIB80211_CRYPT_TKIP=m
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index ae744a8..b44f46f 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -35,6 +35,7 @@
struct meminfo *);
void (*reserve)(void);/* reserve mem blocks */
void (*map_io)(void);/* IO mapping function */
+ void (*init_very_early)(void);
void (*init_early)(void);
void (*init_irq)(void);
struct sys_timer *timer; /* system tick timer */
diff --git a/arch/arm/include/asm/mach/mmc.h b/arch/arm/include/asm/mach/mmc.h
index f138df1..6e55bf3 100644
--- a/arch/arm/include/asm/mach/mmc.h
+++ b/arch/arm/include/asm/mach/mmc.h
@@ -37,6 +37,11 @@
* is set voltage supported for this regulator?
* false => set voltage is not supported
* true => set voltage is supported
+ *
+ * Some regulators (like gpio-regulators, LVS (low voltage swtiches)
+ * PMIC regulators) dont have the capability to call
+ * regulator_set_voltage or regulator_set_optimum_mode
+ * Use this variable to indicate if its a such regulator or not
*/
bool set_voltage_sup;
/* is this regulator enabled? */
diff --git a/arch/arm/kernel/perf_event_msm.c b/arch/arm/kernel/perf_event_msm.c
index ae8bfcb..fb53650 100644
--- a/arch/arm/kernel/perf_event_msm.c
+++ b/arch/arm/kernel/perf_event_msm.c
@@ -16,6 +16,11 @@
#include "../vfp/vfpinstr.h"
#ifdef CONFIG_CPU_V7
+#define SCORPION_EVT_PREFIX 1
+#define SCORPION_MAX_L1_REG 4
+
+static u32 scorpion_evt_type_base[] = {0x4c, 0x50, 0x54, 0x58, 0x5c};
+
enum scorpion_perf_common {
SCORPION_EVT_START_IDX = 0x4c,
SCORPION_ICACHE_EXPL_INV = 0x4c,
@@ -356,6 +361,25 @@
struct scorpion_evt *evtinfo)
{
u32 idx;
+ u8 prefix;
+ u8 reg;
+ u8 code;
+ u8 group;
+
+ prefix = (scorpion_evt_type & 0xF0000) >> 16;
+ if (prefix == SCORPION_EVT_PREFIX) {
+ reg = (scorpion_evt_type & 0x0F000) >> 12;
+ code = (scorpion_evt_type & 0x00FF0) >> 4;
+ group = scorpion_evt_type & 0x0000F;
+
+ if ((group > 3) || (reg > SCORPION_MAX_L1_REG))
+ return -EINVAL;
+
+ evtinfo->group_setval = 0x80000000 | (code << (group * 8));
+ evtinfo->groupcode = reg;
+ evtinfo->armv7_evt_type = scorpion_evt_type_base[reg] | group;
+ return evtinfo->armv7_evt_type;
+ }
if (scorpion_evt_type < SCORPION_EVT_START_IDX || scorpion_evt_type >=
(ARRAY_SIZE(scorpion_event) + SCORPION_EVT_START_IDX))
@@ -561,7 +585,6 @@
*/
if (idx != ARMV7_CYCLE_COUNTER) {
val = hwc->config_base;
- val &= ARMV7_EVTSEL_MASK;
if (val > 0x40) {
event = get_scorpion_evtinfo(val, &evtinfo);
if (event == -EINVAL)
@@ -601,7 +624,6 @@
*/
if (idx != ARMV7_CYCLE_COUNTER) {
val = hwc->config_base;
- val &= ARMV7_EVTSEL_MASK;
if (val < 0x40) {
armv7_pmnc_write_evtsel(idx, hwc->config_base);
} else {
@@ -670,7 +692,7 @@
.disable = scorpion_pmu_disable_event,
.read_counter = armv7pmu_read_counter,
.write_counter = armv7pmu_write_counter,
- .raw_event_mask = 0xFF,
+ .raw_event_mask = 0xFFFFF,
.get_event_idx = armv7pmu_get_event_idx,
.start = armv7pmu_start,
.stop = armv7pmu_stop,
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 9705e8c..eaf8690 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -903,6 +903,9 @@
parse_early_param();
+ if (mdesc->init_very_early)
+ mdesc->init_very_early();
+
sanity_check_meminfo();
arm_memblock_init(&meminfo, mdesc);
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index ad07bbb..66d1044 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -29,6 +29,7 @@
select MSM_GPIOMUX
select REGULATOR
select MULTI_IRQ_HANDLER
+ select MSM_PROC_COMM_REGULATOR
config ARCH_MSM7X30
bool "MSM7x30"
@@ -43,7 +44,6 @@
select MIGRATION
select ARCH_MEMORY_PROBE
select ARCH_MEMORY_REMOVE
- select DONT_RESERVE_FROM_MOVABLE_ZONE
select MSM_GPIOMUX
select RESERVE_FIRST_PAGE
select MSM_DALRPC
@@ -135,7 +135,7 @@
select MSM_SPM_V2
select MSM_L2_SPM
select MSM_NATIVE_RESTART
- select DONT_MAP_HOLE_AFTER_MEMBANK0
+ select DONT_MAP_HOLE_AFTER_MEMBANK0
select MSM_REMOTE_SPINLOCK_SFPB
select ARCH_POPULATES_NODE_MAP
select ARCH_SPARSEMEM_ENABLE
@@ -147,6 +147,36 @@
select ARCH_MEMORY_REMOVE
select DONT_RESERVE_FROM_MOVABLE_ZONE
+config ARCH_MSM8930
+ bool "MSM8930"
+ select ARCH_MSM_KRAITMP
+ select ARM_GIC
+ select CPU_V7
+ select MSM_V2_TLMM
+ select MSM_GPIOMUX
+ select MSM_SCM if SMP
+ select MSM_DIRECT_SCLK_ACCESS
+ select REGULATOR
+ select MSM_RPM
+ select MSM_XO
+ select MSM_QDSP6_APR
+ select MSM_PIL
+ select MSM_AUDIO_QDSP6 if SND_SOC
+ select CPU_HAS_L2_PMU
+ select MSM_SPM_V2
+ select MSM_L2_SPM
+ select MSM_NATIVE_RESTART
+ select DONT_MAP_HOLE_AFTER_MEMBANK0
+ select MSM_REMOTE_SPINLOCK_SFPB
+ select ARCH_POPULATES_NODE_MAP
+ select ARCH_SPARSEMEM_ENABLE
+ select ARCH_HAS_HOLES_MEMORYMODEL
+ select MEMORY_HOTPLUG
+ select MEMORY_HOTREMOVE
+ select MIGRATION
+ select ARCH_MEMORY_PROBE
+ select ARCH_MEMORY_REMOVE
+
config ARCH_APQ8064
bool "APQ8064"
select ARCH_MSM_KRAITMP
@@ -158,6 +188,15 @@
select MSM_GPIOMUX
select MSM_REMOTE_SPINLOCK_SFPB
+config ARCH_MSMCOPPER
+ bool "MSM Copper"
+ select ARCH_MSM_KRAITMP
+ select MSM_V2_TLMM
+ select ARM_GIC
+ select CPU_V7
+ select MSM_SCM if SMP
+ select MSM_GPIOMUX
+
config ARCH_FSM9XXX
bool "FSM9XXX"
select ARCH_MSM_SCORPION
@@ -544,6 +583,24 @@
help
Support for the Qualcomm MSM8960 LIQUID device.
+config MACH_MSM8930_CDP
+ depends on ARCH_MSM8930
+ bool "MSM8930 CDP"
+ help
+ Support for the Qualcomm MSM8930 CDP device.
+
+config MACH_MSM8930_MTP
+ depends on ARCH_MSM8930
+ bool "MSM8930 MTP"
+ help
+ Support for the Qualcomm MSM8930 MTP device.
+
+config MACH_MSM8930_FLUID
+ depends on ARCH_MSM8930
+ bool "MSM8930 FLUID"
+ help
+ Support for the Qualcomm MSM8930 FLUID device.
+
config MACH_MSM9615_CDP
depends on ARCH_MSM9615
bool "MSM9615 CDP"
@@ -601,6 +658,8 @@
default "0x40800000" if ARCH_MSM9615
default "0x80200000" if ARCH_APQ8064
default "0x80200000" if ARCH_MSM8960
+ default "0x80200000" if ARCH_MSM8930
+ default "0x80200000" if ARCH_MSMCOPPER
default "0x10000000" if ARCH_FSM9XXX
default "0x00200000" if !MSM_STACKED_MEMORY
default "0x00000000" if ARCH_QSD8X50 && MSM_SOC_REV_A
@@ -1515,6 +1574,16 @@
This bug is not applicable to any ScorpionMP or Scorpion Uni 65nm(SC65U) cores.
+config MSM_BUSPM_DEV
+ tristate "MSM Bus Performance Monitor Kernel Module"
+ depends on (ARCH_MSM8X60 || ARCH_MSM8960)
+ default m
+ help
+ This kernel module is used to mmap() hardware registers for the
+ performance monitors, counters, etc. The module can also be used to
+ allocate physical memory which is used by bus performance hardware to
+ dump performance data.
+
config MSM_RPM_LOG
tristate "MSM Resource Power Manager Log Driver"
depends on DEBUG_FS
@@ -1656,7 +1725,7 @@
config MSM_SHOW_RESUME_IRQ
bool "Enable logging of interrupts that could have caused resume"
- depends on (ARCH_MSM8X60 || ARCH_MSM8960)
+ depends on (ARCH_MSM8X60 || ARCH_MSM8960 || ARCH_MSMCOPPER)
default n
help
This option logs wake up interrupts that have triggered just before
@@ -1737,4 +1806,12 @@
Enabling this driver allows configuring L2 SPM for low power modes
on supported chipsets.
+config MSM_MULTIMEDIA_USE_ION
+ bool "Multimedia suport using Ion"
+ depends on ION_MSM
+ help
+ Enable support for multimedia drivers using Ion for buffer management
+ instead of pmem. Selecting this may also involve userspace
+ dependencies as well.
+
endif
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index b7357cd..74f312a 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -73,7 +73,7 @@
obj-$(CONFIG_MSM_BAM_DMUX) += bam_dmux.o
obj-$(CONFIG_MSM_SMD_LOGGING) += smem_log.o
obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o remote_spinlock.o
- obj-y += socinfo.o
+obj-y += socinfo.o
ifndef CONFIG_ARCH_MSM9615
ifndef CONFIG_ARCH_APQ8064
ifndef CONFIG_ARCH_MSM8960
@@ -87,10 +87,12 @@
ifndef CONFIG_ARCH_MSM8960
ifndef CONFIG_ARCH_MSM8X60
ifndef CONFIG_ARCH_APQ8064
+ifndef CONFIG_ARCH_MSMCOPPER
obj-y += nand_partitions.o
endif
endif
endif
+endif
obj-$(CONFIG_MSM_SDIO_TTY) += sdio_tty.o sdio_tty_ciq.o
obj-$(CONFIG_MSM_SMD_TTY) += smd_tty.o
obj-$(CONFIG_MSM_SMD_QMI) += smd_qmi.o
@@ -139,6 +141,7 @@
obj-$(CONFIG_ARCH_MSM7X27A) += pm2.o
obj-$(CONFIG_ARCH_MSM7X25) += pm.o
obj-$(CONFIG_ARCH_MSM7X01A) += pm.o
+ obj-y += pm-boot.o
else
obj-y += no-pm.o
endif
@@ -219,11 +222,15 @@
obj-$(CONFIG_MACH_MSM8960_CDP) += board-msm8960.o devices-8960.o board-msm8960-regulator.o
obj-$(CONFIG_MACH_MSM8960_MTP) += board-msm8960.o devices-8960.o board-msm8960-regulator.o
obj-$(CONFIG_MACH_MSM8960_FLUID) += board-msm8960.o devices-8960.o board-msm8960-regulator.o
+obj-$(CONFIG_MACH_MSM8930_CDP) += board-msm8960.o devices-8960.o board-msm8960-regulator.o
+obj-$(CONFIG_MACH_MSM8930_MTP) += board-msm8960.o devices-8960.o board-msm8960-regulator.o
+obj-$(CONFIG_MACH_MSM8930_FLUID) += board-msm8960.o devices-8960.o board-msm8960-regulator.o
obj-$(CONFIG_ARCH_MSM8960) += bms-batterydata.o
obj-$(CONFIG_ARCH_APQ8064) += board-apq8064.o devices-8064.o board-apq8064-regulator.o
obj-$(CONFIG_ARCH_MSM9615) += board-9615.o devices-9615.o board-9615-regulator.o
obj-$(CONFIG_ARCH_MSM9615) += clock-local.o clock-9615.o acpuclock-9615.o clock-rpm.o
obj-$(CONFIG_ARCH_MSM9615) += rpm-regulator.o rpm-regulator-9615.o
+obj-$(CONFIG_ARCH_MSMCOPPER) += board-copper.o board-dt.o
obj-$(CONFIG_MACH_SAPPHIRE) += board-sapphire.o board-sapphire-gpio.o
obj-$(CONFIG_MACH_SAPPHIRE) += board-sapphire-keypad.o board-sapphire-panel.o
@@ -247,6 +254,7 @@
obj-$(CONFIG_MSM_RPM_LOG) += rpm_log.o
obj-$(CONFIG_MSM_XO) += msm_xo.o
obj-$(CONFIG_MSM_BUS_SCALING) += msm_bus/
+obj-$(CONFIG_MSM_BUSPM_DEV) += msm-buspm-dev.o
obj-$(CONFIG_MSM_IOMMU) += iommu.o iommu_dev.o devices-iommu.o iommu_domains.o
@@ -261,6 +269,7 @@
obj-$(CONFIG_ARCH_MSM8960) += gpiomux-v2.o gpiomux.o
obj-$(CONFIG_ARCH_APQ8064) += gpiomux-v2.o gpiomux.o
obj-$(CONFIG_ARCH_MSM9615) += gpiomux-v2.o gpiomux.o
+obj-$(CONFIG_ARCH_MSMCOPPER) += gpiomux-v2.o gpiomux.o
ifdef CONFIG_FSM9XXX_TLMM
obj-y += gpio-fsm9xxx.o
@@ -281,6 +290,8 @@
obj-$(CONFIG_MSM_PROC_COMM_REGULATOR) += proccomm-regulator.o
ifdef CONFIG_MSM_PROC_COMM_REGULATOR
+obj-$(CONFIG_MACH_MSM7X27_SURF) += board-msm7627-regulator.o
+obj-$(CONFIG_MACH_MSM7X27_FFA) += board-msm7627-regulator.o
obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30-regulator.o
obj-$(CONFIG_ARCH_MSM7X27A) += board-msm7x27a-regulator.o
endif
diff --git a/arch/arm/mach-msm/Makefile.boot b/arch/arm/mach-msm/Makefile.boot
index 3e8ea9f..bc15a01 100644
--- a/arch/arm/mach-msm/Makefile.boot
+++ b/arch/arm/mach-msm/Makefile.boot
@@ -35,9 +35,15 @@
# MSM8960
zreladdr-$(CONFIG_ARCH_MSM8960) := 0x80208000
+# MSM8930
+ zreladdr-$(CONFIG_ARCH_MSM8930) := 0x80208000
+
# APQ8064
zreladdr-$(CONFIG_ARCH_APQ8064) := 0x80208000
+# MSMCOPPER
+ zreladdr-$(CONFIG_ARCH_MSMCOPPER) := 0x80208000
+
# MSM9615
zreladdr-$(CONFIG_ARCH_MSM9615) := 0x40808000
diff --git a/arch/arm/mach-msm/acpuclock-8960.c b/arch/arm/mach-msm/acpuclock-8960.c
index cfc7dd0..659c292 100644
--- a/arch/arm/mach-msm/acpuclock-8960.c
+++ b/arch/arm/mach-msm/acpuclock-8960.c
@@ -33,6 +33,7 @@
#include <mach/msm_bus_board.h>
#include <mach/socinfo.h>
#include <mach/msm-krait-l2-accessors.h>
+#include <mach/rpm-regulator.h>
#include "acpuclock.h"
@@ -50,6 +51,7 @@
#define PRI_SRC_SEL_HFPLL 1
#define PRI_SRC_SEL_HFPLL_DIV2 2
#define SEC_SRC_SEL_QSB 0
+#define SEC_SRC_SEL_AUX 2
/* HFPLL registers offsets. */
#define HFPLL_MODE 0x00
@@ -87,6 +89,8 @@
VREG_CORE,
VREG_MEM,
VREG_DIG,
+ VREG_HFPLL_A,
+ VREG_HFPLL_B,
NUM_VREG
};
@@ -143,6 +147,12 @@
.vreg[VREG_DIG] = { "krait0_dig", 1150000,
RPM_VREG_VOTER1,
RPM_VREG_ID_PM8921_S3 },
+ .vreg[VREG_HFPLL_A] = { "hfpll", 2200000,
+ RPM_VREG_VOTER1,
+ RPM_VREG_ID_PM8921_S8 },
+ .vreg[VREG_HFPLL_B] = { "hfpll", 1800000,
+ RPM_VREG_VOTER1,
+ RPM_VREG_ID_PM8921_L23 },
},
[CPU1] = {
.hfpll_base = MSM_HFPLL_BASE + 0x300,
@@ -155,11 +165,23 @@
.vreg[VREG_DIG] = { "krait0_dig", 1150000,
RPM_VREG_VOTER2,
RPM_VREG_ID_PM8921_S3 },
+ .vreg[VREG_HFPLL_A] = { "hfpll", 2200000,
+ RPM_VREG_VOTER2,
+ RPM_VREG_ID_PM8921_S8 },
+ .vreg[VREG_HFPLL_B] = { "hfpll", 1800000,
+ RPM_VREG_VOTER2,
+ RPM_VREG_ID_PM8921_L23 },
},
[L2] = {
.hfpll_base = MSM_HFPLL_BASE + 0x400,
.aux_clk_sel = MSM_APCS_GCC_BASE + 0x028,
.l2cpmr_iaddr = L2CPMR_IADDR,
+ .vreg[VREG_HFPLL_A] = { "hfpll", 2200000,
+ RPM_VREG_VOTER6,
+ RPM_VREG_ID_PM8921_S8 },
+ .vreg[VREG_HFPLL_B] = { "hfpll", 1800000,
+ RPM_VREG_VOTER6,
+ RPM_VREG_ID_PM8921_L23 },
},
};
@@ -410,6 +432,23 @@
/* Enable an already-configured HFPLL. */
static void hfpll_enable(struct scalable *sc)
{
+ int rc;
+
+ if (cpu_is_msm8960()) {
+ rc = rpm_vreg_set_voltage(sc->vreg[VREG_HFPLL_A].rpm_vreg_id,
+ sc->vreg[VREG_HFPLL_A].rpm_vreg_voter, 2200000,
+ 2200000, 0);
+ if (rc)
+ pr_err("%s regulator enable failed (%d)\n",
+ sc->vreg[VREG_HFPLL_A].name, rc);
+ rc = rpm_vreg_set_voltage(sc->vreg[VREG_HFPLL_B].rpm_vreg_id,
+ sc->vreg[VREG_HFPLL_B].rpm_vreg_voter, 1800000,
+ 1800000, 0);
+ if (rc)
+ pr_err("%s regulator enable failed (%d)\n",
+ sc->vreg[VREG_HFPLL_B].name, rc);
+ }
+
/* Disable PLL bypass mode. */
writel_relaxed(0x2, sc->hfpll_base + HFPLL_MODE);
@@ -434,11 +473,28 @@
/* Disable a HFPLL for power-savings or while its being reprogrammed. */
static void hfpll_disable(struct scalable *sc)
{
+ int rc;
+
/*
* Disable the PLL output, disable test mode, enable
* the bypass mode, and assert the reset.
*/
writel_relaxed(0, sc->hfpll_base + HFPLL_MODE);
+
+ if (cpu_is_msm8960()) {
+ rc = rpm_vreg_set_voltage(sc->vreg[VREG_HFPLL_B].rpm_vreg_id,
+ sc->vreg[VREG_HFPLL_B].rpm_vreg_voter, 0,
+ 0, 0);
+ if (rc)
+ pr_err("%s regulator enable failed (%d)\n",
+ sc->vreg[VREG_HFPLL_B].name, rc);
+ rc = rpm_vreg_set_voltage(sc->vreg[VREG_HFPLL_A].rpm_vreg_id,
+ sc->vreg[VREG_HFPLL_A].rpm_vreg_voter, 0,
+ 0, 0);
+ if (rc)
+ pr_err("%s regulator enable failed (%d)\n",
+ sc->vreg[VREG_HFPLL_A].name, rc);
+ }
}
/* Program the HFPLL rate. Assumes HFPLL is already disabled. */
@@ -493,12 +549,11 @@
return;
if (strt_s->src == HFPLL && tgt_s->src == HFPLL) {
- /* Move CPU to QSB source. */
/*
- * TODO: If using QSB here requires elevating voltages,
- * consider using PLL8 instead.
+ * Move to an always-on source running at a frequency that does
+ * not require an elevated CPU voltage. PLL8 is used here.
*/
- set_sec_clk_src(sc, SEC_SRC_SEL_QSB);
+ set_sec_clk_src(sc, SEC_SRC_SEL_AUX);
set_pri_clk_src(sc, PRI_SRC_SEL_SEC_SRC);
/* Program CPU HFPLL. */
@@ -509,7 +564,6 @@
/* Move CPU to HFPLL source. */
set_pri_clk_src(sc, tgt_s->pri_src_sel);
} else if (strt_s->src == HFPLL && tgt_s->src != HFPLL) {
- /* TODO: Enable source. */
/*
* If responding to CPU_DEAD we must be running on another
* CPU. Therefore, we can't access the downed CPU's CP15
@@ -533,12 +587,9 @@
*/
if (reason != SETRATE_HOTPLUG || sc == &scalable[L2])
set_pri_clk_src(sc, tgt_s->pri_src_sel);
- /* TODO: Disable source. */
} else {
- /* TODO: Enable source. */
if (reason != SETRATE_HOTPLUG || sc == &scalable[L2])
set_sec_clk_src(sc, tgt_s->sec_src_sel);
- /* TODO: Disable source. */
}
sc->current_speed = tgt_s;
@@ -549,7 +600,7 @@
unsigned int vdd_dig, enum setrate_reason reason)
{
struct scalable *sc = &scalable[cpu];
- int rc;
+ int rc = 0;
/*
* Increase vdd_mem active-set before vdd_dig.
@@ -821,24 +872,18 @@
}
}
-#define INIT_QSB_ID 0
-#define INIT_HFPLL_ID 1
/* Set initial rate for a given core. */
static void __init init_clock_sources(struct scalable *sc,
struct core_speed *tgt_s)
{
- uint32_t pri_src, regval;
+ uint32_t regval;
- /*
- * If the HFPLL is in use, program AUX source for QSB, switch to it,
- * re-initialize the HFPLL, and switch back to the HFPLL. Otherwise,
- * the HFPLL is not in use, so we can switch directly to it.
- */
- pri_src = get_pri_clk_src(scalable);
- if (pri_src == PRI_SRC_SEL_HFPLL || pri_src == PRI_SRC_SEL_HFPLL_DIV2) {
- set_sec_clk_src(sc, SEC_SRC_SEL_QSB);
- set_pri_clk_src(sc, PRI_SRC_SEL_SEC_SRC);
- }
+ /* Select PLL8 as AUX source input to the secondary MUX. */
+ writel_relaxed(0x3, sc->aux_clk_sel);
+
+ /* Switch away from the HFPLL while it's re-initialized. */
+ set_sec_clk_src(sc, SEC_SRC_SEL_AUX);
+ set_pri_clk_src(sc, PRI_SRC_SEL_SEC_SRC);
hfpll_init(sc, tgt_s);
/* Set PRI_SRC_SEL_HFPLL_DIV2 divider to div-2. */
@@ -846,9 +891,8 @@
regval &= ~(0x3 << 6);
set_l2_indirect_reg(sc->l2cpmr_iaddr, regval);
- /* Select PLL8 as AUX source input to the secondary MUX. */
- writel_relaxed(0x3, sc->aux_clk_sel);
-
+ /* Switch to the target clock source. */
+ set_sec_clk_src(sc, tgt_s->sec_src_sel);
set_pri_clk_src(sc, tgt_s->pri_src_sel);
sc->current_speed = tgt_s;
@@ -981,7 +1025,7 @@
struct acpu_level *l, *max_acpu_level = NULL;
/* Select frequency tables. */
- if (cpu_is_msm8960()) {
+ if (cpu_is_msm8960() || cpu_is_msm8930()) {
uint32_t pte_efuse, pvs;
pte_efuse = readl_relaxed(QFPROM_PTE_EFUSE_ADDR);
diff --git a/arch/arm/mach-msm/bam_dmux.c b/arch/arm/mach-msm/bam_dmux.c
index 603b031..317248e 100644
--- a/arch/arm/mach-msm/bam_dmux.c
+++ b/arch/arm/mach-msm/bam_dmux.c
@@ -29,9 +29,11 @@
#include <mach/sps.h>
#include <mach/bam_dmux.h>
#include <mach/msm_smsm.h>
+#include <mach/subsystem_notif.h>
#define BAM_CH_LOCAL_OPEN 0x1
#define BAM_CH_REMOTE_OPEN 0x2
+#define BAM_CH_IN_RESET 0x4
#define BAM_MUX_HDR_MAGIC_NO 0x33fc
@@ -103,6 +105,7 @@
char is_cmd;
uint32_t len;
struct work_struct work;
+ struct list_head list_node;
};
struct rx_pkt_info {
@@ -136,7 +139,9 @@
static int polling_mode;
static LIST_HEAD(bam_rx_pool);
-static DEFINE_MUTEX(bam_rx_pool_lock);
+static DEFINE_MUTEX(bam_rx_pool_mutexlock);
+static LIST_HEAD(bam_tx_pool);
+static DEFINE_SPINLOCK(bam_tx_pool_spinlock);
struct bam_mux_hdr {
uint16_t magic_num;
@@ -152,7 +157,6 @@
static void handle_bam_mux_cmd(struct work_struct *work);
static void rx_timer_work_func(struct work_struct *work);
-static DEFINE_MUTEX(bam_mux_lock);
static DECLARE_WORK(rx_timer_work, rx_timer_work_func);
static struct workqueue_struct *bam_mux_rx_workqueue;
@@ -178,8 +182,20 @@
static struct clk *dfab_clk;
static DEFINE_RWLOCK(ul_wakeup_lock);
static DECLARE_WORK(kickoff_ul_wakeup, kickoff_ul_wakeup_func);
+static int bam_connection_is_active;
/* End A2 power collaspe */
+/* subsystem restart */
+static int restart_notifier_cb(struct notifier_block *this,
+ unsigned long code,
+ void *data);
+
+static struct notifier_block restart_notifier = {
+ .notifier_call = restart_notifier_cb,
+};
+static int in_global_reset;
+/* end subsystem restart */
+
#define bam_ch_is_open(x) \
(bam_ch[(x)].status == (BAM_CH_LOCAL_OPEN | BAM_CH_REMOTE_OPEN))
@@ -189,11 +205,17 @@
#define bam_ch_is_remote_open(x) \
(bam_ch[(x)].status & BAM_CH_REMOTE_OPEN)
+#define bam_ch_is_in_reset(x) \
+ (bam_ch[(x)].status & BAM_CH_IN_RESET)
+
static void queue_rx(void)
{
void *ptr;
struct rx_pkt_info *info;
+ if (in_global_reset)
+ return;
+
info = kmalloc(sizeof(struct rx_pkt_info), GFP_KERNEL);
if (!info)
return; /*need better way to handle this */
@@ -203,9 +225,9 @@
info->skb = __dev_alloc_skb(BUFFER_SIZE, GFP_KERNEL);
ptr = skb_put(info->skb, BUFFER_SIZE);
- mutex_lock(&bam_rx_pool_lock);
+ mutex_lock(&bam_rx_pool_mutexlock);
list_add_tail(&info->list_node, &bam_rx_pool);
- mutex_unlock(&bam_rx_pool_lock);
+ mutex_unlock(&bam_rx_pool_mutexlock);
/* need a way to handle error case */
info->dma_address = dma_map_single(NULL, ptr, BUFFER_SIZE,
@@ -316,12 +338,10 @@
struct tx_pkt_info *pkt;
dma_addr_t dma_address;
- mutex_lock(&bam_mux_lock);
pkt = kmalloc(sizeof(struct tx_pkt_info), GFP_KERNEL);
if (pkt == NULL) {
pr_err("%s: mem alloc for tx_pkt_info failed\n", __func__);
rc = -ENOMEM;
- mutex_unlock(&bam_mux_lock);
return rc;
}
@@ -330,17 +350,19 @@
if (!dma_address) {
pr_err("%s: dma_map_single() failed\n", __func__);
rc = -ENOMEM;
- mutex_unlock(&bam_mux_lock);
return rc;
}
pkt->skb = (struct sk_buff *)(data);
pkt->len = len;
pkt->dma_address = dma_address;
pkt->is_cmd = 1;
+ INIT_WORK(&pkt->work, bam_mux_write_done);
+ spin_lock(&bam_tx_pool_spinlock);
+ list_add_tail(&pkt->list_node, &bam_tx_pool);
+ spin_unlock(&bam_tx_pool_spinlock);
rc = sps_transfer_one(bam_tx_pipe, dma_address, len,
pkt, SPS_IOVEC_FLAG_INT | SPS_IOVEC_FLAG_EOT);
- mutex_unlock(&bam_mux_lock);
ul_packet_written = 1;
return rc;
}
@@ -351,8 +373,20 @@
struct bam_mux_hdr *hdr;
struct tx_pkt_info *info;
unsigned long event_data;
+ struct list_head *node;
+ if (in_global_reset)
+ return;
+ spin_lock(&bam_tx_pool_spinlock);
+ node = bam_tx_pool.next;
+ list_del(node);
+ spin_unlock(&bam_tx_pool_spinlock);
info = container_of(work, struct tx_pkt_info, work);
+ if (info->is_cmd) {
+ kfree(info->skb);
+ kfree(info);
+ return;
+ }
skb = info->skb;
kfree(info);
hdr = (struct bam_mux_hdr *)skb->data;
@@ -407,7 +441,7 @@
4 - (skb->len & 0x3), GFP_ATOMIC);
if (new_skb == NULL) {
pr_err("%s: cannot allocate skb\n", __func__);
- return -ENOMEM;
+ goto write_fail;
}
dev_kfree_skb_any(skb);
skb = new_skb;
@@ -435,29 +469,36 @@
pkt = kmalloc(sizeof(struct tx_pkt_info), GFP_ATOMIC);
if (pkt == NULL) {
pr_err("%s: mem alloc for tx_pkt_info failed\n", __func__);
- if (new_skb)
- dev_kfree_skb_any(new_skb);
- return -ENOMEM;
+ goto write_fail2;
}
dma_address = dma_map_single(NULL, skb->data, skb->len,
DMA_TO_DEVICE);
if (!dma_address) {
pr_err("%s: dma_map_single() failed\n", __func__);
- if (new_skb)
- dev_kfree_skb_any(new_skb);
- kfree(pkt);
- return -ENOMEM;
+ goto write_fail3;
}
pkt->skb = skb;
pkt->dma_address = dma_address;
pkt->is_cmd = 0;
INIT_WORK(&pkt->work, bam_mux_write_done);
+ spin_lock(&bam_tx_pool_spinlock);
+ list_add_tail(&pkt->list_node, &bam_tx_pool);
+ spin_unlock(&bam_tx_pool_spinlock);
rc = sps_transfer_one(bam_tx_pipe, dma_address, skb->len,
pkt, SPS_IOVEC_FLAG_INT | SPS_IOVEC_FLAG_EOT);
ul_packet_written = 1;
read_unlock(&ul_wakeup_lock);
return rc;
+
+write_fail3:
+ kfree(pkt);
+write_fail2:
+ if (new_skb)
+ dev_kfree_skb_any(new_skb);
+write_fail:
+ read_unlock(&ul_wakeup_lock);
+ return -ENOMEM;
}
int msm_bam_dmux_open(uint32_t id, void *priv,
@@ -536,7 +577,7 @@
return -ENODEV;
read_lock(&ul_wakeup_lock);
- if (!bam_is_connected) {
+ if (!bam_is_connected && !bam_ch_is_in_reset(id)) {
read_unlock(&ul_wakeup_lock);
ul_wakeup();
read_lock(&ul_wakeup_lock);
@@ -549,9 +590,16 @@
bam_ch[id].status &= ~BAM_CH_LOCAL_OPEN;
spin_unlock_irqrestore(&bam_ch[id].lock, flags);
- hdr = kmalloc(sizeof(struct bam_mux_hdr), GFP_KERNEL);
+ if (bam_ch_is_in_reset(id)) {
+ read_unlock(&ul_wakeup_lock);
+ bam_ch[id].status &= ~BAM_CH_IN_RESET;
+ return 0;
+ }
+
+ hdr = kmalloc(sizeof(struct bam_mux_hdr), GFP_ATOMIC);
if (hdr == NULL) {
pr_err("%s: hdr kmalloc failed. ch: %d\n", __func__, id);
+ read_unlock(&ul_wakeup_lock);
return -ENOMEM;
}
hdr->magic_num = BAM_MUX_HDR_MAGIC_NO;
@@ -580,14 +628,16 @@
while (1) { /* timer loop */
++inactive_cycles;
while (1) { /* deplete queue loop */
+ if (in_global_reset)
+ return;
sps_get_iovec(bam_rx_pipe, &iov);
if (iov.addr == 0)
break;
inactive_cycles = 0;
- mutex_lock(&bam_rx_pool_lock);
+ mutex_lock(&bam_rx_pool_mutexlock);
node = bam_rx_pool.next;
list_del(node);
- mutex_unlock(&bam_rx_pool_lock);
+ mutex_unlock(&bam_rx_pool_mutexlock);
info = container_of(node, struct rx_pkt_info,
list_node);
handle_bam_mux_cmd(&info->work);
@@ -623,15 +673,17 @@
}
polling_mode = 0;
}
+ if (in_global_reset)
+ return;
/* handle race condition - missed packet? */
sps_get_iovec(bam_rx_pipe, &iov);
if (iov.addr == 0)
return;
inactive_cycles = 0;
- mutex_lock(&bam_rx_pool_lock);
+ mutex_lock(&bam_rx_pool_mutexlock);
node = bam_rx_pool.next;
list_del(node);
- mutex_unlock(&bam_rx_pool_lock);
+ mutex_unlock(&bam_rx_pool_mutexlock);
info = container_of(node, struct rx_pkt_info,
list_node);
handle_bam_mux_cmd(&info->work);
@@ -648,21 +700,21 @@
DBG("%s: event %d notified\n", __func__, notify->event_id);
+ if (in_global_reset)
+ return;
+
switch (notify->event_id) {
case SPS_EVENT_EOT:
pkt = notify->data.transfer.user;
- if (!pkt->is_cmd) {
+ if (!pkt->is_cmd)
dma_unmap_single(NULL, pkt->dma_address,
pkt->skb->len,
DMA_TO_DEVICE);
- queue_work(bam_mux_tx_workqueue, &pkt->work);
- } else {
+ else
dma_unmap_single(NULL, pkt->dma_address,
pkt->len,
DMA_TO_DEVICE);
- kfree(pkt->skb);
- kfree(pkt);
- }
+ queue_work(bam_mux_tx_workqueue, &pkt->work);
break;
default:
pr_err("%s: recieved unexpected event id %d\n", __func__,
@@ -677,6 +729,9 @@
DBG("%s: event %d notified\n", __func__, notify->event_id);
+ if (in_global_reset)
+ return;
+
switch (notify->event_id) {
case SPS_EVENT_EOT:
/* attempt to disable interrupts in this pipe */
@@ -792,6 +847,8 @@
static void ul_timeout(struct work_struct *work)
{
+ if (in_global_reset)
+ return;
write_lock(&ul_wakeup_lock);
if (ul_packet_written) {
ul_packet_written = 0;
@@ -828,6 +885,7 @@
{
int i;
+ in_global_reset = 0;
vote_dfab();
i = sps_device_reset(a2_device_handle);
if (i)
@@ -847,6 +905,7 @@
for (i = 0; i < NUM_BUFFERS; ++i)
queue_rx();
toggle_apps_ack();
+ bam_connection_is_active = 1;
complete_all(&bam_connection_completion);
}
@@ -855,6 +914,7 @@
struct list_head *node;
struct rx_pkt_info *info;
+ bam_connection_is_active = 0;
INIT_COMPLETION(bam_connection_completion);
sps_disconnect(bam_tx_pipe);
sps_disconnect(bam_rx_pipe);
@@ -886,6 +946,56 @@
clk_disable(dfab_clk);
}
+static int restart_notifier_cb(struct notifier_block *this,
+ unsigned long code,
+ void *data)
+{
+ int i;
+ struct list_head *node;
+ struct tx_pkt_info *info;
+ int temp_remote_status;
+
+ if (code != SUBSYS_AFTER_SHUTDOWN)
+ return NOTIFY_DONE;
+
+ in_global_reset = 1;
+ for (i = 0; i < BAM_DMUX_NUM_CHANNELS; ++i) {
+ temp_remote_status = bam_ch_is_remote_open(i);
+ bam_ch[i].status &= ~BAM_CH_REMOTE_OPEN;
+ if (bam_ch_is_local_open(i))
+ bam_ch[i].status |= BAM_CH_IN_RESET;
+ if (temp_remote_status) {
+ platform_device_unregister(bam_ch[i].pdev);
+ bam_ch[i].pdev = platform_device_alloc(
+ bam_ch[i].name, 2);
+ }
+ }
+ /*cleanup UL*/
+ spin_lock(&bam_tx_pool_spinlock);
+ while (!list_empty(&bam_tx_pool)) {
+ node = bam_tx_pool.next;
+ list_del(node);
+ info = container_of(node, struct tx_pkt_info,
+ list_node);
+ if (!info->is_cmd) {
+ dma_unmap_single(NULL, info->dma_address,
+ info->skb->len,
+ DMA_TO_DEVICE);
+ dev_kfree_skb_any(info->skb);
+ } else {
+ dma_unmap_single(NULL, info->dma_address,
+ info->len,
+ DMA_TO_DEVICE);
+ kfree(info->skb);
+ }
+ kfree(info);
+ }
+ spin_unlock(&bam_tx_pool_spinlock);
+ smsm_change_state(SMSM_APPS_STATE, SMSM_A2_POWER_CONTROL, 0);
+
+ return NOTIFY_DONE;
+}
+
static void bam_init(void)
{
u32 h;
@@ -1017,6 +1127,7 @@
for (i = 0; i < NUM_BUFFERS; ++i)
queue_rx();
toggle_apps_ack();
+ bam_connection_is_active = 1;
complete_all(&bam_connection_completion);
return;
@@ -1079,7 +1190,7 @@
if (bam_mux_initialized)
return 0;
- dfab_clk = clk_get(&pdev->dev, "dfab_clk");
+ dfab_clk = clk_get(&pdev->dev, "bus_clk");
if (IS_ERR(dfab_clk)) {
pr_err("%s: did not get dfab clock\n", __func__);
return -EFAULT;
@@ -1163,6 +1274,7 @@
if (!IS_ERR(dent))
debug_create("tbl", 0444, dent, debug_tbl);
#endif
+ subsys_notif_register_notifier("modem", &restart_notifier);
return platform_driver_register(&bam_dmux_driver);
}
diff --git a/arch/arm/mach-msm/board-9615-regulator.c b/arch/arm/mach-msm/board-9615-regulator.c
index 855d956..c4b7c5a 100644
--- a/arch/arm/mach-msm/board-9615-regulator.c
+++ b/arch/arm/mach-msm/board-9615-regulator.c
@@ -12,6 +12,7 @@
*/
#include <linux/regulator/pm8018-regulator.h>
+#include <linux/regulator/gpio-regulator.h>
#include <mach/rpm-regulator.h>
#include "board-9615.h"
@@ -60,6 +61,7 @@
};
VREG_CONSUMERS(L13) = {
REGULATOR_SUPPLY("8018_l13", NULL),
+ REGULATOR_SUPPLY("sdc_vddp", "msm_sdcc.1"),
};
VREG_CONSUMERS(L14) = {
REGULATOR_SUPPLY("8018_l14", NULL),
@@ -83,6 +85,10 @@
VREG_CONSUMERS(LVS1) = {
REGULATOR_SUPPLY("8018_lvs1", NULL),
};
+VREG_CONSUMERS(EXT_2P95V) = {
+ REGULATOR_SUPPLY("ext_2p95v", NULL),
+ REGULATOR_SUPPLY("sdc_vdd", "msm_sdcc.1"),
+};
#define PM8018_VREG_INIT(_id, _min_uV, _max_uV, _modes, _ops, _apply_uV, \
_pull_down, _always_on, _supply_regulator, \
@@ -238,6 +244,25 @@
.pin_ctrl = _pin_ctrl, \
}
+#define GPIO_VREG_INIT(_id, _reg_name, _gpio_label, _gpio) \
+ [GPIO_VREG_ID_##_id] = { \
+ .init_data = { \
+ .constraints = { \
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS, \
+ }, \
+ .num_consumer_supplies = \
+ ARRAY_SIZE(vreg_consumers_##_id), \
+ .consumer_supplies = vreg_consumers_##_id, \
+ }, \
+ .regulator_name = _reg_name, \
+ .gpio_label = _gpio_label, \
+ .gpio = _gpio, \
+ }
+
+/* GPIO regulator constraints */
+struct gpio_regulator_platform_data msm_gpio_regulator_pdata[] = {
+ GPIO_VREG_INIT(EXT_2P95V, "ext_2p95v", "ext_2p95_en", 18),
+};
/* PM8018 regulator constraints */
struct pm8018_regulator_platform_data
@@ -265,7 +290,7 @@
RPM_LDO(L10, 0, 1, 0, 1050000, 1050000, "8018_s5", 0, 0),
RPM_LDO(L11, 0, 1, 0, 1050000, 1050000, "8018_s5", 0, 0),
RPM_LDO(L12, 0, 1, 0, 1050000, 1050000, "8018_s5", 0, 0),
- RPM_LDO(L13, 0, 1, 0, 2950000, 2950000, NULL, 0, 0),
+ RPM_LDO(L13, 0, 1, 0, 1850000, 2950000, NULL, 0, 0),
RPM_LDO(L14, 0, 1, 0, 2850000, 2850000, NULL, 0, 0),
/* ID a_on pd ss supply */
diff --git a/arch/arm/mach-msm/board-9615.c b/arch/arm/mach-msm/board-9615.c
index 5f0480b..312ea46 100644
--- a/arch/arm/mach-msm/board-9615.c
+++ b/arch/arm/mach-msm/board-9615.c
@@ -25,6 +25,8 @@
#include <linux/usb/android.h>
#include <linux/usb/msm_hsusb.h>
#include <linux/mfd/pm8xxx/pm8xxx-adc.h>
+#include <linux/leds.h>
+#include <linux/leds-pm8xxx.h>
#include "timer.h"
#include "devices.h"
#include "board-9615.h"
@@ -94,6 +96,42 @@
.priority = 0,
};
+#define PM8018_LED_KB_MAX_CURRENT 20 /* I = 20mA */
+#define PM8XXX_LED_PWM_PERIOD_US 1000
+
+/**
+ * PM8XXX_PWM_CHANNEL_NONE shall be used when LED shall not be
+ * driven using PWM feature.
+ */
+#define PM8XXX_PWM_CHANNEL_NONE -1
+
+static struct led_info pm8018_led_info[] = {
+ [0] = {
+ .name = "led:kb",
+ },
+};
+
+static struct led_platform_data pm8018_led_core_pdata = {
+ .num_leds = ARRAY_SIZE(pm8018_led_info),
+ .leds = pm8018_led_info,
+};
+
+static struct pm8xxx_led_config pm8018_led_configs[] = {
+ [0] = {
+ .id = PM8XXX_ID_LED_KB_LIGHT,
+ .mode = PM8XXX_LED_MODE_PWM3,
+ .max_current = PM8018_LED_KB_MAX_CURRENT,
+ .pwm_channel = 2,
+ .pwm_period_us = PM8XXX_LED_PWM_PERIOD_US,
+ },
+};
+
+static struct pm8xxx_led_platform_data pm8xxx_leds_pdata = {
+ .led_core = &pm8018_led_core_pdata,
+ .configs = pm8018_led_configs,
+ .num_configs = ARRAY_SIZE(pm8018_led_configs),
+};
+
static struct pm8018_platform_data pm8018_platform_data __devinitdata = {
.irq_pdata = &pm8xxx_irq_pdata,
.gpio_pdata = &pm8xxx_gpio_pdata,
@@ -103,6 +141,7 @@
.misc_pdata = &pm8xxx_misc_pdata,
.regulator_pdatas = msm_pm8018_regulator_pdata,
.adc_pdata = &pm8018_adc_pdata,
+ .leds_pdata = &pm8xxx_leds_pdata,
};
static struct msm_ssbi_platform_data msm9615_ssbi_pm8018_pdata __devinitdata = {
@@ -121,6 +160,15 @@
},
};
+static struct platform_device msm9615_device_ext_2p95v_vreg = {
+ .name = GPIO_REGULATOR_DEV_NAME,
+ .id = 18,
+ .dev = {
+ .platform_data =
+ &msm_gpio_regulator_pdata[GPIO_VREG_ID_EXT_2P95V],
+ },
+};
+
static struct gpiomux_setting ps_hold = {
.func = GPIOMUX_FUNC_1,
.drv = GPIOMUX_DRV_8MA,
@@ -233,11 +281,10 @@
#if (defined(CONFIG_MMC_MSM_SDC1_SUPPORT)\
|| defined(CONFIG_MMC_MSM_SDC2_SUPPORT))
-#define GPIO_SDCARD_PWR_EN 18
#define GPIO_SDC1_HW_DET 80
#define GPIO_SDC2_DAT1_WAKEUP 26
-/* MDM9x15 have 2 SDCC controllers */
+/* MDM9x15 has 2 SDCC controllers */
enum sdcc_controllers {
SDCC1,
SDCC2,
@@ -245,6 +292,51 @@
};
#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
+/* All SDCC controllers requires VDD/VCC voltage */
+static struct msm_mmc_reg_data mmc_vdd_reg_data[MAX_SDCC_CONTROLLER] = {
+ /* SDCC1 : External card slot connected */
+ [SDCC1] = {
+ .name = "sdc_vdd",
+ /*
+ * This is a gpio-regulator and does not support
+ * regulator_set_voltage and regulator_set_optimum_mode
+ */
+ .set_voltage_sup = false,
+ .high_vol_level = 2950000,
+ .low_vol_level = 2950000,
+ .hpm_uA = 600000, /* 600mA */
+ }
+};
+
+/* All SDCC controllers may require voting for VDD PAD voltage */
+static struct msm_mmc_reg_data mmc_vddp_reg_data[MAX_SDCC_CONTROLLER] = {
+ /* SDCC1 : External card slot connected */
+ [SDCC1] = {
+ .name = "sdc_vddp",
+ .set_voltage_sup = true,
+ .high_vol_level = 2950000,
+ .low_vol_level = 1850000,
+ .always_on = true,
+ .lpm_sup = true,
+ /* Max. Active current required is 16 mA */
+ .hpm_uA = 16000,
+ /*
+ * Sleep current required is ~300 uA. But min. vote can be
+ * in terms of mA (min. 1 mA). So let's vote for 2 mA
+ * during sleep.
+ */
+ .lpm_uA = 2000,
+ }
+};
+
+static struct msm_mmc_slot_reg_data mmc_slot_vreg_data[MAX_SDCC_CONTROLLER] = {
+ /* SDCC1 : External card slot connected */
+ [SDCC1] = {
+ .vdd_data = &mmc_vdd_reg_data[SDCC1],
+ .vddp_data = &mmc_vddp_reg_data[SDCC1],
+ }
+};
+
/* SDC1 pad data */
static struct msm_mmc_pad_drv sdc1_pad_drv_on_cfg[] = {
{TLMM_HDRV_SDC1_CLK, GPIO_CFG_16MA},
@@ -408,8 +500,9 @@
.mmc_bus_width = MMC_CAP_4_BIT_DATA,
.sup_clk_table = sdc1_sup_clk_rates,
.sup_clk_cnt = ARRAY_SIZE(sdc1_sup_clk_rates),
- .pclk_src_dfab = 1,
+ .pclk_src_dfab = true,
.sdcc_v4_sup = true,
+ .vreg_data = &mmc_slot_vreg_data[SDCC1],
.pin_data = &mmc_slot_pin_data[SDCC1],
#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
.status_gpio = GPIO_SDC1_HW_DET,
@@ -446,32 +539,16 @@
static void __init msm9615_init_mmc(void)
{
- int ret;
-
if (msm9615_sdc1_pdata) {
- ret = gpio_request(GPIO_SDCARD_PWR_EN, "SDCARD_PWR_EN");
-
- if (ret) {
- pr_err("%s: sdcc1: Error requesting GPIO "
- "SDCARD_PWR_EN:%d\n", __func__, ret);
- } else {
- ret = gpio_direction_output(GPIO_SDCARD_PWR_EN, 1);
- if (ret) {
- pr_err("%s: sdcc1: Error setting o/p direction"
- " for GPIO SDCARD_PWR_EN:%d\n",
- __func__, ret);
- gpio_free(GPIO_SDCARD_PWR_EN);
- } else {
- msm_add_sdcc(1, msm9615_sdc1_pdata);
- }
- }
+ /* SDC1: External card slot for SD/MMC cards */
+ msm_add_sdcc(1, msm9615_sdc1_pdata);
}
if (msm9615_sdc2_pdata) {
msm_gpiomux_install(msm9615_sdcc2_configs,
ARRAY_SIZE(msm9615_sdcc2_configs));
- /* SDC2: External card slot */
+ /* SDC2: External card slot used for WLAN */
msm_add_sdcc(2, msm9615_sdc2_pdata);
}
}
@@ -566,6 +643,7 @@
&msm_device_gadget_peripheral,
&android_usb_device,
&msm9615_device_uart_gsbi4,
+ &msm9615_device_ext_2p95v_vreg,
&msm9615_device_ssbi_pmic1,
&msm9615_device_qup_i2c_gsbi5,
&msm9615_device_qup_spi_gsbi3,
diff --git a/arch/arm/mach-msm/board-9615.h b/arch/arm/mach-msm/board-9615.h
index 0d9fae7..0f5adf0 100644
--- a/arch/arm/mach-msm/board-9615.h
+++ b/arch/arm/mach-msm/board-9615.h
@@ -15,6 +15,7 @@
#include <mach/irqs.h>
#include <linux/mfd/pm8xxx/pm8018.h>
+#include <linux/regulator/gpio-regulator.h>
/* Macros assume PMIC GPIOs and MPPs start at 1 */
#define PM8018_GPIO_BASE NR_GPIO_IRQS
@@ -32,4 +33,8 @@
extern struct rpm_regulator_platform_data
msm_rpm_regulator_9615_pdata __devinitdata;
+#define GPIO_VREG_ID_EXT_2P95V 0
+
+extern struct gpio_regulator_platform_data msm_gpio_regulator_pdata[];
+
#endif
diff --git a/arch/arm/mach-msm/board-apq8064.c b/arch/arm/mach-msm/board-apq8064.c
index 4328b85..4aa6abe 100644
--- a/arch/arm/mach-msm/board-apq8064.c
+++ b/arch/arm/mach-msm/board-apq8064.c
@@ -33,9 +33,174 @@
#include "devices.h"
#include <mach/gpio.h>
#include <mach/gpiomux.h>
+#include <linux/android_pmem.h>
+#include <mach/msm_memtypes.h>
+#include <linux/bootmem.h>
+#include <asm/setup.h>
#include "board-apq8064.h"
+#define MSM_PMEM_KERNEL_EBI1_SIZE 0x600000
+#define MSM_PMEM_ADSP_SIZE 0x3800000
+#define MSM_PMEM_AUDIO_SIZE 0x28B000
+#define MSM_PMEM_SIZE 0x1800000 /* 24 Mbytes */
+
+static struct memtype_reserve apq8064_reserve_table[] __initdata = {
+ [MEMTYPE_SMI] = {
+ },
+ [MEMTYPE_EBI0] = {
+ .flags = MEMTYPE_FLAGS_1M_ALIGN,
+ },
+ [MEMTYPE_EBI1] = {
+ .flags = MEMTYPE_FLAGS_1M_ALIGN,
+ },
+};
+
+static int apq8064_paddr_to_memtype(unsigned int paddr)
+{
+ return MEMTYPE_EBI1;
+}
+
+static unsigned pmem_size = MSM_PMEM_SIZE;
+static int __init pmem_size_setup(char *p)
+{
+ pmem_size = memparse(p, NULL);
+ return 0;
+}
+early_param("pmem_size", pmem_size_setup);
+
+static unsigned pmem_adsp_size = MSM_PMEM_ADSP_SIZE;
+
+static int __init pmem_adsp_size_setup(char *p)
+{
+ pmem_adsp_size = memparse(p, NULL);
+ return 0;
+}
+early_param("pmem_adsp_size", pmem_adsp_size_setup);
+
+static unsigned pmem_audio_size = MSM_PMEM_AUDIO_SIZE;
+
+static int __init pmem_audio_size_setup(char *p)
+{
+ pmem_audio_size = memparse(p, NULL);
+ return 0;
+}
+early_param("pmem_audio_size", pmem_audio_size_setup);
+
+static struct android_pmem_platform_data android_pmem_pdata = {
+ .name = "pmem",
+ .allocator_type = PMEM_ALLOCATORTYPE_ALLORNOTHING,
+ .cached = 1,
+ .memory_type = MEMTYPE_EBI1,
+};
+
+static struct platform_device android_pmem_device = {
+ .name = "android_pmem",
+ .id = 0,
+ .dev = {.platform_data = &android_pmem_pdata},
+};
+
+static struct android_pmem_platform_data android_pmem_adsp_pdata = {
+ .name = "pmem_adsp",
+ .allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
+ .cached = 0,
+ .memory_type = MEMTYPE_EBI1,
+};
+
+static unsigned pmem_kernel_ebi1_size = MSM_PMEM_KERNEL_EBI1_SIZE;
+static int __init pmem_kernel_ebi1_size_setup(char *p)
+{
+ pmem_kernel_ebi1_size = memparse(p, NULL);
+ return 0;
+}
+early_param("pmem_kernel_ebi1_size", pmem_kernel_ebi1_size_setup);
+
+static struct platform_device android_pmem_adsp_device = {
+ .name = "android_pmem",
+ .id = 2,
+ .dev = { .platform_data = &android_pmem_adsp_pdata },
+};
+
+static struct android_pmem_platform_data android_pmem_audio_pdata = {
+ .name = "pmem_audio",
+ .allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
+ .cached = 0,
+ .memory_type = MEMTYPE_EBI1,
+};
+
+static struct platform_device android_pmem_audio_device = {
+ .name = "android_pmem",
+ .id = 4,
+ .dev = { .platform_data = &android_pmem_audio_pdata },
+};
+
+static void __init size_pmem_devices(void)
+{
+ android_pmem_adsp_pdata.size = pmem_adsp_size;
+ android_pmem_pdata.size = pmem_size;
+ android_pmem_audio_pdata.size = MSM_PMEM_AUDIO_SIZE;
+}
+
+static void __init reserve_memory_for(struct android_pmem_platform_data *p)
+{
+ apq8064_reserve_table[p->memory_type].size += p->size;
+}
+
+
+static void __init reserve_pmem_memory(void)
+{
+ reserve_memory_for(&android_pmem_adsp_pdata);
+ reserve_memory_for(&android_pmem_pdata);
+ reserve_memory_for(&android_pmem_audio_pdata);
+ apq8064_reserve_table[MEMTYPE_EBI1].size += pmem_kernel_ebi1_size;
+}
+
+static void __init apq8064_calculate_reserve_sizes(void)
+{
+ size_pmem_devices();
+ reserve_pmem_memory();
+}
+
+static struct reserve_info apq8064_reserve_info __initdata = {
+ .memtype_reserve_table = apq8064_reserve_table,
+ .calculate_reserve_sizes = apq8064_calculate_reserve_sizes,
+ .paddr_to_memtype = apq8064_paddr_to_memtype,
+};
+
+static int apq8064_memory_bank_size(void)
+{
+ return 1<<29;
+}
+
+static void __init locate_unstable_memory(void)
+{
+ struct membank *mb = &meminfo.bank[meminfo.nr_banks - 1];
+ unsigned long bank_size;
+ unsigned long low, high;
+
+ bank_size = apq8064_memory_bank_size();
+ low = meminfo.bank[0].start;
+ high = mb->start + mb->size;
+ low &= ~(bank_size - 1);
+
+ if (high - low <= bank_size)
+ return;
+ apq8064_reserve_info.low_unstable_address = low + bank_size;
+ apq8064_reserve_info.max_unstable_size = high - low - bank_size;
+ apq8064_reserve_info.bank_size = bank_size;
+ pr_info("low unstable address %lx max size %lx bank size %lx\n",
+ apq8064_reserve_info.low_unstable_address,
+ apq8064_reserve_info.max_unstable_size,
+ apq8064_reserve_info.bank_size);
+}
+
+static void __init apq8064_reserve(void)
+{
+ reserve_info = &apq8064_reserve_info;
+ locate_unstable_memory();
+ msm_reserve();
+}
+
static struct platform_device android_usb_device = {
.name = "android_usb",
.id = -1,
@@ -48,7 +213,7 @@
.pclk_src_name = "dfab_usb_hs_clk",
};
-/* APQ8064 have 4 SDCC controllers */
+/* APQ8064 has 4 SDCC controllers */
enum sdcc_controllers {
SDCC1,
SDCC2,
@@ -57,7 +222,7 @@
MAX_SDCC_CONTROLLER
};
-/* All SDCC controllers requires VDD/VCC voltage */
+/* All SDCC controllers require VDD/VCC voltage */
static struct msm_mmc_reg_data mmc_vdd_reg_data[MAX_SDCC_CONTROLLER] = {
/* SDCC1 : eMMC card connected */
[SDCC1] = {
@@ -325,6 +490,9 @@
&apq8064_device_otg,
&apq8064_device_gadget_peripheral,
&android_usb_device,
+ &android_pmem_device,
+ &android_pmem_adsp_device,
+ &android_pmem_audio_device,
};
static struct platform_device *sim_devices[] __initdata = {
@@ -581,6 +749,7 @@
MACHINE_START(APQ8064_SIM, "QCT APQ8064 SIMULATOR")
.map_io = apq8064_map_io,
+ .reserve = apq8064_reserve,
.init_irq = apq8064_init_irq,
.timer = &msm_timer,
.init_machine = apq8064_sim_init,
@@ -588,6 +757,7 @@
MACHINE_START(APQ8064_RUMI3, "QCT APQ8064 RUMI3")
.map_io = apq8064_map_io,
+ .reserve = apq8064_reserve,
.init_irq = apq8064_init_irq,
.timer = &msm_timer,
.init_machine = apq8064_rumi3_init,
diff --git a/arch/arm/mach-msm/board-copper.c b/arch/arm/mach-msm/board-copper.c
new file mode 100644
index 0000000..f35d493
--- /dev/null
+++ b/arch/arm/mach-msm/board-copper.c
@@ -0,0 +1,99 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <asm/mach/map.h>
+#include <asm/hardware/gic.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/gpiomux.h>
+#include <mach/msm_iomap.h>
+#include "clock.h"
+
+static int __init gpiomux_init(void)
+{
+ int rc;
+
+ rc = msm_gpiomux_init(NR_GPIO_IRQS);
+ if (rc) {
+ pr_err("%s: msm_gpiomux_init failed %d\n", __func__, rc);
+ return rc;
+ }
+
+ return 0;
+}
+
+void __init msm_copper_add_devices(void)
+{
+}
+
+static struct of_device_id msm_copper_gic_match[] __initdata = {
+ { .compatible = "qcom,msm-qgic2", },
+ {}
+};
+
+void __init msm_copper_init_irq(void)
+{
+ unsigned int i;
+
+ gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
+ (void *)MSM_QGIC_CPU_BASE);
+
+ /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
+ writel_relaxed(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
+
+ writel_relaxed(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
+ mb();
+
+ /* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet
+ * as they are configured as level, which does not play nice with
+ * handle_percpu_irq.
+ */
+ for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
+ if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
+ irq_set_handler(i, handle_percpu_irq);
+ }
+ irq_domain_generate_simple(msm_copper_gic_match,
+ COPPER_QGIC_DIST_PHYS, GIC_SPI_START);
+}
+
+static struct clk_lookup msm_clocks_dummy[] = {
+ CLK_DUMMY("core_clk", BLSP2_UART_CLK, "msm_serial_hsl.0", OFF),
+ CLK_DUMMY("iface_clk", BLSP2_UART_CLK, "msm_serial_hsl.0", OFF),
+};
+
+struct clock_init_data msm_dummy_clock_init_data __initdata = {
+ .table = msm_clocks_dummy,
+ .size = ARRAY_SIZE(msm_clocks_dummy),
+};
+
+static struct of_dev_auxdata msm_copper_auxdata_lookup[] __initdata = {
+ OF_DEV_AUXDATA("qcom,msm-lsuart-v14", 0xF9684000, \
+ "msm_serial_hsl.0", NULL),
+ {}
+};
+
+void __init msm_copper_init(struct of_dev_auxdata **adata)
+{
+ if (gpiomux_init())
+ pr_err("%s: gpiomux_init() failed\n", __func__);
+ msm_clock_init(&msm_dummy_clock_init_data);
+
+ *adata = msm_copper_auxdata_lookup;
+}
diff --git a/arch/arm/mach-msm/board-dt.c b/arch/arm/mach-msm/board-dt.c
new file mode 100644
index 0000000..1ede17b
--- /dev/null
+++ b/arch/arm/mach-msm/board-dt.c
@@ -0,0 +1,66 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/of_fdt.h>
+#include <asm/mach/arch.h>
+#include <mach/socinfo.h>
+#include <mach/board.h>
+#include "timer.h"
+
+#define early_machine_is_copper() \
+ of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,msmcopper")
+#define machine_is_copper() \
+ of_machine_is_compatible("qcom,msmcopper")
+
+static void __init msm_dt_init_irq(void)
+{
+ if (machine_is_copper())
+ msm_copper_init_irq();
+}
+
+static void __init msm_dt_map_io(void)
+{
+ if (early_machine_is_copper())
+ msm_map_copper_io();
+ if (socinfo_init() < 0)
+ pr_err("%s: socinfo_init() failed\n", __func__);
+}
+
+static void __init msm_dt_init(void)
+{
+ struct of_dev_auxdata *adata = NULL;
+
+ if (machine_is_copper())
+ msm_copper_init(&adata);
+
+ of_platform_populate(NULL, of_default_bus_match_table, adata, NULL);
+ if (machine_is_copper())
+ msm_copper_add_devices();
+}
+
+static const char *msm_dt_match[] __initdata = {
+ "qcom,msmcopper",
+ NULL
+};
+
+DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)")
+ .map_io = msm_dt_map_io,
+ .init_irq = msm_dt_init_irq,
+ .init_machine = msm_dt_init,
+ .timer = &msm_timer,
+ .dt_compat = msm_dt_match,
+MACHINE_END
diff --git a/arch/arm/mach-msm/board-msm7627-regulator.c b/arch/arm/mach-msm/board-msm7627-regulator.c
new file mode 100644
index 0000000..2ecda72c
--- /dev/null
+++ b/arch/arm/mach-msm/board-msm7627-regulator.c
@@ -0,0 +1,221 @@
+/*
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "board-msm7627-regulator.h"
+
+#define PCOM_VREG_CONSUMERS(name) \
+ static struct regulator_consumer_supply __pcom_vreg_supply_##name[]
+
+#define PCOM_VREG_CONSTRAINT_LVSW(_name, _always_on, _boot_on, _supply_uV) \
+{ \
+ .name = #_name, \
+ .min_uV = 0, \
+ .max_uV = 0, \
+ .input_uV = _supply_uV, \
+ .valid_modes_mask = REGULATOR_MODE_NORMAL, \
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS, \
+ .apply_uV = 0, \
+ .boot_on = _boot_on, \
+ .always_on = _always_on \
+}
+
+#define PCOM_VREG_CONSTRAINT_DYN(_name, _min_uV, _max_uV, _always_on, \
+ _boot_on, _apply_uV, _supply_uV) \
+{ \
+ .name = #_name, \
+ .min_uV = _min_uV, \
+ .max_uV = _max_uV, \
+ .valid_modes_mask = REGULATOR_MODE_NORMAL, \
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, \
+ .input_uV = _supply_uV, \
+ .apply_uV = _apply_uV, \
+ .boot_on = _boot_on, \
+ .always_on = _always_on \
+}
+
+
+#define PCOM_VREG_INIT(_name, _supply, _constraints)\
+{ \
+ .supply_regulator = _supply, \
+ .consumer_supplies = __pcom_vreg_supply_##_name, \
+ .num_consumer_supplies = ARRAY_SIZE(__pcom_vreg_supply_##_name), \
+ .constraints = _constraints \
+}
+
+#define PCOM_VREG_SMP(_name, _id, _supply, _min_uV, _max_uV, _rise_time, \
+ _pulldown, _always_on, _boot_on, _apply_uV, _supply_uV) \
+{ \
+ .init_data = PCOM_VREG_INIT(_name, _supply, \
+ PCOM_VREG_CONSTRAINT_DYN(_name, _min_uV, _max_uV, _always_on, \
+ _boot_on, _apply_uV, _supply_uV)), \
+ .id = _id, \
+ .rise_time = _rise_time, \
+ .pulldown = _pulldown, \
+ .negative = 0, \
+}
+
+#define PCOM_VREG_LDO PCOM_VREG_SMP
+
+PCOM_VREG_CONSUMERS(smps0) = {
+ REGULATOR_SUPPLY("smps0", NULL),
+ REGULATOR_SUPPLY("msmc1", NULL),
+};
+
+PCOM_VREG_CONSUMERS(smps1) = {
+ REGULATOR_SUPPLY("smps1", NULL),
+ REGULATOR_SUPPLY("msmc2", NULL),
+};
+
+PCOM_VREG_CONSUMERS(smps2) = {
+ REGULATOR_SUPPLY("smps2", NULL),
+ REGULATOR_SUPPLY("pa", NULL),
+};
+
+PCOM_VREG_CONSUMERS(smps3) = {
+ REGULATOR_SUPPLY("smps3", NULL),
+ REGULATOR_SUPPLY("msme1", NULL),
+};
+
+PCOM_VREG_CONSUMERS(ldo00) = {
+ REGULATOR_SUPPLY("ldo00", NULL),
+ REGULATOR_SUPPLY("gp3", NULL),
+};
+
+PCOM_VREG_CONSUMERS(ldo01) = {
+ REGULATOR_SUPPLY("ldo01", NULL),
+ REGULATOR_SUPPLY("msma", NULL),
+};
+
+PCOM_VREG_CONSUMERS(ldo02) = {
+ REGULATOR_SUPPLY("ldo02", NULL),
+ REGULATOR_SUPPLY("msmp", NULL),
+};
+
+PCOM_VREG_CONSUMERS(ldo03) = {
+ REGULATOR_SUPPLY("ldo03", NULL),
+ REGULATOR_SUPPLY("ruim", NULL),
+};
+
+PCOM_VREG_CONSUMERS(ldo04) = {
+ REGULATOR_SUPPLY("ldo04", NULL),
+ REGULATOR_SUPPLY("tcxo", NULL),
+};
+
+PCOM_VREG_CONSUMERS(ldo05) = {
+ REGULATOR_SUPPLY("ldo05", NULL),
+ REGULATOR_SUPPLY("mmc", NULL),
+};
+
+PCOM_VREG_CONSUMERS(ldo06) = {
+ REGULATOR_SUPPLY("ldo06", NULL),
+ REGULATOR_SUPPLY("usb", NULL),
+};
+
+PCOM_VREG_CONSUMERS(ldo07) = {
+ REGULATOR_SUPPLY("ldo07", NULL),
+ REGULATOR_SUPPLY("rfrx1", NULL),
+};
+
+PCOM_VREG_CONSUMERS(ldo08) = {
+ REGULATOR_SUPPLY("ldo08", NULL),
+ REGULATOR_SUPPLY("synt", NULL),
+};
+
+PCOM_VREG_CONSUMERS(ldo09) = {
+ REGULATOR_SUPPLY("ldo09", NULL),
+ REGULATOR_SUPPLY("gp1", NULL),
+};
+
+PCOM_VREG_CONSUMERS(ldo10) = {
+ REGULATOR_SUPPLY("ldo10", NULL),
+ REGULATOR_SUPPLY("gp4", NULL),
+};
+
+PCOM_VREG_CONSUMERS(ldo11) = {
+ REGULATOR_SUPPLY("ldo11", NULL),
+ REGULATOR_SUPPLY("gp2", NULL),
+};
+
+PCOM_VREG_CONSUMERS(ldo12) = {
+ REGULATOR_SUPPLY("ldo12", NULL),
+ REGULATOR_SUPPLY("rftx", NULL),
+};
+
+PCOM_VREG_CONSUMERS(ldo13) = {
+ REGULATOR_SUPPLY("ldo13", NULL),
+ REGULATOR_SUPPLY("wlan", NULL),
+};
+
+PCOM_VREG_CONSUMERS(ldo14) = {
+ REGULATOR_SUPPLY("ldo14", NULL),
+ REGULATOR_SUPPLY("rf", NULL),
+};
+
+PCOM_VREG_CONSUMERS(ldo15) = {
+ REGULATOR_SUPPLY("ldo15", NULL),
+ REGULATOR_SUPPLY("gp6", NULL),
+};
+
+PCOM_VREG_CONSUMERS(ldo16) = {
+ REGULATOR_SUPPLY("ldo16", NULL),
+ REGULATOR_SUPPLY("gp5", NULL),
+};
+
+PCOM_VREG_CONSUMERS(ldo17) = {
+ REGULATOR_SUPPLY("ldo17", NULL),
+ REGULATOR_SUPPLY("msme2", NULL),
+};
+
+/**
+ * Minimum and Maximum range for the regulators is as per the
+ * device Datasheet. Actual value used by consumer is between
+ * the provided range.
+ */
+static struct proccomm_regulator_info msm7627_pcom_vreg_info[] = {
+ /* Standard regulators (SMPS and LDO)
+ * R = rise time (us)
+ * P = pulldown (1 = pull down, 0 = float, -1 = don't care)
+ * A = always on
+ * B = boot on
+ * V = automatic voltage set (meaningful for single-voltage regs only)
+ * S = supply voltage (uV)
+ * name id supp min uV max uV R P A B V S */
+ PCOM_VREG_SMP(smps0, 3, NULL, 750000, 3050000, 0, -1, 0, 0, 0, 0),
+ PCOM_VREG_SMP(smps1, 4, NULL, 750000, 3050000, 0, -1, 0, 0, 0, 0),
+ PCOM_VREG_SMP(smps2, 10, NULL, 750000, 3050000, 0, -1, 0, 0, 0, 0),
+ PCOM_VREG_SMP(smps3, 2, NULL, 750000, 3050000, 0, -1, 0, 0, 0, 0),
+ PCOM_VREG_LDO(ldo00, 5, NULL, 2850000, 2850000, 0, -1, 0, 0, 0, 0),
+ PCOM_VREG_LDO(ldo01, 0, NULL, 2600000, 2600000, 0, -1, 0, 0, 0, 0),
+ PCOM_VREG_LDO(ldo02, 1, NULL, 2600000, 2600000, 0, -1, 0, 0, 0, 0),
+ PCOM_VREG_LDO(ldo03, 19, NULL, 2850000, 2850000, 0, -1, 0, 0, 0, 0),
+ PCOM_VREG_LDO(ldo04, 9, NULL, 2850000, 2850000, 0, -1, 0, 0, 0, 0),
+ PCOM_VREG_LDO(ldo05, 18, NULL, 2850000, 2850000, 0, -1, 0, 0, 0, 0),
+ PCOM_VREG_LDO(ldo06, 16, NULL, 3300000, 3300000, 0, -1, 0, 0, 0, 0),
+ PCOM_VREG_LDO(ldo07, 12, NULL, 2700000, 2700000, 0, -1, 0, 0, 0, 0),
+ PCOM_VREG_LDO(ldo08, 14, NULL, 2700000, 2700000, 0, -1, 0, 0, 0, 0),
+ PCOM_VREG_LDO(ldo09, 8, NULL, 2900000, 2900000, 0, -1, 0, 0, 0, 0),
+ PCOM_VREG_LDO(ldo10, 7, NULL, 2600000, 2600000, 0, -1, 0, 0, 0, 0),
+ PCOM_VREG_LDO(ldo11, 21, NULL, 1800000, 1800000, 0, -1, 0, 0, 0, 0),
+ PCOM_VREG_LDO(ldo12, 11, NULL, 1800000, 1800000, 0, -1, 0, 0, 0, 0),
+ PCOM_VREG_LDO(ldo13, 15, NULL, 2850000, 2850000, 0, -1, 0, 0, 0, 0),
+ PCOM_VREG_LDO(ldo14, 24, NULL, 2700000, 2700000, 0, -1, 0, 0, 0, 0),
+ PCOM_VREG_LDO(ldo15, 23, NULL, 2600000, 2600000, 0, -1, 0, 0, 0, 0),
+ PCOM_VREG_LDO(ldo16, 22, NULL, 3000000, 3000000, 0, -1, 0, 0, 0, 0),
+ PCOM_VREG_LDO(ldo17, 6, NULL, 1300000, 1300000, 0, -1, 0, 0, 0, 0),
+
+};
+
+struct proccomm_regulator_platform_data msm7627_proccomm_regulator_data = {
+ .regs = msm7627_pcom_vreg_info,
+ .nregs = ARRAY_SIZE(msm7627_pcom_vreg_info)
+};
diff --git a/arch/arm/mach-msm/board-msm7627-regulator.h b/arch/arm/mach-msm/board-msm7627-regulator.h
new file mode 100644
index 0000000..d82c5c0
--- /dev/null
+++ b/arch/arm/mach-msm/board-msm7627-regulator.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_MSM_BOARD_7627_REGULATOR_H__
+#define __ARCH_ARM_MACH_MSM_BOARD_7627_REGULATOR_H__
+
+#include "proccomm-regulator.h"
+
+extern struct proccomm_regulator_platform_data msm7627_proccomm_regulator_data;
+
+#endif
diff --git a/arch/arm/mach-msm/board-msm7x27.c b/arch/arm/mach-msm/board-msm7x27.c
index 22de352..3114e42 100644
--- a/arch/arm/mach-msm/board-msm7x27.c
+++ b/arch/arm/mach-msm/board-msm7x27.c
@@ -63,11 +63,13 @@
#include <mach/usbdiag.h>
#endif
+#include "board-msm7627-regulator.h"
#include "devices.h"
#include "clock.h"
#include "acpuclock.h"
#include "msm-keypad-devices.h"
#include "pm.h"
+#include "pm-boot.h"
#ifdef CONFIG_ARCH_MSM7X25
#define MSM_PMEM_MDP_SIZE 0xb21000
@@ -1568,7 +1570,21 @@
.aux_dat = 96,
.msm_i2c_config_gpio = msm_i2c_gpio_config,
};
+static struct platform_device msm_proccomm_regulator_dev = {
+ .name = PROCCOMM_REGULATOR_DEV_NAME,
+ .id = -1,
+ .dev = {
+ .platform_data = &msm7627_proccomm_regulator_data
+ }
+};
+static void __init msm7627_init_regulators(void)
+{
+ int rc = platform_device_register(&msm_proccomm_regulator_dev);
+ if (rc)
+ pr_err("%s: could not register regulator device: %d\n",
+ __func__, rc);
+}
static void __init msm_device_i2c_init(void)
{
if (gpio_request(60, "i2c_pri_clk"))
@@ -1623,6 +1639,7 @@
static void __init msm7x2x_init(void)
{
+ msm7627_init_regulators();
#ifdef CONFIG_ARCH_MSM7X25
msm_clock_init(msm_clocks_7x25, msm_num_clocks_7x25);
#elif defined(CONFIG_ARCH_MSM7X27)
@@ -1711,6 +1728,9 @@
else
msm_pm_set_platform_data(msm7x25_pm_data,
ARRAY_SIZE(msm7x25_pm_data));
+
+ BUG_ON(msm_pm_boot_init(MSM_PM_BOOT_CONFIG_RESET_VECTOR,
+ ioremap(0, PAGE_SIZE)));
msm7x27_wlan_init();
}
diff --git a/arch/arm/mach-msm/board-msm7x27a-regulator.c b/arch/arm/mach-msm/board-msm7x27a-regulator.c
index 19e9285..1a3bb75 100644
--- a/arch/arm/mach-msm/board-msm7x27a-regulator.c
+++ b/arch/arm/mach-msm/board-msm7x27a-regulator.c
@@ -205,7 +205,7 @@
PCOM_VREG_LDO(ldo02, 13, NULL, 2850000, 2850000, 0, -1, 0, 0, 0, 0),
PCOM_VREG_LDO(ldo03, 49, NULL, 1200000, 1200000, 0, -1, 0, 0, 0, 0),
PCOM_VREG_LDO(ldo04, 50, NULL, 1100000, 1100000, 0, -1, 0, 0, 0, 0),
- PCOM_VREG_LDO(ldo05, 45, NULL, 1300000, 1300000, 0, -1, 0, 0, 0, 0),
+ PCOM_VREG_LDO(ldo05, 45, NULL, 1300000, 1350000, 0, -1, 0, 0, 0, 0),
PCOM_VREG_LDO(ldo06, 51, NULL, 1200000, 1200000, 0, -1, 0, 0, 0, 0),
PCOM_VREG_LDO(ldo07, 0, NULL, 2600000, 2600000, 0, -1, 0, 0, 0, 0),
PCOM_VREG_LDO(ldo08, 9, NULL, 2850000, 2850000, 0, -1, 0, 0, 0, 0),
@@ -217,9 +217,9 @@
PCOM_VREG_LDO(ldo14, 16, NULL, 3300000, 3300000, 0, -1, 0, 0, 0, 0),
PCOM_VREG_LDO(ldo15, 54, NULL, 1800000, 2850000, 0, -1, 0, 0, 0, 0),
PCOM_VREG_LDO(ldo16, 19, NULL, 1800000, 2850000, 0, -1, 0, 0, 0, 0),
- PCOM_VREG_LDO(ldo17, 56, NULL, 2900000, 3000000, 0, -1, 0, 0, 0, 0),
+ PCOM_VREG_LDO(ldo17, 56, NULL, 2900000, 3300000, 0, -1, 0, 0, 0, 0),
PCOM_VREG_LDO(ldo18, 11, NULL, 2700000, 2700000, 0, -1, 0, 0, 0, 0),
- PCOM_VREG_LDO(ldo19, 57, NULL, 1200000, 1200000, 0, -1, 0, 0, 0, 0),
+ PCOM_VREG_LDO(ldo19, 57, NULL, 1200000, 1800000, 0, -1, 0, 0, 0, 0),
PCOM_VREG_NCP(ncp, 31, NULL, -1800000, -1800000, 0, 0, 0, 0, 0),
};
diff --git a/arch/arm/mach-msm/board-msm7x27a.c b/arch/arm/mach-msm/board-msm7x27a.c
index 44939e7..ca1da75 100644
--- a/arch/arm/mach-msm/board-msm7x27a.c
+++ b/arch/arm/mach-msm/board-msm7x27a.c
@@ -53,6 +53,7 @@
#include "pm.h"
#include <mach/rpc_server_handset.h>
#include <mach/socinfo.h>
+#include "pm-boot.h"
#define PMEM_KERNEL_EBI1_SIZE 0x3A000
#define MSM_PMEM_AUDIO_SIZE 0x5B000
@@ -465,13 +466,14 @@
struct bt_vreg_info {
const char *name;
unsigned int pmapp_id;
- unsigned int level;
+ unsigned int min_level;
+ unsigned int max_level;
unsigned int is_pin_controlled;
struct regulator *reg;
};
static struct bt_vreg_info bt_vregs[] = {
- {"msme1", 2, 1800000, 0, NULL},
- {"bt", 21, 2900000, 1, NULL}
+ {"msme1", 2, 1800000, 1800000, 0, NULL},
+ {"bt", 21, 2900000, 3050000, 1, NULL}
};
static int bahama_bt(int on)
@@ -639,7 +641,8 @@
}
rc = on ? regulator_set_voltage(bt_vregs[i].reg,
- bt_vregs[i].level, bt_vregs[i].level) : 0;
+ bt_vregs[i].min_level,
+ bt_vregs[i].max_level) : 0;
if (rc) {
dev_err(&msm_bt_power_device.dev,
"%s: could not set voltage for %s: %d\n",
@@ -1847,7 +1850,7 @@
if (!strncmp(name, "lcdc_toshiba_fwvga_pt", 21) ||
!strncmp(name, "mipi_cmd_renesas_fwvga", 22))
ret = 0;
- } else if (machine_is_msm7x27a_ffa()) {
+ } else if (machine_is_msm7x27a_ffa() || machine_is_msm7625a_ffa()) {
if (!strncmp(name, "mipi_cmd_renesas_fwvga", 22))
ret = 0;
}
@@ -3199,6 +3202,8 @@
msm_pm_set_platform_data(msm7x27a_pm_data,
ARRAY_SIZE(msm7x27a_pm_data));
+ BUG_ON(msm_pm_boot_init(MSM_PM_BOOT_CONFIG_RESET_VECTOR,
+ ioremap(0, PAGE_SIZE)));
#if defined(CONFIG_I2C) && defined(CONFIG_GPIO_SX150X)
register_i2c_devices();
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
index b71061a..9fb9fb6 100644
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ b/arch/arm/mach-msm/board-msm7x30.c
@@ -80,6 +80,7 @@
#include <mach/usbdiag.h>
#endif
#include "pm.h"
+#include "pm-boot.h"
#include "spm.h"
#include "acpuclock.h"
#include <mach/dal_axi.h>
@@ -388,6 +389,14 @@
return rc;
}
+/* TODO: Put the regulator to LPM / HPM in suspend/resume*/
+static int cyttsp_platform_suspend(struct i2c_client *client)
+{
+ msleep(20);
+
+ return CY_OK;
+}
+
static int cyttsp_platform_resume(struct i2c_client *client)
{
/* add any special code to strobe a wakeup pin or chip reset */
@@ -431,6 +440,7 @@
*/
.lp_intrvl = CY_LP_INTRVL_DFLT,
.resume = cyttsp_platform_resume,
+ .suspend = cyttsp_platform_suspend,
.init = cyttsp_platform_init,
.sleep_gpio = -1,
.resout_gpio = -1,
@@ -6743,6 +6753,7 @@
.pwm_ch_id = 1, /*channel id*/
/*gpio to enable haptic*/
.hap_en_gpio = PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_HAP_ENABLE),
+ .hap_len_gpio = -1,
.max_timeout = 15000,
.mode_ctrl = PWM_GEN_MODE,
.pwm_fd = {
@@ -7002,6 +7013,8 @@
msm_fb_add_devices();
msm_pm_set_platform_data(msm_pm_data, ARRAY_SIZE(msm_pm_data));
+ BUG_ON(msm_pm_boot_init(MSM_PM_BOOT_CONFIG_RESET_VECTOR,
+ (uint32_t *)PAGE_OFFSET));
msm_device_i2c_init();
msm_device_i2c_2_init();
qup_device_i2c_init();
diff --git a/arch/arm/mach-msm/board-msm8960-regulator.c b/arch/arm/mach-msm/board-msm8960-regulator.c
index ca24e79..29b7460 100644
--- a/arch/arm/mach-msm/board-msm8960-regulator.c
+++ b/arch/arm/mach-msm/board-msm8960-regulator.c
@@ -118,6 +118,8 @@
REGULATOR_SUPPLY("8921_l25", NULL),
REGULATOR_SUPPLY("VDDD_CDC_D", "tabla-slim"),
REGULATOR_SUPPLY("CDC_VDDA_A_1P2V", "tabla-slim"),
+ REGULATOR_SUPPLY("VDDD_CDC_D", "tabla2x-slim"),
+ REGULATOR_SUPPLY("CDC_VDDA_A_1P2V", "tabla2x-slim"),
};
VREG_CONSUMERS(L26) = {
REGULATOR_SUPPLY("8921_l26", NULL),
@@ -157,7 +159,12 @@
REGULATOR_SUPPLY("CDC_VDD_CP", "tabla-slim"),
REGULATOR_SUPPLY("CDC_VDDA_TX", "tabla-slim"),
REGULATOR_SUPPLY("CDC_VDDA_RX", "tabla-slim"),
+ REGULATOR_SUPPLY("VDDIO_CDC", "tabla2x-slim"),
+ REGULATOR_SUPPLY("CDC_VDD_CP", "tabla2x-slim"),
+ REGULATOR_SUPPLY("CDC_VDDA_TX", "tabla2x-slim"),
+ REGULATOR_SUPPLY("CDC_VDDA_RX", "tabla2x-slim"),
REGULATOR_SUPPLY("vcc_i2c", "3-005b"),
+ REGULATOR_SUPPLY("EXT_HUB_VDDIO", "msm_hsic_host"),
};
VREG_CONSUMERS(S5) = {
REGULATOR_SUPPLY("8921_s5", NULL),
@@ -478,7 +485,7 @@
RPM_SMPS(S3, 0, 1, 1, 500000, 1150000, NULL, 100000, 4p80),
RPM_SMPS(S4, 1, 1, 0, 1800000, 1800000, NULL, 100000, 3p20),
RPM_SMPS(S7, 0, 1, 0, 1150000, 1150000, NULL, 100000, 3p20),
- RPM_SMPS(S8, 1, 1, 0, 2200000, 2200000, NULL, 100000, 1p60),
+ RPM_SMPS(S8, 1, 1, 1, 2200000, 2200000, NULL, 100000, 1p60),
/* ID a_on pd ss min_uV max_uV supply sys_uA init_ip */
RPM_LDO(L1, 1, 1, 0, 1050000, 1050000, "8921_s4", 0, 10000),
@@ -500,7 +507,7 @@
RPM_LDO(L18, 0, 1, 0, 1300000, 1300000, "8921_s4", 0, 0),
RPM_LDO(L21, 0, 1, 0, 1900000, 1900000, "8921_s8", 0, 0),
RPM_LDO(L22, 0, 1, 0, 2750000, 2750000, NULL, 0, 0),
- RPM_LDO(L23, 1, 1, 0, 1800000, 1800000, "8921_s8", 10000, 10000),
+ RPM_LDO(L23, 1, 1, 1, 1800000, 1800000, "8921_s8", 10000, 10000),
RPM_LDO(L24, 0, 1, 1, 750000, 1150000, "8921_s1", 10000, 10000),
RPM_LDO(L25, 1, 1, 0, 1225000, 1225000, "8921_s1", 10000, 10000),
diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c
index da49082..3412539 100644
--- a/arch/arm/mach-msm/board-msm8960.c
+++ b/arch/arm/mach-msm/board-msm8960.c
@@ -88,6 +88,7 @@
#include "acpuclock.h"
#include "rpm_log.h"
#include "smd_private.h"
+#include "pm-boot.h"
static struct platform_device msm_fm_platform_init = {
.name = "iris_fm",
@@ -153,6 +154,12 @@
PM_GPIO_STRENGTH_HIGH, \
_func, 0, 0)
+#define PM8XXX_GPIO_OUTPUT_VIN(_gpio, _val, _vin) \
+ PM8XXX_GPIO_INIT(_gpio, PM_GPIO_DIR_OUT, PM_GPIO_OUT_BUF_CMOS, _val, \
+ PM_GPIO_PULL_NO, _vin, \
+ PM_GPIO_STRENGTH_HIGH, \
+ PM_GPIO_FUNC_NORMAL, 0, 0)
+
/* Initial PM8921 GPIO configurations */
static struct pm8xxx_gpio_init pm8921_gpios[] __initdata = {
PM8XXX_GPIO_DISABLE(6), /* Disable unused */
@@ -160,7 +167,7 @@
PM8XXX_GPIO_INPUT(16, PM_GPIO_PULL_UP_30), /* SD_CARD_WP */
/* External regulator shared by display and touchscreen on LiQUID */
PM8XXX_GPIO_OUTPUT(17, 0), /* DISP 3.3 V Boost */
- PM8XXX_GPIO_OUTPUT(21, 1), /* Backlight Enable */
+ PM8XXX_GPIO_OUTPUT_VIN(21, 1, PM_GPIO_VIN_VPH), /* Backlight Enable */
PM8XXX_GPIO_DISABLE(22), /* Disable NFC */
PM8XXX_GPIO_OUTPUT_FUNC(24, 0, PM_GPIO_FUNC_2), /* Bl: Off, PWM mode */
PM8XXX_GPIO_INPUT(26, PM_GPIO_PULL_UP_30), /* SD_CARD_DET_N */
@@ -223,7 +230,7 @@
/* The SPI configurations apply to GSBI 1*/
static struct gpiomux_setting spi_active = {
.func = GPIOMUX_FUNC_1,
- .drv = GPIOMUX_DRV_8MA,
+ .drv = GPIOMUX_DRV_12MA,
.pull = GPIOMUX_PULL_NONE,
};
@@ -724,6 +731,12 @@
.pull = GPIOMUX_PULL_DOWN,
};
+static struct gpiomux_setting hsic_hub_act_cfg = {
+ .func = GPIOMUX_FUNC_GPIO,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_NONE,
+};
+
static struct msm_gpiomux_config msm8960_hsic_configs[] = {
{
.gpio = 150, /*HSIC_STROBE */
@@ -739,6 +752,13 @@
[GPIOMUX_SUSPENDED] = &hsic_sus_cfg,
},
},
+ {
+ .gpio = 91, /* HSIC_HUB_RESET */
+ .settings = {
+ [GPIOMUX_ACTIVE] = &hsic_hub_act_cfg,
+ [GPIOMUX_SUSPENDED] = &hsic_sus_cfg,
+ },
+ },
};
#endif
@@ -792,7 +812,15 @@
#else
#define MSM_PMEM_SIZE 0x1800000 /* 24 Mbytes */
#endif
-#define MSM_ION_EBI_SIZE SZ_8M
+
+
+#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
+#define MSM_ION_EBI_SIZE MSM_PMEM_SIZE
+#define MSM_ION_ADSP_SIZE MSM_PMEM_ADSP_SIZE
+#define MSM_ION_HEAP_NUM 4
+#else
+#define MSM_ION_HEAP_NUM 2
+#endif
#ifdef CONFIG_KERNEL_PMEM_EBI_REGION
static unsigned pmem_kernel_ebi1_size = MSM_PMEM_KERNEL_EBI1_SIZE;
@@ -833,6 +861,7 @@
#endif
#ifdef CONFIG_ANDROID_PMEM
+#ifndef CONFIG_MSM_MULTIMEDIA_USE_ION
static struct android_pmem_platform_data android_pmem_pdata = {
.name = "pmem",
.allocator_type = PMEM_ALLOCATORTYPE_ALLORNOTHING,
@@ -857,6 +886,7 @@
.id = 2,
.dev = { .platform_data = &android_pmem_adsp_pdata },
};
+#endif
static struct android_pmem_platform_data android_pmem_audio_pdata = {
.name = "pmem_audio",
@@ -906,8 +936,10 @@
static void __init size_pmem_devices(void)
{
#ifdef CONFIG_ANDROID_PMEM
+#ifndef CONFIG_MSM_MULTIMEDIA_USE_ION
android_pmem_adsp_pdata.size = pmem_adsp_size;
android_pmem_pdata.size = pmem_size;
+#endif
android_pmem_audio_pdata.size = MSM_PMEM_AUDIO_SIZE;
#endif
}
@@ -920,8 +952,10 @@
static void __init reserve_pmem_memory(void)
{
#ifdef CONFIG_ANDROID_PMEM
+#ifndef CONFIG_MSM_MULTIMEDIA_USE_ION
reserve_memory_for(&android_pmem_adsp_pdata);
reserve_memory_for(&android_pmem_pdata);
+#endif
reserve_memory_for(&android_pmem_audio_pdata);
msm8960_reserve_table[MEMTYPE_EBI1].size += pmem_kernel_ebi1_size;
#endif
@@ -934,7 +968,7 @@
#ifdef CONFIG_ION_MSM
struct ion_platform_data ion_pdata = {
- .nr = 3,
+ .nr = MSM_ION_HEAP_NUM,
.heaps = {
{
.id = ION_HEAP_SYSTEM_ID,
@@ -946,6 +980,7 @@
.type = ION_HEAP_TYPE_SYSTEM_CONTIG,
.name = ION_VMALLOC_HEAP_NAME,
},
+#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
{
.id = ION_HEAP_EBI_ID,
.type = ION_HEAP_TYPE_CARVEOUT,
@@ -953,6 +988,14 @@
.size = MSM_ION_EBI_SIZE,
.memory_type = ION_EBI_TYPE,
},
+ {
+ .id = ION_HEAP_ADSP_ID,
+ .type = ION_HEAP_TYPE_CARVEOUT,
+ .name = ION_ADSP_HEAP_NAME,
+ .size = MSM_ION_ADSP_SIZE,
+ .memory_type = ION_EBI_TYPE,
+ },
+#endif
}
};
@@ -965,8 +1008,9 @@
static void reserve_ion_memory(void)
{
-#ifdef CONFIG_ION_MSM
+#if defined(CONFIG_ION_MSM) && defined(CONFIG_MSM_MULTIMEDIA_USE_ION)
msm8960_reserve_table[MEMTYPE_EBI1].size += MSM_ION_EBI_SIZE;
+ msm8960_reserve_table[MEMTYPE_EBI1].size += MSM_ION_ADSP_SIZE;
#endif
}
static void __init msm8960_calculate_reserve_sizes(void)
@@ -1009,10 +1053,23 @@
msm8960_reserve_info.bank_size);
}
-static void __init msm8960_reserve(void)
+static void __init place_movable_zone(void)
+{
+ movable_reserved_start = msm8960_reserve_info.low_unstable_address;
+ movable_reserved_size = msm8960_reserve_info.max_unstable_size;
+ pr_info("movable zone start %lx size %lx\n",
+ movable_reserved_start, movable_reserved_size);
+}
+
+static void __init msm8960_early_memory(void)
{
reserve_info = &msm8960_reserve_info;
locate_unstable_memory();
+ place_movable_zone();
+}
+
+static void __init msm8960_reserve(void)
+{
msm_reserve();
}
@@ -2368,6 +2425,35 @@
.platform_data = &tabla_platform_data,
},
};
+
+static struct tabla_pdata tabla20_platform_data = {
+ .slimbus_slave_device = {
+ .name = "tabla-slave",
+ .e_addr = {0, 0, 0x60, 0, 0x17, 2},
+ },
+ .irq = MSM_GPIO_TO_INT(62),
+ .irq_base = TABLA_INTERRUPT_BASE,
+ .num_irqs = NR_TABLA_IRQS,
+ .reset_gpio = PM8921_GPIO_PM_TO_SYS(34),
+ .micbias = {
+ .ldoh_v = TABLA_LDOH_2P85_V,
+ .cfilt1_mv = 1800,
+ .cfilt2_mv = 1800,
+ .cfilt3_mv = 1800,
+ .bias1_cfilt_sel = TABLA_CFILT1_SEL,
+ .bias2_cfilt_sel = TABLA_CFILT2_SEL,
+ .bias3_cfilt_sel = TABLA_CFILT3_SEL,
+ .bias4_cfilt_sel = TABLA_CFILT3_SEL,
+ }
+};
+
+static struct slim_device msm_slim_tabla20 = {
+ .name = "tabla2x-slim",
+ .e_addr = {0, 1, 0x60, 0, 0x17, 2},
+ .dev = {
+ .platform_data = &tabla20_platform_data,
+ },
+};
#endif
static struct slim_boardinfo msm_slim_devices[] = {
@@ -2376,6 +2462,10 @@
.bus_num = 1,
.slim_slave = &msm_slim_tabla,
},
+ {
+ .bus_num = 1,
+ .slim_slave = &msm_slim_tabla20,
+ },
#endif
/* add more slimbus slaves as needed */
};
@@ -2576,11 +2666,6 @@
msm_gpiomux_install(wcnss_5wire_interface,
ARRAY_SIZE(wcnss_5wire_interface));
-#ifdef CONFIG_USB_EHCI_MSM_HSIC
- msm_gpiomux_install(msm8960_hsic_configs,
- ARRAY_SIZE(msm8960_hsic_configs));
-#endif
-
return 0;
}
@@ -2678,7 +2763,7 @@
}
}
-/* MSM8960 have 5 SDCC controllers */
+/* MSM8960 has 5 SDCC controllers */
enum sdcc_controllers {
SDCC1,
SDCC2,
@@ -2688,7 +2773,7 @@
MAX_SDCC_CONTROLLER
};
-/* All SDCC controllers requires VDD/VCC voltage */
+/* All SDCC controllers require VDD/VCC voltage */
static struct msm_mmc_reg_data mmc_vdd_reg_data[MAX_SDCC_CONTROLLER] = {
/* SDCC1 : eMMC card connected */
[SDCC1] = {
@@ -3019,6 +3104,7 @@
#endif
#ifdef CONFIG_USB_EHCI_MSM_HSIC
+#define HSIC_HUB_RESET_GPIO 91
static struct msm_hsic_host_platform_data msm_hsic_pdata = {
.strobe = 150,
.data = 151,
@@ -3073,8 +3159,7 @@
}
dload->magic_struct.serial_num = SERIAL_NUM_MAGIC_ID;
- strncpy(dload->serial_number, snum, SERIAL_NUMBER_LENGTH);
- dload->serial_number[SERIAL_NUMBER_LENGTH - 1] = '\0';
+ strlcpy(dload->serial_number, snum, SERIAL_NUMBER_LENGTH);
out:
iounmap(dload);
return 0;
@@ -3271,14 +3356,16 @@
.name = "vdd",
.min_uV = CY_TMA300_VTG_MIN_UV,
.max_uV = CY_TMA300_VTG_MAX_UV,
- .load_uA = CY_TMA300_CURR_24HZ_UA,
+ .hpm_load_uA = CY_TMA300_CURR_24HZ_UA,
+ .lpm_load_uA = CY_TMA300_SLEEP_CURR_UA,
},
/* TODO: Remove after runtime PM is enabled in I2C driver */
{
.name = "vcc_i2c",
.min_uV = CY_I2C_VTG_MIN_UV,
.max_uV = CY_I2C_VTG_MAX_UV,
- .load_uA = CY_I2C_CURR_UA,
+ .hpm_load_uA = CY_I2C_CURR_UA,
+ .lpm_load_uA = CY_I2C_SLEEP_CURR_UA,
},
};
@@ -3644,8 +3731,10 @@
&fish_battery_device,
#endif
#ifdef CONFIG_ANDROID_PMEM
+#ifndef CONFIG_MSM_MULTIMEDIA_USE_ION
&android_pmem_device,
&android_pmem_adsp_device,
+#endif
&android_pmem_audio_device,
#endif
&msm_fb_device,
@@ -3725,7 +3814,6 @@
&msm8960_device_otg,
&msm8960_device_gadget_peripheral,
&msm_device_hsusb_host,
- &msm_device_hsic_host,
&android_usb_device,
&msm_pcm,
&msm_pcm_routing,
@@ -4335,6 +4423,28 @@
#endif /* CONFIG_MSM_DSPS */
}
+static void __init msm8960_init_hsic(void)
+{
+#ifdef CONFIG_USB_EHCI_MSM_HSIC
+ uint32_t version = socinfo_get_version();
+
+ pr_info("%s: version:%d mtp:%d\n", __func__,
+ SOCINFO_VERSION_MAJOR(version),
+ machine_is_msm8960_mtp());
+
+ if ((SOCINFO_VERSION_MAJOR(version) == 1) ||
+ machine_is_msm8960_mtp() ||
+ machine_is_msm8960_fluid())
+ return;
+
+ msm_gpiomux_install(msm8960_hsic_configs,
+ ARRAY_SIZE(msm8960_hsic_configs));
+
+ platform_device_register(&msm_device_hsic_host);
+#endif
+}
+
+
#ifdef CONFIG_ISL9519_CHARGER
static struct isl_platform_data isl_data __initdata = {
.valid_n_gpio = 0, /* Not required when notify-by-pmic */
@@ -4460,6 +4570,7 @@
msm_pm_set_rpm_wakeup_irq(RPM_APCC_CPU0_WAKE_UP_IRQ);
msm_cpuidle_set_states(msm_cstates, ARRAY_SIZE(msm_cstates),
msm_pm_data);
+ BUG_ON(msm_pm_boot_init(MSM_PM_BOOT_CONFIG_TZ, NULL));
}
static void __init msm8960_rumi3_init(void)
@@ -4492,6 +4603,7 @@
msm_pm_set_rpm_wakeup_irq(RPM_APCC_CPU0_WAKE_UP_IRQ);
msm_cpuidle_set_states(msm_cstates, ARRAY_SIZE(msm_cstates),
msm_pm_data);
+ BUG_ON(msm_pm_boot_init(MSM_PM_BOOT_CONFIG_TZ, NULL));
}
static void __init msm8960_cdp_init(void)
@@ -4512,6 +4624,12 @@
msm8960_device_otg.dev.platform_data = &msm_otg_pdata;
msm8960_device_gadget_peripheral.dev.parent = &msm8960_device_otg.dev;
msm_device_hsusb_host.dev.parent = &msm8960_device_otg.dev;
+#ifdef CONFIG_USB_EHCI_MSM_HSIC
+ if (machine_is_msm8960_liquid()) {
+ if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 2)
+ msm_hsic_pdata.hub_reset = HSIC_HUB_RESET_GPIO;
+ }
+#endif
msm_device_hsic_host.dev.platform_data = &msm_hsic_pdata;
gpiomux_init();
if (machine_is_msm8960_cdp())
@@ -4536,6 +4654,7 @@
platform_add_devices(common_devices, ARRAY_SIZE(common_devices));
pm8921_gpio_mpp_init();
platform_add_devices(cdp_devices, ARRAY_SIZE(cdp_devices));
+ msm8960_init_hsic();
msm8960_init_cam();
msm8960_init_mmc();
acpuclk_init(&acpuclk_8960_soc_data);
@@ -4551,6 +4670,7 @@
msm_cpuidle_set_states(msm_cstates, ARRAY_SIZE(msm_cstates),
msm_pm_data);
change_memory_power = &msm8960_change_memory_power;
+ BUG_ON(msm_pm_boot_init(MSM_PM_BOOT_CONFIG_TZ, NULL));
}
MACHINE_START(MSM8960_SIM, "QCT MSM8960 SIMULATOR")
@@ -4560,6 +4680,7 @@
.timer = &msm_timer,
.init_machine = msm8960_sim_init,
.init_early = msm8960_allocate_memory_regions,
+ .init_very_early = msm8960_early_memory,
MACHINE_END
MACHINE_START(MSM8960_RUMI3, "QCT MSM8960 RUMI3")
@@ -4569,6 +4690,7 @@
.timer = &msm_timer,
.init_machine = msm8960_rumi3_init,
.init_early = msm8960_allocate_memory_regions,
+ .init_very_early = msm8960_early_memory,
MACHINE_END
MACHINE_START(MSM8960_CDP, "QCT MSM8960 CDP")
@@ -4578,6 +4700,7 @@
.timer = &msm_timer,
.init_machine = msm8960_cdp_init,
.init_early = msm8960_allocate_memory_regions,
+ .init_very_early = msm8960_early_memory,
MACHINE_END
MACHINE_START(MSM8960_MTP, "QCT MSM8960 MTP")
@@ -4587,6 +4710,7 @@
.timer = &msm_timer,
.init_machine = msm8960_cdp_init,
.init_early = msm8960_allocate_memory_regions,
+ .init_very_early = msm8960_early_memory,
MACHINE_END
MACHINE_START(MSM8960_FLUID, "QCT MSM8960 FLUID")
@@ -4596,6 +4720,7 @@
.timer = &msm_timer,
.init_machine = msm8960_cdp_init,
.init_early = msm8960_allocate_memory_regions,
+ .init_very_early = msm8960_early_memory,
MACHINE_END
MACHINE_START(MSM8960_LIQUID, "QCT MSM8960 LIQUID")
@@ -4605,6 +4730,7 @@
.timer = &msm_timer,
.init_machine = msm8960_cdp_init,
.init_early = msm8960_allocate_memory_regions,
+ .init_very_early = msm8960_early_memory,
MACHINE_END
#ifdef CONFIG_ARCH_MSM8930
@@ -4615,6 +4741,7 @@
.timer = &msm_timer,
.init_machine = msm8960_cdp_init,
.init_early = msm8960_allocate_memory_regions,
+ .init_very_early = msm8960_early_memory,
MACHINE_END
MACHINE_START(MSM8930_MTP, "QCT MSM8930 MTP")
@@ -4624,6 +4751,7 @@
.timer = &msm_timer,
.init_machine = msm8960_cdp_init,
.init_early = msm8960_allocate_memory_regions,
+ .init_very_early = msm8960_early_memory,
MACHINE_END
MACHINE_START(MSM8930_FLUID, "QCT MSM8930 FLUID")
@@ -4633,5 +4761,6 @@
.timer = &msm_timer,
.init_machine = msm8960_cdp_init,
.init_early = msm8960_allocate_memory_regions,
+ .init_very_early = msm8960_early_memory,
MACHINE_END
#endif
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index 956387a..d3d5ffa 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -108,6 +108,10 @@
#include <linux/platform_data/qcom_crypto_device.h>
#include "rpm_resources.h"
#include "acpuclock.h"
+#include "pm-boot.h"
+
+#include <linux/ion.h>
+#include <mach/ion.h>
#define MSM_SHARED_RAM_PHYS 0x40000000
@@ -2210,6 +2214,10 @@
#endif
#ifdef CONFIG_IMX074
+static struct msm_camera_sensor_platform_info imx074_sensor_board_info = {
+ .mount_angle = 180
+};
+
static struct msm_camera_sensor_flash_data flash_imx074 = {
.flash_type = MSM_CAMERA_FLASH_LED,
.flash_src = &msm_flash_src
@@ -2226,7 +2234,7 @@
.num_resources = ARRAY_SIZE(msm_camera_resources),
.flash_data = &flash_imx074,
.strobe_flash_data = &strobe_flash_xenon,
- .sensor_platform_info = &sensor_board_info,
+ .sensor_platform_info = &imx074_sensor_board_info,
.csi_if = 1
};
struct platform_device msm_camera_sensor_imx074 = {
@@ -2620,6 +2628,16 @@
#define USER_SMI_SIZE (MSM_SMI_SIZE - KERNEL_SMI_SIZE)
#define MSM_PMEM_SMIPOOL_SIZE USER_SMI_SIZE
+#define MSM_ION_EBI_SIZE MSM_PMEM_SF_SIZE
+#define MSM_ION_ADSP_SIZE MSM_PMEM_ADSP_SIZE
+#define MSM_ION_SMI_SIZE MSM_PMEM_SMIPOOL_SIZE
+
+#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
+#define MSM_ION_HEAP_NUM 5
+#else
+#define MSM_ION_HEAP_NUM 2
+#endif
+
static unsigned fb_size;
static int __init fb_size_setup(char *p)
{
@@ -2749,6 +2767,7 @@
};
#ifdef CONFIG_ANDROID_PMEM
+#ifndef CONFIG_MSM_MULTIMEDIA_USE_ION
static struct android_pmem_platform_data android_pmem_pdata = {
.name = "pmem",
.allocator_type = PMEM_ALLOCATORTYPE_ALLORNOTHING,
@@ -2774,7 +2793,7 @@
.id = 2,
.dev = { .platform_data = &android_pmem_adsp_pdata },
};
-
+#endif
static struct android_pmem_platform_data android_pmem_audio_pdata = {
.name = "pmem_audio",
.allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
@@ -2798,6 +2817,7 @@
}, \
.num_paths = 1, \
}
+#ifndef CONFIG_MSM_MULTIMEDIA_USE_ION
static struct msm_bus_paths pmem_smi_table[] = {
[0] = PMEM_BUS_WIDTH(0), /* Off */
[1] = PMEM_BUS_WIDTH(1), /* On */
@@ -2809,21 +2829,21 @@
.name = "pmem_smi",
};
-void pmem_request_smi_region(void *data)
+void request_smi_region(void *data)
{
int bus_id = (int) data;
msm_bus_scale_client_update_request(bus_id, 1);
}
-void pmem_release_smi_region(void *data)
+void release_smi_region(void *data)
{
int bus_id = (int) data;
msm_bus_scale_client_update_request(bus_id, 0);
}
-void *pmem_setup_smi_region(void)
+void *setup_smi_region(void)
{
return (void *)msm_bus_scale_register_client(&smi_client_pdata);
}
@@ -2832,9 +2852,9 @@
.allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
.cached = 0,
.memory_type = MEMTYPE_SMI,
- .request_region = pmem_request_smi_region,
- .release_region = pmem_release_smi_region,
- .setup_region = pmem_setup_smi_region,
+ .request_region = request_smi_region,
+ .release_region = release_smi_region,
+ .setup_region = setup_smi_region,
.map_on_demand = 1,
};
static struct platform_device android_pmem_smipool_device = {
@@ -2842,7 +2862,7 @@
.id = 7,
.dev = { .platform_data = &android_pmem_smipool_pdata },
};
-
+#endif
#endif
#define GPIO_DONGLE_PWR_EN 258
@@ -3189,6 +3209,14 @@
return rc;
}
+/* TODO: Put the regulator to LPM / HPM in suspend/resume*/
+static int cyttsp_platform_suspend(struct i2c_client *client)
+{
+ msleep(20);
+
+ return CY_OK;
+}
+
static int cyttsp_platform_resume(struct i2c_client *client)
{
/* add any special code to strobe a wakeup pin or chip reset */
@@ -3228,6 +3256,7 @@
.resout_gpio = -1,
.irq_gpio = CYTTSP_TS_GPIO_IRQ,
.resume = cyttsp_platform_resume,
+ .suspend = cyttsp_platform_suspend,
.init = cyttsp_platform_init,
};
@@ -3270,6 +3299,7 @@
.resout_gpio = -1,
.irq_gpio = CYTTSP_TS_GPIO_IRQ,
.resume = cyttsp_platform_resume,
+ .suspend = cyttsp_platform_suspend,
.init = cyttsp_platform_init,
.disable_ghost_det = true,
};
@@ -4127,11 +4157,13 @@
&msm_device_ssbi3,
#endif
#ifdef CONFIG_ANDROID_PMEM
+#ifndef CONFIG_MSM_MULTIMEDIA_USE_ION
&android_pmem_device,
&android_pmem_adsp_device,
- &android_pmem_audio_device,
&android_pmem_smipool_device,
#endif
+ &android_pmem_audio_device,
+#endif
#ifdef CONFIG_MSM_ROTATOR
&msm_rotator_device,
#endif
@@ -4997,11 +5029,13 @@
&msm_batt_device,
#endif
#ifdef CONFIG_ANDROID_PMEM
+#ifndef CONFIG_MSM_MULTIMEDIA_USE_ION
&android_pmem_device,
&android_pmem_adsp_device,
- &android_pmem_audio_device,
&android_pmem_smipool_device,
#endif
+ &android_pmem_audio_device,
+#endif
#ifdef CONFIG_MSM_ROTATOR
&msm_rotator_device,
#endif
@@ -5094,9 +5128,59 @@
&msm_tsens_device,
&msm_rpm_device,
-
+#ifdef CONFIG_ION_MSM
+ &ion_dev,
+#endif
};
+#ifdef CONFIG_ION_MSM
+struct ion_platform_data ion_pdata = {
+ .nr = MSM_ION_HEAP_NUM,
+ .heaps = {
+ {
+ .id = ION_HEAP_SYSTEM_ID,
+ .type = ION_HEAP_TYPE_SYSTEM,
+ .name = ION_VMALLOC_HEAP_NAME,
+ },
+ {
+ .id = ION_HEAP_SYSTEM_CONTIG_ID,
+ .type = ION_HEAP_TYPE_SYSTEM_CONTIG,
+ .name = ION_KMALLOC_HEAP_NAME,
+ },
+#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
+ {
+ .id = ION_HEAP_EBI_ID,
+ .type = ION_HEAP_TYPE_CARVEOUT,
+ .name = ION_EBI1_HEAP_NAME,
+ .size = MSM_ION_EBI_SIZE,
+ .memory_type = ION_EBI_TYPE,
+ },
+ {
+ .id = ION_HEAP_ADSP_ID,
+ .type = ION_HEAP_TYPE_CARVEOUT,
+ .name = ION_ADSP_HEAP_NAME,
+ .size = MSM_ION_ADSP_SIZE,
+ .memory_type = ION_EBI_TYPE,
+ },
+ {
+ .id = ION_HEAP_SMI_ID,
+ .type = ION_HEAP_TYPE_CARVEOUT,
+ .name = ION_SMI_HEAP_NAME,
+ .size = MSM_ION_SMI_SIZE,
+ .memory_type = ION_SMI_TYPE,
+ },
+#endif
+ }
+};
+
+struct platform_device ion_dev = {
+ .name = "ion-msm",
+ .id = 1,
+ .dev = { .platform_data = &ion_pdata },
+};
+#endif
+
+
static struct memtype_reserve msm8x60_reserve_table[] __initdata = {
/* Kernel SMI memory pool for video core, used for firmware */
/* and encoder, decoder scratch buffers */
@@ -5124,14 +5208,25 @@
},
};
+static void reserve_ion_memory(void)
+{
+#if defined(CONFIG_ION_MSM) && defined(CONFIG_MSM_MULTIMEDIA_USE_ION)
+ msm8x60_reserve_table[MEMTYPE_EBI1].size += MSM_ION_EBI_SIZE;
+ msm8x60_reserve_table[MEMTYPE_EBI1].size += MSM_ION_ADSP_SIZE;
+ msm8x60_reserve_table[MEMTYPE_SMI].size += MSM_ION_SMI_SIZE;
+#endif
+}
+
static void __init size_pmem_devices(void)
{
#ifdef CONFIG_ANDROID_PMEM
+#ifndef CONFIG_MSM_MULTIMEDIA_USE_ION
android_pmem_adsp_pdata.size = pmem_adsp_size;
android_pmem_smipool_pdata.size = MSM_PMEM_SMIPOOL_SIZE;
- android_pmem_audio_pdata.size = MSM_PMEM_AUDIO_SIZE;
android_pmem_pdata.size = pmem_sf_size;
#endif
+ android_pmem_audio_pdata.size = MSM_PMEM_AUDIO_SIZE;
+#endif
}
static void __init reserve_memory_for(struct android_pmem_platform_data *p)
@@ -5142,18 +5237,23 @@
static void __init reserve_pmem_memory(void)
{
#ifdef CONFIG_ANDROID_PMEM
+#ifndef CONFIG_MSM_MULTIMEDIA_USE_ION
reserve_memory_for(&android_pmem_adsp_pdata);
reserve_memory_for(&android_pmem_smipool_pdata);
- reserve_memory_for(&android_pmem_audio_pdata);
reserve_memory_for(&android_pmem_pdata);
+#endif
+ reserve_memory_for(&android_pmem_audio_pdata);
msm8x60_reserve_table[MEMTYPE_EBI1].size += pmem_kernel_ebi1_size;
#endif
}
+
+
static void __init msm8x60_calculate_reserve_sizes(void)
{
size_pmem_devices();
reserve_pmem_memory();
+ reserve_ion_memory();
}
static int msm8x60_paddr_to_memtype(unsigned int paddr)
@@ -7559,7 +7659,7 @@
|| defined(CONFIG_MMC_MSM_SDC4_SUPPORT)\
|| defined(CONFIG_MMC_MSM_SDC5_SUPPORT))
-/* 8x60 is having 5 SDCC controllers */
+/* 8x60 has 5 SDCC controllers */
#define MAX_SDCC_CONTROLLER 5
struct msm_sdcc_gpio {
@@ -7883,7 +7983,7 @@
unsigned int lpm_uA;
unsigned int hpm_uA;
};
-/* all SDCC controllers requires VDD/VCC voltage */
+/* all SDCC controllers require VDD/VCC voltage */
static struct sdcc_reg sdcc_vdd_reg_data[MAX_SDCC_CONTROLLER];
/* only SDCC1 requires VCCQ voltage */
static struct sdcc_reg sdcc_vccq_reg_data[1];
@@ -7896,7 +7996,7 @@
struct sdcc_reg *vddp_data; /* keeps VDD Pad regulator info */
unsigned char sts; /* regulator enable/disable status */
};
-/* msm8x60 have 5 SDCC controllers */
+/* msm8x60 has 5 SDCC controllers */
static struct sdcc_reg_data sdcc_vreg_data[MAX_SDCC_CONTROLLER];
static int msm_sdcc_vreg_init_reg(struct sdcc_reg *vreg)
@@ -10321,6 +10421,7 @@
msm_pm_set_rpm_wakeup_irq(RPM_SCSS_CPU0_WAKE_UP_IRQ);
msm_cpuidle_set_states(msm_cstates, ARRAY_SIZE(msm_cstates),
msm_pm_data);
+ BUG_ON(msm_pm_boot_init(MSM_PM_BOOT_CONFIG_TZ, NULL));
#ifdef CONFIG_SENSORS_MSM_ADC
if (machine_is_msm8x60_fluid()) {
diff --git a/arch/arm/mach-msm/board-qrd7627a.c b/arch/arm/mach-msm/board-qrd7627a.c
index 1470026..e46da5b 100644
--- a/arch/arm/mach-msm/board-qrd7627a.c
+++ b/arch/arm/mach-msm/board-qrd7627a.c
@@ -64,10 +64,13 @@
GPIO_BT_SYS_REST_EN = 114,
GPIO_WAKE_ON_WIRELESS,
GPIO_BACKLIGHT_EN,
- GPIO_CAM_3MP_PWDN,
+ GPIO_NC,
+ GPIO_CAM_3MP_PWDN, /* CAM_VGA */
GPIO_WLAN_EN,
GPIO_CAM_5MP_SHDN_EN,
GPIO_CAM_5MP_RESET,
+ GPIO_TP,
+ GPIO_CAM_GP_CAMIF_RESET,
};
/* FM Platform power and shutdown routines */
@@ -1411,7 +1414,7 @@
return rc;
}
-#define GPIO_SDC1_HW_DET 85
+#define GPIO_SDC1_HW_DET 42
#if defined(CONFIG_MMC_MSM_SDC1_SUPPORT) \
&& defined(CONFIG_MMC_MSM_CARD_HW_DETECTION)
@@ -1432,7 +1435,7 @@
} else {
status = gpio_direction_input(GPIO_SDC1_HW_DET);
if (!status)
- status = gpio_get_value(GPIO_SDC1_HW_DET);
+ status = !gpio_get_value(GPIO_SDC1_HW_DET);
gpio_free(GPIO_SDC1_HW_DET);
}
return status;
@@ -1872,6 +1875,334 @@
.dev.platform_data = &msm_psy_batt_data,
};
+#ifdef CONFIG_MSM_CAMERA
+static uint32_t camera_off_gpio_table[] = {
+ GPIO_CFG(15, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
+};
+
+static uint32_t camera_on_gpio_table[] = {
+ GPIO_CFG(15, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
+};
+
+static void qrd1_camera_gpio_cfg(void)
+{
+
+ int rc = 0;
+
+ rc = gpio_request(GPIO_CAM_5MP_SHDN_EN, "ov5640");
+ if (rc < 0)
+ pr_err("%s: gpio_request---GPIO_CAM_5MP_SHDN_EN failed!",
+ __func__);
+
+
+ rc = gpio_tlmm_config(GPIO_CFG(GPIO_CAM_5MP_SHDN_EN, 0,
+ GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP,
+ GPIO_CFG_2MA), GPIO_CFG_ENABLE);
+ if (rc < 0) {
+ pr_err("%s: unable to enable Power Down gpio for main"
+ "camera!\n", __func__);
+ gpio_free(GPIO_CAM_5MP_SHDN_EN);
+ }
+
+
+ rc = gpio_request(GPIO_CAM_5MP_RESET, "ov5640");
+ if (rc < 0) {
+ pr_err("%s: gpio_request---GPIO_CAM_5MP_RESET failed!",
+ __func__);
+ gpio_free(GPIO_CAM_5MP_SHDN_EN);
+ }
+
+
+ rc = gpio_tlmm_config(GPIO_CFG(GPIO_CAM_5MP_RESET, 0,
+ GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP,
+ GPIO_CFG_2MA), GPIO_CFG_ENABLE);
+ if (rc < 0) {
+ pr_err("%s: unable to enable reset gpio for main camera!\n",
+ __func__);
+ gpio_free(GPIO_CAM_5MP_RESET);
+ }
+
+ rc = gpio_request(GPIO_CAM_3MP_PWDN, "ov7692");
+ if (rc < 0)
+ pr_err("%s: gpio_request---GPIO_CAM_3MP_PWDN failed!",
+ __func__);
+
+ rc = gpio_tlmm_config(GPIO_CFG(GPIO_CAM_3MP_PWDN, 0,
+ GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP,
+ GPIO_CFG_2MA), GPIO_CFG_ENABLE);
+ if (rc < 0) {
+ pr_err("%s: unable to enable Power Down gpio for front"
+ "camera!\n", __func__);
+ gpio_free(GPIO_CAM_3MP_PWDN);
+ }
+
+ gpio_direction_output(GPIO_CAM_5MP_SHDN_EN, 1);
+ gpio_direction_output(GPIO_CAM_5MP_RESET, 1);
+ gpio_direction_output(GPIO_CAM_3MP_PWDN, 1);
+}
+
+#endif
+static struct vreg *vreg_gp1;
+static struct vreg *vreg_gp2;
+static struct vreg *vreg_gp3;
+static void msm_camera_vreg_config(int vreg_en)
+{
+ int rc;
+
+ if (vreg_gp1 == NULL) {
+ vreg_gp1 = vreg_get(NULL, "msme1");
+ if (IS_ERR(vreg_gp1)) {
+ pr_err("%s: vreg_get(%s) failed (%ld)\n",
+ __func__, "msme1", PTR_ERR(vreg_gp1));
+ return;
+ }
+
+ rc = vreg_set_level(vreg_gp1, 1800);
+ if (rc) {
+ pr_err("%s: GP1 set_level failed (%d)\n",
+ __func__, rc);
+ return;
+ }
+ }
+
+ if (vreg_gp2 == NULL) {
+ vreg_gp2 = vreg_get(NULL, "gp2");
+ if (IS_ERR(vreg_gp2)) {
+ pr_err("%s: vreg_get(%s) failed (%ld)\n",
+ __func__, "gp2", PTR_ERR(vreg_gp2));
+ return;
+ }
+
+ rc = vreg_set_level(vreg_gp2, 2850);
+ if (rc) {
+ pr_err("%s: GP2 set_level failed (%d)\n",
+ __func__, rc);
+ }
+ }
+
+ if (vreg_gp3 == NULL) {
+ vreg_gp3 = vreg_get(NULL, "usb2");
+ if (IS_ERR(vreg_gp3)) {
+ pr_err("%s: vreg_get(%s) failed (%ld)\n",
+ __func__, "gp3", PTR_ERR(vreg_gp3));
+ return;
+ }
+
+ rc = vreg_set_level(vreg_gp3, 1800);
+ if (rc) {
+ pr_err("%s: GP3 set level failed (%d)\n",
+ __func__, rc);
+ }
+ }
+
+ if (vreg_en) {
+ rc = vreg_enable(vreg_gp1);
+ if (rc) {
+ pr_err("%s: GP1 enable failed (%d)\n",
+ __func__, rc);
+ return;
+ }
+
+ rc = vreg_enable(vreg_gp2);
+ if (rc) {
+ pr_err("%s: GP2 enable failed (%d)\n",
+ __func__, rc);
+ }
+
+ rc = vreg_enable(vreg_gp3);
+ if (rc) {
+ pr_err("%s: GP3 enable failed (%d)\n",
+ __func__, rc);
+ }
+ } else {
+ rc = vreg_disable(vreg_gp1);
+ if (rc)
+ pr_err("%s: GP1 disable failed (%d)\n",
+ __func__, rc);
+
+ rc = vreg_disable(vreg_gp2);
+ if (rc) {
+ pr_err("%s: GP2 disable failed (%d)\n",
+ __func__, rc);
+ }
+
+ rc = vreg_disable(vreg_gp3);
+ if (rc) {
+ pr_err("%s: GP3 disable failed (%d)\n",
+ __func__, rc);
+ }
+ }
+}
+
+static int config_gpio_table(uint32_t *table, int len)
+{
+ int rc = 0, i = 0;
+
+ for (i = 0; i < len; i++) {
+ rc = gpio_tlmm_config(table[i], GPIO_CFG_ENABLE);
+ if (rc) {
+ pr_err("%s not able to get gpio\n", __func__);
+ for (i--; i >= 0; i--)
+ gpio_tlmm_config(camera_off_gpio_table[i],
+ GPIO_CFG_ENABLE);
+ break;
+ }
+ }
+ return rc;
+}
+
+static int config_camera_on_gpios_rear(void)
+{
+ int rc = 0;
+
+ msm_camera_vreg_config(1);
+
+ rc = config_gpio_table(camera_on_gpio_table,
+ ARRAY_SIZE(camera_on_gpio_table));
+ if (rc < 0) {
+ pr_err("%s: CAMSENSOR gpio table request"
+ "failed\n", __func__);
+ return rc;
+ }
+
+ return rc;
+}
+
+static void config_camera_off_gpios_rear(void)
+{
+ msm_camera_vreg_config(0);
+ config_gpio_table(camera_off_gpio_table,
+ ARRAY_SIZE(camera_off_gpio_table));
+}
+
+static int config_camera_on_gpios_front(void)
+{
+ int rc = 0;
+
+ msm_camera_vreg_config(1);
+
+ rc = config_gpio_table(camera_on_gpio_table,
+ ARRAY_SIZE(camera_on_gpio_table));
+ if (rc < 0) {
+ pr_err("%s: CAMSENSOR gpio table request"
+ "failed\n", __func__);
+ return rc;
+ }
+
+ return rc;
+}
+
+static void config_camera_off_gpios_front(void)
+{
+ msm_camera_vreg_config(0);
+
+ config_gpio_table(camera_off_gpio_table,
+ ARRAY_SIZE(camera_off_gpio_table));
+}
+
+struct msm_camera_device_platform_data msm_camera_data_rear = {
+ .camera_gpio_on = config_camera_on_gpios_rear,
+ .camera_gpio_off = config_camera_off_gpios_rear,
+ .ioext.csiphy = 0xA1000000,
+ .ioext.csisz = 0x00100000,
+ .ioext.csiirq = INT_CSI_IRQ_1,
+ .ioclk.mclk_clk_rate = 24000000,
+ .ioclk.vfe_clk_rate = 192000000,
+ .ioext.appphy = MSM_CLK_CTL_PHYS,
+ .ioext.appsz = MSM_CLK_CTL_SIZE,
+};
+
+struct msm_camera_device_platform_data msm_camera_data_front = {
+ .camera_gpio_on = config_camera_on_gpios_front,
+ .camera_gpio_off = config_camera_off_gpios_front,
+ .ioext.csiphy = 0xA0F00000,
+ .ioext.csisz = 0x00100000,
+ .ioext.csiirq = INT_CSI_IRQ_0,
+ .ioclk.mclk_clk_rate = 24000000,
+ .ioclk.vfe_clk_rate = 192000000,
+ .ioext.appphy = MSM_CLK_CTL_PHYS,
+ .ioext.appsz = MSM_CLK_CTL_SIZE,
+};
+
+#ifdef CONFIG_OV5640
+static struct msm_camera_sensor_platform_info ov5640_sensor_info = {
+ .mount_angle = 90
+};
+
+static struct msm_camera_sensor_flash_src msm_flash_src_ov5640 = {
+ .flash_sr_type = MSM_CAMERA_FLASH_SRC_LED,
+ ._fsrc.led_src.led_name = "flashlight",
+ ._fsrc.led_src.led_name_len = 10,
+};
+
+static struct msm_camera_sensor_flash_data flash_ov5640 = {
+ .flash_type = MSM_CAMERA_FLASH_LED,
+ .flash_src = &msm_flash_src_ov5640,
+};
+
+static struct msm_camera_sensor_info msm_camera_sensor_ov5640_data = {
+ .sensor_name = "ov5640",
+ .sensor_reset_enable = 1,
+ .sensor_reset = GPIO_CAM_5MP_RESET,
+ .sensor_pwd = GPIO_CAM_5MP_SHDN_EN,
+ .vcm_pwd = 0,
+ .vcm_enable = 0,
+ .pdata = &msm_camera_data_rear,
+ .flash_data = &flash_ov5640,
+ .sensor_platform_info = &ov5640_sensor_info,
+ .csi_if = 1,
+};
+
+static struct platform_device msm_camera_sensor_ov5640 = {
+ .name = "msm_camera_ov5640",
+ .dev = {
+ .platform_data = &msm_camera_sensor_ov5640_data,
+ },
+};
+#endif
+
+#ifdef CONFIG_WEBCAM_OV7692_QRD
+static struct msm_camera_sensor_platform_info ov7692_sensor_7627a_info = {
+ .mount_angle = 90
+};
+
+static struct msm_camera_sensor_flash_data flash_ov7692 = {
+ .flash_type = MSM_CAMERA_FLASH_NONE,
+};
+
+static struct msm_camera_sensor_info msm_camera_sensor_ov7692_data = {
+ .sensor_name = "ov7692",
+ .sensor_reset_enable = 0,
+ .sensor_reset = 0,
+ .sensor_pwd = GPIO_CAM_3MP_PWDN,
+ .vcm_pwd = 0,
+ .vcm_enable = 0,
+ .pdata = &msm_camera_data_front,
+ .flash_data = &flash_ov7692,
+ .sensor_platform_info = &ov7692_sensor_7627a_info,
+ .csi_if = 1,
+};
+
+static struct platform_device msm_camera_sensor_ov7692 = {
+ .name = "msm_camera_ov7692",
+ .dev = {
+ .platform_data = &msm_camera_sensor_ov7692_data,
+ },
+};
+#endif
+
+static struct i2c_board_info i2c_camera_devices[] = {
+ #ifdef CONFIG_OV5640
+ {
+ I2C_BOARD_INFO("ov5640", 0x78 >> 1),
+ },
+ #endif
+ #ifdef CONFIG_WEBCAM_OV7692_QRD
+ {
+ I2C_BOARD_INFO("ov7692", 0x78),
+ },
+ #endif
+};
static struct platform_device *qrd1_devices[] __initdata = {
&msm_device_dmov,
&msm_device_smd,
@@ -1889,6 +2220,12 @@
&msm_device_snd,
&msm_device_adspdec,
&msm_batt_device,
+#ifdef CONFIG_OV5640
+ &msm_camera_sensor_ov5640,
+#endif
+#ifdef CONFIG_WEBCAM_OV7692_QRD
+ &msm_camera_sensor_ov7692,
+#endif
&msm_kgsl_3d0,
#ifdef CONFIG_BT
&msm_bt_power_device,
@@ -2166,6 +2503,7 @@
msm_device_i2c_init();
msm7627a_init_mmc();
+ qrd1_camera_gpio_cfg();
#ifdef CONFIG_SERIAL_MSM_HS
msm_uart_dm1_pdata.wakeup_irq = gpio_to_irq(UART1DM_RX_GPIO);
msm_device_uart_dm1.dev.platform_data = &msm_uart_dm1_pdata;
@@ -2177,9 +2515,9 @@
msm_device_otg.dev.platform_data = &msm_otg_pdata;
#endif
msm_device_gadget_peripheral.dev.platform_data =
- &msm_gadget_pdata;
+ &msm_gadget_pdata;
platform_add_devices(qrd1_devices,
- ARRAY_SIZE(qrd1_devices));
+ ARRAY_SIZE(qrd1_devices));
#ifdef CONFIG_USB_EHCI_MSM_72K
msm7627a_init_host();
#endif
@@ -2189,18 +2527,20 @@
#if defined(CONFIG_BT) && defined(CONFIG_MARIMBA_CORE)
i2c_register_board_info(MSM_GSBI1_QUP_I2C_BUS_ID,
- bahama_devices,
- ARRAY_SIZE(bahama_devices));
+ bahama_devices,
+ ARRAY_SIZE(bahama_devices));
bt_power_init();
#endif
+ i2c_register_board_info(MSM_GSBI0_QUP_I2C_BUS_ID, i2c_camera_devices,
+ ARRAY_SIZE(i2c_camera_devices));
+
#if defined(CONFIG_TOUCHSCREEN_SYNAPTICS_RMI4_I2C) || \
defined(CONFIG_TOUCHSCREEN_SYNAPTICS_RMI4_I2C_MODULE)
i2c_register_board_info(MSM_GSBI1_QUP_I2C_BUS_ID,
synaptic_i2c_clearpad3k,
ARRAY_SIZE(synaptic_i2c_clearpad3k));
#endif
-
platform_device_register(&hs_pdev);
#ifdef CONFIG_MSM_RPC_VIBRATOR
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c
index b7f6608..0dcd0f4 100644
--- a/arch/arm/mach-msm/board-qsd8x50.c
+++ b/arch/arm/mach-msm/board-qsd8x50.c
@@ -55,6 +55,7 @@
#include "msm-keypad-devices.h"
#include "acpuclock.h"
#include "pm.h"
+#include "pm-boot.h"
#include "proc_comm.h"
#ifdef CONFIG_USB_ANDROID
#include <linux/usb/android_composite.h>
@@ -2436,6 +2437,8 @@
spi_register_board_info(msm_spi_board_info,
ARRAY_SIZE(msm_spi_board_info));
msm_pm_set_platform_data(msm_pm_data, ARRAY_SIZE(msm_pm_data));
+ BUG_ON(msm_pm_boot_init(MSM_PM_BOOT_CONFIG_RESET_VECTOR,
+ (uint32_t *)PAGE_OFFSET));
#ifdef CONFIG_SURF_FFA_GPIO_KEYPAD
if (machine_is_qsd8x50_ffa())
diff --git a/arch/arm/mach-msm/clock-7x30.c b/arch/arm/mach-msm/clock-7x30.c
index e20936f..5df1700 100644
--- a/arch/arm/mach-msm/clock-7x30.c
+++ b/arch/arm/mach-msm/clock-7x30.c
@@ -68,7 +68,6 @@
#define MI2S_NS_REG REG(0x02E0)
#define MI2S_RX_NS_REG REG(0x0070)
#define MI2S_TX_NS_REG REG(0x0078)
-#define MIDI_NS_REG REG(0x02D0)
#define PLL_ENA_REG REG(0x0264)
#define PMDH_NS_REG REG(0x008C)
#define SDAC_NS_REG REG(0x009C)
@@ -137,36 +136,71 @@
/*
* Clock frequency definitions and macros
*/
-#define F_BASIC(f, s, div, v) \
+#define F_BASIC(f, s, div) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = SDIV(SRC_SEL_##s, div), \
- .sys_vdd = v, \
}
-#define F_MND16(f, s, div, m, n, v) \
+#define F_MND16(f, s, div, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD16(m, n), \
.ns_val = N16(m, n) | SPDIV(SRC_SEL_##s, div), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
-#define F_MND8(f, nmsb, nlsb, s, div, m, n, v) \
+#define F_MND8(f, nmsb, nlsb, s, div, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(m, n), \
.ns_val = N8(nmsb, nlsb, m, n) | SPDIV(SRC_SEL_##s, div), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_ops clk_ops_rcg_7x30;
+enum vdd_dig_levels {
+ VDD_DIG_NONE,
+ VDD_DIG_LOW,
+ VDD_DIG_NOMINAL,
+ VDD_DIG_HIGH
+};
+
+static int set_vdd_dig(struct clk_vdd_class *vdd_class, int level)
+{
+ int rc, target_mv;
+
+ static const int mv[] = {
+ [VDD_DIG_NONE] = 1000,
+ [VDD_DIG_LOW] = 1000,
+ [VDD_DIG_NOMINAL] = 1100,
+ [VDD_DIG_HIGH] = 1200
+ };
+
+ target_mv = mv[level];
+ rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_MSMC1, &target_mv, NULL);
+ if (rc)
+ return rc;
+ if (target_mv)
+ rc = -EINVAL;
+
+ return rc;
+}
+
+static DEFINE_VDD_CLASS(vdd_dig, set_vdd_dig);
+
+#define VDD_DIG_FMAX_MAP1(l1, f1) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1)
+#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1), \
+ .fmax[VDD_DIG_##l2] = (f2)
+
#define PCOM_XO_DISABLE 0
#define PCOM_XO_ENABLE 1
#define PCOM_XO_TCXO 0
@@ -290,7 +324,7 @@
static struct clk_ops clk_ops_branch;
static struct clk_freq_tbl clk_tbl_axi[] = {
- F_RAW(1, &lpxo_clk.c, 0, 0, 0, 0, NOMINAL, NULL),
+ F_RAW(1, &lpxo_clk.c, 0, 0, 0, 0, NULL),
F_END,
};
@@ -308,6 +342,7 @@
.c = {
.dbg_name = "glbl_root_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 1),
CLK_INIT(glbl_root_clk.c),
},
};
@@ -948,10 +983,10 @@
};
static struct clk_freq_tbl clk_tbl_csi[] = {
- F_MND8( 0, 0, 0, gnd, 1, 0, 0, NONE),
- F_MND8(153600000, 24, 17, pll1, 2, 2, 5, NOMINAL),
- F_MND8(192000000, 24, 17, pll1, 4, 0, 0, NOMINAL),
- F_MND8(384000000, 24, 17, pll1, 2, 0, 0, NOMINAL),
+ F_MND8( 0, 0, 0, gnd, 1, 0, 0),
+ F_MND8(153600000, 24, 17, pll1, 2, 2, 5),
+ F_MND8(192000000, 24, 17, pll1, 4, 0, 0),
+ F_MND8(384000000, 24, 17, pll1, 2, 0, 0),
F_END,
};
@@ -973,12 +1008,13 @@
.c = {
.dbg_name = "csi0_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 384000000),
CLK_INIT(csi0_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_tcxo[] = {
- F_RAW(19200000, &tcxo_clk.c, 0, 0, 0, 0, NOMINAL, NULL),
+ F_RAW(19200000, &tcxo_clk.c, 0, 0, 0, 0, NULL),
F_END,
};
@@ -997,6 +1033,7 @@
.c = {
.dbg_name = "i2c_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 19200000),
CLK_INIT(i2c_clk.c),
},
};
@@ -1016,6 +1053,7 @@
.c = {
.dbg_name = "i2c_2_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 19200000),
CLK_INIT(i2c_2_clk.c),
},
};
@@ -1035,6 +1073,7 @@
.c = {
.dbg_name = "qup_i2c_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 19200000),
CLK_INIT(qup_i2c_clk.c),
},
};
@@ -1054,6 +1093,7 @@
.c = {
.dbg_name = "uart1_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 19200000),
CLK_INIT(uart1_clk.c),
},
};
@@ -1073,23 +1113,24 @@
.c = {
.dbg_name = "uart2_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 19200000),
CLK_INIT(uart2_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_uartdm[] = {
- F_MND16( 0, gnd, 1, 0, 0, NONE),
- F_MND16( 3686400, pll3, 3, 3, 200, NOMINAL),
- F_MND16( 7372800, pll3, 3, 3, 100, NOMINAL),
- F_MND16(14745600, pll3, 3, 3, 50, NOMINAL),
- F_MND16(32000000, pll3, 3, 25, 192, NOMINAL),
- F_MND16(40000000, pll3, 3, 125, 768, NOMINAL),
- F_MND16(46400000, pll3, 3, 145, 768, NOMINAL),
- F_MND16(48000000, pll3, 3, 25, 128, NOMINAL),
- F_MND16(51200000, pll3, 3, 5, 24, NOMINAL),
- F_MND16(56000000, pll3, 3, 175, 768, NOMINAL),
- F_MND16(58982400, pll3, 3, 6, 25, NOMINAL),
- F_MND16(64000000, pll1, 4, 1, 3, NOMINAL),
+ F_MND16( 0, gnd, 1, 0, 0),
+ F_MND16( 3686400, pll3, 3, 3, 200),
+ F_MND16( 7372800, pll3, 3, 3, 100),
+ F_MND16(14745600, pll3, 3, 3, 50),
+ F_MND16(32000000, pll3, 3, 25, 192),
+ F_MND16(40000000, pll3, 3, 125, 768),
+ F_MND16(46400000, pll3, 3, 145, 768),
+ F_MND16(48000000, pll3, 3, 25, 128),
+ F_MND16(51200000, pll3, 3, 5, 24),
+ F_MND16(56000000, pll3, 3, 175, 768),
+ F_MND16(58982400, pll3, 3, 6, 25),
+ F_MND16(64000000, pll1, 4, 1, 3),
F_END,
};
@@ -1111,6 +1152,7 @@
.c = {
.dbg_name = "uart1dm_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 64000000),
CLK_INIT(uart1dm_clk.c),
},
};
@@ -1133,20 +1175,21 @@
.c = {
.dbg_name = "uart2dm_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 64000000),
CLK_INIT(uart2dm_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_mdh[] = {
- F_BASIC( 0, gnd, 1, NONE),
- F_BASIC( 49150000, pll3, 15, NOMINAL),
- F_BASIC( 92160000, pll3, 8, NOMINAL),
- F_BASIC(122880000, pll3, 6, NOMINAL),
- F_BASIC(184320000, pll3, 4, NOMINAL),
- F_BASIC(245760000, pll3, 3, NOMINAL),
- F_BASIC(368640000, pll3, 2, NOMINAL),
- F_BASIC(384000000, pll1, 2, NOMINAL),
- F_BASIC(445500000, pll4, 2, NOMINAL),
+ F_BASIC( 0, gnd, 1),
+ F_BASIC( 49150000, pll3, 15),
+ F_BASIC( 92160000, pll3, 8),
+ F_BASIC(122880000, pll3, 6),
+ F_BASIC(184320000, pll3, 4),
+ F_BASIC(245760000, pll3, 3),
+ F_BASIC(368640000, pll3, 2),
+ F_BASIC(384000000, pll1, 2),
+ F_BASIC(445500000, pll4, 2),
F_END,
};
@@ -1166,6 +1209,7 @@
.dbg_name = "emdh_clk",
.flags = CLKFLAG_MIN | CLKFLAG_MAX,
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 445500000),
CLK_INIT(emdh_clk.c),
.depends = &axi_li_adsp_a_clk.c,
},
@@ -1187,30 +1231,31 @@
.dbg_name = "pmdh_clk",
.flags = CLKFLAG_MIN | CLKFLAG_MAX,
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 445500000),
CLK_INIT(pmdh_clk.c),
.depends = &axi_li_adsp_a_clk.c,
},
};
static struct clk_freq_tbl clk_tbl_grp[] = {
- F_BASIC( 24576000, lpxo, 1, NOMINAL),
- F_BASIC( 46080000, pll3, 16, NOMINAL),
- F_BASIC( 49152000, pll3, 15, NOMINAL),
- F_BASIC( 52662875, pll3, 14, NOMINAL),
- F_BASIC( 56713846, pll3, 13, NOMINAL),
- F_BASIC( 61440000, pll3, 12, NOMINAL),
- F_BASIC( 67025454, pll3, 11, NOMINAL),
- F_BASIC( 73728000, pll3, 10, NOMINAL),
- F_BASIC( 81920000, pll3, 9, NOMINAL),
- F_BASIC( 92160000, pll3, 8, NOMINAL),
- F_BASIC(105325714, pll3, 7, NOMINAL),
- F_BASIC(122880000, pll3, 6, NOMINAL),
- F_BASIC(147456000, pll3, 5, NOMINAL),
- F_BASIC(184320000, pll3, 4, NOMINAL),
- F_BASIC(192000000, pll1, 4, NOMINAL),
- F_BASIC(245760000, pll3, 3, HIGH),
+ F_BASIC( 24576000, lpxo, 1),
+ F_BASIC( 46080000, pll3, 16),
+ F_BASIC( 49152000, pll3, 15),
+ F_BASIC( 52662875, pll3, 14),
+ F_BASIC( 56713846, pll3, 13),
+ F_BASIC( 61440000, pll3, 12),
+ F_BASIC( 67025454, pll3, 11),
+ F_BASIC( 73728000, pll3, 10),
+ F_BASIC( 81920000, pll3, 9),
+ F_BASIC( 92160000, pll3, 8),
+ F_BASIC(105325714, pll3, 7),
+ F_BASIC(122880000, pll3, 6),
+ F_BASIC(147456000, pll3, 5),
+ F_BASIC(184320000, pll3, 4),
+ F_BASIC(192000000, pll1, 4),
+ F_BASIC(245760000, pll3, 3),
/* Sync to AXI. Hence this "rate" is not fixed. */
- F_RAW(1, &lpxo_clk.c, 0, BIT(14), 0, 0, NOMINAL, NULL),
+ F_RAW(1, &lpxo_clk.c, 0, BIT(14), 0, 0, NULL),
F_END,
};
@@ -1231,6 +1276,7 @@
.c = {
.dbg_name = "grp_2d_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP2(NOMINAL, 192000000, HIGH, 245760000),
CLK_INIT(grp_2d_clk.c),
.depends = &axi_grp_2d_clk.c,
},
@@ -1250,6 +1296,7 @@
.c = {
.dbg_name = "grp_3d_src_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP2(NOMINAL, 192000000, HIGH, 245760000),
CLK_INIT(grp_3d_src_clk.c),
.depends = &axi_li_grp_clk.c,
},
@@ -1288,14 +1335,14 @@
};
static struct clk_freq_tbl clk_tbl_sdc1_3[] = {
- F_MND8( 0, 0, 0, gnd, 1, 0, 0, NONE),
- F_MND8( 144000, 19, 12, lpxo, 1, 1, 171, NOMINAL),
- F_MND8( 400000, 19, 12, lpxo, 1, 2, 123, NOMINAL),
- F_MND8(16027000, 19, 12, pll3, 3, 14, 215, NOMINAL),
- F_MND8(17000000, 19, 12, pll3, 4, 19, 206, NOMINAL),
- F_MND8(20480000, 19, 12, pll3, 4, 23, 212, NOMINAL),
- F_MND8(24576000, 19, 12, lpxo, 1, 0, 0, NOMINAL),
- F_MND8(49152000, 19, 12, pll3, 3, 1, 5, NOMINAL),
+ F_MND8( 0, 0, 0, gnd, 1, 0, 0),
+ F_MND8( 144000, 19, 12, lpxo, 1, 1, 171),
+ F_MND8( 400000, 19, 12, lpxo, 1, 2, 123),
+ F_MND8(16027000, 19, 12, pll3, 3, 14, 215),
+ F_MND8(17000000, 19, 12, pll3, 4, 19, 206),
+ F_MND8(20480000, 19, 12, pll3, 4, 23, 212),
+ F_MND8(24576000, 19, 12, lpxo, 1, 0, 0),
+ F_MND8(49152000, 19, 12, pll3, 3, 1, 5),
F_END,
};
@@ -1317,6 +1364,7 @@
.c = {
.dbg_name = "sdc1_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 49152000),
CLK_INIT(sdc1_clk.c),
},
};
@@ -1339,19 +1387,20 @@
.c = {
.dbg_name = "sdc3_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 49152000),
CLK_INIT(sdc3_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_sdc2_4[] = {
- F_MND8( 0, 0, 0, gnd, 1, 0, 0, NONE),
- F_MND8( 144000, 20, 13, lpxo, 1, 1, 171, NOMINAL),
- F_MND8( 400000, 20, 13, lpxo, 1, 2, 123, NOMINAL),
- F_MND8(16027000, 20, 13, pll3, 3, 14, 215, NOMINAL),
- F_MND8(17000000, 20, 13, pll3, 4, 19, 206, NOMINAL),
- F_MND8(20480000, 20, 13, pll3, 4, 23, 212, NOMINAL),
- F_MND8(24576000, 20, 13, lpxo, 1, 0, 0, NOMINAL),
- F_MND8(49152000, 20, 13, pll3, 3, 1, 5, NOMINAL),
+ F_MND8( 0, 0, 0, gnd, 1, 0, 0),
+ F_MND8( 144000, 20, 13, lpxo, 1, 1, 171),
+ F_MND8( 400000, 20, 13, lpxo, 1, 2, 123),
+ F_MND8(16027000, 20, 13, pll3, 3, 14, 215),
+ F_MND8(17000000, 20, 13, pll3, 4, 19, 206),
+ F_MND8(20480000, 20, 13, pll3, 4, 23, 212),
+ F_MND8(24576000, 20, 13, lpxo, 1, 0, 0),
+ F_MND8(49152000, 20, 13, pll3, 3, 1, 5),
F_END,
};
@@ -1373,6 +1422,7 @@
.c = {
.dbg_name = "sdc2_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 49152000),
CLK_INIT(sdc2_clk.c),
},
};
@@ -1395,20 +1445,21 @@
.c = {
.dbg_name = "sdc4_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 49152000),
CLK_INIT(sdc4_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_mdp_core[] = {
- F_BASIC( 24576000, lpxo, 1, NOMINAL),
- F_BASIC( 46080000, pll3, 16, NOMINAL),
- F_BASIC( 49152000, pll3, 15, NOMINAL),
- F_BASIC( 52663000, pll3, 14, NOMINAL),
- F_BASIC( 92160000, pll3, 8, NOMINAL),
- F_BASIC(122880000, pll3, 6, NOMINAL),
- F_BASIC(147456000, pll3, 5, NOMINAL),
- F_BASIC(153600000, pll1, 5, NOMINAL),
- F_BASIC(192000000, pll1, 4, HIGH),
+ F_BASIC( 24576000, lpxo, 1),
+ F_BASIC( 46080000, pll3, 16),
+ F_BASIC( 49152000, pll3, 15),
+ F_BASIC( 52663000, pll3, 14),
+ F_BASIC( 92160000, pll3, 8),
+ F_BASIC(122880000, pll3, 6),
+ F_BASIC(147456000, pll3, 5),
+ F_BASIC(153600000, pll1, 5),
+ F_BASIC(192000000, pll1, 4),
F_END,
};
@@ -1429,18 +1480,19 @@
.c = {
.dbg_name = "mdp_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP2(NOMINAL, 153600000, HIGH, 192000000),
CLK_INIT(mdp_clk.c),
.depends = &axi_mdp_clk.c,
},
};
static struct clk_freq_tbl clk_tbl_mdp_lcdc[] = {
- F_MND16( 0, gnd, 1, 0, 0, NONE),
- F_MND16(24576000, lpxo, 1, 0, 0, NOMINAL),
- F_MND16(30720000, pll3, 4, 1, 6, NOMINAL),
- F_MND16(32768000, pll3, 3, 2, 15, NOMINAL),
- F_MND16(40960000, pll3, 2, 1, 9, NOMINAL),
- F_MND16(73728000, pll3, 2, 1, 5, NOMINAL),
+ F_MND16( 0, gnd, 1, 0, 0),
+ F_MND16(24576000, lpxo, 1, 0, 0),
+ F_MND16(30720000, pll3, 4, 1, 6),
+ F_MND16(32768000, pll3, 3, 2, 15),
+ F_MND16(40960000, pll3, 2, 1, 9),
+ F_MND16(73728000, pll3, 2, 1, 5),
F_END,
};
@@ -1462,6 +1514,7 @@
.c = {
.dbg_name = "mdp_lcdc_pclk_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 73728000),
CLK_INIT(mdp_lcdc_pclk_clk.c),
},
};
@@ -1483,8 +1536,8 @@
};
static struct clk_freq_tbl clk_tbl_mdp_vsync[] = {
- F_RAW( 0, &gnd_clk.c, 0, (0x3<<2), 0, 0, NONE, NULL),
- F_RAW(24576000, &lpxo_clk.c, 0, (0x1<<2), 0, 0, NOMINAL, NULL),
+ F_RAW( 0, &gnd_clk.c, 0, (0x3<<2), 0, 0, NULL),
+ F_RAW(24576000, &lpxo_clk.c, 0, (0x1<<2), 0, 0, NULL),
F_END,
};
@@ -1504,14 +1557,15 @@
.c = {
.dbg_name = "mdp_vsync_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 24576000),
CLK_INIT(mdp_vsync_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_mi2s_codec[] = {
- F_MND16( 0, gnd, 1, 0, 0, NONE),
- F_MND16( 2048000, lpxo, 4, 1, 3, NOMINAL),
- F_MND16(12288000, lpxo, 2, 0, 0, NOMINAL),
+ F_MND16( 0, gnd, 1, 0, 0),
+ F_MND16( 2048000, lpxo, 4, 1, 3),
+ F_MND16(12288000, lpxo, 2, 0, 0),
F_END,
};
@@ -1533,6 +1587,7 @@
.c = {
.dbg_name = "mi2s_codec_rx_m_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 12288000),
CLK_INIT(mi2s_codec_rx_m_clk.c),
},
};
@@ -1571,6 +1626,7 @@
.c = {
.dbg_name = "mi2s_codec_tx_m_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 12288000),
CLK_INIT(mi2s_codec_tx_m_clk.c),
},
};
@@ -1592,8 +1648,8 @@
};
static struct clk_freq_tbl clk_tbl_mi2s[] = {
- F_MND16( 0, gnd, 1, 0, 0, NONE),
- F_MND16(12288000, lpxo, 2, 0, 0, NOMINAL),
+ F_MND16( 0, gnd, 1, 0, 0),
+ F_MND16(12288000, lpxo, 2, 0, 0),
F_END,
};
@@ -1615,6 +1671,7 @@
.c = {
.dbg_name = "mi2s_m_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 12288000),
CLK_INIT(mi2s_m_clk.c),
},
};
@@ -1635,53 +1692,25 @@
},
};
-static struct clk_freq_tbl clk_tbl_midi[] = {
- F_MND8( 0, 0, 0, gnd, 1, 0, 0, NONE),
- F_MND8(98304000, 19, 12, pll3, 3, 2, 5, NOMINAL),
- F_END,
-};
-
-static struct rcg_clk midi_clk = {
- .b = {
- .ctl_reg = MIDI_NS_REG,
- .en_mask = BIT(9),
- .halt_reg = CLK_HALT_STATEC_REG,
- .halt_bit = 1,
- },
- .ns_reg = MIDI_NS_REG,
- .md_reg = MIDI_NS_REG - 4,
- .ns_mask = F_MASK_MND8(19, 12),
- .root_en_mask = BIT(11),
- .freq_tbl = clk_tbl_midi,
- .current_freq = &rcg_dummy_freq,
- .set_rate = set_rate_mnd,
- .c = {
- .dbg_name = "midi_clk",
- .ops = &clk_ops_rcg_7x30,
- CLK_INIT(midi_clk.c),
- },
-};
-
-#define F_SDAC(f, s, div, m, n, v) \
+#define F_SDAC(f, s, div, m, n) \
{ \
.freq_hz = f, \
.md_val = MD16(m, n), \
.ns_val = N16(m, n) | SPDIV(SRC_SEL_SDAC_##s, div), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
.src_clk = &s##_clk.c, \
}
static struct clk_freq_tbl clk_tbl_sdac[] = {
- F_SDAC( 256000, lpxo, 4, 1, 24, NOMINAL),
- F_SDAC( 352800, lpxo, 1, 147, 10240, NOMINAL),
- F_SDAC( 384000, lpxo, 4, 1, 16, NOMINAL),
- F_SDAC( 512000, lpxo, 4, 1, 12, NOMINAL),
- F_SDAC( 705600, lpxo, 1, 147, 5120, NOMINAL),
- F_SDAC( 768000, lpxo, 4, 1, 8, NOMINAL),
- F_SDAC(1024000, lpxo, 4, 1, 6, NOMINAL),
- F_SDAC(1411200, lpxo, 1, 147, 2560, NOMINAL),
- F_SDAC(1536000, lpxo, 4, 1, 4, NOMINAL),
+ F_SDAC( 256000, lpxo, 4, 1, 24),
+ F_SDAC( 352800, lpxo, 1, 147, 10240),
+ F_SDAC( 384000, lpxo, 4, 1, 16),
+ F_SDAC( 512000, lpxo, 4, 1, 12),
+ F_SDAC( 705600, lpxo, 1, 147, 5120),
+ F_SDAC( 768000, lpxo, 4, 1, 8),
+ F_SDAC(1024000, lpxo, 4, 1, 6),
+ F_SDAC(1411200, lpxo, 1, 147, 2560),
+ F_SDAC(1536000, lpxo, 4, 1, 4),
F_END,
};
@@ -1703,6 +1732,7 @@
.c = {
.dbg_name = "sdac_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 1536000),
CLK_INIT(sdac_clk.c),
},
};
@@ -1724,9 +1754,9 @@
};
static struct clk_freq_tbl clk_tbl_tv[] = {
- F_MND8( 0, 0, 0, gnd, 1, 0, 0, NONE),
- F_MND8(27000000, 23, 16, pll4, 2, 2, 33, NOMINAL),
- F_MND8(74250000, 23, 16, pll4, 2, 1, 6, NOMINAL),
+ F_MND8( 0, 0, 0, gnd, 1, 0, 0),
+ F_MND8(27000000, 23, 16, pll4, 2, 2, 33),
+ F_MND8(74250000, 23, 16, pll4, 2, 1, 6),
F_END,
};
@@ -1745,6 +1775,7 @@
.c = {
.dbg_name = "tv_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 74250000),
CLK_INIT(tv_clk.c),
},
};
@@ -1815,8 +1846,8 @@
};
static struct clk_freq_tbl clk_tbl_usb[] = {
- F_MND8( 0, 0, 0, gnd, 1, 0, 0, NONE),
- F_MND8(60000000, 23, 16, pll1, 2, 5, 32, NOMINAL),
+ F_MND8( 0, 0, 0, gnd, 1, 0, 0),
+ F_MND8(60000000, 23, 16, pll1, 2, 5, 32),
F_END,
};
@@ -1835,6 +1866,7 @@
.c = {
.dbg_name = "usb_hs_src_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 60000000),
CLK_INIT(usb_hs_src_clk.c),
.depends = &axi_li_adsp_a_clk.c,
},
@@ -1936,19 +1968,19 @@
};
static struct clk_freq_tbl clk_tbl_vfe_jpeg[] = {
- F_MND16( 24576000, lpxo, 1, 0, 0, NOMINAL),
- F_MND16( 36864000, pll3, 4, 1, 5, NOMINAL),
- F_MND16( 46080000, pll3, 4, 1, 4, NOMINAL),
- F_MND16( 61440000, pll3, 4, 1, 3, NOMINAL),
- F_MND16( 73728000, pll3, 2, 1, 5, NOMINAL),
- F_MND16( 81920000, pll3, 3, 1, 3, NOMINAL),
- F_MND16( 92160000, pll3, 4, 1, 2, NOMINAL),
- F_MND16( 98304000, pll3, 3, 2, 5, NOMINAL),
- F_MND16(105326000, pll3, 2, 2, 7, NOMINAL),
- F_MND16(122880000, pll3, 2, 1, 3, NOMINAL),
- F_MND16(147456000, pll3, 2, 2, 5, NOMINAL),
- F_MND16(153600000, pll1, 2, 2, 5, NOMINAL),
- F_MND16(192000000, pll1, 4, 0, 0, HIGH),
+ F_MND16( 24576000, lpxo, 1, 0, 0),
+ F_MND16( 36864000, pll3, 4, 1, 5),
+ F_MND16( 46080000, pll3, 4, 1, 4),
+ F_MND16( 61440000, pll3, 4, 1, 3),
+ F_MND16( 73728000, pll3, 2, 1, 5),
+ F_MND16( 81920000, pll3, 3, 1, 3),
+ F_MND16( 92160000, pll3, 4, 1, 2),
+ F_MND16( 98304000, pll3, 3, 2, 5),
+ F_MND16(105326000, pll3, 2, 2, 7),
+ F_MND16(122880000, pll3, 2, 1, 3),
+ F_MND16(147456000, pll3, 2, 2, 5),
+ F_MND16(153600000, pll1, 2, 2, 5),
+ F_MND16(192000000, pll1, 4, 0, 0),
F_END,
};
@@ -1970,6 +2002,7 @@
.c = {
.dbg_name = "jpeg_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP2(NOMINAL, 153600000, HIGH, 192000000),
CLK_INIT(jpeg_clk.c),
.depends = &axi_li_jpeg_clk.c,
},
@@ -1993,6 +2026,7 @@
.c = {
.dbg_name = "vfe_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP2(NOMINAL, 153600000, HIGH, 192000000),
CLK_INIT(vfe_clk.c),
.depends = &axi_li_vfe_clk.c,
},
@@ -2047,16 +2081,16 @@
};
static struct clk_freq_tbl clk_tbl_cam[] = {
- F_MND16( 0, gnd, 1, 0, 0, NONE),
- F_MND16( 6000000, pll1, 4, 1, 32, NOMINAL),
- F_MND16( 8000000, pll1, 4, 1, 24, NOMINAL),
- F_MND16(12000000, pll1, 4, 1, 16, NOMINAL),
- F_MND16(16000000, pll1, 4, 1, 12, NOMINAL),
- F_MND16(19200000, pll1, 4, 1, 10, NOMINAL),
- F_MND16(24000000, pll1, 4, 1, 8, NOMINAL),
- F_MND16(32000000, pll1, 4, 1, 6, NOMINAL),
- F_MND16(48000000, pll1, 4, 1, 4, NOMINAL),
- F_MND16(64000000, pll1, 4, 1, 3, NOMINAL),
+ F_MND16( 0, gnd, 1, 0, 0),
+ F_MND16( 6000000, pll1, 4, 1, 32),
+ F_MND16( 8000000, pll1, 4, 1, 24),
+ F_MND16(12000000, pll1, 4, 1, 16),
+ F_MND16(16000000, pll1, 4, 1, 12),
+ F_MND16(19200000, pll1, 4, 1, 10),
+ F_MND16(24000000, pll1, 4, 1, 8),
+ F_MND16(32000000, pll1, 4, 1, 6),
+ F_MND16(48000000, pll1, 4, 1, 4),
+ F_MND16(64000000, pll1, 4, 1, 3),
F_END,
};
@@ -2076,18 +2110,19 @@
.c = {
.dbg_name = "cam_m_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 64000000),
CLK_INIT(cam_m_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_vpe[] = {
- F_MND8( 24576000, 22, 15, lpxo, 1, 0, 0, NOMINAL),
- F_MND8( 30720000, 22, 15, pll3, 4, 1, 6, NOMINAL),
- F_MND8( 61440000, 22, 15, pll3, 4, 1, 3, NOMINAL),
- F_MND8( 81920000, 22, 15, pll3, 3, 1, 3, NOMINAL),
- F_MND8(122880000, 22, 15, pll3, 3, 1, 2, NOMINAL),
- F_MND8(147456000, 22, 15, pll3, 1, 1, 5, NOMINAL),
- F_MND8(153600000, 22, 15, pll1, 1, 1, 5, NOMINAL),
+ F_MND8( 24576000, 22, 15, lpxo, 1, 0, 0),
+ F_MND8( 30720000, 22, 15, pll3, 4, 1, 6),
+ F_MND8( 61440000, 22, 15, pll3, 4, 1, 3),
+ F_MND8( 81920000, 22, 15, pll3, 3, 1, 3),
+ F_MND8(122880000, 22, 15, pll3, 3, 1, 2),
+ F_MND8(147456000, 22, 15, pll3, 1, 1, 5),
+ F_MND8(153600000, 22, 15, pll1, 1, 1, 5),
F_END,
};
@@ -2109,21 +2144,21 @@
.c = {
.dbg_name = "vpe_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 153600000),
CLK_INIT(vpe_clk.c),
.depends = &axi_vpe_clk.c,
},
};
-
static struct clk_freq_tbl clk_tbl_mfc[] = {
- F_MND8( 24576000, 24, 17, lpxo, 1, 0, 0, NOMINAL),
- F_MND8( 30720000, 24, 17, pll3, 4, 1, 6, NOMINAL),
- F_MND8( 61440000, 24, 17, pll3, 4, 1, 3, NOMINAL),
- F_MND8( 81920000, 24, 17, pll3, 3, 1, 3, NOMINAL),
- F_MND8(122880000, 24, 17, pll3, 3, 1, 2, NOMINAL),
- F_MND8(147456000, 24, 17, pll3, 1, 1, 5, NOMINAL),
- F_MND8(153600000, 24, 17, pll1, 1, 1, 5, NOMINAL),
- F_MND8(170667000, 24, 17, pll1, 1, 2, 9, NOMINAL),
+ F_MND8( 24576000, 24, 17, lpxo, 1, 0, 0),
+ F_MND8( 30720000, 24, 17, pll3, 4, 1, 6),
+ F_MND8( 61440000, 24, 17, pll3, 4, 1, 3),
+ F_MND8( 81920000, 24, 17, pll3, 3, 1, 3),
+ F_MND8(122880000, 24, 17, pll3, 3, 1, 2),
+ F_MND8(147456000, 24, 17, pll3, 1, 1, 5),
+ F_MND8(153600000, 24, 17, pll1, 1, 1, 5),
+ F_MND8(170667000, 24, 17, pll1, 1, 2, 9),
F_END,
};
@@ -2145,6 +2180,7 @@
.c = {
.dbg_name = "mfc_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 170667000),
CLK_INIT(mfc_clk.c),
.depends = &axi_mfc_clk.c,
},
@@ -2167,9 +2203,9 @@
};
static struct clk_freq_tbl clk_tbl_spi[] = {
- F_MND8( 0, 0, 0, gnd, 1, 0, 0, NONE),
- F_MND8( 9963243, 19, 12, pll3, 4, 2, 37, NOMINAL),
- F_MND8(26331429, 19, 12, pll3, 4, 1, 7, NOMINAL),
+ F_MND8( 0, 0, 0, gnd, 1, 0, 0),
+ F_MND8( 9963243, 19, 12, pll3, 4, 2, 37),
+ F_MND8(26331429, 19, 12, pll3, 4, 1, 7),
F_END,
};
@@ -2191,15 +2227,16 @@
.c = {
.dbg_name = "spi_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 26331429),
CLK_INIT(spi_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_lpa_codec[] = {
- F_RAW(1, NULL, 0, 0, 0, 0, LOW, NULL), /* src MI2S_CODEC_RX */
- F_RAW(2, NULL, 0, 1, 0, 0, LOW, NULL), /* src ECODEC_CIF */
- F_RAW(3, NULL, 0, 2, 0, 0, LOW, NULL), /* src MI2S */
- F_RAW(4, NULL, 0, 3, 0, 0, LOW, NULL), /* src SDAC */
+ F_RAW(1, NULL, 0, 0, 0, 0, NULL), /* src MI2S_CODEC_RX */
+ F_RAW(2, NULL, 0, 1, 0, 0, NULL), /* src ECODEC_CIF */
+ F_RAW(3, NULL, 0, 2, 0, 0, NULL), /* src MI2S */
+ F_RAW(4, NULL, 0, 3, 0, 0, NULL), /* src SDAC */
F_END,
};
@@ -2219,12 +2256,13 @@
.c = {
.dbg_name = "lpa_codec_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(LOW, 4),
CLK_INIT(lpa_codec_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_mdc[] = {
- F_RAW(1, NULL, 0, 0, 0, 0, LOW, NULL),
+ F_RAW(1, NULL, 0, 0, 0, 0, NULL),
F_END
};
@@ -2244,6 +2282,7 @@
.c = {
.dbg_name = "mdc_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(LOW, 1),
CLK_INIT(mdc_clk.c),
},
};
@@ -2368,32 +2407,6 @@
static DEFINE_CLK_VOTER(ebi_vfe_clk, &ebi1_fixed_clk.c);
static DEFINE_CLK_VOTER(ebi_adm_clk, &ebi1_fixed_clk.c);
-/*
- * SoC-specific functions required by clock-local driver
- */
-
-/* Update the sys_vdd voltage given a level. */
-static int msm7x30_update_sys_vdd(enum sys_vdd_level level)
-{
- int rc, target_mv;
- static const int mv[NUM_SYS_VDD_LEVELS] = {
- [NONE...LOW] = 1000,
- [NOMINAL] = 1100,
- [HIGH] = 1200,
- };
-
- target_mv = mv[level];
- rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_MSMC1, &target_mv, NULL);
- if (rc)
- goto out;
- if (target_mv) {
- rc = -EINVAL;
- goto out;
- }
-out:
- return rc;
-}
-
#ifdef CONFIG_DEBUG_FS
#define CLK_TEST_2(s) (s)
@@ -2412,7 +2425,6 @@
{ CLK_TEST_2(0x07), &lpa_p_clk.c },
{ CLK_TEST_2(0x08), &usb_hs2_p_clk.c },
{ CLK_TEST_2(0x09), &spi_clk.c },
- { CLK_TEST_2(0x0A), &midi_clk.c },
{ CLK_TEST_2(0x0B), &i2c_2_clk.c },
{ CLK_TEST_2(0x0D), &mi2s_m_clk.c },
{ CLK_TEST_2(0x0E), &lpa_core_clk.c },
@@ -2777,8 +2789,6 @@
OWN(APPS1, 12, "mi2s_codec_rx_s_clk", mi2s_codec_rx_s_clk, NULL),
OWN(APPS1, 14, "mi2s_codec_tx_m_clk", mi2s_codec_tx_m_clk, NULL),
OWN(APPS1, 14, "mi2s_codec_tx_s_clk", mi2s_codec_tx_s_clk, NULL),
- { CLK_LOOKUP("midi_clk", midi_clk.c, NULL),
- O(APPS1), BIT(22) },
OWN(APPS1, 26, "sdac_clk", sdac_clk, NULL),
OWN(APPS1, 26, "sdac_m_clk", sdac_m_clk, NULL),
OWN(APPS1, 8, "vfe_clk", vfe_clk, NULL),
@@ -2863,10 +2873,10 @@
O(GLBL), BIT(13), &dummy_clk },
OWN(GLBL, 8, "core_clk", ce_clk, "qce.0"),
OWN(GLBL, 8, "core_clk", ce_clk, "crypto.0"),
- OWN(GLBL, 13, "rotator_clk", axi_rotator_clk, NULL),
+ OWN(GLBL, 13, "core_clk", axi_rotator_clk, "msm_rotator.0"),
OWN(GLBL, 13, "core_clk", axi_rotator_clk, "footswitch-pcom.6"),
- OWN(GLBL, 13, "rotator_imem_clk", rotator_imem_clk, NULL),
- OWN(GLBL, 13, "rotator_pclk", rotator_p_clk, NULL),
+ OWN(GLBL, 13, "mem_clk", rotator_imem_clk, "msm_rotator.0"),
+ OWN(GLBL, 13, "iface_clk", rotator_p_clk, "msm_rotator.0"),
OWN(GLBL, 13, "iface_clk", rotator_p_clk, "footswitch-pcom.6"),
{ CLK_LOOKUP("iface_clk", uart1dm_p_clk.c, "msm_serial_hs.0"),
O(GLBL), BIT(8), &dummy_clk },
@@ -2947,8 +2957,6 @@
print_ownership();
set_clock_ownership();
- soc_update_sys_vdd = msm7x30_update_sys_vdd;
-
/* When we have no local clock control, the rest of the code in this
* function is a NOP since writes to shadow regions that we don't own
* are ignored. */
@@ -2968,7 +2976,6 @@
clk_set_rate(&uart1_clk.c, 19200000);
clk_set_rate(&uart2_clk.c, 19200000);
clk_set_rate(&mi2s_m_clk.c, 12288000);
- clk_set_rate(&midi_clk.c, 98304000);
clk_set_rate(&mdp_vsync_clk.c, 24576000);
clk_set_rate(&glbl_root_clk.c, 1);
clk_set_rate(&mdc_clk.c, 1);
@@ -2990,7 +2997,7 @@
static struct clk_ops clk_ops_rcg_7x30 = {
.enable = rcg_clk_enable,
.disable = rcg_clk_disable,
- .auto_off = rcg_clk_auto_off,
+ .auto_off = rcg_clk_disable,
.set_rate = rcg_clk_set_rate,
.set_min_rate = rcg_clk_set_min_rate,
.get_rate = rcg_clk_get_rate,
@@ -3006,7 +3013,7 @@
static struct clk_ops clk_ops_branch = {
.enable = branch_clk_enable,
.disable = branch_clk_disable,
- .auto_off = branch_clk_auto_off,
+ .auto_off = branch_clk_disable,
.is_enabled = branch_clk_is_enabled,
.reset = soc_branch_clk_reset,
.set_flags = soc_clk_set_flags,
diff --git a/arch/arm/mach-msm/clock-8960.c b/arch/arm/mach-msm/clock-8960.c
index 0a7f66c..37dabc8 100644
--- a/arch/arm/mach-msm/clock-8960.c
+++ b/arch/arm/mach-msm/clock-8960.c
@@ -426,6 +426,77 @@
};
#define PLL_RATE(l, m, n, v, d, i) { l, m, n, v, (d>>1), i }
+enum vdd_dig_levels {
+ VDD_DIG_NONE,
+ VDD_DIG_LOW,
+ VDD_DIG_NOMINAL,
+ VDD_DIG_HIGH
+};
+
+static int set_vdd_dig(struct clk_vdd_class *vdd_class, int level)
+{
+ static const int vdd_uv[] = {
+ [VDD_DIG_NONE] = 0,
+ [VDD_DIG_LOW] = 945000,
+ [VDD_DIG_NOMINAL] = 1050000,
+ [VDD_DIG_HIGH] = 1150000
+ };
+
+ return rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S3, RPM_VREG_VOTER3,
+ vdd_uv[level], 1150000, 1);
+}
+
+static DEFINE_VDD_CLASS(vdd_dig, set_vdd_dig);
+
+#define VDD_DIG_FMAX_MAP1(l1, f1) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1)
+#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1), \
+ .fmax[VDD_DIG_##l2] = (f2)
+#define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1), \
+ .fmax[VDD_DIG_##l2] = (f2), \
+ .fmax[VDD_DIG_##l3] = (f3)
+
+enum vdd_l23_levels {
+ VDD_L23_OFF,
+ VDD_L23_ON
+};
+
+static int set_vdd_l23(struct clk_vdd_class *vdd_class, int level)
+{
+ int rc;
+
+ if (level == VDD_L23_OFF) {
+ rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_L23,
+ RPM_VREG_VOTER3, 0, 0, 1);
+ if (rc)
+ return rc;
+ rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S8,
+ RPM_VREG_VOTER3, 0, 0, 1);
+ if (rc)
+ rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_L23,
+ RPM_VREG_VOTER3, 1800000, 1800000, 1);
+ } else {
+ rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S8,
+ RPM_VREG_VOTER3, 2200000, 2200000, 1);
+ if (rc)
+ return rc;
+ rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_L23,
+ RPM_VREG_VOTER3, 1800000, 1800000, 1);
+ if (rc)
+ rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S8,
+ RPM_VREG_VOTER3, 0, 0, 1);
+ }
+
+ return rc;
+}
+
+static DEFINE_VDD_CLASS(vdd_l23, set_vdd_l23);
+
/*
* Clock Descriptions
*/
@@ -502,6 +573,8 @@
.c = {
.dbg_name = "pll3_clk",
.ops = &clk_ops_pll,
+ .vdd_class = &vdd_l23,
+ .fmax[VDD_L23_ON] = ULONG_MAX,
CLK_INIT(pll3_clk.c),
},
};
@@ -556,24 +629,6 @@
},
};
-/*
- * SoC-specific functions required by clock-local driver
- */
-
-/* Update the sys_vdd voltage given a level. */
-static int msm8960_update_sys_vdd(enum sys_vdd_level level)
-{
- static const int vdd_uv[] = {
- [NONE] = 0,
- [LOW] = 945000,
- [NOMINAL] = 1050000,
- [HIGH] = 1150000,
- };
-
- return rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S3, RPM_VREG_VOTER3,
- vdd_uv[level], vdd_uv[HIGH], 1);
-}
-
static int soc_clk_reset(struct clk *clk, enum clk_reset_action action)
{
return branch_reset(&to_rcg_clk(clk)->b, action);
@@ -582,7 +637,7 @@
static struct clk_ops clk_ops_rcg_8960 = {
.enable = rcg_clk_enable,
.disable = rcg_clk_disable,
- .auto_off = rcg_clk_auto_off,
+ .auto_off = rcg_clk_disable,
.handoff = rcg_clk_handoff,
.set_rate = rcg_clk_set_rate,
.set_min_rate = rcg_clk_set_min_rate,
@@ -598,7 +653,7 @@
static struct clk_ops clk_ops_branch = {
.enable = branch_clk_enable,
.disable = branch_clk_disable,
- .auto_off = branch_clk_auto_off,
+ .auto_off = branch_clk_disable,
.is_enabled = branch_clk_is_enabled,
.reset = branch_clk_reset,
.is_local = local_clk_is_local,
@@ -1187,34 +1242,34 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8960, \
+ VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 64000000), \
CLK_INIT(i##_clk.c), \
}, \
}
-#define F_GSBI_UART(f, s, d, m, n, v) \
+#define F_GSBI_UART(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD16(m, n), \
.ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gsbi_uart[] = {
- F_GSBI_UART( 0, gnd, 1, 0, 0, NONE),
- F_GSBI_UART( 1843200, pll8, 1, 3, 625, LOW),
- F_GSBI_UART( 3686400, pll8, 1, 6, 625, LOW),
- F_GSBI_UART( 7372800, pll8, 1, 12, 625, LOW),
- F_GSBI_UART(14745600, pll8, 1, 24, 625, LOW),
- F_GSBI_UART(16000000, pll8, 4, 1, 6, LOW),
- F_GSBI_UART(24000000, pll8, 4, 1, 4, LOW),
- F_GSBI_UART(32000000, pll8, 4, 1, 3, LOW),
- F_GSBI_UART(40000000, pll8, 1, 5, 48, NOMINAL),
- F_GSBI_UART(46400000, pll8, 1, 29, 240, NOMINAL),
- F_GSBI_UART(48000000, pll8, 4, 1, 2, NOMINAL),
- F_GSBI_UART(51200000, pll8, 1, 2, 15, NOMINAL),
- F_GSBI_UART(56000000, pll8, 1, 7, 48, NOMINAL),
- F_GSBI_UART(58982400, pll8, 1, 96, 625, NOMINAL),
- F_GSBI_UART(64000000, pll8, 2, 1, 3, NOMINAL),
+ F_GSBI_UART( 0, gnd, 1, 0, 0),
+ F_GSBI_UART( 1843200, pll8, 1, 3, 625),
+ F_GSBI_UART( 3686400, pll8, 1, 6, 625),
+ F_GSBI_UART( 7372800, pll8, 1, 12, 625),
+ F_GSBI_UART(14745600, pll8, 1, 24, 625),
+ F_GSBI_UART(16000000, pll8, 4, 1, 6),
+ F_GSBI_UART(24000000, pll8, 4, 1, 4),
+ F_GSBI_UART(32000000, pll8, 4, 1, 3),
+ F_GSBI_UART(40000000, pll8, 1, 5, 48),
+ F_GSBI_UART(46400000, pll8, 1, 29, 240),
+ F_GSBI_UART(48000000, pll8, 4, 1, 2),
+ F_GSBI_UART(51200000, pll8, 1, 2, 15),
+ F_GSBI_UART(56000000, pll8, 1, 7, 48),
+ F_GSBI_UART(58982400, pll8, 1, 96, 625),
+ F_GSBI_UART(64000000, pll8, 2, 1, 3),
F_END
};
@@ -1251,29 +1306,29 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8960, \
+ VDD_DIG_FMAX_MAP2(LOW, 24000000, NOMINAL, 52000000), \
CLK_INIT(i##_clk.c), \
}, \
}
-#define F_GSBI_QUP(f, s, d, m, n, v) \
+#define F_GSBI_QUP(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(16, m, 0, n), \
.ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gsbi_qup[] = {
- F_GSBI_QUP( 0, gnd, 1, 0, 0, NONE),
- F_GSBI_QUP( 1100000, pxo, 1, 2, 49, LOW),
- F_GSBI_QUP( 5400000, pxo, 1, 1, 5, LOW),
- F_GSBI_QUP(10800000, pxo, 1, 2, 5, LOW),
- F_GSBI_QUP(15060000, pll8, 1, 2, 51, LOW),
- F_GSBI_QUP(24000000, pll8, 4, 1, 4, LOW),
- F_GSBI_QUP(25600000, pll8, 1, 1, 15, NOMINAL),
- F_GSBI_QUP(27000000, pxo, 1, 0, 0, NOMINAL),
- F_GSBI_QUP(48000000, pll8, 4, 1, 2, NOMINAL),
- F_GSBI_QUP(51200000, pll8, 1, 2, 15, NOMINAL),
+ F_GSBI_QUP( 0, gnd, 1, 0, 0),
+ F_GSBI_QUP( 1100000, pxo, 1, 2, 49),
+ F_GSBI_QUP( 5400000, pxo, 1, 1, 5),
+ F_GSBI_QUP(10800000, pxo, 1, 2, 5),
+ F_GSBI_QUP(15060000, pll8, 1, 2, 51),
+ F_GSBI_QUP(24000000, pll8, 4, 1, 4),
+ F_GSBI_QUP(25600000, pll8, 1, 1, 15),
+ F_GSBI_QUP(27000000, pxo, 1, 0, 0),
+ F_GSBI_QUP(48000000, pll8, 4, 1, 2),
+ F_GSBI_QUP(51200000, pll8, 1, 2, 15),
F_END
};
@@ -1290,17 +1345,16 @@
static CLK_GSBI_QUP(gsbi11_qup, 11, CLK_HALT_CFPB_STATEC_REG, 15);
static CLK_GSBI_QUP(gsbi12_qup, 12, CLK_HALT_CFPB_STATEC_REG, 11);
-#define F_QDSS(f, s, d, v) \
+#define F_QDSS(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_DIVSRC(6, 3, d, 2, 0, s##_to_bb_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_qdss[] = {
- F_QDSS( 27000000, pxo, 1, LOW),
- F_QDSS(128000000, pll8, 3, LOW),
- F_QDSS(300000000, pll3, 4, NOMINAL),
+ F_QDSS( 27000000, pxo, 1),
+ F_QDSS(128000000, pll8, 3),
+ F_QDSS(300000000, pll3, 4),
F_END
};
@@ -1416,7 +1470,7 @@
const struct qdss_bank *bank = clk->bank_info;
u32 reg, bank_sel_mask = bank->bank_sel_mask;
- rcg_clk_auto_off(c);
+ rcg_clk_disable(c);
/* Switch to bank 0 */
reg = readl_relaxed(clk->ns_reg);
reg &= ~bank_sel_mask;
@@ -1460,6 +1514,7 @@
.c = {
.dbg_name = "qdss_at_clk",
.ops = &clk_ops_qdss,
+ VDD_DIG_FMAX_MAP2(LOW, 150000000, NOMINAL, 300000000),
CLK_INIT(qdss_at_clk.c),
},
};
@@ -1506,14 +1561,15 @@
.c = {
.dbg_name = "qdss_traceclkin_clk",
.ops = &clk_ops_qdss,
+ VDD_DIG_FMAX_MAP2(LOW, 150000000, NOMINAL, 300000000),
CLK_INIT(qdss_traceclkin_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_qdss_tsctr[] = {
- F_QDSS( 27000000, pxo, 1, LOW),
- F_QDSS(200000000, pll3, 6, LOW),
- F_QDSS(400000000, pll3, 3, NOMINAL),
+ F_QDSS( 27000000, pxo, 1),
+ F_QDSS(200000000, pll3, 6),
+ F_QDSS(400000000, pll3, 3),
F_END
};
@@ -1541,6 +1597,7 @@
.c = {
.dbg_name = "qdss_tsctr_clk",
.ops = &clk_ops_qdss,
+ VDD_DIG_FMAX_MAP2(LOW, 200000000, NOMINAL, 400000000),
CLK_INIT(qdss_tsctr_clk.c),
},
};
@@ -1562,16 +1619,15 @@
},
};
-#define F_PDM(f, s, d, v) \
+#define F_PDM(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_pdm[] = {
- F_PDM( 0, gnd, 1, NONE),
- F_PDM(27000000, pxo, 1, LOW),
+ F_PDM( 0, gnd, 1),
+ F_PDM(27000000, pxo, 1),
F_END
};
@@ -1593,6 +1649,7 @@
.c = {
.dbg_name = "pdm_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP1(LOW, 27000000),
CLK_INIT(pdm_clk.c),
},
};
@@ -1611,14 +1668,13 @@
},
};
-#define F_PRNG(f, s, v) \
+#define F_PRNG(f, s) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_prng[] = {
- F_PRNG(64000000, pll8, NOMINAL),
+ F_PRNG(64000000, pll8),
F_END
};
@@ -1636,11 +1692,12 @@
.c = {
.dbg_name = "prng_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 65000000),
CLK_INIT(prng_clk.c),
},
};
-#define CLK_SDC(name, n, h_b, f_table) \
+#define CLK_SDC(name, n, h_b, fmax_low, fmax_nom) \
struct rcg_clk name = { \
.b = { \
.ctl_reg = SDCn_APPS_CLK_NS_REG(n), \
@@ -1655,85 +1712,54 @@
.root_en_mask = BIT(11), \
.ns_mask = (BM(23, 16) | BM(6, 0)), \
.set_rate = set_rate_mnd, \
- .freq_tbl = f_table, \
+ .freq_tbl = clk_tbl_sdc, \
.current_freq = &rcg_dummy_freq, \
.c = { \
.dbg_name = #name, \
.ops = &clk_ops_rcg_8960, \
+ VDD_DIG_FMAX_MAP2(LOW, fmax_low, NOMINAL, fmax_nom), \
CLK_INIT(name.c), \
}, \
}
-#define F_SDC(f, s, d, m, n, v) \
+#define F_SDC(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(16, m, 0, n), \
.ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
-static struct clk_freq_tbl clk_tbl_sdc1_2[] = {
- F_SDC( 0, gnd, 1, 0, 0, NONE),
- F_SDC( 144000, pxo, 3, 2, 125, LOW),
- F_SDC( 400000, pll8, 4, 1, 240, LOW),
- F_SDC( 16000000, pll8, 4, 1, 6, LOW),
- F_SDC( 17070000, pll8, 1, 2, 45, LOW),
- F_SDC( 20210000, pll8, 1, 1, 19, LOW),
- F_SDC( 24000000, pll8, 4, 1, 4, LOW),
- F_SDC( 48000000, pll8, 4, 1, 2, LOW),
- F_SDC( 64000000, pll8, 3, 1, 2, NOMINAL),
- F_SDC( 96000000, pll8, 4, 0, 0, NOMINAL),
+static struct clk_freq_tbl clk_tbl_sdc[] = {
+ F_SDC( 0, gnd, 1, 0, 0),
+ F_SDC( 144000, pxo, 3, 2, 125),
+ F_SDC( 400000, pll8, 4, 1, 240),
+ F_SDC( 16000000, pll8, 4, 1, 6),
+ F_SDC( 17070000, pll8, 1, 2, 45),
+ F_SDC( 20210000, pll8, 1, 1, 19),
+ F_SDC( 24000000, pll8, 4, 1, 4),
+ F_SDC( 48000000, pll8, 4, 1, 2),
+ F_SDC( 64000000, pll8, 3, 1, 2),
+ F_SDC( 96000000, pll8, 4, 0, 0),
F_END
};
-static CLK_SDC(sdc1_clk, 1, 6, clk_tbl_sdc1_2);
-static CLK_SDC(sdc2_clk, 2, 5, clk_tbl_sdc1_2);
+static CLK_SDC(sdc1_clk, 1, 6, 52000000, 104000000);
+static CLK_SDC(sdc2_clk, 2, 5, 52000000, 104000000);
+static CLK_SDC(sdc3_clk, 3, 4, 104000000, 208000000);
+static CLK_SDC(sdc4_clk, 4, 3, 33000000, 67000000);
+static CLK_SDC(sdc5_clk, 5, 2, 33000000, 67000000);
-static struct clk_freq_tbl clk_tbl_sdc3[] = {
- F_SDC( 0, gnd, 1, 0, 0, NONE),
- F_SDC( 144000, pxo, 3, 2, 125, LOW),
- F_SDC( 400000, pll8, 4, 1, 240, LOW),
- F_SDC( 16000000, pll8, 4, 1, 6, LOW),
- F_SDC( 17070000, pll8, 1, 2, 45, LOW),
- F_SDC( 20210000, pll8, 1, 1, 19, LOW),
- F_SDC( 24000000, pll8, 4, 1, 4, LOW),
- F_SDC( 48000000, pll8, 4, 1, 2, LOW),
- F_SDC( 64000000, pll8, 3, 1, 2, LOW),
- F_SDC( 96000000, pll8, 4, 0, 0, LOW),
- F_SDC(192000000, pll8, 2, 0, 0, NOMINAL),
- F_END
-};
-
-static CLK_SDC(sdc3_clk, 3, 4, clk_tbl_sdc3);
-
-static struct clk_freq_tbl clk_tbl_sdc4_5[] = {
- F_SDC( 0, gnd, 1, 0, 0, NONE),
- F_SDC( 144000, pxo, 3, 2, 125, LOW),
- F_SDC( 400000, pll8, 4, 1, 240, LOW),
- F_SDC( 16000000, pll8, 4, 1, 6, LOW),
- F_SDC( 17070000, pll8, 1, 2, 45, LOW),
- F_SDC( 20210000, pll8, 1, 1, 19, LOW),
- F_SDC( 24000000, pll8, 4, 1, 4, LOW),
- F_SDC( 48000000, pll8, 4, 1, 2, NOMINAL),
- F_SDC( 64000000, pll8, 3, 1, 2, NOMINAL),
- F_END
-};
-
-static CLK_SDC(sdc4_clk, 4, 3, clk_tbl_sdc4_5);
-static CLK_SDC(sdc5_clk, 5, 2, clk_tbl_sdc4_5);
-
-#define F_TSIF_REF(f, s, d, m, n, v) \
+#define F_TSIF_REF(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD16(m, n), \
.ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_tsif_ref[] = {
- F_TSIF_REF( 0, gnd, 1, 0, 0, NONE),
- F_TSIF_REF(105000, pxo, 1, 1, 256, LOW),
+ F_TSIF_REF( 0, gnd, 1, 0, 0),
+ F_TSIF_REF(105000, pxo, 1, 1, 256),
F_END
};
@@ -1754,20 +1780,20 @@
.c = {
.dbg_name = "tsif_ref_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 27000000, NOMINAL, 54000000),
CLK_INIT(tsif_ref_clk.c),
},
};
-#define F_TSSC(f, s, v) \
+#define F_TSSC(f, s) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_tssc[] = {
- F_TSSC( 0, gnd, NONE),
- F_TSSC(27000000, pxo, LOW),
+ F_TSSC( 0, gnd),
+ F_TSSC(27000000, pxo),
F_END
};
@@ -1786,6 +1812,7 @@
.c = {
.dbg_name = "tssc_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP1(LOW, 27000000),
CLK_INIT(tssc_clk.c),
},
};
@@ -1810,22 +1837,22 @@
.c = { \
.dbg_name = #name, \
.ops = &clk_ops_rcg_8960, \
+ VDD_DIG_FMAX_MAP1(NOMINAL, 64000000), \
CLK_INIT(name.c), \
}, \
}
-#define F_USB(f, s, d, m, n, v) \
+#define F_USB(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(16, m, 0, n), \
.ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_usb[] = {
- F_USB( 0, gnd, 1, 0, 0, NONE),
- F_USB(60000000, pll8, 1, 5, 32, NOMINAL),
+ F_USB( 0, gnd, 1, 0, 0),
+ F_USB(60000000, pll8, 1, 5, 32),
F_END
};
@@ -1834,8 +1861,8 @@
CLK_USB_HS(usb_hs4_xcvr_clk, 4, 2);
static struct clk_freq_tbl clk_tbl_usb_hsic[] = {
- F_USB( 0, gnd, 1, 0, 0, NONE),
- F_USB(60000000, pll8, 1, 5, 32, LOW),
+ F_USB( 0, gnd, 1, 0, 0),
+ F_USB(60000000, pll8, 1, 5, 32),
F_END
};
@@ -1856,6 +1883,7 @@
.c = {
.dbg_name = "usb_hsic_xcvr_fs_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP1(LOW, 60000000),
CLK_INIT(usb_hsic_xcvr_fs_clk.c),
},
};
@@ -1877,14 +1905,13 @@
},
};
-#define F_USB_HSIC(f, s, v) \
+#define F_USB_HSIC(f, s) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_usb2_hsic[] = {
- F_USB_HSIC(480000000, pll14, LOW),
+ F_USB_HSIC(480000000, pll14),
F_END
};
@@ -1900,6 +1927,7 @@
.c = {
.dbg_name = "usb_hsic_hsic_src_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP1(LOW, 480000000),
CLK_INIT(usb_hsic_hsic_src_clk.c),
},
};
@@ -1919,14 +1947,13 @@
},
};
-#define F_USB_HSIO_CAL(f, s, v) \
+#define F_USB_HSIO_CAL(f, s) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_usb_hsio_cal[] = {
- F_USB_HSIO_CAL(9000000, pxo, LOW),
+ F_USB_HSIO_CAL(9000000, pxo),
F_END
};
@@ -1943,6 +1970,7 @@
.c = {
.dbg_name = "usb_hsic_hsio_cal_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP1(LOW, 10000000),
CLK_INIT(usb_hsic_hsio_cal_clk.c),
},
};
@@ -1959,7 +1987,7 @@
},
};
-#define CLK_USB_FS(i, n) \
+#define CLK_USB_FS(i, n, fmax_nom) \
struct rcg_clk i##_clk = { \
.ns_reg = USB_FSn_XCVR_FS_CLK_NS_REG(n), \
.b = { \
@@ -1975,11 +2003,12 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8960, \
+ VDD_DIG_FMAX_MAP1(NOMINAL, fmax_nom), \
CLK_INIT(i##_clk.c), \
}, \
}
-static CLK_USB_FS(usb_fs1_src, 1);
+static CLK_USB_FS(usb_fs1_src, 1, 64000000);
static struct branch_clk usb_fs1_xcvr_clk = {
.b = {
.ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(1),
@@ -2014,7 +2043,7 @@
},
};
-static CLK_USB_FS(usb_fs2_src, 2);
+static CLK_USB_FS(usb_fs2_src, 2, 60000000);
static struct branch_clk usb_fs2_xcvr_clk = {
.b = {
.ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(2),
@@ -2078,18 +2107,17 @@
},
};
-#define F_CE3(f, s, d, v) \
+#define F_CE3(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_DIVSRC(6, 3, d, 2, 0, s##_to_bb_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_ce3[] = {
- F_CE3( 0, gnd, 1, NONE),
- F_CE3( 48000000, pll8, 8, LOW),
- F_CE3(100000000, pll3, 12, NOMINAL),
+ F_CE3( 0, gnd, 1),
+ F_CE3( 48000000, pll8, 8),
+ F_CE3(100000000, pll3, 12),
F_END
};
@@ -2107,6 +2135,7 @@
.c = {
.dbg_name = "ce3_src_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000),
CLK_INIT(ce3_src_clk.c),
},
};
@@ -2681,10 +2710,11 @@
.c = { \
.dbg_name = #name, \
.ops = &clk_ops_rcg_8960, \
+ VDD_DIG_FMAX_MAP2(LOW, 64000000, NOMINAL, 128000000), \
CLK_INIT(name.c), \
}, \
}
-#define F_CAM(f, s, d, m, n, v) \
+#define F_CAM(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2692,21 +2722,20 @@
.ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_cam[] = {
- F_CAM( 0, gnd, 1, 0, 0, NONE),
- F_CAM( 6000000, pll8, 4, 1, 16, LOW),
- F_CAM( 8000000, pll8, 4, 1, 12, LOW),
- F_CAM( 12000000, pll8, 4, 1, 8, LOW),
- F_CAM( 16000000, pll8, 4, 1, 6, LOW),
- F_CAM( 19200000, pll8, 4, 1, 5, LOW),
- F_CAM( 24000000, pll8, 4, 1, 4, LOW),
- F_CAM( 32000000, pll8, 4, 1, 3, LOW),
- F_CAM( 48000000, pll8, 4, 1, 2, LOW),
- F_CAM( 64000000, pll8, 3, 1, 2, LOW),
- F_CAM( 96000000, pll8, 4, 0, 0, NOMINAL),
- F_CAM(128000000, pll8, 3, 0, 0, NOMINAL),
+ F_CAM( 0, gnd, 1, 0, 0),
+ F_CAM( 6000000, pll8, 4, 1, 16),
+ F_CAM( 8000000, pll8, 4, 1, 12),
+ F_CAM( 12000000, pll8, 4, 1, 8),
+ F_CAM( 16000000, pll8, 4, 1, 6),
+ F_CAM( 19200000, pll8, 4, 1, 5),
+ F_CAM( 24000000, pll8, 4, 1, 4),
+ F_CAM( 32000000, pll8, 4, 1, 3),
+ F_CAM( 48000000, pll8, 4, 1, 2),
+ F_CAM( 64000000, pll8, 3, 1, 2),
+ F_CAM( 96000000, pll8, 4, 0, 0),
+ F_CAM(128000000, pll8, 3, 0, 0),
F_END
};
@@ -2714,7 +2743,7 @@
static CLK_CAM(cam1_clk, 1, 16);
static CLK_CAM(cam2_clk, 2, 31);
-#define F_CSI(f, s, d, m, n, v) \
+#define F_CSI(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2722,12 +2751,12 @@
.ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_csi[] = {
- F_CSI( 0, gnd, 1, 0, 0, NONE),
- F_CSI( 85330000, pll8, 1, 2, 9, LOW),
- F_CSI(177780000, pll2, 1, 2, 9, NOMINAL),
+ F_CSI( 0, gnd, 1, 0, 0),
+ F_CSI( 27000000, pxo, 1, 0, 0),
+ F_CSI( 85330000, pll8, 1, 2, 9),
+ F_CSI(177780000, pll2, 1, 2, 9),
F_END
};
@@ -2747,6 +2776,7 @@
.c = {
.dbg_name = "csi0_src_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
CLK_INIT(csi0_src_clk.c),
},
};
@@ -2801,6 +2831,7 @@
.c = {
.dbg_name = "csi1_src_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
CLK_INIT(csi1_src_clk.c),
},
};
@@ -2855,6 +2886,7 @@
.c = {
.dbg_name = "csi2_src_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
CLK_INIT(csi2_src_clk.c),
},
};
@@ -2893,37 +2925,166 @@
},
};
-/*
- * The csi pix and csi rdi clocks have two bits in two registers to control a
- * three input mux. So we have the generic rcg_clk_enable() path handle the
- * first bit, and this function handle the second bit.
- */
-static void set_rate_pix_rdi(struct rcg_clk *clk, struct clk_freq_tbl *nf)
-{
- u32 reg = readl_relaxed(MISC_CC3_REG);
- u32 bit = (u32)nf->extra_freq_data;
- if (nf->freq_hz == 2)
- reg |= bit;
- else
- reg &= ~bit;
- writel_relaxed(reg, MISC_CC3_REG);
-}
-
-#define F_CSI_PIX(s) \
- { \
- .src_clk = &csi##s##_clk.c, \
- .freq_hz = s, \
- .ns_val = BVAL(25, 25, s), \
- .extra_freq_data = (void *)BIT(13), \
- }
-static struct clk_freq_tbl clk_tbl_csi_pix[] = {
- F_CSI_PIX(0), /* CSI0 source */
- F_CSI_PIX(1), /* CSI1 source */
- F_CSI_PIX(2), /* CSI2 source */
- F_END
+static struct clk *pix_rdi_mux_map[] = {
+ [0] = &csi0_clk.c,
+ [1] = &csi1_clk.c,
+ [2] = &csi2_clk.c,
+ NULL,
};
-static struct rcg_clk csi_pix_clk = {
+struct pix_rdi_clk {
+ bool enabled;
+ unsigned cur_rate;
+
+ void __iomem *const s_reg;
+ u32 s_mask;
+
+ void __iomem *const s2_reg;
+ u32 s2_mask;
+
+ struct branch b;
+ struct clk c;
+};
+
+static inline struct pix_rdi_clk *to_pix_rdi_clk(struct clk *clk)
+{
+ return container_of(clk, struct pix_rdi_clk, c);
+}
+
+static int pix_rdi_clk_set_rate(struct clk *c, unsigned rate)
+{
+ int ret, i;
+ u32 reg;
+ unsigned long flags;
+ struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
+ struct clk **mux_map = pix_rdi_mux_map;
+
+ /*
+ * These clocks select three inputs via two muxes. One mux selects
+ * between csi0 and csi1 and the second mux selects between that mux's
+ * output and csi2. The source and destination selections for each
+ * mux must be clocking for the switch to succeed so just turn on
+ * all three sources because it's easier than figuring out what source
+ * needs to be on at what time.
+ */
+ for (i = 0; mux_map[i]; i++) {
+ ret = clk_enable(mux_map[i]);
+ if (ret)
+ goto err;
+ }
+ if (rate >= i) {
+ ret = -EINVAL;
+ goto err;
+ }
+ /* Keep the new source on when switching inputs of an enabled clock */
+ if (clk->enabled) {
+ clk_disable(mux_map[clk->cur_rate]);
+ clk_enable(mux_map[rate]);
+ }
+ spin_lock_irqsave(&local_clock_reg_lock, flags);
+ reg = readl_relaxed(clk->s2_reg);
+ reg &= ~clk->s2_mask;
+ reg |= rate == 2 ? clk->s2_mask : 0;
+ writel_relaxed(reg, clk->s2_reg);
+ /*
+ * Wait at least 6 cycles of slowest clock
+ * for the glitch-free MUX to fully switch sources.
+ */
+ mb();
+ udelay(1);
+ reg = readl_relaxed(clk->s_reg);
+ reg &= ~clk->s_mask;
+ reg |= rate == 1 ? clk->s_mask : 0;
+ writel_relaxed(reg, clk->s_reg);
+ /*
+ * Wait at least 6 cycles of slowest clock
+ * for the glitch-free MUX to fully switch sources.
+ */
+ mb();
+ udelay(1);
+ clk->cur_rate = rate;
+ spin_unlock_irqrestore(&local_clock_reg_lock, flags);
+err:
+ for (i--; i >= 0; i--)
+ clk_disable(mux_map[i]);
+
+ return 0;
+}
+
+static unsigned pix_rdi_clk_get_rate(struct clk *c)
+{
+ return to_pix_rdi_clk(c)->cur_rate;
+}
+
+static int pix_rdi_clk_enable(struct clk *c)
+{
+ unsigned long flags;
+ struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
+
+ spin_lock_irqsave(&local_clock_reg_lock, flags);
+ __branch_clk_enable_reg(&clk->b, clk->c.dbg_name);
+ spin_unlock_irqrestore(&local_clock_reg_lock, flags);
+ clk->enabled = true;
+
+ return 0;
+}
+
+static void pix_rdi_clk_disable(struct clk *c)
+{
+ unsigned long flags;
+ struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
+
+ spin_lock_irqsave(&local_clock_reg_lock, flags);
+ __branch_clk_disable_reg(&clk->b, clk->c.dbg_name);
+ spin_unlock_irqrestore(&local_clock_reg_lock, flags);
+ clk->enabled = false;
+}
+
+static int pix_rdi_clk_reset(struct clk *clk, enum clk_reset_action action)
+{
+ return branch_reset(&to_pix_rdi_clk(clk)->b, action);
+}
+
+static struct clk *pix_rdi_clk_get_parent(struct clk *c)
+{
+ struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
+
+ return pix_rdi_mux_map[clk->cur_rate];
+}
+
+static int pix_rdi_clk_list_rate(struct clk *c, unsigned n)
+{
+ if (pix_rdi_mux_map[n])
+ return n;
+ return -ENXIO;
+}
+
+static int pix_rdi_clk_handoff(struct clk *c)
+{
+ u32 reg;
+ struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
+
+ reg = readl_relaxed(clk->s_reg);
+ clk->cur_rate = reg & clk->s_mask ? 1 : 0;
+ reg = readl_relaxed(clk->s2_reg);
+ clk->cur_rate = reg & clk->s2_mask ? 2 : clk->cur_rate;
+ return 0;
+}
+
+static struct clk_ops clk_ops_pix_rdi_8960 = {
+ .enable = pix_rdi_clk_enable,
+ .disable = pix_rdi_clk_disable,
+ .auto_off = pix_rdi_clk_disable,
+ .handoff = pix_rdi_clk_handoff,
+ .set_rate = pix_rdi_clk_set_rate,
+ .get_rate = pix_rdi_clk_get_rate,
+ .list_rate = pix_rdi_clk_list_rate,
+ .reset = pix_rdi_clk_reset,
+ .is_local = local_clk_is_local,
+ .get_parent = pix_rdi_clk_get_parent,
+};
+
+static struct pix_rdi_clk csi_pix_clk = {
.b = {
.ctl_reg = MISC_CC_REG,
.en_mask = BIT(26),
@@ -2931,32 +3092,18 @@
.reset_reg = SW_RESET_CORE_REG,
.reset_mask = BIT(26),
},
- .ns_reg = MISC_CC_REG,
- .ns_mask = BIT(25),
- .set_rate = set_rate_pix_rdi,
- .freq_tbl = clk_tbl_csi_pix,
- .current_freq = &rcg_dummy_freq,
+ .s_reg = MISC_CC_REG,
+ .s_mask = BIT(25),
+ .s2_reg = MISC_CC3_REG,
+ .s2_mask = BIT(13),
.c = {
.dbg_name = "csi_pix_clk",
- .ops = &clk_ops_rcg_8960,
+ .ops = &clk_ops_pix_rdi_8960,
CLK_INIT(csi_pix_clk.c),
},
};
-#define F_CSI_PIX1(s) \
- { \
- .src_clk = &csi##s##_clk.c, \
- .freq_hz = s, \
- .ns_val = BVAL(9, 8, s), \
- }
-static struct clk_freq_tbl clk_tbl_csi_pix1[] = {
- F_CSI_PIX1(0), /* CSI0 source */
- F_CSI_PIX1(1), /* CSI1 source */
- F_CSI_PIX1(2), /* CSI2 source */
- F_END
-};
-
-static struct rcg_clk csi_pix1_clk = {
+static struct pix_rdi_clk csi_pix1_clk = {
.b = {
.ctl_reg = MISC_CC3_REG,
.en_mask = BIT(10),
@@ -2964,33 +3111,18 @@
.reset_reg = SW_RESET_CORE_REG,
.reset_mask = BIT(30),
},
- .ns_reg = MISC_CC3_REG,
- .ns_mask = BM(9, 8),
- .set_rate = set_rate_nop,
- .freq_tbl = clk_tbl_csi_pix1,
- .current_freq = &rcg_dummy_freq,
+ .s_reg = MISC_CC3_REG,
+ .s_mask = BIT(8),
+ .s2_reg = MISC_CC3_REG,
+ .s2_mask = BIT(9),
.c = {
.dbg_name = "csi_pix1_clk",
- .ops = &clk_ops_rcg_8960,
+ .ops = &clk_ops_pix_rdi_8960,
CLK_INIT(csi_pix1_clk.c),
},
};
-#define F_CSI_RDI(s) \
- { \
- .src_clk = &csi##s##_clk.c, \
- .freq_hz = s, \
- .ns_val = BVAL(12, 12, s), \
- .extra_freq_data = (void *)BIT(12), \
- }
-static struct clk_freq_tbl clk_tbl_csi_rdi[] = {
- F_CSI_RDI(0), /* CSI0 source */
- F_CSI_RDI(1), /* CSI1 source */
- F_CSI_RDI(2), /* CSI2 source */
- F_END
-};
-
-static struct rcg_clk csi_rdi_clk = {
+static struct pix_rdi_clk csi_rdi_clk = {
.b = {
.ctl_reg = MISC_CC_REG,
.en_mask = BIT(13),
@@ -2998,32 +3130,18 @@
.reset_reg = SW_RESET_CORE_REG,
.reset_mask = BIT(27),
},
- .ns_reg = MISC_CC_REG,
- .ns_mask = BIT(12),
- .set_rate = set_rate_pix_rdi,
- .freq_tbl = clk_tbl_csi_rdi,
- .current_freq = &rcg_dummy_freq,
+ .s_reg = MISC_CC_REG,
+ .s_mask = BIT(12),
+ .s2_reg = MISC_CC3_REG,
+ .s2_mask = BIT(12),
.c = {
.dbg_name = "csi_rdi_clk",
- .ops = &clk_ops_rcg_8960,
+ .ops = &clk_ops_pix_rdi_8960,
CLK_INIT(csi_rdi_clk.c),
},
};
-#define F_CSI_RDI1(s) \
- { \
- .src_clk = &csi##s##_clk.c, \
- .freq_hz = s, \
- .ns_val = BVAL(1, 0, s), \
- }
-static struct clk_freq_tbl clk_tbl_csi_rdi1[] = {
- F_CSI_RDI1(0), /* CSI0 source */
- F_CSI_RDI1(1), /* CSI1 source */
- F_CSI_RDI1(2), /* CSI2 source */
- F_END
-};
-
-static struct rcg_clk csi_rdi1_clk = {
+static struct pix_rdi_clk csi_rdi1_clk = {
.b = {
.ctl_reg = MISC_CC3_REG,
.en_mask = BIT(2),
@@ -3031,32 +3149,18 @@
.reset_reg = SW_RESET_CORE2_REG,
.reset_mask = BIT(1),
},
- .ns_reg = MISC_CC3_REG,
- .ns_mask = BM(1, 0),
- .set_rate = set_rate_nop,
- .freq_tbl = clk_tbl_csi_rdi1,
- .current_freq = &rcg_dummy_freq,
+ .s_reg = MISC_CC3_REG,
+ .s_mask = BIT(0),
+ .s2_reg = MISC_CC3_REG,
+ .s2_mask = BIT(1),
.c = {
.dbg_name = "csi_rdi1_clk",
- .ops = &clk_ops_rcg_8960,
+ .ops = &clk_ops_pix_rdi_8960,
CLK_INIT(csi_rdi1_clk.c),
},
};
-#define F_CSI_RDI2(s) \
- { \
- .src_clk = &csi##s##_clk.c, \
- .freq_hz = s, \
- .ns_val = BVAL(5, 4, s), \
- }
-static struct clk_freq_tbl clk_tbl_csi_rdi2[] = {
- F_CSI_RDI2(0), /* CSI0 source */
- F_CSI_RDI2(1), /* CSI1 source */
- F_CSI_RDI2(2), /* CSI2 source */
- F_END
-};
-
-static struct rcg_clk csi_rdi2_clk = {
+static struct pix_rdi_clk csi_rdi2_clk = {
.b = {
.ctl_reg = MISC_CC3_REG,
.en_mask = BIT(6),
@@ -3064,19 +3168,18 @@
.reset_reg = SW_RESET_CORE2_REG,
.reset_mask = BIT(0),
},
- .ns_reg = MISC_CC3_REG,
- .ns_mask = BM(5, 4),
- .set_rate = set_rate_nop,
- .freq_tbl = clk_tbl_csi_rdi2,
- .current_freq = &rcg_dummy_freq,
+ .s_reg = MISC_CC3_REG,
+ .s_mask = BIT(4),
+ .s2_reg = MISC_CC3_REG,
+ .s2_mask = BIT(5),
.c = {
.dbg_name = "csi_rdi2_clk",
- .ops = &clk_ops_rcg_8960,
+ .ops = &clk_ops_pix_rdi_8960,
CLK_INIT(csi_rdi2_clk.c),
},
};
-#define F_CSI_PHYTIMER(f, s, d, m, n, v) \
+#define F_CSI_PHYTIMER(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -3084,12 +3187,11 @@
.ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_csi_phytimer[] = {
- F_CSI_PHYTIMER( 0, gnd, 1, 0, 0, NONE),
- F_CSI_PHYTIMER( 85330000, pll8, 1, 2, 9, LOW),
- F_CSI_PHYTIMER(177780000, pll2, 1, 2, 9, NOMINAL),
+ F_CSI_PHYTIMER( 0, gnd, 1, 0, 0),
+ F_CSI_PHYTIMER( 85330000, pll8, 1, 2, 9),
+ F_CSI_PHYTIMER(177780000, pll2, 1, 2, 9),
F_END
};
@@ -3109,6 +3211,7 @@
.c = {
.dbg_name = "csiphy_timer_src_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
CLK_INIT(csiphy_timer_src_clk.c),
},
};
@@ -3261,7 +3364,7 @@
},
};
-#define F_GFX2D(f, s, m, n, v) \
+#define F_GFX2D(f, s, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -3269,22 +3372,21 @@
.ns_val = NS_MND_BANKED4(20, 16, n, m, 3, 0, s##_to_mm_mux), \
.ctl_val = CC_BANKED(9, 6, n), \
.mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gfx2d[] = {
- F_GFX2D( 0, gnd, 0, 0, NONE),
- F_GFX2D( 27000000, pxo, 0, 0, LOW),
- F_GFX2D( 48000000, pll8, 1, 8, LOW),
- F_GFX2D( 54857000, pll8, 1, 7, LOW),
- F_GFX2D( 64000000, pll8, 1, 6, LOW),
- F_GFX2D( 76800000, pll8, 1, 5, LOW),
- F_GFX2D( 96000000, pll8, 1, 4, LOW),
- F_GFX2D(128000000, pll8, 1, 3, NOMINAL),
- F_GFX2D(145455000, pll2, 2, 11, NOMINAL),
- F_GFX2D(160000000, pll2, 1, 5, NOMINAL),
- F_GFX2D(177778000, pll2, 2, 9, NOMINAL),
- F_GFX2D(200000000, pll2, 1, 4, NOMINAL),
- F_GFX2D(228571000, pll2, 2, 7, HIGH),
+ F_GFX2D( 0, gnd, 0, 0),
+ F_GFX2D( 27000000, pxo, 0, 0),
+ F_GFX2D( 48000000, pll8, 1, 8),
+ F_GFX2D( 54857000, pll8, 1, 7),
+ F_GFX2D( 64000000, pll8, 1, 6),
+ F_GFX2D( 76800000, pll8, 1, 5),
+ F_GFX2D( 96000000, pll8, 1, 4),
+ F_GFX2D(128000000, pll8, 1, 3),
+ F_GFX2D(145455000, pll2, 2, 11),
+ F_GFX2D(160000000, pll2, 1, 5),
+ F_GFX2D(177778000, pll2, 2, 9),
+ F_GFX2D(200000000, pll2, 1, 4),
+ F_GFX2D(228571000, pll2, 2, 7),
F_END
};
@@ -3324,6 +3426,8 @@
.c = {
.dbg_name = "gfx2d0_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
+ HIGH, 228571000),
CLK_INIT(gfx2d0_clk.c),
},
};
@@ -3364,11 +3468,13 @@
.c = {
.dbg_name = "gfx2d1_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
+ HIGH, 228571000),
CLK_INIT(gfx2d1_clk.c),
},
};
-#define F_GFX3D(f, s, m, n, v) \
+#define F_GFX3D(f, s, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -3376,69 +3482,80 @@
.ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \
.ctl_val = CC_BANKED(9, 6, n), \
.mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gfx3d_8960[] = {
- F_GFX3D( 0, gnd, 0, 0, NONE),
- F_GFX3D( 27000000, pxo, 0, 0, LOW),
- F_GFX3D( 48000000, pll8, 1, 8, LOW),
- F_GFX3D( 54857000, pll8, 1, 7, LOW),
- F_GFX3D( 64000000, pll8, 1, 6, LOW),
- F_GFX3D( 76800000, pll8, 1, 5, LOW),
- F_GFX3D( 96000000, pll8, 1, 4, LOW),
- F_GFX3D(128000000, pll8, 1, 3, LOW),
- F_GFX3D(145455000, pll2, 2, 11, NOMINAL),
- F_GFX3D(160000000, pll2, 1, 5, NOMINAL),
- F_GFX3D(177778000, pll2, 2, 9, NOMINAL),
- F_GFX3D(200000000, pll2, 1, 4, NOMINAL),
- F_GFX3D(228571000, pll2, 2, 7, NOMINAL),
- F_GFX3D(266667000, pll2, 1, 3, NOMINAL),
- F_GFX3D(320000000, pll2, 2, 5, HIGH),
+ F_GFX3D( 0, gnd, 0, 0),
+ F_GFX3D( 27000000, pxo, 0, 0),
+ F_GFX3D( 48000000, pll8, 1, 8),
+ F_GFX3D( 54857000, pll8, 1, 7),
+ F_GFX3D( 64000000, pll8, 1, 6),
+ F_GFX3D( 76800000, pll8, 1, 5),
+ F_GFX3D( 96000000, pll8, 1, 4),
+ F_GFX3D(128000000, pll8, 1, 3),
+ F_GFX3D(145455000, pll2, 2, 11),
+ F_GFX3D(160000000, pll2, 1, 5),
+ F_GFX3D(177778000, pll2, 2, 9),
+ F_GFX3D(200000000, pll2, 1, 4),
+ F_GFX3D(228571000, pll2, 2, 7),
+ F_GFX3D(266667000, pll2, 1, 3),
+ F_GFX3D(320000000, pll2, 2, 5),
F_END
};
static struct clk_freq_tbl clk_tbl_gfx3d_8960_v2[] = {
- F_GFX3D( 0, gnd, 0, 0, NONE),
- F_GFX3D( 27000000, pxo, 0, 0, LOW),
- F_GFX3D( 48000000, pll8, 1, 8, LOW),
- F_GFX3D( 54857000, pll8, 1, 7, LOW),
- F_GFX3D( 64000000, pll8, 1, 6, LOW),
- F_GFX3D( 76800000, pll8, 1, 5, LOW),
- F_GFX3D( 96000000, pll8, 1, 4, LOW),
- F_GFX3D(128000000, pll8, 1, 3, LOW),
- F_GFX3D(145455000, pll2, 2, 11, NOMINAL),
- F_GFX3D(160000000, pll2, 1, 5, NOMINAL),
- F_GFX3D(177778000, pll2, 2, 9, NOMINAL),
- F_GFX3D(200000000, pll2, 1, 4, NOMINAL),
- F_GFX3D(228571000, pll2, 2, 7, NOMINAL),
- F_GFX3D(266667000, pll2, 1, 3, NOMINAL),
- F_GFX3D(300000000, pll3, 1, 4, NOMINAL),
- F_GFX3D(320000000, pll2, 2, 5, HIGH),
- F_GFX3D(400000000, pll2, 1, 2, HIGH),
+ F_GFX3D( 0, gnd, 0, 0),
+ F_GFX3D( 27000000, pxo, 0, 0),
+ F_GFX3D( 48000000, pll8, 1, 8),
+ F_GFX3D( 54857000, pll8, 1, 7),
+ F_GFX3D( 64000000, pll8, 1, 6),
+ F_GFX3D( 76800000, pll8, 1, 5),
+ F_GFX3D( 96000000, pll8, 1, 4),
+ F_GFX3D(128000000, pll8, 1, 3),
+ F_GFX3D(145455000, pll2, 2, 11),
+ F_GFX3D(160000000, pll2, 1, 5),
+ F_GFX3D(177778000, pll2, 2, 9),
+ F_GFX3D(200000000, pll2, 1, 4),
+ F_GFX3D(228571000, pll2, 2, 7),
+ F_GFX3D(266667000, pll2, 1, 3),
+ F_GFX3D(300000000, pll3, 1, 4),
+ F_GFX3D(320000000, pll2, 2, 5),
+ F_GFX3D(400000000, pll2, 1, 2),
F_END
};
-/* TODO: need to add 325MHz back once it is fixed in the simulation model */
+static unsigned long fmax_gfx3d_8960_v2[MAX_VDD_LEVELS] __initdata = {
+ [VDD_DIG_LOW] = 128000000,
+ [VDD_DIG_NOMINAL] = 300000000,
+ [VDD_DIG_HIGH] = 400000000
+};
+
static struct clk_freq_tbl clk_tbl_gfx3d_8064[] = {
- F_GFX3D( 0, gnd, 0, 0, NONE),
- F_GFX3D( 27000000, pxo, 0, 0, LOW),
- F_GFX3D( 48000000, pll8, 1, 8, LOW),
- F_GFX3D( 54857000, pll8, 1, 7, LOW),
- F_GFX3D( 64000000, pll8, 1, 6, LOW),
- F_GFX3D( 76800000, pll8, 1, 5, LOW),
- F_GFX3D( 96000000, pll8, 1, 4, LOW),
- F_GFX3D(128000000, pll8, 1, 3, LOW),
- F_GFX3D(145455000, pll2, 2, 11, NOMINAL),
- F_GFX3D(160000000, pll2, 1, 5, NOMINAL),
- F_GFX3D(177778000, pll2, 2, 9, NOMINAL),
- F_GFX3D(200000000, pll2, 1, 4, NOMINAL),
- F_GFX3D(228571000, pll2, 2, 7, NOMINAL),
- F_GFX3D(266667000, pll2, 1, 3, NOMINAL),
- F_GFX3D(400000000, pll2, 1, 2, HIGH),
+ F_GFX3D( 0, gnd, 0, 0),
+ F_GFX3D( 27000000, pxo, 0, 0),
+ F_GFX3D( 48000000, pll8, 1, 8),
+ F_GFX3D( 54857000, pll8, 1, 7),
+ F_GFX3D( 64000000, pll8, 1, 6),
+ F_GFX3D( 76800000, pll8, 1, 5),
+ F_GFX3D( 96000000, pll8, 1, 4),
+ F_GFX3D(128000000, pll8, 1, 3),
+ F_GFX3D(145455000, pll2, 2, 11),
+ F_GFX3D(160000000, pll2, 1, 5),
+ F_GFX3D(177778000, pll2, 2, 9),
+ F_GFX3D(200000000, pll2, 1, 4),
+ F_GFX3D(228571000, pll2, 2, 7),
+ F_GFX3D(266667000, pll2, 1, 3),
+ F_GFX3D(325000000, pll15, 1, 3),
+ F_GFX3D(400000000, pll2, 1, 2),
F_END
};
+static unsigned long fmax_gfx3d_8064[MAX_VDD_LEVELS] __initdata = {
+ [VDD_DIG_LOW] = 128000000,
+ [VDD_DIG_NOMINAL] = 325000000,
+ [VDD_DIG_HIGH] = 400000000
+};
+
static struct bank_masks bmnd_info_gfx3d = {
.bank_sel_mask = BIT(11),
.bank0_mask = {
@@ -3475,12 +3592,14 @@
.c = {
.dbg_name = "gfx3d_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP3(LOW, 128000000, NOMINAL, 266667000,
+ HIGH, 320000000),
CLK_INIT(gfx3d_clk.c),
.depends = &gmem_axi_clk.c,
},
};
-#define F_VCAP(f, s, m, n, v) \
+#define F_VCAP(f, s, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -3488,18 +3607,17 @@
.ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \
.ctl_val = CC_BANKED(9, 6, n), \
.mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_vcap[] = {
- F_VCAP( 0, gnd, 0, 0, NONE),
- F_VCAP( 27000000, pxo, 0, 0, LOW),
- F_VCAP( 54860000, pll8, 1, 7, LOW),
- F_VCAP( 64000000, pll8, 1, 6, LOW),
- F_VCAP( 76800000, pll8, 1, 5, LOW),
- F_VCAP(128000000, pll8, 1, 3, NOMINAL),
- F_VCAP(160000000, pll2, 1, 5, NOMINAL),
- F_VCAP(200000000, pll2, 1, 4, NOMINAL),
+ F_VCAP( 0, gnd, 0, 0),
+ F_VCAP( 27000000, pxo, 0, 0),
+ F_VCAP( 54860000, pll8, 1, 7),
+ F_VCAP( 64000000, pll8, 1, 6),
+ F_VCAP( 76800000, pll8, 1, 5),
+ F_VCAP(128000000, pll8, 1, 3),
+ F_VCAP(160000000, pll2, 1, 5),
+ F_VCAP(200000000, pll2, 1, 4),
F_END
};
@@ -3538,6 +3656,7 @@
.dbg_name = "vcap_clk",
.ops = &clk_ops_rcg_8960,
.depends = &vcap_axi_clk.c,
+ VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
CLK_INIT(vcap_clk.c),
},
};
@@ -3557,7 +3676,7 @@
},
};
-#define F_IJPEG(f, s, d, m, n, v) \
+#define F_IJPEG(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -3565,37 +3684,34 @@
.ns_val = NS_MM(23, 16, n, m, 15, 12, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
-static struct clk_freq_tbl clk_tbl_ijpeg_8960[] = {
- F_IJPEG( 0, gnd, 1, 0, 0, NONE),
- F_IJPEG( 27000000, pxo, 1, 0, 0, LOW),
- F_IJPEG( 36570000, pll8, 1, 2, 21, LOW),
- F_IJPEG( 54860000, pll8, 7, 0, 0, LOW),
- F_IJPEG( 96000000, pll8, 4, 0, 0, LOW),
- F_IJPEG(109710000, pll8, 1, 2, 7, LOW),
- F_IJPEG(128000000, pll8, 3, 0, 0, NOMINAL),
- F_IJPEG(153600000, pll8, 1, 2, 5, NOMINAL),
- F_IJPEG(200000000, pll2, 4, 0, 0, NOMINAL),
- F_IJPEG(228571000, pll2, 1, 2, 7, NOMINAL),
- F_IJPEG(266667000, pll2, 1, 1, 3, NOMINAL),
- F_IJPEG(320000000, pll2, 1, 2, 5, HIGH),
+static struct clk_freq_tbl clk_tbl_ijpeg[] = {
+ F_IJPEG( 0, gnd, 1, 0, 0),
+ F_IJPEG( 27000000, pxo, 1, 0, 0),
+ F_IJPEG( 36570000, pll8, 1, 2, 21),
+ F_IJPEG( 54860000, pll8, 7, 0, 0),
+ F_IJPEG( 96000000, pll8, 4, 0, 0),
+ F_IJPEG(109710000, pll8, 1, 2, 7),
+ F_IJPEG(128000000, pll8, 3, 0, 0),
+ F_IJPEG(153600000, pll8, 1, 2, 5),
+ F_IJPEG(200000000, pll2, 4, 0, 0),
+ F_IJPEG(228571000, pll2, 1, 2, 7),
+ F_IJPEG(266667000, pll2, 1, 1, 3),
+ F_IJPEG(320000000, pll2, 1, 2, 5),
F_END
};
-static struct clk_freq_tbl clk_tbl_ijpeg_8064[] = {
- F_IJPEG( 0, gnd, 1, 0, 0, NONE),
- F_IJPEG( 36570000, pll8, 1, 2, 21, LOW),
- F_IJPEG( 54860000, pll8, 7, 0, 0, LOW),
- F_IJPEG( 96000000, pll8, 4, 0, 0, LOW),
- F_IJPEG(109710000, pll8, 1, 2, 7, LOW),
- F_IJPEG(128000000, pll8, 3, 0, 0, LOW),
- F_IJPEG(153600000, pll8, 1, 2, 5, NOMINAL),
- F_IJPEG(200000000, pll2, 4, 0, 0, NOMINAL),
- F_IJPEG(228571000, pll2, 1, 2, 7, NOMINAL),
- F_IJPEG(320000000, pll2, 1, 2, 5, HIGH),
- F_END
+static unsigned long fmax_ijpeg_8960_v2[MAX_VDD_LEVELS] __initdata = {
+ [VDD_DIG_LOW] = 110000000,
+ [VDD_DIG_NOMINAL] = 266667000,
+ [VDD_DIG_HIGH] = 320000000
+};
+
+static unsigned long fmax_ijpeg_8064[MAX_VDD_LEVELS] __initdata = {
+ [VDD_DIG_LOW] = 128000000,
+ [VDD_DIG_NOMINAL] = 266667000,
+ [VDD_DIG_HIGH] = 320000000
};
static struct rcg_clk ijpeg_clk = {
@@ -3613,30 +3729,30 @@
.ns_mask = (BM(23, 16) | BM(15, 12) | BM(2, 0)),
.ctl_mask = BM(7, 6),
.set_rate = set_rate_mnd,
- .freq_tbl = clk_tbl_ijpeg_8960,
+ .freq_tbl = clk_tbl_ijpeg,
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "ijpeg_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 110000000, NOMINAL, 266667000),
CLK_INIT(ijpeg_clk.c),
.depends = &ijpeg_axi_clk.c,
},
};
-#define F_JPEGD(f, s, d, v) \
+#define F_JPEGD(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_jpegd[] = {
- F_JPEGD( 0, gnd, 1, NONE),
- F_JPEGD( 64000000, pll8, 6, LOW),
- F_JPEGD( 76800000, pll8, 5, LOW),
- F_JPEGD( 96000000, pll8, 4, LOW),
- F_JPEGD(160000000, pll2, 5, NOMINAL),
- F_JPEGD(200000000, pll2, 4, NOMINAL),
+ F_JPEGD( 0, gnd, 1),
+ F_JPEGD( 64000000, pll8, 6),
+ F_JPEGD( 76800000, pll8, 5),
+ F_JPEGD( 96000000, pll8, 4),
+ F_JPEGD(160000000, pll2, 5),
+ F_JPEGD(200000000, pll2, 4),
F_END
};
@@ -3658,12 +3774,13 @@
.c = {
.dbg_name = "jpegd_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
CLK_INIT(jpegd_clk.c),
.depends = &jpegd_axi_clk.c,
},
};
-#define F_MDP(f, s, m, n, v) \
+#define F_MDP(f, s, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -3671,44 +3788,30 @@
.ns_val = NS_MND_BANKED8(22, 14, n, m, 3, 0, s##_to_mm_mux), \
.ctl_val = CC_BANKED(9, 6, n), \
.mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
- .sys_vdd = v, \
}
-static struct clk_freq_tbl clk_tbl_mdp_8960[] = {
- F_MDP( 0, gnd, 0, 0, NONE),
- F_MDP( 9600000, pll8, 1, 40, LOW),
- F_MDP( 13710000, pll8, 1, 28, LOW),
- F_MDP( 27000000, pxo, 0, 0, LOW),
- F_MDP( 29540000, pll8, 1, 13, LOW),
- F_MDP( 34910000, pll8, 1, 11, LOW),
- F_MDP( 38400000, pll8, 1, 10, LOW),
- F_MDP( 59080000, pll8, 2, 13, LOW),
- F_MDP( 76800000, pll8, 1, 5, LOW),
- F_MDP( 85330000, pll8, 2, 9, LOW),
- F_MDP( 96000000, pll8, 1, 4, NOMINAL),
- F_MDP(128000000, pll8, 1, 3, NOMINAL),
- F_MDP(160000000, pll2, 1, 5, NOMINAL),
- F_MDP(177780000, pll2, 2, 9, NOMINAL),
- F_MDP(200000000, pll2, 1, 4, NOMINAL),
+static struct clk_freq_tbl clk_tbl_mdp[] = {
+ F_MDP( 0, gnd, 0, 0),
+ F_MDP( 9600000, pll8, 1, 40),
+ F_MDP( 13710000, pll8, 1, 28),
+ F_MDP( 27000000, pxo, 0, 0),
+ F_MDP( 29540000, pll8, 1, 13),
+ F_MDP( 34910000, pll8, 1, 11),
+ F_MDP( 38400000, pll8, 1, 10),
+ F_MDP( 59080000, pll8, 2, 13),
+ F_MDP( 76800000, pll8, 1, 5),
+ F_MDP( 85330000, pll8, 2, 9),
+ F_MDP( 96000000, pll8, 1, 4),
+ F_MDP(128000000, pll8, 1, 3),
+ F_MDP(160000000, pll2, 1, 5),
+ F_MDP(177780000, pll2, 2, 9),
+ F_MDP(200000000, pll2, 1, 4),
+ F_MDP(266667000, pll2, 1, 3),
F_END
};
-static struct clk_freq_tbl clk_tbl_mdp_8064[] = {
- F_MDP( 0, gnd, 0, 0, NONE),
- F_MDP( 9600000, pll8, 1, 40, LOW),
- F_MDP( 13710000, pll8, 1, 28, LOW),
- F_MDP( 29540000, pll8, 1, 13, LOW),
- F_MDP( 34910000, pll8, 1, 11, LOW),
- F_MDP( 38400000, pll8, 1, 10, LOW),
- F_MDP( 59080000, pll8, 2, 13, LOW),
- F_MDP( 76800000, pll8, 1, 5, LOW),
- F_MDP( 85330000, pll8, 2, 9, LOW),
- F_MDP( 96000000, pll8, 1, 4, LOW),
- F_MDP(128000000, pll8, 1, 3, LOW),
- F_MDP(160000000, pll2, 1, 5, NOMINAL),
- F_MDP(177780000, pll2, 2, 9, NOMINAL),
- F_MDP(200000000, pll2, 1, 4, NOMINAL),
- F_MDP(266000000, pll2, 1, 3, NOMINAL),
- F_END
+static unsigned long fmax_mdp_8064[MAX_VDD_LEVELS] __initdata = {
+ [VDD_DIG_LOW] = 128000000,
+ [VDD_DIG_NOMINAL] = 266667000
};
static struct bank_masks bmnd_info_mdp = {
@@ -3741,12 +3844,13 @@
.ns_reg = MDP_NS_REG,
.root_en_mask = BIT(2),
.set_rate = set_rate_mnd_banked,
- .freq_tbl = clk_tbl_mdp_8960,
+ .freq_tbl = clk_tbl_mdp,
.bank_info = &bmnd_info_mdp,
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "mdp_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
CLK_INIT(mdp_clk.c),
.depends = &mdp_axi_clk.c,
},
@@ -3767,15 +3871,14 @@
},
};
-#define F_MDP_VSYNC(f, s, v) \
+#define F_MDP_VSYNC(f, s) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_SRC_SEL(13, 13, s##_to_bb_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_mdp_vsync[] = {
- F_MDP_VSYNC(27000000, pxo, LOW),
+ F_MDP_VSYNC(27000000, pxo),
F_END
};
@@ -3796,34 +3899,34 @@
.c = {
.dbg_name = "mdp_vsync_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP1(LOW, 27000000),
CLK_INIT(mdp_vsync_clk.c),
},
};
-#define F_ROT(f, s, d, v) \
+#define F_ROT(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_DIVSRC_BANKED(29, 26, 25, 22, d, \
21, 19, 18, 16, s##_to_mm_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_rot[] = {
- F_ROT( 0, gnd, 1, NONE),
- F_ROT( 27000000, pxo, 1, LOW),
- F_ROT( 29540000, pll8, 13, LOW),
- F_ROT( 32000000, pll8, 12, LOW),
- F_ROT( 38400000, pll8, 10, LOW),
- F_ROT( 48000000, pll8, 8, LOW),
- F_ROT( 54860000, pll8, 7, LOW),
- F_ROT( 64000000, pll8, 6, LOW),
- F_ROT( 76800000, pll8, 5, LOW),
- F_ROT( 96000000, pll8, 4, LOW),
- F_ROT(100000000, pll2, 8, NOMINAL),
- F_ROT(114290000, pll2, 7, NOMINAL),
- F_ROT(133330000, pll2, 6, NOMINAL),
- F_ROT(160000000, pll2, 5, NOMINAL),
- F_ROT(200000000, pll2, 4, NOMINAL),
+ F_ROT( 0, gnd, 1),
+ F_ROT( 27000000, pxo, 1),
+ F_ROT( 29540000, pll8, 13),
+ F_ROT( 32000000, pll8, 12),
+ F_ROT( 38400000, pll8, 10),
+ F_ROT( 48000000, pll8, 8),
+ F_ROT( 54860000, pll8, 7),
+ F_ROT( 64000000, pll8, 6),
+ F_ROT( 76800000, pll8, 5),
+ F_ROT( 96000000, pll8, 4),
+ F_ROT(100000000, pll2, 8),
+ F_ROT(114290000, pll2, 7),
+ F_ROT(133330000, pll2, 6),
+ F_ROT(160000000, pll2, 5),
+ F_ROT(200000000, pll2, 4),
F_END
};
@@ -3855,6 +3958,7 @@
.c = {
.dbg_name = "rot_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
CLK_INIT(rot_clk.c),
.depends = &rot_axi_clk.c,
},
@@ -3902,7 +4006,7 @@
CLK_INIT(hdmi_pll_clk),
};
-#define F_TV_GND(f, s, p_r, d, m, n, v) \
+#define F_TV_GND(f, s, p_r, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -3910,9 +4014,8 @@
.ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
-#define F_TV(f, s, p_r, d, m, n, v) \
+#define F_TV(f, s, p_r, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk, \
@@ -3920,20 +4023,24 @@
.ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
.extra_freq_data = (void *)p_r, \
}
/* Switching TV freqs requires PLL reconfiguration. */
static struct clk_freq_tbl clk_tbl_tv[] = {
- F_TV_GND( 0, gnd, 0, 1, 0, 0, NONE),
- F_TV( 25200000, hdmi_pll, 25200000, 1, 0, 0, LOW),
- F_TV( 27000000, hdmi_pll, 27000000, 1, 0, 0, LOW),
- F_TV( 27030000, hdmi_pll, 27030000, 1, 0, 0, LOW),
- F_TV( 74250000, hdmi_pll, 74250000, 1, 0, 0, NOMINAL),
- F_TV(148500000, hdmi_pll, 148500000, 1, 0, 0, NOMINAL),
+ F_TV_GND( 0, gnd, 0, 1, 0, 0),
+ F_TV( 25200000, hdmi_pll, 25200000, 1, 0, 0),
+ F_TV( 27000000, hdmi_pll, 27000000, 1, 0, 0),
+ F_TV( 27030000, hdmi_pll, 27030000, 1, 0, 0),
+ F_TV( 74250000, hdmi_pll, 74250000, 1, 0, 0),
+ F_TV(148500000, hdmi_pll, 148500000, 1, 0, 0),
F_END
};
+static unsigned long fmax_tv_src_8064[MAX_VDD_LEVELS] __initdata = {
+ [VDD_DIG_LOW] = 74250000,
+ [VDD_DIG_NOMINAL] = 149000000
+};
+
/*
* Unlike other clocks, the TV rate is adjusted through PLL
* re-programming. It is also routed through an MND divider.
@@ -3962,6 +4069,7 @@
.c = {
.dbg_name = "tv_src_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 27030000, NOMINAL, 149000000),
CLK_INIT(tv_src_clk.c),
},
};
@@ -4065,7 +4173,7 @@
.mode_mask = BM(12, 11),
},
};
-#define F_VCODEC(f, s, m, n, v) \
+#define F_VCODEC(f, s, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -4073,18 +4181,17 @@
.ns_val = NS_MND_BANKED8(11, 19, n, m, 0, 27, s##_to_mm_mux), \
.ctl_val = CC_BANKED(6, 11, n), \
.mnd_en_mask = (BIT(10) | BIT(5)) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_vcodec[] = {
- F_VCODEC( 0, gnd, 0, 0, NONE),
- F_VCODEC( 27000000, pxo, 0, 0, LOW),
- F_VCODEC( 32000000, pll8, 1, 12, LOW),
- F_VCODEC( 48000000, pll8, 1, 8, LOW),
- F_VCODEC( 54860000, pll8, 1, 7, LOW),
- F_VCODEC( 96000000, pll8, 1, 4, LOW),
- F_VCODEC(133330000, pll2, 1, 6, NOMINAL),
- F_VCODEC(200000000, pll2, 1, 4, NOMINAL),
- F_VCODEC(228570000, pll2, 2, 7, HIGH),
+ F_VCODEC( 0, gnd, 0, 0),
+ F_VCODEC( 27000000, pxo, 0, 0),
+ F_VCODEC( 32000000, pll8, 1, 12),
+ F_VCODEC( 48000000, pll8, 1, 8),
+ F_VCODEC( 54860000, pll8, 1, 7),
+ F_VCODEC( 96000000, pll8, 1, 4),
+ F_VCODEC(133330000, pll2, 1, 6),
+ F_VCODEC(200000000, pll2, 1, 4),
+ F_VCODEC(228570000, pll2, 2, 7),
F_END
};
@@ -4106,28 +4213,29 @@
.c = {
.dbg_name = "vcodec_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
+ HIGH, 228571000),
CLK_INIT(vcodec_clk.c),
.depends = &vcodec_axi_clk.c,
},
};
-#define F_VPE(f, s, d, v) \
+#define F_VPE(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_vpe[] = {
- F_VPE( 0, gnd, 1, NONE),
- F_VPE( 27000000, pxo, 1, LOW),
- F_VPE( 34909000, pll8, 11, LOW),
- F_VPE( 38400000, pll8, 10, LOW),
- F_VPE( 64000000, pll8, 6, LOW),
- F_VPE( 76800000, pll8, 5, LOW),
- F_VPE( 96000000, pll8, 4, NOMINAL),
- F_VPE(100000000, pll2, 8, NOMINAL),
- F_VPE(160000000, pll2, 5, NOMINAL),
+ F_VPE( 0, gnd, 1),
+ F_VPE( 27000000, pxo, 1),
+ F_VPE( 34909000, pll8, 11),
+ F_VPE( 38400000, pll8, 10),
+ F_VPE( 64000000, pll8, 6),
+ F_VPE( 76800000, pll8, 5),
+ F_VPE( 96000000, pll8, 4),
+ F_VPE(100000000, pll2, 8),
+ F_VPE(160000000, pll2, 5),
F_END
};
@@ -4149,12 +4257,13 @@
.c = {
.dbg_name = "vpe_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 76800000, NOMINAL, 160000000),
CLK_INIT(vpe_clk.c),
.depends = &vpe_axi_clk.c,
},
};
-#define F_VFE(f, s, d, m, n, v) \
+#define F_VFE(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -4162,50 +4271,40 @@
.ns_val = NS_MM(23, 16, n, m, 11, 10, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
-static struct clk_freq_tbl clk_tbl_vfe_8960[] = {
- F_VFE( 0, gnd, 1, 0, 0, NONE),
- F_VFE( 13960000, pll8, 1, 2, 55, LOW),
- F_VFE( 27000000, pxo, 1, 0, 0, LOW),
- F_VFE( 36570000, pll8, 1, 2, 21, LOW),
- F_VFE( 38400000, pll8, 2, 1, 5, LOW),
- F_VFE( 45180000, pll8, 1, 2, 17, LOW),
- F_VFE( 48000000, pll8, 2, 1, 4, LOW),
- F_VFE( 54860000, pll8, 1, 1, 7, LOW),
- F_VFE( 64000000, pll8, 2, 1, 3, LOW),
- F_VFE( 76800000, pll8, 1, 1, 5, LOW),
- F_VFE( 96000000, pll8, 2, 1, 2, LOW),
- F_VFE(109710000, pll8, 1, 2, 7, LOW),
- F_VFE(128000000, pll8, 1, 1, 3, NOMINAL),
- F_VFE(153600000, pll8, 1, 2, 5, NOMINAL),
- F_VFE(200000000, pll2, 2, 1, 2, NOMINAL),
- F_VFE(228570000, pll2, 1, 2, 7, NOMINAL),
- F_VFE(266667000, pll2, 1, 1, 3, NOMINAL),
- F_VFE(320000000, pll2, 1, 2, 5, HIGH),
+static struct clk_freq_tbl clk_tbl_vfe[] = {
+ F_VFE( 0, gnd, 1, 0, 0),
+ F_VFE( 13960000, pll8, 1, 2, 55),
+ F_VFE( 27000000, pxo, 1, 0, 0),
+ F_VFE( 36570000, pll8, 1, 2, 21),
+ F_VFE( 38400000, pll8, 2, 1, 5),
+ F_VFE( 45180000, pll8, 1, 2, 17),
+ F_VFE( 48000000, pll8, 2, 1, 4),
+ F_VFE( 54860000, pll8, 1, 1, 7),
+ F_VFE( 64000000, pll8, 2, 1, 3),
+ F_VFE( 76800000, pll8, 1, 1, 5),
+ F_VFE( 96000000, pll8, 2, 1, 2),
+ F_VFE(109710000, pll8, 1, 2, 7),
+ F_VFE(128000000, pll8, 1, 1, 3),
+ F_VFE(153600000, pll8, 1, 2, 5),
+ F_VFE(200000000, pll2, 2, 1, 2),
+ F_VFE(228570000, pll2, 1, 2, 7),
+ F_VFE(266667000, pll2, 1, 1, 3),
+ F_VFE(320000000, pll2, 1, 2, 5),
F_END
};
-static struct clk_freq_tbl clk_tbl_vfe_8064[] = {
- F_VFE( 0, gnd, 1, 0, 0, NONE),
- F_VFE( 13960000, pll8, 1, 2, 55, LOW),
- F_VFE( 36570000, pll8, 1, 2, 21, LOW),
- F_VFE( 38400000, pll8, 2, 1, 5, LOW),
- F_VFE( 45180000, pll8, 1, 2, 17, LOW),
- F_VFE( 48000000, pll8, 2, 1, 4, LOW),
- F_VFE( 54860000, pll8, 1, 1, 7, LOW),
- F_VFE( 64000000, pll8, 2, 1, 3, LOW),
- F_VFE( 76800000, pll8, 1, 1, 5, LOW),
- F_VFE( 96000000, pll8, 2, 1, 2, LOW),
- F_VFE(109710000, pll8, 1, 2, 7, LOW),
- F_VFE(128000000, pll8, 1, 1, 3, LOW),
- F_VFE(153600000, pll8, 1, 2, 5, NOMINAL),
- F_VFE(200000000, pll2, 2, 1, 2, NOMINAL),
- F_VFE(228570000, pll2, 1, 2, 7, NOMINAL),
- F_VFE(266667000, pll2, 1, 1, 3, NOMINAL),
- F_VFE(320000000, pll2, 1, 2, 5, HIGH),
- F_END
+static unsigned long fmax_vfe_8960_v2[MAX_VDD_LEVELS] __initdata = {
+ [VDD_DIG_LOW] = 110000000,
+ [VDD_DIG_NOMINAL] = 266667000,
+ [VDD_DIG_HIGH] = 320000000
+};
+
+static unsigned long fmax_vfe_8064[MAX_VDD_LEVELS] __initdata = {
+ [VDD_DIG_LOW] = 128000000,
+ [VDD_DIG_NOMINAL] = 266667000,
+ [VDD_DIG_HIGH] = 320000000
};
static struct rcg_clk vfe_clk = {
@@ -4223,11 +4322,12 @@
.ns_mask = (BM(23, 16) | BM(11, 10) | BM(2, 0)),
.ctl_mask = BM(7, 6),
.set_rate = set_rate_mnd,
- .freq_tbl = clk_tbl_vfe_8960,
+ .freq_tbl = clk_tbl_vfe,
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "vfe_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 110000000, NOMINAL, 266667000),
CLK_INIT(vfe_clk.c),
.depends = &vfe_axi_clk.c,
},
@@ -4253,28 +4353,27 @@
/*
* Low Power Audio Clocks
*/
-#define F_AIF_OSR(f, s, d, m, n, v) \
+#define F_AIF_OSR(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(8, m, 0, n), \
.ns_val = NS(31, 24, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_aif_osr[] = {
- F_AIF_OSR( 0, gnd, 1, 0, 0, NONE),
- F_AIF_OSR( 512000, pll4, 4, 1, 192, LOW),
- F_AIF_OSR( 768000, pll4, 4, 1, 128, LOW),
- F_AIF_OSR( 1024000, pll4, 4, 1, 96, LOW),
- F_AIF_OSR( 1536000, pll4, 4, 1, 64, LOW),
- F_AIF_OSR( 2048000, pll4, 4, 1, 48, LOW),
- F_AIF_OSR( 3072000, pll4, 4, 1, 32, LOW),
- F_AIF_OSR( 4096000, pll4, 4, 1, 24, LOW),
- F_AIF_OSR( 6144000, pll4, 4, 1, 16, LOW),
- F_AIF_OSR( 8192000, pll4, 4, 1, 12, LOW),
- F_AIF_OSR(12288000, pll4, 4, 1, 8, LOW),
- F_AIF_OSR(24576000, pll4, 4, 1, 4, LOW),
+ F_AIF_OSR( 0, gnd, 1, 0, 0),
+ F_AIF_OSR( 512000, pll4, 4, 1, 192),
+ F_AIF_OSR( 768000, pll4, 4, 1, 128),
+ F_AIF_OSR( 1024000, pll4, 4, 1, 96),
+ F_AIF_OSR( 1536000, pll4, 4, 1, 64),
+ F_AIF_OSR( 2048000, pll4, 4, 1, 48),
+ F_AIF_OSR( 3072000, pll4, 4, 1, 32),
+ F_AIF_OSR( 4096000, pll4, 4, 1, 24),
+ F_AIF_OSR( 6144000, pll4, 4, 1, 16),
+ F_AIF_OSR( 8192000, pll4, 4, 1, 12),
+ F_AIF_OSR(12288000, pll4, 4, 1, 8),
+ F_AIF_OSR(24576000, pll4, 4, 1, 4),
F_END
};
@@ -4299,6 +4398,7 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8960, \
+ VDD_DIG_FMAX_MAP1(LOW, 24576000), \
CLK_INIT(i##_clk.c), \
}, \
}
@@ -4323,6 +4423,7 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8960, \
+ VDD_DIG_FMAX_MAP1(LOW, 24576000), \
CLK_INIT(i##_clk.c), \
}, \
}
@@ -4421,28 +4522,27 @@
static CLK_AIF_BIT_DIV(spare_i2s_spkr_bit, LCC_SPARE_I2S_SPKR_NS_REG,
LCC_SPARE_I2S_SPKR_STATUS_REG);
-#define F_PCM(f, s, d, m, n, v) \
+#define F_PCM(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD16(m, n), \
.ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_pcm[] = {
- F_PCM( 0, gnd, 1, 0, 0, NONE),
- F_PCM( 512000, pll4, 4, 1, 192, LOW),
- F_PCM( 768000, pll4, 4, 1, 128, LOW),
- F_PCM( 1024000, pll4, 4, 1, 96, LOW),
- F_PCM( 1536000, pll4, 4, 1, 64, LOW),
- F_PCM( 2048000, pll4, 4, 1, 48, LOW),
- F_PCM( 3072000, pll4, 4, 1, 32, LOW),
- F_PCM( 4096000, pll4, 4, 1, 24, LOW),
- F_PCM( 6144000, pll4, 4, 1, 16, LOW),
- F_PCM( 8192000, pll4, 4, 1, 12, LOW),
- F_PCM(12288000, pll4, 4, 1, 8, LOW),
- F_PCM(24576000, pll4, 4, 1, 4, LOW),
+ F_PCM( 0, gnd, 1, 0, 0),
+ F_PCM( 512000, pll4, 4, 1, 192),
+ F_PCM( 768000, pll4, 4, 1, 128),
+ F_PCM( 1024000, pll4, 4, 1, 96),
+ F_PCM( 1536000, pll4, 4, 1, 64),
+ F_PCM( 2048000, pll4, 4, 1, 48),
+ F_PCM( 3072000, pll4, 4, 1, 32),
+ F_PCM( 4096000, pll4, 4, 1, 24),
+ F_PCM( 6144000, pll4, 4, 1, 16),
+ F_PCM( 8192000, pll4, 4, 1, 12),
+ F_PCM(12288000, pll4, 4, 1, 8),
+ F_PCM(24576000, pll4, 4, 1, 4),
F_END
};
@@ -4466,6 +4566,7 @@
.c = {
.dbg_name = "pcm_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP1(LOW, 24576000),
CLK_INIT(pcm_clk.c),
},
};
@@ -4490,6 +4591,7 @@
.c = {
.dbg_name = "audio_slimbus_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP1(LOW, 24576000),
CLK_INIT(audio_slimbus_clk.c),
},
};
@@ -4542,6 +4644,7 @@
static DEFINE_CLK_VOTER(dfab_sdc4_clk, &dfab_clk.c);
static DEFINE_CLK_VOTER(dfab_sdc5_clk, &dfab_clk.c);
static DEFINE_CLK_VOTER(dfab_sps_clk, &dfab_clk.c);
+static DEFINE_CLK_VOTER(dfab_bam_dmux_clk, &dfab_clk.c);
static DEFINE_CLK_VOTER(ebi1_msmbus_clk, &ebi1_clk.c);
/*
@@ -5031,23 +5134,23 @@
CLK_LOOKUP("cam_clk", cam0_clk.c, NULL),
CLK_LOOKUP("cam_clk", cam0_clk.c, NULL),
CLK_LOOKUP("cam_clk", cam0_clk.c, NULL),
- CLK_DUMMY("csi_src_clk", CSI0_SRC_CLK, NULL, OFF),
+ CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, NULL),
CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, NULL),
CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, NULL),
CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, NULL),
- CLK_DUMMY("csi_clk", CSI0_CLK, NULL, OFF),
+ CLK_LOOKUP("csi_clk", csi0_clk.c, NULL),
CLK_LOOKUP("csi_clk", csi1_clk.c, NULL),
CLK_LOOKUP("csi_clk", csi1_clk.c, NULL),
CLK_LOOKUP("csi_clk", csi2_clk.c, NULL),
- CLK_DUMMY("csi_phy_clk", CSI0_PHY_CLK, NULL, OFF),
+ CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, NULL),
CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, NULL),
CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, NULL),
CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, NULL),
- CLK_DUMMY("csi_pix_clk", CSI_PIX_CLK, NULL, OFF),
- CLK_DUMMY("csi_rdi_clk", CSI_RDI_CLK, NULL, OFF),
- CLK_DUMMY("csi_pix_clk", CSI_PIX1_CLK, NULL, OFF),
- CLK_DUMMY("csi_rdi_clk", CSI_RDI1_CLK, NULL, OFF),
- CLK_DUMMY("csi_rdi_clk", CSI_RDI2_CLK, NULL, OFF),
+ CLK_LOOKUP("csi_pix_clk", csi_pix_clk.c, NULL),
+ CLK_LOOKUP("csi_pix_clk", csi_pix1_clk.c, NULL),
+ CLK_LOOKUP("csi_rdi_clk", csi_rdi_clk.c, NULL),
+ CLK_LOOKUP("csi_rdi_clk", csi_rdi1_clk.c, NULL),
+ CLK_LOOKUP("csi_rdi_clk", csi_rdi2_clk.c, NULL),
CLK_LOOKUP("csiphy_timer_src_clk", csiphy_timer_src_clk.c, NULL),
CLK_LOOKUP("csiphy_timer_clk", csi0phy_timer_clk.c, NULL),
CLK_LOOKUP("csiphy_timer_clk", csi1phy_timer_clk.c, NULL),
@@ -5059,32 +5162,43 @@
CLK_DUMMY("rgb_tv_clk", RGB_TV_CLK, NULL, OFF),
CLK_DUMMY("npl_tv_clk", NPL_TV_CLK, NULL, OFF),
CLK_LOOKUP("core_clk", gfx3d_clk.c, NULL),
+ CLK_LOOKUP("core_clk", gfx3d_clk.c, "footswitch-8x60.2"),
+ CLK_LOOKUP("bus_clk", gfx3d_axi_clk.c, "footswitch-8x60.2"),
CLK_LOOKUP("iface_clk", vcap_p_clk.c, NULL),
- CLK_LOOKUP("bus_clk", vcap_axi_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", vcap_p_clk.c, "footswitch-8x60.10"),
+ CLK_LOOKUP("bus_clk", vcap_axi_clk.c, "footswitch-8x60.10"),
CLK_LOOKUP("core_clk", vcap_clk.c, NULL),
+ CLK_LOOKUP("core_clk", vcap_clk.c, "footswitch-8x60.10"),
CLK_LOOKUP("vcap_npl_clk", vcap_npl_clk.c, NULL),
- CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, NULL),
+ CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, "footswitch-8x60.3"),
CLK_LOOKUP("mem_clk", imem_axi_clk.c, NULL),
CLK_LOOKUP("ijpeg_clk", ijpeg_clk.c, NULL),
+ CLK_LOOKUP("core_clk", ijpeg_clk.c, "footswitch-8x60.3"),
CLK_LOOKUP("core_clk", jpegd_clk.c, NULL),
CLK_LOOKUP("mdp_clk", mdp_clk.c, NULL),
+ CLK_LOOKUP("core_clk", mdp_clk.c, "footswitch-8x60.4"),
CLK_LOOKUP("mdp_vsync_clk", mdp_vsync_clk.c, NULL),
CLK_LOOKUP("lut_mdp", lut_mdp_clk.c, NULL),
- CLK_LOOKUP("rot_clk", rot_clk.c, NULL),
+ CLK_LOOKUP("core_clk", rot_clk.c, "msm_rotator.0"),
+ CLK_LOOKUP("core_clk", rot_clk.c, "footswitch-8x60.6"),
CLK_DUMMY("tv_src_clk", TV_SRC_CLK, NULL, OFF),
CLK_LOOKUP("core_clk", vcodec_clk.c, NULL),
+ CLK_LOOKUP("core_clk", vcodec_clk.c, "footswitch-8x60.7"),
CLK_DUMMY("mdp_tv_clk", MDP_TV_CLK, NULL, OFF),
CLK_DUMMY("hdmi_clk", HDMI_TV_CLK, NULL, OFF),
CLK_LOOKUP("core_clk", hdmi_app_clk.c, NULL),
CLK_LOOKUP("vpe_clk", vpe_clk.c, NULL),
+ CLK_LOOKUP("core_clk", vpe_clk.c, "footswitch-8x60.9"),
CLK_LOOKUP("vfe_clk", vfe_clk.c, NULL),
+ CLK_LOOKUP("core_clk", vfe_clk.c, "footswitch-8x60.8"),
CLK_LOOKUP("csi_vfe_clk", csi_vfe_clk.c, NULL),
- CLK_LOOKUP("vfe_axi_clk", vfe_axi_clk.c, NULL),
- CLK_LOOKUP("mdp_axi_clk", mdp_axi_clk.c, NULL),
- CLK_LOOKUP("bus_clk", vcodec_axi_clk.c, NULL),
- CLK_LOOKUP("bus_a_clk", vcodec_axi_a_clk.c, NULL),
- CLK_LOOKUP("bus_b_clk", vcodec_axi_b_clk.c, NULL),
- CLK_LOOKUP("vpe_axi_clk", vpe_axi_clk.c, NULL),
+ CLK_LOOKUP("bus_clk", vfe_axi_clk.c, "footswitch-8x60.8"),
+ CLK_LOOKUP("bus_clk", mdp_axi_clk.c, "footswitch-8x60.4"),
+ CLK_LOOKUP("bus_clk", rot_axi_clk.c, "footswitch-8x60.6"),
+ CLK_LOOKUP("bus_clk", vcodec_axi_clk.c, "footswitch-8x60.7"),
+ CLK_LOOKUP("bus_a_clk", vcodec_axi_a_clk.c, "footswitch-8x60.7"),
+ CLK_LOOKUP("bus_b_clk", vcodec_axi_b_clk.c, "footswitch-8x60.7"),
+ CLK_LOOKUP("bus_clk", vpe_axi_clk.c, "footswitch-8x60.9"),
CLK_LOOKUP("amp_pclk", amp_p_clk.c, NULL),
CLK_LOOKUP("csi_pclk", csi_p_clk.c, NULL),
CLK_LOOKUP("dsi_m_pclk", dsi1_m_p_clk.c, NULL),
@@ -5092,17 +5206,24 @@
CLK_LOOKUP("dsi_m_pclk", dsi2_m_p_clk.c, NULL),
CLK_LOOKUP("dsi_s_pclk", dsi2_s_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "footswitch-8x60.2"),
CLK_LOOKUP("master_iface_clk", hdmi_m_p_clk.c, NULL),
CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, NULL),
CLK_LOOKUP("ijpeg_pclk", ijpeg_p_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "footswitch-8x60.3"),
CLK_LOOKUP("iface_clk", jpegd_p_clk.c, NULL),
CLK_LOOKUP("mem_iface_clk", imem_p_clk.c, NULL),
CLK_LOOKUP("mdp_pclk", mdp_p_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", mdp_p_clk.c, "footswitch-8x60.4"),
CLK_LOOKUP("iface_clk", smmu_p_clk.c, NULL),
- CLK_LOOKUP("rotator_pclk", rot_p_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", rot_p_clk.c, "msm_rotator.0"),
+ CLK_LOOKUP("iface_clk", rot_p_clk.c, "footswitch-8x60.6"),
CLK_LOOKUP("iface_clk", vcodec_p_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "footswitch-8x60.7"),
CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", vfe_p_clk.c, "footswitch-8x60.8"),
CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, NULL),
+ CLK_LOOKUP("iface_pclk", vpe_p_clk.c, "footswitch-8x60.9"),
CLK_LOOKUP("mi2s_bit_clk", mi2s_bit_clk.c, NULL),
CLK_LOOKUP("mi2s_osr_clk", mi2s_osr_clk.c, NULL),
CLK_LOOKUP("i2s_mic_bit_clk", codec_i2s_mic_bit_clk.c, NULL),
@@ -5125,7 +5246,7 @@
CLK_LOOKUP("core_clk", vfe_axi_clk.c, NULL),
CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, NULL),
CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, NULL),
- CLK_DUMMY("core_clk", GFX3D_AXI_CLK, NULL, 0),
+ CLK_LOOKUP("core_clk", gfx3d_axi_clk.c, NULL),
CLK_DUMMY("dfab_dsps_clk", DFAB_DSPS_CLK, NULL, 0),
CLK_DUMMY("dfab_usb_hs_clk", DFAB_USB_HS_CLK, NULL, 0),
CLK_DUMMY("bus_clk", DFAB_SDC1_CLK, NULL, 0),
@@ -5140,7 +5261,7 @@
CLK_LOOKUP("usb_hsic_p_clk", usb_hsic_p_clk.c, NULL),
CLK_LOOKUP("ebi1_msmbus_clk", ebi1_msmbus_clk.c, NULL),
- CLK_LOOKUP("ebi1_clk", ebi1_adm_clk.c, "msm_dmov"),
+ CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"),
CLK_LOOKUP("l2_mclk", l2_m_clk, NULL),
CLK_LOOKUP("krait0_mclk", krait0_m_clk, NULL),
@@ -5299,7 +5420,7 @@
CLK_LOOKUP("qdss_traceclkin_clk", qdss_traceclkin_clk.c, NULL),
CLK_LOOKUP("qdss_tsctr_clk", qdss_tsctr_clk.c, NULL),
CLK_LOOKUP("qdss_stm_clk", qdss_stm_clk.c, NULL),
- CLK_LOOKUP("rot_clk", rot_clk.c, NULL),
+ CLK_LOOKUP("core_clk", rot_clk.c, "msm_rotator.0"),
CLK_LOOKUP("core_clk", rot_clk.c, "footswitch-8x60.6"),
CLK_LOOKUP("tv_src_clk", tv_src_clk.c, NULL),
CLK_LOOKUP("tv_enc_clk", tv_enc_clk.c, NULL),
@@ -5342,7 +5463,7 @@
CLK_LOOKUP("mdp_pclk", mdp_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", mdp_p_clk.c, "footswitch-8x60.4"),
CLK_LOOKUP("iface_clk", smmu_p_clk.c, "msm_iommu"),
- CLK_LOOKUP("rotator_pclk", rot_p_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", rot_p_clk.c, "msm_rotator.0"),
CLK_LOOKUP("iface_clk", rot_p_clk.c, "footswitch-8x60.6"),
CLK_LOOKUP("tv_enc_pclk", tv_enc_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "msm_vidc.0"),
@@ -5384,6 +5505,7 @@
CLK_LOOKUP("bus_clk", dfab_sdc4_clk.c, "msm_sdcc.4"),
CLK_LOOKUP("bus_clk", dfab_sdc5_clk.c, "msm_sdcc.5"),
CLK_LOOKUP("dfab_clk", dfab_sps_clk.c, "msm_sps"),
+ CLK_LOOKUP("bus_clk", dfab_bam_dmux_clk.c, "BAM_RMNT"),
CLK_LOOKUP("ebi1_msmbus_clk", ebi1_msmbus_clk.c, NULL),
CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"),
@@ -5507,7 +5629,7 @@
rmwreg(0x80FF0000, VFE_CC_REG, 0xE0FF4010);
rmwreg(0x800000FF, VFE_CC2_REG, 0xE00000FF);
rmwreg(0x80FF0000, VPE_CC_REG, 0xE0FF0010);
- if (cpu_is_msm8960()) {
+ if (cpu_is_msm8960() || cpu_is_msm8930()) {
rmwreg(0x80FF0000, GFX2D0_CC_REG, 0xE0FF0010);
rmwreg(0x80FF0000, GFX2D1_CC_REG, 0xE0FF0010);
rmwreg(0x80FF0000, TV_CC_REG, 0xE1FFC010);
@@ -5552,7 +5674,7 @@
writel_relaxed(BIT(15), PDM_CLK_NS_REG);
/* Source SLIMBus xo src from slimbus reference clock */
- if (cpu_is_msm8960())
+ if (cpu_is_msm8960() || cpu_is_msm8930())
writel_relaxed(0x3, SLIMBUS_XO_SRC_CLK_CTL_REG);
/* Source the dsi_byte_clks from the DSI PHY PLLs */
@@ -5576,10 +5698,10 @@
/* Check if PLL8 is active */
is_pll_enabled = readl_relaxed(BB_PLL8_STATUS_REG) & BIT(16);
if (!is_pll_enabled) {
- /* Ref clk = 24.5MHz and program pll8 to 384MHz */
- writel_relaxed(0xF, BB_PLL8_L_VAL_REG);
- writel_relaxed(0x21, BB_PLL8_M_VAL_REG);
- writel_relaxed(0x31, BB_PLL8_N_VAL_REG);
+ /* Ref clk = 27MHz and program pll8 to 384MHz */
+ writel_relaxed(0xE, BB_PLL8_L_VAL_REG);
+ writel_relaxed(0x2, BB_PLL8_M_VAL_REG);
+ writel_relaxed(0x9, BB_PLL8_N_VAL_REG);
regval = readl_relaxed(BB_PLL8_CONFIG_REG);
@@ -5605,10 +5727,10 @@
/* Check if PLL3 is active */
is_pll_enabled = readl_relaxed(GPLL1_STATUS_REG) & BIT(16);
if (!is_pll_enabled) {
- /* Ref clk = 24.5MHz and program pll3 to 1200MHz */
- writel_relaxed(0x30, GPLL1_L_VAL_REG);
- writel_relaxed(0x30, GPLL1_M_VAL_REG);
- writel_relaxed(0x31, GPLL1_N_VAL_REG);
+ /* Ref clk = 27MHz and program pll3 to 1200MHz */
+ writel_relaxed(0x2C, GPLL1_L_VAL_REG);
+ writel_relaxed(0x4, GPLL1_M_VAL_REG);
+ writel_relaxed(0x9, GPLL1_N_VAL_REG);
regval = readl_relaxed(GPLL1_CONFIG_REG);
@@ -5624,10 +5746,10 @@
/* Check if PLL14 is active */
is_pll_enabled = readl_relaxed(BB_PLL14_STATUS_REG) & BIT(16);
if (!is_pll_enabled) {
- /* Ref clk = 24.5MHz and program pll14 to 480MHz */
- writel_relaxed(0x13, BB_PLL14_L_VAL_REG);
- writel_relaxed(0x1D, BB_PLL14_M_VAL_REG);
- writel_relaxed(0x31, BB_PLL14_N_VAL_REG);
+ /* Ref clk = 27MHz and program pll14 to 480MHz */
+ writel_relaxed(0x11, BB_PLL14_L_VAL_REG);
+ writel_relaxed(0x7, BB_PLL14_M_VAL_REG);
+ writel_relaxed(0x9, BB_PLL14_N_VAL_REG);
regval = readl_relaxed(BB_PLL14_CONFIG_REG);
@@ -5691,10 +5813,10 @@
/* Check if PLL4 is active */
is_pll_enabled = readl_relaxed(LCC_PLL0_STATUS_REG) & BIT(16);
if (!is_pll_enabled) {
- /* Ref clk = 24.5MHz and program pll4 to 393.2160MHz */
- writel_relaxed(0x10, LCC_PLL0_L_VAL_REG);
- writel_relaxed(0x130, LCC_PLL0_M_VAL_REG);
- writel_relaxed(0x17ED, LCC_PLL0_N_VAL_REG);
+ /* Ref clk = 27MHz and program pll4 to 393.2160MHz */
+ writel_relaxed(0xE, LCC_PLL0_L_VAL_REG);
+ writel_relaxed(0x27A, LCC_PLL0_M_VAL_REG);
+ writel_relaxed(0x465, LCC_PLL0_N_VAL_REG);
regval = readl_relaxed(LCC_PLL0_CONFIG_REG);
@@ -5735,11 +5857,19 @@
BUG();
}
- if (cpu_is_msm8960()) {
+ if (cpu_is_msm8960() || cpu_is_msm8930()) {
memcpy(msm_clocks_8960, msm_clocks_8960_v1,
sizeof(msm_clocks_8960_v1));
if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 2) {
gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8960_v2;
+
+ memcpy(gfx3d_clk.c.fmax, fmax_gfx3d_8960_v2,
+ sizeof(gfx3d_clk.c.fmax));
+ memcpy(ijpeg_clk.c.fmax, fmax_ijpeg_8960_v2,
+ sizeof(ijpeg_clk.c.fmax));
+ memcpy(vfe_clk.c.fmax, fmax_vfe_8960_v2,
+ sizeof(vfe_clk.c.fmax));
+
memcpy(msm_clocks_8960 + ARRAY_SIZE(msm_clocks_8960_v1),
msm_clocks_8960_v2, sizeof(msm_clocks_8960_v2));
num_lookups = ARRAY_SIZE(msm_clocks_8960);
@@ -5748,20 +5878,27 @@
}
/*
- * Change the freq tables for gfx3d_clk, ijpeg_clk, mdp_clk,
- * tv_src_clk and vfe_clk at runtime and chain gmem_axi_clk
- * with gfx3d_axi_clk for 8064.
+ * Change the freq tables for and voltage requirements for
+ * clocks which differ between 8960 and 8064.
*/
if (cpu_is_apq8064()) {
gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8064;
- ijpeg_clk.freq_tbl = clk_tbl_ijpeg_8064;
- mdp_clk.freq_tbl = clk_tbl_mdp_8064;
- vfe_clk.freq_tbl = clk_tbl_vfe_8064;
+
+ memcpy(gfx3d_clk.c.fmax, fmax_gfx3d_8064,
+ sizeof(gfx3d_clk.c.fmax));
+ memcpy(ijpeg_clk.c.fmax, fmax_ijpeg_8064,
+ sizeof(ijpeg_clk.c.fmax));
+ memcpy(mdp_clk.c.fmax, fmax_mdp_8064,
+ sizeof(ijpeg_clk.c.fmax));
+ memcpy(tv_src_clk.c.fmax, fmax_tv_src_8064,
+ sizeof(tv_src_clk.c.fmax));
+ memcpy(vfe_clk.c.fmax, fmax_vfe_8064,
+ sizeof(vfe_clk.c.fmax));
+
gmem_axi_clk.c.depends = &gfx3d_axi_clk.c;
}
- soc_update_sys_vdd = msm8960_update_sys_vdd;
- local_vote_sys_vdd(HIGH);
+ vote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
clk_ops_pll.enable = sr_pll_clk_enable;
@@ -5780,11 +5917,18 @@
clk_set_rate(&usb_hs4_xcvr_clk.c, 60000000);
}
clk_set_rate(&usb_fs1_src_clk.c, 60000000);
- if (cpu_is_msm8960())
+ if (cpu_is_msm8960() || cpu_is_msm8930())
clk_set_rate(&usb_fs2_src_clk.c, 60000000);
clk_set_rate(&usb_hsic_xcvr_fs_clk.c, 60000000);
clk_set_rate(&usb_hsic_hsic_src_clk.c, 480000000);
clk_set_rate(&usb_hsic_hsio_cal_clk.c, 9000000);
+ /*
+ * Set the CSI rates to a safe default to avoid warnings when
+ * switching csi pix and rdi clocks.
+ */
+ clk_set_rate(&csi0_src_clk.c, 27000000);
+ clk_set_rate(&csi1_src_clk.c, 27000000);
+ clk_set_rate(&csi2_src_clk.c, 27000000);
/*
* The halt status bits for these clocks may be incorrect at boot.
@@ -5798,7 +5942,9 @@
SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 2) {
clk_enable(&usb_hsic_hsic_clk.c);
clk_disable(&usb_hsic_hsic_clk.c);
- }
+ } else
+ /* CSI2 hardware not present on 8960v1 devices */
+ pix_rdi_mux_map[2] = NULL;
if (machine_is_msm8960_sim()) {
clk_set_rate(&sdc1_clk.c, 48000000);
@@ -5837,7 +5983,8 @@
rc = clk_enable(cfpb_a_clk);
if (WARN(rc, "cfpb_a_clk not enabled (%d)\n", rc))
return rc;
- return local_unvote_sys_vdd(HIGH);
+
+ return unvote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
}
struct clock_init_data msm8960_clock_init_data __initdata = {
diff --git a/arch/arm/mach-msm/clock-8x60.c b/arch/arm/mach-msm/clock-8x60.c
index 4e891d0..c5d3d1d 100644
--- a/arch/arm/mach-msm/clock-8x60.c
+++ b/arch/arm/mach-msm/clock-8x60.c
@@ -313,6 +313,41 @@
| BVAL((mde1_lsb+1), mde1_lsb, MN_MODE_DUAL_EDGE)) \
* !!(n))
+enum vdd_dig_levels {
+ VDD_DIG_NONE,
+ VDD_DIG_LOW,
+ VDD_DIG_NOMINAL,
+ VDD_DIG_HIGH
+};
+
+static int set_vdd_dig(struct clk_vdd_class *vdd_class, int level)
+{
+ static const int vdd_uv[] = {
+ [VDD_DIG_NONE] = 500000,
+ [VDD_DIG_LOW] = 1000000,
+ [VDD_DIG_NOMINAL] = 1100000,
+ [VDD_DIG_HIGH] = 1200000
+ };
+
+ return rpm_vreg_set_voltage(RPM_VREG_ID_PM8058_S1, RPM_VREG_VOTER3,
+ vdd_uv[level], 1200000, 1);
+}
+
+static DEFINE_VDD_CLASS(vdd_dig, set_vdd_dig);
+
+#define VDD_DIG_FMAX_MAP1(l1, f1) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1)
+#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1), \
+ .fmax[VDD_DIG_##l2] = (f2)
+#define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1), \
+ .fmax[VDD_DIG_##l2] = (f2), \
+ .fmax[VDD_DIG_##l3] = (f3)
+
static struct msm_xo_voter *xo_pxo, *xo_cxo;
static bool xo_clk_is_local(struct clk *clk)
@@ -498,24 +533,6 @@
writel_relaxed(pll_mode, MM_PLL2_MODE_REG);
}
-/*
- * SoC-specific functions required by clock-local driver
- */
-
-/* Update the sys_vdd voltage given a level. */
-static int msm8660_update_sys_vdd(enum sys_vdd_level level)
-{
- static const int vdd_uv[] = {
- [NONE] = 500000,
- [LOW] = 1000000,
- [NOMINAL] = 1100000,
- [HIGH] = 1200000,
- };
-
- return rpm_vreg_set_voltage(RPM_VREG_ID_PM8058_S1, RPM_VREG_VOTER3,
- vdd_uv[level], vdd_uv[HIGH], 1);
-}
-
static int soc_clk_reset(struct clk *clk, enum clk_reset_action action)
{
return branch_reset(&to_rcg_clk(clk)->b, action);
@@ -524,7 +541,7 @@
static struct clk_ops clk_ops_rcg_8x60 = {
.enable = rcg_clk_enable,
.disable = rcg_clk_disable,
- .auto_off = rcg_clk_auto_off,
+ .auto_off = rcg_clk_disable,
.handoff = rcg_clk_handoff,
.set_rate = rcg_clk_set_rate,
.set_min_rate = rcg_clk_set_min_rate,
@@ -540,7 +557,7 @@
static struct clk_ops clk_ops_branch = {
.enable = branch_clk_enable,
.disable = branch_clk_disable,
- .auto_off = branch_clk_auto_off,
+ .auto_off = branch_clk_disable,
.is_enabled = branch_clk_is_enabled,
.reset = branch_clk_reset,
.is_local = local_clk_is_local,
@@ -1053,34 +1070,34 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8x60, \
+ VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 64000000), \
CLK_INIT(i##_clk.c), \
}, \
}
-#define F_GSBI_UART(f, s, d, m, n, v) \
+#define F_GSBI_UART(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD16(m, n), \
.ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gsbi_uart[] = {
- F_GSBI_UART( 0, gnd, 1, 0, 0, NONE),
- F_GSBI_UART( 1843200, pll8, 1, 3, 625, LOW),
- F_GSBI_UART( 3686400, pll8, 1, 6, 625, LOW),
- F_GSBI_UART( 7372800, pll8, 1, 12, 625, LOW),
- F_GSBI_UART(14745600, pll8, 1, 24, 625, LOW),
- F_GSBI_UART(16000000, pll8, 4, 1, 6, LOW),
- F_GSBI_UART(24000000, pll8, 4, 1, 4, LOW),
- F_GSBI_UART(32000000, pll8, 4, 1, 3, LOW),
- F_GSBI_UART(40000000, pll8, 1, 5, 48, NOMINAL),
- F_GSBI_UART(46400000, pll8, 1, 29, 240, NOMINAL),
- F_GSBI_UART(48000000, pll8, 4, 1, 2, NOMINAL),
- F_GSBI_UART(51200000, pll8, 1, 2, 15, NOMINAL),
- F_GSBI_UART(56000000, pll8, 1, 7, 48, NOMINAL),
- F_GSBI_UART(58982400, pll8, 1, 96, 625, NOMINAL),
- F_GSBI_UART(64000000, pll8, 2, 1, 3, NOMINAL),
+ F_GSBI_UART( 0, gnd, 1, 0, 0),
+ F_GSBI_UART( 1843200, pll8, 1, 3, 625),
+ F_GSBI_UART( 3686400, pll8, 1, 6, 625),
+ F_GSBI_UART( 7372800, pll8, 1, 12, 625),
+ F_GSBI_UART(14745600, pll8, 1, 24, 625),
+ F_GSBI_UART(16000000, pll8, 4, 1, 6),
+ F_GSBI_UART(24000000, pll8, 4, 1, 4),
+ F_GSBI_UART(32000000, pll8, 4, 1, 3),
+ F_GSBI_UART(40000000, pll8, 1, 5, 48),
+ F_GSBI_UART(46400000, pll8, 1, 29, 240),
+ F_GSBI_UART(48000000, pll8, 4, 1, 2),
+ F_GSBI_UART(51200000, pll8, 1, 2, 15),
+ F_GSBI_UART(56000000, pll8, 1, 7, 48),
+ F_GSBI_UART(58982400, pll8, 1, 96, 625),
+ F_GSBI_UART(64000000, pll8, 2, 1, 3),
F_END
};
@@ -1117,29 +1134,29 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8x60, \
+ VDD_DIG_FMAX_MAP2(LOW, 24000000, NOMINAL, 52000000), \
CLK_INIT(i##_clk.c), \
}, \
}
-#define F_GSBI_QUP(f, s, d, m, n, v) \
+#define F_GSBI_QUP(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(16, m, 0, n), \
.ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gsbi_qup[] = {
- F_GSBI_QUP( 0, gnd, 1, 0, 0, NONE),
- F_GSBI_QUP( 1100000, pxo, 1, 2, 49, LOW),
- F_GSBI_QUP( 5400000, pxo, 1, 1, 5, LOW),
- F_GSBI_QUP(10800000, pxo, 1, 2, 5, LOW),
- F_GSBI_QUP(15060000, pll8, 1, 2, 51, LOW),
- F_GSBI_QUP(24000000, pll8, 4, 1, 4, LOW),
- F_GSBI_QUP(25600000, pll8, 1, 1, 15, NOMINAL),
- F_GSBI_QUP(27000000, pxo, 1, 0, 0, NOMINAL),
- F_GSBI_QUP(48000000, pll8, 4, 1, 2, NOMINAL),
- F_GSBI_QUP(51200000, pll8, 1, 2, 15, NOMINAL),
+ F_GSBI_QUP( 0, gnd, 1, 0, 0),
+ F_GSBI_QUP( 1100000, pxo, 1, 2, 49),
+ F_GSBI_QUP( 5400000, pxo, 1, 1, 5),
+ F_GSBI_QUP(10800000, pxo, 1, 2, 5),
+ F_GSBI_QUP(15060000, pll8, 1, 2, 51),
+ F_GSBI_QUP(24000000, pll8, 4, 1, 4),
+ F_GSBI_QUP(25600000, pll8, 1, 1, 15),
+ F_GSBI_QUP(27000000, pxo, 1, 0, 0),
+ F_GSBI_QUP(48000000, pll8, 4, 1, 2),
+ F_GSBI_QUP(51200000, pll8, 1, 2, 15),
F_END
};
@@ -1156,16 +1173,15 @@
static CLK_GSBI_QUP(gsbi11_qup, 11, CLK_HALT_CFPB_STATEC_REG, 15);
static CLK_GSBI_QUP(gsbi12_qup, 12, CLK_HALT_CFPB_STATEC_REG, 11);
-#define F_PDM(f, s, d, v) \
+#define F_PDM(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_pdm[] = {
- F_PDM( 0, gnd, 1, NONE),
- F_PDM(27000000, pxo, 1, LOW),
+ F_PDM( 0, gnd, 1),
+ F_PDM(27000000, pxo, 1),
F_END
};
@@ -1187,6 +1203,7 @@
.c = {
.dbg_name = "pdm_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP1(LOW, 27000000),
CLK_INIT(pdm_clk.c),
},
};
@@ -1205,14 +1222,13 @@
},
};
-#define F_PRNG(f, s, v) \
+#define F_PRNG(f, s) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_prng[] = {
- F_PRNG(64000000, pll8, NOMINAL),
+ F_PRNG(64000000, pll8),
F_END
};
@@ -1230,6 +1246,7 @@
.c = {
.dbg_name = "prng_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 65000000),
CLK_INIT(prng_clk.c),
},
};
@@ -1254,27 +1271,27 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8x60, \
+ VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), \
CLK_INIT(i##_clk.c), \
}, \
}
-#define F_SDC(f, s, d, m, n, v) \
+#define F_SDC(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(16, m, 0, n), \
.ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_sdc[] = {
- F_SDC( 0, gnd, 1, 0, 0, NONE),
- F_SDC( 144000, pxo, 3, 2, 125, LOW),
- F_SDC( 400000, pll8, 4, 1, 240, LOW),
- F_SDC(16000000, pll8, 4, 1, 6, LOW),
- F_SDC(17070000, pll8, 1, 2, 45, LOW),
- F_SDC(20210000, pll8, 1, 1, 19, LOW),
- F_SDC(24000000, pll8, 4, 1, 4, LOW),
- F_SDC(48000000, pll8, 4, 1, 2, NOMINAL),
+ F_SDC( 0, gnd, 1, 0, 0),
+ F_SDC( 144000, pxo, 3, 2, 125),
+ F_SDC( 400000, pll8, 4, 1, 240),
+ F_SDC(16000000, pll8, 4, 1, 6),
+ F_SDC(17070000, pll8, 1, 2, 45),
+ F_SDC(20210000, pll8, 1, 1, 19),
+ F_SDC(24000000, pll8, 4, 1, 4),
+ F_SDC(48000000, pll8, 4, 1, 2),
F_END
};
@@ -1284,18 +1301,17 @@
static CLK_SDC(sdc4, 4, CLK_HALT_DFAB_STATE_REG, 3);
static CLK_SDC(sdc5, 5, CLK_HALT_DFAB_STATE_REG, 2);
-#define F_TSIF_REF(f, s, d, m, n, v) \
+#define F_TSIF_REF(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD16(m, n), \
.ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_tsif_ref[] = {
- F_TSIF_REF( 0, gnd, 1, 0, 0, NONE),
- F_TSIF_REF(105000, pxo, 1, 1, 256, LOW),
+ F_TSIF_REF( 0, gnd, 1, 0, 0),
+ F_TSIF_REF(105000, pxo, 1, 1, 256),
F_END
};
@@ -1320,16 +1336,15 @@
},
};
-#define F_TSSC(f, s, v) \
+#define F_TSSC(f, s) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_tssc[] = {
- F_TSSC( 0, gnd, NONE),
- F_TSSC(27000000, pxo, LOW),
+ F_TSSC( 0, gnd),
+ F_TSSC(27000000, pxo),
F_END
};
@@ -1348,22 +1363,22 @@
.c = {
.dbg_name = "tssc_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP1(LOW, 27000000),
CLK_INIT(tssc_clk.c),
},
};
-#define F_USB(f, s, d, m, n, v) \
+#define F_USB(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(16, m, 0, n), \
.ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_usb[] = {
- F_USB( 0, gnd, 1, 0, 0, NONE),
- F_USB(60000000, pll8, 1, 5, 32, NOMINAL),
+ F_USB( 0, gnd, 1, 0, 0),
+ F_USB(60000000, pll8, 1, 5, 32),
F_END
};
@@ -1386,6 +1401,7 @@
.c = {
.dbg_name = "usb_hs1_xcvr_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 60000000),
CLK_INIT(usb_hs1_xcvr_clk.c),
},
};
@@ -1418,6 +1434,7 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8x60, \
+ VDD_DIG_FMAX_MAP1(NOMINAL, 60000000), \
CLK_INIT(i##_clk.c), \
}, \
}
@@ -2014,7 +2031,7 @@
},
};
-#define F_CAM(f, s, d, m, n, v) \
+#define F_CAM(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2022,21 +2039,20 @@
.ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_cam[] = {
- F_CAM( 0, gnd, 1, 0, 0, NONE),
- F_CAM( 6000000, pll8, 4, 1, 16, LOW),
- F_CAM( 8000000, pll8, 4, 1, 12, LOW),
- F_CAM( 12000000, pll8, 4, 1, 8, LOW),
- F_CAM( 16000000, pll8, 4, 1, 6, LOW),
- F_CAM( 19200000, pll8, 4, 1, 5, LOW),
- F_CAM( 24000000, pll8, 4, 1, 4, LOW),
- F_CAM( 32000000, pll8, 4, 1, 3, LOW),
- F_CAM( 48000000, pll8, 4, 1, 2, LOW),
- F_CAM( 64000000, pll8, 3, 1, 2, LOW),
- F_CAM( 96000000, pll8, 4, 0, 0, NOMINAL),
- F_CAM(128000000, pll8, 3, 0, 0, NOMINAL),
+ F_CAM( 0, gnd, 1, 0, 0),
+ F_CAM( 6000000, pll8, 4, 1, 16),
+ F_CAM( 8000000, pll8, 4, 1, 12),
+ F_CAM( 12000000, pll8, 4, 1, 8),
+ F_CAM( 16000000, pll8, 4, 1, 6),
+ F_CAM( 19200000, pll8, 4, 1, 5),
+ F_CAM( 24000000, pll8, 4, 1, 4),
+ F_CAM( 32000000, pll8, 4, 1, 3),
+ F_CAM( 48000000, pll8, 4, 1, 2),
+ F_CAM( 64000000, pll8, 3, 1, 2),
+ F_CAM( 96000000, pll8, 4, 0, 0),
+ F_CAM(128000000, pll8, 3, 0, 0),
F_END
};
@@ -2057,21 +2073,21 @@
.c = {
.dbg_name = "cam_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP2(LOW, 64000000, NOMINAL, 128000000),
CLK_INIT(cam_clk.c),
},
};
-#define F_CSI(f, s, d, v) \
+#define F_CSI(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_csi[] = {
- F_CSI( 0, gnd, 1, NONE),
- F_CSI(192000000, pll8, 2, LOW),
- F_CSI(384000000, pll8, 1, NOMINAL),
+ F_CSI( 0, gnd, 1),
+ F_CSI(192000000, pll8, 2),
+ F_CSI(384000000, pll8, 1),
F_END
};
@@ -2089,6 +2105,7 @@
.c = {
.dbg_name = "csi_src_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP2(LOW, 192000000, NOMINAL, 384000000),
CLK_INIT(csi_src_clk.c),
},
};
@@ -2178,7 +2195,7 @@
},
};
-#define F_GFX2D(f, s, m, n, v) \
+#define F_GFX2D(f, s, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2186,22 +2203,21 @@
.ns_val = NS_MND_BANKED4(20, 16, n, m, 3, 0, s##_to_mm_mux), \
.ctl_val = CC_BANKED(9, 6, n), \
.mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gfx2d[] = {
- F_GFX2D( 0, gnd, 0, 0, NONE),
- F_GFX2D( 27000000, pxo, 0, 0, LOW),
- F_GFX2D( 48000000, pll8, 1, 8, LOW),
- F_GFX2D( 54857000, pll8, 1, 7, LOW),
- F_GFX2D( 64000000, pll8, 1, 6, LOW),
- F_GFX2D( 76800000, pll8, 1, 5, LOW),
- F_GFX2D( 96000000, pll8, 1, 4, LOW),
- F_GFX2D(128000000, pll8, 1, 3, NOMINAL),
- F_GFX2D(145455000, pll2, 2, 11, NOMINAL),
- F_GFX2D(160000000, pll2, 1, 5, NOMINAL),
- F_GFX2D(177778000, pll2, 2, 9, NOMINAL),
- F_GFX2D(200000000, pll2, 1, 4, NOMINAL),
- F_GFX2D(228571000, pll2, 2, 7, HIGH),
+ F_GFX2D( 0, gnd, 0, 0),
+ F_GFX2D( 27000000, pxo, 0, 0),
+ F_GFX2D( 48000000, pll8, 1, 8),
+ F_GFX2D( 54857000, pll8, 1, 7),
+ F_GFX2D( 64000000, pll8, 1, 6),
+ F_GFX2D( 76800000, pll8, 1, 5),
+ F_GFX2D( 96000000, pll8, 1, 4),
+ F_GFX2D(128000000, pll8, 1, 3),
+ F_GFX2D(145455000, pll2, 2, 11),
+ F_GFX2D(160000000, pll2, 1, 5),
+ F_GFX2D(177778000, pll2, 2, 9),
+ F_GFX2D(200000000, pll2, 1, 4),
+ F_GFX2D(228571000, pll2, 2, 7),
F_END
};
@@ -2241,6 +2257,8 @@
.c = {
.dbg_name = "gfx2d0_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
+ HIGH, 228571000),
CLK_INIT(gfx2d0_clk.c),
},
};
@@ -2281,11 +2299,13 @@
.c = {
.dbg_name = "gfx2d1_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
+ HIGH, 228571000),
CLK_INIT(gfx2d1_clk.c),
},
};
-#define F_GFX3D(f, s, m, n, v) \
+#define F_GFX3D(f, s, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2293,24 +2313,23 @@
.ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \
.ctl_val = CC_BANKED(9, 6, n), \
.mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gfx3d[] = {
- F_GFX3D( 0, gnd, 0, 0, NONE),
- F_GFX3D( 27000000, pxo, 0, 0, LOW),
- F_GFX3D( 48000000, pll8, 1, 8, LOW),
- F_GFX3D( 54857000, pll8, 1, 7, LOW),
- F_GFX3D( 64000000, pll8, 1, 6, LOW),
- F_GFX3D( 76800000, pll8, 1, 5, LOW),
- F_GFX3D( 96000000, pll8, 1, 4, LOW),
- F_GFX3D(128000000, pll8, 1, 3, NOMINAL),
- F_GFX3D(145455000, pll2, 2, 11, NOMINAL),
- F_GFX3D(160000000, pll2, 1, 5, NOMINAL),
- F_GFX3D(177778000, pll2, 2, 9, NOMINAL),
- F_GFX3D(200000000, pll2, 1, 4, NOMINAL),
- F_GFX3D(228571000, pll2, 2, 7, HIGH),
- F_GFX3D(266667000, pll2, 1, 3, HIGH),
- F_GFX3D(320000000, pll2, 2, 5, HIGH),
+ F_GFX3D( 0, gnd, 0, 0),
+ F_GFX3D( 27000000, pxo, 0, 0),
+ F_GFX3D( 48000000, pll8, 1, 8),
+ F_GFX3D( 54857000, pll8, 1, 7),
+ F_GFX3D( 64000000, pll8, 1, 6),
+ F_GFX3D( 76800000, pll8, 1, 5),
+ F_GFX3D( 96000000, pll8, 1, 4),
+ F_GFX3D(128000000, pll8, 1, 3),
+ F_GFX3D(145455000, pll2, 2, 11),
+ F_GFX3D(160000000, pll2, 1, 5),
+ F_GFX3D(177778000, pll2, 2, 9),
+ F_GFX3D(200000000, pll2, 1, 4),
+ F_GFX3D(228571000, pll2, 2, 7),
+ F_GFX3D(266667000, pll2, 1, 3),
+ F_GFX3D(320000000, pll2, 2, 5),
F_END
};
@@ -2350,12 +2369,14 @@
.c = {
.dbg_name = "gfx3d_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP3(LOW, 96000000, NOMINAL, 200000000,
+ HIGH, 320000000),
CLK_INIT(gfx3d_clk.c),
.depends = &gmem_axi_clk.c,
},
};
-#define F_IJPEG(f, s, d, m, n, v) \
+#define F_IJPEG(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2363,19 +2384,18 @@
.ns_val = NS_MM(23, 16, n, m, 15, 12, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!n, \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_ijpeg[] = {
- F_IJPEG( 0, gnd, 1, 0, 0, NONE),
- F_IJPEG( 27000000, pxo, 1, 0, 0, LOW),
- F_IJPEG( 36570000, pll8, 1, 2, 21, LOW),
- F_IJPEG( 54860000, pll8, 7, 0, 0, LOW),
- F_IJPEG( 96000000, pll8, 4, 0, 0, LOW),
- F_IJPEG(109710000, pll8, 1, 2, 7, LOW),
- F_IJPEG(128000000, pll8, 3, 0, 0, NOMINAL),
- F_IJPEG(153600000, pll8, 1, 2, 5, NOMINAL),
- F_IJPEG(200000000, pll2, 4, 0, 0, NOMINAL),
- F_IJPEG(228571000, pll2, 1, 2, 7, NOMINAL),
+ F_IJPEG( 0, gnd, 1, 0, 0),
+ F_IJPEG( 27000000, pxo, 1, 0, 0),
+ F_IJPEG( 36570000, pll8, 1, 2, 21),
+ F_IJPEG( 54860000, pll8, 7, 0, 0),
+ F_IJPEG( 96000000, pll8, 4, 0, 0),
+ F_IJPEG(109710000, pll8, 1, 2, 7),
+ F_IJPEG(128000000, pll8, 3, 0, 0),
+ F_IJPEG(153600000, pll8, 1, 2, 5),
+ F_IJPEG(200000000, pll2, 4, 0, 0),
+ F_IJPEG(228571000, pll2, 1, 2, 7),
F_END
};
@@ -2399,25 +2419,25 @@
.c = {
.dbg_name = "ijpeg_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP2(LOW, 110000000, NOMINAL, 228571000),
CLK_INIT(ijpeg_clk.c),
.depends = &ijpeg_axi_clk.c,
},
};
-#define F_JPEGD(f, s, d, v) \
+#define F_JPEGD(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_jpegd[] = {
- F_JPEGD( 0, gnd, 1, NONE),
- F_JPEGD( 64000000, pll8, 6, LOW),
- F_JPEGD( 76800000, pll8, 5, LOW),
- F_JPEGD( 96000000, pll8, 4, LOW),
- F_JPEGD(160000000, pll2, 5, NOMINAL),
- F_JPEGD(200000000, pll2, 4, NOMINAL),
+ F_JPEGD( 0, gnd, 1),
+ F_JPEGD( 64000000, pll8, 6),
+ F_JPEGD( 76800000, pll8, 5),
+ F_JPEGD( 96000000, pll8, 4),
+ F_JPEGD(160000000, pll2, 5),
+ F_JPEGD(200000000, pll2, 4),
F_END
};
@@ -2439,12 +2459,13 @@
.c = {
.dbg_name = "jpegd_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
CLK_INIT(jpegd_clk.c),
.depends = &jpegd_axi_clk.c,
},
};
-#define F_MDP(f, s, m, n, v) \
+#define F_MDP(f, s, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2452,24 +2473,23 @@
.ns_val = NS_MND_BANKED8(22, 14, n, m, 3, 0, s##_to_mm_mux), \
.ctl_val = CC_BANKED(9, 6, n), \
.mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_mdp[] = {
- F_MDP( 0, gnd, 0, 0, NONE),
- F_MDP( 9600000, pll8, 1, 40, LOW),
- F_MDP( 13710000, pll8, 1, 28, LOW),
- F_MDP( 27000000, pxo, 0, 0, LOW),
- F_MDP( 29540000, pll8, 1, 13, LOW),
- F_MDP( 34910000, pll8, 1, 11, LOW),
- F_MDP( 38400000, pll8, 1, 10, LOW),
- F_MDP( 59080000, pll8, 2, 13, LOW),
- F_MDP( 76800000, pll8, 1, 5, LOW),
- F_MDP( 85330000, pll8, 2, 9, LOW),
- F_MDP( 96000000, pll8, 1, 4, NOMINAL),
- F_MDP(128000000, pll8, 1, 3, NOMINAL),
- F_MDP(160000000, pll2, 1, 5, NOMINAL),
- F_MDP(177780000, pll2, 2, 9, NOMINAL),
- F_MDP(200000000, pll2, 1, 4, NOMINAL),
+ F_MDP( 0, gnd, 0, 0),
+ F_MDP( 9600000, pll8, 1, 40),
+ F_MDP( 13710000, pll8, 1, 28),
+ F_MDP( 27000000, pxo, 0, 0),
+ F_MDP( 29540000, pll8, 1, 13),
+ F_MDP( 34910000, pll8, 1, 11),
+ F_MDP( 38400000, pll8, 1, 10),
+ F_MDP( 59080000, pll8, 2, 13),
+ F_MDP( 76800000, pll8, 1, 5),
+ F_MDP( 85330000, pll8, 2, 9),
+ F_MDP( 96000000, pll8, 1, 4),
+ F_MDP(128000000, pll8, 1, 3),
+ F_MDP(160000000, pll2, 1, 5),
+ F_MDP(177780000, pll2, 2, 9),
+ F_MDP(200000000, pll2, 1, 4),
F_END
};
@@ -2509,20 +2529,21 @@
.c = {
.dbg_name = "mdp_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP3(LOW, 85330000, NOMINAL, 200000000,
+ HIGH, 228571000),
CLK_INIT(mdp_clk.c),
.depends = &mdp_axi_clk.c,
},
};
-#define F_MDP_VSYNC(f, s, v) \
+#define F_MDP_VSYNC(f, s) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_SRC_SEL(13, 13, s##_to_bb_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_mdp_vsync[] = {
- F_MDP_VSYNC(27000000, pxo, LOW),
+ F_MDP_VSYNC(27000000, pxo),
F_END
};
@@ -2543,11 +2564,12 @@
.c = {
.dbg_name = "mdp_vsync_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP1(LOW, 27000000),
CLK_INIT(mdp_vsync_clk.c),
},
};
-#define F_PIXEL_MDP(f, s, d, m, n, v) \
+#define F_PIXEL_MDP(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2555,21 +2577,20 @@
.ns_val = NS_MM(31, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_pixel_mdp[] = {
- F_PIXEL_MDP( 0, gnd, 1, 0, 0, NONE),
- F_PIXEL_MDP( 25600000, pll8, 3, 1, 5, LOW),
- F_PIXEL_MDP( 42667000, pll8, 1, 1, 9, LOW),
- F_PIXEL_MDP( 43192000, pll8, 1, 64, 569, LOW),
- F_PIXEL_MDP( 48000000, pll8, 4, 1, 2, LOW),
- F_PIXEL_MDP( 53990000, pll8, 2, 169, 601, LOW),
- F_PIXEL_MDP( 64000000, pll8, 2, 1, 3, LOW),
- F_PIXEL_MDP( 69300000, pll8, 1, 231, 1280, LOW),
- F_PIXEL_MDP( 76800000, pll8, 1, 1, 5, LOW),
- F_PIXEL_MDP( 85333000, pll8, 1, 2, 9, LOW),
- F_PIXEL_MDP(106500000, pll8, 1, 71, 256, NOMINAL),
- F_PIXEL_MDP(109714000, pll8, 1, 2, 7, NOMINAL),
+ F_PIXEL_MDP( 0, gnd, 1, 0, 0),
+ F_PIXEL_MDP( 25600000, pll8, 3, 1, 5),
+ F_PIXEL_MDP( 42667000, pll8, 1, 1, 9),
+ F_PIXEL_MDP( 43192000, pll8, 1, 64, 569),
+ F_PIXEL_MDP( 48000000, pll8, 4, 1, 2),
+ F_PIXEL_MDP( 53990000, pll8, 2, 169, 601),
+ F_PIXEL_MDP( 64000000, pll8, 2, 1, 3),
+ F_PIXEL_MDP( 69300000, pll8, 1, 231, 1280),
+ F_PIXEL_MDP( 76800000, pll8, 1, 1, 5),
+ F_PIXEL_MDP( 85333000, pll8, 1, 2, 9),
+ F_PIXEL_MDP(106500000, pll8, 1, 71, 256),
+ F_PIXEL_MDP(109714000, pll8, 1, 2, 7),
F_END
};
@@ -2593,6 +2614,7 @@
.c = {
.dbg_name = "pixel_mdp_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP2(LOW, 85333000, NOMINAL, 170000000),
CLK_INIT(pixel_mdp_clk.c),
},
};
@@ -2612,29 +2634,28 @@
},
};
-#define F_ROT(f, s, d, v) \
+#define F_ROT(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_DIVSRC_BANKED(29, 26, 25, 22, d, \
21, 19, 18, 16, s##_to_mm_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_rot[] = {
- F_ROT( 0, gnd, 1, NONE),
- F_ROT( 27000000, pxo, 1, LOW),
- F_ROT( 29540000, pll8, 13, LOW),
- F_ROT( 32000000, pll8, 12, LOW),
- F_ROT( 38400000, pll8, 10, LOW),
- F_ROT( 48000000, pll8, 8, LOW),
- F_ROT( 54860000, pll8, 7, LOW),
- F_ROT( 64000000, pll8, 6, LOW),
- F_ROT( 76800000, pll8, 5, LOW),
- F_ROT( 96000000, pll8, 4, NOMINAL),
- F_ROT(100000000, pll2, 8, NOMINAL),
- F_ROT(114290000, pll2, 7, NOMINAL),
- F_ROT(133330000, pll2, 6, NOMINAL),
- F_ROT(160000000, pll2, 5, NOMINAL),
+ F_ROT( 0, gnd, 1),
+ F_ROT( 27000000, pxo, 1),
+ F_ROT( 29540000, pll8, 13),
+ F_ROT( 32000000, pll8, 12),
+ F_ROT( 38400000, pll8, 10),
+ F_ROT( 48000000, pll8, 8),
+ F_ROT( 54860000, pll8, 7),
+ F_ROT( 64000000, pll8, 6),
+ F_ROT( 76800000, pll8, 5),
+ F_ROT( 96000000, pll8, 4),
+ F_ROT(100000000, pll2, 8),
+ F_ROT(114290000, pll2, 7),
+ F_ROT(133330000, pll2, 6),
+ F_ROT(160000000, pll2, 5),
F_END
};
@@ -2666,12 +2687,13 @@
.c = {
.dbg_name = "rot_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP2(LOW, 80000000, NOMINAL, 160000000),
CLK_INIT(rot_clk.c),
.depends = &rot_axi_clk.c,
},
};
-#define F_TV(f, s, p_r, d, m, n, v) \
+#define F_TV(f, s, p_r, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2679,7 +2701,6 @@
.ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
.extra_freq_data = p_r, \
}
/* Switching TV freqs requires PLL reconfiguration. */
@@ -2691,12 +2712,12 @@
[4] = PLL_RATE(44, 0, 0, 2, 4, 0x6248F), /* 297000000 Hz */
};
static struct clk_freq_tbl clk_tbl_tv[] = {
- F_TV( 0, gnd, &mm_pll2_rate[0], 1, 0, 0, NONE),
- F_TV( 25200000, pll3, &mm_pll2_rate[0], 2, 0, 0, LOW),
- F_TV( 27000000, pll3, &mm_pll2_rate[1], 2, 0, 0, LOW),
- F_TV( 27030000, pll3, &mm_pll2_rate[2], 4, 0, 0, LOW),
- F_TV( 74250000, pll3, &mm_pll2_rate[3], 2, 0, 0, NOMINAL),
- F_TV(148500000, pll3, &mm_pll2_rate[4], 2, 0, 0, NOMINAL),
+ F_TV( 0, gnd, &mm_pll2_rate[0], 1, 0, 0),
+ F_TV( 25200000, pll3, &mm_pll2_rate[0], 2, 0, 0),
+ F_TV( 27000000, pll3, &mm_pll2_rate[1], 2, 0, 0),
+ F_TV( 27030000, pll3, &mm_pll2_rate[2], 4, 0, 0),
+ F_TV( 74250000, pll3, &mm_pll2_rate[3], 2, 0, 0),
+ F_TV(148500000, pll3, &mm_pll2_rate[4], 2, 0, 0),
F_END
};
@@ -2716,6 +2737,7 @@
.c = {
.dbg_name = "tv_src_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP2(LOW, 27030000, NOMINAL, 149000000),
CLK_INIT(tv_src_clk.c),
},
};
@@ -2802,7 +2824,7 @@
},
};
-#define F_VCODEC(f, s, m, n, v) \
+#define F_VCODEC(f, s, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2810,18 +2832,17 @@
.ns_val = NS_MM(18, 11, n, m, 0, 0, 1, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_vcodec[] = {
- F_VCODEC( 0, gnd, 0, 0, NONE),
- F_VCODEC( 27000000, pxo, 0, 0, LOW),
- F_VCODEC( 32000000, pll8, 1, 12, LOW),
- F_VCODEC( 48000000, pll8, 1, 8, LOW),
- F_VCODEC( 54860000, pll8, 1, 7, LOW),
- F_VCODEC( 96000000, pll8, 1, 4, LOW),
- F_VCODEC(133330000, pll2, 1, 6, NOMINAL),
- F_VCODEC(200000000, pll2, 1, 4, NOMINAL),
- F_VCODEC(228570000, pll2, 2, 7, HIGH),
+ F_VCODEC( 0, gnd, 0, 0),
+ F_VCODEC( 27000000, pxo, 0, 0),
+ F_VCODEC( 32000000, pll8, 1, 12),
+ F_VCODEC( 48000000, pll8, 1, 8),
+ F_VCODEC( 54860000, pll8, 1, 7),
+ F_VCODEC( 96000000, pll8, 1, 4),
+ F_VCODEC(133330000, pll2, 1, 6),
+ F_VCODEC(200000000, pll2, 1, 4),
+ F_VCODEC(228570000, pll2, 2, 7),
F_END
};
@@ -2845,29 +2866,30 @@
.c = {
.dbg_name = "vcodec_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
+ HIGH, 228571000),
CLK_INIT(vcodec_clk.c),
.depends = &vcodec_axi_clk.c,
},
};
-#define F_VPE(f, s, d, v) \
+#define F_VPE(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_vpe[] = {
- F_VPE( 0, gnd, 1, NONE),
- F_VPE( 27000000, pxo, 1, LOW),
- F_VPE( 34909000, pll8, 11, LOW),
- F_VPE( 38400000, pll8, 10, LOW),
- F_VPE( 64000000, pll8, 6, LOW),
- F_VPE( 76800000, pll8, 5, LOW),
- F_VPE( 96000000, pll8, 4, NOMINAL),
- F_VPE(100000000, pll2, 8, NOMINAL),
- F_VPE(160000000, pll2, 5, NOMINAL),
- F_VPE(200000000, pll2, 4, HIGH),
+ F_VPE( 0, gnd, 1),
+ F_VPE( 27000000, pxo, 1),
+ F_VPE( 34909000, pll8, 11),
+ F_VPE( 38400000, pll8, 10),
+ F_VPE( 64000000, pll8, 6),
+ F_VPE( 76800000, pll8, 5),
+ F_VPE( 96000000, pll8, 4),
+ F_VPE(100000000, pll2, 8),
+ F_VPE(160000000, pll2, 5),
+ F_VPE(200000000, pll2, 4),
F_END
};
@@ -2889,12 +2911,14 @@
.c = {
.dbg_name = "vpe_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP3(LOW, 76800000, NOMINAL, 160000000,
+ HIGH, 200000000),
CLK_INIT(vpe_clk.c),
.depends = &vpe_axi_clk.c,
},
};
-#define F_VFE(f, s, d, m, n, v) \
+#define F_VFE(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2902,26 +2926,25 @@
.ns_val = NS_MM(23, 16, n, m, 11, 10, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_vfe[] = {
- F_VFE( 0, gnd, 1, 0, 0, NONE),
- F_VFE( 13960000, pll8, 1, 2, 55, LOW),
- F_VFE( 27000000, pxo, 1, 0, 0, LOW),
- F_VFE( 36570000, pll8, 1, 2, 21, LOW),
- F_VFE( 38400000, pll8, 2, 1, 5, LOW),
- F_VFE( 45180000, pll8, 1, 2, 17, LOW),
- F_VFE( 48000000, pll8, 2, 1, 4, LOW),
- F_VFE( 54860000, pll8, 1, 1, 7, LOW),
- F_VFE( 64000000, pll8, 2, 1, 3, LOW),
- F_VFE( 76800000, pll8, 1, 1, 5, LOW),
- F_VFE( 96000000, pll8, 2, 1, 2, LOW),
- F_VFE(109710000, pll8, 1, 2, 7, LOW),
- F_VFE(128000000, pll8, 1, 1, 3, NOMINAL),
- F_VFE(153600000, pll8, 1, 2, 5, NOMINAL),
- F_VFE(200000000, pll2, 2, 1, 2, NOMINAL),
- F_VFE(228570000, pll2, 1, 2, 7, NOMINAL),
- F_VFE(266667000, pll2, 1, 1, 3, HIGH),
+ F_VFE( 0, gnd, 1, 0, 0),
+ F_VFE( 13960000, pll8, 1, 2, 55),
+ F_VFE( 27000000, pxo, 1, 0, 0),
+ F_VFE( 36570000, pll8, 1, 2, 21),
+ F_VFE( 38400000, pll8, 2, 1, 5),
+ F_VFE( 45180000, pll8, 1, 2, 17),
+ F_VFE( 48000000, pll8, 2, 1, 4),
+ F_VFE( 54860000, pll8, 1, 1, 7),
+ F_VFE( 64000000, pll8, 2, 1, 3),
+ F_VFE( 76800000, pll8, 1, 1, 5),
+ F_VFE( 96000000, pll8, 2, 1, 2),
+ F_VFE(109710000, pll8, 1, 2, 7),
+ F_VFE(128000000, pll8, 1, 1, 3),
+ F_VFE(153600000, pll8, 1, 2, 5),
+ F_VFE(200000000, pll2, 2, 1, 2),
+ F_VFE(228570000, pll2, 1, 2, 7),
+ F_VFE(266667000, pll2, 1, 1, 3),
F_END
};
@@ -2945,6 +2968,8 @@
.c = {
.dbg_name = "vfe_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP3(LOW, 110000000, NOMINAL, 228570000,
+ HIGH, 266667000),
CLK_INIT(vfe_clk.c),
.depends = &vfe_axi_clk.c,
},
@@ -2987,27 +3012,26 @@
/*
* Low Power Audio Clocks
*/
-#define F_AIF_OSR(f, s, d, m, n, v) \
+#define F_AIF_OSR(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(8, m, 0, n), \
.ns_val = NS(31, 24, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_aif_osr[] = {
- F_AIF_OSR( 0, gnd, 1, 0, 0, NONE),
- F_AIF_OSR( 768000, pll4, 4, 1, 176, LOW),
- F_AIF_OSR( 1024000, pll4, 4, 1, 132, LOW),
- F_AIF_OSR( 1536000, pll4, 4, 1, 88, LOW),
- F_AIF_OSR( 2048000, pll4, 4, 1, 66, LOW),
- F_AIF_OSR( 3072000, pll4, 4, 1, 44, LOW),
- F_AIF_OSR( 4096000, pll4, 4, 1, 33, LOW),
- F_AIF_OSR( 6144000, pll4, 4, 1, 22, LOW),
- F_AIF_OSR( 8192000, pll4, 2, 1, 33, LOW),
- F_AIF_OSR(12288000, pll4, 4, 1, 11, LOW),
- F_AIF_OSR(24576000, pll4, 2, 1, 11, LOW),
+ F_AIF_OSR( 0, gnd, 1, 0, 0),
+ F_AIF_OSR( 768000, pll4, 4, 1, 176),
+ F_AIF_OSR( 1024000, pll4, 4, 1, 132),
+ F_AIF_OSR( 1536000, pll4, 4, 1, 88),
+ F_AIF_OSR( 2048000, pll4, 4, 1, 66),
+ F_AIF_OSR( 3072000, pll4, 4, 1, 44),
+ F_AIF_OSR( 4096000, pll4, 4, 1, 33),
+ F_AIF_OSR( 6144000, pll4, 4, 1, 22),
+ F_AIF_OSR( 8192000, pll4, 2, 1, 33),
+ F_AIF_OSR(12288000, pll4, 4, 1, 11),
+ F_AIF_OSR(24576000, pll4, 2, 1, 11),
F_END
};
@@ -3032,6 +3056,7 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8x60, \
+ VDD_DIG_FMAX_MAP1(LOW, 24576000), \
CLK_INIT(i##_clk.c), \
}, \
}
@@ -3094,28 +3119,27 @@
static CLK_AIF_BIT(spare_i2s_spkr_bit, LCC_SPARE_I2S_SPKR_NS_REG,
LCC_SPARE_I2S_SPKR_STATUS_REG);
-#define F_PCM(f, s, d, m, n, v) \
+#define F_PCM(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD16(m, n), \
.ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_pcm[] = {
- F_PCM( 0, gnd, 1, 0, 0, NONE),
- F_PCM( 512000, pll4, 4, 1, 264, LOW),
- F_PCM( 768000, pll4, 4, 1, 176, LOW),
- F_PCM( 1024000, pll4, 4, 1, 132, LOW),
- F_PCM( 1536000, pll4, 4, 1, 88, LOW),
- F_PCM( 2048000, pll4, 4, 1, 66, LOW),
- F_PCM( 3072000, pll4, 4, 1, 44, LOW),
- F_PCM( 4096000, pll4, 4, 1, 33, LOW),
- F_PCM( 6144000, pll4, 4, 1, 22, LOW),
- F_PCM( 8192000, pll4, 2, 1, 33, LOW),
- F_PCM(12288000, pll4, 4, 1, 11, LOW),
- F_PCM(24580000, pll4, 2, 1, 11, LOW),
+ F_PCM( 0, gnd, 1, 0, 0),
+ F_PCM( 512000, pll4, 4, 1, 264),
+ F_PCM( 768000, pll4, 4, 1, 176),
+ F_PCM( 1024000, pll4, 4, 1, 132),
+ F_PCM( 1536000, pll4, 4, 1, 88),
+ F_PCM( 2048000, pll4, 4, 1, 66),
+ F_PCM( 3072000, pll4, 4, 1, 44),
+ F_PCM( 4096000, pll4, 4, 1, 33),
+ F_PCM( 6144000, pll4, 4, 1, 22),
+ F_PCM( 8192000, pll4, 2, 1, 33),
+ F_PCM(12288000, pll4, 4, 1, 11),
+ F_PCM(24580000, pll4, 2, 1, 11),
F_END
};
@@ -3139,6 +3163,7 @@
.c = {
.dbg_name = "pcm_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP1(LOW, 24580000),
CLK_INIT(pcm_clk.c),
},
};
@@ -3649,7 +3674,7 @@
CLK_LOOKUP("mdp_vsync_clk", mdp_vsync_clk.c, NULL),
CLK_LOOKUP("pixel_lcdc_clk", pixel_lcdc_clk.c, NULL),
CLK_LOOKUP("pixel_mdp_clk", pixel_mdp_clk.c, NULL),
- CLK_LOOKUP("rot_clk", rot_clk.c, NULL),
+ CLK_LOOKUP("core_clk", rot_clk.c, "msm_rotator.0"),
CLK_LOOKUP("core_clk", rot_clk.c, "footswitch-8x60.6"),
CLK_LOOKUP("tv_enc_clk", tv_enc_clk.c, NULL),
CLK_LOOKUP("tv_dac_clk", tv_dac_clk.c, NULL),
@@ -3694,7 +3719,7 @@
CLK_LOOKUP("mdp_pclk", mdp_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", mdp_p_clk.c, "footswitch-8x60.4"),
CLK_LOOKUP("iface_clk", smmu_p_clk.c, "msm_iommu"),
- CLK_LOOKUP("rotator_pclk", rot_p_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", rot_p_clk.c, "msm_rotator.0"),
CLK_LOOKUP("iface_clk", rot_p_clk.c, "footswitch-8x60.6"),
CLK_LOOKUP("tv_enc_pclk", tv_enc_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "msm_vidc.0"),
@@ -3843,7 +3868,6 @@
/* Local clock driver initialization. */
static void __init msm8660_clock_init(void)
{
- soc_update_sys_vdd = msm8660_update_sys_vdd;
xo_pxo = msm_xo_get(MSM_XO_PXO, "clock-8x60");
if (IS_ERR(xo_pxo)) {
pr_err("%s: msm_xo_get(PXO) failed.\n", __func__);
@@ -3855,7 +3879,7 @@
BUG();
}
- local_vote_sys_vdd(HIGH);
+ vote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
/* Initialize clock registers. */
reg_init();
@@ -3893,11 +3917,7 @@
if (WARN(rc, "mmfpb_a_clk not enabled (%d)\n", rc))
return rc;
- /* Remove temporary vote for HIGH vdd_dig. */
- rc = local_unvote_sys_vdd(HIGH);
- WARN(rc, "local_unvote_sys_vdd(HIGH) failed (%d)\n", rc);
-
- return rc;
+ return unvote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
}
struct clock_init_data msm8x60_clock_init_data __initdata = {
diff --git a/arch/arm/mach-msm/clock-9615.c b/arch/arm/mach-msm/clock-9615.c
index 306de34..dca8268 100644
--- a/arch/arm/mach-msm/clock-9615.c
+++ b/arch/arm/mach-msm/clock-9615.c
@@ -185,6 +185,36 @@
#define NS_SRC_SEL(s_msb, s_lsb, s) \
BVAL(s_msb, s_lsb, s)
+enum vdd_dig_levels {
+ VDD_DIG_NONE,
+ VDD_DIG_LOW,
+ VDD_DIG_NOMINAL,
+ VDD_DIG_HIGH
+};
+
+static int set_vdd_dig(struct clk_vdd_class *vdd_class, int level)
+{
+ /* TODO: Update these voltages when info becomes available. */
+ static const int vdd_uv[] = {
+ [VDD_DIG_NONE] = 1150000,
+ [VDD_DIG_LOW] = 1150000,
+ [VDD_DIG_NOMINAL] = 1150000,
+ [VDD_DIG_HIGH] = 1150000
+ };
+
+ return rpm_vreg_set_voltage(RPM_VREG_ID_PM8018_S1, RPM_VREG_VOTER3,
+ vdd_uv[level], vdd_uv[VDD_DIG_HIGH], 1);
+}
+
+static DEFINE_VDD_CLASS(vdd_dig, set_vdd_dig);
+
+#define VDD_DIG_FMAX_MAP1(l1, f1) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1)
+#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1), \
+ .fmax[VDD_DIG_##l2] = (f2)
/*
* Clock Descriptions
@@ -283,24 +313,6 @@
},
};
-/*
- * SoC-specific functions required by clock-local driver
- */
-
-/* TODO: Update these voltages when info becomes available. */
-/* Update the sys_vdd voltage given a level. */
-static int msm9615_update_sys_vdd(enum sys_vdd_level level)
-{
- static const int vdd_uv[] = {
- [NONE...LOW] = 1150000,
- [NOMINAL] = 1150000,
- [HIGH] = 1150000,
- };
-
- return rpm_vreg_set_voltage(RPM_VREG_ID_PM8018_S1, RPM_VREG_VOTER3,
- vdd_uv[level], vdd_uv[HIGH], 1);
-}
-
static int soc_clk_reset(struct clk *clk, enum clk_reset_action action)
{
return branch_reset(&to_rcg_clk(clk)->b, action);
@@ -309,7 +321,7 @@
static struct clk_ops clk_ops_rcg_9615 = {
.enable = rcg_clk_enable,
.disable = rcg_clk_disable,
- .auto_off = rcg_clk_auto_off,
+ .auto_off = rcg_clk_disable,
.set_rate = rcg_clk_set_rate,
.set_min_rate = rcg_clk_set_min_rate,
.get_rate = rcg_clk_get_rate,
@@ -324,7 +336,7 @@
static struct clk_ops clk_ops_branch = {
.enable = branch_clk_enable,
.disable = branch_clk_disable,
- .auto_off = branch_clk_auto_off,
+ .auto_off = branch_clk_disable,
.is_enabled = branch_clk_is_enabled,
.reset = branch_clk_reset,
.is_local = local_clk_is_local,
@@ -355,33 +367,33 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_9615, \
+ VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 64000000), \
CLK_INIT(i##_clk.c), \
}, \
}
-#define F_GSBI_UART(f, s, d, m, n, v) \
+#define F_GSBI_UART(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD16(m, n), \
.ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gsbi_uart[] = {
- F_GSBI_UART( 0, gnd, 1, 0, 0, NONE),
- F_GSBI_UART( 3686400, pll8, 1, 6, 625, LOW),
- F_GSBI_UART( 7372800, pll8, 1, 12, 625, LOW),
- F_GSBI_UART(14745600, pll8, 1, 24, 625, LOW),
- F_GSBI_UART(16000000, pll8, 4, 1, 6, LOW),
- F_GSBI_UART(24000000, pll8, 4, 1, 4, LOW),
- F_GSBI_UART(32000000, pll8, 4, 1, 3, LOW),
- F_GSBI_UART(40000000, pll8, 1, 5, 48, NOMINAL),
- F_GSBI_UART(46400000, pll8, 1, 29, 240, NOMINAL),
- F_GSBI_UART(48000000, pll8, 4, 1, 2, NOMINAL),
- F_GSBI_UART(51200000, pll8, 1, 2, 15, NOMINAL),
- F_GSBI_UART(56000000, pll8, 1, 7, 48, NOMINAL),
- F_GSBI_UART(58982400, pll8, 1, 96, 625, NOMINAL),
- F_GSBI_UART(64000000, pll8, 2, 1, 3, NOMINAL),
+ F_GSBI_UART( 0, gnd, 1, 0, 0),
+ F_GSBI_UART( 3686400, pll8, 1, 6, 625),
+ F_GSBI_UART( 7372800, pll8, 1, 12, 625),
+ F_GSBI_UART(14745600, pll8, 1, 24, 625),
+ F_GSBI_UART(16000000, pll8, 4, 1, 6),
+ F_GSBI_UART(24000000, pll8, 4, 1, 4),
+ F_GSBI_UART(32000000, pll8, 4, 1, 3),
+ F_GSBI_UART(40000000, pll8, 1, 5, 48),
+ F_GSBI_UART(46400000, pll8, 1, 29, 240),
+ F_GSBI_UART(48000000, pll8, 4, 1, 2),
+ F_GSBI_UART(51200000, pll8, 1, 2, 15),
+ F_GSBI_UART(56000000, pll8, 1, 7, 48),
+ F_GSBI_UART(58982400, pll8, 1, 96, 625),
+ F_GSBI_UART(64000000, pll8, 2, 1, 3),
F_END
};
@@ -411,28 +423,28 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_9615, \
+ VDD_DIG_FMAX_MAP2(LOW, 24000000, NOMINAL, 52000000), \
CLK_INIT(i##_clk.c), \
}, \
}
-#define F_GSBI_QUP(f, s, d, m, n, v) \
+#define F_GSBI_QUP(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(16, m, 0, n), \
.ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gsbi_qup[] = {
- F_GSBI_QUP( 0, gnd, 1, 0, 0, NONE),
- F_GSBI_QUP( 960000, cxo, 4, 1, 5, LOW),
- F_GSBI_QUP( 4800000, cxo, 4, 0, 1, LOW),
- F_GSBI_QUP( 9600000, cxo, 2, 0, 1, LOW),
- F_GSBI_QUP(15058800, pll8, 1, 2, 51, LOW),
- F_GSBI_QUP(24000000, pll8, 4, 1, 4, LOW),
- F_GSBI_QUP(25600000, pll8, 1, 1, 15, NOMINAL),
- F_GSBI_QUP(48000000, pll8, 4, 1, 2, NOMINAL),
- F_GSBI_QUP(51200000, pll8, 1, 2, 15, NOMINAL),
+ F_GSBI_QUP( 0, gnd, 1, 0, 0),
+ F_GSBI_QUP( 960000, cxo, 4, 1, 5),
+ F_GSBI_QUP( 4800000, cxo, 4, 0, 1),
+ F_GSBI_QUP( 9600000, cxo, 2, 0, 1),
+ F_GSBI_QUP(15058800, pll8, 1, 2, 51),
+ F_GSBI_QUP(24000000, pll8, 4, 1, 4),
+ F_GSBI_QUP(25600000, pll8, 1, 1, 15),
+ F_GSBI_QUP(48000000, pll8, 4, 1, 2),
+ F_GSBI_QUP(51200000, pll8, 1, 2, 15),
F_END
};
@@ -442,16 +454,15 @@
static CLK_GSBI_QUP(gsbi4_qup, 4, CLK_HALT_CFPB_STATEB_REG, 24);
static CLK_GSBI_QUP(gsbi5_qup, 5, CLK_HALT_CFPB_STATEB_REG, 20);
-#define F_PDM(f, s, d, v) \
+#define F_PDM(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_pdm[] = {
- F_PDM( 0, gnd, 1, NONE),
- F_PDM(19200000, cxo, 1, LOW),
+ F_PDM( 0, gnd, 1),
+ F_PDM(19200000, cxo, 1),
F_END
};
@@ -473,6 +484,7 @@
.c = {
.dbg_name = "pdm_clk",
.ops = &clk_ops_rcg_9615,
+ VDD_DIG_FMAX_MAP1(LOW, 19200000),
CLK_INIT(pdm_clk.c),
},
};
@@ -491,14 +503,13 @@
},
};
-#define F_PRNG(f, s, v) \
+#define F_PRNG(f, s) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_prng[] = {
- F_PRNG(32000000, pll8, LOW),
+ F_PRNG(32000000, pll8),
F_END
};
@@ -516,6 +527,7 @@
.c = {
.dbg_name = "prng_clk",
.ops = &clk_ops_rcg_9615,
+ VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 65000000),
CLK_INIT(prng_clk.c),
},
};
@@ -540,45 +552,44 @@
.c = { \
.dbg_name = #name, \
.ops = &clk_ops_rcg_9615, \
+ VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), \
CLK_INIT(name.c), \
}, \
}
-#define F_SDC(f, s, d, m, n, v) \
+#define F_SDC(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(16, m, 0, n), \
.ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_sdc1_2[] = {
- F_SDC( 0, gnd, 1, 0, 0, NONE),
- F_SDC( 144300, cxo, 1, 1, 133, LOW),
- F_SDC( 400000, pll8, 4, 1, 240, LOW),
- F_SDC( 16000000, pll8, 4, 1, 6, LOW),
- F_SDC( 17070000, pll8, 1, 2, 45, LOW),
- F_SDC( 20210000, pll8, 1, 1, 19, LOW),
- F_SDC( 24000000, pll8, 4, 1, 4, LOW),
- F_SDC( 48000000, pll8, 4, 1, 2, NOMINAL),
+ F_SDC( 0, gnd, 1, 0, 0),
+ F_SDC( 144300, cxo, 1, 1, 133),
+ F_SDC( 400000, pll8, 4, 1, 240),
+ F_SDC( 16000000, pll8, 4, 1, 6),
+ F_SDC( 17070000, pll8, 1, 2, 45),
+ F_SDC( 20210000, pll8, 1, 1, 19),
+ F_SDC( 24000000, pll8, 4, 1, 4),
+ F_SDC( 48000000, pll8, 4, 1, 2),
F_END
};
static CLK_SDC(sdc1_clk, 1, 6, clk_tbl_sdc1_2);
static CLK_SDC(sdc2_clk, 2, 5, clk_tbl_sdc1_2);
-#define F_USB(f, s, d, m, n, v) \
+#define F_USB(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(16, m, 0, n), \
.ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_usb[] = {
- F_USB( 0, gnd, 1, 0, 0, NONE),
- F_USB(60000000, pll8, 1, 5, 32, NOMINAL),
+ F_USB( 0, gnd, 1, 0, 0),
+ F_USB(60000000, pll8, 1, 5, 32),
F_END
};
@@ -601,6 +612,7 @@
.c = {
.dbg_name = "usb_hs1_xcvr_clk",
.ops = &clk_ops_rcg_9615,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 60000000),
CLK_INIT(usb_hs1_xcvr_clk.c),
},
};
@@ -624,6 +636,7 @@
.c = {
.dbg_name = "usb_hs1_sys_clk",
.ops = &clk_ops_rcg_9615,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 60000000),
CLK_INIT(usb_hs1_sys_clk.c),
},
};
@@ -647,6 +660,7 @@
.c = {
.dbg_name = "usb_hsic_xcvr_clk",
.ops = &clk_ops_rcg_9615,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 60000000),
CLK_INIT(usb_hsic_xcvr_clk.c),
},
};
@@ -670,13 +684,14 @@
.c = {
.dbg_name = "usb_hsic_sys_clk",
.ops = &clk_ops_rcg_9615,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 60000000),
CLK_INIT(usb_hsic_sys_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_usb_hsic[] = {
- F_USB( 0, gnd, 1, 0, 0, NONE),
- F_USB(480000000, pll14, 1, 0, 1, NOMINAL),
+ F_USB( 0, gnd, 1, 0, 0),
+ F_USB(480000000, pll14, 1, 0, 1),
F_END
};
@@ -699,6 +714,7 @@
.c = {
.dbg_name = "usb_hsic_clk",
.ops = &clk_ops_rcg_9615,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 480000000),
CLK_INIT(usb_hsic_clk.c),
},
};
@@ -980,28 +996,27 @@
/*
* Low Power Audio Clocks
*/
-#define F_AIF_OSR(f, s, d, m, n, v) \
+#define F_AIF_OSR(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(8, m, 0, n), \
.ns_val = NS(31, 24, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_aif_osr[] = {
- F_AIF_OSR( 0, gnd, 1, 0, 0, NONE),
- F_AIF_OSR( 512000, pll4, 4, 1, 192, LOW),
- F_AIF_OSR( 768000, pll4, 4, 1, 128, LOW),
- F_AIF_OSR( 1024000, pll4, 4, 1, 96, LOW),
- F_AIF_OSR( 1536000, pll4, 4, 1, 64, LOW),
- F_AIF_OSR( 2048000, pll4, 4, 1, 48, LOW),
- F_AIF_OSR( 3072000, pll4, 4, 1, 32, LOW),
- F_AIF_OSR( 4096000, pll4, 4, 1, 24, LOW),
- F_AIF_OSR( 6144000, pll4, 4, 1, 16, LOW),
- F_AIF_OSR( 8192000, pll4, 4, 1, 12, LOW),
- F_AIF_OSR(12288000, pll4, 4, 1, 8, LOW),
- F_AIF_OSR(24576000, pll4, 4, 1, 4, LOW),
+ F_AIF_OSR( 0, gnd, 1, 0, 0),
+ F_AIF_OSR( 512000, pll4, 4, 1, 192),
+ F_AIF_OSR( 768000, pll4, 4, 1, 128),
+ F_AIF_OSR( 1024000, pll4, 4, 1, 96),
+ F_AIF_OSR( 1536000, pll4, 4, 1, 64),
+ F_AIF_OSR( 2048000, pll4, 4, 1, 48),
+ F_AIF_OSR( 3072000, pll4, 4, 1, 32),
+ F_AIF_OSR( 4096000, pll4, 4, 1, 24),
+ F_AIF_OSR( 6144000, pll4, 4, 1, 16),
+ F_AIF_OSR( 8192000, pll4, 4, 1, 12),
+ F_AIF_OSR(12288000, pll4, 4, 1, 8),
+ F_AIF_OSR(24576000, pll4, 4, 1, 4),
F_END
};
@@ -1148,28 +1163,27 @@
static CLK_AIF_BIT_DIV(spare_i2s_spkr_bit, LCC_SPARE_I2S_SPKR_NS_REG,
LCC_SPARE_I2S_SPKR_STATUS_REG);
-#define F_PCM(f, s, d, m, n, v) \
+#define F_PCM(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD16(m, n), \
.ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_pcm[] = {
- F_PCM( 0, gnd, 1, 0, 0, NONE),
- F_PCM( 512000, pll4, 4, 1, 192, LOW),
- F_PCM( 768000, pll4, 4, 1, 128, LOW),
- F_PCM( 1024000, pll4, 4, 1, 96, LOW),
- F_PCM( 1536000, pll4, 4, 1, 64, LOW),
- F_PCM( 2048000, pll4, 4, 1, 48, LOW),
- F_PCM( 3072000, pll4, 4, 1, 32, LOW),
- F_PCM( 4096000, pll4, 4, 1, 24, LOW),
- F_PCM( 6144000, pll4, 4, 1, 16, LOW),
- F_PCM( 8192000, pll4, 4, 1, 12, LOW),
- F_PCM(12288000, pll4, 4, 1, 8, LOW),
- F_PCM(24576000, pll4, 4, 1, 4, LOW),
+ F_PCM( 0, gnd, 1, 0, 0),
+ F_PCM( 512000, pll4, 4, 1, 192),
+ F_PCM( 768000, pll4, 4, 1, 128),
+ F_PCM( 1024000, pll4, 4, 1, 96),
+ F_PCM( 1536000, pll4, 4, 1, 64),
+ F_PCM( 2048000, pll4, 4, 1, 48),
+ F_PCM( 3072000, pll4, 4, 1, 32),
+ F_PCM( 4096000, pll4, 4, 1, 24),
+ F_PCM( 6144000, pll4, 4, 1, 16),
+ F_PCM( 8192000, pll4, 4, 1, 12),
+ F_PCM(12288000, pll4, 4, 1, 8),
+ F_PCM(24576000, pll4, 4, 1, 4),
F_END
};
@@ -1193,6 +1207,7 @@
.c = {
.dbg_name = "pcm_clk",
.ops = &clk_ops_rcg_9615,
+ VDD_DIG_FMAX_MAP1(LOW, 24576000),
CLK_INIT(pcm_clk.c),
},
};
@@ -1217,6 +1232,7 @@
.c = {
.dbg_name = "audio_slimbus_clk",
.ops = &clk_ops_rcg_9615,
+ VDD_DIG_FMAX_MAP1(LOW, 24576000),
CLK_INIT(audio_slimbus_clk.c),
},
};
@@ -1717,8 +1733,7 @@
BUG();
}
- soc_update_sys_vdd = msm9615_update_sys_vdd;
- local_vote_sys_vdd(HIGH);
+ vote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
clk_ops_pll.enable = sr_pll_clk_enable;
@@ -1744,7 +1759,7 @@
static int __init msm9615_clock_late_init(void)
{
- return local_unvote_sys_vdd(HIGH);
+ return unvote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
}
struct clock_init_data msm9615_clock_init_data __initdata = {
diff --git a/arch/arm/mach-msm/clock-debug.c b/arch/arm/mach-msm/clock-debug.c
index c0af9b5..ab4d8c1 100644
--- a/arch/arm/mach-msm/clock-debug.c
+++ b/arch/arm/mach-msm/clock-debug.c
@@ -170,10 +170,25 @@
static int list_rates_show(struct seq_file *m, void *unused)
{
struct clk *clock = m->private;
- int rate, i = 0;
+ int rate, level, fmax = 0, i = 0;
- while ((rate = clock->ops->list_rate(clock, i++)) >= 0)
- seq_printf(m, "%d\n", rate);
+ /* Find max frequency supported within voltage constraints. */
+ if (!clock->vdd_class) {
+ fmax = INT_MAX;
+ } else {
+ for (level = 0; level < ARRAY_SIZE(clock->fmax); level++)
+ if (clock->fmax[level])
+ fmax = clock->fmax[level];
+ }
+
+ /*
+ * List supported frequencies <= fmax. Higher frequencies may appear in
+ * the frequency table, but are not valid and should not be listed.
+ */
+ while ((rate = clock->ops->list_rate(clock, i++)) >= 0) {
+ if (rate <= fmax)
+ seq_printf(m, "%u\n", rate);
+ }
return 0;
}
@@ -198,7 +213,7 @@
if (!debugfs_base)
return -ENOMEM;
- strncpy(temp, clock->dbg_name, ARRAY_SIZE(temp)-1);
+ strlcpy(temp, clock->dbg_name, ARRAY_SIZE(temp));
for (ptr = temp; *ptr; ptr++)
*ptr = tolower(*ptr);
diff --git a/arch/arm/mach-msm/clock-local.c b/arch/arm/mach-msm/clock-local.c
index ea76512..ca25802 100644
--- a/arch/arm/mach-msm/clock-local.c
+++ b/arch/arm/mach-msm/clock-local.c
@@ -48,9 +48,6 @@
DEFINE_SPINLOCK(local_clock_reg_lock);
struct clk_freq_tbl rcg_dummy_freq = F_END;
-unsigned local_sys_vdd_votes[NUM_SYS_VDD_LEVELS];
-static DEFINE_SPINLOCK(sys_vdd_vote_lock);
-
/*
* Common Set-Rate Functions
*/
@@ -264,81 +261,6 @@
clk->ns_mask = new_bank_masks->ns_mask;
}
-int (*soc_update_sys_vdd)(enum sys_vdd_level level);
-
-/*
- * SYS_VDD voting functions
- */
-
-/* Update system voltage level given the current votes. */
-static int local_update_sys_vdd(void)
-{
- static int cur_level = NUM_SYS_VDD_LEVELS;
- int level, rc = 0;
-
- if (local_sys_vdd_votes[HIGH])
- level = HIGH;
- else if (local_sys_vdd_votes[NOMINAL])
- level = NOMINAL;
- else if (local_sys_vdd_votes[LOW])
- level = LOW;
- else
- level = NONE;
-
- if (level == cur_level)
- return rc;
-
- rc = soc_update_sys_vdd(level);
- if (!rc)
- cur_level = level;
-
- return rc;
-}
-
-/* Vote for a system voltage level. */
-int local_vote_sys_vdd(unsigned level)
-{
- int rc = 0;
- unsigned long flags;
-
- /* Bounds checking. */
- if (level >= ARRAY_SIZE(local_sys_vdd_votes))
- return -EINVAL;
-
- spin_lock_irqsave(&sys_vdd_vote_lock, flags);
- local_sys_vdd_votes[level]++;
- rc = local_update_sys_vdd();
- if (rc)
- local_sys_vdd_votes[level]--;
- spin_unlock_irqrestore(&sys_vdd_vote_lock, flags);
-
- return rc;
-}
-
-/* Remove vote for a system voltage level. */
-int local_unvote_sys_vdd(unsigned level)
-{
- int rc = 0;
- unsigned long flags;
-
- /* Bounds checking. */
- if (level >= ARRAY_SIZE(local_sys_vdd_votes))
- return -EINVAL;
-
- spin_lock_irqsave(&sys_vdd_vote_lock, flags);
-
- if (WARN(!local_sys_vdd_votes[level],
- "Reference counts are incorrect for level %d!\n", level))
- goto out;
-
- local_sys_vdd_votes[level]--;
- rc = local_update_sys_vdd();
- if (rc)
- local_sys_vdd_votes[level]++;
-out:
- spin_unlock_irqrestore(&sys_vdd_vote_lock, flags);
- return rc;
-}
/*
* Clock enable/disable functions
*/
@@ -351,7 +273,7 @@
return invert ? !status_bit : status_bit;
}
-static void __branch_clk_enable_reg(const struct branch *clk, const char *name)
+void __branch_clk_enable_reg(const struct branch *clk, const char *name)
{
u32 reg_val;
@@ -422,7 +344,7 @@
}
/* Perform any register operations required to disable the branch. */
-static u32 __branch_clk_disable_reg(const struct branch *clk, const char *name)
+u32 __branch_clk_disable_reg(const struct branch *clk, const char *name)
{
u32 reg_val;
@@ -486,19 +408,25 @@
}
}
-static void _rcg_clk_enable(struct rcg_clk *clk)
+/* Enable a rate-settable clock. */
+int rcg_clk_enable(struct clk *c)
{
unsigned long flags;
+ struct rcg_clk *clk = to_rcg_clk(c);
spin_lock_irqsave(&local_clock_reg_lock, flags);
__rcg_clk_enable_reg(clk);
clk->enabled = true;
spin_unlock_irqrestore(&local_clock_reg_lock, flags);
+
+ return 0;
}
-static void _rcg_clk_disable(struct rcg_clk *clk)
+/* Disable a rate-settable clock. */
+void rcg_clk_disable(struct clk *c)
{
unsigned long flags;
+ struct rcg_clk *clk = to_rcg_clk(c);
spin_lock_irqsave(&local_clock_reg_lock, flags);
__rcg_clk_disable_reg(clk);
@@ -506,34 +434,6 @@
spin_unlock_irqrestore(&local_clock_reg_lock, flags);
}
-/* Enable a clock and any related power rail. */
-int rcg_clk_enable(struct clk *c)
-{
- int rc;
- struct rcg_clk *clk = to_rcg_clk(c);
-
- rc = local_vote_sys_vdd(clk->current_freq->sys_vdd);
- if (rc)
- return rc;
- _rcg_clk_enable(clk);
- return rc;
-}
-
-/* Disable a clock and any related power rail. */
-void rcg_clk_disable(struct clk *c)
-{
- struct rcg_clk *clk = to_rcg_clk(c);
-
- _rcg_clk_disable(clk);
- local_unvote_sys_vdd(clk->current_freq->sys_vdd);
-}
-
-/* Turn off a clock at boot, without checking refcounts. */
-void rcg_clk_auto_off(struct clk *c)
-{
- _rcg_clk_disable(to_rcg_clk(c));
-}
-
/*
* Frequency-related functions
*/
@@ -544,25 +444,17 @@
struct clk_freq_tbl *cf;
int rc = 0;
struct clk *chld;
- unsigned long flags;
-
- spin_lock_irqsave(&clk->c.lock, flags);
/* Check if frequency is actually changed. */
cf = clk->current_freq;
if (nf == cf)
- goto unlock;
+ return 0;
if (clk->enabled) {
- /* Vote for voltage and source for new freq. */
- rc = local_vote_sys_vdd(nf->sys_vdd);
- if (rc)
- goto unlock;
+ /* Enable source clock dependency for the new freq. */
rc = clk_enable(nf->src_clk);
- if (rc) {
- local_unvote_sys_vdd(nf->sys_vdd);
- goto unlock;
- }
+ if (rc)
+ return rc;
}
spin_lock(&local_clock_reg_lock);
@@ -608,13 +500,9 @@
spin_unlock(&local_clock_reg_lock);
- /* Release requirements of the old freq. */
- if (clk->enabled) {
+ /* Release source requirements of the old freq. */
+ if (clk->enabled)
clk_disable(cf->src_clk);
- local_unvote_sys_vdd(cf->sys_vdd);
- }
-unlock:
- spin_unlock_irqrestore(&clk->c.lock, flags);
return rc;
}
@@ -985,16 +873,6 @@
return branch->enabled;
}
-void branch_clk_auto_off(struct clk *clk)
-{
- struct branch_clk *branch = to_branch_clk(clk);
- unsigned long flags;
-
- spin_lock_irqsave(&local_clock_reg_lock, flags);
- __branch_clk_disable_reg(&branch->b, branch->c.dbg_name);
- spin_unlock_irqrestore(&local_clock_reg_lock, flags);
-}
-
int branch_reset(struct branch *clk, enum clk_reset_action action)
{
int ret = 0;
diff --git a/arch/arm/mach-msm/clock-local.h b/arch/arm/mach-msm/clock-local.h
index f62e753..9887bb1 100644
--- a/arch/arm/mach-msm/clock-local.h
+++ b/arch/arm/mach-msm/clock-local.h
@@ -74,22 +74,17 @@
const struct bank_mask_info bank1_mask;
};
-#define F_RAW(f, sc, m_v, n_v, c_v, m_m, v, e) { \
+#define F_RAW(f, sc, m_v, n_v, c_v, m_m, e) { \
.freq_hz = f, \
.src_clk = sc, \
.md_val = m_v, \
.ns_val = n_v, \
.ctl_val = c_v, \
.mnd_en_mask = m_m, \
- .sys_vdd = v, \
.extra_freq_data = e, \
}
#define FREQ_END (UINT_MAX-1)
-#define F_END \
- { \
- .freq_hz = FREQ_END, \
- .sys_vdd = LOW, \
- }
+#define F_END { .freq_hz = FREQ_END }
/**
* struct branch - branch on/off
@@ -114,6 +109,8 @@
};
int branch_reset(struct branch *clk, enum clk_reset_action action);
+void __branch_clk_enable_reg(const struct branch *clk, const char *name);
+u32 __branch_clk_disable_reg(const struct branch *clk, const char *name);
/*
* Generic clock-definition struct and macros
@@ -146,7 +143,6 @@
int rcg_clk_enable(struct clk *clk);
void rcg_clk_disable(struct clk *clk);
-void rcg_clk_auto_off(struct clk *clk);
int rcg_clk_set_rate(struct clk *clk, unsigned rate);
int rcg_clk_set_min_rate(struct clk *clk, unsigned rate);
unsigned rcg_clk_get_rate(struct clk *clk);
@@ -156,17 +152,6 @@
struct clk *rcg_clk_get_parent(struct clk *c);
int rcg_clk_handoff(struct clk *c);
-/*
- * SYS_VDD voltage levels
- */
-enum sys_vdd_level {
- NONE,
- LOW,
- NOMINAL,
- HIGH,
- NUM_SYS_VDD_LEVELS
-};
-
/**
* struct fixed_clk - fixed rate clock (used for crystal oscillators)
* @rate: output rate
@@ -268,7 +253,6 @@
struct clk *branch_clk_get_parent(struct clk *clk);
int branch_clk_set_parent(struct clk *clk, struct clk *parent);
int branch_clk_is_enabled(struct clk *clk);
-void branch_clk_auto_off(struct clk *clk);
int branch_clk_reset(struct clk *c, enum clk_reset_action action);
/**
@@ -301,16 +285,9 @@
/*
* Local-clock APIs
*/
-int local_vote_sys_vdd(enum sys_vdd_level level);
-int local_unvote_sys_vdd(enum sys_vdd_level level);
bool local_clk_is_local(struct clk *clk);
/*
- * Required SoC-specific functions, implemented for every supported SoC
- */
-extern int (*soc_update_sys_vdd)(enum sys_vdd_level level);
-
-/*
* Generic set-rate implementations
*/
void set_rate_mnd(struct rcg_clk *clk, struct clk_freq_tbl *nf);
diff --git a/arch/arm/mach-msm/clock-pcom-lookup.c b/arch/arm/mach-msm/clock-pcom-lookup.c
index b176301..d1a257d 100644
--- a/arch/arm/mach-msm/clock-pcom-lookup.c
+++ b/arch/arm/mach-msm/clock-pcom-lookup.c
@@ -263,6 +263,9 @@
CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_camera_ov9726.0"),
CLK_LOOKUP("csi_pclk", csi0_p_clk.c, "msm_camera_ov9726.0"),
CLK_LOOKUP("csi_vfe_clk", csi0_vfe_clk.c, "msm_camera_ov9726.0"),
+ CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_camera_ov7692.0"),
+ CLK_LOOKUP("csi_pclk", csi0_p_clk.c, "msm_camera_ov7692.0"),
+ CLK_LOOKUP("csi_vfe_clk", csi0_vfe_clk.c, "msm_camera_ov7692.0"),
CLK_LOOKUP("csi_clk", csi1_clk.c, NULL),
CLK_LOOKUP("csi_pclk", csi1_p_clk.c, NULL),
CLK_LOOKUP("csi_vfe_clk", csi1_vfe_clk.c, NULL),
diff --git a/arch/arm/mach-msm/clock-rpm.c b/arch/arm/mach-msm/clock-rpm.c
index 286b3d0..2ccebb4 100644
--- a/arch/arm/mach-msm/clock-rpm.c
+++ b/arch/arm/mach-msm/clock-rpm.c
@@ -104,11 +104,6 @@
return;
}
-static void rpm_clk_auto_off(struct clk *clk)
-{
- /* Not supported */
-}
-
static int rpm_clk_set_min_rate(struct clk *clk, unsigned rate)
{
unsigned long flags;
@@ -194,7 +189,6 @@
struct clk_ops clk_ops_rpm = {
.enable = rpm_clk_enable,
.disable = rpm_clk_disable,
- .auto_off = rpm_clk_auto_off,
.set_min_rate = rpm_clk_set_min_rate,
.get_rate = rpm_clk_get_rate,
.is_enabled = rpm_clk_is_enabled,
diff --git a/arch/arm/mach-msm/clock-voter.c b/arch/arm/mach-msm/clock-voter.c
index 1c742b1..e754752 100644
--- a/arch/arm/mach-msm/clock-voter.c
+++ b/arch/arm/mach-msm/clock-voter.c
@@ -75,7 +75,7 @@
static int voter_clk_enable(struct clk *clk)
{
- int ret;
+ int ret = 0;
unsigned long flags;
unsigned cur_rate;
struct clk *parent;
diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c
index 58a64a3..de89382 100644
--- a/arch/arm/mach-msm/clock.c
+++ b/arch/arm/mach-msm/clock.c
@@ -24,13 +24,116 @@
#include "clock.h"
+/* Find the voltage level required for a given rate. */
+static int find_vdd_level(struct clk *clk, unsigned long rate)
+{
+ int level;
+
+ for (level = 0; level < ARRAY_SIZE(clk->fmax); level++)
+ if (rate <= clk->fmax[level])
+ break;
+
+ if (level == ARRAY_SIZE(clk->fmax)) {
+ pr_err("Rate %lu for %s is greater than highest Fmax\n", rate,
+ clk->dbg_name);
+ return -EINVAL;
+ }
+
+ return level;
+}
+
+/* Update voltage level given the current votes. */
+static int update_vdd(struct clk_vdd_class *vdd_class)
+{
+ int level, rc;
+
+ for (level = ARRAY_SIZE(vdd_class->level_votes)-1; level > 0; level--)
+ if (vdd_class->level_votes[level])
+ break;
+
+ if (level == vdd_class->cur_level)
+ return 0;
+
+ rc = vdd_class->set_vdd(vdd_class, level);
+ if (!rc)
+ vdd_class->cur_level = level;
+
+ return rc;
+}
+
+/* Vote for a voltage level. */
+int vote_vdd_level(struct clk_vdd_class *vdd_class, int level)
+{
+ unsigned long flags;
+ int rc;
+
+ spin_lock_irqsave(&vdd_class->lock, flags);
+ vdd_class->level_votes[level]++;
+ rc = update_vdd(vdd_class);
+ if (rc)
+ vdd_class->level_votes[level]--;
+ spin_unlock_irqrestore(&vdd_class->lock, flags);
+
+ return rc;
+}
+
+/* Remove vote for a voltage level. */
+int unvote_vdd_level(struct clk_vdd_class *vdd_class, int level)
+{
+ unsigned long flags;
+ int rc = 0;
+
+ spin_lock_irqsave(&vdd_class->lock, flags);
+ if (WARN(!vdd_class->level_votes[level],
+ "Reference counts are incorrect for %s level %d\n",
+ vdd_class->class_name, level))
+ goto out;
+ vdd_class->level_votes[level]--;
+ rc = update_vdd(vdd_class);
+ if (rc)
+ vdd_class->level_votes[level]++;
+out:
+ spin_unlock_irqrestore(&vdd_class->lock, flags);
+ return rc;
+}
+
+/* Vote for a voltage level corresponding to a clock's rate. */
+static int vote_rate_vdd(struct clk *clk, unsigned long rate)
+{
+ int level;
+
+ if (!clk->vdd_class)
+ return 0;
+
+ level = find_vdd_level(clk, rate);
+ if (level < 0)
+ return level;
+
+ return vote_vdd_level(clk->vdd_class, level);
+}
+
+/* Remove vote for a voltage level corresponding to a clock's rate. */
+static void unvote_rate_vdd(struct clk *clk, unsigned long rate)
+{
+ int level;
+
+ if (!clk->vdd_class)
+ return;
+
+ level = find_vdd_level(clk, rate);
+ if (level < 0)
+ return;
+
+ unvote_vdd_level(clk->vdd_class, level);
+}
+
/*
* Standard clock functions defined in include/linux/clk.h
*/
int clk_enable(struct clk *clk)
{
int ret = 0;
- unsigned long flags;
+ unsigned long flags, rate;
struct clk *parent;
if (!clk)
@@ -39,22 +142,22 @@
spin_lock_irqsave(&clk->lock, flags);
if (clk->count == 0) {
parent = clk_get_parent(clk);
+ rate = clk_get_rate(clk);
+
ret = clk_enable(parent);
if (ret)
- goto out;
+ goto err_enable_parent;
ret = clk_enable(clk->depends);
- if (ret) {
- clk_disable(parent);
- goto out;
- }
+ if (ret)
+ goto err_enable_depends;
+ ret = vote_rate_vdd(clk, rate);
+ if (ret)
+ goto err_vote_vdd;
if (clk->ops->enable)
ret = clk->ops->enable(clk);
- if (ret) {
- clk_disable(clk->depends);
- clk_disable(parent);
- goto out;
- }
+ if (ret)
+ goto err_enable_clock;
} else if (clk->flags & CLKFLAG_HANDOFF_RATE) {
/*
* The clock was already enabled by handoff code so there is no
@@ -69,6 +172,16 @@
out:
spin_unlock_irqrestore(&clk->lock, flags);
+ return 0;
+
+err_enable_clock:
+ unvote_rate_vdd(clk, rate);
+err_vote_vdd:
+ clk_disable(clk->depends);
+err_enable_depends:
+ clk_disable(parent);
+err_enable_parent:
+ spin_unlock_irqrestore(&clk->lock, flags);
return ret;
}
EXPORT_SYMBOL(clk_enable);
@@ -76,7 +189,6 @@
void clk_disable(struct clk *clk)
{
unsigned long flags;
- struct clk *parent;
if (!clk)
return;
@@ -85,10 +197,13 @@
if (WARN(clk->count == 0, "%s is unbalanced", clk->dbg_name))
goto out;
if (clk->count == 1) {
+ struct clk *parent = clk_get_parent(clk);
+ unsigned long rate = clk_get_rate(clk);
+
if (clk->ops->disable)
clk->ops->disable(clk);
+ unvote_rate_vdd(clk, rate);
clk_disable(clk->depends);
- parent = clk_get_parent(clk);
clk_disable(parent);
}
clk->count--;
@@ -117,10 +232,35 @@
int clk_set_rate(struct clk *clk, unsigned long rate)
{
+ unsigned long start_rate, flags;
+ int rc;
+
if (!clk->ops->set_rate)
return -ENOSYS;
- return clk->ops->set_rate(clk, rate);
+ spin_lock_irqsave(&clk->lock, flags);
+ if (clk->count) {
+ start_rate = clk_get_rate(clk);
+ /* Enforce vdd requirements for target frequency. */
+ rc = vote_rate_vdd(clk, rate);
+ if (rc)
+ goto err_vote_vdd;
+ rc = clk->ops->set_rate(clk, rate);
+ if (rc)
+ goto err_set_rate;
+ /* Release vdd requirements for starting frequency. */
+ unvote_rate_vdd(clk, start_rate);
+ } else {
+ rc = clk->ops->set_rate(clk, rate);
+ }
+ spin_unlock_irqrestore(&clk->lock, flags);
+ return rc;
+
+err_set_rate:
+ unvote_rate_vdd(clk, rate);
+err_vote_vdd:
+ spin_unlock_irqrestore(&clk->lock, flags);
+ return rc;
}
EXPORT_SYMBOL(clk_set_rate);
diff --git a/arch/arm/mach-msm/clock.h b/arch/arm/mach-msm/clock.h
index f4a7363..ed5c9c6 100644
--- a/arch/arm/mach-msm/clock.h
+++ b/arch/arm/mach-msm/clock.h
@@ -33,6 +33,32 @@
#define CLKFLAG_MIN 0x00000400
#define CLKFLAG_MAX 0x00000800
+#define MAX_VDD_LEVELS 4
+
+/**
+ * struct clk_vdd_class - Voltage scaling class
+ * @class_name: name of the class
+ * @set_vdd: function to call when applying a new voltage setting
+ * @level_votes: array of votes for each level
+ * @cur_level: the currently set voltage level
+ * @lock: lock to protect this struct
+ */
+struct clk_vdd_class {
+ const char *class_name;
+ int (*set_vdd)(struct clk_vdd_class *v_class, int level);
+ int level_votes[MAX_VDD_LEVELS];
+ unsigned cur_level;
+ spinlock_t lock;
+};
+
+#define DEFINE_VDD_CLASS(_name, _set_vdd) \
+ struct clk_vdd_class _name = { \
+ .class_name = #_name, \
+ .set_vdd = _set_vdd, \
+ .cur_level = ARRAY_SIZE(_name.level_votes), \
+ .lock = __SPIN_LOCK_UNLOCKED(lock) \
+ }
+
struct clk_ops {
int (*enable)(struct clk *clk);
void (*disable)(struct clk *clk);
@@ -57,12 +83,16 @@
* @count: enable refcount
* @lock: protects clk_enable()/clk_disable() path and @count
* @depends: non-direct parent of clock to enable when this clock is enabled
+ * @vdd_class: voltage scaling requirement class
+ * @fmax: maximum frequency in Hz supported at each voltage level
*/
struct clk {
uint32_t flags;
struct clk_ops *ops;
const char *dbg_name;
struct clk *depends;
+ struct clk_vdd_class *vdd_class;
+ unsigned long fmax[MAX_VDD_LEVELS];
struct list_head children;
struct list_head siblings;
@@ -104,6 +134,8 @@
extern struct clock_init_data qds8x50_clock_init_data;
void msm_clock_init(struct clock_init_data *data);
+int vote_vdd_level(struct clk_vdd_class *vdd_class, int level);
+int unvote_vdd_level(struct clk_vdd_class *vdd_class, int level);
#ifdef CONFIG_DEBUG_FS
int clock_debug_init(struct clock_init_data *data);
diff --git a/arch/arm/mach-msm/dal.c b/arch/arm/mach-msm/dal.c
index 218bd0f..94c02f0 100644
--- a/arch/arm/mach-msm/dal.c
+++ b/arch/arm/mach-msm/dal.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -407,7 +407,7 @@
if (!p)
return NULL;
- strncpy(p->port, port, sizeof(p->port) - 1);
+ strlcpy(p->port, port, sizeof(p->port));
p->refcount = 1;
snprintf(wq_name, sizeof(wq_name), "dalrpc_rcv_%s", port);
@@ -537,8 +537,8 @@
} else if (strnlen((char *)&h->msg.param[1],
DALRPC_MAX_PORTNAME_LEN)) {
/* another port was recommended in the response. */
- strncpy(dyn_port, (char *)&h->msg.param[1],
- DALRPC_MAX_PORTNAME_LEN);
+ strlcpy(dyn_port, (char *)&h->msg.param[1],
+ sizeof(dyn_port));
dyn_port[DALRPC_MAX_PORTNAME_LEN] = 0;
port = dyn_port;
} else if (port == dyn_port) {
diff --git a/arch/arm/mach-msm/devices-8064.c b/arch/arm/mach-msm/devices-8064.c
index 694a70d..fd2be92 100644
--- a/arch/arm/mach-msm/devices-8064.c
+++ b/arch/arm/mach-msm/devices-8064.c
@@ -680,7 +680,7 @@
CLK_DUMMY("mdp_clk", MDP_CLK, NULL, OFF),
CLK_DUMMY("mdp_vsync_clk", MDP_VSYNC_CLK, NULL, OFF),
CLK_DUMMY("lut_mdp", LUT_MDP_CLK, NULL, OFF),
- CLK_DUMMY("rot_clk", ROT_CLK, NULL, OFF),
+ CLK_DUMMY("core_clk", ROT_CLK, NULL, OFF),
CLK_DUMMY("tv_src_clk", TV_SRC_CLK, NULL, OFF),
CLK_DUMMY("core_clk", VCODEC_CLK, NULL, OFF),
CLK_DUMMY("mdp_tv_clk", MDP_TV_CLK, NULL, OFF),
@@ -694,7 +694,7 @@
CLK_DUMMY("vfe_axi_clk", VFE_AXI_CLK, NULL, OFF),
CLK_DUMMY("ijpeg_axi_clk", IJPEG_AXI_CLK, NULL, OFF),
CLK_DUMMY("mdp_axi_clk", MDP_AXI_CLK, NULL, OFF),
- CLK_DUMMY("rot_axi_clk", ROT_AXI_CLK, NULL, OFF),
+ CLK_DUMMY("bus_clk", ROT_AXI_CLK, NULL, OFF),
CLK_DUMMY("vcodec_axi_clk", VCODEC_AXI_CLK, NULL, OFF),
CLK_DUMMY("vcodec_axi_a_clk", VCODEC_AXI_A_CLK, NULL, OFF),
CLK_DUMMY("vcodec_axi_b_clk", VCODEC_AXI_B_CLK, NULL, OFF),
@@ -720,7 +720,7 @@
CLK_DUMMY("mem_iface_clk", IMEM_P_CLK, NULL, OFF),
CLK_DUMMY("mdp_pclk", MDP_P_CLK, NULL, OFF),
CLK_DUMMY("iface_clk", SMMU_P_CLK, "msm_smmu", OFF),
- CLK_DUMMY("rotator_pclk", ROT_P_CLK, NULL, OFF),
+ CLK_DUMMY("iface_clk", ROT_P_CLK, NULL, OFF),
CLK_DUMMY("vcodec_pclk", VCODEC_P_CLK, NULL, OFF),
CLK_DUMMY("vfe_pclk", VFE_P_CLK, NULL, OFF),
CLK_DUMMY("vpe_pclk", VPE_P_CLK, NULL, OFF),
diff --git a/arch/arm/mach-msm/devices-8960.c b/arch/arm/mach-msm/devices-8960.c
index 7512414..899f2e1 100644
--- a/arch/arm/mach-msm/devices-8960.c
+++ b/arch/arm/mach-msm/devices-8960.c
@@ -1297,12 +1297,12 @@
static struct msm_rot_clocks rotator_clocks[] = {
{
- .clk_name = "rot_clk",
+ .clk_name = "core_clk",
.clk_type = ROTATOR_CORE_CLK,
.clk_rate = 200 * 1000 * 1000,
},
{
- .clk_name = "rotator_pclk",
+ .clk_name = "iface_clk",
.clk_type = ROTATOR_PCLK,
.clk_rate = 0,
},
@@ -1659,7 +1659,7 @@
CLK_DUMMY("mdp_clk", MDP_CLK, NULL, OFF),
CLK_DUMMY("mdp_vsync_clk", MDP_VSYNC_CLK, NULL, OFF),
CLK_DUMMY("lut_mdp", LUT_MDP_CLK, NULL, OFF),
- CLK_DUMMY("rot_clk", ROT_CLK, NULL, OFF),
+ CLK_DUMMY("core_clk", ROT_CLK, NULL, OFF),
CLK_DUMMY("tv_src_clk", TV_SRC_CLK, NULL, OFF),
CLK_DUMMY("tv_enc_clk", TV_ENC_CLK, NULL, OFF),
CLK_DUMMY("tv_dac_clk", TV_DAC_CLK, NULL, OFF),
@@ -1673,7 +1673,7 @@
CLK_DUMMY("vfe_axi_clk", VFE_AXI_CLK, NULL, OFF),
CLK_DUMMY("ijpeg_axi_clk", IJPEG_AXI_CLK, NULL, OFF),
CLK_DUMMY("mdp_axi_clk", MDP_AXI_CLK, NULL, OFF),
- CLK_DUMMY("rot_axi_clk", ROT_AXI_CLK, NULL, OFF),
+ CLK_DUMMY("bus_clk", ROT_AXI_CLK, NULL, OFF),
CLK_DUMMY("vcodec_axi_clk", VCODEC_AXI_CLK, NULL, OFF),
CLK_DUMMY("vcodec_axi_a_clk", VCODEC_AXI_A_CLK, NULL, OFF),
CLK_DUMMY("vcodec_axi_b_clk", VCODEC_AXI_B_CLK, NULL, OFF),
@@ -1694,7 +1694,7 @@
CLK_DUMMY("mem_iface_clk", IMEM_P_CLK, NULL, OFF),
CLK_DUMMY("mdp_pclk", MDP_P_CLK, NULL, OFF),
CLK_DUMMY("iface_clk", SMMU_P_CLK, NULL, OFF),
- CLK_DUMMY("rotator_pclk", ROT_P_CLK, NULL, OFF),
+ CLK_DUMMY("iface_clk", ROT_P_CLK, NULL, OFF),
CLK_DUMMY("tv_enc_pclk", TV_ENC_P_CLK, NULL, OFF),
CLK_DUMMY("vcodec_pclk", VCODEC_P_CLK, NULL, OFF),
CLK_DUMMY("vfe_pclk", VFE_P_CLK, NULL, OFF),
diff --git a/arch/arm/mach-msm/devices-9615.c b/arch/arm/mach-msm/devices-9615.c
index 74e7871..13772ce 100644
--- a/arch/arm/mach-msm/devices-9615.c
+++ b/arch/arm/mach-msm/devices-9615.c
@@ -721,20 +721,19 @@
};
static uint8_t spm_wfi_cmd_sequence[] __initdata = {
- 0x00, 0x03, 0x0B, 0x00,
- 0x0f,
+ 0x00, 0x03, 0x00, 0x0f,
};
static uint8_t spm_power_collapse_without_rpm[] __initdata = {
- 0x30, 0x20, 0x10, 0x00,
- 0x50, 0x03, 0x50, 0x00,
- 0x10, 0x20, 0x30, 0x0f,
+ 0x34, 0x24, 0x14, 0x04,
+ 0x54, 0x03, 0x54, 0x04,
+ 0x14, 0x24, 0x3e, 0x0f,
};
static uint8_t spm_power_collapse_with_rpm[] __initdata = {
- 0x30, 0x20, 0x10, 0x00,
- 0x50, 0x07, 0x50, 0x00,
- 0x10, 0x20, 0x30, 0x0f,
+ 0x34, 0x24, 0x14, 0x04,
+ 0x54, 0x07, 0x54, 0x04,
+ 0x14, 0x24, 0x3e, 0x0f,
};
static struct msm_spm_seq_entry msm_spm_seq_list[] __initdata = {
@@ -759,7 +758,7 @@
[0] = {
.reg_base_addr = MSM_SAW0_BASE,
.reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x01,
- .reg_init_values[MSM_SPM_REG_SAW2_CFG] = 0x1F,
+ .reg_init_values[MSM_SPM_REG_SAW2_CFG] = 0x1001,
.num_modes = ARRAY_SIZE(msm_spm_seq_list),
.modes = msm_spm_seq_list,
},
diff --git a/arch/arm/mach-msm/devices-iommu.c b/arch/arm/mach-msm/devices-iommu.c
index b04bc11..3d2d2e7 100644
--- a/arch/arm/mach-msm/devices-iommu.c
+++ b/arch/arm/mach-msm/devices-iommu.c
@@ -16,8 +16,6 @@
#include <mach/irqs.h>
#include <mach/iommu.h>
#include <mach/socinfo.h>
-#include <mach/irqs-8960.h>
-#include <mach/irqs-8064.h>
static struct resource msm_iommu_jpegd_resources[] = {
{
@@ -28,14 +26,14 @@
},
{
.name = "nonsecure_irq",
- .start = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ,
- .end = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ,
+ .start = 98,
+ .end = 98,
.flags = IORESOURCE_IRQ,
},
{
.name = "secure_irq",
- .start = SMMU_JPEGD_CB_SC_SECURE_IRQ,
- .end = SMMU_JPEGD_CB_SC_SECURE_IRQ,
+ .start = 97,
+ .end = 97,
.flags = IORESOURCE_IRQ,
},
};
@@ -49,14 +47,14 @@
},
{
.name = "nonsecure_irq",
- .start = SMMU_VPE_CB_SC_NON_SECURE_IRQ,
- .end = SMMU_VPE_CB_SC_NON_SECURE_IRQ,
+ .start = 84,
+ .end = 84,
.flags = IORESOURCE_IRQ,
},
{
.name = "secure_irq",
- .start = SMMU_VPE_CB_SC_SECURE_IRQ,
- .end = SMMU_VPE_CB_SC_SECURE_IRQ,
+ .start = 83,
+ .end = 83,
.flags = IORESOURCE_IRQ,
},
};
@@ -70,14 +68,14 @@
},
{
.name = "nonsecure_irq",
- .start = SMMU_MDP0_CB_SC_NON_SECURE_IRQ,
- .end = SMMU_MDP0_CB_SC_NON_SECURE_IRQ,
+ .start = 96,
+ .end = 96,
.flags = IORESOURCE_IRQ,
},
{
.name = "secure_irq",
- .start = SMMU_MDP0_CB_SC_SECURE_IRQ,
- .end = SMMU_MDP0_CB_SC_SECURE_IRQ,
+ .start = 95,
+ .end = 95,
.flags = IORESOURCE_IRQ,
},
};
@@ -91,14 +89,14 @@
},
{
.name = "nonsecure_irq",
- .start = SMMU_MDP1_CB_SC_NON_SECURE_IRQ,
- .end = SMMU_MDP1_CB_SC_NON_SECURE_IRQ,
+ .start = 94,
+ .end = 94,
.flags = IORESOURCE_IRQ,
},
{
.name = "secure_irq",
- .start = SMMU_MDP1_CB_SC_SECURE_IRQ,
- .end = SMMU_MDP1_CB_SC_SECURE_IRQ,
+ .start = 93,
+ .end = 93,
.flags = IORESOURCE_IRQ,
},
};
@@ -112,14 +110,14 @@
},
{
.name = "nonsecure_irq",
- .start = SMMU_ROT_CB_SC_NON_SECURE_IRQ,
- .end = SMMU_ROT_CB_SC_NON_SECURE_IRQ,
+ .start = 92,
+ .end = 92,
.flags = IORESOURCE_IRQ,
},
{
.name = "secure_irq",
- .start = SMMU_ROT_CB_SC_SECURE_IRQ,
- .end = SMMU_ROT_CB_SC_SECURE_IRQ,
+ .start = 91,
+ .end = 91,
.flags = IORESOURCE_IRQ,
},
};
@@ -133,14 +131,14 @@
},
{
.name = "nonsecure_irq",
- .start = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ,
- .end = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ,
+ .start = 100,
+ .end = 100,
.flags = IORESOURCE_IRQ,
},
{
.name = "secure_irq",
- .start = SMMU_IJPEG_CB_SC_SECURE_IRQ,
- .end = SMMU_IJPEG_CB_SC_SECURE_IRQ,
+ .start = 99,
+ .end = 99,
.flags = IORESOURCE_IRQ,
},
};
@@ -154,14 +152,14 @@
},
{
.name = "nonsecure_irq",
- .start = SMMU_VFE_CB_SC_NON_SECURE_IRQ,
- .end = SMMU_VFE_CB_SC_NON_SECURE_IRQ,
+ .start = 86,
+ .end = 86,
.flags = IORESOURCE_IRQ,
},
{
.name = "secure_irq",
- .start = SMMU_VFE_CB_SC_SECURE_IRQ,
- .end = SMMU_VFE_CB_SC_SECURE_IRQ,
+ .start = 85,
+ .end = 85,
.flags = IORESOURCE_IRQ,
},
};
@@ -175,14 +173,14 @@
},
{
.name = "nonsecure_irq",
- .start = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ,
- .end = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ,
+ .start = 90,
+ .end = 90,
.flags = IORESOURCE_IRQ,
},
{
.name = "secure_irq",
- .start = SMMU_VCODEC_A_CB_SC_SECURE_IRQ,
- .end = SMMU_VCODEC_A_CB_SC_SECURE_IRQ,
+ .start = 89,
+ .end = 89,
.flags = IORESOURCE_IRQ,
},
};
@@ -196,14 +194,14 @@
},
{
.name = "nonsecure_irq",
- .start = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ,
- .end = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ,
+ .start = 88,
+ .end = 88,
.flags = IORESOURCE_IRQ,
},
{
.name = "secure_irq",
- .start = SMMU_VCODEC_B_CB_SC_SECURE_IRQ,
- .end = SMMU_VCODEC_B_CB_SC_SECURE_IRQ,
+ .start = 87,
+ .end = 87,
.flags = IORESOURCE_IRQ,
},
};
@@ -217,14 +215,14 @@
},
{
.name = "nonsecure_irq",
- .start = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ,
- .end = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ,
+ .start = 102,
+ .end = 102,
.flags = IORESOURCE_IRQ,
},
{
.name = "secure_irq",
- .start = SMMU_GFX3D_CB_SC_SECURE_IRQ,
- .end = SMMU_GFX3D_CB_SC_SECURE_IRQ,
+ .start = 101,
+ .end = 101,
.flags = IORESOURCE_IRQ,
},
};
@@ -238,14 +236,14 @@
},
{
.name = "nonsecure_irq",
- .start = SMMU_GFX3D1_CB_SC_NON_SECURE_IRQ,
- .end = SMMU_GFX3D1_CB_SC_NON_SECURE_IRQ,
+ .start = 243,
+ .end = 243,
.flags = IORESOURCE_IRQ,
},
{
.name = "secure_irq",
- .start = SMMU_GFX3D1_CB_SC_SECURE_IRQ,
- .end = SMMU_GFX3D1_CB_SC_SECURE_IRQ,
+ .start = 242,
+ .end = 242,
.flags = IORESOURCE_IRQ,
},
};
@@ -259,14 +257,14 @@
},
{
.name = "nonsecure_irq",
- .start = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ,
- .end = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ,
+ .start = 104,
+ .end = 104,
.flags = IORESOURCE_IRQ,
},
{
.name = "secure_irq",
- .start = SMMU_GFX2D0_CB_SC_SECURE_IRQ,
- .end = SMMU_GFX2D0_CB_SC_SECURE_IRQ,
+ .start = 103,
+ .end = 103,
.flags = IORESOURCE_IRQ,
},
};
@@ -280,14 +278,14 @@
},
{
.name = "nonsecure_irq",
- .start = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ,
- .end = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ,
+ .start = 243,
+ .end = 243,
.flags = IORESOURCE_IRQ,
},
{
.name = "secure_irq",
- .start = SMMU_GFX2D1_CB_SC_SECURE_IRQ,
- .end = SMMU_GFX2D1_CB_SC_SECURE_IRQ,
+ .start = 242,
+ .end = 242,
.flags = IORESOURCE_IRQ,
},
};
@@ -301,14 +299,14 @@
},
{
.name = "nonsecure_irq",
- .start = SMMU_VCAP_CB_SC_NON_SECURE_IRQ,
- .end = SMMU_VCAP_CB_SC_NON_SECURE_IRQ,
+ .start = 269,
+ .end = 269,
.flags = IORESOURCE_IRQ,
},
{
.name = "secure_irq",
- .start = SMMU_VCAP_CB_SC_SECURE_IRQ,
- .end = SMMU_VCAP_CB_SC_SECURE_IRQ,
+ .start = 268,
+ .end = 268,
.flags = IORESOURCE_IRQ,
},
};
@@ -1059,9 +1057,7 @@
static int __init iommu_init(void)
{
int ret;
-
- if (cpu_is_msm8960() &&
- SOCINFO_VERSION_MAJOR(socinfo_get_version()) < 2) {
+ if (!msm_soc_version_supports_iommu()) {
pr_err("IOMMU is not supported on this SoC version.\n");
return -ENODEV;
}
diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c
index d7fc93e..b76a844 100644
--- a/arch/arm/mach-msm/devices-msm7x30.c
+++ b/arch/arm/mach-msm/devices-msm7x30.c
@@ -1000,17 +1000,17 @@
static struct msm_rot_clocks rotator_clocks[] = {
{
- .clk_name = "rotator_clk",
+ .clk_name = "core_clk",
.clk_type = ROTATOR_CORE_CLK,
.clk_rate = 0,
},
{
- .clk_name = "rotator_pclk",
+ .clk_name = "iface_clk",
.clk_type = ROTATOR_PCLK,
.clk_rate = 0,
},
{
- .clk_name = "rotator_imem_clk",
+ .clk_name = "mem_clk",
.clk_type = ROTATOR_IMEM_CLK,
.clk_rate = 0,
},
diff --git a/arch/arm/mach-msm/devices-msm8x60.c b/arch/arm/mach-msm/devices-msm8x60.c
index 9f3e03d..49f3d3b 100644
--- a/arch/arm/mach-msm/devices-msm8x60.c
+++ b/arch/arm/mach-msm/devices-msm8x60.c
@@ -1424,12 +1424,12 @@
static struct msm_rot_clocks rotator_clocks[] = {
{
- .clk_name = "rot_clk",
+ .clk_name = "core_clk",
.clk_type = ROTATOR_CORE_CLK,
.clk_rate = 160 * 1000 * 1000,
},
{
- .clk_name = "rotator_pclk",
+ .clk_name = "iface_clk",
.clk_type = ROTATOR_PCLK,
.clk_rate = 0,
},
diff --git a/arch/arm/mach-msm/idle.h b/arch/arm/mach-msm/idle.h
index 740ef91..138db45 100644
--- a/arch/arm/mach-msm/idle.h
+++ b/arch/arm/mach-msm/idle.h
@@ -17,6 +17,7 @@
int msm_arch_idle(void);
int msm_pm_collapse(void);
void msm_pm_collapse_exit(void);
+void msm_warmboot_entry(void);
#ifdef CONFIG_CPU_V7
void msm_pm_boot_entry(void);
diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h
index 5a30df5..e7f156e 100644
--- a/arch/arm/mach-msm/include/mach/board.h
+++ b/arch/arm/mach-msm/include/mach/board.h
@@ -23,6 +23,7 @@
#include <linux/usb.h>
#include <linux/leds-pmic8058.h>
#include <linux/clkdev.h>
+#include <linux/of_platform.h>
#include <linux/msm_ssbi.h>
#include <mach/msm_bus.h>
@@ -92,7 +93,7 @@
#define MSM_CAMERA_FLASH_SRC_PWM (0x00000001<<1)
#define MSM_CAMERA_FLASH_SRC_CURRENT_DRIVER (0x00000001<<2)
#define MSM_CAMERA_FLASH_SRC_EXT (0x00000001<<3)
-
+#define MSM_CAMERA_FLASH_SRC_LED (0x00000001<<3)
struct msm_camera_sensor_flash_pmic {
uint8_t num_of_src;
@@ -124,6 +125,11 @@
struct msm_cam_expander_info *expander_info;
};
+struct msm_camera_sensor_flash_led {
+ const char *led_name;
+ const int led_name_len;
+};
+
struct msm_camera_sensor_flash_src {
int flash_sr_type;
@@ -134,6 +140,7 @@
current_driver_src;
struct msm_camera_sensor_flash_external
ext_driver_src;
+ struct msm_camera_sensor_flash_led led_src;
} _fsrc;
};
@@ -410,7 +417,11 @@
#endif
/* common init routines for use by arch/arm/mach-msm/board-*.c */
+#ifdef CONFIG_OF_DEVICE
+void msm_copper_init(struct of_dev_auxdata **);
+#endif
void msm_add_devices(void);
+void msm_copper_add_devices(void);
void msm_map_common_io(void);
void msm_map_qsd8x50_io(void);
void msm_map_msm8x60_io(void);
@@ -419,7 +430,9 @@
void msm_map_apq8064_io(void);
void msm_map_msm7x30_io(void);
void msm_map_fsm9xxx_io(void);
+void msm_map_copper_io(void);
void msm_init_irq(void);
+void msm_copper_init_irq(void);
void vic_handle_irq(struct pt_regs *regs);
struct mmc_platform_data;
diff --git a/arch/arm/mach-msm/include/mach/cpu.h b/arch/arm/mach-msm/include/mach/cpu.h
deleted file mode 100644
index 0308b7b..0000000
--- a/arch/arm/mach-msm/include/mach/cpu.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __ARCH_ARM_MACH_MSM_CPU_H__
-#define __ARCH_ARM_MACH_MSM_CPU_H__
-
-/* TODO: For now, only one CPU can be compiled at a time. */
-
-#define cpu_is_msm7x01() 0
-#define cpu_is_msm7x30() 0
-#define cpu_is_qsd8x50() 0
-#define cpu_is_msm8x60() 0
-#define cpu_is_msm8960() 0
-
-#ifdef CONFIG_ARCH_MSM7X00A
-# undef cpu_is_msm7x01
-# define cpu_is_msm7x01() 1
-#endif
-
-#ifdef CONFIG_ARCH_MSM7X30
-# undef cpu_is_msm7x30
-# define cpu_is_msm7x30() 1
-#endif
-
-#ifdef CONFIG_ARCH_QSD8X50
-# undef cpu_is_qsd8x50
-# define cpu_is_qsd8x50() 1
-#endif
-
-#ifdef CONFIG_ARCH_MSM8X60
-# undef cpu_is_msm8x60
-# define cpu_is_msm8x60() 1
-#endif
-
-#ifdef CONFIG_ARCH_MSM8960
-# undef cpu_is_msm8960
-# define cpu_is_msm8960() 1
-#endif
-
-#endif
diff --git a/arch/arm/mach-msm/include/mach/iommu.h b/arch/arm/mach-msm/include/mach/iommu.h
index 5542ff4..9405459 100644
--- a/arch/arm/mach-msm/include/mach/iommu.h
+++ b/arch/arm/mach-msm/include/mach/iommu.h
@@ -15,6 +15,7 @@
#include <linux/interrupt.h>
#include <linux/clk.h>
+#include <mach/socinfo.h>
/* Sharability attributes of MSM IOMMU mappings */
#define MSM_IOMMU_ATTR_NON_SH 0x0
@@ -121,3 +122,17 @@
#endif
#endif
+
+static inline int msm_soc_version_supports_iommu(void)
+{
+ if (cpu_is_msm8960() &&
+ SOCINFO_VERSION_MAJOR(socinfo_get_version()) < 2)
+ return 0;
+
+ if (cpu_is_msm8x60() &&
+ (SOCINFO_VERSION_MAJOR(socinfo_get_version()) != 2 ||
+ SOCINFO_VERSION_MINOR(socinfo_get_version()) < 1)) {
+ return 0;
+ }
+ return 1;
+}
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7xxx.h b/arch/arm/mach-msm/include/mach/msm_iomap-7xxx.h
index da0c54c..d7dc4f4 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7xxx.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7xxx.h
@@ -47,6 +47,10 @@
#define MSM_TMR_BASE MSM_CSR_BASE
#define MSM_TMR_SIZE SZ_4K
+#define MSM_TMR0_BASE MSM_TMR_BASE
+
+#define MSM_QGIC_DIST_BASE MSM_VIC_BASE
+
#define MSM_GPIO1_BASE IOMEM(0xFA003000)
#define MSM_GPIO1_PHYS 0xA9200000
#define MSM_GPIO1_SIZE SZ_4K
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-copper.h b/arch/arm/mach-msm/include/mach/msm_iomap-copper.h
index d613671..3999982 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-copper.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-copper.h
@@ -32,4 +32,10 @@
#define COPPER_TLMM_PHYS 0xFC4A0000
#define COPPER_TLMM_SIZE SZ_16K
+#define COPPER_TMR_PHYS 0xF900A000
+#define COPPER_TMR_SIZE SZ_4K
+
+#define COPPER_TMR0_PHYS 0xF908A000
+#define COPPER_TMR0_SIZE SZ_4K
+
#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_smd.h b/arch/arm/mach-msm/include/mach/msm_smd.h
index 320f08f..af47425 100644
--- a/arch/arm/mach-msm/include/mach/msm_smd.h
+++ b/arch/arm/mach-msm/include/mach/msm_smd.h
@@ -22,16 +22,38 @@
#define SMD_MAX_CH_NAME_LEN 20 /* includes null char at end */
-/* warning: notify() may be called before open returns */
-int smd_open(const char *name, smd_channel_t **ch, void *priv,
- void (*notify)(void *priv, unsigned event));
-
#define SMD_EVENT_DATA 1
#define SMD_EVENT_OPEN 2
#define SMD_EVENT_CLOSE 3
#define SMD_EVENT_STATUS 4
#define SMD_EVENT_REOPEN_READY 5
+enum {
+ SMD_APPS_MODEM = 0,
+ SMD_APPS_QDSP,
+ SMD_MODEM_QDSP,
+ SMD_APPS_DSPS,
+ SMD_MODEM_DSPS,
+ SMD_QDSP_DSPS,
+ SMD_APPS_WCNSS,
+ SMD_MODEM_WCNSS,
+ SMD_QDSP_WCNSS,
+ SMD_DSPS_WCNSS,
+ SMD_APPS_Q6FW,
+ SMD_MODEM_Q6FW,
+ SMD_QDSP_Q6FW,
+ SMD_DSPS_Q6FW,
+ SMD_WCNSS_Q6FW,
+ SMD_NUM_TYPE,
+ SMD_LOOPBACK_TYPE = 100,
+
+};
+
+#ifdef CONFIG_MSM_SMD
+/* warning: notify() may be called before open returns */
+int smd_open(const char *name, smd_channel_t **ch, void *priv,
+ void (*notify)(void *priv, unsigned event));
+
int smd_close(smd_channel_t *ch);
/* passing a null pointer for data reads and discards */
@@ -77,28 +99,6 @@
int smd_tiocmset(smd_channel_t *ch, unsigned int set, unsigned int clear);
int
smd_tiocmset_from_cb(smd_channel_t *ch, unsigned int set, unsigned int clear);
-
-enum {
- SMD_APPS_MODEM = 0,
- SMD_APPS_QDSP,
- SMD_MODEM_QDSP,
- SMD_APPS_DSPS,
- SMD_MODEM_DSPS,
- SMD_QDSP_DSPS,
- SMD_APPS_WCNSS,
- SMD_MODEM_WCNSS,
- SMD_QDSP_WCNSS,
- SMD_DSPS_WCNSS,
- SMD_APPS_Q6FW,
- SMD_MODEM_Q6FW,
- SMD_QDSP_Q6FW,
- SMD_DSPS_Q6FW,
- SMD_WCNSS_Q6FW,
- SMD_NUM_TYPE,
- SMD_LOOPBACK_TYPE = 100,
-
-};
-
int smd_named_open_on_edge(const char *name, uint32_t edge, smd_channel_t **_ch,
void *priv, void (*notify)(void *, unsigned));
@@ -162,4 +162,107 @@
*/
int smd_write_end(smd_channel_t *ch);
+#else
+
+static inline int smd_open(const char *name, smd_channel_t **ch, void *priv,
+ void (*notify)(void *priv, unsigned event))
+{
+ return -ENODEV;
+}
+
+static inline int smd_close(smd_channel_t *ch)
+{
+ return -ENODEV;
+}
+
+static inline int smd_read(smd_channel_t *ch, void *data, int len)
+{
+ return -ENODEV;
+}
+
+static inline int smd_read_from_cb(smd_channel_t *ch, void *data, int len)
+{
+ return -ENODEV;
+}
+
+static inline int smd_read_user_buffer(smd_channel_t *ch, void *data, int len)
+{
+ return -ENODEV;
+}
+
+static inline int smd_write(smd_channel_t *ch, const void *data, int len)
+{
+ return -ENODEV;
+}
+
+static inline int
+smd_write_user_buffer(smd_channel_t *ch, const void *data, int len)
+{
+ return -ENODEV;
+}
+
+static inline int smd_write_avail(smd_channel_t *ch)
+{
+ return -ENODEV;
+}
+
+static inline int smd_read_avail(smd_channel_t *ch)
+{
+ return -ENODEV;
+}
+
+static inline int smd_cur_packet_size(smd_channel_t *ch)
+{
+ return -ENODEV;
+}
+
+static inline int smd_tiocmget(smd_channel_t *ch)
+{
+ return -ENODEV;
+}
+
+static inline int
+smd_tiocmset(smd_channel_t *ch, unsigned int set, unsigned int clear)
+{
+ return -ENODEV;
+}
+
+static inline int
+smd_tiocmset_from_cb(smd_channel_t *ch, unsigned int set, unsigned int clear)
+{
+ return -ENODEV;
+}
+
+static inline int
+smd_named_open_on_edge(const char *name, uint32_t edge, smd_channel_t **_ch,
+ void *priv, void (*notify)(void *, unsigned))
+{
+ return -ENODEV;
+}
+
+static inline void smd_enable_read_intr(smd_channel_t *ch)
+{
+}
+
+static inline void smd_disable_read_intr(smd_channel_t *ch)
+{
+}
+
+static inline int smd_write_start(smd_channel_t *ch, int len)
+{
+ return -ENODEV;
+}
+
+static inline int
+smd_write_segment(smd_channel_t *ch, void *data, int len, int user_buf)
+{
+ return -ENODEV;
+}
+
+static inline int smd_write_end(smd_channel_t *ch)
+{
+ return -ENODEV;
+}
+#endif
+
#endif
diff --git a/arch/arm/mach-msm/include/mach/rpm-regulator.h b/arch/arm/mach-msm/include/mach/rpm-regulator.h
index 7ffa2985..f857ab8 100644
--- a/arch/arm/mach-msm/include/mach/rpm-regulator.h
+++ b/arch/arm/mach-msm/include/mach/rpm-regulator.h
@@ -132,6 +132,7 @@
RPM_VREG_VOTER3, /* for use by other drivers */
RPM_VREG_VOTER4, /* for use by the acpu-clock driver */
RPM_VREG_VOTER5, /* for use by the acpu-clock driver */
+ RPM_VREG_VOTER6, /* for use by the acpu-clock driver */
RPM_VREG_VOTER_COUNT,
};
diff --git a/arch/arm/mach-msm/include/mach/socinfo.h b/arch/arm/mach-msm/include/mach/socinfo.h
index c8867bd..dbde068 100644
--- a/arch/arm/mach-msm/include/mach/socinfo.h
+++ b/arch/arm/mach-msm/include/mach/socinfo.h
@@ -210,7 +210,11 @@
static inline int cpu_is_msm8930(void)
{
+#ifdef CONFIG_ARCH_MSM8930
return read_msm_cpu_type() == MSM_CPU_8930;
+#else
+ return 0;
+#endif
}
static inline int cpu_is_fsm9xxx(void)
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 171f482..65f5da0 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -282,6 +282,8 @@
MSM_CHIP_DEVICE(QGIC_DIST, COPPER),
MSM_CHIP_DEVICE(QGIC_CPU, COPPER),
MSM_CHIP_DEVICE(TLMM, COPPER),
+ MSM_CHIP_DEVICE(TMR, COPPER),
+ MSM_CHIP_DEVICE(TMR0, COPPER),
};
void __init msm_map_copper_io(void)
diff --git a/arch/arm/mach-msm/iommu.c b/arch/arm/mach-msm/iommu.c
index 0a77781..442a1b4 100644
--- a/arch/arm/mach-msm/iommu.c
+++ b/arch/arm/mach-msm/iommu.c
@@ -1006,6 +1006,9 @@
static int __init msm_iommu_init(void)
{
+ if (!msm_soc_version_supports_iommu())
+ return -ENODEV;
+
setup_iommu_tex_classes();
register_iommu(&msm_iommu_ops);
return 0;
diff --git a/arch/arm/mach-msm/iommu_dev.c b/arch/arm/mach-msm/iommu_dev.c
index ca2ecc6..d1dd3ed 100644
--- a/arch/arm/mach-msm/iommu_dev.c
+++ b/arch/arm/mach-msm/iommu_dev.c
@@ -69,7 +69,7 @@
r.name = ctx_name;
found = device_for_each_child(&msm_iommu_root_dev->dev, &r, each_iommu);
- if (!found) {
+ if (!found || !dev_get_drvdata(r.dev)) {
pr_err("Could not find context <%s>\n", ctx_name);
goto fail;
}
diff --git a/arch/arm/mach-msm/modem-8960.c b/arch/arm/mach-msm/modem-8960.c
index 03afc94..7bcd844 100644
--- a/arch/arm/mach-msm/modem-8960.c
+++ b/arch/arm/mach-msm/modem-8960.c
@@ -227,7 +227,7 @@
{
int ret;
- if (!cpu_is_msm8960())
+ if (!cpu_is_msm8960() && !cpu_is_msm8930())
return -ENODEV;
ret = smsm_state_cb_register(SMSM_MODEM_STATE, SMSM_RESET,
diff --git a/arch/arm/mach-msm/msm-buspm-dev.c b/arch/arm/mach-msm/msm-buspm-dev.c
new file mode 100644
index 0000000..296418d
--- /dev/null
+++ b/arch/arm/mach-msm/msm-buspm-dev.c
@@ -0,0 +1,256 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* #define DEBUG */
+
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/device.h>
+#include <linux/uaccess.h>
+#include <linux/miscdevice.h>
+#include <linux/memory_alloc.h>
+#include "msm-buspm-dev.h"
+
+#define MSM_BUSPM_DRV_NAME "msm-buspm-dev"
+
+/*
+ * Allocate kernel buffer.
+ * Currently limited to one buffer per file descriptor. If alloc() is
+ * called twice for the same descriptor, the original buffer is freed.
+ * There is also no locking protection so the same descriptor can not be shared.
+ */
+
+static inline void *msm_buspm_dev_get_vaddr(struct file *filp)
+{
+ struct msm_buspm_map_dev *dev = filp->private_data;
+
+ return (dev) ? dev->vaddr : NULL;
+}
+
+static inline unsigned long msm_buspm_dev_get_paddr(struct file *filp)
+{
+ struct msm_buspm_map_dev *dev = filp->private_data;
+
+ return (dev) ? dev->paddr : 0L;
+}
+
+static void msm_buspm_dev_free(struct file *filp)
+{
+ struct msm_buspm_map_dev *dev = filp->private_data;
+
+ if (dev) {
+ pr_debug("freeing memory at 0x%p\n", dev->vaddr);
+ free_contiguous_memory(dev->vaddr);
+ dev->paddr = 0L;
+ dev->vaddr = NULL;
+ }
+}
+
+static int msm_buspm_dev_open(struct inode *inode, struct file *filp)
+{
+ struct msm_buspm_map_dev *dev;
+
+ if (capable(CAP_SYS_ADMIN)) {
+ dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+ if (dev)
+ filp->private_data = dev;
+ else
+ return -ENOMEM;
+ } else {
+ return -EPERM;
+ }
+
+ return 0;
+}
+
+static int
+msm_buspm_dev_alloc(struct file *filp, struct buspm_alloc_params data)
+{
+ unsigned long paddr;
+ void *vaddr;
+ struct msm_buspm_map_dev *dev = filp->private_data;
+
+ /* If buffer already allocated, then free it */
+ if (dev->vaddr)
+ msm_buspm_dev_free(filp);
+
+ /* Allocate uncached memory */
+ vaddr = allocate_contiguous_ebi(data.size, PAGE_SIZE, 0);
+ paddr = (vaddr) ? memory_pool_node_paddr(vaddr) : 0L;
+
+ if (vaddr == NULL) {
+ pr_err("allocation of 0x%x bytes failed", data.size);
+ return -ENOMEM;
+ }
+
+ dev->vaddr = vaddr;
+ dev->paddr = paddr;
+ dev->buflen = data.size;
+ filp->f_pos = 0;
+ pr_debug("virt addr = 0x%p\n", dev->vaddr);
+ pr_debug("phys addr = 0x%lx\n", dev->paddr);
+
+ return 0;
+}
+
+static long
+msm_buspm_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
+{
+ struct buspm_xfer_req xfer;
+ struct buspm_alloc_params alloc_data;
+ unsigned long paddr;
+ int retval = 0;
+ void *buf = msm_buspm_dev_get_vaddr(filp);
+ unsigned char *dbgbuf = buf;
+
+ switch (cmd) {
+ case MSM_BUSPM_IOC_FREE:
+ pr_debug("cmd = 0x%x (FREE)\n", cmd);
+ msm_buspm_dev_free(filp);
+ break;
+
+ case MSM_BUSPM_IOC_ALLOC:
+ pr_debug("cmd = 0x%x (ALLOC)\n", cmd);
+ retval = __get_user(alloc_data.size, (size_t __user *)arg);
+
+ if (retval == 0)
+ retval = msm_buspm_dev_alloc(filp, alloc_data);
+ break;
+
+ case MSM_BUSPM_IOC_RD_PHYS_ADDR:
+ pr_debug("Read Physical Address\n");
+ paddr = msm_buspm_dev_get_paddr(filp);
+ if (paddr == 0L) {
+ retval = -EINVAL;
+ } else {
+ pr_debug("phys addr = 0x%lx\n", paddr);
+ retval = __put_user(paddr,
+ (unsigned long __user *)arg);
+ }
+ break;
+
+ case MSM_BUSPM_IOC_RDBUF:
+ pr_debug("Read Buffer: 0x%x%x%x%x\n",
+ dbgbuf[0], dbgbuf[1], dbgbuf[2], dbgbuf[3]);
+
+ if (!buf) {
+ retval = -EINVAL;
+ break;
+ }
+
+ if (copy_from_user(&xfer, (void __user *)arg, sizeof(xfer))) {
+ retval = -EFAULT;
+ break;
+ }
+
+ if ((xfer.size <= sizeof(buf)) &&
+ (copy_to_user((void __user *)xfer.data, buf,
+ xfer.size))) {
+ retval = -EFAULT;
+ break;
+ }
+ break;
+
+ case MSM_BUSPM_IOC_WRBUF:
+ pr_debug("Write Buffer\n");
+
+ if (!buf) {
+ retval = -EINVAL;
+ break;
+ }
+
+ if (copy_from_user(&xfer, (void __user *)arg, sizeof(xfer))) {
+ retval = -EFAULT;
+ break;
+ }
+
+ if ((sizeof(buf) <= xfer.size) &&
+ (copy_from_user(buf, (void __user *)xfer.data,
+ xfer.size))) {
+ retval = -EFAULT;
+ break;
+ }
+ break;
+
+ default:
+ pr_debug("Unknown command 0x%x\n", cmd);
+ retval = -EINVAL;
+ break;
+ }
+
+ return retval;
+}
+
+static int msm_buspm_dev_release(struct inode *inode, struct file *filp)
+{
+ struct msm_buspm_map_dev *dev = filp->private_data;
+
+ msm_buspm_dev_free(filp);
+ kfree(dev);
+ filp->private_data = NULL;
+
+ return 0;
+}
+
+static int msm_buspm_dev_mmap(struct file *filp, struct vm_area_struct *vma)
+{
+ pr_debug("vma = 0x%p\n", vma);
+
+ /* Mappings are uncached */
+ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+ if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
+ vma->vm_end - vma->vm_start, vma->vm_page_prot))
+ return -EFAULT;
+
+ return 0;
+}
+
+static const struct file_operations msm_buspm_dev_fops = {
+ .owner = THIS_MODULE,
+ .mmap = msm_buspm_dev_mmap,
+ .open = msm_buspm_dev_open,
+ .unlocked_ioctl = msm_buspm_dev_ioctl,
+ .llseek = noop_llseek,
+ .release = msm_buspm_dev_release,
+};
+
+struct miscdevice msm_buspm_misc = {
+ .minor = MISC_DYNAMIC_MINOR,
+ .name = MSM_BUSPM_DRV_NAME,
+ .fops = &msm_buspm_dev_fops,
+};
+
+static int __init msm_buspm_dev_init(void)
+{
+ int ret = 0;
+
+ ret = misc_register(&msm_buspm_misc);
+ if (ret < 0)
+ pr_err("%s: Cannot register misc device\n", __func__);
+
+ return ret;
+}
+
+static void __exit msm_buspm_dev_exit(void)
+{
+ misc_deregister(&msm_buspm_misc);
+}
+module_init(msm_buspm_dev_init);
+module_exit(msm_buspm_dev_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_VERSION("1.0");
+MODULE_ALIAS("platform:"MSM_BUSPM_DRV_NAME);
diff --git a/arch/arm/mach-msm/msm-buspm-dev.h b/arch/arm/mach-msm/msm-buspm-dev.h
new file mode 100644
index 0000000..5839087
--- /dev/null
+++ b/arch/arm/mach-msm/msm-buspm-dev.h
@@ -0,0 +1,50 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MSM_BUSPM_DEV_H__
+#define __MSM_BUSPM_DEV_H__
+
+#include <linux/ioctl.h>
+
+struct msm_buspm_map_dev {
+ void *vaddr;
+ unsigned long paddr;
+ size_t buflen;
+};
+
+/* Read/write data into kernel buffer */
+struct buspm_xfer_req {
+ int size; /* Size of this request, in bytes */
+ void *data; /* Data buffer to transfer data to/from */
+};
+
+struct buspm_alloc_params {
+ int size;
+};
+
+#define MSM_BUSPM_IOC_MAGIC 'p'
+
+#define MSM_BUSPM_IOC_FREE \
+ _IOW(MSM_BUSPM_IOC_MAGIC, 0, void *)
+
+#define MSM_BUSPM_IOC_ALLOC \
+ _IOW(MSM_BUSPM_IOC_MAGIC, 1, size_t)
+
+#define MSM_BUSPM_IOC_RDBUF \
+ _IOW(MSM_BUSPM_IOC_MAGIC, 2, struct buspm_xfer_req)
+
+#define MSM_BUSPM_IOC_WRBUF \
+ _IOW(MSM_BUSPM_IOC_MAGIC, 3, struct buspm_xfer_req)
+
+#define MSM_BUSPM_IOC_RD_PHYS_ADDR \
+ _IOR(MSM_BUSPM_IOC_MAGIC, 4, unsigned long)
+#endif
diff --git a/arch/arm/mach-msm/msm_rq_stats.c b/arch/arm/mach-msm/msm_rq_stats.c
index a39703a..425000d 100644
--- a/arch/arm/mach-msm/msm_rq_stats.c
+++ b/arch/arm/mach-msm/msm_rq_stats.c
@@ -27,7 +27,7 @@
#include <linux/spinlock.h>
#include <linux/rq_stats.h>
-#define MAX_LONG_SIZE 16
+#define MAX_LONG_SIZE 24
#define DEFAULT_RQ_POLL_JIFFIES 1
#define DEFAULT_DEF_TIMER_JIFFIES 5
@@ -55,7 +55,7 @@
rq_info.rq_avg = 0;
spin_unlock_irqrestore(&rq_lock, flags);
- return sprintf(buf, "%d.%d\n", val/10, val%10);
+ return snprintf(buf, PAGE_SIZE, "%d.%d\n", val/10, val%10);
}
static ssize_t show_run_queue_poll_ms(struct kobject *kobj,
@@ -95,8 +95,10 @@
static ssize_t show_def_timer_ms(struct kobject *kobj,
struct kobj_attribute *attr, char *buf)
{
- return snprintf(buf, MAX_LONG_SIZE, "%lu\n",
- rq_info.def_timer_jiffies);
+ int64_t diff_ms;
+ diff_ms = ktime_to_ns(ktime_get()) - rq_info.def_start_time;
+ do_div(diff_ms, 1000 * 1000);
+ return snprintf(buf, MAX_LONG_SIZE, "%lld\n", diff_ms);
}
static ssize_t store_def_timer_ms(struct kobject *kobj,
diff --git a/arch/arm/mach-msm/msm_xo.c b/arch/arm/mach-msm/msm_xo.c
index a82d4d5..1e9c05f 100644
--- a/arch/arm/mach-msm/msm_xo.c
+++ b/arch/arm/mach-msm/msm_xo.c
@@ -190,11 +190,11 @@
{
int ret;
unsigned long flags;
- /* TODO: Remove or fix this function for 8064 once xo is in */
- if (cpu_is_apq8064())
+
+ if (!xo_voter)
return 0;
- if (mode >= NUM_MSM_XO_MODES)
+ if (mode >= NUM_MSM_XO_MODES || IS_ERR(xo_voter))
return -EINVAL;
spin_lock_irqsave(&msm_xo_lock, flags);
@@ -221,7 +221,10 @@
unsigned long flags;
struct msm_xo_voter *xo_voter;
- /* TODO: Remove or fix this function for 8064 once xo is in */
+ /*
+ * TODO: Remove early return for 8064 once RPM XO voting support
+ * is available.
+ */
if (cpu_is_apq8064())
return NULL;
@@ -271,6 +274,9 @@
{
unsigned long flags;
+ if (!xo_voter || IS_ERR(xo_voter))
+ return;
+
spin_lock_irqsave(&msm_xo_lock, flags);
__msm_xo_mode_vote(xo_voter, MSM_XO_MODE_OFF);
xo_voter->xo->votes[MSM_XO_MODE_OFF]--;
diff --git a/arch/arm/mach-msm/pm-8x60.c b/arch/arm/mach-msm/pm-8x60.c
index 911d546..ad6da6a 100644
--- a/arch/arm/mach-msm/pm-8x60.c
+++ b/arch/arm/mach-msm/pm-8x60.c
@@ -48,6 +48,7 @@
#include "spm.h"
#include "timer.h"
#include "qdss.h"
+#include "pm-boot.h"
/******************************************************************************
* Debug Definitions
@@ -161,7 +162,7 @@
}
if (ret > 0) {
- strcat(buf, "\n");
+ strlcat(buf, "\n", PAGE_SIZE);
ret++;
}
@@ -215,7 +216,7 @@
{
char cpu_name[8];
struct kobject *cpu_kobj;
- struct msm_pm_sysfs_sleep_mode *mode;
+ struct msm_pm_sysfs_sleep_mode *mode = NULL;
int i, j, k;
int ret;
@@ -649,7 +650,7 @@
entry = (!dev->cpu || from_idle) ?
msm_pm_collapse_exit : msm_secondary_startup;
- msm_pm_write_boot_vector(dev->cpu, virt_to_phys(entry));
+ msm_pm_boot_config_before_pc(dev->cpu, virt_to_phys(entry));
if (MSM_PM_DEBUG_RESET_VECTOR & msm_pm_debug_mask)
pr_info("CPU%u: %s: program vector to %p\n",
@@ -661,6 +662,8 @@
collapsed = msm_pm_collapse();
+ msm_pm_boot_config_after_pc(dev->cpu);
+
if (collapsed) {
#ifdef CONFIG_VFP
vfp_reinit();
@@ -1179,15 +1182,6 @@
init_completion(&dev->cpu_killed);
#endif
}
-#ifdef CONFIG_MSM_SCM
- ret = scm_set_boot_addr((void *)virt_to_phys(msm_pm_boot_entry),
- SCM_FLAG_WARMBOOT_CPU0 | SCM_FLAG_WARMBOOT_CPU1);
- if (ret) {
- pr_err("%s: failed to set up scm boot addr: %d\n",
- __func__, ret);
- return ret;
- }
-#endif
#ifdef CONFIG_MSM_IDLE_STATS
for_each_possible_cpu(cpu) {
diff --git a/arch/arm/mach-msm/pm-boot.c b/arch/arm/mach-msm/pm-boot.c
new file mode 100644
index 0000000..6becc61
--- /dev/null
+++ b/arch/arm/mach-msm/pm-boot.c
@@ -0,0 +1,114 @@
+/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include "scm-boot.h"
+#include "idle.h"
+#include "pm-boot.h"
+
+static uint32_t *msm_pm_reset_vector;
+static uint32_t saved_vector[2];
+static void (*msm_pm_boot_before_pc)(unsigned int cpu, unsigned long entry);
+static void (*msm_pm_boot_after_pc)(unsigned int cpu);
+
+#ifdef CONFIG_MSM_SCM
+static int __init msm_pm_tz_boot_init(void)
+{
+ int flag = 0;
+ if (num_possible_cpus() == 1)
+ flag = SCM_FLAG_WARMBOOT_CPU0;
+ else if (num_possible_cpus() == 2)
+ flag = SCM_FLAG_WARMBOOT_CPU0 | SCM_FLAG_WARMBOOT_CPU1;
+ else
+ __WARN();
+
+ return scm_set_boot_addr((void *)virt_to_phys(msm_pm_boot_entry), flag);
+}
+
+static void msm_pm_config_tz_before_pc(unsigned int cpu,
+ unsigned long entry)
+{
+ msm_pm_write_boot_vector(cpu, entry);
+}
+#else
+static int __init msm_pm_tz_boot_init(void)
+{
+ return 0;
+};
+
+static inline void msm_pm_config_tz_before_pc(unsigned int cpu,
+ unsigned long entry) {}
+#endif
+
+static int __init msm_pm_boot_reset_vector_init(uint32_t *reset_vector)
+{
+ WARN_ON(!reset_vector);
+ msm_pm_reset_vector = reset_vector;
+ mb();
+
+ return 0;
+}
+
+static void msm_pm_config_rst_vector_before_pc(unsigned int cpu,
+ unsigned long entry)
+{
+ saved_vector[0] = msm_pm_reset_vector[0];
+ saved_vector[1] = msm_pm_reset_vector[1];
+ msm_pm_reset_vector[0] = 0xE51FF004; /* ldr pc, 4 */
+ msm_pm_reset_vector[1] = entry;
+}
+
+static void msm_pm_config_rst_vector_after_pc(unsigned int cpu)
+{
+ msm_pm_reset_vector[0] = saved_vector[0];
+ msm_pm_reset_vector[1] = saved_vector[1];
+}
+
+void msm_pm_boot_config_before_pc(unsigned int cpu, unsigned long entry)
+{
+ if (msm_pm_boot_before_pc)
+ msm_pm_boot_before_pc(cpu, entry);
+}
+
+void msm_pm_boot_config_after_pc(unsigned int cpu)
+{
+ if (msm_pm_boot_after_pc)
+ msm_pm_boot_after_pc(cpu);
+}
+
+int __init msm_pm_boot_init(int tz_available, uint32_t* address)
+{
+ int ret = 0;
+
+ switch (tz_available) {
+ case MSM_PM_BOOT_CONFIG_TZ:
+ ret = msm_pm_tz_boot_init();
+ msm_pm_boot_before_pc = msm_pm_config_tz_before_pc;
+ msm_pm_boot_after_pc = NULL;
+ break;
+ case MSM_PM_BOOT_CONFIG_RESET_VECTOR:
+ ret = msm_pm_boot_reset_vector_init(address);
+ msm_pm_boot_before_pc
+ = msm_pm_config_rst_vector_before_pc;
+ msm_pm_boot_after_pc
+ = msm_pm_config_rst_vector_after_pc;
+ break;
+ default:
+ __WARN();
+ }
+
+ return ret;
+}
diff --git a/arch/arm/mach-msm/pm-boot.h b/arch/arm/mach-msm/pm-boot.h
new file mode 100644
index 0000000..7e1a439
--- /dev/null
+++ b/arch/arm/mach-msm/pm-boot.h
@@ -0,0 +1,25 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef _ARCH_ARM_MACH_MSM_PM_BOOT_H
+#define _ARCH_ARM_MACH_MSM_PM_BOOT_H
+
+enum {
+ MSM_PM_BOOT_CONFIG_TZ = 0,
+ MSM_PM_BOOT_CONFIG_RESET_VECTOR = 1,
+};
+
+int __init msm_pm_boot_init(int boot_config, uint32_t* address);
+void msm_pm_boot_config_before_pc(unsigned int cpu, unsigned long entry);
+void msm_pm_boot_config_after_pc(unsigned int cpu);
+
+#endif
diff --git a/arch/arm/mach-msm/pm.c b/arch/arm/mach-msm/pm.c
index 9e19d40..d684a5a 100644
--- a/arch/arm/mach-msm/pm.c
+++ b/arch/arm/mach-msm/pm.c
@@ -45,6 +45,7 @@
#include "gpio.h"
#include "timer.h"
#include "pm.h"
+#include "pm-boot.h"
enum {
MSM_PM_DEBUG_SUSPEND = 1U << 0,
@@ -100,7 +101,6 @@
struct smsm_interrupt_info_ext *int_info_ext;
} msm_pm_sma;
-static uint32_t *msm_pm_reset_vector;
static uint32_t msm_pm_max_sleep_time;
static struct msm_pm_platform_data *msm_pm_modes;
@@ -238,7 +238,6 @@
static int msm_sleep(int sleep_mode, uint32_t sleep_delay,
uint32_t sleep_limit, int from_idle)
{
- uint32_t saved_vector[2];
int collapsed;
uint32_t enter_state;
uint32_t enter_wait_set = 0;
@@ -344,17 +343,10 @@
msm_pm_sma.int_info->aArm_en_mask,
msm_pm_sma.int_info->aArm_wakeup_reason,
msm_pm_sma.int_info->aArm_interrupts_pending);
- saved_vector[0] = msm_pm_reset_vector[0];
- saved_vector[1] = msm_pm_reset_vector[1];
- msm_pm_reset_vector[0] = 0xE51FF004; /* ldr pc, 4 */
- msm_pm_reset_vector[1] = virt_to_phys(msm_pm_collapse_exit);
- if (msm_pm_debug_mask & MSM_PM_DEBUG_RESET_VECTOR)
- printk(KERN_INFO "msm_sleep(): vector %x %x -> "
- "%x %x\n", saved_vector[0], saved_vector[1],
- msm_pm_reset_vector[0], msm_pm_reset_vector[1]);
+ msm_pm_boot_config_before_pc(smp_processor_id(),
+ virt_to_phys(msm_pm_collapse_exit));
collapsed = msm_pm_collapse();
- msm_pm_reset_vector[0] = saved_vector[0];
- msm_pm_reset_vector[1] = saved_vector[1];
+ msm_pm_boot_config_after_pc(smp_processor_id());
if (collapsed) {
cpu_init();
local_fiq_enable();
@@ -871,22 +863,6 @@
return -ENODEV;
}
-#if defined(CONFIG_ARCH_MSM_SCORPION) && !defined(CONFIG_MSM_SMP)
- /* The bootloader is responsible for initializing many of Scorpion's
- * coprocessor registers for things like cache timing. The state of
- * these coprocessor registers is lost on reset, so part of the
- * bootloader must be re-executed. Do not overwrite the reset vector
- * or bootloader area.
- */
- msm_pm_reset_vector = (uint32_t *) PAGE_OFFSET;
-#else
- msm_pm_reset_vector = ioremap(0, PAGE_SIZE);
- if (msm_pm_reset_vector == NULL) {
- printk(KERN_ERR "msm_pm_init: failed to map reset vector\n");
- return -ENODEV;
- }
-#endif /* CONFIG_ARCH_MSM_SCORPION */
-
ret = msm_timer_init_time_sync(msm_pm_timeout);
if (ret)
return ret;
diff --git a/arch/arm/mach-msm/pm2.c b/arch/arm/mach-msm/pm2.c
index 6b24a02..4cdd7ae 100644
--- a/arch/arm/mach-msm/pm2.c
+++ b/arch/arm/mach-msm/pm2.c
@@ -61,6 +61,7 @@
#include "pm.h"
#include "spm.h"
#include "sirc.h"
+#include "pm-boot.h"
/******************************************************************************
* Debug Definitions
@@ -962,7 +963,6 @@
*
*****************************************************************************/
static struct msm_pm_smem_t *msm_pm_smem_data;
-static uint32_t *msm_pm_reset_vector;
static atomic_t msm_pm_init_done = ATOMIC_INIT(0);
static int msm_pm_modem_busy(void)
@@ -991,7 +991,6 @@
{
struct msm_pm_polled_group state_grps[2];
unsigned long saved_acpuclk_rate;
- uint32_t saved_vector[2];
int collapsed = 0;
int ret;
@@ -1078,15 +1077,8 @@
goto power_collapse_early_exit;
}
- saved_vector[0] = msm_pm_reset_vector[0];
- saved_vector[1] = msm_pm_reset_vector[1];
- msm_pm_reset_vector[0] = 0xE51FF004; /* ldr pc, 4 */
- msm_pm_reset_vector[1] = virt_to_phys(msm_pm_collapse_exit);
-
- MSM_PM_DPRINTK(MSM_PM_DEBUG_RESET_VECTOR, KERN_INFO,
- "%s(): vector %x %x -> %x %x\n", __func__,
- saved_vector[0], saved_vector[1],
- msm_pm_reset_vector[0], msm_pm_reset_vector[1]);
+ msm_pm_boot_config_before_pc(smp_processor_id(),
+ virt_to_phys(msm_pm_collapse_exit));
#ifdef CONFIG_VFP
if (from_idle)
@@ -1103,8 +1095,7 @@
l2x0_resume(collapsed);
#endif
- msm_pm_reset_vector[0] = saved_vector[0];
- msm_pm_reset_vector[1] = saved_vector[1];
+ msm_pm_boot_config_after_pc(smp_processor_id());
if (collapsed) {
#ifdef CONFIG_VFP
@@ -1283,7 +1274,6 @@
*/
static int msm_pm_power_collapse_standalone(void)
{
- uint32_t saved_vector[2];
int collapsed = 0;
int ret;
@@ -1293,15 +1283,8 @@
ret = msm_spm_set_low_power_mode(MSM_SPM_MODE_POWER_COLLAPSE, false);
WARN_ON(ret);
- saved_vector[0] = msm_pm_reset_vector[0];
- saved_vector[1] = msm_pm_reset_vector[1];
- msm_pm_reset_vector[0] = 0xE51FF004; /* ldr pc, 4 */
- msm_pm_reset_vector[1] = virt_to_phys(msm_pm_collapse_exit);
-
- MSM_PM_DPRINTK(MSM_PM_DEBUG_RESET_VECTOR, KERN_INFO,
- "%s(): vector %x %x -> %x %x\n", __func__,
- saved_vector[0], saved_vector[1],
- msm_pm_reset_vector[0], msm_pm_reset_vector[1]);
+ msm_pm_boot_config_before_pc(smp_processor_id(),
+ virt_to_phys(msm_pm_collapse_exit));
#ifdef CONFIG_VFP
vfp_flush_context();
@@ -1317,8 +1300,7 @@
l2x0_resume(collapsed);
#endif
- msm_pm_reset_vector[0] = saved_vector[0];
- msm_pm_reset_vector[1] = saved_vector[1];
+ msm_pm_boot_config_after_pc(smp_processor_id());
if (collapsed) {
#ifdef CONFIG_VFP
@@ -1836,21 +1818,6 @@
printk(KERN_ERR "%s: failed to get smsm_data\n", __func__);
return -ENODEV;
}
-#if defined(CONFIG_ARCH_MSM_SCORPION) && !defined(CONFIG_MSM_SMP)
- /* The bootloader is responsible for initializing many of Scorpion's
- * coprocessor registers for things like cache timing. The state of
- * these coprocessor registers is lost on reset, so part of the
- * bootloader must be re-executed. Do not overwrite the reset vector
- * or bootloader area.
- */
- msm_pm_reset_vector = (uint32_t *) PAGE_OFFSET;
-#else
- msm_pm_reset_vector = ioremap(0, PAGE_SIZE);
- if (msm_pm_reset_vector == NULL) {
- printk(KERN_ERR "%s: failed to map reset vector\n", __func__);
- return -ENODEV;
- }
-#endif /* CONFIG_ARCH_MSM_SCORPION */
ret = msm_timer_init_time_sync(msm_pm_timeout);
if (ret)
diff --git a/arch/arm/mach-msm/rpm_resources.c b/arch/arm/mach-msm/rpm_resources.c
index f2b3e88..e6b91ee 100644
--- a/arch/arm/mach-msm/rpm_resources.c
+++ b/arch/arm/mach-msm/rpm_resources.c
@@ -683,7 +683,7 @@
rc = param_get_uint(buf, &kp);
if (rc > 0) {
- strcat(buf, "\n");
+ strlcat(buf, "\n", PAGE_SIZE);
rc++;
}
@@ -1057,7 +1057,7 @@
static int __init msm_rpmrs_l2_counter_init(void)
{
- if (cpu_is_msm8960()) {
+ if (cpu_is_msm8960() || cpu_is_msm8930()) {
msm_rpmrs_l2_counter_addr = MSM_IMEM_BASE + L2_PC_COUNTER_ADDR;
writel_relaxed(msm_rpmrs_l2_reset_count,
msm_rpmrs_l2_counter_addr);
diff --git a/arch/arm/mach-msm/sdio_al.c b/arch/arm/mach-msm/sdio_al.c
index ace437b..891d655 100644
--- a/arch/arm/mach-msm/sdio_al.c
+++ b/arch/arm/mach-msm/sdio_al.c
@@ -15,7 +15,7 @@
*
* To be used with Qualcomm's SDIO-Client connected to this host.
*/
-#include <sdio_al_private.h>
+#include "sdio_al_private.h"
#include <linux/module.h>
#include <linux/scatterlist.h>
@@ -878,8 +878,7 @@
*/
static int write_lpm_info(struct sdio_al_device *sdio_al_dev)
{
- struct sdio_func *lpm_func =
- sdio_al_dev->card->sdio_func[sdio_al_dev->lpm_chan+1];
+ struct sdio_func *lpm_func = NULL;
int offset = offsetof(struct peer_sdioc_sw_mailbox, ch_config)+
sizeof(struct peer_sdioc_channel_config) *
sdio_al_dev->lpm_chan+
@@ -893,6 +892,14 @@
return -EINVAL;
}
+ if (!sdio_al_dev->card ||
+ !sdio_al_dev->card->sdio_func[sdio_al_dev->lpm_chan+1]) {
+ sdio_al_loge(sdio_al_dev->dev_log, MODULE_NAME
+ ": NULL card or lpm_func\n");
+ return -ENODEV;
+ }
+ lpm_func = sdio_al_dev->card->sdio_func[sdio_al_dev->lpm_chan+1];
+
pr_debug(MODULE_NAME ":write_lpm_info is_ok_to_sleep=%d, device %d\n",
sdio_al_dev->is_ok_to_sleep,
sdio_al_dev->host->index);
@@ -1900,8 +1907,7 @@
ch->poll_delay_msec = 0;
ch->num = i;
-
- ch->func = sdio_al_dev->card->sdio_func[ch->num+1];
+ ch->func = NULL;
ch->rx_pipe_index = ch->num*2;
ch->tx_pipe_index = ch->num*2+1;
@@ -1916,6 +1922,15 @@
ch->state = SDIO_CHANNEL_STATE_IDLE;
ch->sdio_al_dev = sdio_al_dev;
+ if (sdio_al_dev->card->sdio_func[ch->num+1]) {
+ ch->func =
+ sdio_al_dev->card->sdio_func[ch->num+1];
+ } else {
+ sdio_al_loge(sdio_al_dev->dev_log, MODULE_NAME
+ ": NULL func for channel %s\n",
+ ch->name);
+ goto exit_err;
+ }
} else {
ch->state = SDIO_CHANNEL_STATE_INVALID;
}
@@ -2802,18 +2817,19 @@
{
int ret;
int offset;
- struct sdio_func *wk_func;
+ struct sdio_func *wk_func = NULL;
u32 peer_operation;
int loop_count = 0;
- wk_func = sdio_al_dev->card->sdio_func[SDIO_AL_WAKEUP_FUNC-1];
- if (!wk_func) {
- sdio_al_loge(sdio_al_dev->dev_log, MODULE_NAME ":%s: NULL "
- "wakeup func:%d\n", __func__,
- SDIO_AL_WAKEUP_FUNC);
+ if (!sdio_al_dev->card ||
+ !sdio_al_dev->card->sdio_func[SDIO_AL_WAKEUP_FUNC-1]) {
+ sdio_al_loge(sdio_al_dev->dev_log, MODULE_NAME
+ ": NULL card or wk_func\n");
ret = -ENODEV;
goto exit;
}
+ wk_func = sdio_al_dev->card->sdio_func[SDIO_AL_WAKEUP_FUNC-1];
+
/* calculate offset of peer_operation field in sw mailbox struct */
offset = offsetof(struct peer_sdioc_sw_mailbox, ch_config) +
sizeof(struct peer_sdioc_channel_config) * ch->num +
@@ -3440,7 +3456,6 @@
*sdio_al_dev)
{
int ret = 0;
- struct sdio_func *func1 = NULL;
struct platform_device *pdev_arr[SDIO_AL_MAX_CHANNELS];
int j;
@@ -3449,13 +3464,6 @@
if (sdio_al_claim_mutex_and_verify_dev(sdio_al_dev, __func__))
return;
- if (!sdio_al_dev->card || !sdio_al_dev->card->sdio_func[0]) {
- sdio_al_loge(&sdio_al->gen_log, MODULE_NAME ": %s: "
- "NULL func1 for card %d", __func__,
- sdio_al_dev->host->index);
- goto exit_err;
- }
-
if (sdio_al_dev->state == CARD_REMOVED) {
sdio_al_logi(&sdio_al->gen_log, MODULE_NAME ": %s: "
"card %d is already removed", __func__,
@@ -3487,13 +3495,13 @@
ret = sdio_al_wake_up(sdio_al_dev, 1, NULL);
}
- if (!ret && (!sdio_al_dev->is_err)) {
- sdio_al_logi(sdio_al_dev->dev_log, MODULE_NAME
+ if (!ret && (!sdio_al_dev->is_err) && sdio_al_dev->card &&
+ sdio_al_dev->card->sdio_func[0]) {
+ sdio_al_logi(sdio_al_dev->dev_log, MODULE_NAME
": %s: sdio_release_irq for card %d",
__func__,
sdio_al_dev->host->index);
- func1 = sdio_al_dev->card->sdio_func[0];
- sdio_release_irq(sdio_al_dev->card->sdio_func[0]);
+ sdio_release_irq(sdio_al_dev->card->sdio_func[0]);
}
memset(pdev_arr, 0, sizeof(pdev_arr));
diff --git a/arch/arm/mach-msm/sdio_al_dloader.c b/arch/arm/mach-msm/sdio_al_dloader.c
index a172d2b..77a06a3 100644
--- a/arch/arm/mach-msm/sdio_al_dloader.c
+++ b/arch/arm/mach-msm/sdio_al_dloader.c
@@ -25,7 +25,7 @@
#include <linux/dma-mapping.h>
#include <mach/dma.h>
#include <linux/mmc/sdio_func.h>
-#include <sdio_al_private.h>
+#include "sdio_al_private.h"
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/kthread.h>
diff --git a/arch/arm/mach-msm/sdio_al_test.c b/arch/arm/mach-msm/sdio_al_test.c
index bc48821..8b9abcf 100644
--- a/arch/arm/mach-msm/sdio_al_test.c
+++ b/arch/arm/mach-msm/sdio_al_test.c
@@ -30,7 +30,7 @@
#include <linux/wakelock.h>
#include <linux/uaccess.h>
-#include <sdio_al_private.h>
+#include "sdio_al_private.h"
#include <linux/debugfs.h>
#include <linux/kthread.h>
diff --git a/arch/arm/mach-msm/sdio_cmux.c b/arch/arm/mach-msm/sdio_cmux.c
index f7c25c3..0aa5423 100644
--- a/arch/arm/mach-msm/sdio_cmux.c
+++ b/arch/arm/mach-msm/sdio_cmux.c
@@ -336,10 +336,12 @@
ch = &logical_ch[id];
mutex_lock(&ch->lc_lock);
+ ch->receive_cb = NULL;
+ mutex_lock(&ch->tx_lock);
+ ch->write_done = NULL;
+ mutex_unlock(&ch->tx_lock);
ch->is_local_open = 0;
ch->priv = NULL;
- ch->receive_cb = NULL;
- ch->write_done = NULL;
mutex_unlock(&ch->lc_lock);
sdio_cmux_write_cmd(ch->lc_id, CLOSE);
return 0;
diff --git a/arch/arm/mach-msm/smd.c b/arch/arm/mach-msm/smd.c
index 532a2f7..eeaab60 100644
--- a/arch/arm/mach-msm/smd.c
+++ b/arch/arm/mach-msm/smd.c
@@ -172,7 +172,8 @@
#define MSM_TRIG_A2DSPS_SMSM_INT
#define MSM_TRIG_A2WCNSS_SMD_INT
#define MSM_TRIG_A2WCNSS_SMSM_INT
-#elif defined(CONFIG_ARCH_MSM8960)
+#elif defined(CONFIG_ARCH_MSM8960) || defined(CONFIG_ARCH_MSM8930) || \
+ defined(CONFIG_ARCH_APQ8064)
#define MSM_TRIG_A2M_SMD_INT \
(smd_write_intr(1 << 3, MSM_APCS_GCC_BASE + 0x8))
#define MSM_TRIG_A2Q6_SMD_INT \
@@ -202,23 +203,6 @@
#define MSM_TRIG_A2DSPS_SMSM_INT
#define MSM_TRIG_A2WCNSS_SMD_INT
#define MSM_TRIG_A2WCNSS_SMSM_INT
-#elif defined(CONFIG_ARCH_APQ8064)
-#define MSM_TRIG_A2M_SMD_INT \
- (smd_write_intr(1 << 3, MSM_APCS_GCC_BASE + 0x8))
-#define MSM_TRIG_A2Q6_SMD_INT \
- (smd_write_intr(1 << 15, MSM_APCS_GCC_BASE + 0x8))
-#define MSM_TRIG_A2M_SMSM_INT \
- (smd_write_intr(1 << 4, MSM_APCS_GCC_BASE + 0x8))
-#define MSM_TRIG_A2Q6_SMSM_INT \
- (smd_write_intr(1 << 14, MSM_APCS_GCC_BASE + 0x8))
-#define MSM_TRIG_A2DSPS_SMD_INT \
- (smd_write_intr(1, MSM_SIC_NON_SECURE_BASE + 0x4080))
-#define MSM_TRIG_A2DSPS_SMSM_INT \
- (smd_write_intr(1, MSM_SIC_NON_SECURE_BASE + 0x4094))
-#define MSM_TRIG_A2WCNSS_SMD_INT \
- (smd_write_intr(1 << 25, MSM_APCS_GCC_BASE + 0x8))
-#define MSM_TRIG_A2WCNSS_SMSM_INT \
- (smd_write_intr(1 << 23, MSM_APCS_GCC_BASE + 0x8))
#elif defined(CONFIG_ARCH_FSM9XXX)
#define MSM_TRIG_A2Q6_SMD_INT \
(smd_write_intr(1 << 10, MSM_GCC_BASE + 0x8))
@@ -277,8 +261,10 @@
* trigger GPIO 40 to wake up RIVA from power collaspe
* not to be sent to customers
*/
- __raw_writel(0x0, MSM_TLMM_BASE + 0x1284);
- __raw_writel(0x2, MSM_TLMM_BASE + 0x1284);
+ if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 1) {
+ __raw_writel(0x0, MSM_TLMM_BASE + 0x1284);
+ __raw_writel(0x2, MSM_TLMM_BASE + 0x1284);
+ }
/* end workaround */
}
#else
@@ -297,17 +283,15 @@
if (smsm_info.intr_mask &&
(__raw_readl(SMSM_INTR_MASK_ADDR(smsm_entry, SMSM_Q6))
& notify_mask)) {
-#if !defined(CONFIG_ARCH_MSM8X60) && !defined(MCONFIG_ARCH_MSM8960)
uint32_t mux_val;
- if (smsm_info.intr_mux) {
+ if (cpu_is_qsd8x50() && smsm_info.intr_mux) {
mux_val = __raw_readl(
SMSM_INTR_MUX_ADDR(SMEM_APPS_Q6_SMSM));
mux_val++;
__raw_writel(mux_val,
SMSM_INTR_MUX_ADDR(SMEM_APPS_Q6_SMSM));
}
-#endif
MSM_TRIG_A2Q6_SMSM_INT;
}
@@ -2041,23 +2025,20 @@
{
unsigned long flags;
-#if !defined(CONFIG_ARCH_MSM8X60)
- uint32_t mux_val;
- static uint32_t prev_smem_q6_apps_smsm;
-
if (irq == INT_ADSP_A11_SMSM) {
- if (!smsm_info.intr_mux)
- return IRQ_HANDLED;
- mux_val = __raw_readl(SMSM_INTR_MUX_ADDR(SMEM_Q6_APPS_SMSM));
- if (mux_val != prev_smem_q6_apps_smsm)
- prev_smem_q6_apps_smsm = mux_val;
+ uint32_t mux_val;
+ static uint32_t prev_smem_q6_apps_smsm;
+
+ if (smsm_info.intr_mux && cpu_is_qsd8x50()) {
+ mux_val = __raw_readl(
+ SMSM_INTR_MUX_ADDR(SMEM_Q6_APPS_SMSM));
+ if (mux_val != prev_smem_q6_apps_smsm)
+ prev_smem_q6_apps_smsm = mux_val;
+ }
+
+ schedule_work(&smsm_cb_work);
return IRQ_HANDLED;
}
-#else
- if (irq == INT_ADSP_A11_SMSM)
- return IRQ_HANDLED;
-#endif
-
spin_lock_irqsave(&smem_lock, flags);
if (!smsm_info.state) {
@@ -2073,7 +2054,7 @@
/* If we get an interrupt and the apps SMSM_RESET
bit is already set, the modem is acking the
app's reset ack. */
- if (!cpu_is_msm8960())
+ if (!cpu_is_msm8960() && !cpu_is_msm8930())
apps &= ~SMSM_RESET;
/* Issue a fake irq to handle any
* smd state changes during reset
@@ -2084,7 +2065,7 @@
modem_queue_start_reset_notify();
} else if (modm & SMSM_RESET) {
- if (!cpu_is_msm8960())
+ if (!cpu_is_msm8960() && !cpu_is_msm8930())
apps |= SMSM_RESET;
pr_err("\nSMSM: Modem SMSM state changed to SMSM_RESET.");
diff --git a/arch/arm/mach-msm/socinfo.c b/arch/arm/mach-msm/socinfo.c
index 45653a2..9df1a68 100644
--- a/arch/arm/mach-msm/socinfo.c
+++ b/arch/arm/mach-msm/socinfo.c
@@ -210,9 +210,12 @@
[104] = MSM_CPU_9615,
[105] = MSM_CPU_9615,
- /* 8064 IDs*/
+ /* 8064 IDs */
[109] = MSM_CPU_8064,
+ /* 8930 IDs */
+ [116] = MSM_CPU_8930,
+
/* Uninitialized IDs are not known to run Linux.
MSM_CPU_UNKNOWN is set to 0 to ensure these IDs are
considered as unknown CPU. */
@@ -700,9 +703,12 @@
const int read_msm_cpu_type(void)
{
- if (machine_is_msm8960_sim())
+ if (machine_is_msm8960_sim() || machine_is_msm8960_rumi3())
return MSM_CPU_8960;
+ if (socinfo_get_msm_cpu() != MSM_CPU_UNKNOWN)
+ return socinfo_get_msm_cpu();
+
switch (read_cpuid_id()) {
case 0x510F02D0:
case 0x510F02D2:
@@ -712,13 +718,12 @@
case 0x510F04D0:
case 0x510F04D1:
case 0x510F04D2:
+ case 0x511F04D0:
+ case 0x512F04D0:
return MSM_CPU_8960;
- case 0x511F04D0:
- if (get_core_count() == 2)
- return MSM_CPU_8960;
- else
- return MSM_CPU_8930;
+ case 0x51404D11: /* We can't get here unless we are in bringup */
+ return MSM_CPU_8930;
case 0x510F06F0:
return MSM_CPU_8064;
diff --git a/arch/arm/mach-msm/subsystem_restart.c b/arch/arm/mach-msm/subsystem_restart.c
index b862ad4..ff699e2 100644
--- a/arch/arm/mach-msm/subsystem_restart.c
+++ b/arch/arm/mach-msm/subsystem_restart.c
@@ -569,7 +569,7 @@
n_restart_orders = ARRAY_SIZE(orders_8x60_all);
}
- if (cpu_is_msm8960()) {
+ if (cpu_is_msm8960() || cpu_is_msm8930()) {
restart_orders = restart_orders_8960;
n_restart_orders = ARRAY_SIZE(restart_orders_8960);
}
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index a0602f0..d9488ec 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -27,6 +27,7 @@
#include <asm/mach/time.h>
#include <asm/hardware/gic.h>
#include <asm/sched_clock.h>
+#include <asm/smp_plat.h>
#include <mach/msm_iomap.h>
#include <mach/irqs.h>
#include <mach/socinfo.h>
@@ -48,6 +49,10 @@
#define DG_TIMER_RATING 300
#endif
+#ifndef MSM_TMR0_BASE
+#define MSM_TMR0_BASE MSM_TMR_BASE
+#endif
+
#define MSM_DGT_SHIFT (5)
#define TIMER_MATCH_VAL 0x0000
@@ -278,14 +283,15 @@
static struct msm_clock *clockevent_to_clock(struct clock_event_device *evt)
{
-#ifdef CONFIG_SMP
int i;
+
+ if (!is_smp())
+ return container_of(evt, struct msm_clock, clockevent);
+
for (i = 0; i < NR_TIMERS; i++)
if (evt == &(msm_clocks[i].clockevent))
return &msm_clocks[i];
return &msm_clocks[msm_global_timer];
-#endif
- return container_of(evt, struct msm_clock, clockevent);
}
static int msm_timer_set_next_event(unsigned long cycles,
@@ -334,6 +340,7 @@
struct msm_clock *clock;
struct msm_clock_percpu_data *clock_state, *gpt_state;
unsigned long irq_flags;
+ struct irq_chip *chip;
clock = clockevent_to_clock(evt);
clock_state = &__get_cpu_var(msm_clocks_percpu)[clock->index];
@@ -353,11 +360,9 @@
get_cpu_var(msm_active_clock) = clock;
put_cpu_var(msm_active_clock);
__raw_writel(TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE);
- if (irq_get_chip(clock->irq.irq) &&
- irq_get_chip(clock->irq.irq)->irq_unmask) {
- irq_get_chip(clock->irq.irq)->irq_unmask(
- irq_get_irq_data(clock->irq.irq));
- }
+ chip = irq_get_chip(clock->irq.irq);
+ if (chip && chip->irq_unmask)
+ chip->irq_unmask(irq_get_irq_data(clock->irq.irq));
if (clock != &msm_clocks[MSM_CLOCK_GPT])
__raw_writel(TIMER_ENABLE_EN,
msm_clocks[MSM_CLOCK_GPT].regbase +
@@ -373,15 +378,14 @@
msm_read_timer_count(clock, LOCAL_TIMER) +
clock_state->sleep_offset;
__raw_writel(0, clock->regbase + TIMER_MATCH_VAL);
- if (irq_get_chip(clock->irq.irq) &&
- irq_get_chip(clock->irq.irq)->irq_mask) {
- irq_get_chip(clock->irq.irq)->irq_mask(
- irq_get_irq_data(clock->irq.irq));
- }
-#ifdef CONFIG_MSM_SMP
- if (clock != &msm_clocks[MSM_CLOCK_DGT] || smp_processor_id())
-#endif
+ chip = irq_get_chip(clock->irq.irq);
+ if (chip && chip->irq_mask)
+ chip->irq_mask(irq_get_irq_data(clock->irq.irq));
+
+ if (!is_smp() || clock != &msm_clocks[MSM_CLOCK_DGT]
+ || smp_processor_id())
__raw_writel(0, clock->regbase + TIMER_ENABLE);
+
if (clock != &msm_clocks[MSM_CLOCK_GPT]) {
gpt_state->in_sync = 0;
__raw_writel(0, msm_clocks[MSM_CLOCK_GPT].regbase +
@@ -393,7 +397,6 @@
local_irq_restore(irq_flags);
}
-/* Call this after SMP init */
void __iomem *msm_timer_get_timer0_base(void)
{
return MSM_TMR_BASE + global_timer_offset;
@@ -952,14 +955,12 @@
update_sched_clock(&cd, cyc, ((u32)~0) >> clock->shift);
}
-#ifdef CONFIG_MSM_SMP
int read_current_timer(unsigned long *timer_val)
{
struct msm_clock *dgt = &msm_clocks[MSM_CLOCK_DGT];
*timer_val = msm_read_timer_count(dgt, GLOBAL_TIMER);
return 0;
}
-#endif
static void __init msm_sched_clock_init(void)
{
@@ -972,6 +973,7 @@
{
int i;
int res;
+ struct irq_chip *chip;
struct msm_clock *dgt = &msm_clocks[MSM_CLOCK_DGT];
struct msm_clock *gpt = &msm_clocks[MSM_CLOCK_GPT];
@@ -994,10 +996,17 @@
else if (cpu_is_msm7x30() || cpu_is_msm8x55())
dgt->freq = 6144000;
else if (cpu_is_msm8x60()) {
+ global_timer_offset = MSM_TMR0_BASE - MSM_TMR_BASE;
dgt->freq = 6750000;
__raw_writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
- } else if (cpu_is_msm8960() || cpu_is_apq8064() || cpu_is_msm8930()
- || cpu_is_msm9615()) {
+ } else if (cpu_is_msm9615()) {
+ dgt->freq = 6750000;
+ __raw_writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
+ gpt->freq = 32765;
+ gpt_hz = 32765;
+ sclk_hz = 32765;
+ } else if (cpu_is_msm8960() || cpu_is_apq8064() || cpu_is_msm8930()) {
+ global_timer_offset = MSM_TMR0_BASE - MSM_TMR_BASE;
dgt->freq = 6750000;
__raw_writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
gpt->freq = 32765;
@@ -1055,16 +1064,19 @@
printk(KERN_ERR "msm_timer_init: setup_irq "
"failed for %s\n", cs->name);
- irq_get_chip(clock->irq.irq)->irq_mask(irq_get_irq_data(
- clock->irq.irq));
+ chip = irq_get_chip(clock->irq.irq);
+ if (chip && chip->irq_mask)
+ chip->irq_mask(irq_get_irq_data(clock->irq.irq));
clockevents_register_device(ce);
}
msm_sched_clock_init();
-#ifdef CONFIG_MSM_SMP
- __raw_writel(1, msm_clocks[MSM_CLOCK_DGT].regbase + TIMER_ENABLE);
- set_delay_fn(read_current_timer_delay_loop);
-#endif
+
+ if (is_smp()) {
+ __raw_writel(1,
+ msm_clocks[MSM_CLOCK_DGT].regbase + TIMER_ENABLE);
+ set_delay_fn(read_current_timer_delay_loop);
+ }
}
#ifdef CONFIG_SMP
@@ -1079,8 +1091,9 @@
if (!smp_processor_id())
return 0;
- global_timer_offset = MSM_TMR0_BASE - MSM_TMR_BASE;
- __raw_writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
+ if (cpu_is_msm8x60() || cpu_is_msm8960() || cpu_is_apq8064()
+ || cpu_is_msm8930())
+ __raw_writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
if (__get_cpu_var(first_boot)) {
__raw_writel(0, clock->regbase + TIMER_ENABLE);
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 350e5a9..aeaa173 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -791,6 +791,19 @@
{
int i, j, highmem = 0;
+#if (defined CONFIG_HIGHMEM) && (defined CONFIG_FIX_MOVABLE_ZONE)
+
+/* For now, we must ensure that a small highmem zone exists
+ * after most of it is transformed into the movable zone.
+ */
+#define MIN_HIGHMEM_SIZE (5 * SECTION_SIZE)
+ void *v_movable_start;
+
+ v_movable_start = __va(movable_reserved_start) - MIN_HIGHMEM_SIZE;
+
+ if (vmalloc_min > v_movable_start)
+ vmalloc_min = v_movable_start;
+#endif
for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
struct membank *bank = &meminfo.bank[j];
*bank = meminfo.bank[i];
diff --git a/drivers/base/iommu.c b/drivers/base/iommu.c
index 1377e85..6507d8b 100644
--- a/drivers/base/iommu.c
+++ b/drivers/base/iommu.c
@@ -45,6 +45,9 @@
struct iommu_domain *domain;
int ret;
+ if (!iommu_found())
+ return NULL;
+
domain = kmalloc(sizeof(*domain), GFP_KERNEL);
if (!domain)
return NULL;
@@ -64,6 +67,9 @@
void iommu_domain_free(struct iommu_domain *domain)
{
+ if (!iommu_found())
+ return;
+
iommu_ops->domain_destroy(domain);
kfree(domain);
}
@@ -71,12 +77,18 @@
int iommu_attach_device(struct iommu_domain *domain, struct device *dev)
{
+ if (!iommu_found())
+ return -ENODEV;
+
return iommu_ops->attach_dev(domain, dev);
}
EXPORT_SYMBOL_GPL(iommu_attach_device);
void iommu_detach_device(struct iommu_domain *domain, struct device *dev)
{
+ if (!iommu_found())
+ return;
+
iommu_ops->detach_dev(domain, dev);
}
EXPORT_SYMBOL_GPL(iommu_detach_device);
@@ -84,6 +96,9 @@
phys_addr_t iommu_iova_to_phys(struct iommu_domain *domain,
unsigned long iova)
{
+ if (!iommu_found())
+ return 0;
+
return iommu_ops->iova_to_phys(domain, iova);
}
EXPORT_SYMBOL_GPL(iommu_iova_to_phys);
@@ -91,6 +106,9 @@
int iommu_domain_has_cap(struct iommu_domain *domain,
unsigned long cap)
{
+ if (!iommu_found())
+ return -ENODEV;
+
return iommu_ops->domain_has_cap(domain, cap);
}
EXPORT_SYMBOL_GPL(iommu_domain_has_cap);
@@ -101,6 +119,9 @@
unsigned long invalid_mask;
size_t size;
+ if (!iommu_found())
+ return -ENODEV;
+
size = 0x1000UL << gfp_order;
invalid_mask = size - 1;
@@ -115,6 +136,9 @@
unsigned long invalid_mask;
size_t size;
+ if (!iommu_found())
+ return -ENODEV;
+
size = 0x1000UL << gfp_order;
invalid_mask = size - 1;
@@ -127,6 +151,9 @@
int iommu_map_range(struct iommu_domain *domain, unsigned int iova,
struct scatterlist *sg, unsigned int len, int prot)
{
+ if (!iommu_found())
+ return -ENODEV;
+
BUG_ON(iova & (~PAGE_MASK));
return iommu_ops->map_range(domain, iova, sg, len, prot);
@@ -136,6 +163,9 @@
int iommu_unmap_range(struct iommu_domain *domain, unsigned int iova,
unsigned int len)
{
+ if (!iommu_found())
+ return -ENODEV;
+
BUG_ON(iova & (~PAGE_MASK));
return iommu_ops->unmap_range(domain, iova, len);
diff --git a/drivers/bluetooth/hci_smd.c b/drivers/bluetooth/hci_smd.c
index 66bab6b..2ecddcf 100644
--- a/drivers/bluetooth/hci_smd.c
+++ b/drivers/bluetooth/hci_smd.c
@@ -147,7 +147,7 @@
goto out_data;
}
- rc = smd_read_from_cb(hsmd->data_channel, (void *)buf, len);
+ rc = smd_read(hsmd->data_channel, (void *)buf, len);
if (rc < len) {
BT_ERR("Error in reading from the channel");
goto out_data;
@@ -220,7 +220,7 @@
rc = -ENOMEM;
goto out_event;
}
- rc = smd_read_from_cb(hsmd->event_channel, (void *)buf, len);
+ rc = smd_read(hsmd->event_channel, (void *)buf, len);
if (rc < len) {
BT_ERR("Error in reading from the event channel");
goto out_event;
@@ -285,7 +285,7 @@
break;
case HCI_ACLDATA_PKT:
case HCI_SCODATA_PKT:
- avail = smd_write_avail(hs.event_channel);
+ avail = smd_write_avail(hs.data_channel);
if (!avail) {
BT_ERR("No space available for smd frame");
ret = -ENOSPC;
diff --git a/drivers/char/diag/diagchar_core.c b/drivers/char/diag/diagchar_core.c
index eabdb4f..0729753 100644
--- a/drivers/char/diag/diagchar_core.c
+++ b/drivers/char/diag/diagchar_core.c
@@ -142,7 +142,7 @@
if (diagpriv_data)
diagpriv_data->pid = current->tgid;
file->private_data = diagpriv_data;
- strncpy(driver->client_map[i].name, current->comm, 20);
+ strlcpy(driver->client_map[i].name, current->comm, 20);
driver->client_map[i].name[19] = '\0';
}
diff --git a/drivers/char/diag/diagfwd.c b/drivers/char/diag/diagfwd.c
index caf3901..0ae987a 100644
--- a/drivers/char/diag/diagfwd.c
+++ b/drivers/char/diag/diagfwd.c
@@ -503,7 +503,7 @@
} else {
if (len > 0) {
if (entry.client_id == MODEM_PROC && driver->ch) {
- if (cpu_is_msm8960() &&
+ if ((cpu_is_msm8960() || cpu_is_msm8930()) &&
(int)(*(char *)buf) == MODE_CMD)
if ((int)(*(char *)(buf+1)) == RESET_ID)
return;
@@ -542,7 +542,7 @@
temp += 2;
data_type = APPS_DATA;
/* Dont send any command other than mode reset */
- if (cpu_is_msm8960() && cmd_code == MODE_CMD) {
+ if ((cpu_is_msm8960() || cpu_is_msm8930()) && cmd_code == MODE_CMD) {
if (subsys_id != RESET_ID)
data_type = MODEM_DATA;
}
@@ -826,7 +826,8 @@
return 0;
}
/* Check for download command */
- else if ((cpu_is_msm8x60() || cpu_is_msm8960()) && (*buf == 0x3A)) {
+ else if ((cpu_is_msm8x60() || cpu_is_msm8960() || cpu_is_msm8930())
+ && (*buf == 0x3A)) {
/* send response back */
driver->apps_rsp_buf[0] = *buf;
ENCODE_RSP_AND_SEND(0);
diff --git a/drivers/char/diag/diagfwd_cntl.c b/drivers/char/diag/diagfwd_cntl.c
index 534c016..9730d4f 100644
--- a/drivers/char/diag/diagfwd_cntl.c
+++ b/drivers/char/diag/diagfwd_cntl.c
@@ -121,12 +121,10 @@
queue_work(driver->diag_wq, &(driver->diag_read_smd_cntl_work));
}
-#if defined(CONFIG_MSM_N_WAY_SMD)
static void diag_smd_qdsp_cntl_notify(void *ctxt, unsigned event)
{
queue_work(driver->diag_wq, &(driver->diag_read_smd_qdsp_cntl_work));
}
-#endif
static void diag_smd_wcnss_cntl_notify(void *ctxt, unsigned event)
{
diff --git a/drivers/char/hw_random/msm_rng.c b/drivers/char/hw_random/msm_rng.c
index 5937c78..b03a4ec 100644
--- a/drivers/char/hw_random/msm_rng.c
+++ b/drivers/char/hw_random/msm_rng.c
@@ -22,6 +22,7 @@
#include <linux/io.h>
#include <linux/err.h>
#include <linux/types.h>
+#include <mach/msm_iomap.h>
#include <mach/socinfo.h>
#define DRIVER_NAME "msm_rng"
@@ -36,11 +37,12 @@
#define PRNG_LFSR_CFG_MASK 0xFFFF0000
#define PRNG_LFSR_CFG_CLOCKS 0x0000DDDD
#define PRNG_CONFIG_MASK 0xFFFFFFFD
-#define PRNG_CONFIG_ENABLE 0x00000002
+#define PRNG_HW_ENABLE 0x00000002
#define MAX_HW_FIFO_DEPTH 16 /* FIFO is 16 words deep */
#define MAX_HW_FIFO_SIZE (MAX_HW_FIFO_DEPTH * 4) /* FIFO is 32 bits wide */
+
struct msm_rng_device {
struct platform_device *pdev;
void __iomem *base;
@@ -110,40 +112,43 @@
static int __devinit msm_rng_enable_hw(struct msm_rng_device *msm_rng_dev)
{
unsigned long val = 0;
+ unsigned long reg_val = 0;
int ret = 0;
- int error = 0;
+ /* Enable the PRNG CLK */
ret = clk_enable(msm_rng_dev->prng_clk);
if (ret) {
dev_err(&(msm_rng_dev->pdev)->dev,
"failed to enable clock in probe\n");
- error = -EPERM;
- return error;
+ return -EPERM;
}
-
- /* enable PRNG h/w*/
val = readl_relaxed(msm_rng_dev->base + PRNG_LFSR_CFG_OFFSET) &
- PRNG_LFSR_CFG_MASK;
+ PRNG_LFSR_CFG_MASK;
val |= PRNG_LFSR_CFG_MASK;
writel_relaxed(val, msm_rng_dev->base + PRNG_LFSR_CFG_OFFSET);
- /* The PRNG CONFIG register should be read after writing to the
- * PRNG_LFSR_CFG register.
- */
+ /* The PRNG CONFIG register should be first written before reading */
mb();
- val = readl_relaxed(msm_rng_dev->base + PRNG_CONFIG_OFFSET) &
- PRNG_CONFIG_MASK;
- val |= PRNG_CONFIG_ENABLE;
- writel_relaxed(val, msm_rng_dev->base + PRNG_CONFIG_OFFSET);
- /* The PRNG clk should be disabled only after we have enabled the
- * PRNG H/W by writting to the PRNG_CONFIG register.
- */
- mb();
+ /* Enable PRNG h/w only if it is NOT ON */
+ val = readl_relaxed(msm_rng_dev->base + PRNG_CONFIG_OFFSET) &
+ PRNG_HW_ENABLE;
+ /* PRNG H/W is not ON */
+ if (val != PRNG_HW_ENABLE) {
+ reg_val = readl_relaxed(msm_rng_dev->base + PRNG_CONFIG_OFFSET)
+ & PRNG_CONFIG_MASK;
+ reg_val |= PRNG_HW_ENABLE;
+ writel_relaxed(reg_val, msm_rng_dev->base + PRNG_CONFIG_OFFSET);
+
+ /* The PRNG clk should be disabled only after we enable the
+ * PRNG h/w by writing to the PRNG CONFIG register.
+ */
+ mb();
+ }
clk_disable(msm_rng_dev->prng_clk);
- return error;
+ return 0;
}
static int __devinit msm_rng_probe(struct platform_device *pdev)
@@ -188,8 +193,7 @@
platform_set_drvdata(pdev, msm_rng_dev);
/* Enable rng h/w */
- if (cpu_is_msm9615())
- error = msm_rng_enable_hw(msm_rng_dev);
+ error = msm_rng_enable_hw(msm_rng_dev);
if (error)
goto rollback_clk;
diff --git a/drivers/crypto/msm/qce40.c b/drivers/crypto/msm/qce40.c
index 4ef2e08..893933b 100644
--- a/drivers/crypto/msm/qce40.c
+++ b/drivers/crypto/msm/qce40.c
@@ -25,6 +25,7 @@
#include <linux/delay.h>
#include <linux/crypto.h>
#include <linux/qcedev.h>
+#include <linux/bitops.h>
#include <crypto/hash.h>
#include <crypto/sha.h>
#include <mach/dma.h>
@@ -168,23 +169,24 @@
return 0;
};
-#ifdef CONFIG_ARCH_MSM9615
static void config_ce_engine(struct qce_device *pce_dev)
{
unsigned int val = 0;
+ unsigned int ret = 0;
- val = (1 << CRYPTO_MASK_DOUT_INTR) | (1 << CRYPTO_MASK_DIN_INTR) |
- (1 << CRYPTO_MASK_OP_DONE_INTR) |
- (1 << CRYPTO_MASK_ERR_INTR);
+ /* Crypto config register returns a 0 when it is XPU protected. */
+ ret = readl_relaxed(pce_dev->iobase + CRYPTO_CONFIG_REG);
- writel_relaxed(val, pce_dev->iobase + CRYPTO_CONFIG_REG);
+ /* Configure the crypto register if it is not XPU protected. */
+ if (ret) {
+ val = BIT(CRYPTO_MASK_DOUT_INTR) |
+ BIT(CRYPTO_MASK_DIN_INTR) |
+ BIT(CRYPTO_MASK_OP_DONE_INTR) |
+ BIT(CRYPTO_MASK_ERR_INTR);
+
+ writel_relaxed(val, pce_dev->iobase + CRYPTO_CONFIG_REG);
+ }
}
-#else
-static void config_ce_engine(struct qce_device *pce_dev)
-{
-
-}
-#endif
static void _check_probe_done_call_back(struct msm_dmov_cmd *cmd_ptr,
unsigned int result, struct msm_dmov_errdata *err)
@@ -2569,4 +2571,4 @@
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Mona Hossain <mhossain@codeaurora.org>");
MODULE_DESCRIPTION("Crypto Engine driver");
-MODULE_VERSION("2.12");
+MODULE_VERSION("2.13");
diff --git a/drivers/crypto/msm/qcedev.c b/drivers/crypto/msm/qcedev.c
index 405d021..3ae1647 100644
--- a/drivers/crypto/msm/qcedev.c
+++ b/drivers/crypto/msm/qcedev.c
@@ -439,7 +439,7 @@
creq.alg = CIPHER_ALG_AES;
break;
default:
- break;
+ return -EINVAL;
};
switch (qcedev_areq->cipher_op_req.mode) {
@@ -458,7 +458,7 @@
creq.mode = QCE_MODE_XTS;
break;
default:
- break;
+ return -EINVAL;
};
if ((creq.alg == CIPHER_ALG_AES) &&
diff --git a/drivers/crypto/msm/qcrypto.c b/drivers/crypto/msm/qcrypto.c
index 73627d4..67301877 100644
--- a/drivers/crypto/msm/qcrypto.c
+++ b/drivers/crypto/msm/qcrypto.c
@@ -889,6 +889,9 @@
if (areq->assoclen)
qreq->nonce[0] |= 64;
+ if (i > MAX_NONCE)
+ return -EINVAL;
+
return aead_ccm_set_msg_len(qreq->nonce + 16 - i, qreq->cryptlen, i);
}
diff --git a/drivers/gpio/pm8xxx-gpio.c b/drivers/gpio/pm8xxx-gpio.c
index 026fd05..377510f 100644
--- a/drivers/gpio/pm8xxx-gpio.c
+++ b/drivers/gpio/pm8xxx-gpio.c
@@ -289,7 +289,8 @@
GFP_KERNEL);
if (!pm_gpio_chip->bank1) {
pr_err("Cannot allocate pm_gpio_chip->bank1\n");
- return -ENOMEM;
+ ret = -ENOMEM;
+ goto free_chip;
}
spin_lock_init(&pm_gpio_chip->pm_lock);
@@ -332,6 +333,8 @@
pr_err("failed to remove gpio chip\n");
reset_drvdata:
platform_set_drvdata(pdev, NULL);
+ kfree(pm_gpio_chip->bank1);
+free_chip:
kfree(pm_gpio_chip);
return ret;
}
diff --git a/drivers/gpu/ion/ion.c b/drivers/gpu/ion/ion.c
index c37d952..60bc276 100644
--- a/drivers/gpu/ion/ion.c
+++ b/drivers/gpu/ion/ion.c
@@ -204,6 +204,7 @@
/* XXX Can a handle be destroyed while it's map count is non-zero?:
if (handle->map_cnt) unmap
*/
+ WARN_ON(handle->kmap_cnt || handle->dmap_cnt || handle->usermap_cnt);
ion_buffer_put(handle->buffer);
mutex_lock(&handle->client->lock);
if (!RB_EMPTY_NODE(&handle->node))
@@ -673,8 +674,8 @@
return ERR_PTR(-EINVAL);
}
if (file->f_op != &ion_share_fops) {
- pr_err("%s: imported file is not a shared ion file.\n",
- __func__);
+ pr_err("%s: imported file %s is not a shared ion"
+ " file.", __func__, file->f_dentry->d_name.name);
handle = ERR_PTR(-EINVAL);
goto end;
}
@@ -688,29 +689,25 @@
{
struct ion_client *client = s->private;
struct rb_node *n;
- size_t sizes[ION_NUM_HEAPS] = {0};
- const char *names[ION_NUM_HEAPS] = {0};
- int i;
+ seq_printf(s, "%16.16s: %16.16s : %16.16s : %16.16s\n", "heap_name",
+ "size_in_bytes", "handle refcount", "buffer");
mutex_lock(&client->lock);
for (n = rb_first(&client->handles); n; n = rb_next(n)) {
struct ion_handle *handle = rb_entry(n, struct ion_handle,
node);
- enum ion_heap_type type = handle->buffer->heap->type;
- if (!names[type])
- names[type] = handle->buffer->heap->name;
- sizes[type] += handle->buffer->size;
+ seq_printf(s, "%16.16s: %16x : %16d : %16p\n",
+ handle->buffer->heap->name,
+ handle->buffer->size,
+ atomic_read(&handle->ref.refcount),
+ handle->buffer);
}
+
+ seq_printf(s, "%16.16s %d\n", "client refcount:",
+ atomic_read(&client->ref.refcount));
mutex_unlock(&client->lock);
- seq_printf(s, "%16.16s: %16.16s\n", "heap_name", "size_in_bytes");
- for (i = 0; i < ION_NUM_HEAPS; i++) {
- if (!names[i])
- continue;
- seq_printf(s, "%16.16s: %16u %d\n", names[i], sizes[i],
- atomic_read(&client->ref.refcount));
- }
return 0;
}
@@ -874,9 +871,32 @@
void ion_client_destroy(struct ion_client *client)
{
- ion_client_put(client);
+ if (client)
+ ion_client_put(client);
}
+int ion_handle_get_flags(struct ion_client *client, struct ion_handle *handle,
+ unsigned long *flags)
+{
+ struct ion_buffer *buffer;
+
+ mutex_lock(&client->lock);
+ if (!ion_handle_validate(client, handle)) {
+ pr_err("%s: invalid handle passed to %s.\n",
+ __func__, __func__);
+ mutex_unlock(&client->lock);
+ return -EINVAL;
+ }
+ buffer = handle->buffer;
+ mutex_lock(&buffer->lock);
+ *flags = buffer->flags;
+ mutex_unlock(&buffer->lock);
+ mutex_unlock(&client->lock);
+
+ return 0;
+}
+EXPORT_SYMBOL(ion_handle_get_flags);
+
static int ion_share_release(struct inode *inode, struct file* file)
{
struct ion_buffer *buffer = file->private_data;
@@ -1163,6 +1183,22 @@
data.offset, data.length, cmd);
}
+ case ION_IOC_GET_FLAGS:
+ {
+ struct ion_flag_data data;
+ int ret;
+ if (copy_from_user(&data, (void __user *)arg,
+ sizeof(struct ion_flag_data)))
+ return -EFAULT;
+
+ ret = ion_handle_get_flags(client, data.handle, &data.flags);
+ if (ret < 0)
+ return ret;
+ if (copy_to_user((void __user *)arg, &data,
+ sizeof(struct ion_flag_data)))
+ return -EFAULT;
+ break;
+ }
default:
return -ENOTTY;
}
@@ -1201,7 +1237,7 @@
};
static size_t ion_debug_heap_total(struct ion_client *client,
- enum ion_heap_type type)
+ enum ion_heap_ids id)
{
size_t size = 0;
struct rb_node *n;
@@ -1211,7 +1247,7 @@
struct ion_handle *handle = rb_entry(n,
struct ion_handle,
node);
- if (handle->buffer->heap->type == type)
+ if (handle->buffer->heap->id == id)
size += handle->buffer->size;
}
mutex_unlock(&client->lock);
@@ -1229,24 +1265,32 @@
struct ion_client *client = rb_entry(n, struct ion_client,
node);
char task_comm[TASK_COMM_LEN];
- size_t size = ion_debug_heap_total(client, heap->type);
+ size_t size = ion_debug_heap_total(client, heap->id);
if (!size)
continue;
get_task_comm(task_comm, client->task);
- seq_printf(s, "%16.s %16u %16u\n", task_comm, client->pid,
+ seq_printf(s, "%16.s %16u %16x\n", task_comm, client->pid,
size);
}
for (n = rb_first(&dev->kernel_clients); n; n = rb_next(n)) {
struct ion_client *client = rb_entry(n, struct ion_client,
node);
- size_t size = ion_debug_heap_total(client, heap->type);
+ size_t size = ion_debug_heap_total(client, heap->id);
if (!size)
continue;
- seq_printf(s, "%16.s %16u %16u\n", client->name, client->pid,
+ seq_printf(s, "%16.s %16u %16x\n", client->name, client->pid,
size);
}
+ if (heap->ops->get_allocated) {
+ seq_printf(s, "total bytes currently allocated: %lx\n",
+ heap->ops->get_allocated(heap));
+ }
+ if (heap->ops->get_total) {
+ seq_printf(s, "total heap size: %lx\n",
+ heap->ops->get_total(heap));
+ }
return 0;
}
@@ -1293,6 +1337,83 @@
mutex_unlock(&dev->lock);
}
+static int ion_debug_leak_show(struct seq_file *s, void *unused)
+{
+ struct ion_device *dev = s->private;
+ struct rb_node *n;
+ struct rb_node *n2;
+
+ /* mark all buffers as 1 */
+ seq_printf(s, "%16.s %16.s %16.s %16.s\n", "buffer", "heap", "size",
+ "ref cnt");
+ mutex_lock(&dev->lock);
+ for (n = rb_first(&dev->buffers); n; n = rb_next(n)) {
+ struct ion_buffer *buf = rb_entry(n, struct ion_buffer,
+ node);
+
+ buf->marked = 1;
+ }
+
+ /* now see which buffers we can access */
+ for (n = rb_first(&dev->kernel_clients); n; n = rb_next(n)) {
+ struct ion_client *client = rb_entry(n, struct ion_client,
+ node);
+
+ mutex_lock(&client->lock);
+ for (n2 = rb_first(&client->handles); n2; n2 = rb_next(n2)) {
+ struct ion_handle *handle = rb_entry(n2,
+ struct ion_handle, node);
+
+ handle->buffer->marked = 0;
+
+ }
+ mutex_unlock(&client->lock);
+
+ }
+
+ for (n = rb_first(&dev->user_clients); n; n = rb_next(n)) {
+ struct ion_client *client = rb_entry(n, struct ion_client,
+ node);
+
+ mutex_lock(&client->lock);
+ for (n2 = rb_first(&client->handles); n2; n2 = rb_next(n2)) {
+ struct ion_handle *handle = rb_entry(n2,
+ struct ion_handle, node);
+
+ handle->buffer->marked = 0;
+
+ }
+ mutex_unlock(&client->lock);
+
+ }
+ /* And anyone still marked as a 1 means a leaked handle somewhere */
+ for (n = rb_first(&dev->buffers); n; n = rb_next(n)) {
+ struct ion_buffer *buf = rb_entry(n, struct ion_buffer,
+ node);
+
+ if (buf->marked == 1)
+ seq_printf(s, "%16.x %16.s %16.x %16.d\n",
+ (int)buf, buf->heap->name, buf->size,
+ atomic_read(&buf->ref.refcount));
+ }
+ mutex_unlock(&dev->lock);
+ return 0;
+}
+
+static int ion_debug_leak_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, ion_debug_leak_show, inode->i_private);
+}
+
+static const struct file_operations debug_leak_fops = {
+ .open = ion_debug_leak_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+};
+
+
+
struct ion_device *ion_device_create(long (*custom_ioctl)
(struct ion_client *client,
unsigned int cmd,
@@ -1325,6 +1446,8 @@
idev->heaps = RB_ROOT;
idev->user_clients = RB_ROOT;
idev->kernel_clients = RB_ROOT;
+ debugfs_create_file("check_leaked_fds", 0664, idev->debug_root, idev,
+ &debug_leak_fops);
return idev;
}
diff --git a/drivers/gpu/ion/ion_carveout_heap.c b/drivers/gpu/ion/ion_carveout_heap.c
index 86d4c8e..71dea89 100644
--- a/drivers/gpu/ion/ion_carveout_heap.c
+++ b/drivers/gpu/ion/ion_carveout_heap.c
@@ -31,6 +31,8 @@
struct ion_heap heap;
struct gen_pool *pool;
ion_phys_addr_t base;
+ unsigned long allocated_bytes;
+ unsigned long total_size;
};
ion_phys_addr_t ion_carveout_allocate(struct ion_heap *heap,
@@ -42,9 +44,19 @@
unsigned long offset = gen_pool_alloc_aligned(carveout_heap->pool,
size, ilog2(align));
- if (!offset)
+ if (!offset) {
+ if ((carveout_heap->total_size -
+ carveout_heap->allocated_bytes) > size)
+ pr_debug("%s: heap %s has enough memory (%lx) but"
+ " the allocation of size %lx still failed."
+ " Memory is probably fragmented.",
+ __func__, heap->name,
+ carveout_heap->total_size -
+ carveout_heap->allocated_bytes, size);
return ION_CARVEOUT_ALLOCATE_FAIL;
+ }
+ carveout_heap->allocated_bytes += size;
return offset;
}
@@ -57,6 +69,7 @@
if (addr == ION_CARVEOUT_ALLOCATE_FAIL)
return;
gen_pool_free(carveout_heap->pool, addr, size);
+ carveout_heap->allocated_bytes -= size;
}
static int ion_carveout_heap_phys(struct ion_heap *heap,
@@ -88,13 +101,27 @@
struct scatterlist *ion_carveout_heap_map_dma(struct ion_heap *heap,
struct ion_buffer *buffer)
{
- return ERR_PTR(-EINVAL);
+ struct scatterlist *sglist;
+ struct page *page = phys_to_page(buffer->priv_phys);
+
+ if (page == NULL)
+ return NULL;
+
+ sglist = vmalloc(sizeof(struct scatterlist));
+ if (!sglist)
+ return ERR_PTR(-ENOMEM);
+
+ sg_init_table(sglist, 1);
+ sg_set_page(sglist, page, buffer->size, 0);
+
+ return sglist;
}
void ion_carveout_heap_unmap_dma(struct ion_heap *heap,
struct ion_buffer *buffer)
{
- return;
+ if (buffer->sglist)
+ vfree(buffer->sglist);
}
void *ion_carveout_heap_map_kernel(struct ion_heap *heap,
@@ -156,6 +183,22 @@
return 0;
}
+static unsigned long ion_carveout_get_allocated(struct ion_heap *heap)
+{
+ struct ion_carveout_heap *carveout_heap =
+ container_of(heap, struct ion_carveout_heap, heap);
+
+ return carveout_heap->allocated_bytes;
+}
+
+static unsigned long ion_carveout_get_total(struct ion_heap *heap)
+{
+ struct ion_carveout_heap *carveout_heap =
+ container_of(heap, struct ion_carveout_heap, heap);
+
+ return carveout_heap->total_size;
+}
+
static struct ion_heap_ops carveout_heap_ops = {
.allocate = ion_carveout_heap_allocate,
.free = ion_carveout_heap_free,
@@ -163,7 +206,11 @@
.map_user = ion_carveout_heap_map_user,
.map_kernel = ion_carveout_heap_map_kernel,
.unmap_kernel = ion_carveout_heap_unmap_kernel,
+ .map_dma = ion_carveout_heap_map_dma,
+ .unmap_dma = ion_carveout_heap_unmap_dma,
.cache_op = ion_carveout_cache_ops,
+ .get_allocated = ion_carveout_get_allocated,
+ .get_total = ion_carveout_get_total,
};
struct ion_heap *ion_carveout_heap_create(struct ion_platform_heap *heap_data)
@@ -189,6 +236,8 @@
}
carveout_heap->heap.ops = &carveout_heap_ops;
carveout_heap->heap.type = ION_HEAP_TYPE_CARVEOUT;
+ carveout_heap->allocated_bytes = 0;
+ carveout_heap->total_size = heap_data->size;
return &carveout_heap->heap;
}
diff --git a/drivers/gpu/ion/ion_priv.h b/drivers/gpu/ion/ion_priv.h
index fd5c125..888b599 100644
--- a/drivers/gpu/ion/ion_priv.h
+++ b/drivers/gpu/ion/ion_priv.h
@@ -72,6 +72,7 @@
int dmap_cnt;
struct scatterlist *sglist;
int umap_cnt;
+ int marked;
};
/**
@@ -104,6 +105,8 @@
int (*cache_op)(struct ion_heap *heap, struct ion_buffer *buffer,
void *vaddr, unsigned int offset,
unsigned int length, unsigned int cmd);
+ unsigned long (*get_allocated)(struct ion_heap *heap);
+ unsigned long (*get_total)(struct ion_heap *heap);
};
/**
diff --git a/drivers/gpu/ion/ion_system_heap.c b/drivers/gpu/ion/ion_system_heap.c
index 5609b72..b26d48c 100644
--- a/drivers/gpu/ion/ion_system_heap.c
+++ b/drivers/gpu/ion/ion_system_heap.c
@@ -23,6 +23,9 @@
#include "ion_priv.h"
#include <mach/memory.h>
+static atomic_t system_heap_allocated;
+static atomic_t system_contig_heap_allocated;
+
static int ion_system_heap_allocate(struct ion_heap *heap,
struct ion_buffer *buffer,
unsigned long size, unsigned long align,
@@ -31,12 +34,15 @@
buffer->priv_virt = vmalloc_user(size);
if (!buffer->priv_virt)
return -ENOMEM;
+
+ atomic_add(size, &system_heap_allocated);
return 0;
}
void ion_system_heap_free(struct ion_buffer *buffer)
{
vfree(buffer->priv_virt);
+ atomic_sub(buffer->size, &system_heap_allocated);
}
struct scatterlist *ion_system_heap_map_dma(struct ion_heap *heap,
@@ -149,6 +155,11 @@
return 0;
}
+static unsigned long ion_system_heap_get_allocated(struct ion_heap *heap)
+{
+ return atomic_read(&system_heap_allocated);
+}
+
static struct ion_heap_ops vmalloc_ops = {
.allocate = ion_system_heap_allocate,
.free = ion_system_heap_free,
@@ -158,6 +169,7 @@
.unmap_kernel = ion_system_heap_unmap_kernel,
.map_user = ion_system_heap_map_user,
.cache_op = ion_system_heap_cache_ops,
+ .get_allocated = ion_system_heap_get_allocated,
};
struct ion_heap *ion_system_heap_create(struct ion_platform_heap *unused)
@@ -186,12 +198,14 @@
buffer->priv_virt = kzalloc(len, GFP_KERNEL);
if (!buffer->priv_virt)
return -ENOMEM;
+ atomic_add(len, &system_contig_heap_allocated);
return 0;
}
void ion_system_contig_heap_free(struct ion_buffer *buffer)
{
kfree(buffer->priv_virt);
+ atomic_sub(buffer->size, &system_contig_heap_allocated);
}
static int ion_system_contig_heap_phys(struct ion_heap *heap,
@@ -266,6 +280,11 @@
return 0;
}
+static unsigned long ion_system_contig_heap_get_allocated(struct ion_heap *heap)
+{
+ return atomic_read(&system_contig_heap_allocated);
+}
+
static struct ion_heap_ops kmalloc_ops = {
.allocate = ion_system_contig_heap_allocate,
.free = ion_system_contig_heap_free,
@@ -276,6 +295,7 @@
.unmap_kernel = ion_system_heap_unmap_kernel,
.map_user = ion_system_contig_heap_map_user,
.cache_op = ion_system_contig_heap_cache_ops,
+ .get_allocated = ion_system_contig_heap_get_allocated,
};
struct ion_heap *ion_system_contig_heap_create(struct ion_platform_heap *unused)
diff --git a/drivers/gpu/ion/msm/msm_ion.c b/drivers/gpu/ion/msm/msm_ion.c
index 8b45b3a..54dd056 100644
--- a/drivers/gpu/ion/msm/msm_ion.c
+++ b/drivers/gpu/ion/msm/msm_ion.c
@@ -19,9 +19,9 @@
#include <mach/msm_memtypes.h>
#include "../ion_priv.h"
-struct ion_device *idev;
-int num_heaps;
-struct ion_heap **heaps;
+static struct ion_device *idev;
+static int num_heaps;
+static struct ion_heap **heaps;
struct ion_client *msm_ion_client_create(unsigned int heap_mask,
const char *name)
@@ -83,19 +83,17 @@
heaps[i] = ion_heap_create(heap_data);
if (IS_ERR_OR_NULL(heaps[i])) {
- err = PTR_ERR(heaps[i]);
- goto heapdestroy;
+ pr_err("%s: could not create ion heap %s"
+ " (id %x)\n", __func__, heap_data->name,
+ heap_data->id);
+ heaps[i] = 0;
+ continue;
}
ion_device_add_heap(idev, heaps[i]);
}
platform_set_drvdata(pdev, idev);
return 0;
-heapdestroy:
- for (i = 0; i < num_heaps; i++) {
- if (!IS_ERR_OR_NULL(heaps[i]))
- ion_heap_destroy(heaps[i]);
- }
freeheaps:
kfree(heaps);
out:
diff --git a/drivers/gpu/msm/adreno.c b/drivers/gpu/msm/adreno.c
index 4207def..7599894 100644
--- a/drivers/gpu/msm/adreno.c
+++ b/drivers/gpu/msm/adreno.c
@@ -359,7 +359,7 @@
* adreno 22x gpus are indicated by coreid 2,
* but REG_RBBM_PERIPHID1 always contains 0 for this field
*/
- if (cpu_is_msm8960() || cpu_is_msm8x60())
+ if (cpu_is_msm8960() || cpu_is_msm8x60() || cpu_is_msm8930())
chipid = 2 << 24;
else
chipid = (coreid & 0xF) << 24;
@@ -536,7 +536,7 @@
adreno_regwrite(device, REG_SQ_VS_PROGRAM, 0x00000000);
adreno_regwrite(device, REG_SQ_PS_PROGRAM, 0x00000000);
- if (cpu_is_msm8960())
+ if (cpu_is_msm8960() || cpu_is_msm8930())
adreno_regwrite(device, REG_RBBM_PM_OVERRIDE1, 0x200);
else
adreno_regwrite(device, REG_RBBM_PM_OVERRIDE1, 0);
diff --git a/drivers/gpu/msm/kgsl.c b/drivers/gpu/msm/kgsl.c
index 7e61a32..c6fceaa 100644
--- a/drivers/gpu/msm/kgsl.c
+++ b/drivers/gpu/msm/kgsl.c
@@ -23,6 +23,7 @@
#include <linux/ashmem.h>
#include <linux/major.h>
+#include <linux/ion.h>
#include "kgsl.h"
#include "kgsl_debugfs.h"
@@ -43,6 +44,8 @@
MODULE_PARM_DESC(ksgl_mmu_type,
"Type of MMU to be used for graphics. Valid values are 'iommu' or 'gpummu' or 'nommu'");
+static struct ion_client *kgsl_ion_client;
+
static inline struct kgsl_mem_entry *
kgsl_mem_entry_create(void)
{
@@ -62,18 +65,34 @@
struct kgsl_mem_entry *entry = container_of(kref,
struct kgsl_mem_entry,
refcount);
- size_t size = entry->memdesc.size;
+
+ entry->priv->stats[entry->memtype].cur -= entry->memdesc.size;
+
+ if (entry->memtype != KGSL_MEM_ENTRY_KERNEL)
+ kgsl_driver.stats.mapped -= entry->memdesc.size;
+
+ /*
+ * Ion takes care of freeing the sglist for us (how nice </sarcasm>) so
+ * unmap the dma before freeing the sharedmem so kgsl_sharedmem_free
+ * doesn't try to free it again
+ */
+
+ if (entry->memtype == KGSL_MEM_ENTRY_ION) {
+ ion_unmap_dma(kgsl_ion_client, entry->priv_data);
+ entry->memdesc.sg = NULL;
+ }
kgsl_sharedmem_free(&entry->memdesc);
- if (entry->memtype == KGSL_USER_MEMORY)
- entry->priv->stats.user -= size;
- else if (entry->memtype == KGSL_MAPPED_MEMORY) {
- if (entry->file_ptr)
- fput(entry->file_ptr);
-
- kgsl_driver.stats.mapped -= size;
- entry->priv->stats.mapped -= size;
+ switch (entry->memtype) {
+ case KGSL_MEM_ENTRY_PMEM:
+ case KGSL_MEM_ENTRY_ASHMEM:
+ if (entry->priv_data)
+ fput(entry->priv_data);
+ break;
+ case KGSL_MEM_ENTRY_ION:
+ ion_free(kgsl_ion_client, entry->priv_data);
+ break;
}
kfree(entry);
@@ -513,11 +532,6 @@
if (--private->refcnt)
goto unlock;
- KGSL_MEM_INFO(device,
- "Memory usage: user (%d/%d) mapped (%d/%d)\n",
- private->stats.user, private->stats.user_max,
- private->stats.mapped, private->stats.mapped_max);
-
kgsl_process_uninit_sysfs(private);
list_del(&private->list);
@@ -1113,13 +1127,12 @@
param->gpuaddr = entry->memdesc.gpuaddr;
- entry->memtype = KGSL_USER_MEMORY;
+ entry->memtype = KGSL_MEM_ENTRY_KERNEL;
kgsl_mem_entry_attach_process(entry, private);
/* Process specific statistics */
- KGSL_STATS_ADD(len, private->stats.user,
- private->stats.user_max);
+ kgsl_process_add_stats(private, entry->memtype, len);
kgsl_check_idle(dev_priv->device);
return 0;
@@ -1220,7 +1233,7 @@
}
- entry->file_ptr = filep;
+ entry->priv_data = filep;
entry->memdesc.pagetable = pagetable;
entry->memdesc.size = size;
@@ -1392,7 +1405,7 @@
goto err;
}
- entry->file_ptr = filep;
+ entry->priv_data = filep;
entry->memdesc.pagetable = pagetable;
entry->memdesc.size = ALIGN(size, PAGE_SIZE);
entry->memdesc.hostptr = hostptr;
@@ -1416,6 +1429,51 @@
}
#endif
+static int kgsl_setup_ion(struct kgsl_mem_entry *entry,
+ struct kgsl_pagetable *pagetable, int fd)
+{
+ struct ion_handle *handle;
+ struct scatterlist *s;
+ unsigned long flags;
+
+ if (kgsl_ion_client == NULL) {
+ kgsl_ion_client = msm_ion_client_create(UINT_MAX, KGSL_NAME);
+ if (kgsl_ion_client == NULL)
+ return -ENODEV;
+ }
+
+ handle = ion_import_fd(kgsl_ion_client, fd);
+ if (IS_ERR_OR_NULL(handle))
+ return PTR_ERR(handle);
+
+ entry->memtype = KGSL_MEM_ENTRY_ION;
+ entry->priv_data = handle;
+ entry->memdesc.pagetable = pagetable;
+ entry->memdesc.size = 0;
+
+ if (ion_handle_get_flags(kgsl_ion_client, handle, &flags))
+ goto err;
+
+ entry->memdesc.sg = ion_map_dma(kgsl_ion_client, handle, flags);
+
+ if (IS_ERR_OR_NULL(entry->memdesc.sg))
+ goto err;
+
+ /* Calculate the size of the memdesc from the sglist */
+
+ entry->memdesc.sglen = 0;
+
+ for (s = entry->memdesc.sg; s != NULL; s = sg_next(s)) {
+ entry->memdesc.size += s->length;
+ entry->memdesc.sglen++;
+ }
+
+ return 0;
+err:
+ ion_free(kgsl_ion_client, handle);
+ return -ENOMEM;
+}
+
static long kgsl_ioctl_map_user_mem(struct kgsl_device_private *dev_priv,
unsigned int cmd, void *data)
{
@@ -1443,6 +1501,7 @@
result = kgsl_setup_phys_file(entry, private->pagetable,
param->fd, param->offset,
param->len);
+ entry->memtype = KGSL_MEM_ENTRY_PMEM;
break;
case KGSL_USER_MEM_TYPE_ADDR:
@@ -1459,6 +1518,7 @@
result = kgsl_setup_hostptr(entry, private->pagetable,
(void *) param->hostptr,
param->offset, param->len);
+ entry->memtype = KGSL_MEM_ENTRY_USER;
break;
case KGSL_USER_MEM_TYPE_ASHMEM:
@@ -1475,6 +1535,12 @@
result = kgsl_setup_ashmem(entry, private->pagetable,
param->fd, (void *) param->hostptr,
param->len);
+
+ entry->memtype = KGSL_MEM_ENTRY_ASHMEM;
+ break;
+ case KGSL_USER_MEM_TYPE_ION:
+ result = kgsl_setup_ion(entry, private->pagetable,
+ param->fd);
break;
default:
KGSL_CORE_ERR("Invalid memory type: %x\n", memtype);
@@ -1494,14 +1560,10 @@
/* Adjust the returned value for a non 4k aligned offset */
param->gpuaddr = entry->memdesc.gpuaddr + (param->offset & ~PAGE_MASK);
- entry->memtype = KGSL_MAPPED_MEMORY;
-
KGSL_STATS_ADD(param->len, kgsl_driver.stats.mapped,
- kgsl_driver.stats.mapped_max);
+ kgsl_driver.stats.mapped_max);
- /* Statistics */
- KGSL_STATS_ADD(param->len, private->stats.mapped,
- private->stats.mapped_max);
+ kgsl_process_add_stats(private, entry->memtype, param->len);
kgsl_mem_entry_attach_process(entry, private);
@@ -1509,8 +1571,8 @@
return result;
error_put_file_ptr:
- if (entry->file_ptr)
- fput(entry->file_ptr);
+ if (entry->priv_data)
+ fput(entry->priv_data);
error:
kfree(entry);
@@ -1548,9 +1610,6 @@
}
kgsl_cache_range_op(&entry->memdesc, KGSL_CACHE_OP_CLEAN);
-
- /* Statistics - keep track of how many flushes each process does */
- private->stats.flushes++;
done:
spin_unlock(&private->mem_lock);
return result;
@@ -1573,12 +1632,11 @@
param->size, param->flags);
if (result == 0) {
- entry->memtype = KGSL_USER_MEMORY;
+ entry->memtype = KGSL_MEM_ENTRY_KERNEL;
kgsl_mem_entry_attach_process(entry, private);
param->gpuaddr = entry->memdesc.gpuaddr;
- KGSL_STATS_ADD(entry->memdesc.size, private->stats.user,
- private->stats.user_max);
+ kgsl_process_add_stats(private, entry->memtype, param->size);
} else
kfree(entry);
diff --git a/drivers/gpu/msm/kgsl.h b/drivers/gpu/msm/kgsl.h
index 1480df4..b5c24f0 100644
--- a/drivers/gpu/msm/kgsl.h
+++ b/drivers/gpu/msm/kgsl.h
@@ -101,9 +101,6 @@
extern struct kgsl_driver kgsl_driver;
-#define KGSL_USER_MEMORY 1
-#define KGSL_MAPPED_MEMORY 2
-
struct kgsl_pagetable;
struct kgsl_memdesc_ops;
@@ -120,11 +117,20 @@
struct kgsl_memdesc_ops *ops;
};
+/* List of different memory entry types */
+
+#define KGSL_MEM_ENTRY_KERNEL 0
+#define KGSL_MEM_ENTRY_PMEM 1
+#define KGSL_MEM_ENTRY_ASHMEM 2
+#define KGSL_MEM_ENTRY_USER 3
+#define KGSL_MEM_ENTRY_ION 4
+#define KGSL_MEM_ENTRY_MAX 5
+
struct kgsl_mem_entry {
struct kref refcount;
struct kgsl_memdesc memdesc;
int memtype;
- struct file *file_ptr;
+ void *priv_data;
struct list_head list;
uint32_t free_timestamp;
/* back pointer to private structure under whose context this
diff --git a/drivers/gpu/msm/kgsl_cffdump.c b/drivers/gpu/msm/kgsl_cffdump.c
index d419592..aa33152 100644
--- a/drivers/gpu/msm/kgsl_cffdump.c
+++ b/drivers/gpu/msm/kgsl_cffdump.c
@@ -363,7 +363,7 @@
/*TODO: move this to where we can report correct gmemsize*/
unsigned int va_base;
- if (cpu_is_msm8x60() || cpu_is_msm8960())
+ if (cpu_is_msm8x60() || cpu_is_msm8960() || cpu_is_msm8930())
va_base = 0x40000000;
else
va_base = 0x20000000;
diff --git a/drivers/gpu/msm/kgsl_device.h b/drivers/gpu/msm/kgsl_device.h
index 2f369ed..e261b84 100644
--- a/drivers/gpu/msm/kgsl_device.h
+++ b/drivers/gpu/msm/kgsl_device.h
@@ -185,15 +185,12 @@
struct list_head mem_list;
struct kgsl_pagetable *pagetable;
struct list_head list;
- struct kobject *kobj;
+ struct kobject kobj;
struct {
- unsigned int user;
- unsigned int user_max;
- unsigned int mapped;
- unsigned int mapped_max;
- unsigned int flushes;
- } stats;
+ unsigned int cur;
+ unsigned int max;
+ } stats[KGSL_MEM_ENTRY_MAX];
};
struct kgsl_device_private {
@@ -208,6 +205,14 @@
struct kgsl_device *kgsl_get_device(int dev_idx);
+static inline void kgsl_process_add_stats(struct kgsl_process_private *priv,
+ unsigned int type, size_t size)
+{
+ priv->stats[type].cur += size;
+ if (priv->stats[type].max < priv->stats[type].cur)
+ priv->stats[type].max = priv->stats[type].cur;
+}
+
static inline void kgsl_regread(struct kgsl_device *device,
unsigned int offsetwords,
unsigned int *value)
diff --git a/drivers/gpu/msm/kgsl_pwrctrl.c b/drivers/gpu/msm/kgsl_pwrctrl.c
index 84f2b33..343a39a 100644
--- a/drivers/gpu/msm/kgsl_pwrctrl.c
+++ b/drivers/gpu/msm/kgsl_pwrctrl.c
@@ -582,11 +582,10 @@
idle_check_ws);
mutex_lock(&device->mutex);
- if (device->ftbl->isidle(device) &&
- (device->requested_state != KGSL_STATE_SLEEP))
- kgsl_pwrscale_idle(device);
-
if (device->state & (KGSL_STATE_ACTIVE | KGSL_STATE_NAP)) {
+ if (device->requested_state != KGSL_STATE_SLEEP)
+ kgsl_pwrscale_idle(device);
+
if (kgsl_pwrctrl_sleep(device) != 0) {
mod_timer(&device->idle_timer,
jiffies +
diff --git a/drivers/gpu/msm/kgsl_pwrscale_trustzone.c b/drivers/gpu/msm/kgsl_pwrscale_trustzone.c
index 45f7607..f3e84e4 100644
--- a/drivers/gpu/msm/kgsl_pwrscale_trustzone.c
+++ b/drivers/gpu/msm/kgsl_pwrscale_trustzone.c
@@ -166,7 +166,7 @@
struct tz_priv *priv;
/* Trustzone is only valid for some SOCs */
- if (!(cpu_is_msm8x60() || cpu_is_msm8960()))
+ if (!(cpu_is_msm8x60() || cpu_is_msm8960() || cpu_is_msm8930()))
return -EINVAL;
priv = pwrscale->priv = kzalloc(sizeof(struct tz_priv), GFP_KERNEL);
diff --git a/drivers/gpu/msm/kgsl_sharedmem.c b/drivers/gpu/msm/kgsl_sharedmem.c
index 8f75daa..b59761d 100644
--- a/drivers/gpu/msm/kgsl_sharedmem.c
+++ b/drivers/gpu/msm/kgsl_sharedmem.c
@@ -19,6 +19,52 @@
#include "kgsl_cffdump.h"
#include "kgsl_device.h"
+/* An attribute for showing per-process memory statistics */
+struct kgsl_mem_entry_attribute {
+ struct attribute attr;
+ int memtype;
+ ssize_t (*show)(struct kgsl_process_private *priv,
+ int type, char *buf);
+};
+
+#define to_mem_entry_attr(a) \
+container_of(a, struct kgsl_mem_entry_attribute, attr)
+
+#define __MEM_ENTRY_ATTR(_type, _name, _show) \
+{ \
+ .attr = { .name = __stringify(_name), .mode = 0444 }, \
+ .memtype = _type, \
+ .show = _show, \
+}
+
+/*
+ * A structure to hold the attributes for a particular memory type.
+ * For each memory type in each process we store the current and maximum
+ * memory usage and display the counts in sysfs. This structure and
+ * the following macro allow us to simplify the definition for those
+ * adding new memory types
+ */
+
+struct mem_entry_stats {
+ int memtype;
+ struct kgsl_mem_entry_attribute attr;
+ struct kgsl_mem_entry_attribute max_attr;
+};
+
+
+#define MEM_ENTRY_STAT(_type, _name) \
+{ \
+ .memtype = _type, \
+ .attr = __MEM_ENTRY_ATTR(_type, _name, mem_entry_show), \
+ .max_attr = __MEM_ENTRY_ATTR(_type, _name##_max, \
+ mem_entry_max_show), \
+}
+
+
+/**
+ * Given a kobj, find the process structure attached to it
+ */
+
static struct kgsl_process_private *
_get_priv_from_kobj(struct kobject *kobj)
{
@@ -39,87 +85,109 @@
return NULL;
}
-/* sharedmem / memory sysfs files */
+/**
+ * Show the current amount of memory allocated for the given memtype
+ */
static ssize_t
-process_show(struct kobject *kobj,
- struct kobj_attribute *attr,
- char *buf)
+mem_entry_show(struct kgsl_process_private *priv, int type, char *buf)
{
+ return snprintf(buf, PAGE_SIZE, "%d\n", priv->stats[type].cur);
+}
+
+/**
+ * Show the maximum memory allocated for the given memtype through the life of
+ * the process
+ */
+
+static ssize_t
+mem_entry_max_show(struct kgsl_process_private *priv, int type, char *buf)
+{
+ return snprintf(buf, PAGE_SIZE, "%d\n", priv->stats[type].max);
+}
+
+
+static void mem_entry_sysfs_release(struct kobject *kobj)
+{
+}
+
+static ssize_t mem_entry_sysfs_show(struct kobject *kobj,
+ struct attribute *attr, char *buf)
+{
+ struct kgsl_mem_entry_attribute *pattr = to_mem_entry_attr(attr);
struct kgsl_process_private *priv;
- unsigned int val = 0;
+ ssize_t ret;
mutex_lock(&kgsl_driver.process_mutex);
priv = _get_priv_from_kobj(kobj);
- if (priv == NULL) {
- mutex_unlock(&kgsl_driver.process_mutex);
- return 0;
- }
-
- if (!strncmp(attr->attr.name, "user", 4))
- val = priv->stats.user;
- if (!strncmp(attr->attr.name, "user_max", 8))
- val = priv->stats.user_max;
- if (!strncmp(attr->attr.name, "mapped", 6))
- val = priv->stats.mapped;
- if (!strncmp(attr->attr.name, "mapped_max", 10))
- val = priv->stats.mapped_max;
- if (!strncmp(attr->attr.name, "flushes", 7))
- val = priv->stats.flushes;
+ if (priv && pattr->show)
+ ret = pattr->show(priv, pattr->memtype, buf);
+ else
+ ret = -EIO;
mutex_unlock(&kgsl_driver.process_mutex);
- return snprintf(buf, PAGE_SIZE, "%u\n", val);
+ return ret;
}
-#define KGSL_MEMSTAT_ATTR(_name, _show) \
- static struct kobj_attribute attr_##_name = \
- __ATTR(_name, 0444, _show, NULL)
-
-KGSL_MEMSTAT_ATTR(user, process_show);
-KGSL_MEMSTAT_ATTR(user_max, process_show);
-KGSL_MEMSTAT_ATTR(mapped, process_show);
-KGSL_MEMSTAT_ATTR(mapped_max, process_show);
-KGSL_MEMSTAT_ATTR(flushes, process_show);
-
-static struct attribute *process_attrs[] = {
- &attr_user.attr,
- &attr_user_max.attr,
- &attr_mapped.attr,
- &attr_mapped_max.attr,
- &attr_flushes.attr,
- NULL
+static const struct sysfs_ops mem_entry_sysfs_ops = {
+ .show = mem_entry_sysfs_show,
};
-static struct attribute_group process_attr_group = {
- .attrs = process_attrs,
+static struct kobj_type ktype_mem_entry = {
+ .sysfs_ops = &mem_entry_sysfs_ops,
+ .default_attrs = NULL,
+ .release = mem_entry_sysfs_release
+};
+
+static struct mem_entry_stats mem_stats[] = {
+ MEM_ENTRY_STAT(KGSL_MEM_ENTRY_KERNEL, kernel),
+#ifdef CONFIG_ANDROID_PMEM
+ MEM_ENTRY_STAT(KGSL_MEM_ENTRY_PMEM, pmem),
+#endif
+#ifdef CONFIG_ASHMEM
+ MEM_ENTRY_STAT(KGSL_MEM_ENTRY_ASHMEM, ashmem),
+#endif
+ MEM_ENTRY_STAT(KGSL_MEM_ENTRY_USER, user),
+#ifdef CONFIG_ION
+ MEM_ENTRY_STAT(KGSL_MEM_ENTRY_USER, ion),
+#endif
};
void
kgsl_process_uninit_sysfs(struct kgsl_process_private *private)
{
- /* Remove the sysfs entry */
- if (private->kobj) {
- sysfs_remove_group(private->kobj, &process_attr_group);
- kobject_put(private->kobj);
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(mem_stats); i++) {
+ sysfs_remove_file(&private->kobj, &mem_stats[i].attr.attr);
+ sysfs_remove_file(&private->kobj,
+ &mem_stats[i].max_attr.attr);
}
+
+ kobject_put(&private->kobj);
}
void
kgsl_process_init_sysfs(struct kgsl_process_private *private)
{
unsigned char name[16];
+ int i, ret;
- /* Add a entry to the sysfs device */
snprintf(name, sizeof(name), "%d", private->pid);
- private->kobj = kobject_create_and_add(name, kgsl_driver.prockobj);
- /* sysfs failure isn't fatal, just annoying */
- if (private->kobj != NULL) {
- if (sysfs_create_group(private->kobj, &process_attr_group)) {
- kobject_put(private->kobj);
- private->kobj = NULL;
- }
+ if (kobject_init_and_add(&private->kobj, &ktype_mem_entry,
+ kgsl_driver.prockobj, name))
+ return;
+
+ for (i = 0; i < ARRAY_SIZE(mem_stats); i++) {
+ /* We need to check the value of sysfs_create_file, but we
+ * don't really care if it passed or not */
+
+ ret = sysfs_create_file(&private->kobj,
+ &mem_stats[i].attr.attr);
+ ret = sysfs_create_file(&private->kobj,
+ &mem_stats[i].max_attr.attr);
}
}
diff --git a/drivers/gpu/msm/z180.c b/drivers/gpu/msm/z180.c
index 6cd57b3..9e14247 100644
--- a/drivers/gpu/msm/z180.c
+++ b/drivers/gpu/msm/z180.c
@@ -411,7 +411,7 @@
unsigned int sizedwords;
if (device->state & KGSL_STATE_HUNG) {
- return -EINVAL;
+ result = -EINVAL;
goto error;
}
if (numibs != 1) {
diff --git a/drivers/hwmon/msmproc_adc.c b/drivers/hwmon/msmproc_adc.c
index a0ee748..fa6949e 100644
--- a/drivers/hwmon/msmproc_adc.c
+++ b/drivers/hwmon/msmproc_adc.c
@@ -34,81 +34,89 @@
};
static const struct pm8921_adc_map_pt adcmap_btm_threshold[] = {
- {-30, 41001},
- {-20, 40017},
- {-10, 38721},
- {0, 37186},
- {10, 35554},
- {11, 35392},
- {12, 35230},
- {13, 35070},
- {14, 34910},
- {15, 34751},
- {16, 34594},
- {17, 34438},
- {18, 34284},
- {19, 34131},
- {20, 33980},
- {21, 33830},
- {22, 33683},
- {23, 33538},
- {24, 33394},
- {25, 33253},
- {26, 33114},
- {27, 32977},
- {28, 32842},
- {29, 32710},
- {30, 32580},
- {31, 32452},
- {32, 32327},
- {33, 32204},
- {34, 32084},
- {35, 31966},
- {36, 31850},
- {37, 31737},
- {38, 31627},
- {39, 31518},
- {40, 31412},
- {41, 31309},
- {42, 31208},
- {43, 31109},
- {44, 31013},
- {45, 30918},
- {46, 30827},
- {47, 30737},
- {48, 30649},
- {49, 30564},
- {50, 30481},
- {51, 30400},
- {52, 30321},
- {53, 30244},
- {54, 30169},
- {55, 30096},
- {56, 30025},
- {57, 29956},
- {58, 29889},
- {59, 29823},
- {60, 29759},
- {61, 29697},
- {62, 29637},
- {63, 29578},
- {64, 29521},
- {65, 29465},
- {66, 29411},
- {67, 29359},
- {68, 29308},
- {69, 29258},
- {70, 29209},
- {71, 29162},
- {72, 29117},
- {73, 29072},
- {74, 29029},
- {75, 28987},
- {76, 28946},
- {77, 28906},
- {78, 28868},
- {79, 28830},
- {80, 28794}
+ {-30, 1642},
+ {-20, 1544},
+ {-10, 1414},
+ {0, 1260},
+ {1, 1244},
+ {2, 1228},
+ {3, 1212},
+ {4, 1195},
+ {5, 1179},
+ {6, 1162},
+ {7, 1146},
+ {8, 1129},
+ {9, 1113},
+ {10, 1097},
+ {11, 1080},
+ {12, 1064},
+ {13, 1048},
+ {14, 1032},
+ {15, 1016},
+ {16, 1000},
+ {17, 985},
+ {18, 969},
+ {19, 954},
+ {20, 939},
+ {21, 924},
+ {22, 909},
+ {23, 894},
+ {24, 880},
+ {25, 866},
+ {26, 852},
+ {27, 838},
+ {28, 824},
+ {29, 811},
+ {30, 798},
+ {31, 785},
+ {32, 773},
+ {33, 760},
+ {34, 748},
+ {35, 736},
+ {36, 725},
+ {37, 713},
+ {38, 702},
+ {39, 691},
+ {40, 681},
+ {41, 670},
+ {42, 660},
+ {43, 650},
+ {44, 640},
+ {45, 631},
+ {46, 622},
+ {47, 613},
+ {48, 604},
+ {49, 595},
+ {50, 587},
+ {51, 579},
+ {52, 571},
+ {53, 563},
+ {54, 556},
+ {55, 548},
+ {56, 541},
+ {57, 534},
+ {58, 527},
+ {59, 521},
+ {60, 514},
+ {61, 508},
+ {62, 502},
+ {63, 496},
+ {64, 490},
+ {65, 485},
+ {66, 281},
+ {67, 274},
+ {68, 267},
+ {69, 260},
+ {70, 254},
+ {71, 247},
+ {72, 241},
+ {73, 235},
+ {74, 229},
+ {75, 224},
+ {76, 218},
+ {77, 213},
+ {78, 208},
+ {79, 203}
};
static const struct pm8921_adc_map_pt adcmap_pa_therm[] = {
@@ -591,7 +599,9 @@
}
EXPORT_SYMBOL_GPL(pm8921_adc_tdkntcg_therm);
-int32_t pm8921_adc_batt_scaler(struct pm8921_adc_arb_btm_param *btm_param)
+int32_t pm8921_adc_batt_scaler(struct pm8921_adc_arb_btm_param *btm_param,
+ const struct pm8921_adc_properties *adc_properties,
+ const struct pm8921_adc_chan_properties *chan_properties)
{
int rc;
@@ -600,14 +610,28 @@
ARRAY_SIZE(adcmap_btm_threshold),
btm_param->low_thr_temp,
&btm_param->low_thr_voltage);
+ if (rc)
+ return rc;
- if (!rc) {
- rc = pm8921_adc_map_linear(
+ btm_param->low_thr_voltage *=
+ chan_properties->adc_graph[ADC_CALIB_RATIOMETRIC].dy;
+ do_div(btm_param->low_thr_voltage, adc_properties->adc_vdd_reference);
+ btm_param->low_thr_voltage +=
+ chan_properties->adc_graph[ADC_CALIB_RATIOMETRIC].adc_gnd;
+
+ rc = pm8921_adc_map_linear(
adcmap_btm_threshold,
ARRAY_SIZE(adcmap_btm_threshold),
btm_param->high_thr_temp,
&btm_param->high_thr_voltage);
- }
+ if (rc)
+ return rc;
+
+ btm_param->high_thr_voltage *=
+ chan_properties->adc_graph[ADC_CALIB_RATIOMETRIC].dy;
+ do_div(btm_param->high_thr_voltage, adc_properties->adc_vdd_reference);
+ btm_param->high_thr_voltage +=
+ chan_properties->adc_graph[ADC_CALIB_RATIOMETRIC].adc_gnd;
return rc;
}
diff --git a/drivers/hwmon/pm8921-adc.c b/drivers/hwmon/pm8921-adc.c
index 5ab6296..38e18de 100644
--- a/drivers/hwmon/pm8921-adc.c
+++ b/drivers/hwmon/pm8921-adc.c
@@ -31,6 +31,7 @@
#include <linux/mfd/pm8xxx/pm8921-adc.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
+#include <linux/wakelock.h>
/* User Bank register set */
#define PM8921_ADC_ARB_USRP_CNTRL1 0x197
@@ -142,6 +143,8 @@
uint32_t mpp_base;
struct sensor_device_attribute *sens_attr;
struct device *hwmon;
+ struct wake_lock adc_wakelock;
+ int msm_suspend_check;
};
struct pm8921_adc_amux_properties {
@@ -188,14 +191,18 @@
static bool pm8921_adc_calib_first_adc;
static bool pm8921_adc_initialized, pm8921_adc_calib_device_init;
-static int32_t pm8921_adc_arb_cntrl(uint32_t arb_cntrl)
+static int32_t pm8921_adc_arb_cntrl(uint32_t arb_cntrl, uint32_t channel)
{
struct pm8921_adc *adc_pmic = pmic_adc;
int i, rc;
u8 data_arb_cntrl = 0;
- if (arb_cntrl)
+ if (arb_cntrl) {
+ if (adc_pmic->msm_suspend_check)
+ pr_err("PM8921 ADC request being made after suspend "
+ "irq with channel id:%d\n", channel);
data_arb_cntrl |= PM8921_ADC_ARB_USRP_CNTRL1_EN_ARB;
+ }
/* Write twice to the CNTRL register for the arbiter settings
to take into effect */
@@ -212,6 +219,13 @@
data_arb_cntrl |= PM8921_ADC_ARB_USRP_CNTRL1_REQ;
rc = pm8xxx_writeb(adc_pmic->dev->parent,
PM8921_ADC_ARB_USRP_CNTRL1, data_arb_cntrl);
+ if (rc < 0) {
+ pr_err("PM8921 arb cntrl write failed with %d\n", rc);
+ return rc;
+ }
+ wake_lock(&adc_pmic->adc_wakelock);
+ } else {
+ wake_unlock(&adc_pmic->adc_wakelock);
}
return 0;
@@ -369,7 +383,7 @@
if (!pm8921_adc_calib_first_adc)
enable_irq(adc_pmic->adc_irq);
- rc = pm8921_adc_arb_cntrl(1);
+ rc = pm8921_adc_arb_cntrl(1, chan_prop->amux_mpp_channel);
if (rc < 0) {
pr_err("Configuring ADC Arbiter"
"enable failed with %d\n", rc);
@@ -409,7 +423,7 @@
/* Default value for switching off the arbiter after reading
the ADC value. Bit 0 set to 0. */
- rc = pm8921_adc_arb_cntrl(0);
+ rc = pm8921_adc_arb_cntrl(0, CHANNEL_MUXOFF);
if (rc < 0) {
pr_err("%s: Configuring ADC Arbiter disable"
"failed\n", __func__);
@@ -558,7 +572,7 @@
(calib_read_1 - calib_read_2);
adc_pmic->conv->chan_prop->adc_graph[ADC_CALIB_ABSOLUTE].dx
= PM8921_CHANNEL_ADC_625_MV;
- rc = pm8921_adc_arb_cntrl(0);
+ rc = pm8921_adc_arb_cntrl(0, CHANNEL_MUXOFF);
if (rc < 0) {
pr_err("%s: Configuring ADC Arbiter disable"
"failed\n", __func__);
@@ -630,15 +644,18 @@
offset_adc = calib_read_2 -
((slope_adc * adc_pmic->adc_prop->adc_vdd_reference)
>> PM8921_ADC_MUL);
-
adc_pmic->conv->chan_prop->adc_graph[ADC_CALIB_RATIOMETRIC].offset
= offset_adc;
adc_pmic->conv->chan_prop->adc_graph[ADC_CALIB_RATIOMETRIC].dy =
(calib_read_1 - calib_read_2);
adc_pmic->conv->chan_prop->adc_graph[ADC_CALIB_RATIOMETRIC].dx =
adc_pmic->adc_prop->adc_vdd_reference;
+ adc_pmic->conv->chan_prop->adc_graph[ADC_CALIB_RATIOMETRIC].adc_vref =
+ calib_read_1;
+ adc_pmic->conv->chan_prop->adc_graph[ADC_CALIB_RATIOMETRIC].adc_gnd =
+ calib_read_2;
calib_fail:
- rc = pm8921_adc_arb_cntrl(0);
+ rc = pm8921_adc_arb_cntrl(0, CHANNEL_MUXOFF);
if (rc < 0) {
pr_err("%s: Configuring ADC Arbiter disable"
"failed\n", __func__);
@@ -813,7 +830,8 @@
return -EINVAL;
}
- rc = pm8921_adc_batt_scaler(btm_param);
+ rc = pm8921_adc_batt_scaler(btm_param, adc_pmic->adc_prop,
+ adc_pmic->conv->chan_prop);
if (rc < 0) {
pr_err("Failed to lookup the BTM thresholds\n");
return rc;
@@ -1122,11 +1140,43 @@
return rc;
}
+#ifdef CONFIG_PM
+static int pm8921_adc_suspend_noirq(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct pm8921_adc *adc_pmic = platform_get_drvdata(pdev);
+
+ adc_pmic->msm_suspend_check = 1;
+
+ return 0;
+}
+
+static int pm8921_adc_resume_noirq(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct pm8921_adc *adc_pmic = platform_get_drvdata(pdev);
+
+ adc_pmic->msm_suspend_check = 0;
+
+ return 0;
+}
+
+static const struct dev_pm_ops pm8921_adc_dev_pm_ops = {
+ .suspend_noirq = pm8921_adc_suspend_noirq,
+ .resume_noirq = pm8921_adc_resume_noirq,
+};
+
+#define PM8921_ADC_DEV_PM_OPS (&pm8921_adc_dev_pm_ops)
+#else
+#define PM8921_ADC_DEV_PM_OPS NULL
+#endif
+
static int __devexit pm8921_adc_teardown(struct platform_device *pdev)
{
struct pm8921_adc *adc_pmic = pmic_adc;
int i;
+ wake_lock_destroy(&adc_pmic->adc_wakelock);
free_irq(adc_pmic->adc_irq, adc_pmic);
free_irq(adc_pmic->btm_warm_irq, adc_pmic);
free_irq(adc_pmic->btm_cool_irq, adc_pmic);
@@ -1262,6 +1312,8 @@
INIT_WORK(&adc_pmic->warm_work, pm8921_adc_btm_warm_scheduler_fn);
INIT_WORK(&adc_pmic->cool_work, pm8921_adc_btm_cool_scheduler_fn);
+ wake_lock_init(&adc_pmic->adc_wakelock, WAKE_LOCK_SUSPEND,
+ "pm8921_adc_wakelock");
create_debugfs_entries();
pm8921_adc_calib_first_adc = false;
pm8921_adc_calib_device_init = false;
@@ -1286,6 +1338,7 @@
.driver = {
.name = PM8921_ADC_DEV_NAME,
.owner = THIS_MODULE,
+ .pm = PM8921_ADC_DEV_PM_OPS,
},
};
diff --git a/drivers/input/touchscreen/cyttsp-i2c.c b/drivers/input/touchscreen/cyttsp-i2c.c
index a3446a3..aefce3e 100644
--- a/drivers/input/touchscreen/cyttsp-i2c.c
+++ b/drivers/input/touchscreen/cyttsp-i2c.c
@@ -2419,7 +2419,7 @@
}
rc = regulator_set_optimum_mode(ts->vdd[i],
- reg_info[i].load_uA);
+ reg_info[i].hpm_load_uA);
if (rc < 0) {
pr_err("%s: regulator_set_optimum_mode failed rc=%d\n",
__func__, rc);
@@ -2838,6 +2838,57 @@
}
#ifdef CONFIG_PM
+static int cyttsp_regulator_lpm(struct cyttsp *ts, bool on)
+{
+ int rc = 0, i;
+ const struct cyttsp_regulator *reg_info =
+ ts->platform_data->regulator_info;
+ u8 num_reg = ts->platform_data->num_regulators;
+
+ if (on == false)
+ goto regulator_hpm;
+
+ for (i = 0; i < num_reg; i++) {
+ rc = regulator_set_optimum_mode(ts->vdd[i],
+ reg_info[i].lpm_load_uA);
+ if (rc < 0) {
+ pr_err("%s: regulator_set_optimum failed rc = %d\n",
+ __func__, rc);
+ goto fail_regulator_lpm;
+ }
+
+ }
+
+ return 0;
+
+regulator_hpm:
+ for (i = 0; i < num_reg; i++) {
+ rc = regulator_set_optimum_mode(ts->vdd[i],
+ reg_info[i].hpm_load_uA);
+ if (rc < 0) {
+ pr_err("%s: regulator_set_optimum failed"
+ "rc = %d\n", __func__, rc);
+ goto fail_regulator_hpm;
+ }
+ }
+
+ return 0;
+
+fail_regulator_lpm:
+ while (i--)
+ regulator_set_optimum_mode(ts->vdd[i],
+ reg_info[i].hpm_load_uA);
+
+ return rc;
+
+fail_regulator_hpm:
+ while (i--)
+ regulator_set_optimum_mode(ts->vdd[i],
+ reg_info[i].lpm_load_uA);
+
+ return rc;
+}
+
/* Function to manage power-on resume */
static int cyttsp_resume(struct device *dev)
{
@@ -2865,6 +2916,8 @@
(ts->platform_data->power_state != CY_ACTIVE_STATE)) {
if (ts->platform_data->resume)
retval = ts->platform_data->resume(ts->client);
+ else
+ retval = cyttsp_regulator_lpm(ts, false);
/* take TTSP device out of bootloader mode;
* switch back to TrueTouch operational mode */
if (!(retval < CY_OK)) {
@@ -2948,14 +3001,23 @@
if (!(retval < CY_OK)) {
if (ts->platform_data->use_sleep &&
(ts->platform_data->power_state == CY_ACTIVE_STATE)) {
+ if (ts->platform_data->suspend) {
+ retval =
+ ts->platform_data->suspend(ts->client);
+ } else {
+ retval = cyttsp_regulator_lpm(ts, true);
+ }
if (ts->platform_data->use_sleep & CY_USE_DEEP_SLEEP_SEL)
sleep_mode = CY_DEEP_SLEEP_MODE;
else
sleep_mode = CY_LOW_PWR_MODE;
- retval = i2c_smbus_write_i2c_block_data(ts->client,
- CY_REG_BASE,
- sizeof(sleep_mode), &sleep_mode);
+ if (!(retval < CY_OK)) {
+ retval =
+ i2c_smbus_write_i2c_block_data(ts->client,
+ CY_REG_BASE,
+ sizeof(sleep_mode), &sleep_mode);
+ }
}
}
diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig
index feb345d..60c200e 100644
--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig
@@ -354,7 +354,7 @@
config LEDS_MSM_PMIC
tristate "LED Support for Qualcomm PMIC connected LEDs"
- default y
+ default n
depends on ARCH_MSM
help
This option enables support for LEDs connected over PMIC
diff --git a/drivers/leds/led-class.c b/drivers/leds/led-class.c
index b9520c8..b76b6d9 100644
--- a/drivers/leds/led-class.c
+++ b/drivers/leds/led-class.c
@@ -20,53 +20,12 @@
#include <linux/err.h>
#include <linux/ctype.h>
#include <linux/leds.h>
-#include <linux/slab.h>
#include "leds.h"
#define LED_BUFF_SIZE 50
static struct class *leds_class;
-#ifdef CONFIG_HAS_EARLYSUSPEND
-
-static void change_brightness(struct work_struct *brightness_change_data)
-{
- struct deferred_brightness_change *brightness_change = container_of(
- brightness_change_data,
- struct deferred_brightness_change,
- brightness_change_work);
- struct led_classdev *led_cdev = brightness_change->led_cdev;
- enum led_brightness value = brightness_change->value;
-
- led_cdev->brightness_set(led_cdev, value);
-
- /* Free up memory for the brightness_change structure. */
- kfree(brightness_change);
-}
-
-int queue_brightness_change(struct led_classdev *led_cdev,
- enum led_brightness value)
-{
- /* Initialize the brightness_change_work and its super-struct. */
- struct deferred_brightness_change *brightness_change =
- kzalloc(sizeof(struct deferred_brightness_change), GFP_KERNEL);
-
- if (!brightness_change)
- return -ENOMEM;
-
- brightness_change->led_cdev = led_cdev;
- brightness_change->value = value;
-
- INIT_WORK(&(brightness_change->brightness_change_work),
- change_brightness);
- queue_work(suspend_work_queue,
- &(brightness_change->brightness_change_work));
-
- return 0;
-}
-
-#endif
-
static void led_update_brightness(struct led_classdev *led_cdev)
{
if (led_cdev->brightness_get)
diff --git a/drivers/leds/leds.h b/drivers/leds/leds.h
index 593a63c..e77c7f8 100644
--- a/drivers/leds/leds.h
+++ b/drivers/leds/leds.h
@@ -16,21 +16,6 @@
#include <linux/device.h>
#include <linux/rwsem.h>
#include <linux/leds.h>
-#include <linux/workqueue.h>
-
-#ifdef CONFIG_HAS_EARLYSUSPEND
-
-extern struct workqueue_struct *suspend_work_queue;
-extern int queue_brightness_change(struct led_classdev *led_cdev,
- enum led_brightness value);
-
-struct deferred_brightness_change {
- struct work_struct brightness_change_work;
- struct led_classdev *led_cdev;
- enum led_brightness value;
-};
-
-#endif
static inline void led_set_brightness(struct led_classdev *led_cdev,
enum led_brightness value)
@@ -38,12 +23,8 @@
if (value > led_cdev->max_brightness)
value = led_cdev->max_brightness;
led_cdev->brightness = value;
- if (!(led_cdev->flags & LED_SUSPENDED)) {
-#ifdef CONFIG_HAS_EARLYSUSPEND
- if (queue_brightness_change(led_cdev, value) != 0)
-#endif
- led_cdev->brightness_set(led_cdev, value);
- }
+ if (!(led_cdev->flags & LED_SUSPENDED))
+ led_cdev->brightness_set(led_cdev, value);
}
static inline int led_get_brightness(struct led_classdev *led_cdev)
diff --git a/drivers/media/radio/radio-iris.c b/drivers/media/radio/radio-iris.c
index 179f465..a256e51 100644
--- a/drivers/media/radio/radio-iris.c
+++ b/drivers/media/radio/radio-iris.c
@@ -84,11 +84,13 @@
struct hci_fm_trans_conf_req_struct trans_conf;
struct hci_fm_rds_grp_req rds_grp;
unsigned char g_search_mode;
+ unsigned char power_mode;
int search_on;
unsigned int tone_freq;
unsigned char g_scan_time;
unsigned int g_antenna;
unsigned int g_rds_grp_proc_ps;
+ unsigned char event_mask;
enum iris_region_t region;
struct hci_fm_dbg_param_rsp st_dbg_param;
struct hci_ev_srch_list_compl srch_st_result;
@@ -98,6 +100,7 @@
};
static struct video_device *priv_videodev;
+static int iris_do_calibration(struct iris_device *radio);
static struct v4l2_queryctrl iris_v4l2_queryctrl[] = {
{
@@ -402,6 +405,20 @@
.type = V4L2_CTRL_TYPE_INTEGER,
.name = "Write default",
},
+ {
+ .id = V4L2_CID_PRIVATE_IRIS_SET_CALIBRATION,
+ .type = V4L2_CTRL_TYPE_BOOLEAN,
+ .name = "SET Calibration",
+ .minimum = 0,
+ .maximum = 1,
+ },
+ {
+ .id = V4L2_CID_PRIVATE_IRIS_DO_CALIBRATION,
+ .type = V4L2_CTRL_TYPE_BOOLEAN,
+ .name = "SET Calibration",
+ .minimum = 0,
+ .maximum = 1,
+ },
};
static void iris_q_event(struct iris_device *radio,
@@ -748,6 +765,17 @@
&sig_threshold);
}
+static int hci_fm_set_event_mask(struct radio_hci_dev *hdev,
+ unsigned long param)
+{
+ u16 opcode = 0;
+ u8 event_mask = param;
+
+ opcode = hci_opcode_pack(HCI_OGF_FM_RECV_CTRL_CMD_REQ,
+ HCI_OCF_FM_SET_EVENT_MASK);
+ return radio_hci_send_cmd(hdev, opcode, sizeof(event_mask),
+ &event_mask);
+}
static int hci_fm_get_sig_threshold_req(struct radio_hci_dev *hdev,
unsigned long param)
{
@@ -1080,6 +1108,13 @@
return ret;
}
+static inline int hci_conf_event_mask(__u8 *arg,
+ struct radio_hci_dev *hdev)
+{
+ u8 event_mask = *arg;
+ return radio_hci_request(hdev, hci_fm_set_event_mask,
+ event_mask, RADIO_HCI_TIMEOUT);
+}
static int hci_set_fm_recv_conf(struct hci_fm_recv_conf_req *arg,
struct radio_hci_dev *hdev)
{
@@ -1317,6 +1352,32 @@
return ret;
}
+static int hci_fm_set_cal_req(struct radio_hci_dev *hdev,
+ unsigned long param)
+{
+ u16 opcode = 0;
+ struct hci_fm_set_cal_req *cal_req =
+ (struct hci_fm_set_cal_req *)param;
+
+ opcode = hci_opcode_pack(HCI_OGF_FM_COMMON_CTRL_CMD_REQ,
+ HCI_OCF_FM_SET_CALIBRATION);
+ return radio_hci_send_cmd(hdev, opcode, sizeof((*hci_fm_set_cal_req)),
+ cal_req);
+
+}
+
+static int hci_fm_do_cal_req(struct radio_hci_dev *hdev,
+ unsigned long param)
+{
+ u16 opcode = 0;
+ u8 cal_mode = param;
+
+ opcode = hci_opcode_pack(HCI_OGF_FM_COMMON_CTRL_CMD_REQ,
+ HCI_OCF_FM_DO_CALIBRATION);
+ return radio_hci_send_cmd(hdev, opcode, sizeof(cal_mode),
+ &cal_mode);
+
+}
static int hci_cmd(unsigned int cmd, struct radio_hci_dev *hdev)
{
int ret = 0;
@@ -1670,6 +1731,29 @@
}
+static void hci_cc_do_calibration_rsp(struct radio_hci_dev *hdev,
+ struct sk_buff *skb)
+{
+ struct iris_device *radio = video_get_drvdata(video_get_dev());
+ static struct hci_cc_do_calibration_rsp rsp ;
+ rsp.status = skb->data[0];
+ rsp.mode = skb->data[CALIB_MODE_OFSET];
+
+ if (rsp.status) {
+ FMDERR("status = %d", rsp.status);
+ return;
+ }
+ if (rsp.mode == PROCS_CALIB_MODE) {
+ memcpy(&rsp.data[0], &skb->data[CALIB_DATA_OFSET],
+ PROCS_CALIB_SIZE);
+ } else if (rsp.mode == DC_CALIB_MODE) {
+ memcpy(&rsp.data[PROCS_CALIB_SIZE],
+ &skb->data[CALIB_DATA_OFSET], DC_CALIB_SIZE);
+ iris_q_evt_data(radio, rsp.data, (PROCS_CALIB_SIZE +
+ DC_CALIB_SIZE), IRIS_BUF_CAL_DATA);
+ }
+ radio_hci_req_complete(hdev, rsp.status);
+}
static inline void hci_cmd_complete_event(struct radio_hci_dev *hdev,
struct sk_buff *skb)
{
@@ -1713,6 +1797,8 @@
case hci_diagnostic_cmd_op_pack(HCI_OCF_FM_SSBI_POKE_REG):
case hci_diagnostic_cmd_op_pack(HCI_OCF_FM_POKE_DATA):
case hci_diagnostic_cmd_op_pack(HCI_FM_SET_INTERNAL_TONE_GENRATOR):
+ case hci_common_cmd_op_pack(HCI_OCF_FM_SET_CALIBRATION):
+ case hci_recv_ctrl_cmd_op_pack(HCI_OCF_FM_SET_EVENT_MASK):
hci_cc_rsp(hdev, skb);
break;
@@ -1761,6 +1847,9 @@
case hci_status_param_op_pack(HCI_OCF_FM_READ_GRP_COUNTERS):
hci_cc_rds_grp_cntrs_rsp(hdev, skb);
break;
+ case hci_common_cmd_op_pack(HCI_OCF_FM_DO_CALIBRATION):
+ hci_cc_do_calibration_rsp(hdev, skb);
+ break;
default:
FMDERR("%s opcode 0x%x", hdev->name, opcode);
@@ -2089,6 +2178,43 @@
return retval;
}
+static int set_low_power_mode(struct iris_device *radio, int power_mode)
+{
+
+ int rds_grps_proc = 0x00;
+ int retval = 0;
+ if (radio->power_mode != power_mode) {
+
+ if (power_mode) {
+ radio->event_mask = 0x00;
+ rds_grps_proc = 0x00 | AF_JUMP_ENABLE ;
+ retval = hci_fm_rds_grps_process(
+ &rds_grps_proc,
+ radio->fm_hdev);
+ if (retval < 0) {
+ FMDERR("Disable RDS failed");
+ return retval;
+ }
+ retval = hci_conf_event_mask(&radio->event_mask,
+ radio->fm_hdev);
+ } else {
+
+ radio->event_mask = SIG_LEVEL_INTR |
+ RDS_SYNC_INTR | AUDIO_CTRL_INTR;
+ retval = hci_conf_event_mask(&radio->event_mask,
+ radio->fm_hdev);
+ if (retval < 0) {
+ FMDERR("Enable Async events failed");
+ return retval;
+ }
+ retval = hci_fm_rds_grps_process(
+ &radio->g_rds_grp_proc_ps,
+ radio->fm_hdev);
+ }
+ radio->power_mode = power_mode;
+ }
+ return retval;
+}
static int iris_recv_set_region(struct iris_device *radio, int req_region)
{
int retval;
@@ -2201,6 +2327,37 @@
return retval;
}
+static int iris_do_calibration(struct iris_device *radio)
+{
+ char cal_mode = 0x00;
+ int retval = 0x00;
+
+ cal_mode = PROCS_CALIB_MODE;
+ retval = hci_cmd(HCI_FM_ENABLE_RECV_CMD,
+ radio->fm_hdev);
+ if (retval < 0) {
+ FMDERR("Enable failed before calibration %x", retval);
+ return retval;
+ }
+ retval = radio_hci_request(radio->fm_hdev, hci_fm_do_cal_req,
+ (unsigned long)cal_mode, RADIO_HCI_TIMEOUT);
+ if (retval < 0) {
+ FMDERR("Do Process calibration failed %x", retval);
+ return retval;
+ }
+ cal_mode = DC_CALIB_MODE;
+ retval = radio_hci_request(radio->fm_hdev, hci_fm_do_cal_req,
+ (unsigned long)cal_mode, RADIO_HCI_TIMEOUT);
+ if (retval < 0) {
+ FMDERR("Do DC calibration failed %x", retval);
+ return retval;
+ }
+ retval = hci_cmd(HCI_FM_DISABLE_RECV_CMD,
+ radio->fm_hdev);
+ if (retval < 0)
+ FMDERR("Disable Failed after calibration %d", retval);
+ return retval;
+}
static int iris_vidioc_g_ctrl(struct file *file, void *priv,
struct v4l2_control *ctrl)
{
@@ -2303,6 +2460,7 @@
ctrl->value = radio->rds_grp.rds_buf_size;
break;
case V4L2_CID_PRIVATE_IRIS_LP_MODE:
+ ctrl->value = radio->power_mode;
break;
case V4L2_CID_PRIVATE_IRIS_ANTENNA:
ctrl->value = radio->g_antenna;
@@ -2310,6 +2468,9 @@
case V4L2_CID_PRIVATE_IRIS_SOFT_MUTE:
ctrl->value = radio->mute_mode.soft_mute;
break;
+ case V4L2_CID_PRIVATE_IRIS_DO_CALIBRATION:
+ retval = iris_do_calibration(radio);
+ break;
default:
retval = -EINVAL;
}
@@ -2351,6 +2512,7 @@
struct hci_fm_tx_ps tx_ps;
struct hci_fm_tx_rt tx_rt;
struct hci_fm_def_data_wr_req default_data;
+ struct hci_fm_set_cal_req cal_req;
struct iris_device *radio = video_get_drvdata(video_devdata(file));
char *data = NULL;
@@ -2402,6 +2564,28 @@
if (copy_from_user(&default_data, data, sizeof(default_data)))
return -EFAULT;
retval = hci_def_data_write(&default_data, radio->fm_hdev);
+ break;
+ case V4L2_CID_PRIVATE_IRIS_SET_CALIBRATION:
+ FMDERR("In Set Calibration");
+ data = (ctrl->controls[0]).string;
+ bytes_to_copy = (ctrl->controls[0]).size;
+ memset(cal_req.data, 0, MAX_CALIB_SIZE);
+ cal_req.mode = PROCS_CALIB_MODE;
+ if (copy_from_user(&cal_req.data[0],
+ data, PROCS_CALIB_SIZE))
+ return -EFAULT;
+ retval = radio_hci_request(radio->fm_hdev, hci_fm_set_cal_req,
+ (unsigned long)&cal_req, RADIO_HCI_TIMEOUT);
+ if (retval < 0)
+ FMDERR("Set Process calibration failed %d", retval);
+ if (copy_from_user(&cal_req.data[PROCS_CALIB_SIZE],
+ data, DC_CALIB_SIZE))
+ return -EFAULT;
+ cal_req.mode = DC_CALIB_MODE;
+ retval = radio_hci_request(radio->fm_hdev, hci_fm_set_cal_req,
+ (unsigned long)&cal_req, RADIO_HCI_TIMEOUT);
+ if (retval < 0)
+ FMDERR("Set DC calibration failed %d", retval);
break;
default:
FMDBG("Shouldn't reach here\n");
@@ -2464,8 +2648,10 @@
retval = hci_set_fm_mute_mode(
&radio->mute_mode,
radio->fm_hdev);
- if (retval < 0)
+ if (retval < 0) {
FMDERR("Failed to enable Smute\n");
+ return retval;
+ }
radio->stereo_mode.stereo_mode = CTRL_OFF;
radio->stereo_mode.sig_blend = CTRL_ON;
radio->stereo_mode.intf_blend = CTRL_ON;
@@ -2473,8 +2659,10 @@
retval = hci_set_fm_stereo_mode(
&radio->stereo_mode,
radio->fm_hdev);
- if (retval < 0)
+ if (retval < 0) {
FMDERR("Failed to set stereo mode\n");
+ return retval;
+ }
retval = hci_cmd(HCI_FM_GET_RECV_CONF_CMD,
radio->fm_hdev);
if (retval < 0)
@@ -2642,6 +2830,7 @@
radio->fm_hdev);
break;
case V4L2_CID_PRIVATE_IRIS_LP_MODE:
+ set_low_power_mode(radio, ctrl->value);
break;
case V4L2_CID_PRIVATE_IRIS_ANTENNA:
temp_val = ctrl->value;
diff --git a/drivers/media/video/msm/Kconfig b/drivers/media/video/msm/Kconfig
index a86460b..9361f5a9 100644
--- a/drivers/media/video/msm/Kconfig
+++ b/drivers/media/video/msm/Kconfig
@@ -37,6 +37,18 @@
default y
---help---
SONY 13.5 MP Bayer Sensor
+config OV5640
+ bool "Sensor OV5640 (YUV 5M)"
+ depends on MSM_CAMERA && !MSM_CAMERA_V4L2
+ default n
+ ---help---
+ Omni 5M YUV Sensor
+config WEBCAM_OV7692_QRD
+ bool "Sensor OV7692 QRD(VGA YUV)"
+ depends on MSM_CAMERA && ARCH_MSM7X27A && !MSM_CAMERA_V4L2
+ default n
+ ---help---
+ Omni Vision VGA YUV Sensor for QRD Devices
config WEBCAM_OV7692
bool "Sensor OV7692 (VGA YUV)"
depends on MSM_CAMERA && ARCH_MSM8X60 && !MSM_CAMERA_V4L2
diff --git a/drivers/media/video/msm/Makefile b/drivers/media/video/msm/Makefile
index bd3fffe..3f41d43 100644
--- a/drivers/media/video/msm/Makefile
+++ b/drivers/media/video/msm/Makefile
@@ -39,6 +39,8 @@
obj-$(CONFIG_IMX072) += imx072.o imx072_reg.o
obj-$(CONFIG_WEBCAM_OV9726) += ov9726.o ov9726_reg.o
obj-$(CONFIG_WEBCAM_OV7692) += ov7692.o
+obj-$(CONFIG_WEBCAM_OV7692_QRD) += ov7692_qrd.o
+obj-$(CONFIG_OV5640) += ov5640.o
obj-$(CONFIG_MT9D112) += mt9d112.o mt9d112_reg.o
obj-$(CONFIG_MT9D113) += mt9d113.o mt9d113_reg.o
diff --git a/drivers/media/video/msm/gemini/msm_gemini_core.c b/drivers/media/video/msm/gemini/msm_gemini_core.c
index db0f505..480500b 100644
--- a/drivers/media/video/msm/gemini/msm_gemini_core.c
+++ b/drivers/media/video/msm/gemini/msm_gemini_core.c
@@ -71,7 +71,8 @@
for (i = 0; i < 2; i++) {
if (we_pingpong_buf.buf_status[i] && release_buf)
msm_gemini_platform_p2v(we_pingpong_buf.buf[i].file,
- &we_pingpong_buf.buf[i].msm_buffer);
+ &we_pingpong_buf.buf[i].msm_buffer,
+ &we_pingpong_buf.buf[i].handle);
we_pingpong_buf.buf_status[i] = 0;
}
}
diff --git a/drivers/media/video/msm/gemini/msm_gemini_hw.h b/drivers/media/video/msm/gemini/msm_gemini_hw.h
index f91a135..3c2fc6a 100644
--- a/drivers/media/video/msm/gemini/msm_gemini_hw.h
+++ b/drivers/media/video/msm/gemini/msm_gemini_hw.h
@@ -16,6 +16,7 @@
#include <media/msm_gemini.h>
#include "msm_gemini_hw_reg.h"
#include <mach/msm_subsystem_map.h>
+#include <linux/ion.h>
struct msm_gemini_hw_buf {
struct msm_gemini_buf vbuf;
@@ -28,6 +29,7 @@
uint32_t num_of_mcu_rows;
struct msm_mapped_buffer *msm_buffer;
int *subsystem_id;
+ struct ion_handle *handle;
};
struct msm_gemini_hw_pingpong {
diff --git a/drivers/media/video/msm/gemini/msm_gemini_platform.c b/drivers/media/video/msm/gemini/msm_gemini_platform.c
index 9f5ec16..e81215e 100644
--- a/drivers/media/video/msm/gemini/msm_gemini_platform.c
+++ b/drivers/media/video/msm/gemini/msm_gemini_platform.c
@@ -25,29 +25,38 @@
/* AXI rate in KHz */
#define MSM_SYSTEM_BUS_RATE 160000
+struct ion_client *gemini_client;
void msm_gemini_platform_p2v(struct file *file,
- struct msm_mapped_buffer **msm_buffer)
+ struct msm_mapped_buffer **msm_buffer,
+ struct ion_handle **ionhandle)
{
-
if (msm_subsystem_unmap_buffer(
(struct msm_mapped_buffer *)*msm_buffer) < 0)
pr_err("%s: umapped stat memory\n", __func__);
*msm_buffer = NULL;
-#ifdef CONFIG_ANDROID_PMEM
+#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
+ ion_free(gemini_client, *ionhandle);
+ *ionhandle = NULL;
+#elif CONFIG_ANDROID_PMEM
put_pmem_file(file);
#endif
}
uint32_t msm_gemini_platform_v2p(int fd, uint32_t len, struct file **file_p,
- struct msm_mapped_buffer **msm_buffer,
- int *subsys_id)
+ struct msm_mapped_buffer **msm_buffer,
+ int *subsys_id, struct ion_handle **ionhandle)
{
unsigned long paddr;
unsigned long size;
int rc;
int flags;
-#ifdef CONFIG_ANDROID_PMEM
+#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
+ *ionhandle = ion_import_fd(gemini_client, fd);
+ if (IS_ERR_OR_NULL(*ionhandle))
+ return 0;
+ rc = ion_phys(gemini_client, *ionhandle, &paddr, (size_t *)&size);
+#elif CONFIG_ANDROID_PMEM
unsigned long kvstart;
rc = get_pmem_file(fd, &paddr, &kvstart, &size, file_p);
#else
@@ -73,6 +82,12 @@
flags, subsys_id, 1);
if (IS_ERR((void *)*msm_buffer)) {
pr_err("%s: msm_subsystem_map_buffer failed\n", __func__);
+#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
+ ion_free(gemini_client, *ionhandle);
+ *ionhandle = NULL;
+#elif CONFIG_ANDROID_PMEM
+ put_pmem_file(*file_p);
+#endif
return 0;
}
paddr = ((struct msm_mapped_buffer *)*msm_buffer)->iova[0];
@@ -136,6 +151,10 @@
*mem = gemini_mem;
*base = gemini_base;
*irq = gemini_irq;
+
+#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
+ gemini_client = msm_ion_client_create(-1, "camera/gemini");
+#endif
GMN_DBG("%s:%d] success\n", __func__, __LINE__);
return rc;
@@ -159,7 +178,9 @@
result = msm_camio_jpeg_clk_disable();
iounmap(base);
release_mem_region(mem->start, resource_size(mem));
-
+#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
+ ion_client_destroy(gemini_client);
+#endif
GMN_DBG("%s:%d] success\n", __func__, __LINE__);
return result;
}
diff --git a/drivers/media/video/msm/gemini/msm_gemini_platform.h b/drivers/media/video/msm/gemini/msm_gemini_platform.h
index cd897b0..c54d7df 100644
--- a/drivers/media/video/msm/gemini/msm_gemini_platform.h
+++ b/drivers/media/video/msm/gemini/msm_gemini_platform.h
@@ -15,12 +15,13 @@
#include <linux/interrupt.h>
#include <linux/platform_device.h>
-
+#include <linux/ion.h>
void msm_gemini_platform_p2v(struct file *file,
- struct msm_mapped_buffer **msm_buffer);
+ struct msm_mapped_buffer **msm_buffer,
+ struct ion_handle **ionhandle);
uint32_t msm_gemini_platform_v2p(int fd, uint32_t len, struct file **file,
struct msm_mapped_buffer **msm_buffer,
- int *subsys_id);
+ int *subsys_id, struct ion_handle **ionhandle);
int msm_gemini_platform_clk_enable(void);
int msm_gemini_platform_clk_disable(void);
diff --git a/drivers/media/video/msm/gemini/msm_gemini_sync.c b/drivers/media/video/msm/gemini/msm_gemini_sync.c
index c8d4fa0..0f0bd67 100644
--- a/drivers/media/video/msm/gemini/msm_gemini_sync.c
+++ b/drivers/media/video/msm/gemini/msm_gemini_sync.c
@@ -151,7 +151,7 @@
buf_p = msm_gemini_q_out(q_p);
if (buf_p) {
msm_gemini_platform_p2v(buf_p->file,
- &buf_p->msm_buffer);
+ &buf_p->msm_buffer, &buf_p->handle);
GMN_DBG("%s:%d] %s\n", __func__, __LINE__, q_p->name);
kfree(buf_p->subsystem_id);
kfree(buf_p);
@@ -317,7 +317,8 @@
}
buf_cmd = buf_p->vbuf;
- msm_gemini_platform_p2v(buf_p->file, &buf_p->msm_buffer);
+ msm_gemini_platform_p2v(buf_p->file, &buf_p->msm_buffer,
+ &buf_p->handle);
kfree(buf_p->subsystem_id);
kfree(buf_p);
@@ -368,7 +369,7 @@
}
buf_p->y_buffer_addr = msm_gemini_platform_v2p(buf_cmd.fd,
buf_cmd.y_len, &buf_p->file, &buf_p->msm_buffer,
- buf_p->subsystem_id);
+ buf_p->subsystem_id, &buf_p->handle);
if (!buf_p->y_buffer_addr) {
GMN_PR_ERR("%s:%d] v2p wrong\n", __func__, __LINE__);
kfree(buf_p->subsystem_id);
@@ -434,7 +435,8 @@
}
buf_cmd = buf_p->vbuf;
- msm_gemini_platform_p2v(buf_p->file, &buf_p->msm_buffer);
+ msm_gemini_platform_p2v(buf_p->file, &buf_p->msm_buffer,
+ &buf_p->handle);
kfree(buf_p->subsystem_id);
kfree(buf_p);
@@ -484,7 +486,7 @@
}
buf_p->y_buffer_addr = msm_gemini_platform_v2p(buf_cmd.fd,
buf_cmd.y_len + buf_cmd.cbcr_len, &buf_p->file,
- &buf_p->msm_buffer, buf_p->subsystem_id)
+ &buf_p->msm_buffer, buf_p->subsystem_id, &buf_p->handle)
+ buf_cmd.offset;
buf_p->y_len = buf_cmd.y_len;
diff --git a/drivers/media/video/msm/msm.c b/drivers/media/video/msm/msm.c
index 5d9112e..40a273a 100644
--- a/drivers/media/video/msm/msm.c
+++ b/drivers/media/video/msm/msm.c
@@ -1574,10 +1574,12 @@
mutex_lock(&pcam->vid_lock);
+ pcam_inst->streamon = 0;
pcam->use_count--;
pcam->dev_inst_map[pcam_inst->image_mode] = NULL;
if (pcam_inst->vbqueue_initialized)
vb2_queue_release(&pcam_inst->vid_bufq);
+ D("%s Closing down instance %p ", __func__, pcam_inst);
pcam->dev_inst[pcam_inst->my_index] = NULL;
if (pcam_inst->my_index == 0) {
v4l2_fh_del(&pcam_inst->eventHandle);
diff --git a/drivers/media/video/msm/msm_camera.c b/drivers/media/video/msm/msm_camera.c
index 6bc7d8e..565c724 100644
--- a/drivers/media/video/msm/msm_camera.c
+++ b/drivers/media/video/msm/msm_camera.c
@@ -2516,20 +2516,17 @@
} else {
enable &= PP_MASK;
if (enable & (enable - 1)) {
- pr_err("%s: error: more than one PP request!\n",
+ CDBG("%s: more than one PP request!\n",
__func__);
- return -EINVAL;
}
if (sync->pp_mask) {
if (enable) {
- pr_err("%s: postproc %x is already enabled\n",
+ CDBG("%s: postproc %x is already enabled\n",
__func__, sync->pp_mask & enable);
- return -EINVAL;
} else {
sync->pp_mask &= enable;
CDBG("%s: sync->pp_mask %d enable %d\n",
__func__, sync->pp_mask, enable);
- return 0;
}
}
diff --git a/drivers/media/video/msm/msm_isp.c b/drivers/media/video/msm/msm_isp.c
index 6983d70..e12d6b1 100644
--- a/drivers/media/video/msm/msm_isp.c
+++ b/drivers/media/video/msm/msm_isp.c
@@ -81,7 +81,11 @@
struct msm_cam_v4l2_device *pcam = sync->pcam_sync;
int vfe_id = vdata->evt_msg.msg_id;
-
+ if (!pcam) {
+ pr_err("%s pcam is null. return\n", __func__);
+ msm_isp_sync_free(vdata);
+ return rc;
+ }
switch (vdata->type) {
case VFE_MSG_V32_START:
case VFE_MSG_V32_START_RECORDING:
@@ -518,6 +522,8 @@
case CMD_AXI_CFG_PREVIEW:
case CMD_AXI_CFG_SNAP:
case CMD_AXI_CFG_ZSL:
+ case CMD_AXI_CFG_VIDEO_ALL_CHNLS:
+ case CMD_AXI_CFG_ZSL_ALL_CHNLS:
case CMD_RAW_PICT_AXI_CFG:
/* Dont need to pass buffer information.
* subdev will get the buffer from media
diff --git a/drivers/media/video/msm/msm_mctl.c b/drivers/media/video/msm/msm_mctl.c
index 4ee6117..a7fe8a2 100644
--- a/drivers/media/video/msm/msm_mctl.c
+++ b/drivers/media/video/msm/msm_mctl.c
@@ -73,6 +73,14 @@
.colorspace = V4L2_COLORSPACE_JPEG,
},
{
+ .name = "YU12BAYER",
+ .depth = 8,
+ .bitsperpxl = 8,
+ .fourcc = V4L2_PIX_FMT_YUV420M,
+ .pxlcode = V4L2_MBUS_FMT_SBGGR10_1X10, /* Bayer sensor */
+ .colorspace = V4L2_COLORSPACE_JPEG,
+ },
+ {
.name = "RAWBAYER",
.depth = 10,
.bitsperpxl = 10,
diff --git a/drivers/media/video/msm/msm_mctl_buf.c b/drivers/media/video/msm/msm_mctl_buf.c
index a8554ee..1bbb029 100644
--- a/drivers/media/video/msm/msm_mctl_buf.c
+++ b/drivers/media/video/msm/msm_mctl_buf.c
@@ -368,23 +368,28 @@
int msm_mctl_out_type_to_inst_index(struct msm_cam_v4l2_device *pcam,
int out_type)
{
+ int image_mode;
switch (out_type) {
case VFE_MSG_OUTPUT_P:
- return pcam->dev_inst_map
- [MSM_V4L2_EXT_CAPTURE_MODE_PREVIEW]->my_index;
+ image_mode = MSM_V4L2_EXT_CAPTURE_MODE_PREVIEW;
+ break;
case VFE_MSG_OUTPUT_V:
- return pcam->dev_inst_map
- [MSM_V4L2_EXT_CAPTURE_MODE_VIDEO]->my_index;
+ image_mode = MSM_V4L2_EXT_CAPTURE_MODE_VIDEO;
+ break;
case VFE_MSG_OUTPUT_S:
- return pcam->dev_inst_map
- [MSM_V4L2_EXT_CAPTURE_MODE_MAIN]->my_index;
+ image_mode = MSM_V4L2_EXT_CAPTURE_MODE_MAIN;
+ break;
case VFE_MSG_OUTPUT_T:
- return pcam->dev_inst_map
- [MSM_V4L2_EXT_CAPTURE_MODE_THUMBNAIL]->my_index;
+ image_mode = MSM_V4L2_EXT_CAPTURE_MODE_THUMBNAIL;
+ break;
default:
- return 0;
+ image_mode = -1;
+ break;
}
- return 0;
+ if ((image_mode >= 0) && pcam->dev_inst_map[image_mode])
+ return pcam->dev_inst_map[image_mode]->my_index;
+ else
+ return -EINVAL;
}
void msm_mctl_gettimeofday(struct timeval *tv)
@@ -482,6 +487,11 @@
else {
idx = msm_mctl_out_type_to_inst_index(
p_mctl->sync.pcam_sync, msg_type);
+ if (idx < 0) {
+ pr_err("%s Invalid instance, dropping buffer\n",
+ __func__);
+ return idx;
+ }
pcam_inst = p_mctl->sync.pcam_sync->dev_inst[idx];
rc = msm_mctl_buf_done_proc(p_mctl, pcam_inst,
msg_type, fbuf,
@@ -508,16 +518,20 @@
int rc = -EINVAL, idx, i;
uint32_t buf_idx, plane_offset = 0;
- if (!free_buf) {
- pr_err("%s: free_buf= null\n", __func__);
+ if (!free_buf || !pmctl) {
+ pr_err("%s: free_buf/pmctl is null\n", __func__);
return rc;
}
memset(free_buf, 0, sizeof(struct msm_free_buf));
idx = msm_mctl_out_type_to_inst_index(pmctl->sync.pcam_sync,
msg_type);
+ if (idx < 0) {
+ pr_err("%s Invalid instance, returning\n", __func__);
+ return idx;
+ }
pcam_inst = pmctl->sync.pcam_sync->dev_inst[idx];
if (!pcam_inst || !pcam_inst->streamon) {
- D("%s: stream is turned off\n", __func__);
+ pr_err("%s: stream is turned off\n", __func__);
return rc;
}
spin_lock_irqsave(&pcam_inst->vq_irqlock, flags);
@@ -582,6 +596,10 @@
return rc;
idx = msm_mctl_out_type_to_inst_index(pmctl->sync.pcam_sync, msg_type);
+ if (idx < 0) {
+ pr_err("%s Invalid instance, buffer not released\n", __func__);
+ return idx;
+ }
pcam_inst = pmctl->sync.pcam_sync->dev_inst[idx];
spin_lock_irqsave(&pcam_inst->vq_irqlock, flags);
list_for_each_entry(buf, &pcam_inst->free_vq, list) {
@@ -611,6 +629,10 @@
idx = msm_mctl_out_type_to_inst_index(
pmctl->sync.pcam_sync, msg_type);
+ if (idx < 0) {
+ pr_err("%s Invalid instance, buffer dropped\n", __func__);
+ return idx;
+ }
pcam_inst = pmctl->sync.pcam_sync->dev_inst[idx];
D("%s:inst=0x%p, paddr=0x%x, dirty=%d",
__func__, pcam_inst, frame->ch_paddr[0], dirty);
@@ -634,6 +656,10 @@
idx = msm_mctl_out_type_to_inst_index(pmctl->sync.pcam_sync,
msg_type);
+ if (idx < 0) {
+ pr_err("%s Invalid instance, cant get buffer\n", __func__);
+ return NULL;
+ }
pcam_inst = pmctl->sync.pcam_sync->dev_inst[idx];
if (!pcam_inst->streamon) {
D("%s: stream 0x%p is off\n", __func__, pcam_inst);
@@ -669,6 +695,10 @@
idx = msm_mctl_out_type_to_inst_index(pmctl->sync.pcam_sync,
msg_type);
+ if (idx < 0) {
+ pr_err("%s Invalid instance, cant put buffer\n", __func__);
+ return idx;
+ }
pcam_inst = pmctl->sync.pcam_sync->dev_inst[idx];
if (!pcam_inst->streamon) {
D("%s: stream 0x%p is off\n", __func__, pcam_inst);
@@ -700,6 +730,10 @@
idx = msm_mctl_out_type_to_inst_index(pmctl->sync.pcam_sync,
msg_type);
+ if (idx < 0) {
+ pr_err("%s Invalid instance, cant delete buffer\n", __func__);
+ return idx;
+ }
pcam_inst = pmctl->sync.pcam_sync->dev_inst[idx];
D("%s: idx = %d, pinst=0x%p", __func__, idx, pcam_inst);
spin_lock_irqsave(&pcam_inst->vq_irqlock, flags);
diff --git a/drivers/media/video/msm/msm_mctl_pp.c b/drivers/media/video/msm/msm_mctl_pp.c
index a09514b..2bf95a0 100644
--- a/drivers/media/video/msm/msm_mctl_pp.c
+++ b/drivers/media/video/msm/msm_mctl_pp.c
@@ -126,6 +126,10 @@
idx = msm_mctl_out_type_to_inst_index(
p_mctl->sync.pcam_sync, msg_type);
+ if (idx < 0) {
+ pr_err("%s Invalid instance. returning\n", __func__);
+ return -EINVAL;
+ }
pcam_inst = p_mctl->sync.pcam_sync->dev_inst[idx];
vb = msm_mctl_buf_find(p_mctl, pcam_inst,
del_buf, msg_type, fbuf);
@@ -192,27 +196,52 @@
}
static int msm_mctl_pp_get_phy_addr(
+ struct msm_cam_v4l2_dev_inst *pcam_inst,
uint32_t frame_handle,
struct msm_pp_frame *pp_frame)
{
struct msm_frame_buffer *vb = NULL;
struct videobuf2_contig_pmem *mem;
+ int i, buf_idx = 0;
vb = (struct msm_frame_buffer *)frame_handle;
- mem = vb2_plane_cookie(&vb->vidbuf, 0);
+ buf_idx = vb->vidbuf.v4l2_buf.index;
memset(pp_frame, 0, sizeof(struct msm_pp_frame));
pp_frame->handle = (uint32_t)vb;
pp_frame->frame_id = vb->vidbuf.v4l2_buf.sequence;
- pp_frame->image_type = (unsigned short)mem->path;
pp_frame->timestamp = vb->vidbuf.v4l2_buf.timestamp;
- /* hard coded for now. Will need to expand to MP case */
- pp_frame->num_planes = 1;
- pp_frame->sp.addr_offset = mem->addr_offset;
- pp_frame->sp.phy_addr = videobuf2_to_pmem_contig(&vb->vidbuf, 0);
- pp_frame->sp.y_off = 0;
- pp_frame->sp.cbcr_off = mem->offset.sp_off.cbcr_off;
- pp_frame->sp.length = mem->size;
- pp_frame->sp.fd = (int)mem->vaddr;
+ /* Get the cookie for 1st plane and store the path.
+ * Also use this to check the number of planes in
+ * this buffer.*/
+ mem = vb2_plane_cookie(&vb->vidbuf, 0);
+ pp_frame->image_type = (unsigned short)mem->path;
+ if (mem->buffer_type == VIDEOBUF2_SINGLE_PLANE) {
+ pp_frame->num_planes = 1;
+ pp_frame->sp.addr_offset = mem->addr_offset;
+ pp_frame->sp.phy_addr =
+ videobuf2_to_pmem_contig(&vb->vidbuf, 0);
+ pp_frame->sp.y_off = 0;
+ pp_frame->sp.cbcr_off = mem->offset.sp_off.cbcr_off;
+ pp_frame->sp.length = mem->size;
+ pp_frame->sp.fd = (int)mem->vaddr;
+ } else {
+ pp_frame->num_planes = pcam_inst->plane_info.num_planes;
+ for (i = 0; i < pp_frame->num_planes; i++) {
+ mem = vb2_plane_cookie(&vb->vidbuf, i);
+ pp_frame->mp[i].addr_offset = mem->addr_offset;
+ pp_frame->mp[i].phy_addr =
+ videobuf2_to_pmem_contig(&vb->vidbuf, i);
+ pp_frame->mp[i].data_offset =
+ pcam_inst->buf_offset[buf_idx][i].data_offset;
+ pp_frame->mp[i].fd = (int)mem->vaddr;
+ pp_frame->mp[i].length = mem->size;
+ D("%s frame id %d buffer %d plane %d phy addr 0x%x"
+ " fd %d length %d\n", __func__,
+ pp_frame->frame_id, buf_idx, i,
+ (uint32_t)pp_frame->mp[i].phy_addr,
+ pp_frame->mp[i].fd, pp_frame->mp[i].length);
+ }
+ }
return 0;
}
@@ -235,12 +264,38 @@
return 0;
}
+static int msm_mctl_pp_path_to_inst_index(struct msm_cam_v4l2_device *pcam,
+ int out_type)
+{
+ int image_mode;
+ switch (out_type) {
+ case OUTPUT_TYPE_P:
+ image_mode = MSM_V4L2_EXT_CAPTURE_MODE_PREVIEW;
+ break;
+ case OUTPUT_TYPE_V:
+ image_mode = MSM_V4L2_EXT_CAPTURE_MODE_VIDEO;
+ break;
+ case OUTPUT_TYPE_S:
+ image_mode = MSM_V4L2_EXT_CAPTURE_MODE_MAIN;
+ break;
+ default:
+ image_mode = -1;
+ break;
+ }
+ if ((image_mode >= 0) && pcam->dev_inst_map[image_mode])
+ return pcam->dev_inst_map[image_mode]->my_index;
+ else
+ return -EINVAL;
+}
+
int msm_mctl_pp_proc_vpe_cmd(
struct msm_cam_media_controller *p_mctl,
struct msm_mctl_pp_cmd *pp_cmd)
{
- int rc = 0;
+ int rc = 0, idx;
void __user *argp = (void __user *)pp_cmd->value;
+ struct msm_cam_v4l2_dev_inst *pcam_inst;
+
switch (pp_cmd->id) {
case VPE_CMD_INIT:
case VPE_CMD_DEINIT:
@@ -422,15 +477,27 @@
zoom->pp_frame_cmd.cookie,
zoom->pp_frame_cmd.vpe_output_action,
zoom->pp_frame_cmd.path);
-
+ idx = msm_mctl_pp_path_to_inst_index(p_mctl->sync.pcam_sync,
+ zoom->pp_frame_cmd.path);
+ if (idx < 0) {
+ pr_err("%s Invalid path, returning\n", __func__);
+ kfree(zoom);
+ return idx;
+ }
+ pcam_inst = p_mctl->sync.pcam_sync->dev_inst[idx];
+ if (!pcam_inst) {
+ pr_err("%s Invalid instance, returning\n", __func__);
+ kfree(zoom);
+ return -EINVAL;
+ }
zoom->user_cmd = pp_cmd->id;
- rc = msm_mctl_pp_get_phy_addr(
+ rc = msm_mctl_pp_get_phy_addr(pcam_inst,
zoom->pp_frame_cmd.src_buf_handle, &zoom->src_frame);
if (rc) {
kfree(zoom);
break;
}
- rc = msm_mctl_pp_get_phy_addr(
+ rc = msm_mctl_pp_get_phy_addr(pcam_inst,
zoom->pp_frame_cmd.dest_buf_handle, &zoom->dest_frame);
if (rc) {
kfree(zoom);
diff --git a/drivers/media/video/msm/msm_vfe32.c b/drivers/media/video/msm/msm_vfe32.c
index 219e504..5c02f85 100644
--- a/drivers/media/video/msm/msm_vfe32.c
+++ b/drivers/media/video/msm/msm_vfe32.c
@@ -454,7 +454,7 @@
break;
case OUTPUT_1_2_AND_3:
- CDBG("%s: OUTPUT_1_2_AND_3", __func__);
+ CDBG("%s: OUTPUT_ZSL", __func__);
/* use wm0& 4 for postview, wm1&5 for preview.*/
/* use wm2& 6 for main img */
vfe32_ctrl->outpath.output_mode |=
@@ -478,6 +478,23 @@
vfe32_ctrl->outpath.out1.ch0 = 0; /* raw */
vfe32_ctrl->outpath.output_mode |= VFE32_OUTPUT_MODE_S;
break;
+ case OUTPUT_ALL_CHNLS:
+ /* YV12 preview */
+ vfe32_ctrl->outpath.output_mode |=
+ VFE32_OUTPUT_MODE_P_ALL_CHNLS;
+ /* video */
+ vfe32_ctrl->outpath.output_mode |=
+ VFE32_OUTPUT_MODE_V;
+ break;
+ case OUTPUT_ZSL_ALL_CHNLS:
+ CDBG("%s: OUTPUT_ZSL_ALL_CHNLS", __func__);
+ vfe32_ctrl->outpath.output_mode |=
+ VFE32_OUTPUT_MODE_S; /* main image.*/
+ vfe32_ctrl->outpath.output_mode |=
+ VFE32_OUTPUT_MODE_P_ALL_CHNLS; /* preview. */
+ vfe32_ctrl->outpath.output_mode |=
+ VFE32_OUTPUT_MODE_T; /* thumbnail. */
+ break;
default:
break;
}
@@ -678,7 +695,7 @@
msm_io_w(VFE_IMASK_WHILE_STOPPING_1,
vfe32_ctrl->vfebase + VFE_IRQ_MASK_1);
- msm_io_dump(vfe32_ctrl->vfebase, 0x7B4);
+ msm_io_dump(vfe32_ctrl->vfebase, vfe32_ctrl->register_total * 4);
/* Ensure the write order while writing
to the command register using the barrier */
@@ -725,6 +742,12 @@
irq_comp_mask |=
((0x1 << (vfe32_ctrl->outpath.out0.ch0)) |
(0x1 << (vfe32_ctrl->outpath.out0.ch1)));
+ } else if (vfe32_ctrl->outpath.output_mode &
+ VFE32_OUTPUT_MODE_P_ALL_CHNLS) {
+ pr_debug("%s Enabling all channels ", __func__);
+ irq_comp_mask |= (0x1 << vfe32_ctrl->outpath.out0.ch0 |
+ 0x1 << vfe32_ctrl->outpath.out0.ch1 |
+ 0x1 << vfe32_ctrl->outpath.out0.ch2);
}
if (vfe32_ctrl->outpath.output_mode & VFE32_OUTPUT_MODE_T) {
irq_comp_mask |=
@@ -741,6 +764,14 @@
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch0]);
msm_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch1]);
+ } else if (vfe32_ctrl->outpath.output_mode &
+ VFE32_OUTPUT_MODE_P_ALL_CHNLS) {
+ msm_io_w(1, vfe32_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch0]);
+ msm_io_w(1, vfe32_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch1]);
+ msm_io_w(1, vfe32_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch2]);
}
if (vfe32_ctrl->outpath.output_mode & VFE32_OUTPUT_MODE_T) {
msm_io_w(1, vfe32_ctrl->vfebase +
@@ -839,6 +870,12 @@
if (vfe32_ctrl->outpath.output_mode & VFE32_OUTPUT_MODE_PT) {
irq_comp_mask |= (0x1 << vfe32_ctrl->outpath.out0.ch0 |
0x1 << vfe32_ctrl->outpath.out0.ch1);
+ } else if (vfe32_ctrl->outpath.output_mode &
+ VFE32_OUTPUT_MODE_P_ALL_CHNLS) {
+ pr_debug("%s Enabling all channels ", __func__);
+ irq_comp_mask |= (0x1 << vfe32_ctrl->outpath.out0.ch0 |
+ 0x1 << vfe32_ctrl->outpath.out0.ch1 |
+ 0x1 << vfe32_ctrl->outpath.out0.ch2);
}
if (vfe32_ctrl->outpath.output_mode & VFE32_OUTPUT_MODE_V) {
@@ -853,6 +890,14 @@
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch0]);
msm_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch1]);
+ } else if (vfe32_ctrl->outpath.output_mode &
+ VFE32_OUTPUT_MODE_P_ALL_CHNLS) {
+ msm_io_w(1, vfe32_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch0]);
+ msm_io_w(1, vfe32_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch1]);
+ msm_io_w(1, vfe32_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch2]);
}
msm_camio_set_perf_lvl(S_PREVIEW);
vfe32_start_common();
@@ -986,7 +1031,6 @@
int i;
uint32_t value, value1, value2;
vfe32_program_dmi_cfg(channel_sel);
- /* for loop for extracting init table. */
for (i = 0 ; i < (VFE32_GAMMA_NUM_ENTRIES/2) ; i++) {
value = *tbl++;
value1 = value & 0x0000FFFF;
@@ -997,6 +1041,20 @@
vfe32_program_dmi_cfg(NO_MEM_SELECTED);
}
+static void vfe32_read_gamma_cfg(enum VFE32_DMI_RAM_SEL channel_sel,
+ uint32_t *tbl)
+{
+ int i;
+ vfe32_program_dmi_cfg(channel_sel);
+ CDBG("%s: Gamma table channel: %d\n", __func__, channel_sel);
+ for (i = 0 ; i < VFE32_GAMMA_NUM_ENTRIES ; i++) {
+ *tbl = msm_io_r(vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ CDBG("%s: %08x\n", __func__, *tbl);
+ tbl++;
+ }
+ vfe32_program_dmi_cfg(NO_MEM_SELECTED);
+}
+
static void vfe32_write_la_cfg(enum VFE32_DMI_RAM_SEL channel_sel,
const uint32_t *tbl)
{
@@ -1004,7 +1062,6 @@
uint32_t value, value1, value2;
vfe32_program_dmi_cfg(channel_sel);
- /* for loop for extracting init table. */
for (i = 0 ; i < (VFE32_LA_TABLE_LENGTH/2) ; i++) {
value = *tbl++;
value1 = value & 0x0000FFFF;
@@ -1196,23 +1253,6 @@
}
rc = vfe32_capture(snapshot_cnt);
break;
- case VFE_CMD_GET_HW_VERSION:
- if (cmd->length != V32_GET_HW_VERSION_LEN) {
- rc = -EINVAL;
- goto proc_general_done;
- }
- cmdp = kmalloc(V32_GET_HW_VERSION_LEN, GFP_ATOMIC);
- if (!cmdp) {
- rc = -ENOMEM;
- goto proc_general_done;
- }
- *cmdp = msm_io_r(vfe32_ctrl->vfebase+V32_GET_HW_VERSION_OFF);
- if (copy_to_user((void __user *)(cmd->value), cmdp,
- V32_GET_HW_VERSION_LEN)) {
- rc = -EFAULT;
- goto proc_general_done;
- }
- break;
case VFE_CMD_START_RECORDING:
pr_info("vfe32_proc_general: cmdID = %s\n",
vfe32_general_cmd[cmd->id]);
@@ -1342,12 +1382,6 @@
rc = -EFAULT;
goto proc_general_done;
}
- /*
- old_val = msm_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
- old_val |= RS_ENABLE_MASK;
- msm_io_w(old_val,
- vfe32_ctrl->vfebase + VFE_MODULE_CFG);
- */
msm_io_memcpy(vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
cmdp, (vfe32_cmd[cmd->id].length));
}
@@ -1365,12 +1399,6 @@
rc = -EFAULT;
goto proc_general_done;
}
- /*
- old_val = msm_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
- old_val |= CS_ENABLE_MASK;
- msm_io_w(old_val,
- vfe32_ctrl->vfebase + VFE_MODULE_CFG);
- */
msm_io_memcpy(vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
cmdp, (vfe32_cmd[cmd->id].length));
}
@@ -1453,6 +1481,44 @@
}
break;
+ case VFE_CMD_GET_MESH_ROLLOFF_TABLE:
+ temp1 = sizeof(uint32_t) * ((V32_MESH_ROLL_OFF_INIT_TABLE_SIZE *
+ 2) + (V32_MESH_ROLL_OFF_DELTA_TABLE_SIZE * 2));
+ if (cmd->length != temp1) {
+ rc = -EINVAL;
+ goto proc_general_done;
+ }
+ cmdp = kzalloc(temp1, GFP_KERNEL);
+ if (!cmdp) {
+ rc = -ENOMEM;
+ goto proc_general_done;
+ }
+ cmdp_local = cmdp;
+ vfe32_program_dmi_cfg(ROLLOFF_RAM0_BANK0);
+ CDBG("%s: Mesh Rolloff init Table\n", __func__);
+ for (i = 0; i < (V32_MESH_ROLL_OFF_INIT_TABLE_SIZE * 2); i++) {
+ *cmdp_local =
+ msm_io_r(vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ CDBG("%s: %08x\n", __func__, *cmdp_local);
+ cmdp_local++;
+ }
+ msm_io_w(V32_MESH_ROLL_OFF_DELTA_TABLE_OFFSET,
+ vfe32_ctrl->vfebase + VFE_DMI_ADDR);
+ CDBG("%s: Mesh Rolloff Delta Table\n", __func__);
+ for (i = 0; i < (V32_MESH_ROLL_OFF_DELTA_TABLE_SIZE * 2); i++) {
+ *cmdp_local =
+ msm_io_r(vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ CDBG("%s: %08x\n", __func__, *cmdp_local);
+ cmdp_local++;
+ }
+ CDBG("done reading delta table\n");
+ vfe32_program_dmi_cfg(NO_MEM_SELECTED);
+ if (copy_to_user((void __user *)(cmd->value), cmdp,
+ temp1)) {
+ rc = -EFAULT;
+ goto proc_general_done;
+ }
+ break;
case VFE_CMD_LA_CFG:
cmdp = kmalloc(cmd->length, GFP_ATOMIC);
if (!cmdp) {
@@ -1500,6 +1566,36 @@
vfe32_ctrl->update_la = true;
break;
+ case VFE_CMD_GET_LA_TABLE:
+ temp1 = sizeof(uint32_t) * VFE32_LA_TABLE_LENGTH / 2;
+ if (cmd->length != temp1) {
+ rc = -EINVAL;
+ goto proc_general_done;
+ }
+ cmdp = kzalloc(temp1, GFP_KERNEL);
+ if (!cmdp) {
+ rc = -ENOMEM;
+ goto proc_general_done;
+ }
+ cmdp_local = cmdp;
+ if (msm_io_r(vfe32_ctrl->vfebase + V32_LA_OFF))
+ vfe32_program_dmi_cfg(LUMA_ADAPT_LUT_RAM_BANK1);
+ else
+ vfe32_program_dmi_cfg(LUMA_ADAPT_LUT_RAM_BANK0);
+ for (i = 0 ; i < (VFE32_LA_TABLE_LENGTH / 2) ; i++) {
+ *cmdp_local =
+ msm_io_r(vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ *cmdp_local |= (msm_io_r(vfe32_ctrl->vfebase +
+ VFE_DMI_DATA_LO)) << 16;
+ cmdp_local++;
+ }
+ vfe32_program_dmi_cfg(NO_MEM_SELECTED);
+ if (copy_to_user((void __user *)(cmd->value), cmdp,
+ temp1)) {
+ rc = -EFAULT;
+ goto proc_general_done;
+ }
+ break;
case VFE_CMD_SK_ENHAN_CFG:
case VFE_CMD_SK_ENHAN_UPDATE:{
cmdp = kmalloc(cmd->length, GFP_ATOMIC);
@@ -1542,7 +1638,7 @@
cmdp_local = cmdp + 17;
vfe32_write_linear_cfg(BLACK_LUT_RAM_BANK0, cmdp_local);
- break;
+ break;
case VFE_CMD_LINEARIZATION_UPDATE:
cmdp = kmalloc(cmd->length, GFP_ATOMIC);
@@ -1572,8 +1668,38 @@
else
vfe32_write_linear_cfg(BLACK_LUT_RAM_BANK1, cmdp_local);
vfe32_ctrl->update_linear = true;
- break;
+ break;
+ case VFE_CMD_GET_LINEARIZATON_TABLE:
+ temp1 = sizeof(uint32_t) * VFE32_LINEARIZATON_TABLE_LENGTH;
+ if (cmd->length != temp1) {
+ rc = -EINVAL;
+ goto proc_general_done;
+ }
+ cmdp = kzalloc(temp1, GFP_KERNEL);
+ if (!cmdp) {
+ rc = -ENOMEM;
+ goto proc_general_done;
+ }
+ cmdp_local = cmdp;
+ if (msm_io_r(vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF1))
+ vfe32_program_dmi_cfg(BLACK_LUT_RAM_BANK1);
+ else
+ vfe32_program_dmi_cfg(BLACK_LUT_RAM_BANK0);
+ CDBG("%s: Linearization Table\n", __func__);
+ for (i = 0 ; i < VFE32_LINEARIZATON_TABLE_LENGTH ; i++) {
+ *cmdp_local =
+ msm_io_r(vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ CDBG("%s: %08x\n", __func__, *cmdp_local);
+ cmdp_local++;
+ }
+ vfe32_program_dmi_cfg(NO_MEM_SELECTED);
+ if (copy_to_user((void __user *)(cmd->value), cmdp,
+ temp1)) {
+ rc = -EFAULT;
+ goto proc_general_done;
+ }
+ break;
case VFE_CMD_DEMOSAICV3:
if (cmd->length !=
V32_DEMOSAICV3_0_LEN+V32_DEMOSAICV3_1_LEN) {
@@ -1592,6 +1718,12 @@
goto proc_general_done;
}
cmdp_local = cmdp;
+ new_val = *cmdp_local;
+
+ old_val = msm_io_r(vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF);
+ old_val &= DEMOSAIC_MASK;
+ new_val = new_val | old_val;
+ *cmdp_local = new_val;
msm_io_memcpy(vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF,
cmdp_local, V32_DEMOSAICV3_0_LEN);
@@ -1600,6 +1732,45 @@
cmdp_local, V32_DEMOSAICV3_1_LEN);
break;
+ case VFE_CMD_DEMOSAICV3_UPDATE:
+ if (cmd->length !=
+ V32_DEMOSAICV3_0_LEN * V32_DEMOSAICV3_UP_REG_CNT) {
+ rc = -EFAULT;
+ goto proc_general_done;
+ }
+ cmdp = kmalloc(cmd->length, GFP_ATOMIC);
+ if (!cmdp) {
+ rc = -ENOMEM;
+ goto proc_general_done;
+ }
+ if (copy_from_user(cmdp,
+ (void __user *)(cmd->value),
+ cmd->length)) {
+ rc = -EFAULT;
+ goto proc_general_done;
+ }
+ cmdp_local = cmdp;
+ new_val = *cmdp_local;
+
+ old_val = msm_io_r(vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF);
+ old_val &= DEMOSAIC_MASK;
+ new_val = new_val | old_val;
+ *cmdp_local = new_val;
+
+ msm_io_memcpy(vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF,
+ cmdp_local, V32_DEMOSAICV3_0_LEN);
+ /* As the address space is not contiguous increment by 2
+ * before copying to next address space */
+ cmdp_local += 1;
+ msm_io_memcpy(vfe32_ctrl->vfebase + V32_DEMOSAICV3_1_OFF,
+ cmdp_local, 2 * V32_DEMOSAICV3_0_LEN);
+ /* As the address space is not contiguous increment by 2
+ * before copying to next address space */
+ cmdp_local += 2;
+ msm_io_memcpy(vfe32_ctrl->vfebase + V32_DEMOSAICV3_2_OFF,
+ cmdp_local, 2 * V32_DEMOSAICV3_0_LEN);
+ break;
+
case VFE_CMD_DEMOSAICV3_ABCC_CFG:
rc = -EFAULT;
break;
@@ -1755,6 +1926,34 @@
cmdp -= 1;
break;
+ case VFE_CMD_GET_RGB_G_TABLE:
+ temp1 = sizeof(uint32_t) * VFE32_GAMMA_NUM_ENTRIES * 3;
+ if (cmd->length != temp1) {
+ rc = -EINVAL;
+ goto proc_general_done;
+ }
+ cmdp = kzalloc(temp1, GFP_KERNEL);
+ if (!cmdp) {
+ rc = -ENOMEM;
+ goto proc_general_done;
+ }
+ cmdp_local = cmdp;
+
+ old_val = msm_io_r(vfe32_ctrl->vfebase + V32_RGB_G_OFF);
+ temp2 = old_val ? RGBLUT_RAM_CH0_BANK1 :
+ RGBLUT_RAM_CH0_BANK0;
+ for (i = 0; i < 3; i++) {
+ vfe32_read_gamma_cfg(temp2,
+ cmdp_local + (VFE32_GAMMA_NUM_ENTRIES * i));
+ temp2 += 2;
+ }
+ if (copy_to_user((void __user *)(cmd->value), cmdp,
+ temp1)) {
+ rc = -EFAULT;
+ goto proc_general_done;
+ }
+ break;
+
case VFE_CMD_STATS_AWB_STOP: {
old_val = msm_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~AWB_ENABLE_MASK;
@@ -1947,9 +2146,9 @@
CDBG("%s: start writing RollOff Ram0 table\n", __func__);
if (temp2)
- vfe32_program_dmi_cfg(ROLLOFF_RAM0_BANK0);
- else
vfe32_program_dmi_cfg(ROLLOFF_RAM0_BANK1);
+ else
+ vfe32_program_dmi_cfg(ROLLOFF_RAM0_BANK0);
msm_io_w(temp1, vfe32_ctrl->vfebase + VFE_DMI_ADDR);
for (i = 0 ; i < V33_PCA_ROLL_OFF_TABLE_SIZE ; i++) {
@@ -1963,9 +2162,9 @@
CDBG("%s: start writing RollOff Ram1 table\n", __func__);
if (temp2)
- vfe32_program_dmi_cfg(ROLLOFF_RAM1_BANK0);
- else
vfe32_program_dmi_cfg(ROLLOFF_RAM1_BANK1);
+ else
+ vfe32_program_dmi_cfg(ROLLOFF_RAM1_BANK0);
msm_io_w(temp1, vfe32_ctrl->vfebase + VFE_DMI_ADDR);
for (i = 0 ; i < V33_PCA_ROLL_OFF_TABLE_SIZE ; i++) {
@@ -1978,7 +2177,88 @@
vfe32_program_dmi_cfg(NO_MEM_SELECTED);
vfe32_ctrl->update_rolloff = true;
break;
+ case VFE_CMD_GET_PCA_ROLLOFF_TABLE:
+ temp1 = sizeof(uint64_t) * V33_PCA_ROLL_OFF_TABLE_SIZE * 2;
+ if (cmd->length != temp1) {
+ rc = -EINVAL;
+ goto proc_general_done;
+ }
+ cmdp = kzalloc(temp1, GFP_KERNEL);
+ if (!cmdp) {
+ rc = -ENOMEM;
+ goto proc_general_done;
+ }
+ cmdp_local = cmdp;
+ old_val = msm_io_r(vfe32_ctrl->vfebase +
+ V33_PCA_ROLL_OFF_CFG_OFF1) &
+ V33_PCA_ROLL_OFF_LUT_BANK_SEL_MASK;
+ if (old_val)
+ vfe32_program_dmi_cfg(ROLLOFF_RAM0_BANK1);
+ else
+ vfe32_program_dmi_cfg(ROLLOFF_RAM0_BANK0);
+
+ CDBG("%s: PCA Rolloff Ram0\n", __func__);
+ for (i = 0 ; i < V33_PCA_ROLL_OFF_TABLE_SIZE * 2; i++) {
+ temp2 = (i == (V33_PCA_ROLL_OFF_TABLE_SIZE - 1));
+ if (old_val && temp2)
+ vfe32_program_dmi_cfg(ROLLOFF_RAM1_BANK1);
+ else if (!old_val && temp2)
+ vfe32_program_dmi_cfg(ROLLOFF_RAM1_BANK0);
+
+ *(cmdp_local + 1) =
+ msm_io_r(vfe32_ctrl->vfebase +
+ VFE33_DMI_DATA_HI);
+ *cmdp_local = msm_io_r(vfe32_ctrl->vfebase +
+ VFE33_DMI_DATA_LO);
+ CDBG("%s: %08x%08x\n", __func__,
+ *(cmdp_local + 1), *cmdp_local);
+ cmdp_local += 2;
+ }
+ vfe32_program_dmi_cfg(NO_MEM_SELECTED);
+ if (copy_to_user((void __user *)(cmd->value), cmdp,
+ temp1)) {
+ rc = -EFAULT;
+ goto proc_general_done;
+ }
+ break;
+ case VFE_CMD_GET_HW_VERSION:
+ if (cmd->length != V32_GET_HW_VERSION_LEN) {
+ rc = -EINVAL;
+ goto proc_general_done;
+ }
+ cmdp = kmalloc(V32_GET_HW_VERSION_LEN, GFP_ATOMIC);
+ if (!cmdp) {
+ rc = -ENOMEM;
+ goto proc_general_done;
+ }
+ *cmdp = msm_io_r(vfe32_ctrl->vfebase+V32_GET_HW_VERSION_OFF);
+ if (copy_to_user((void __user *)(cmd->value), cmdp,
+ V32_GET_HW_VERSION_LEN)) {
+ rc = -EFAULT;
+ goto proc_general_done;
+ }
+ break;
+ case VFE_CMD_GET_REG_DUMP:
+ temp1 = sizeof(uint32_t) * vfe32_ctrl->register_total;
+ if (cmd->length != temp1) {
+ rc = -EINVAL;
+ goto proc_general_done;
+ }
+ cmdp = kmalloc(temp1, GFP_ATOMIC);
+ if (!cmdp) {
+ rc = -ENOMEM;
+ goto proc_general_done;
+ }
+ msm_io_dump(vfe32_ctrl->vfebase, vfe32_ctrl->register_total*4);
+ CDBG("%s: %p %p %d\n", __func__, (void *)cmdp,
+ vfe32_ctrl->vfebase, temp1);
+ memcpy_fromio((void *)cmdp, vfe32_ctrl->vfebase, temp1);
+ if (copy_to_user((void __user *)(cmd->value), cmdp, temp1)) {
+ rc = -EFAULT;
+ goto proc_general_done;
+ }
+ break;
default:
if (cmd->length != vfe32_cmd[cmd->id].length)
return -EINVAL;
@@ -3309,6 +3589,27 @@
}
break;
+ case CMD_AXI_CFG_ZSL_ALL_CHNLS: {
+ uint32_t *axio = NULL;
+ CDBG("%s, CMD_AXI_CFG_ZSL\n", __func__);
+ axio = kmalloc(vfe32_cmd[VFE_CMD_AXI_OUT_CFG].length,
+ GFP_ATOMIC);
+ if (!axio) {
+ rc = -ENOMEM;
+ break;
+ }
+
+ if (copy_from_user(axio, (void __user *)(vfecmd.value),
+ vfe32_cmd[VFE_CMD_AXI_OUT_CFG].length)) {
+ kfree(axio);
+ rc = -EFAULT;
+ break;
+ }
+ vfe32_config_axi(OUTPUT_ZSL_ALL_CHNLS, axio);
+ kfree(axio);
+ }
+ break;
+
case CMD_AXI_CFG_VIDEO: {
uint32_t *axio = NULL;
axio = kmalloc(vfe32_cmd[VFE_CMD_AXI_OUT_CFG].length,
@@ -3328,6 +3629,26 @@
kfree(axio);
}
break;
+
+ case CMD_AXI_CFG_VIDEO_ALL_CHNLS: {
+ uint32_t *axio = NULL;
+ axio = kmalloc(vfe32_cmd[VFE_CMD_AXI_OUT_CFG].length,
+ GFP_ATOMIC);
+ if (!axio) {
+ rc = -ENOMEM;
+ break;
+ }
+
+ if (copy_from_user(axio, (void __user *)(vfecmd.value),
+ vfe32_cmd[VFE_CMD_AXI_OUT_CFG].length)) {
+ kfree(axio);
+ rc = -EFAULT;
+ break;
+ }
+ vfe32_config_axi(OUTPUT_ALL_CHNLS, axio);
+ kfree(axio);
+ }
+ break;
default:
break;
}
@@ -3371,6 +3692,12 @@
msm_camio_set_perf_lvl(S_INIT);
msm_camio_set_perf_lvl(S_PREVIEW);
+ if (msm_io_r(vfe32_ctrl->vfebase + V32_GET_HW_VERSION_OFF) ==
+ VFE32_HW_NUMBER)
+ vfe32_ctrl->register_total = VFE32_REGISTER_TOTAL;
+ else
+ vfe32_ctrl->register_total = VFE33_REGISTER_TOTAL;
+
/* TO DO: Need to release the VFE resources */
rc = request_irq(vfe32_ctrl->vfeirq, vfe32_parse_irq,
IRQF_TRIGGER_RISING, "vfe", 0);
diff --git a/drivers/media/video/msm/msm_vfe32.h b/drivers/media/video/msm/msm_vfe32.h
index d763c2e..a01d910 100644
--- a/drivers/media/video/msm/msm_vfe32.h
+++ b/drivers/media/video/msm/msm_vfe32.h
@@ -16,6 +16,15 @@
#define TRUE 1
#define FALSE 0
+#define VFE32_HW_NUMBER 0x3030B
+#define VFE33_HW_NUMBER 0x30408
+
+/* This defines total number registers in VFE.
+ * Each register is 4 bytes so to get the range,
+ * multiply this number with 4. */
+#define VFE32_REGISTER_TOTAL 0x000001CD
+#define VFE33_REGISTER_TOTAL 0x000001EE
+
/* at start of camif, bit 1:0 = 0x01:enable
* image data capture at frame boundary. */
#define CAMIF_COMMAND_START 0x00000005
@@ -131,6 +140,9 @@
/* For DBPC bit 1 is set to zero and other's 1 */
#define DBCC_MASK 0xFFFFFFFD
+/* For DBPC/ABF/DBCC/ABCC bits are set to 1 all others 0 */
+#define DEMOSAIC_MASK 0xF
+
/* For MCE enable bit 28 set to zero and other's 1 */
#define MCE_EN_MASK 0xEFFFFFFF
@@ -202,6 +214,8 @@
#define V32_DEMOSAICV3_0_LEN 4
#define V32_DEMOSAICV3_1_OFF 0x0000061C
#define V32_DEMOSAICV3_1_LEN 88
+#define V32_DEMOSAICV3_2_OFF 0x0000066C
+#define V32_DEMOSAICV3_UP_REG_CNT 5
/* BPC */
#define V32_DEMOSAIC_2_OFF 0x0000029C
#define V32_DEMOSAIC_2_LEN 8
@@ -862,6 +876,7 @@
#define VFE32_OUTPUT_MODE_V (0x1 << 2)
#define VFE32_OUTPUT_MODE_P (0x1 << 3)
#define VFE32_OUTPUT_MODE_T (0x1 << 4)
+#define VFE32_OUTPUT_MODE_P_ALL_CHNLS (0x1 << 5)
struct vfe_stats_control {
uint8_t ackPending;
@@ -903,6 +918,7 @@
int vfeirq;
void __iomem *vfebase;
void *syncdata;
+ uint32_t register_total;
struct resource *vfemem;
struct resource *vfeio;
diff --git a/drivers/media/video/msm/msm_vfe7x27a.c b/drivers/media/video/msm/msm_vfe7x27a.c
index c8bfacc..9f7dff7 100644
--- a/drivers/media/video/msm/msm_vfe7x27a.c
+++ b/drivers/media/video/msm/msm_vfe7x27a.c
@@ -287,8 +287,7 @@
kfree(extdata);
extlen = 0;
- /* set back the AXI frequency to default */
- /* TODO msm_camio_set_perf_lvl(S_DEFAULT); */
+ msm_camio_set_perf_lvl(S_EXIT);
}
static int vfe_7x_init(struct msm_vfe_callback *presp,
diff --git a/drivers/media/video/msm/ov5640.c b/drivers/media/video/msm/ov5640.c
new file mode 100644
index 0000000..1380bcf
--- /dev/null
+++ b/drivers/media/video/msm/ov5640.c
@@ -0,0 +1,1477 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* #define DEBUG */
+
+#include <linux/delay.h>
+#include <linux/types.h>
+#include <linux/i2c.h>
+#include <linux/uaccess.h>
+#include <linux/miscdevice.h>
+#include <linux/leds.h>
+#include <linux/slab.h>
+#include <media/msm_camera.h>
+#include <mach/gpio.h>
+#include <mach/camera.h>
+#include "ov5640.h"
+
+#define FALSE 0
+#define TRUE 1
+
+struct ov5640_work {
+ struct work_struct work;
+};
+
+struct __ov5640_ctrl {
+ const struct msm_camera_sensor_info *sensordata;
+ int sensormode;
+ uint fps_divider; /* init to 1 * 0x00000400 */
+ uint pict_fps_divider; /* init to 1 * 0x00000400 */
+ u16 curr_step_pos;
+ u16 curr_lens_pos;
+ u16 init_curr_lens_pos;
+ u16 my_reg_gain;
+ u16 my_reg_line_count;
+ enum msm_s_resolution prev_res;
+ enum msm_s_resolution pict_res;
+ enum msm_s_resolution curr_res;
+ enum msm_s_test_mode set_test;
+};
+
+static DECLARE_WAIT_QUEUE_HEAD(ov5640_wait_queue);
+DEFINE_MUTEX(ov5640_mutex);
+
+static int ov5640_pwdn_gpio;
+static int ov5640_reset_gpio;
+static int ov5640_driver_pwdn_gpio;
+static int OV5640_CSI_CONFIG;
+static struct ov5640_work *ov5640_sensorw;
+static struct i2c_client *ov5640_client;
+static u8 ov5640_i2c_buf[4];
+static u8 ov5640_counter;
+static int16_t ov5640_effect;
+static int is_autoflash;
+static int effect_value;
+unsigned int ov5640_SAT_U = 0x40;
+unsigned int ov5640_SAT_V = 0x40;
+
+static struct __ov5640_ctrl *ov5640_ctrl;
+static int ov5640_afinit = 1;
+
+struct rw_semaphore ov_leds_list_lock;
+struct list_head ov_leds_list;
+
+static int ov5640_i2c_remove(struct i2c_client *client);
+static int ov5640_i2c_probe(struct i2c_client *client,
+ const struct i2c_device_id *id);
+
+static int ov5640_i2c_txdata(u16 saddr, u8 *txdata, int length)
+{
+ struct i2c_msg msg[] = {
+ {
+ .addr = saddr,
+ .flags = 0,
+ .len = length,
+ .buf = txdata,
+ },
+ };
+
+ if (i2c_transfer(ov5640_client->adapter, msg, 1) < 0)
+ return -EIO;
+ else
+ return 0;
+}
+
+static int ov5640_i2c_write(unsigned short saddr, unsigned int waddr,
+ unsigned short bdata, u8 trytimes)
+{
+ int rc = -EIO;
+
+ ov5640_counter = 0;
+ ov5640_i2c_buf[0] = (waddr & 0xFF00) >> 8;
+ ov5640_i2c_buf[1] = (waddr & 0x00FF);
+ ov5640_i2c_buf[2] = (bdata & 0x00FF);
+
+ while ((ov5640_counter < trytimes) && (rc != 0)) {
+ rc = ov5640_i2c_txdata(saddr, ov5640_i2c_buf, 3);
+
+ if (rc < 0) {
+ ov5640_counter++;
+ CDBG("***--CAMERA i2c_write_w failed,i2c addr=0x%x,"
+ "command addr = 0x%x, val = 0x%x,s=%d,"
+ "rc=%d!\n", saddr, waddr, bdata,
+ ov5640_counter, rc);
+ msleep(20);
+ }
+ }
+ return rc;
+}
+
+static int ov5640_i2c_rxdata(unsigned short saddr, unsigned char *rxdata,
+ int length)
+{
+ struct i2c_msg msgs[] = {
+ {
+ .addr = saddr,
+ .flags = 0,
+ .len = 2,
+ .buf = rxdata,
+ },
+ {
+ .addr = saddr,
+ .flags = I2C_M_RD,
+ .len = length,
+ .buf = rxdata,
+ },
+ };
+
+ if (i2c_transfer(ov5640_client->adapter, msgs, 2) < 0) {
+ CDBG("ov5640_i2c_rxdata failed!\n");
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int32_t ov5640_i2c_read_byte(unsigned short saddr,
+ unsigned int raddr, unsigned int *rdata)
+{
+ int rc = 0;
+ unsigned char buf[2];
+
+ memset(buf, 0, sizeof(buf));
+
+ buf[0] = (raddr & 0xFF00)>>8;
+ buf[1] = (raddr & 0x00FF);
+
+ rc = ov5640_i2c_rxdata(saddr, buf, 1);
+ if (rc < 0) {
+ CDBG("ov5640_i2c_read_byte failed!\n");
+ return rc;
+ }
+
+ *rdata = buf[0];
+
+ return rc;
+}
+
+static int32_t ov5640_writepregs(struct ov5640_sensor *ptb, int32_t len)
+{
+ int32_t i, ret = 0;
+ uint32_t regv;
+
+ for (i = 0; i < len; i++) {
+ if (0 == ptb[i].mask) {
+ ov5640_i2c_write(ov5640_client->addr, ptb[i].addr,
+ ptb[i].data, 10);
+ } else {
+ ov5640_i2c_read_byte(ov5640_client->addr, ptb[i].addr,
+ ®v);
+ regv &= ptb[i].mask;
+ regv |= (ptb[i].data & (~ptb[i].mask));
+ ov5640_i2c_write(ov5640_client->addr, ptb[i].addr,
+ regv, 10);
+ }
+ }
+ return ret;
+}
+
+static void camera_sw_power_onoff(int v)
+{
+ if (v == 0) {
+ CDBG("camera_sw_power_onoff: down\n");
+ ov5640_i2c_write(ov5640_client->addr, 0x3008, 0x42, 10);
+ } else {
+ CDBG("camera_sw_power_onoff: on\n");
+ ov5640_i2c_write(ov5640_client->addr, 0x3008, 0x02, 10);
+ }
+}
+
+static void ov5640_power_off(void)
+{
+ CDBG("--CAMERA-- %s ... (Start...)\n", __func__);
+ gpio_set_value(ov5640_pwdn_gpio, 1);
+ CDBG("--CAMERA-- %s ... (End...)\n", __func__);
+}
+
+static void ov5640_power_on(void)
+{
+ CDBG("--CAMERA-- %s ... (Start...)\n", __func__);
+ gpio_set_value(ov5640_pwdn_gpio, 0);
+ CDBG("--CAMERA-- %s ... (End...)\n", __func__);
+}
+
+static void ov5640_power_reset(void)
+{
+ CDBG("--CAMERA-- %s ... (Start...)\n", __func__);
+ gpio_set_value(ov5640_reset_gpio, 1); /* reset camera reset pin */
+ msleep(20);
+ gpio_set_value(ov5640_reset_gpio, 0);
+ msleep(20);
+ gpio_set_value(ov5640_reset_gpio, 1);
+ msleep(20);
+
+ CDBG("--CAMERA-- %s ... (End...)\n", __func__);
+}
+
+static int ov5640_probe_readID(const struct msm_camera_sensor_info *data)
+{
+ int rc = 0;
+ u32 device_id_high = 0;
+ u32 device_id_low = 0;
+
+ CDBG("--CAMERA-- %s (Start...)\n", __func__);
+ CDBG("--CAMERA-- %s sensor poweron,begin to read ID!\n", __func__);
+
+ /* 0x300A ,sensor ID register */
+ rc = ov5640_i2c_read_byte(ov5640_client->addr, 0x300A,
+ &device_id_high);
+
+ if (rc < 0) {
+ CDBG("--CAMERA-- %s ok , readI2C failed, rc = 0x%x\r\n",
+ __func__, rc);
+ return rc;
+ }
+ CDBG("--CAMERA-- %s readID high byte, data = 0x%x\r\n",
+ __func__, device_id_high);
+
+ /* 0x300B ,sensor ID register */
+ rc = ov5640_i2c_read_byte(ov5640_client->addr, 0x300B,
+ &device_id_low);
+ if (rc < 0) {
+ CDBG("--CAMERA-- %s ok , readI2C failed,rc = 0x%x\r\n",
+ __func__, rc);
+ return rc;
+ }
+
+ CDBG("--CAMERA-- %s readID low byte, data = 0x%x\r\n",
+ __func__, device_id_low);
+ CDBG("--CAMERA-- %s return ID :0x%x\n", __func__,
+ (device_id_high << 8) + device_id_low);
+
+ /* 0x5640, ov5640 chip id */
+ if ((device_id_high << 8) + device_id_low != OV5640_SENSOR_ID) {
+ CDBG("--CAMERA-- %s ok , device id error, should be 0x%x\r\n",
+ __func__, OV5640_SENSOR_ID);
+ return -EINVAL;
+ } else {
+ CDBG("--CAMERA-- %s ok , device id=0x%x\n", __func__,
+ OV5640_SENSOR_ID);
+ return 0;
+ }
+}
+
+static int ov5640_af_setting(void)
+{
+ int rc = 0;
+ int lens = sizeof(ov5640_afinit_tbl) / sizeof(ov5640_afinit_tbl[0]);
+
+ CDBG("--CAMERA-- ov5640_af_setting\n");
+
+ ov5640_i2c_write(ov5640_client->addr, 0x3000, 0x20, 10);
+
+ rc = ov5640_i2c_txdata(ov5640_client->addr, ov5640_afinit_tbl, lens);
+ if (rc < 0) {
+ CDBG("--CAMERA-- AF_init failed\n");
+ return rc;
+ }
+
+ ov5640_i2c_write(ov5640_client->addr, OV5640_CMD_MAIN, 0x00, 10);
+ ov5640_i2c_write(ov5640_client->addr, OV5640_CMD_ACK, 0x00, 10);
+ ov5640_i2c_write(ov5640_client->addr, OV5640_CMD_PARA0, 0x00, 10);
+ ov5640_i2c_write(ov5640_client->addr, OV5640_CMD_PARA1, 0x00, 10);
+ ov5640_i2c_write(ov5640_client->addr, OV5640_CMD_PARA2, 0x00, 10);
+ ov5640_i2c_write(ov5640_client->addr, OV5640_CMD_PARA3, 0x00, 10);
+ ov5640_i2c_write(ov5640_client->addr, OV5640_CMD_PARA4, 0x00, 10);
+ ov5640_i2c_write(ov5640_client->addr, OV5640_CMD_FW_STATUS, 0x7f, 10);
+ ov5640_i2c_write(ov5640_client->addr, 0x3000, 0x00, 10);
+
+ return rc;
+}
+
+static int ov5640_set_flash_light(enum led_brightness brightness)
+{
+ struct led_classdev *led_cdev;
+
+ CDBG("ov5640_set_flash_light brightness = %d\n", brightness);
+
+ down_read(&ov_leds_list_lock);
+ list_for_each_entry(led_cdev, &ov_leds_list, node) {
+ if (!strncmp(led_cdev->name, "flashlight", 10))
+ break;
+ }
+ up_read(&ov_leds_list_lock);
+
+ if (led_cdev) {
+ led_brightness_set(led_cdev, brightness);
+ } else {
+ CDBG("get flashlight device failed\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int ov5640_video_config(void)
+{
+ int rc = 0;
+
+ CDBG("--CAMERA-- ov5640_video_config\n");
+ CDBG("--CAMERA-- preview in, is_autoflash - 0x%x\n", is_autoflash);
+
+ /* autoflash setting */
+ if (is_autoflash == 1)
+ ov5640_set_flash_light(LED_OFF);
+
+ /* preview setting */
+ rc = OV5640CORE_WRITEPREG(ov5640_preview_tbl);
+ return rc;
+}
+
+static int ov5640_snapshot_config(void)
+{
+ int rc = 0;
+ unsigned int tmp;
+
+ CDBG("--CAMERA-- SENSOR_SNAPSHOT_MODE\n");
+ CDBG("--CAMERA-- %s, snapshot in, is_autoflash - 0x%x\n", __func__,
+ is_autoflash);
+
+ if (is_autoflash == 1) {
+ ov5640_i2c_read_byte(ov5640_client->addr, 0x350b, &tmp);
+ CDBG("--CAMERA-- GAIN VALUE : %x\n", tmp);
+ if ((tmp & 0x80) == 0)
+ ov5640_set_flash_light(LED_OFF);
+ else
+ ov5640_set_flash_light(LED_FULL);
+ }
+
+ rc = OV5640CORE_WRITEPREG(ov5640_capture_tbl);
+
+ return rc;
+}
+
+static int ov5640_setting(enum msm_s_reg_update rupdate,
+ enum msm_s_setting rt)
+{
+ int rc = -EINVAL, tmp;
+ struct msm_camera_csi_params ov5640_csi_params;
+
+ CDBG("--CAMERA-- %s (Start...), rupdate=%d\n", __func__, rupdate);
+
+ switch (rupdate) {
+ case S_UPDATE_PERIODIC:
+ if (!OV5640_CSI_CONFIG) {
+ camera_sw_power_onoff(0); /* standby */
+ msleep(20);
+
+ ov5640_csi_params.lane_cnt = 2;
+ ov5640_csi_params.data_format = CSI_8BIT;
+ ov5640_csi_params.lane_assign = 0xe4;
+ ov5640_csi_params.dpcm_scheme = 0;
+ ov5640_csi_params.settle_cnt = 0x6;
+
+ CDBG("%s: msm_camio_csi_config\n", __func__);
+
+ rc = msm_camio_csi_config(&ov5640_csi_params);
+ msleep(20);
+ camera_sw_power_onoff(1); /* on */
+ msleep(20);
+
+ OV5640_CSI_CONFIG = 1;
+
+ } else {
+ rc = 0;
+ }
+
+ if (S_RES_PREVIEW == rt)
+ rc = ov5640_video_config();
+ else if (S_RES_CAPTURE == rt)
+ rc = ov5640_snapshot_config();
+
+ break; /* UPDATE_PERIODIC */
+
+ case S_REG_INIT:
+ CDBG("--CAMERA-- S_REG_INIT (Start)\n");
+
+ rc = ov5640_i2c_write(ov5640_client->addr, 0x3103, 0x11, 10);
+ rc = ov5640_i2c_write(ov5640_client->addr, 0x3008, 0x82, 10);
+ msleep(20);
+
+ /* set sensor init setting */
+ CDBG("set sensor init setting\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_init_tbl);
+ if (rc < 0) {
+ CDBG("sensor init setting failed\n");
+ break;
+ }
+
+ /* set image quality setting */
+ rc = OV5640CORE_WRITEPREG(ov5640_init_iq_tbl);
+ rc = ov5640_i2c_read_byte(ov5640_client->addr, 0x4740, &tmp);
+ CDBG("--CAMERA-- init 0x4740 value=0x%x\n", tmp);
+
+ if (tmp != 0x21) {
+ rc = ov5640_i2c_write(ov5640_client->addr, 0x4740,
+ 0x21, 10);
+ msleep(20);
+ rc = ov5640_i2c_read_byte(ov5640_client->addr,
+ 0x4740, &tmp);
+ CDBG("--CAMERA-- WG 0x4740 value=0x%x\n", tmp);
+ }
+
+ CDBG("--CAMERA-- AF_init: ov5640_afinit = %d\n",
+ ov5640_afinit);
+ if (ov5640_afinit == 1) {
+ rc = ov5640_af_setting();
+ if (rc < 0) {
+ CDBG("--CAMERA-- ov5640_af_setting failed\n");
+ break;
+ }
+ ov5640_afinit = 0;
+ }
+
+ /* reset fps_divider */
+ ov5640_ctrl->fps_divider = 1 * 0x0400;
+ CDBG("--CAMERA-- S_REG_INIT (End)\n");
+ break; /* case REG_INIT: */
+
+ default:
+ break;
+ } /* switch (rupdate) */
+
+ CDBG("--CAMERA-- %s (End), rupdate=%d\n", __func__, rupdate);
+
+ return rc;
+}
+
+static int ov5640_sensor_open_init(const struct msm_camera_sensor_info *data)
+{
+ int rc = -ENOMEM;
+
+ CDBG("--CAMERA-- %s\n", __func__);
+ ov5640_ctrl = kzalloc(sizeof(struct __ov5640_ctrl), GFP_KERNEL);
+ if (!ov5640_ctrl) {
+ CDBG("--CAMERA-- kzalloc ov5640_ctrl error !!\n");
+ kfree(ov5640_ctrl);
+ return rc;
+ }
+
+ ov5640_ctrl->fps_divider = 1 * 0x00000400;
+ ov5640_ctrl->pict_fps_divider = 1 * 0x00000400;
+ ov5640_ctrl->set_test = S_TEST_OFF;
+ ov5640_ctrl->prev_res = S_QTR_SIZE;
+ ov5640_ctrl->pict_res = S_FULL_SIZE;
+
+ if (data)
+ ov5640_ctrl->sensordata = data;
+
+ ov5640_power_off();
+
+ CDBG("%s: msm_camio_clk_rate_set\n", __func__);
+
+ msm_camio_clk_rate_set(24000000);
+ msleep(20);
+
+ ov5640_power_on();
+ ov5640_power_reset();
+
+ CDBG("%s: init sequence\n", __func__);
+
+ if (ov5640_ctrl->prev_res == S_QTR_SIZE)
+ rc = ov5640_setting(S_REG_INIT, S_RES_PREVIEW);
+ else
+ rc = ov5640_setting(S_REG_INIT, S_RES_CAPTURE);
+
+ if (rc < 0) {
+ CDBG("--CAMERA-- %s : ov5640_setting failed. rc = %d\n",
+ __func__, rc);
+ kfree(ov5640_ctrl);
+ return rc;
+ }
+
+ OV5640_CSI_CONFIG = 0;
+
+ CDBG("--CAMERA--re_init_sensor ok!!\n");
+ return rc;
+}
+
+static int ov5640_sensor_release(void)
+{
+ CDBG("--CAMERA--ov5640_sensor_release!!\n");
+
+ mutex_lock(&ov5640_mutex);
+
+ ov5640_power_off();
+
+ kfree(ov5640_ctrl);
+ ov5640_ctrl = NULL;
+
+ OV5640_CSI_CONFIG = 0;
+
+ mutex_unlock(&ov5640_mutex);
+ return 0;
+}
+
+static const struct i2c_device_id ov5640_i2c_id[] = {
+ {"ov5640", 0}, {}
+};
+
+static int ov5640_i2c_remove(struct i2c_client *client)
+{
+ return 0;
+}
+
+static int ov5640_init_client(struct i2c_client *client)
+{
+ /* Initialize the MSM_CAMI2C Chip */
+ init_waitqueue_head(&ov5640_wait_queue);
+ return 0;
+}
+
+static long ov5640_set_effect(int mode, int effect)
+{
+ int rc = 0;
+
+ CDBG("--CAMERA-- %s ...(Start)\n", __func__);
+
+ switch (mode) {
+ case SENSOR_PREVIEW_MODE:
+ /* Context A Special Effects */
+ CDBG("--CAMERA-- %s ...SENSOR_PREVIEW_MODE\n", __func__);
+ break;
+
+ case SENSOR_SNAPSHOT_MODE:
+ /* Context B Special Effects */
+ CDBG("--CAMERA-- %s ...SENSOR_SNAPSHOT_MODE\n", __func__);
+ break;
+
+ default:
+ break;
+ }
+
+ effect_value = effect;
+
+ switch (effect) {
+ case CAMERA_EFFECT_OFF:
+ CDBG("--CAMERA-- %s ...CAMERA_EFFECT_OFF\n", __func__);
+ rc = OV5640CORE_WRITEPREG(ov5640_effect_normal_tbl);
+ /* for recover saturation level when change special effect */
+ ov5640_i2c_write(ov5640_client->addr, 0x5583, ov5640_SAT_U,
+ 10);
+ /* for recover saturation level when change special effect */
+ ov5640_i2c_write(ov5640_client->addr, 0x5584, ov5640_SAT_V,
+ 10);
+ break;
+
+ case CAMERA_EFFECT_MONO:
+ CDBG("--CAMERA-- %s ...CAMERA_EFFECT_MONO\n", __func__);
+ rc = OV5640CORE_WRITEPREG(ov5640_effect_mono_tbl);
+ break;
+
+ case CAMERA_EFFECT_BW:
+ CDBG("--CAMERA-- %s ...CAMERA_EFFECT_BW\n", __func__);
+ rc = OV5640CORE_WRITEPREG(ov5640_effect_bw_tbl);
+ break;
+
+ case CAMERA_EFFECT_BLUISH:
+ CDBG("--CAMERA-- %s ...CAMERA_EFFECT_BLUISH\n", __func__);
+ rc = OV5640CORE_WRITEPREG(ov5640_effect_bluish_tbl);
+ break;
+
+ case CAMERA_EFFECT_SOLARIZE:
+ CDBG("--CAMERA-- %s ...CAMERA_EFFECT_NEGATIVE\n", __func__);
+ rc = OV5640CORE_WRITEPREG(ov5640_effect_solarize_tbl);
+ break;
+
+ case CAMERA_EFFECT_SEPIA:
+ CDBG("--CAMERA-- %s ...CAMERA_EFFECT_SEPIA\n", __func__);
+ rc = OV5640CORE_WRITEPREG(ov5640_effect_sepia_tbl);
+ break;
+
+ case CAMERA_EFFECT_REDDISH:
+ CDBG("--CAMERA-- %s ...CAMERA_EFFECT_REDDISH\n", __func__);
+ rc = OV5640CORE_WRITEPREG(ov5640_effect_reddish_tbl);
+ break;
+
+ case CAMERA_EFFECT_GREENISH:
+ CDBG("--CAMERA-- %s ...CAMERA_EFFECT_GREENISH\n", __func__);
+ rc = OV5640CORE_WRITEPREG(ov5640_effect_greenish_tbl);
+ break;
+
+ case CAMERA_EFFECT_NEGATIVE:
+ CDBG("--CAMERA-- %s ...CAMERA_EFFECT_NEGATIVE\n", __func__);
+ rc = OV5640CORE_WRITEPREG(ov5640_effect_negative_tbl);
+ break;
+
+ default:
+ CDBG("--CAMERA-- %s ...Default(Not Support)\n", __func__);
+ }
+
+ ov5640_effect = effect;
+ /* Refresh Sequencer */
+ CDBG("--CAMERA-- %s ...(End)\n", __func__);
+ return rc;
+}
+
+static int ov5640_set_brightness(int8_t brightness)
+{
+ int rc = 0;
+
+ CDBG("--CAMERA-- %s ...(Start)\n", __func__);
+ CDBG("--CAMERA-- %s ...brightness = %d\n", __func__ , brightness);
+
+ switch (brightness) {
+ case CAMERA_BRIGHTNESS_LV0:
+ CDBG("--CAMERA--CAMERA_BRIGHTNESS_LV0\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_brightness_lv0_tbl);
+ break;
+
+ case CAMERA_BRIGHTNESS_LV1:
+ CDBG("--CAMERA--CAMERA_BRIGHTNESS_LV1\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_brightness_lv1_tbl);
+ break;
+
+ case CAMERA_BRIGHTNESS_LV2:
+ CDBG("--CAMERA--CAMERA_BRIGHTNESS_LV2\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_brightness_lv2_tbl);
+ break;
+
+ case CAMERA_BRIGHTNESS_LV3:
+ CDBG("--CAMERA--CAMERA_BRIGHTNESS_LV3\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_brightness_lv3_tbl);
+ break;
+
+ case CAMERA_BRIGHTNESS_LV4:
+ CDBG("--CAMERA--CAMERA_BRIGHTNESS_LV4\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_brightness_default_lv4_tbl);
+ break;
+
+ case CAMERA_BRIGHTNESS_LV5:
+ CDBG("--CAMERA--CAMERA_BRIGHTNESS_LV5\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_brightness_lv5_tbl);
+ break;
+
+ case CAMERA_BRIGHTNESS_LV6:
+ CDBG("--CAMERA--CAMERA_BRIGHTNESS_LV6\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_brightness_lv6_tbl);
+ break;
+
+ case CAMERA_BRIGHTNESS_LV7:
+ CDBG("--CAMERA--CAMERA_BRIGHTNESS_LV7\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_brightness_lv7_tbl);
+ break;
+
+ case CAMERA_BRIGHTNESS_LV8:
+ CDBG("--CAMERA--CAMERA_BRIGHTNESS_LV8\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_brightness_lv8_tbl);
+ break;
+
+ default:
+ CDBG("--CAMERA--CAMERA_BRIGHTNESS_ERROR COMMAND\n");
+ break;
+ }
+
+ CDBG("--CAMERA-- %s ...(End)\n", __func__);
+ return rc;
+}
+
+static int ov5640_set_contrast(int contrast)
+{
+ int rc = 0;
+
+ CDBG("--CAMERA-- %s ...(Start)\n", __func__);
+ CDBG("--CAMERA-- %s ...contrast = %d\n", __func__ , contrast);
+
+ if (effect_value == CAMERA_EFFECT_OFF) {
+ switch (contrast) {
+ case CAMERA_CONTRAST_LV0:
+ CDBG("--CAMERA--CAMERA_CONTRAST_LV0\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_contrast_lv0_tbl);
+ break;
+
+ case CAMERA_CONTRAST_LV1:
+ CDBG("--CAMERA--CAMERA_CONTRAST_LV1\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_contrast_lv1_tbl);
+ break;
+
+ case CAMERA_CONTRAST_LV2:
+ CDBG("--CAMERA--CAMERA_CONTRAST_LV2\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_contrast_lv2_tbl);
+ break;
+
+ case CAMERA_CONTRAST_LV3:
+ CDBG("--CAMERA--CAMERA_CONTRAST_LV3\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_contrast_lv3_tbl);
+ break;
+
+ case CAMERA_CONTRAST_LV4:
+ CDBG("--CAMERA--CAMERA_CONTRAST_LV4\n");
+ rc = OV5640CORE_WRITEPREG(
+ ov5640_contrast_default_lv4_tbl);
+ break;
+
+ case CAMERA_CONTRAST_LV5:
+ CDBG("--CAMERA--CAMERA_CONTRAST_LV5\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_contrast_lv5_tbl);
+ break;
+
+ case CAMERA_CONTRAST_LV6:
+ CDBG("--CAMERA--CAMERA_CONTRAST_LV6\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_contrast_lv6_tbl);
+ break;
+
+ case CAMERA_CONTRAST_LV7:
+ CDBG("--CAMERA--CAMERA_CONTRAST_LV7\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_contrast_lv7_tbl);
+ break;
+
+ case CAMERA_CONTRAST_LV8:
+ CDBG("--CAMERA--CAMERA_CONTRAST_LV8\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_contrast_lv8_tbl);
+ break;
+
+ default:
+ CDBG("--CAMERA--CAMERA_CONTRAST_ERROR COMMAND\n");
+ break;
+ }
+ }
+
+ CDBG("--CAMERA-- %s ...(End)\n", __func__);
+ return rc;
+}
+
+static int ov5640_set_sharpness(int sharpness)
+{
+ int rc = 0;
+
+ CDBG("--CAMERA-- %s ...(Start)\n", __func__);
+ CDBG("--CAMERA-- %s ...sharpness = %d\n", __func__ , sharpness);
+
+ if (effect_value == CAMERA_EFFECT_OFF) {
+ switch (sharpness) {
+ case CAMERA_SHARPNESS_LV0:
+ CDBG("--CAMERA--CAMERA_SHARPNESS_LV0\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_sharpness_lv0_tbl);
+ break;
+
+ case CAMERA_SHARPNESS_LV1:
+ CDBG("--CAMERA--CAMERA_SHARPNESS_LV1\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_sharpness_lv1_tbl);
+ break;
+
+ case CAMERA_SHARPNESS_LV2:
+ CDBG("--CAMERA--CAMERA_SHARPNESS_LV2\n");
+ rc = OV5640CORE_WRITEPREG(
+ ov5640_sharpness_default_lv2_tbl);
+ break;
+
+ case CAMERA_SHARPNESS_LV3:
+ CDBG("--CAMERA--CAMERA_SHARPNESS_LV3\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_sharpness_lv3_tbl);
+ break;
+
+ case CAMERA_SHARPNESS_LV4:
+ CDBG("--CAMERA--CAMERA_SHARPNESS_LV4\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_sharpness_lv4_tbl);
+ break;
+
+ case CAMERA_SHARPNESS_LV5:
+ CDBG("--CAMERA--CAMERA_SHARPNESS_LV5\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_sharpness_lv5_tbl);
+ break;
+
+ case CAMERA_SHARPNESS_LV6:
+ CDBG("--CAMERA--CAMERA_SHARPNESS_LV6\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_sharpness_lv6_tbl);
+ break;
+
+ case CAMERA_SHARPNESS_LV7:
+ CDBG("--CAMERA--CAMERA_SHARPNESS_LV7\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_sharpness_lv7_tbl);
+ break;
+
+ case CAMERA_SHARPNESS_LV8:
+ CDBG("--CAMERA--CAMERA_SHARPNESS_LV8\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_sharpness_lv8_tbl);
+ break;
+
+ default:
+ CDBG("--CAMERA--CAMERA_SHARPNESS_ERROR COMMAND\n");
+ break;
+ }
+ }
+
+ CDBG("--CAMERA-- %s ...(End)\n", __func__);
+ return rc;
+}
+
+static int ov5640_set_saturation(int saturation)
+{
+ long rc = 0;
+
+ CDBG("--CAMERA-- %s ...(Start)\n", __func__);
+ CDBG("--CAMERA-- %s ...saturation = %d\n", __func__ , saturation);
+
+ if (effect_value == CAMERA_EFFECT_OFF) {
+ switch (saturation) {
+ case CAMERA_SATURATION_LV0:
+ CDBG("--CAMERA--CAMERA_SATURATION_LV0\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_saturation_lv0_tbl);
+ break;
+
+ case CAMERA_SATURATION_LV1:
+ CDBG("--CAMERA--CAMERA_SATURATION_LV1\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_saturation_lv1_tbl);
+ break;
+
+ case CAMERA_SATURATION_LV2:
+ CDBG("--CAMERA--CAMERA_SATURATION_LV2\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_saturation_lv2_tbl);
+ break;
+
+ case CAMERA_SATURATION_LV3:
+ CDBG("--CAMERA--CAMERA_SATURATION_LV3\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_saturation_lv3_tbl);
+ break;
+
+ case CAMERA_SATURATION_LV4:
+ CDBG("--CAMERA--CAMERA_SATURATION_LV4\n");
+ rc = OV5640CORE_WRITEPREG(
+ ov5640_saturation_default_lv4_tbl);
+ break;
+
+ case CAMERA_SATURATION_LV5:
+ CDBG("--CAMERA--CAMERA_SATURATION_LV5\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_saturation_lv5_tbl);
+ break;
+
+ case CAMERA_SATURATION_LV6:
+ CDBG("--CAMERA--CAMERA_SATURATION_LV6\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_saturation_lv6_tbl);
+ break;
+
+ case CAMERA_SATURATION_LV7:
+ CDBG("--CAMERA--CAMERA_SATURATION_LV7\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_saturation_lv7_tbl);
+ break;
+
+ case CAMERA_SATURATION_LV8:
+ CDBG("--CAMERA--CAMERA_SATURATION_LV8\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_saturation_lv8_tbl);
+ break;
+
+ default:
+ CDBG("--CAMERA--CAMERA_SATURATION_ERROR COMMAND\n");
+ break;
+ }
+ }
+
+ /* for recover saturation level when change special effect */
+ switch (saturation) {
+ case CAMERA_SATURATION_LV0:
+ CDBG("--CAMERA--CAMERA_SATURATION_LV0\n");
+ ov5640_SAT_U = 0x00;
+ ov5640_SAT_V = 0x00;
+ break;
+ case CAMERA_SATURATION_LV1:
+ CDBG("--CAMERA--CAMERA_SATURATION_LV1\n");
+ ov5640_SAT_U = 0x10;
+ ov5640_SAT_V = 0x10;
+ break;
+ case CAMERA_SATURATION_LV2:
+ CDBG("--CAMERA--CAMERA_SATURATION_LV2\n");
+ ov5640_SAT_U = 0x20;
+ ov5640_SAT_V = 0x20;
+ break;
+ case CAMERA_SATURATION_LV3:
+ CDBG("--CAMERA--CAMERA_SATURATION_LV3\n");
+ ov5640_SAT_U = 0x30;
+ ov5640_SAT_V = 0x30;
+ break;
+ case CAMERA_SATURATION_LV4:
+ CDBG("--CAMERA--CAMERA_SATURATION_LV4\n");
+ ov5640_SAT_U = 0x40;
+ ov5640_SAT_V = 0x40; break;
+ case CAMERA_SATURATION_LV5:
+ CDBG("--CAMERA--CAMERA_SATURATION_LV5\n");
+ ov5640_SAT_U = 0x50;
+ ov5640_SAT_V = 0x50; break;
+ case CAMERA_SATURATION_LV6:
+ CDBG("--CAMERA--CAMERA_SATURATION_LV6\n");
+ ov5640_SAT_U = 0x60;
+ ov5640_SAT_V = 0x60;
+ break;
+ case CAMERA_SATURATION_LV7:
+ CDBG("--CAMERA--CAMERA_SATURATION_LV7\n");
+ ov5640_SAT_U = 0x70;
+ ov5640_SAT_V = 0x70; break;
+ case CAMERA_SATURATION_LV8:
+ CDBG("--CAMERA--CAMERA_SATURATION_LV8\n");
+ ov5640_SAT_U = 0x80;
+ ov5640_SAT_V = 0x80;
+ break;
+ default:
+ CDBG("--CAMERA--CAMERA_SATURATION_ERROR COMMAND\n");
+ break;
+ }
+
+ CDBG("--CAMERA-- %s ...(End)\n", __func__);
+ return rc;
+}
+
+static long ov5640_set_antibanding(int antibanding)
+{
+ long rc = 0;
+
+ CDBG("--CAMERA-- %s ...(Start)\n", __func__);
+ CDBG("--CAMERA-- %s ...antibanding = %d\n", __func__, antibanding);
+
+ switch (antibanding) {
+ case CAMERA_ANTIBANDING_OFF:
+ CDBG("--CAMERA--CAMERA_ANTIBANDING_OFF\n");
+ break;
+
+ case CAMERA_ANTIBANDING_60HZ:
+ CDBG("--CAMERA--CAMERA_ANTIBANDING_60HZ\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_antibanding_60z_tbl);
+ break;
+
+ case CAMERA_ANTIBANDING_50HZ:
+ CDBG("--CAMERA--CAMERA_ANTIBANDING_50HZ\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_antibanding_50z_tbl);
+ break;
+
+ case CAMERA_ANTIBANDING_AUTO:
+ CDBG("--CAMERA--CAMERA_ANTIBANDING_AUTO\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_antibanding_auto_tbl);
+ break;
+
+ default:
+ CDBG("--CAMERA--CAMERA_ANTIBANDING_ERROR COMMAND\n");
+ break;
+ }
+
+ CDBG("--CAMERA-- %s ...(End)\n", __func__);
+ return rc;
+}
+
+static long ov5640_set_exposure_mode(int mode)
+{
+ long rc = 0;
+ CDBG("--CAMERA-- %s ...(Start)\n", __func__);
+ CDBG("--CAMERA-- %s ...mode = %d\n", __func__ , mode);
+ CDBG("--CAMERA-- %s ...(End)\n", __func__);
+ return rc;
+}
+
+static int32_t ov5640_lens_shading_enable(uint8_t is_enable)
+{
+ int32_t rc = 0;
+ CDBG("--CAMERA--%s: ...(Start). enable = %d\n", __func__, is_enable);
+
+ if (is_enable) {
+ CDBG("%s: enable~!!\n", __func__);
+ rc = OV5640CORE_WRITEPREG(ov5640_lens_shading_on_tbl);
+ } else {
+ CDBG("%s: disable~!!\n", __func__);
+ rc = OV5640CORE_WRITEPREG(ov5640_lens_shading_off_tbl);
+ }
+ CDBG("--CAMERA--%s: ...(End). rc = %d\n", __func__, rc);
+ return rc;
+}
+
+static int ov5640_set_sensor_mode(int mode, int res)
+{
+ int rc = 0;
+
+ CDBG("--CAMERA-- ov5640_set_sensor_mode mode = %d, res = %d\n",
+ mode, res);
+
+ switch (mode) {
+ case SENSOR_PREVIEW_MODE:
+ CDBG("--CAMERA-- SENSOR_PREVIEW_MODE\n");
+ rc = ov5640_setting(S_UPDATE_PERIODIC, S_RES_PREVIEW);
+ break;
+
+ case SENSOR_SNAPSHOT_MODE:
+ CDBG("--CAMERA-- SENSOR_SNAPSHOT_MODE\n");
+ rc = ov5640_setting(S_UPDATE_PERIODIC, S_RES_CAPTURE);
+ break;
+
+ case SENSOR_RAW_SNAPSHOT_MODE:
+ CDBG("--CAMERA-- SENSOR_RAW_SNAPSHOT_MODE\n");
+ rc = ov5640_setting(S_UPDATE_PERIODIC, S_RES_CAPTURE);
+ break;
+
+ default:
+ CDBG("--CAMERA--ov5640_set_sensor_mode no support\n");
+ rc = -EINVAL;
+ break;
+ }
+
+ return rc;
+}
+
+static int ov5640_set_wb_oem(uint8_t param)
+{
+ int rc = 0;
+ unsigned int tmp2;
+
+ CDBG("[kylin] %s \r\n", __func__);
+
+ ov5640_i2c_read_byte(ov5640_client->addr, 0x350b, &tmp2);
+ CDBG("--CAMERA-- GAIN VALUE : %x\n", tmp2);
+
+ switch (param) {
+ case CAMERA_WB_AUTO:
+
+ CDBG("--CAMERA--CAMERA_WB_AUTO\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_wb_def);
+ break;
+
+ case CAMERA_WB_CUSTOM:
+ CDBG("--CAMERA--CAMERA_WB_CUSTOM\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_wb_custom);
+ break;
+ case CAMERA_WB_INCANDESCENT:
+ CDBG("--CAMERA--CAMERA_WB_INCANDESCENT\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_wb_inc);
+ break;
+ case CAMERA_WB_DAYLIGHT:
+ CDBG("--CAMERA--CAMERA_WB_DAYLIGHT\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_wb_daylight);
+ break;
+ case CAMERA_WB_CLOUDY_DAYLIGHT:
+ CDBG("--CAMERA--CAMERA_WB_CLOUDY_DAYLIGHT\n");
+ rc = OV5640CORE_WRITEPREG(ov5640_wb_cloudy);
+ break;
+ default:
+ break;
+ }
+ return rc;
+}
+
+static int ov5640_set_touchaec(uint32_t x, uint32_t y)
+{
+ uint8_t aec_arr[8] = {0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11};
+ int idx = 0;
+ int i;
+
+ CDBG("[kylin] %s x: %d ,y: %d\r\n", __func__ , x, y);
+ idx = x / 2 + y * 2;
+ CDBG("[kylin] idx: %d\r\n", idx);
+
+ if (x % 2 == 0)
+ aec_arr[idx] = 0x10 | 0x0a;
+ else
+ aec_arr[idx] = 0x01 | 0xa0;
+
+ for (i = 0; i < 8; i++) {
+ CDBG("write : %x val : %x ", 0x5688 + i, aec_arr[i]);
+ ov5640_i2c_write(ov5640_client->addr, 0x5688 + i,
+ aec_arr[i], 10);
+ }
+
+ return 1;
+}
+
+static int ov5640_set_exposure_compensation(int compensation)
+{
+ long rc = 0;
+
+ CDBG("--CAMERA-- %s ...(Start)\n", __func__);
+
+ CDBG("--CAMERA-- %s ...exposure_compensation = %d\n", __func__ ,
+ compensation);
+
+ switch (compensation) {
+ case CAMERA_EXPOSURE_COMPENSATION_LV0:
+ CDBG("--CAMERA--CAMERA_EXPOSURE_COMPENSATION_LV0\n");
+ rc = OV5640CORE_WRITEPREG(
+ ov5640_exposure_compensation_lv0_tbl);
+ break;
+
+ case CAMERA_EXPOSURE_COMPENSATION_LV1:
+ CDBG("--CAMERA--CAMERA_EXPOSURE_COMPENSATION_LV1\n");
+ rc = OV5640CORE_WRITEPREG(
+ ov5640_exposure_compensation_lv1_tbl);
+ break;
+
+ case CAMERA_EXPOSURE_COMPENSATION_LV2:
+ CDBG("--CAMERA--CAMERA_EXPOSURE_COMPENSATION_LV2\n");
+ rc = OV5640CORE_WRITEPREG(
+ ov5640_exposure_compensation_lv2_default_tbl);
+ break;
+
+ case CAMERA_EXPOSURE_COMPENSATION_LV3:
+ CDBG("--CAMERA--CAMERA_EXPOSURE_COMPENSATION_LV3\n");
+ rc = OV5640CORE_WRITEPREG(
+ ov5640_exposure_compensation_lv3_tbl);
+ break;
+
+ case CAMERA_EXPOSURE_COMPENSATION_LV4:
+ CDBG("--CAMERA--CAMERA_EXPOSURE_COMPENSATION_LV3\n");
+ rc = OV5640CORE_WRITEPREG(
+ ov5640_exposure_compensation_lv4_tbl);
+ break;
+
+ default:
+ CDBG("--CAMERA--ERROR CAMERA_EXPOSURE_COMPENSATION\n");
+ break;
+ }
+
+ CDBG("--CAMERA-- %s ...(End)\n", __func__);
+
+ return rc;
+}
+
+static int ov5640_sensor_start_af(void)
+{
+ int i;
+ unsigned int af_st = 0;
+ unsigned int af_ack = 0;
+ unsigned int tmp = 0;
+ int rc = 0;
+
+ CDBG("--CAMERA-- %s (Start...)\n", __func__);
+
+ ov5640_i2c_read_byte(ov5640_client->addr,
+ OV5640_CMD_FW_STATUS, &af_st);
+ CDBG("--CAMERA-- %s af_st = %d\n", __func__, af_st);
+
+ ov5640_i2c_write(ov5640_client->addr, OV5640_CMD_ACK, 0x01, 10);
+ ov5640_i2c_write(ov5640_client->addr, OV5640_CMD_MAIN, 0x03, 10);
+
+ for (i = 0; i < 50; i++) {
+ ov5640_i2c_read_byte(ov5640_client->addr,
+ OV5640_CMD_ACK, &af_ack);
+ if (af_ack == 0)
+ break;
+ msleep(50);
+ }
+ CDBG("--CAMERA-- %s af_ack = 0x%x\n", __func__, af_ack);
+
+ ov5640_i2c_read_byte(ov5640_client->addr, OV5640_CMD_FW_STATUS,
+ &af_st);
+ CDBG("--CAMERA-- %s af_st = %d\n", __func__, af_st);
+
+ if (af_st == 0x10) {
+ CDBG("--CAMERA-- %s AF ok and release AF setting~!!\n",
+ __func__);
+ } else {
+ CDBG("--CAMERA-- %s AF not ready!!\n", __func__);
+ }
+
+ ov5640_i2c_write(ov5640_client->addr, OV5640_CMD_ACK, 0x01, 10);
+ ov5640_i2c_write(ov5640_client->addr, OV5640_CMD_MAIN, 0x07, 10);
+
+ for (i = 0; i < 70; i++) {
+ ov5640_i2c_read_byte(ov5640_client->addr, OV5640_CMD_ACK,
+ &af_ack);
+ if (af_ack == 0)
+ break;
+ msleep(25);
+ }
+
+ ov5640_i2c_read_byte(ov5640_client->addr, OV5640_CMD_PARA0, &tmp);
+ CDBG("0x3024 = %x\n", tmp);
+ rc = ((tmp == 0) ? 1 : 0);
+
+ ov5640_i2c_read_byte(ov5640_client->addr, OV5640_CMD_PARA1, &tmp);
+ CDBG("0x3025 = %x\n", tmp);
+ rc = ((tmp == 0) ? 1 : 0);
+
+ ov5640_i2c_read_byte(ov5640_client->addr, OV5640_CMD_PARA2, &tmp);
+ CDBG("0x3026 = %x\n", tmp);
+ rc = ((tmp == 0) ? 1 : 0);
+
+ ov5640_i2c_read_byte(ov5640_client->addr, OV5640_CMD_PARA3, &tmp);
+ CDBG("0x3027 = %x\n", tmp);
+ rc = ((tmp == 0) ? 1 : 0) ;
+
+ ov5640_i2c_read_byte(ov5640_client->addr, OV5640_CMD_PARA4, &tmp);
+ CDBG("0x3028 = %x\n", tmp);
+ rc = ((tmp == 0) ? 1 : 0) ;
+
+ CDBG("--CAMERA-- %s rc = %d(End...)\n", __func__, rc);
+ return rc;
+}
+
+static int ov5640_sensor_config(void __user *argp)
+{
+ struct sensor_cfg_data cdata;
+ long rc = 0;
+
+ if (copy_from_user(&cdata, (void *)argp,
+ sizeof(struct sensor_cfg_data)))
+ return -EFAULT;
+
+ CDBG("--CAMERA-- %s %d\n", __func__, cdata.cfgtype);
+
+ mutex_lock(&ov5640_mutex);
+
+ switch (cdata.cfgtype) {
+ case CFG_SET_MODE:
+ rc = ov5640_set_sensor_mode(cdata.mode, cdata.rs);
+ break;
+
+ case CFG_SET_EFFECT:
+ CDBG("--CAMERA-- CFG_SET_EFFECT mode=%d,"
+ "effect = %d !!\n", cdata.mode,
+ cdata.cfg.effect);
+ rc = ov5640_set_effect(cdata.mode, cdata.cfg.effect);
+ break;
+
+ case CFG_START:
+ CDBG("--CAMERA-- CFG_START (Not Support) !!\n");
+ /* Not Support */
+ break;
+
+ case CFG_PWR_UP:
+ CDBG("--CAMERA-- CFG_PWR_UP (Not Support) !!\n");
+ /* Not Support */
+ break;
+
+ case CFG_PWR_DOWN:
+ CDBG("--CAMERA-- CFG_PWR_DOWN (Not Support)\n");
+ ov5640_power_off();
+ break;
+
+ case CFG_SET_DEFAULT_FOCUS:
+ CDBG("--CAMERA-- CFG_SET_DEFAULT_FOCUS (Not Implement) !!\n");
+ break;
+
+ case CFG_MOVE_FOCUS:
+ CDBG("--CAMERA-- CFG_MOVE_FOCUS (Not Implement) !!\n");
+ break;
+
+ case CFG_SET_BRIGHTNESS:
+ CDBG("--CAMERA-- CFG_SET_BRIGHTNESS !!\n");
+ rc = ov5640_set_brightness(cdata.cfg.brightness);
+ break;
+
+ case CFG_SET_CONTRAST:
+ CDBG("--CAMERA-- CFG_SET_CONTRAST !!\n");
+ rc = ov5640_set_contrast(cdata.cfg.contrast);
+ break;
+
+ case CFG_SET_EXPOSURE_MODE:
+ CDBG("--CAMERA-- CFG_SET_EXPOSURE_MODE !!\n");
+ rc = ov5640_set_exposure_mode(cdata.cfg.ae_mode);
+ break;
+
+ case CFG_SET_ANTIBANDING:
+ CDBG("--CAMERA-- CFG_SET_ANTIBANDING antibanding = %d!!\n",
+ cdata.cfg.antibanding);
+ rc = ov5640_set_antibanding(cdata.cfg.antibanding);
+ break;
+
+ case CFG_SET_LENS_SHADING:
+ CDBG("--CAMERA-- CFG_SET_LENS_SHADING !!\n");
+ rc = ov5640_lens_shading_enable(
+ cdata.cfg.lens_shading);
+ break;
+
+ case CFG_SET_SATURATION:
+ CDBG("--CAMERA-- CFG_SET_SATURATION !!\n");
+ rc = ov5640_set_saturation(cdata.cfg.saturation);
+ break;
+
+ case CFG_SET_SHARPNESS:
+ CDBG("--CAMERA-- CFG_SET_SHARPNESS !!\n");
+ rc = ov5640_set_sharpness(cdata.cfg.sharpness);
+ break;
+
+ case CFG_SET_WB:
+ CDBG("--CAMERA-- CFG_SET_WB!!\n");
+ ov5640_set_wb_oem(cdata.cfg.wb_val);
+ rc = 0 ;
+ break;
+
+ case CFG_SET_TOUCHAEC:
+ CDBG("--CAMERA-- CFG_SET_TOUCHAEC!!\n");
+ ov5640_set_touchaec(cdata.cfg.aec_cord.x,
+ cdata.cfg.aec_cord.y);
+ rc = 0 ;
+ break;
+
+ case CFG_SET_AUTO_FOCUS:
+ CDBG("--CAMERA-- CFG_SET_AUTO_FOCUS !\n");
+ rc = ov5640_sensor_start_af();
+ break;
+
+ case CFG_SET_AUTOFLASH:
+ CDBG("--CAMERA-- CFG_SET_AUTOFLASH !\n");
+ is_autoflash = cdata.cfg.is_autoflash;
+ CDBG("[kylin] is autoflash %d\r\n", is_autoflash);
+ rc = 0;
+ break;
+
+ case CFG_SET_EXPOSURE_COMPENSATION:
+ CDBG("--CAMERA-- CFG_SET_EXPOSURE_COMPENSATION !\n");
+ rc = ov5640_set_exposure_compensation(
+ cdata.cfg.exp_compensation);
+ break;
+
+ default:
+ CDBG("%s: Command=%d (Not Implement)!!\n", __func__,
+ cdata.cfgtype);
+ rc = -EINVAL;
+ break;
+ }
+
+ mutex_unlock(&ov5640_mutex);
+ return rc;
+}
+
+static struct i2c_driver ov5640_i2c_driver = {
+ .id_table = ov5640_i2c_id,
+ .probe = ov5640_i2c_probe,
+ .remove = ov5640_i2c_remove,
+ .driver = {
+ .name = "ov5640",
+ },
+};
+
+static int ov5640_probe_init_gpio(const struct msm_camera_sensor_info *data)
+{
+ int rc = 0;
+
+ CDBG("--CAMERA-- %s\n", __func__);
+
+ ov5640_pwdn_gpio = data->sensor_pwd;
+ ov5640_reset_gpio = data->sensor_reset;
+ ov5640_driver_pwdn_gpio = data->vcm_pwd ;
+
+ if (data->vcm_enable)
+ gpio_direction_output(data->vcm_pwd, 1);
+
+ gpio_direction_output(data->sensor_reset, 1);
+ gpio_direction_output(data->sensor_pwd, 1);
+
+ return rc;
+
+}
+
+static void ov5640_probe_free_gpio(const struct msm_camera_sensor_info *data)
+{
+ gpio_free(ov5640_pwdn_gpio);
+ gpio_free(ov5640_reset_gpio);
+
+ if (data->vcm_enable) {
+ gpio_free(ov5640_driver_pwdn_gpio);
+ ov5640_driver_pwdn_gpio = 0xFF ;
+ }
+
+ ov5640_pwdn_gpio = 0xFF;
+ ov5640_reset_gpio = 0xFF;
+}
+
+static int ov5640_sensor_probe(const struct msm_camera_sensor_info *info,
+ struct msm_sensor_ctrl *s)
+{
+ int rc = -ENOTSUPP;
+
+ CDBG("--CAMERA-- %s (Start...)\n", __func__);
+ rc = i2c_add_driver(&ov5640_i2c_driver);
+ CDBG("--CAMERA-- i2c_add_driver ret:0x%x,ov5640_client=0x%x\n",
+ rc, (unsigned int)ov5640_client);
+ if ((rc < 0) || (ov5640_client == NULL)) {
+ CDBG("--CAMERA-- i2c_add_driver FAILS!!\n");
+ return rc;
+ }
+
+ rc = ov5640_probe_init_gpio(info);
+ if (rc < 0)
+ return rc;
+
+ ov5640_power_off();
+
+ /* SENSOR NEED MCLK TO DO I2C COMMUNICTION, OPEN CLK FIRST*/
+ msm_camio_clk_rate_set(24000000);
+
+ msleep(20);
+
+ ov5640_power_on();
+ ov5640_power_reset();
+
+ rc = ov5640_probe_readID(info);
+
+ if (rc < 0) {
+ CDBG("--CAMERA--ov5640_probe_readID Fail !!~~~~!!\n");
+ CDBG("--CAMERA-- %s, unregister\n", __func__);
+ i2c_del_driver(&ov5640_i2c_driver);
+ ov5640_power_off();
+ ov5640_probe_free_gpio(info);
+ return rc;
+ }
+
+ s->s_init = ov5640_sensor_open_init;
+ s->s_release = ov5640_sensor_release;
+ s->s_config = ov5640_sensor_config;
+ s->s_camera_type = BACK_CAMERA_2D;
+ s->s_mount_angle = info->sensor_platform_info->mount_angle;
+
+ ov5640_power_off();
+
+ CDBG("--CAMERA-- %s (End...)\n", __func__);
+ return rc;
+}
+
+static int ov5640_i2c_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ CDBG("--CAMERA-- %s ... (Start...)\n", __func__);
+
+ if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
+ CDBG("--CAMERA--i2c_check_functionality failed\n");
+ return -ENOMEM;
+ }
+
+ ov5640_sensorw = kzalloc(sizeof(struct ov5640_work), GFP_KERNEL);
+ if (!ov5640_sensorw) {
+ CDBG("--CAMERA--kzalloc failed\n");
+ return -ENOMEM;
+ }
+
+ i2c_set_clientdata(client, ov5640_sensorw);
+ ov5640_init_client(client);
+ ov5640_client = client;
+
+ CDBG("--CAMERA-- %s ... (End...)\n", __func__);
+ return 0;
+}
+
+static int __ov5640_probe(struct platform_device *pdev)
+{
+ return msm_camera_drv_start(pdev, ov5640_sensor_probe);
+}
+
+static struct platform_driver msm_camera_driver = {
+ .probe = __ov5640_probe,
+ .driver = {
+ .name = "msm_camera_ov5640",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init ov5640_init(void)
+{
+ ov5640_i2c_buf[0] = 0x5A;
+ return platform_driver_register(&msm_camera_driver);
+}
+
+module_init(ov5640_init);
+
+MODULE_DESCRIPTION("OV5640 YUV MIPI sensor driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/video/msm/ov5640.h b/drivers/media/video/msm/ov5640.h
new file mode 100644
index 0000000..0e65329
--- /dev/null
+++ b/drivers/media/video/msm/ov5640.h
@@ -0,0 +1,2993 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+/*
+[SENSOR]
+Sensor Model: OV5640
+Camera Module:
+Lens Model:
+Driver IC:
+PV Size = 640 x 480
+Cap Size = 2592 x 1944
+Output Format = YUYV
+MCLK Speed = 24M
+PV DVP_PCLK = 28M
+Cap DVP_PCLK = 56M
+PV Frame Rate = 30fps
+Cap Frame Rate = 7.5fps
+I2C Slave ID = 0x78
+I2C Mode = 16Addr, 8Data
+*/
+
+#ifndef CAMSENSOR_OV5640
+#define CAMSENSOR_OV5640
+
+#define INVMASK(v) (0xff-v)
+#define OV5640CORE_WRITEPREG(PTBL) ov5640_writepregs(PTBL,\
+ sizeof(PTBL)/sizeof(PTBL[0]))
+
+/* OV SENSOR SCCB */
+struct ov5640_sensor {
+ uint16_t addr;
+ uint8_t data;
+ uint8_t mask;
+};
+
+/* Auto Focus Command */
+#define OV5640_CMD_MAIN 0x3022
+#define OV5640_CMD_ACK 0x3023
+#define OV5640_CMD_PARA0 0x3024
+#define OV5640_CMD_PARA1 0x3025
+#define OV5640_CMD_PARA2 0x3026
+#define OV5640_CMD_PARA3 0x3027
+#define OV5640_CMD_PARA4 0x3028
+#define OV5640_CMD_FW_STATUS 0x3029
+
+/* Sensor ID */
+#define OV5640_SENSOR_ID 0x5640
+
+#define capture_framerate 750 /* 7.5fps capture frame rate */
+#define g_preview_frameRate 3000 /* 30fps preview frame rate */
+
+struct ov5640_sensor ov5640_init_tbl[] = {
+ {0x3008, 0x42},
+ {0x3103, 0x03},
+ {0x3017, 0x00},
+ {0x3018, 0x00},
+ {0x3034, 0x18},
+ {0x3035, 0x14},
+ {0x3036, 0x38},
+ {0x3037, 0x13},
+ {0x3108, 0x01},
+ {0x3630, 0x36},
+ {0x3631, 0x0e},
+ {0x3632, 0xe2},
+ {0x3633, 0x12},
+ {0x3621, 0xe0},
+ {0x3704, 0xa0},
+ {0x3703, 0x5a},
+ {0x3715, 0x78},
+ {0x3717, 0x01},
+ {0x370b, 0x60},
+ {0x3705, 0x1a},
+ {0x3905, 0x02},
+ {0x3906, 0x10},
+ {0x3901, 0x0a},
+ {0x3731, 0x12},
+ {0x3600, 0x08},
+ {0x3601, 0x33},
+ {0x302d, 0x60},
+ {0x3620, 0x52},
+ {0x371b, 0x20},
+ {0x471c, 0x50},
+ {0x3a13, 0x43},
+ {0x3a18, 0x00},
+ {0x3a19, 0xf8},
+ {0x3635, 0x13},
+ {0x3636, 0x03},
+ {0x3634, 0x40},
+ {0x3622, 0x01},
+ {0x3c01, 0x34},
+ {0x3c04, 0x28},
+ {0x3c05, 0x98},
+ {0x3c06, 0x00},
+ {0x3c07, 0x08},
+ {0x3c08, 0x00},
+ {0x3c09, 0x1c},
+ {0x3c0a, 0x9c},
+ {0x3c0b, 0x40},
+ {0x3820, 0x41},
+ {0x3821, 0x07},
+ {0x3814, 0x31},
+ {0x3815, 0x31},
+ {0x3800, 0x00},
+ {0x3801, 0x00},
+ {0x3802, 0x00},
+ {0x3803, 0x04},
+ {0x3804, 0x0a},
+ {0x3805, 0x3f},
+ {0x3806, 0x07},
+ {0x3807, 0x9b},
+ {0x3808, 0x02},
+ {0x3809, 0x80},
+ {0x380a, 0x01},
+ {0x380b, 0xe0},
+ {0x380c, 0x07},
+ {0x380d, 0x68},
+ {0x380e, 0x03},
+ {0x380f, 0xd8},
+ {0x3810, 0x00},
+ {0x3811, 0x10},
+ {0x3812, 0x00},
+ {0x3813, 0x06},
+ {0x3618, 0x00},
+ {0x3612, 0x29},
+ {0x3708, 0x64},
+ {0x3709, 0x52},
+ {0x370c, 0x03},
+ {0x3a02, 0x03},
+ {0x3a03, 0xd8},
+ {0x3a08, 0x01},
+ {0x3a09, 0x27},
+ {0x3a0a, 0x00},
+ {0x3a0b, 0xf6},
+ {0x3a0e, 0x03},
+ {0x3a0d, 0x04},
+ {0x3a14, 0x03},
+ {0x3a15, 0xd8},
+ {0x4001, 0x02},
+ {0x4004, 0x02},
+ {0x3000, 0x00},
+ {0x3002, 0x1c},
+ {0x3004, 0xff},
+ {0x3006, 0xc3},
+ {0x300e, 0x45},
+ {0x302e, 0x08},
+ {0x4300, 0x30},
+ {0x501f, 0x00},
+ {0x4713, 0x03},
+ {0x4407, 0x04},
+ {0x440e, 0x00},
+ {0x460b, 0x35},
+ {0x460c, 0x22},
+ {0x4837, 0x44},
+ {0x3824, 0x02},
+ {0x5000, 0xa7},
+ {0x5001, 0xa3},
+ {0x5180, 0xff},
+ {0x5181, 0xf2},
+ {0x5182, 0x00},
+ {0x5183, 0x14},
+ {0x5184, 0x25},
+ {0x5185, 0x24},
+ {0x5186, 0x09},
+ {0x5187, 0x09},
+ {0x5188, 0x09},
+ {0x5189, 0x75},
+ {0x518a, 0x54},
+ {0x518b, 0xe0},
+ {0x518c, 0xb2},
+ {0x518d, 0x42},
+ {0x518e, 0x3d},
+ {0x518f, 0x56},
+ {0x5190, 0x46},
+ {0x5191, 0xf8},
+ {0x5192, 0x04},
+ {0x5193, 0x70},
+ {0x5194, 0xf0},
+ {0x5195, 0xf0},
+ {0x5196, 0x03},
+ {0x5197, 0x01},
+ {0x5198, 0x04},
+ {0x5199, 0x12},
+ {0x519a, 0x04},
+ {0x519b, 0x00},
+ {0x519c, 0x06},
+ {0x519d, 0x82},
+ {0x519e, 0x38},
+ {0x5381, 0x1e},
+ {0x5382, 0x5b},
+ {0x5383, 0x08},
+ {0x5384, 0x0a},
+ {0x5385, 0x7e},
+ {0x5386, 0x88},
+ {0x5387, 0x7c},
+ {0x5388, 0x6c},
+ {0x5389, 0x10},
+ {0x538a, 0x01},
+ {0x538b, 0x98},
+ {0x5300, 0x08},
+ {0x5301, 0x30},
+ {0x5302, 0x10},
+ {0x5303, 0x00},
+ {0x5304, 0x08},
+ {0x5305, 0x30},
+ {0x5306, 0x08},
+ {0x5307, 0x16},
+ {0x5309, 0x08},
+ {0x530a, 0x30},
+ {0x530b, 0x04},
+ {0x530c, 0x06},
+ {0x5480, 0x01},
+ {0x5481, 0x08},
+ {0x5482, 0x14},
+ {0x5483, 0x28},
+ {0x5484, 0x51},
+ {0x5485, 0x65},
+ {0x5486, 0x71},
+ {0x5487, 0x7d},
+ {0x5488, 0x87},
+ {0x5489, 0x91},
+ {0x548a, 0x9a},
+ {0x548b, 0xaa},
+ {0x548c, 0xb8},
+ {0x548d, 0xcd},
+ {0x548e, 0xdd},
+ {0x548f, 0xea},
+ {0x5490, 0x1d},
+ {0x5580, 0x02},
+ {0x5583, 0x40},
+ {0x5584, 0x10},
+ {0x5589, 0x10},
+ {0x558a, 0x00},
+ {0x558b, 0xf8},
+ {0x5800, 0x23},
+ {0x5801, 0x14},
+ {0x5802, 0x0f},
+ {0x5803, 0x0f},
+ {0x5804, 0x12},
+ {0x5805, 0x26},
+ {0x5806, 0x0c},
+ {0x5807, 0x08},
+ {0x5808, 0x05},
+ {0x5809, 0x05},
+ {0x580a, 0x08},
+ {0x580b, 0x0d},
+ {0x580c, 0x08},
+ {0x580d, 0x03},
+ {0x580e, 0x00},
+ {0x580f, 0x00},
+ {0x5810, 0x03},
+ {0x5811, 0x09},
+ {0x5812, 0x07},
+ {0x5813, 0x03},
+ {0x5814, 0x00},
+ {0x5815, 0x01},
+ {0x5816, 0x03},
+ {0x5817, 0x08},
+ {0x5818, 0x0d},
+ {0x5819, 0x08},
+ {0x581a, 0x05},
+ {0x581b, 0x06},
+ {0x581c, 0x08},
+ {0x581d, 0x0e},
+ {0x581e, 0x29},
+ {0x581f, 0x17},
+ {0x5820, 0x11},
+ {0x5821, 0x11},
+ {0x5822, 0x15},
+ {0x5823, 0x28},
+ {0x5824, 0x46},
+ {0x5825, 0x26},
+ {0x5826, 0x08},
+ {0x5827, 0x26},
+ {0x5828, 0x64},
+ {0x5829, 0x26},
+ {0x582a, 0x24},
+ {0x582b, 0x22},
+ {0x582c, 0x24},
+ {0x582d, 0x24},
+ {0x582e, 0x06},
+ {0x582f, 0x22},
+ {0x5830, 0x40},
+ {0x5831, 0x42},
+ {0x5832, 0x24},
+ {0x5833, 0x26},
+ {0x5834, 0x24},
+ {0x5835, 0x22},
+ {0x5836, 0x22},
+ {0x5837, 0x26},
+ {0x5838, 0x44},
+ {0x5839, 0x24},
+ {0x583a, 0x26},
+ {0x583b, 0x28},
+ {0x583c, 0x42},
+ {0x583d, 0xce},
+ {0x5025, 0x00},
+ {0x3a0f, 0x30},
+ {0x3a10, 0x28},
+ {0x3a1b, 0x30},
+ {0x3a1e, 0x26},
+ {0x3a11, 0x60},
+ {0x3a1f, 0x14},
+ {0x3008, 0x02},
+};
+
+struct ov5640_sensor ov5640_init_iq_tbl[] = {
+/* Lens correction */
+/* OV5640 LENC setting */
+ {0x5800, 0x3f},
+ {0x5801, 0x20},
+ {0x5802, 0x1a},
+ {0x5803, 0x1a},
+ {0x5804, 0x23},
+ {0x5805, 0x3f},
+ {0x5806, 0x11},
+ {0x5807, 0x0c},
+ {0x5808, 0x09},
+ {0x5809, 0x08},
+ {0x580a, 0x0d},
+ {0x580b, 0x12},
+ {0x580c, 0x0d},
+ {0x580d, 0x04},
+ {0x580e, 0x00},
+ {0x580f, 0x00},
+ {0x5810, 0x05},
+ {0x5811, 0x0d},
+ {0x5812, 0x0d},
+ {0x5813, 0x04},
+ {0x5814, 0x00},
+ {0x5815, 0x00},
+ {0x5816, 0x04},
+ {0x5817, 0x0d},
+ {0x5818, 0x13},
+ {0x5819, 0x0d},
+ {0x581a, 0x08},
+ {0x581b, 0x08},
+ {0x581c, 0x0c},
+ {0x581d, 0x13},
+ {0x581e, 0x3f},
+ {0x581f, 0x1f},
+ {0x5820, 0x1b},
+ {0x5821, 0x1c},
+ {0x5822, 0x23},
+ {0x5823, 0x3f},
+ {0x5824, 0x6a},
+ {0x5825, 0x06},
+ {0x5826, 0x08},
+ {0x5827, 0x06},
+ {0x5828, 0x2a},
+ {0x5829, 0x08},
+ {0x582a, 0x24},
+ {0x582b, 0x24},
+ {0x582c, 0x24},
+ {0x582d, 0x08},
+ {0x582e, 0x08},
+ {0x582f, 0x22},
+ {0x5830, 0x40},
+ {0x5831, 0x22},
+ {0x5832, 0x06},
+ {0x5833, 0x08},
+ {0x5834, 0x24},
+ {0x5835, 0x24},
+ {0x5836, 0x04},
+ {0x5837, 0x0a},
+ {0x5838, 0x86},
+ {0x5839, 0x08},
+ {0x583a, 0x28},
+ {0x583b, 0x28},
+ {0x583c, 0x66},
+ {0x583d, 0xce},
+/* AEC */
+ {0x3a0f, 0x38},
+ {0x3a10, 0x30},
+ {0x3a11, 0x61},
+ {0x3a1b, 0x38},
+ {0x3a1e, 0x30},
+ {0x3a1f, 0x10},
+ /* AWB */
+ {0x5180, 0xff},
+ {0x5181, 0xf2},
+ {0x5182, 0x00},
+ {0x5183, 0x14},
+ {0x5184, 0x25},
+ {0x5185, 0x24},
+ {0x5186, 0x09},
+ {0x5187, 0x09},
+ {0x5188, 0x09},
+ {0x5189, 0x88},
+ {0x518a, 0x54},
+ {0x518b, 0xee},
+ {0x518c, 0xb2},
+ {0x518d, 0x50},
+ {0x518e, 0x34},
+ {0x518f, 0x6b},
+ {0x5190, 0x46},
+ {0x5191, 0xf8},
+ {0x5192, 0x04},
+ {0x5193, 0x70},
+ {0x5194, 0xf0},
+ {0x5195, 0xf0},
+ {0x5196, 0x03},
+ {0x5197, 0x01},
+ {0x5198, 0x04},
+ {0x5199, 0x6c},
+ {0x519a, 0x04},
+ {0x519b, 0x00},
+ {0x519c, 0x09},
+ {0x519d, 0x2b},
+ {0x519e, 0x38},
+
+/* UV Adjust Auto Mode */
+ {0x5580, 0x02}, /* 02 ;Sat enable */
+ {0x5588, 0x01}, /*40 ;enable UV adj */
+ {0x5583, 0x40}, /* ;offset high */
+ {0x5584, 0x18}, /* ;offset low */
+ {0x5589, 0x18}, /* ;gth1 */
+ {0x558a, 0x00},
+ {0x358b, 0xf8}, /* ;gth2 */
+};
+
+struct ov5640_sensor ov5640_preview_tbl[] = {
+/* @@ MIPI_2lane_5M to vga(YUV) 30fps 99 640 480 98 0 0 */
+ {0x3503, 0x00}, /* enable AE back from capture to preview */
+ {0x3035, 0x14},
+ {0x3036, 0x38},
+ {0x3820, 0x41},
+ {0x3821, 0x07},
+ {0x3814, 0x31},
+ {0x3815, 0x31},
+ {0x3803, 0x04},
+ {0x3807, 0x9b},
+ {0x3808, 0x02},
+ {0x3809, 0x80},
+ {0x380a, 0x01},
+ {0x380b, 0xe0},
+ {0x380c, 0x07},
+ {0x380d, 0x68},
+ {0x380e, 0x03},
+ {0x380f, 0xd8},
+ {0x3813, 0x06},
+ {0x3618, 0x00},
+ {0x3612, 0x29},
+ {0x3708, 0x64},
+ {0x3709, 0x52},
+ {0x370c, 0x03},
+ {0x5001, 0xa3},
+ {0x4004, 0x02},
+ {0x4005, 0x18},
+ {0x4837, 0x44},
+ {0x4713, 0x03},
+ {0x4407, 0x04},
+ {0x460b, 0x35},
+ {0x460c, 0x22},
+ {0x3824, 0x02},
+};
+
+struct ov5640_sensor ov5640_capture_tbl[] = {
+/* @@ MIPI_2lane_5M(YUV) 7.5/15fps 99 2592 1944 98 0 0 */
+ {0x3035, 0x21}, /* 11 */
+ {0x3036, 0x54},
+ {0x3820, 0x40},
+ {0x3821, 0x06},
+ {0x3814, 0x11},
+ {0x3815, 0x11},
+ {0x3803, 0x00},
+ {0x3807, 0x9f},
+ {0x3808, 0x0a},
+ {0x3809, 0x20},
+ {0x380a, 0x07},
+ {0x380b, 0x98},
+ {0x380c, 0x0b},
+ {0x380d, 0x1c},
+ {0x380e, 0x07},
+ {0x380f, 0xb0},
+ {0x3813, 0x04},
+ {0x3618, 0x04},
+ {0x3612, 0x2b},
+ {0x3708, 0x21},
+ {0x3709, 0x12},
+ {0x370c, 0x00},
+ {0x5001, 0x83},
+ {0x4004, 0x06},
+ {0x4005, 0x1a},
+ {0x4837, 0x15}, /* 0a */
+ {0x4713, 0x02},
+ {0x4407, 0x0c},
+ {0x460b, 0x37},
+ {0x460c, 0x20},
+ {0x3824, 0x01},
+};
+
+/* Contrast */
+
+struct ov5640_sensor ov5640_contrast_lv0_tbl[] = {
+/* Contrast -4 */
+ {0x5001, 0x83, INVMASK(0x80)},
+ {0x5580, 0x04, INVMASK(0x04)}, /* Enable BIT2 for contrast/brightness
+ control*/
+ {0x5586, 0x10}, /* Gain */
+ {0x5585, 0x10}, /* Offset */
+ {0x5588, 0x00, INVMASK(0x04)}, /* Offset sign */
+};
+
+struct ov5640_sensor ov5640_contrast_lv1_tbl[] = {
+/* Contrast -3 */
+ {0x5001, 0x83, INVMASK(0x80)},
+ {0x5580, 0x04, INVMASK(0x04)}, /* Enable BIT2 for contrast/brightness
+ control */
+ {0x5586, 0x14}, /* Gain */
+ {0x5585, 0x14}, /* Offset */
+ {0x5588, 0x00, INVMASK(0x04)}, /* Offset sign */
+};
+
+struct ov5640_sensor ov5640_contrast_lv2_tbl[] = {
+/* Contrast -2 */
+ {0x5001, 0x83, INVMASK(0x80)},
+ {0x5580, 0x04, INVMASK(0x04)}, /* Enable BIT2 for contrast/brightness
+ control */
+ {0x5586, 0x18}, /* Gain */
+ {0x5585, 0x18}, /* Offset */
+ {0x5588, 0x00, INVMASK(0x04)}, /* Offset sign */
+};
+
+struct ov5640_sensor ov5640_contrast_lv3_tbl[] = {
+/* Contrast -1 */
+ {0x5001, 0x83, INVMASK(0x80)},
+ {0x5580, 0x04, INVMASK(0x04)},
+ {0x5586, 0x1c},
+ {0x5585, 0x1c},
+ {0x5588, 0x00, INVMASK(0x04)},
+};
+
+struct ov5640_sensor ov5640_contrast_default_lv4_tbl[] = {
+/* Contrast (Default) */
+ {0x5001, 0x83, INVMASK(0x80)},
+ {0x5580, 0x04, INVMASK(0x04)},
+ {0x5586, 0x20},
+ {0x5585, 0x00},
+ {0x5588, 0x00, INVMASK(0x04)},
+};
+
+struct ov5640_sensor ov5640_contrast_lv5_tbl[] = {
+/* Contrast +1 */
+ {0x5001, 0x83, INVMASK(0x80)},
+ {0x5580, 0x04, INVMASK(0x04)},
+ {0x5586, 0x24},
+ {0x5585, 0x10},
+ {0x5588, 0x00, INVMASK(0x04)},
+};
+
+struct ov5640_sensor ov5640_contrast_lv6_tbl[] = {
+/* Contrast +2 */
+ {0x5001, 0x83, INVMASK(0x80)},
+ {0x5580, 0x04, INVMASK(0x04)},
+ {0x5586, 0x28},
+ {0x5585, 0x18},
+ {0x5588, 0x00, INVMASK(0x04)},
+};
+
+struct ov5640_sensor ov5640_contrast_lv7_tbl[] = {
+/* Contrast +3 */
+ {0x5001, 0x83, INVMASK(0x80)},
+ {0x5580, 0x04, INVMASK(0x04)},
+ {0x5586, 0x2c},
+ {0x5585, 0x1c},
+ {0x5588, 0x00, INVMASK(0x04)},
+};
+
+struct ov5640_sensor ov5640_contrast_lv8_tbl[] = {
+/* Contrast +4 */
+ {0x5001, 0x83, INVMASK(0x80)},
+ {0x5580, 0x04, INVMASK(0x04)},
+ {0x5586, 0x30},
+ {0x5585, 0x20},
+ {0x5588, 0x00, INVMASK(0x04)},
+};
+
+/* Sharpness */
+
+struct ov5640_sensor ov5640_sharpness_lv0_tbl[] = {
+/* Sharpness 0 */
+ {0x5308, 0x40, INVMASK(0x40)},
+ {0x5302, 0x00},
+};
+
+struct ov5640_sensor ov5640_sharpness_lv1_tbl[] = {
+/* Sharpness 1 */
+ {0x5308, 0x40, INVMASK(0x40)},
+ {0x5302, 0x02},
+};
+
+struct ov5640_sensor ov5640_sharpness_default_lv2_tbl[] = {
+/* Sharpness_Auto (Default) */
+ {0x5308, 0x00, INVMASK(0x40)},
+ {0x5300, 0x08},
+ {0x5301, 0x30},
+ {0x5302, 0x10},
+ {0x5303, 0x00},
+ {0x5309, 0x08},
+ {0x530a, 0x30},
+ {0x530b, 0x04},
+ {0x530c, 0x06},
+};
+
+struct ov5640_sensor ov5640_sharpness_lv3_tbl[] = {
+/* Sharpness 3 */
+ {0x5308, 0x40, INVMASK(0x40)},
+ {0x5302, 0x08},
+};
+
+struct ov5640_sensor ov5640_sharpness_lv4_tbl[] = {
+/* Sharpness 4 */
+ {0x5308, 0x40, INVMASK(0x40)},
+ {0x5302, 0x0c},
+};
+
+struct ov5640_sensor ov5640_sharpness_lv5_tbl[] = {
+/* Sharpness 5 */
+ {0x5308, 0x40, INVMASK(0x40)},
+ {0x5302, 0x10},
+};
+
+struct ov5640_sensor ov5640_sharpness_lv6_tbl[] = {
+/* Sharpness 6 */
+ {0x5308, 0x40, INVMASK(0x40)},
+ {0x5302, 0x14},
+};
+
+struct ov5640_sensor ov5640_sharpness_lv7_tbl[] = {
+/* Sharpness 7 */
+ {0x5308, 0x40, INVMASK(0x40)},
+ {0x5302, 0x18},
+};
+
+struct ov5640_sensor ov5640_sharpness_lv8_tbl[] = {
+/* Sharpness 8 */
+ {0x5308, 0x40, INVMASK(0x40)},
+ {0x5302, 0x20},
+};
+
+/* Saturation */
+
+struct ov5640_sensor ov5640_saturation_lv0_tbl[] = {
+/* Saturation x0.25 */
+ {0x5001, 0x83, INVMASK(0x80)}, /* SDE_En */
+ {0x5583, 0x00}, /* Saturaion gain in U */
+ {0x5584, 0x00}, /* Saturation gain in V */
+ {0x5580, 0x02, INVMASK(0x02)}, /* Saturation enable */
+ {0x5588, 0x40, INVMASK(0x40)},
+};
+
+struct ov5640_sensor ov5640_saturation_lv1_tbl[] = {
+/* Saturation x0.5 */
+ {0x5001, 0x83, INVMASK(0x80)},
+ {0x5583, 0x10},
+ {0x5584, 0x10},
+ {0x5580, 0x02, INVMASK(0x02)},
+ {0x5588, 0x40, INVMASK(0x40)},
+};
+
+struct ov5640_sensor ov5640_saturation_lv2_tbl[] = {
+/* Saturation x0.75 */
+ {0x5001, 0x83, INVMASK(0x80)},
+ {0x5583, 0x20},
+ {0x5584, 0x20},
+ {0x5580, 0x02, INVMASK(0x02)},
+ {0x5588, 0x40, INVMASK(0x40)},
+};
+
+struct ov5640_sensor ov5640_saturation_lv3_tbl[] = {
+/* Saturation x0.75 */
+ {0x5001, 0x83, INVMASK(0x80)},
+ {0x5583, 0x30},
+ {0x5584, 0x30},
+ {0x5580, 0x02, INVMASK(0x02)},
+ {0x5588, 0x40, INVMASK(0x40)},
+};
+
+struct ov5640_sensor ov5640_saturation_default_lv4_tbl[] = {
+/* Saturation x1 (Default) */
+ {0x5001, 0x83, INVMASK(0x80)},
+ {0x5583, 0x40},
+ {0x5584, 0x40},
+ {0x5580, 0x02, INVMASK(0x02)},
+ {0x5588, 0x40, INVMASK(0x40)},
+};
+
+struct ov5640_sensor ov5640_saturation_lv5_tbl[] = {
+/* Saturation x1.25 */
+ {0x5001, 0x83, INVMASK(0x80)},
+ {0x5583, 0x50},
+ {0x5584, 0x50},
+ {0x5580, 0x02, INVMASK(0x02)},
+ {0x5588, 0x40, INVMASK(0x40)},
+};
+
+struct ov5640_sensor ov5640_saturation_lv6_tbl[] = {
+/* Saturation x1.5 */
+ {0x5001, 0x83, INVMASK(0x80)},
+ {0x5583, 0x60},
+ {0x5584, 0x60},
+ {0x5580, 0x02, INVMASK(0x02)},
+ {0x5588, 0x40, INVMASK(0x40)},
+};
+
+struct ov5640_sensor ov5640_saturation_lv7_tbl[] = {
+/* Saturation x1.25 */
+ {0x5001, 0x83, INVMASK(0x80)},
+ {0x5583, 0x70},
+ {0x5584, 0x70},
+ {0x5580, 0x02, INVMASK(0x02)},
+ {0x5588, 0x40, INVMASK(0x40)},
+};
+
+struct ov5640_sensor ov5640_saturation_lv8_tbl[] = {
+/* Saturation x1.5 */
+ {0x5001, 0x83, INVMASK(0x80)},
+ {0x5583, 0x80},
+ {0x5584, 0x80},
+ {0x5580, 0x02, INVMASK(0x02)},
+ {0x5588, 0x40, INVMASK(0x40)},
+};
+
+/* Brightness */
+
+struct ov5640_sensor ov5640_brightness_lv0_tbl[] = {
+/* Brightness -4 */
+ {0x5001, 0x83, INVMASK(0x80)},
+ {0x5587, 0x40},
+ {0x5580, 0x04, INVMASK(0x04)},
+ {0x5588, 0x08, INVMASK(0x08)},
+};
+
+struct ov5640_sensor ov5640_brightness_lv1_tbl[] = {
+/* Brightness -3 */
+ {0x5001, 0x83, INVMASK(0x80)},
+ {0x5587, 0x30},
+ {0x5580, 0x04, INVMASK(0x04)},
+ {0x5588, 0x08, INVMASK(0x08)},
+};
+
+struct ov5640_sensor ov5640_brightness_lv2_tbl[] = {
+/* Brightness -2 */
+ {0x5001, 0x83, INVMASK(0x80)},
+ {0x5587, 0x20},
+ {0x5580, 0x04, INVMASK(0x04)},
+ {0x5588, 0x08, INVMASK(0x08)},
+};
+
+struct ov5640_sensor ov5640_brightness_lv3_tbl[] = {
+/* Brightness -1 */
+ {0x5001, 0x83, INVMASK(0x80)},
+ {0x5587, 0x10},
+ {0x5580, 0x04, INVMASK(0x04)},
+ {0x5588, 0x08, INVMASK(0x08)},
+};
+
+struct ov5640_sensor ov5640_brightness_default_lv4_tbl[] = {
+/* Brightness 0 (Default) */
+ {0x5001, 0x83, INVMASK(0x80)},
+ {0x5587, 0x00},
+ {0x5580, 0x04, INVMASK(0x04)},
+ {0x5588, 0x00, INVMASK(0x08)},
+};
+
+struct ov5640_sensor ov5640_brightness_lv5_tbl[] = {
+/* Brightness +1 */
+ {0x5001, 0x83, INVMASK(0x80)},
+ {0x5587, 0x10},
+ {0x5580, 0x04, INVMASK(0x04)},
+ {0x5588, 0x00, INVMASK(0x08)},
+};
+
+struct ov5640_sensor ov5640_brightness_lv6_tbl[] = {
+/* Brightness +2 */
+ {0x5001, 0x83, INVMASK(0x80)},
+ {0x5587, 0x20},
+ {0x5580, 0x04, INVMASK(0x04)},
+ {0x5588, 0x00, INVMASK(0x08)},
+};
+
+struct ov5640_sensor ov5640_brightness_lv7_tbl[] = {
+/* Brightness +3 */
+ {0x5001, 0x83, INVMASK(0x80)},
+ {0x5587, 0x30},
+ {0x5580, 0x04, INVMASK(0x04)},
+ {0x5588, 0x00, INVMASK(0x08)},
+};
+
+struct ov5640_sensor ov5640_brightness_lv8_tbl[] = {
+/* Brightness +4 */
+ {0x5001, 0x83, INVMASK(0x80)},
+ {0x5587, 0x40},
+ {0x5580, 0x04, INVMASK(0x04)},
+ {0x5588, 0x00, INVMASK(0x08)},
+};
+
+/* Exposure Compensation */
+struct ov5640_sensor ov5640_exposure_compensation_lv0_tbl[] = {
+ /* @@ +1.7EV */
+ {0x3a0f, 0x60},
+ {0x3a10, 0x58},
+ {0x3a11, 0xa0},
+ {0x3a1b, 0x60},
+ {0x3a1e, 0x58},
+ {0x3a1f, 0x20},
+};
+
+struct ov5640_sensor ov5640_exposure_compensation_lv1_tbl[] = {
+ /* @@ +1.0EV */
+ {0x3a0f, 0x50},
+ {0x3a10, 0x48},
+ {0x3a11, 0x90},
+ {0x3a1b, 0x50},
+ {0x3a1e, 0x48},
+ {0x3a1f, 0x20},
+};
+
+struct ov5640_sensor ov5640_exposure_compensation_lv2_default_tbl[] = {
+ /* @@ default */
+ {0x3a0f, 0x38},
+ {0x3a10, 0x30},
+ {0x3a11, 0x61},
+ {0x3a1b, 0x38},
+ {0x3a1e, 0x30},
+ {0x3a1f, 0x10},
+};
+
+struct ov5640_sensor ov5640_exposure_compensation_lv3_tbl[] = {
+ /* @@ -1.0EV */
+ {0x3a0f, 0x20},
+ {0x3a10, 0x18},
+ {0x3a11, 0x41},
+ {0x3a1b, 0x20},
+ {0x3a1e, 0x18},
+ {0x3a1f, 0x10},
+};
+
+struct ov5640_sensor ov5640_exposure_compensation_lv4_tbl[] = {
+ /* @@ -1.7EV */
+ {0x3a0f, 0x10},
+ {0x3a10, 0x08},
+ {0x3a11, 0x10},
+ {0x3a1b, 0x08},
+ {0x3a1e, 0x20},
+ {0x3a1f, 0x10},
+};
+
+/* Auto Expourse Weight */
+
+struct ov5640_sensor ov5640_ae_average_tbl[] = {
+ /* Whole Image Average */
+ {0x5688, 0x11}, /* Zone 1/Zone 0 weight */
+ {0x5689, 0x11}, /* Zone 3/Zone 2 weight */
+ {0x569a, 0x11}, /* Zone 5/Zone 4 weight */
+ {0x569b, 0x11}, /* Zone 7/Zone 6 weight */
+ {0x569c, 0x11}, /* Zone 9/Zone 8 weight */
+ {0x569d, 0x11}, /* Zone b/Zone a weight */
+ {0x569e, 0x11}, /* Zone d/Zone c weight */
+ {0x569f, 0x11}, /* Zone f/Zone e weight */
+};
+
+struct ov5640_sensor ov5640_ae_centerweight_tbl[] = {
+ /* Whole Image Center More weight */
+ {0x5688, 0x62},
+ {0x5689, 0x26},
+ {0x568a, 0xe6},
+ {0x568b, 0x6e},
+ {0x568c, 0xea},
+ {0x568d, 0xae},
+ {0x568e, 0xa6},
+ {0x568f, 0x6a},
+};
+
+/* Light Mode */
+struct ov5640_sensor ov5640_wb_def[] = {
+ {0x3406, 0x00, INVMASK(0x01)},
+};
+
+struct ov5640_sensor ov5640_wb_custom[] = {
+ {0x3406, 0x01, INVMASK(0x01)},
+ {0x3400, 0x04},
+ {0x3401, 0x58},
+ {0x3402, 0x04},
+ {0x3403, 0x00},
+ {0x3404, 0x08},
+ {0x3405, 0x40},
+};
+
+struct ov5640_sensor ov5640_wb_inc[] = {
+ {0x3406, 0x01, INVMASK(0x01)},
+ {0x3400, 0x04},
+ {0x3401, 0x88},
+ {0x3402, 0x04},
+ {0x3403, 0x00},
+ {0x3404, 0x08},
+ {0x3405, 0xb6},
+};
+
+struct ov5640_sensor ov5640_wb_daylight[] = {
+ {0x3406, 0x01, INVMASK(0x01)},
+ {0x3400, 0x07},
+ {0x3401, 0x02},
+ {0x3402, 0x04},
+ {0x3403, 0x00},
+ {0x3404, 0x05},
+ {0x3405, 0x15},
+};
+
+struct ov5640_sensor ov5640_wb_cloudy[] = {
+ {0x3406, 0x01, INVMASK(0x01)},
+ {0x3400, 0x07},
+ {0x3401, 0x88},
+ {0x3402, 0x04},
+ {0x3403, 0x00},
+ {0x3404, 0x05},
+ {0x3405, 0x00},
+};
+
+/* EFFECT */
+struct ov5640_sensor ov5640_effect_normal_tbl[] = {
+ {0x5001, 0x83, INVMASK(0x80)},
+ {0x5580, 0x00, INVMASK(0x78)},
+ {0x5003, 0x08},
+ {0x5583, 0x40},
+ {0x5584, 0x40},
+};
+
+struct ov5640_sensor ov5640_effect_mono_tbl[] = {
+ {0x5001, 0x83, INVMASK(0x80)},
+ {0x5580, 0x20, INVMASK(0x78)},
+ {0x5003, 0x08},
+ {0x5583, 0x40},
+ {0x5584, 0x40},
+};
+
+struct ov5640_sensor ov5640_effect_bw_tbl[] = {
+ {0x5001, 0x83, INVMASK(0x80)},
+ {0x5580, 0x18, INVMASK(0x78)},
+ {0x5003, 0x08},
+ {0x5583, 0x80},
+ {0x5584, 0x80},
+};
+
+struct ov5640_sensor ov5640_effect_bluish_tbl[] = {
+ {0x5001, 0x83, INVMASK(0x80)},
+ {0x5580, 0x18, INVMASK(0x78)},
+ {0x5003, 0x08},
+ {0x5583, 0xa0},
+ {0x5584, 0x40},
+};
+
+struct ov5640_sensor ov5640_effect_solarize_tbl[] = {
+ {0x5001, 0x83, INVMASK(0x80)},
+ {0x5580, 0x00, INVMASK(0x78)},
+ {0x5003, 0x09},
+};
+
+
+struct ov5640_sensor ov5640_effect_sepia_tbl[] = {
+ {0x5001, 0x83, INVMASK(0x80)},
+ {0x5580, 0x18, INVMASK(0x78)},
+ {0x5003, 0x08},
+ {0x5583, 0x40},
+ {0x5584, 0xa0},
+};
+
+struct ov5640_sensor ov5640_effect_reddish_tbl[] = {
+ {0x5001, 0x83, INVMASK(0x80)},
+ {0x5580, 0x18, INVMASK(0x78)},
+ {0x5003, 0x08},
+ {0x5583, 0x80},
+ {0x5584, 0xc0},
+};
+
+struct ov5640_sensor ov5640_effect_greenish_tbl[] = {
+ {0x5001, 0x83, INVMASK(0x80)},
+ {0x5580, 0x18, INVMASK(0x78)},
+ {0x5003, 0x08},
+ {0x5583, 0x60},
+ {0x5584, 0x60},
+};
+
+struct ov5640_sensor ov5640_effect_negative_tbl[] = {
+ {0x5001, 0x83, INVMASK(0x80)},
+ {0x5580, 0x40, INVMASK(0x78)},
+ {0x5003, 0x08},
+};
+
+/* AntiBanding */
+struct ov5640_sensor ov5640_antibanding_auto_tbl[] = {
+ /* Auto-XCLK24MHz */
+ {0x3622, 0x01}, /* PD-sel */
+ {0x3635, 0x1c}, /* VMREF 3635[2:0] */
+ {0x3634, 0x40}, /* I_5060 3643[2:0] */
+ {0x3c01, 0x34},
+ {0x3c00, 0x00},
+ {0x3c04, 0x28},
+ {0x3c05, 0x98},
+ {0x3c06, 0x00},
+ {0x3c07, 0x08},
+ {0x3c08, 0x00},
+ {0x3c09, 0x1c},
+ {0x300c, 0x22}, /* 50/60div 300c[2:0] */
+ {0x3c0a, 0x9c},
+ {0x3c0b, 0x40},
+};
+
+struct ov5640_sensor ov5640_antibanding_50z_tbl[] = {
+ /* Band 50Hz */
+ {0x3c01, 0x80, INVMASK(0x80)},
+ {0x3c00, 0x04},
+};
+
+struct ov5640_sensor ov5640_antibanding_60z_tbl[] = {
+ /* Band 60Hz */
+ {0x3c01, 0x80, INVMASK(0x80)},
+ {0x3c00, 0x00},
+};
+
+
+/* Lens_shading */
+
+struct ov5640_sensor ov5640_lens_shading_on_tbl[] = {
+ /* @@ Lenc On(C) */
+ {0x5000, 0x80, INVMASK(0x80)},
+};
+
+struct ov5640_sensor ov5640_lens_shading_off_tbl[] = {
+ /* Lenc Off */
+ {0x5000, 0x00, INVMASK(0x80)},
+};
+
+/* Auto Focus Firmware-use 2011-08-24 firmware settings */
+u8 ov5640_afinit_tbl[] = {
+ 0x80, 0x00, 0x02, 0x0b, 0x7b, 0x02, 0x07, 0xbd, 0xc2,
+ 0x01, 0x22, 0x22, 0x00, 0x02, 0x0b, 0x57, 0xe5, 0x1f,
+ 0x70, 0x72, 0xf5, 0x1e, 0xd2, 0x35, 0xff, 0xef, 0x25,
+ 0xe0, 0x24, 0x4b, 0xf8, 0xe4, 0xf6, 0x08, 0xf6, 0x0f,
+ 0xbf, 0x34, 0xf2, 0x90, 0x0e, 0x88, 0xe4, 0x93, 0xff,
+ 0xe5, 0x49, 0xc3, 0x9f, 0x50, 0x04, 0x7f, 0x05, 0x80,
+ 0x02, 0x7f, 0xfb, 0x78, 0xba, 0xa6, 0x07, 0x12, 0x0a,
+ 0xb4, 0x40, 0x04, 0x7f, 0x03, 0x80, 0x02, 0x7f, 0x30,
+ 0x78, 0xb9, 0xa6, 0x07, 0xe6, 0x18, 0xf6, 0x08, 0xe6,
+ 0x78, 0xb6, 0xf6, 0x78, 0xb9, 0xe6, 0x78, 0xb7, 0xf6,
+ 0x78, 0xbc, 0x76, 0x33, 0xe4, 0x08, 0xf6, 0x78, 0xb5,
+ 0x76, 0x01, 0x75, 0x48, 0x02, 0x78, 0xb3, 0xf6, 0x08,
+ 0xf6, 0x74, 0xff, 0x78, 0xbe, 0xf6, 0x08, 0xf6, 0x75,
+ 0x1f, 0x01, 0x78, 0xb9, 0xe6, 0x75, 0xf0, 0x05, 0xa4,
+ 0xf5, 0x49, 0x12, 0x08, 0x5b, 0xc2, 0x37, 0x22, 0x78,
+ 0xb5, 0xe6, 0xd3, 0x94, 0x00, 0x40, 0x02, 0x16, 0x22,
+ 0xe5, 0x1f, 0x64, 0x05, 0x70, 0x28, 0xf5, 0x1f, 0xc2,
+ 0x01, 0x78, 0xb6, 0xe6, 0x25, 0xe0, 0x24, 0x4b, 0xf8,
+ 0xe6, 0xfe, 0x08, 0xe6, 0xff, 0x78, 0x4b, 0xa6, 0x06,
+ 0x08, 0xa6, 0x07, 0xa2, 0x37, 0xe4, 0x33, 0xf5, 0x3c,
+ 0x90, 0x30, 0x28, 0xf0, 0x75, 0x1e, 0x10, 0xd2, 0x35,
+ 0x22, 0xe5, 0x49, 0x75, 0xf0, 0x05, 0x84, 0x78, 0xb9,
+ 0xf6, 0x90, 0x0e, 0x85, 0xe4, 0x93, 0xff, 0x25, 0xe0,
+ 0x24, 0x0a, 0xf8, 0xe6, 0xfc, 0x08, 0xe6, 0xfd, 0x78,
+ 0xb9, 0xe6, 0x25, 0xe0, 0x24, 0x4b, 0xf8, 0xa6, 0x04,
+ 0x08, 0xa6, 0x05, 0xef, 0x12, 0x0a, 0xbb, 0xd3, 0x78,
+ 0xb4, 0x96, 0xee, 0x18, 0x96, 0x40, 0x0d, 0x78, 0xb9,
+ 0xe6, 0x78, 0xb6, 0xf6, 0x78, 0xb3, 0xa6, 0x06, 0x08,
+ 0xa6, 0x07, 0x90, 0x0e, 0x85, 0xe4, 0x93, 0x12, 0x0a,
+ 0xbb, 0xc3, 0x78, 0xbf, 0x96, 0xee, 0x18, 0x96, 0x50,
+ 0x0d, 0x78, 0xb9, 0xe6, 0x78, 0xb7, 0xf6, 0x78, 0xbe,
+ 0xa6, 0x06, 0x08, 0xa6, 0x07, 0x78, 0xb3, 0xe6, 0xfe,
+ 0x08, 0xe6, 0xc3, 0x78, 0xbf, 0x96, 0xff, 0xee, 0x18,
+ 0x96, 0x78, 0xc0, 0xf6, 0x08, 0xa6, 0x07, 0x90, 0x0e,
+ 0x8a, 0xe4, 0x18, 0x12, 0x0a, 0x99, 0xc3, 0x33, 0xce,
+ 0x33, 0xce, 0xd8, 0xf9, 0xff, 0xd3, 0xed, 0x9f, 0xec,
+ 0x9e, 0x40, 0x02, 0xd2, 0x37, 0x78, 0xb9, 0xe6, 0x08,
+ 0x26, 0x08, 0xf6, 0xe5, 0x1f, 0x64, 0x01, 0x70, 0x55,
+ 0xe6, 0xc3, 0x78, 0xbd, 0x12, 0x0a, 0x8f, 0x40, 0x10,
+ 0x12, 0x0a, 0x8a, 0x50, 0x0b, 0x30, 0x37, 0x41, 0x78,
+ 0xb9, 0xe6, 0x78, 0xb6, 0x66, 0x60, 0x39, 0x12, 0x0a,
+ 0xb2, 0x40, 0x04, 0x7f, 0xfe, 0x80, 0x02, 0x7f, 0x02,
+ 0x78, 0xba, 0xa6, 0x07, 0x78, 0xb6, 0xe6, 0x24, 0x03,
+ 0x78, 0xbc, 0xf6, 0x78, 0xb6, 0xe6, 0x24, 0xfd, 0x78,
+ 0xbd, 0xf6, 0x12, 0x0a, 0xb2, 0x40, 0x06, 0x78, 0xbd,
+ 0xe6, 0xff, 0x80, 0x04, 0x78, 0xbc, 0xe6, 0xff, 0x78,
+ 0xbb, 0xa6, 0x07, 0x75, 0x1f, 0x02, 0x78, 0xb5, 0x76,
+ 0x01, 0x02, 0x02, 0x68, 0xe5, 0x1f, 0x64, 0x02, 0x60,
+ 0x03, 0x02, 0x02, 0x48, 0x78, 0xbb, 0xe6, 0xff, 0xc3,
+ 0x78, 0xbd, 0x12, 0x0a, 0x90, 0x40, 0x08, 0x12, 0x0a,
+ 0x8a, 0x50, 0x03, 0x02, 0x02, 0x46, 0x12, 0x0a, 0xb2,
+ 0x40, 0x04, 0x7f, 0xff, 0x80, 0x02, 0x7f, 0x01, 0x78,
+ 0xba, 0xa6, 0x07, 0x78, 0xb6, 0xe6, 0x04, 0x78, 0xbc,
+ 0xf6, 0x78, 0xb6, 0xe6, 0x14, 0x78, 0xbd, 0xf6, 0x18,
+ 0x12, 0x0a, 0xb4, 0x40, 0x04, 0xe6, 0xff, 0x80, 0x02,
+ 0x7f, 0x00, 0x78, 0xbc, 0xa6, 0x07, 0xd3, 0x08, 0xe6,
+ 0x64, 0x80, 0x94, 0x80, 0x40, 0x04, 0xe6, 0xff, 0x80,
+ 0x02, 0x7f, 0x00, 0x78, 0xbd, 0xa6, 0x07, 0xc3, 0x18,
+ 0xe6, 0x64, 0x80, 0x94, 0xb3, 0x50, 0x04, 0xe6, 0xff,
+ 0x80, 0x02, 0x7f, 0x33, 0x78, 0xbc, 0xa6, 0x07, 0xc3,
+ 0x08, 0xe6, 0x64, 0x80, 0x94, 0xb3, 0x50, 0x04, 0xe6,
+ 0xff, 0x80, 0x02, 0x7f, 0x33, 0x78, 0xbd, 0xa6, 0x07,
+ 0x12, 0x0a, 0xb2, 0x40, 0x06, 0x78, 0xbd, 0xe6, 0xff,
+ 0x80, 0x04, 0x78, 0xbc, 0xe6, 0xff, 0x78, 0xbb, 0xa6,
+ 0x07, 0x75, 0x1f, 0x03, 0x78, 0xb5, 0x76, 0x01, 0x80,
+ 0x20, 0xe5, 0x1f, 0x64, 0x03, 0x70, 0x26, 0x78, 0xbb,
+ 0xe6, 0xff, 0xc3, 0x78, 0xbd, 0x12, 0x0a, 0x90, 0x40,
+ 0x05, 0x12, 0x0a, 0x8a, 0x40, 0x09, 0x78, 0xb6, 0xe6,
+ 0x78, 0xbb, 0xf6, 0x75, 0x1f, 0x04, 0x78, 0xbb, 0xe6,
+ 0x75, 0xf0, 0x05, 0xa4, 0xf5, 0x49, 0x02, 0x08, 0x5b,
+ 0xe5, 0x1f, 0xb4, 0x04, 0x1d, 0x90, 0x0e, 0x89, 0xe4,
+ 0x78, 0xc0, 0x12, 0x0a, 0x99, 0xc3, 0x33, 0xce, 0x33,
+ 0xce, 0xd8, 0xf9, 0xff, 0xd3, 0xed, 0x9f, 0xec, 0x9e,
+ 0x40, 0x02, 0xd2, 0x37, 0x75, 0x1f, 0x05, 0x22, 0xef,
+ 0x8d, 0xf0, 0xa4, 0xa8, 0xf0, 0xcf, 0x8c, 0xf0, 0xa4,
+ 0x28, 0xce, 0x8d, 0xf0, 0xa4, 0x2e, 0xfe, 0x22, 0xbc,
+ 0x00, 0x0b, 0xbe, 0x00, 0x29, 0xef, 0x8d, 0xf0, 0x84,
+ 0xff, 0xad, 0xf0, 0x22, 0xe4, 0xcc, 0xf8, 0x75, 0xf0,
+ 0x08, 0xef, 0x2f, 0xff, 0xee, 0x33, 0xfe, 0xec, 0x33,
+ 0xfc, 0xee, 0x9d, 0xec, 0x98, 0x40, 0x05, 0xfc, 0xee,
+ 0x9d, 0xfe, 0x0f, 0xd5, 0xf0, 0xe9, 0xe4, 0xce, 0xfd,
+ 0x22, 0xed, 0xf8, 0xf5, 0xf0, 0xee, 0x84, 0x20, 0xd2,
+ 0x1c, 0xfe, 0xad, 0xf0, 0x75, 0xf0, 0x08, 0xef, 0x2f,
+ 0xff, 0xed, 0x33, 0xfd, 0x40, 0x07, 0x98, 0x50, 0x06,
+ 0xd5, 0xf0, 0xf2, 0x22, 0xc3, 0x98, 0xfd, 0x0f, 0xd5,
+ 0xf0, 0xea, 0x22, 0xe8, 0x8f, 0xf0, 0xa4, 0xcc, 0x8b,
+ 0xf0, 0xa4, 0x2c, 0xfc, 0xe9, 0x8e, 0xf0, 0xa4, 0x2c,
+ 0xfc, 0x8a, 0xf0, 0xed, 0xa4, 0x2c, 0xfc, 0xea, 0x8e,
+ 0xf0, 0xa4, 0xcd, 0xa8, 0xf0, 0x8b, 0xf0, 0xa4, 0x2d,
+ 0xcc, 0x38, 0x25, 0xf0, 0xfd, 0xe9, 0x8f, 0xf0, 0xa4,
+ 0x2c, 0xcd, 0x35, 0xf0, 0xfc, 0xeb, 0x8e, 0xf0, 0xa4,
+ 0xfe, 0xa9, 0xf0, 0xeb, 0x8f, 0xf0, 0xa4, 0xcf, 0xc5,
+ 0xf0, 0x2e, 0xcd, 0x39, 0xfe, 0xe4, 0x3c, 0xfc, 0xea,
+ 0xa4, 0x2d, 0xce, 0x35, 0xf0, 0xfd, 0xe4, 0x3c, 0xfc,
+ 0x22, 0x75, 0xf0, 0x08, 0x75, 0x82, 0x00, 0xef, 0x2f,
+ 0xff, 0xee, 0x33, 0xfe, 0xcd, 0x33, 0xcd, 0xcc, 0x33,
+ 0xcc, 0xc5, 0x82, 0x33, 0xc5, 0x82, 0x9b, 0xed, 0x9a,
+ 0xec, 0x99, 0xe5, 0x82, 0x98, 0x40, 0x0c, 0xf5, 0x82,
+ 0xee, 0x9b, 0xfe, 0xed, 0x9a, 0xfd, 0xec, 0x99, 0xfc,
+ 0x0f, 0xd5, 0xf0, 0xd6, 0xe4, 0xce, 0xfb, 0xe4, 0xcd,
+ 0xfa, 0xe4, 0xcc, 0xf9, 0xa8, 0x82, 0x22, 0xb8, 0x00,
+ 0xc1, 0xb9, 0x00, 0x59, 0xba, 0x00, 0x2d, 0xec, 0x8b,
+ 0xf0, 0x84, 0xcf, 0xce, 0xcd, 0xfc, 0xe5, 0xf0, 0xcb,
+ 0xf9, 0x78, 0x18, 0xef, 0x2f, 0xff, 0xee, 0x33, 0xfe,
+ 0xed, 0x33, 0xfd, 0xec, 0x33, 0xfc, 0xeb, 0x33, 0xfb,
+ 0x10, 0xd7, 0x03, 0x99, 0x40, 0x04, 0xeb, 0x99, 0xfb,
+ 0x0f, 0xd8, 0xe5, 0xe4, 0xf9, 0xfa, 0x22, 0x78, 0x18,
+ 0xef, 0x2f, 0xff, 0xee, 0x33, 0xfe, 0xed, 0x33, 0xfd,
+ 0xec, 0x33, 0xfc, 0xc9, 0x33, 0xc9, 0x10, 0xd7, 0x05,
+ 0x9b, 0xe9, 0x9a, 0x40, 0x07, 0xec, 0x9b, 0xfc, 0xe9,
+ 0x9a, 0xf9, 0x0f, 0xd8, 0xe0, 0xe4, 0xc9, 0xfa, 0xe4,
+ 0xcc, 0xfb, 0x22, 0x75, 0xf0, 0x10, 0xef, 0x2f, 0xff,
+ 0xee, 0x33, 0xfe, 0xed, 0x33, 0xfd, 0xcc, 0x33, 0xcc,
+ 0xc8, 0x33, 0xc8, 0x10, 0xd7, 0x07, 0x9b, 0xec, 0x9a,
+ 0xe8, 0x99, 0x40, 0x0a, 0xed, 0x9b, 0xfd, 0xec, 0x9a,
+ 0xfc, 0xe8, 0x99, 0xf8, 0x0f, 0xd5, 0xf0, 0xda, 0xe4,
+ 0xcd, 0xfb, 0xe4, 0xcc, 0xfa, 0xe4, 0xc8, 0xf9, 0x22,
+ 0xeb, 0x9f, 0xf5, 0xf0, 0xea, 0x9e, 0x42, 0xf0, 0xe9,
+ 0x9d, 0x42, 0xf0, 0xe8, 0x9c, 0x45, 0xf0, 0x22, 0xe8,
+ 0x60, 0x0f, 0xef, 0xc3, 0x33, 0xff, 0xee, 0x33, 0xfe,
+ 0xed, 0x33, 0xfd, 0xec, 0x33, 0xfc, 0xd8, 0xf1, 0x22,
+ 0xe4, 0x93, 0xfc, 0x74, 0x01, 0x93, 0xfd, 0x74, 0x02,
+ 0x93, 0xfe, 0x74, 0x03, 0x93, 0xff, 0x22, 0xe6, 0xfb,
+ 0x08, 0xe6, 0xf9, 0x08, 0xe6, 0xfa, 0x08, 0xe6, 0xcb,
+ 0xf8, 0x22, 0xec, 0xf6, 0x08, 0xed, 0xf6, 0x08, 0xee,
+ 0xf6, 0x08, 0xef, 0xf6, 0x22, 0xa4, 0x25, 0x82, 0xf5,
+ 0x82, 0xe5, 0xf0, 0x35, 0x83, 0xf5, 0x83, 0x22, 0xd0,
+ 0x83, 0xd0, 0x82, 0xf8, 0xe4, 0x93, 0x70, 0x12, 0x74,
+ 0x01, 0x93, 0x70, 0x0d, 0xa3, 0xa3, 0x93, 0xf8, 0x74,
+ 0x01, 0x93, 0xf5, 0x82, 0x88, 0x83, 0xe4, 0x73, 0x74,
+ 0x02, 0x93, 0x68, 0x60, 0xef, 0xa3, 0xa3, 0xa3, 0x80,
+ 0xdf, 0x90, 0x38, 0x04, 0x78, 0x4f, 0x12, 0x09, 0x50,
+ 0x90, 0x38, 0x00, 0xe0, 0xfe, 0xa3, 0xe0, 0xfd, 0xed,
+ 0xff, 0xc3, 0x12, 0x09, 0x09, 0x90, 0x38, 0x10, 0x12,
+ 0x08, 0xfd, 0x90, 0x38, 0x06, 0x78, 0x51, 0x12, 0x09,
+ 0x50, 0x90, 0x38, 0x02, 0xe0, 0xfe, 0xa3, 0xe0, 0xfd,
+ 0xed, 0xff, 0xc3, 0x12, 0x09, 0x09, 0x90, 0x38, 0x12,
+ 0x12, 0x08, 0xfd, 0xa3, 0xe0, 0xb4, 0x31, 0x07, 0x78,
+ 0x4f, 0x79, 0x4f, 0x12, 0x09, 0x66, 0x90, 0x38, 0x14,
+ 0xe0, 0xb4, 0x71, 0x15, 0x78, 0x4f, 0xe6, 0xfe, 0x08,
+ 0xe6, 0x78, 0x02, 0xce, 0xc3, 0x13, 0xce, 0x13, 0xd8,
+ 0xf9, 0x79, 0x50, 0xf7, 0xee, 0x19, 0xf7, 0x90, 0x38,
+ 0x15, 0xe0, 0xb4, 0x31, 0x07, 0x78, 0x51, 0x79, 0x51,
+ 0x12, 0x09, 0x66, 0x90, 0x38, 0x15, 0xe0, 0xb4, 0x71,
+ 0x15, 0x78, 0x51, 0xe6, 0xfe, 0x08, 0xe6, 0x78, 0x02,
+ 0xce, 0xc3, 0x13, 0xce, 0x13, 0xd8, 0xf9, 0x79, 0x52,
+ 0xf7, 0xee, 0x19, 0xf7, 0x79, 0x4f, 0x12, 0x09, 0x38,
+ 0x09, 0x12, 0x09, 0x38, 0xaf, 0x45, 0x12, 0x08, 0xee,
+ 0x7d, 0x50, 0x12, 0x02, 0xa9, 0x78, 0x57, 0xa6, 0x06,
+ 0x08, 0xa6, 0x07, 0xaf, 0x43, 0x12, 0x08, 0xee, 0x7d,
+ 0x50, 0x12, 0x02, 0xa9, 0x78, 0x53, 0xa6, 0x06, 0x08,
+ 0xa6, 0x07, 0xaf, 0x46, 0x78, 0x51, 0x12, 0x08, 0xf0,
+ 0x7d, 0x3c, 0x12, 0x02, 0xa9, 0x78, 0x59, 0xa6, 0x06,
+ 0x08, 0xa6, 0x07, 0xaf, 0x44, 0x7e, 0x00, 0x78, 0x51,
+ 0x12, 0x08, 0xf2, 0x7d, 0x3c, 0x12, 0x02, 0xa9, 0x78,
+ 0x55, 0xa6, 0x06, 0x08, 0xa6, 0x07, 0xc3, 0x78, 0x58,
+ 0xe6, 0x94, 0x08, 0x18, 0xe6, 0x94, 0x00, 0x50, 0x05,
+ 0x76, 0x00, 0x08, 0x76, 0x08, 0xc3, 0x78, 0x5a, 0xe6,
+ 0x94, 0x08, 0x18, 0xe6, 0x94, 0x00, 0x50, 0x05, 0x76,
+ 0x00, 0x08, 0x76, 0x08, 0x78, 0x57, 0x12, 0x09, 0x25,
+ 0xff, 0xd3, 0x78, 0x54, 0xe6, 0x9f, 0x18, 0xe6, 0x9e,
+ 0x40, 0x0e, 0x78, 0x57, 0xe6, 0x13, 0xfe, 0x08, 0xe6,
+ 0x78, 0x54, 0x12, 0x09, 0x5b, 0x80, 0x04, 0x7e, 0x00,
+ 0x7f, 0x00, 0x78, 0x5b, 0x12, 0x09, 0x1d, 0xff, 0xd3,
+ 0x78, 0x56, 0xe6, 0x9f, 0x18, 0xe6, 0x9e, 0x40, 0x0e,
+ 0x78, 0x59, 0xe6, 0x13, 0xfe, 0x08, 0xe6, 0x78, 0x56,
+ 0x12, 0x09, 0x5b, 0x80, 0x04, 0x7e, 0x00, 0x7f, 0x00,
+ 0xe4, 0xfc, 0xfd, 0x78, 0x5f, 0x12, 0x04, 0x5c, 0x78,
+ 0x57, 0x12, 0x09, 0x25, 0x78, 0x54, 0x26, 0xff, 0xee,
+ 0x18, 0x36, 0xfe, 0x78, 0x63, 0x12, 0x09, 0x1d, 0x78,
+ 0x56, 0x26, 0xff, 0xee, 0x18, 0x36, 0xfe, 0xe4, 0xfc,
+ 0xfd, 0x78, 0x67, 0x12, 0x04, 0x5c, 0x12, 0x09, 0x2d,
+ 0x78, 0x63, 0x12, 0x04, 0x4f, 0xd3, 0x12, 0x04, 0x1b,
+ 0x40, 0x08, 0x12, 0x09, 0x2d, 0x78, 0x63, 0x12, 0x04,
+ 0x5c, 0x78, 0x51, 0x12, 0x09, 0x2f, 0x78, 0x67, 0x12,
+ 0x04, 0x4f, 0xd3, 0x12, 0x04, 0x1b, 0x40, 0x0a, 0x78,
+ 0x51, 0x12, 0x09, 0x2f, 0x78, 0x67, 0x12, 0x04, 0x5c,
+ 0xe4, 0xfd, 0x78, 0x5e, 0x12, 0x09, 0x48, 0x24, 0x01,
+ 0x12, 0x09, 0x11, 0x78, 0x62, 0x12, 0x09, 0x48, 0x24,
+ 0x02, 0x12, 0x09, 0x11, 0x78, 0x66, 0x12, 0x09, 0x48,
+ 0x24, 0x03, 0x12, 0x09, 0x11, 0x78, 0x6a, 0x12, 0x09,
+ 0x48, 0x24, 0x04, 0x12, 0x09, 0x11, 0x0d, 0xbd, 0x05,
+ 0xd4, 0xc2, 0x0e, 0xc2, 0x06, 0x22, 0x85, 0x08, 0x41,
+ 0x90, 0x30, 0x24, 0xe0, 0xf5, 0x3d, 0xa3, 0xe0, 0xf5,
+ 0x3e, 0xa3, 0xe0, 0xf5, 0x3f, 0xa3, 0xe0, 0xf5, 0x40,
+ 0xa3, 0xe0, 0xf5, 0x3c, 0xd2, 0x34, 0xe5, 0x41, 0x12,
+ 0x04, 0x74, 0x06, 0xc7, 0x03, 0x06, 0xcb, 0x04, 0x06,
+ 0xd1, 0x07, 0x06, 0xda, 0x08, 0x06, 0xeb, 0x12, 0x07,
+ 0x03, 0x18, 0x07, 0x19, 0x19, 0x06, 0xee, 0x1a, 0x06,
+ 0xfa, 0x1b, 0x07, 0x3e, 0x80, 0x07, 0x43, 0x81, 0x07,
+ 0xa1, 0x8f, 0x07, 0x90, 0x90, 0x07, 0xa1, 0x91, 0x07,
+ 0xa1, 0x92, 0x07, 0xa1, 0x93, 0x07, 0xa1, 0x94, 0x07,
+ 0xa1, 0x98, 0x07, 0x9e, 0x9f, 0x00, 0x00, 0x07, 0xbc,
+ 0x12, 0x0a, 0xf4, 0x22, 0x12, 0x0a, 0xf4, 0xd2, 0x03,
+ 0x22, 0xa2, 0x37, 0xe4, 0x33, 0xf5, 0x3c, 0x02, 0x07,
+ 0xa1, 0xc2, 0x01, 0xc2, 0x02, 0xc2, 0x03, 0x12, 0x09,
+ 0x70, 0x75, 0x1e, 0x70, 0xd2, 0x35, 0x02, 0x07, 0xa1,
+ 0x02, 0x07, 0x8b, 0x85, 0x40, 0x48, 0x85, 0x3c, 0x49,
+ 0x12, 0x08, 0x5b, 0x02, 0x07, 0xa1, 0x85, 0x48, 0x40,
+ 0x85, 0x49, 0x3c, 0x02, 0x07, 0xa1, 0xe4, 0xf5, 0x22,
+ 0xf5, 0x23, 0x85, 0x40, 0x31, 0x85, 0x3f, 0x30, 0x85,
+ 0x3e, 0x2f, 0x85, 0x3d, 0x2e, 0x12, 0x0a, 0xc6, 0x80,
+ 0x1f, 0x75, 0x22, 0x00, 0x75, 0x23, 0x01, 0x74, 0xff,
+ 0xf5, 0x2d, 0xf5, 0x2c, 0xf5, 0x2b, 0xf5, 0x2a, 0x12,
+ 0x0a, 0xc6, 0x85, 0x2d, 0x40, 0x85, 0x2c, 0x3f, 0x85,
+ 0x2b, 0x3e, 0x85, 0x2a, 0x3d, 0xe4, 0xf5, 0x3c, 0x02,
+ 0x07, 0xa1, 0x12, 0x0b, 0x3d, 0x80, 0x5e, 0x85, 0x3d,
+ 0x43, 0x85, 0x3e, 0x44, 0xe5, 0x45, 0xc3, 0x13, 0xff,
+ 0xe5, 0x43, 0xc3, 0x9f, 0x50, 0x02, 0x8f, 0x43, 0xe5,
+ 0x46, 0xc3, 0x13, 0xff, 0xe5, 0x44, 0xc3, 0x9f, 0x50,
+ 0x02, 0x8f, 0x44, 0xe5, 0x45, 0xc3, 0x13, 0xff, 0xfd,
+ 0xe5, 0x43, 0x90, 0x0e, 0x7f, 0x12, 0x0b, 0x10, 0x40,
+ 0x04, 0xee, 0x9f, 0xf5, 0x43, 0xe5, 0x46, 0xc3, 0x13,
+ 0xff, 0xfd, 0xe5, 0x44, 0x90, 0x0e, 0x80, 0x12, 0x0b,
+ 0x10, 0x40, 0x04, 0xee, 0x9f, 0xf5, 0x44, 0x12, 0x04,
+ 0x9a, 0x80, 0x11, 0x85, 0x40, 0x46, 0x85, 0x3f, 0x45,
+ 0x85, 0x3e, 0x44, 0x85, 0x3d, 0x43, 0x80, 0x03, 0x02,
+ 0x04, 0x9a, 0x90, 0x30, 0x24, 0xe5, 0x3d, 0xf0, 0xa3,
+ 0xe5, 0x3e, 0xf0, 0xa3, 0xe5, 0x3f, 0xf0, 0xa3, 0xe5,
+ 0x40, 0xf0, 0xa3, 0xe5, 0x3c, 0xf0, 0x90, 0x30, 0x23,
+ 0xe4, 0xf0, 0x22, 0xc0, 0xe0, 0xc0, 0x83, 0xc0, 0x82,
+ 0xc0, 0xd0, 0x90, 0x3f, 0x0c, 0xe0, 0xf5, 0x32, 0xe5,
+ 0x32, 0x30, 0xe3, 0x4c, 0x30, 0x36, 0x3e, 0x90, 0x60,
+ 0x19,
+ 0xe0,
+ 0xf5,
+ 0x0a,
+ 0xa3,
+ 0xe0,
+ 0xf5,
+ 0x0b,
+ 0x90,
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+ 0x1d,
+ 0xe0,
+ 0xf5,
+ 0x14,
+ 0xa3,
+ 0xe0,
+ 0xf5,
+ 0x15,
+ 0x30,
+ 0x01,
+ 0x06,
+ 0x30,
+ 0x33,
+ 0x03,
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+ 0xc3,
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+ 0x02,
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+ 0x01,
+ 0x03,
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+ 0x01,
+ 0xc3,
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+ 0x90,
+ 0x30,
+ 0x01,
+ 0xe0,
+ 0x44,
+ 0x40,
+ 0xf0,
+ 0xe0,
+ 0x54,
+ 0xbf,
+ 0xf0,
+ 0xe5,
+ 0x32,
+ 0x30,
+ 0xe1,
+ 0x14,
+ 0x30,
+ 0x34,
+ 0x11,
+ 0x90,
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+ 0x22,
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+ 0x08,
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+ 0x00,
+ 0x03,
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+};
+
+#endif /* CAMSENSOR_OV5640 */
diff --git a/drivers/media/video/msm/ov7692_qrd.c b/drivers/media/video/msm/ov7692_qrd.c
new file mode 100644
index 0000000..e558e57
--- /dev/null
+++ b/drivers/media/video/msm/ov7692_qrd.c
@@ -0,0 +1,679 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* #define DEBUG */
+
+#include <linux/delay.h>
+#include <linux/types.h>
+#include <linux/i2c.h>
+#include <linux/uaccess.h>
+#include <linux/miscdevice.h>
+#include <linux/slab.h>
+#include <media/msm_camera.h>
+#include <mach/camera.h>
+#include <mach/gpio.h>
+#include "ov7692.h"
+
+/*=============================================================
+ SENSOR REGISTER DEFINES
+==============================================================*/
+#define Q8 0x00000100
+
+/* Omnivision8810 product ID register address */
+#define REG_OV7692_MODEL_ID_MSB 0x0A
+#define REG_OV7692_MODEL_ID_LSB 0x0B
+
+#define OV7692_MODEL_ID 0x7692
+/* Omnivision8810 product ID */
+
+/* Time in milisecs for waiting for the sensor to reset */
+#define OV7692_RESET_DELAY_MSECS 66
+#define OV7692_DEFAULT_CLOCK_RATE 24000000
+/* Registers*/
+
+/* Color bar pattern selection */
+#define OV7692_COLOR_BAR_PATTERN_SEL_REG 0x82
+/* Color bar enabling control */
+#define OV7692_COLOR_BAR_ENABLE_REG 0x601
+/* Time in milisecs for waiting for the sensor to reset*/
+#define OV7692_RESET_DELAY_MSECS 66
+
+static int ov7692_pwdn_gpio;
+static int ov7692_reset_gpio;
+
+
+/*============================================================================
+ DATA DECLARATIONS
+ ============================================================================*/
+/* 96MHz PCLK @ 24MHz MCLK */
+struct reg_addr_val_pair_struct ov7692_init_settings_array[] = {
+ {0x12, 0x80},
+ {0x0e, 0x08},
+ {0x69, 0x52},
+ {0x1e, 0xb3},
+ {0x48, 0x42},
+ {0xff, 0x01},
+ {0xae, 0xa0},
+ {0xa8, 0x26},
+ {0xb4, 0xc0},
+ {0xb5, 0x40},
+ {0xff, 0x00},
+ {0x0c, 0x00},
+ {0x62, 0x10},
+ {0x12, 0x00},
+ {0x17, 0x65},
+ {0x18, 0xa4},
+ {0x19, 0x0a},
+ {0x1a, 0xf6},
+ {0x3e, 0x30},
+ {0x64, 0x0a},
+ {0xff, 0x01},
+ {0xb4, 0xc0},
+ {0xff, 0x00},
+ {0x67, 0x20},
+ {0x81, 0x3f},
+ {0xcc, 0x02},
+ {0xcd, 0x80},
+ {0xce, 0x01},
+ {0xcf, 0xe0},
+ {0xc8, 0x02},
+ {0xc9, 0x80},
+ {0xca, 0x01},
+ {0xcb, 0xe0},
+ {0xd0, 0x48},
+ {0x82, 0x03},
+ {0x0e, 0x00},
+ {0x70, 0x00},
+ {0x71, 0x34},
+ {0x74, 0x28},
+ {0x75, 0x98},
+ {0x76, 0x00},
+ {0x77, 0x64},
+ {0x78, 0x01},
+ {0x79, 0xc2},
+ {0x7a, 0x4e},
+ {0x7b, 0x1f},
+ {0x7c, 0x00},
+ {0x11, 0x00},
+ {0x20, 0x00},
+ {0x21, 0x23},
+ {0x50, 0x9a},
+ {0x51, 0x80},
+ {0x4c, 0x7d},
+ {0x0e, 0x00},
+ {0x85, 0x10},
+ {0x86, 0x00},
+ {0x87, 0x00},
+ {0x88, 0x00},
+ {0x89, 0x2a},
+ {0x8a, 0x26},
+ {0x8b, 0x22},
+ {0xbb, 0x7a},
+ {0xbc, 0x69},
+ {0xbd, 0x11},
+ {0xbe, 0x13},
+ {0xbf, 0x81},
+ {0xc0, 0x96},
+ {0xc1, 0x1e},
+ {0xb7, 0x05},
+ {0xb8, 0x09},
+ {0xb9, 0x00},
+ {0xba, 0x18},
+ {0x5a, 0x1f},
+ {0x5b, 0x9f},
+ {0x5c, 0x6a},
+ {0x5d, 0x42},
+ {0x24, 0x78},
+ {0x25, 0x68},
+ {0x26, 0xb3},
+ {0xa3, 0x0b},
+ {0xa4, 0x15},
+ {0xa5, 0x2a},
+ {0xa6, 0x51},
+ {0xa7, 0x63},
+ {0xa8, 0x74},
+ {0xa9, 0x83},
+ {0xaa, 0x91},
+ {0xab, 0x9e},
+ {0xac, 0xaa},
+ {0xad, 0xbe},
+ {0xae, 0xce},
+ {0xaf, 0xe5},
+ {0xb0, 0xf3},
+ {0xb1, 0xfb},
+ {0xb2, 0x06},
+ {0x8c, 0x5c},
+ {0x8d, 0x11},
+ {0x8e, 0x12},
+ {0x8f, 0x19},
+ {0x90, 0x50},
+ {0x91, 0x20},
+ {0x92, 0x96},
+ {0x93, 0x80},
+ {0x94, 0x13},
+ {0x95, 0x1b},
+ {0x96, 0xff},
+ {0x97, 0x00},
+ {0x98, 0x3d},
+ {0x99, 0x36},
+ {0x9a, 0x51},
+ {0x9b, 0x43},
+ {0x9c, 0xf0},
+ {0x9d, 0xf0},
+ {0x9e, 0xf0},
+ {0x9f, 0xff},
+ {0xa0, 0x68},
+ {0xa1, 0x62},
+ {0xa2, 0x0e},
+};
+
+static bool OV7692_CSI_CONFIG;
+/* 816x612, 24MHz MCLK 96MHz PCLK */
+uint32_t OV7692_FULL_SIZE_WIDTH = 640;
+uint32_t OV7692_FULL_SIZE_HEIGHT = 480;
+
+uint32_t OV7692_QTR_SIZE_WIDTH = 640;
+uint32_t OV7692_QTR_SIZE_HEIGHT = 480;
+
+uint32_t OV7692_HRZ_FULL_BLK_PIXELS = 16;
+uint32_t OV7692_VER_FULL_BLK_LINES = 12;
+uint32_t OV7692_HRZ_QTR_BLK_PIXELS = 16;
+uint32_t OV7692_VER_QTR_BLK_LINES = 12;
+
+struct ov7692_work_t {
+ struct work_struct work;
+};
+static struct ov7692_work_t *ov7692_sensorw;
+static struct i2c_client *ov7692_client;
+struct ov7692_ctrl_t {
+ const struct msm_camera_sensor_info *sensordata;
+ uint32_t sensormode;
+ uint32_t fps_divider; /* init to 1 * 0x00000400 */
+ uint32_t pict_fps_divider; /* init to 1 * 0x00000400 */
+ uint32_t fps;
+ int32_t curr_lens_pos;
+ uint32_t curr_step_pos;
+ uint32_t my_reg_gain;
+ uint32_t my_reg_line_count;
+ uint32_t total_lines_per_frame;
+ enum ov7692_resolution_t prev_res;
+ enum ov7692_resolution_t pict_res;
+ enum ov7692_resolution_t curr_res;
+ enum ov7692_test_mode_t set_test;
+ unsigned short imgaddr;
+};
+static struct ov7692_ctrl_t *ov7692_ctrl;
+static DECLARE_WAIT_QUEUE_HEAD(ov7692_wait_queue);
+DEFINE_MUTEX(ov7692_mut);
+
+/*=============================================================*/
+
+static int ov7692_i2c_rxdata(unsigned short saddr,
+ unsigned char *rxdata, int length)
+{
+ struct i2c_msg msgs[] = {
+ {
+ .addr = saddr,
+ .flags = 0,
+ .len = 1,
+ .buf = rxdata,
+ },
+ {
+ .addr = saddr,
+ .flags = I2C_M_RD,
+ .len = 1,
+ .buf = rxdata,
+ },
+ };
+ if (i2c_transfer(ov7692_client->adapter, msgs, 2) < 0) {
+ CDBG("ov7692_i2c_rxdata failed!\n");
+ return -EIO;
+ }
+ return 0;
+}
+static int32_t ov7692_i2c_txdata(unsigned short saddr,
+ unsigned char *txdata, int length)
+{
+ struct i2c_msg msg[] = {
+ {
+ .addr = saddr,
+ .flags = 0,
+ .len = 2,
+ .buf = txdata,
+ },
+ };
+ if (i2c_transfer(ov7692_client->adapter, msg, 1) < 0) {
+ CDBG("ov7692_i2c_txdata faild 0x%x\n", ov7692_client->addr);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int32_t ov7692_i2c_read(uint8_t raddr,
+ uint8_t *rdata, int rlen)
+{
+ int32_t rc = 0;
+ unsigned char buf[1];
+ if (!rdata)
+ return -EIO;
+ memset(buf, 0, sizeof(buf));
+ buf[0] = raddr;
+ rc = ov7692_i2c_rxdata(ov7692_client->addr >> 1, buf, rlen);
+ if (rc < 0) {
+ CDBG("ov7692_i2c_read 0x%x failed!\n", raddr);
+ return rc;
+ }
+ *rdata = buf[0];
+ return rc;
+}
+static int32_t ov7692_i2c_write_b_sensor(uint8_t waddr, uint8_t bdata)
+{
+ int32_t rc = -EFAULT;
+ unsigned char buf[2];
+
+ memset(buf, 0, sizeof(buf));
+ buf[0] = waddr;
+ buf[1] = bdata;
+
+ rc = ov7692_i2c_txdata(ov7692_client->addr >> 1, buf, 2);
+ if (rc < 0)
+ CDBG("i2c_write_b failed, addr = 0x%x, val = 0x%x!\n",
+ waddr, bdata);
+ return rc;
+}
+
+static int32_t ov7692_sensor_setting(int update_type, int rt)
+{
+ int32_t i, array_length;
+ int32_t rc = 0;
+ struct msm_camera_csi_params ov7692_csi_params;
+
+ CDBG("%s: rt = %d\n", __func__, rt);
+
+ switch (update_type) {
+ case REG_INIT:
+ OV7692_CSI_CONFIG = 0;
+ ov7692_i2c_write_b_sensor(0x0e, 0x08);
+ return rc;
+ break;
+ case UPDATE_PERIODIC:
+ if (!OV7692_CSI_CONFIG) {
+ ov7692_csi_params.lane_cnt = 1;
+ ov7692_csi_params.data_format = CSI_8BIT;
+ ov7692_csi_params.lane_assign = 0xe4;
+ ov7692_csi_params.dpcm_scheme = 0;
+ ov7692_csi_params.settle_cnt = 0x14;
+
+ rc = msm_camio_csi_config(&ov7692_csi_params);
+ msleep(20);
+ array_length = sizeof(ov7692_init_settings_array) /
+ sizeof(ov7692_init_settings_array[0]);
+ for (i = 0; i < array_length; i++) {
+ rc = ov7692_i2c_write_b_sensor(
+ ov7692_init_settings_array[i].reg_addr,
+ ov7692_init_settings_array[i].reg_val);
+ if (rc < 0)
+ return rc;
+ }
+ OV7692_CSI_CONFIG = 1;
+ msleep(20);
+ return rc;
+ }
+ break;
+ default:
+ rc = -EINVAL;
+ break;
+ }
+ return rc;
+}
+
+static int32_t ov7692_video_config(int mode)
+{
+ int32_t rc = 0;
+ int rt;
+ /* change sensor resolution if needed */
+ rt = RES_PREVIEW;
+
+ CDBG("%s\n", __func__);
+
+ if (ov7692_sensor_setting(UPDATE_PERIODIC, rt) < 0)
+ return rc;
+ ov7692_ctrl->curr_res = ov7692_ctrl->prev_res;
+ ov7692_ctrl->sensormode = mode;
+ return rc;
+}
+
+static int32_t ov7692_set_sensor_mode(int mode,
+ int res)
+{
+ int32_t rc = 0;
+ switch (mode) {
+ case SENSOR_PREVIEW_MODE:
+ rc = ov7692_video_config(mode);
+ break;
+ case SENSOR_SNAPSHOT_MODE:
+ case SENSOR_RAW_SNAPSHOT_MODE:
+ break;
+ default:
+ rc = -EINVAL;
+ break;
+ }
+ return rc;
+}
+
+static void ov7692_power_on(void)
+{
+ CDBG("%s\n", __func__);
+ gpio_set_value(ov7692_pwdn_gpio, 0);
+}
+
+static void ov7692_power_down(void)
+{
+ CDBG("%s\n", __func__);
+ gpio_set_value(ov7692_pwdn_gpio, 1);
+}
+
+static void ov7692_sw_reset(void)
+{
+ CDBG("%s\n", __func__);
+ ov7692_i2c_write_b_sensor(0x12, 0x80);
+}
+
+static void ov7692_hw_reset(void)
+{
+ CDBG("--CAMERA-- %s ... (Start...)\n", __func__);
+ gpio_set_value(ov7692_reset_gpio, 1); /* reset camera reset pin */
+ msleep(20);
+ gpio_set_value(ov7692_reset_gpio, 0);
+ msleep(20);
+ gpio_set_value(ov7692_reset_gpio, 1);
+ msleep(20);
+
+ CDBG("--CAMERA-- %s ... (End...)\n", __func__);
+}
+
+
+
+static int ov7692_probe_init_sensor(const struct msm_camera_sensor_info *data)
+{
+ uint8_t model_id_msb, model_id_lsb = 0;
+ uint16_t model_id = 0;
+ int32_t rc = 0;
+ /*The reset pin is not physically connected to the sensor.
+ The standby pin will do the reset hence there is no need
+ to request the gpio reset*/
+
+ /* Read sensor Model ID: */
+ rc = ov7692_i2c_read(REG_OV7692_MODEL_ID_MSB, &model_id_msb, 1);
+ if (rc < 0)
+ goto init_probe_fail;
+ rc = ov7692_i2c_read(REG_OV7692_MODEL_ID_LSB, &model_id_lsb, 1);
+ if (rc < 0)
+ goto init_probe_fail;
+ model_id = (model_id_msb << 8) | ((model_id_lsb & 0x00FF)) ;
+ CDBG("ov7692 model_id = 0x%x, 0x%x, 0x%x\n",
+ model_id, model_id_msb, model_id_lsb);
+ /* 4. Compare sensor ID to OV7692 ID: */
+ if (model_id != OV7692_MODEL_ID) {
+ rc = -ENODEV;
+ goto init_probe_fail;
+ }
+ goto init_probe_done;
+init_probe_fail:
+ pr_warning(" ov7692_probe_init_sensor fails\n");
+init_probe_done:
+ CDBG(" ov7692_probe_init_sensor finishes\n");
+ return rc;
+}
+
+int ov7692_sensor_open_init(const struct msm_camera_sensor_info *data)
+{
+ int32_t rc = 0;
+
+ CDBG("%s: %d\n", __func__, __LINE__);
+ CDBG("Calling ov7692_sensor_open_init\n");
+ ov7692_ctrl = kzalloc(sizeof(struct ov7692_ctrl_t), GFP_KERNEL);
+ if (!ov7692_ctrl) {
+ CDBG("ov7692_init failed!\n");
+ rc = -ENOMEM;
+ goto init_done;
+ }
+ ov7692_ctrl->fps_divider = 1 * 0x00000400;
+ ov7692_ctrl->pict_fps_divider = 1 * 0x00000400;
+ ov7692_ctrl->fps = 30 * Q8;
+ ov7692_ctrl->set_test = TEST_OFF;
+ ov7692_ctrl->prev_res = QTR_SIZE;
+ ov7692_ctrl->pict_res = FULL_SIZE;
+ ov7692_ctrl->curr_res = INVALID_SIZE;
+
+ if (data)
+ ov7692_ctrl->sensordata = data;
+
+ /* enable mclk first */
+
+ msm_camio_clk_rate_set(24000000);
+ msleep(20);
+
+ ov7692_power_on();
+ msleep(20);
+
+ rc = ov7692_probe_init_sensor(data);
+ if (rc < 0) {
+ CDBG("Calling ov7692_sensor_open_init fail\n");
+ goto init_fail;
+ }
+
+ rc = ov7692_sensor_setting(REG_INIT, RES_PREVIEW);
+ if (rc < 0)
+ goto init_fail;
+ else
+ goto init_done;
+
+init_fail:
+ CDBG(" ov7692_sensor_open_init fail\n");
+ kfree(ov7692_ctrl);
+init_done:
+ CDBG("ov7692_sensor_open_init done\n");
+ return rc;
+}
+
+static int ov7692_init_client(struct i2c_client *client)
+{
+ /* Initialize the MSM_CAMI2C Chip */
+ init_waitqueue_head(&ov7692_wait_queue);
+ return 0;
+}
+
+static const struct i2c_device_id ov7692_i2c_id[] = {
+ {"ov7692", 0},
+ { }
+};
+
+static int ov7692_i2c_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ int rc = 0;
+ CDBG("ov7692_i2c_probe called!\n");
+
+ if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
+ CDBG("i2c_check_functionality failed\n");
+ goto probe_failure;
+ }
+
+ ov7692_sensorw = kzalloc(sizeof(struct ov7692_work_t), GFP_KERNEL);
+ if (!ov7692_sensorw) {
+ CDBG("kzalloc failed.\n");
+ rc = -ENOMEM;
+ goto probe_failure;
+ }
+
+ i2c_set_clientdata(client, ov7692_sensorw);
+ ov7692_init_client(client);
+ ov7692_client = client;
+
+ CDBG("ov7692_i2c_probe success! rc = %d\n", rc);
+ return 0;
+
+probe_failure:
+ CDBG("ov7692_i2c_probe failed! rc = %d\n", rc);
+ return rc;
+}
+
+static int __exit ov7692_remove(struct i2c_client *client)
+{
+ struct ov7692_work_t_t *sensorw = i2c_get_clientdata(client);
+ free_irq(client->irq, sensorw);
+ ov7692_client = NULL;
+ kfree(sensorw);
+ return 0;
+}
+
+static struct i2c_driver ov7692_i2c_driver = {
+ .id_table = ov7692_i2c_id,
+ .probe = ov7692_i2c_probe,
+ .remove = __exit_p(ov7692_i2c_remove),
+ .driver = {
+ .name = "ov7692",
+ },
+};
+
+int ov7692_sensor_config(void __user *argp)
+{
+ struct sensor_cfg_data cdata;
+ long rc = 0;
+ if (copy_from_user(&cdata,
+ (void *)argp,
+ sizeof(struct sensor_cfg_data)))
+ return -EFAULT;
+ mutex_lock(&ov7692_mut);
+ CDBG("ov7692_sensor_config: cfgtype = %d\n", cdata.cfgtype);
+ switch (cdata.cfgtype) {
+ case CFG_SET_MODE:
+ rc = ov7692_set_sensor_mode(cdata.mode,
+ cdata.rs);
+ break;
+ case CFG_PWR_DOWN:
+ ov7692_power_down();
+ break;
+ default:
+ rc = -EFAULT;
+ break;
+ }
+
+ mutex_unlock(&ov7692_mut);
+
+ return rc;
+}
+static int ov7692_sensor_release(void)
+{
+ int rc = -EBADF;
+ mutex_lock(&ov7692_mut);
+ ov7692_sw_reset();
+ ov7692_power_down();
+ kfree(ov7692_ctrl);
+ ov7692_ctrl = NULL;
+ CDBG("ov7692_release completed\n");
+ mutex_unlock(&ov7692_mut);
+
+ return rc;
+}
+
+static int ov7692_probe_init_gpio(const struct msm_camera_sensor_info *data)
+{
+ int rc = 0;
+
+ ov7692_pwdn_gpio = data->sensor_pwd;
+ ov7692_reset_gpio = data->sensor_reset ;
+
+ if (data->sensor_reset_enable)
+ gpio_direction_output(data->sensor_reset, 1);
+
+ gpio_direction_output(data->sensor_pwd, 1);
+
+ return rc;
+
+}
+
+
+static int ov7692_sensor_probe(const struct msm_camera_sensor_info *info,
+ struct msm_sensor_ctrl *s)
+{
+ int rc = 0;
+ rc = i2c_add_driver(&ov7692_i2c_driver);
+ if (rc < 0 || ov7692_client == NULL) {
+ rc = -ENOTSUPP;
+ goto probe_fail;
+ }
+
+ rc = ov7692_probe_init_gpio(info);
+ if (rc < 0) {
+ CDBG("%s: gpio init failed\n", __func__);
+ goto probe_fail;
+ }
+
+ ov7692_power_down();
+
+ msm_camio_clk_rate_set(24000000);
+ msleep(20);
+
+ ov7692_power_on();
+ msleep(20);
+
+ if (info->sensor_reset_enable)
+ ov7692_hw_reset();
+ else
+ ov7692_sw_reset();
+
+ rc = ov7692_probe_init_sensor(info);
+ if (rc < 0)
+ goto probe_fail;
+
+
+ s->s_init = ov7692_sensor_open_init;
+ s->s_release = ov7692_sensor_release;
+ s->s_config = ov7692_sensor_config;
+ s->s_camera_type = FRONT_CAMERA_2D;
+ s->s_mount_angle = info->sensor_platform_info->mount_angle;
+
+ ov7692_power_down();
+
+ return rc;
+
+probe_fail:
+ CDBG("ov7692_sensor_probe: SENSOR PROBE FAILS!\n");
+ i2c_del_driver(&ov7692_i2c_driver);
+ return rc;
+}
+
+static int __ov7692_probe(struct platform_device *pdev)
+{
+ return msm_camera_drv_start(pdev, ov7692_sensor_probe);
+}
+
+static struct platform_driver msm_camera_driver = {
+ .probe = __ov7692_probe,
+ .driver = {
+ .name = "msm_camera_ov7692",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init ov7692_init(void)
+{
+ return platform_driver_register(&msm_camera_driver);
+}
+
+module_init(ov7692_init);
+
+MODULE_DESCRIPTION("OMNI VGA YUV sensor driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/mfd/pm8921-core.c b/drivers/mfd/pm8921-core.c
index f05fb8e..742d8dd 100644
--- a/drivers/mfd/pm8921-core.c
+++ b/drivers/mfd/pm8921-core.c
@@ -270,6 +270,7 @@
SINGLE_IRQ_RESOURCE("PM8921_BMS_OCV_FOR_R", PM8921_BMS_OCV_FOR_R),
SINGLE_IRQ_RESOURCE("PM8921_BMS_GOOD_OCV", PM8921_BMS_GOOD_OCV),
SINGLE_IRQ_RESOURCE("PM8921_BMS_VSENSE_AVG", PM8921_BMS_VSENSE_AVG),
+ SINGLE_IRQ_RESOURCE("PM8921_BMS_CCADC_EOC", PM8921_BMS_CCADC_EOC),
};
static struct mfd_cell charger_cell __devinitdata = {
diff --git a/drivers/mfd/pm8xxx-batt-alarm.c b/drivers/mfd/pm8xxx-batt-alarm.c
index 92ade1c..1d30db9 100644
--- a/drivers/mfd/pm8xxx-batt-alarm.c
+++ b/drivers/mfd/pm8xxx-batt-alarm.c
@@ -502,15 +502,16 @@
= container_of(work, struct pm8xxx_batt_alarm_chip, irq_work);
int status;
- if (chip) {
- status = pm8xxx_batt_alarm_status_read();
+ if (!chip)
+ return;
- if (status < 0)
- pr_err("failed to read status, rc=%d\n", status);
- else
- srcu_notifier_call_chain(&chip->irq_notifier_list,
- status, NULL);
- }
+ status = pm8xxx_batt_alarm_status_read();
+
+ if (status < 0)
+ pr_err("failed to read status, rc=%d\n", status);
+ else
+ srcu_notifier_call_chain(&chip->irq_notifier_list,
+ status, NULL);
enable_irq(chip->irq);
}
diff --git a/drivers/mfd/pm8xxx-misc.c b/drivers/mfd/pm8xxx-misc.c
index 00ac2ab..7367e66 100644
--- a/drivers/mfd/pm8xxx-misc.c
+++ b/drivers/mfd/pm8xxx-misc.c
@@ -53,6 +53,12 @@
#define PM8901_REGULATOR_PMR_STATE_MASK 0x60
#define PM8901_REGULATOR_PMR_STATE_OFF 0x20
+/* GPIO UART MUX CTRL registers */
+#define REG_PM8XXX_GPIO_MUX_CTRL 0x1CC
+
+#define UART_PATH_SEL_MASK 0x60
+#define UART_PATH_SEL_SHIFT 0x5
+
struct pm8xxx_misc_chip {
struct list_head link;
struct pm8xxx_misc_platform_data pdata;
@@ -260,6 +266,47 @@
}
EXPORT_SYMBOL_GPL(pm8xxx_reset_pwr_off);
+/**
+ * pm8xxx_uart_gpio_mux_ctrl - Mux configuration to select the UART
+ *
+ * @uart_path_sel: Input argument to select either UART1/2/3
+ *
+ * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
+ */
+int pm8xxx_uart_gpio_mux_ctrl(enum pm8xxx_uart_path_sel uart_path_sel)
+{
+ struct pm8xxx_misc_chip *chip;
+ unsigned long flags;
+ int rc = 0;
+
+ spin_lock_irqsave(&pm8xxx_misc_chips_lock, flags);
+
+ /* Loop over all attached PMICs and call specific functions for them. */
+ list_for_each_entry(chip, &pm8xxx_misc_chips, link) {
+ switch (chip->version) {
+ case PM8XXX_VERSION_8018:
+ case PM8XXX_VERSION_8058:
+ case PM8XXX_VERSION_8921:
+ rc = pm8xxx_misc_masked_write(chip,
+ REG_PM8XXX_GPIO_MUX_CTRL, UART_PATH_SEL_MASK,
+ uart_path_sel << UART_PATH_SEL_SHIFT);
+ break;
+ default:
+ /* Functionality not supported */
+ break;
+ }
+ if (rc) {
+ pr_err("uart_gpio_mux_ctrl failed, rc=%d\n", rc);
+ break;
+ }
+ }
+
+ spin_unlock_irqrestore(&pm8xxx_misc_chips_lock, flags);
+
+ return rc;
+}
+EXPORT_SYMBOL(pm8xxx_uart_gpio_mux_ctrl);
+
static int __devinit pm8xxx_misc_probe(struct platform_device *pdev)
{
const struct pm8xxx_misc_platform_data *pdata = pdev->dev.platform_data;
diff --git a/drivers/mfd/pm8xxx-pwm.c b/drivers/mfd/pm8xxx-pwm.c
index ca9eebb..fa4b130 100644
--- a/drivers/mfd/pm8xxx-pwm.c
+++ b/drivers/mfd/pm8xxx-pwm.c
@@ -25,12 +25,33 @@
#include <linux/mfd/pm8xxx/core.h>
#include <linux/mfd/pm8xxx/pwm.h>
-#define PM8XXX_LPG_BANKS 8
-#define PM8XXX_PWM_CHANNELS PM8XXX_LPG_BANKS
+#define PM8XXX_PWM_CHANNELS 3
+#define PM8XXX_LPG_BANKS 8
+#define PM8XXX_LPG_PWM_CHANNELS PM8XXX_LPG_BANKS
#define PM8XXX_LPG_CTL_REGS 7
/* PM8XXX PWM */
+#define SSBI_REG_ADDR_PWM1_CTRL1 0x88
+#define SSBI_REG_ADDR_PWM1_CTRL2 0x89
+#define SSBI_REG_ADDR_PWM_CTL(id, base) (id == 0 ? base : (base + (id << 1)))
+#define SSBI_REG_ADDR_PWM_CTL1(id) SSBI_REG_ADDR_PWM_CTL(id, \
+ SSBI_REG_ADDR_PWM1_CTRL1)
+#define SSBI_REG_ADDR_PWM_CTL2(id) SSBI_REG_ADDR_PWM_CTL(id, \
+ SSBI_REG_ADDR_PWM1_CTRL2)
+
+#define PM8XXX_PWM_CLK_SEL_SHIFT 6
+#define PM8XXX_PWM_CLK_SEL_MASK 0xC0
+#define PM8XXX_PWM_PREDIVIDE_SHIFT 5
+#define PM8XXX_PWM_PREDIVIDE_MASK 0x20
+#define PM8XXX_PWM_M_SHIFT 2
+#define PM8XXX_PWM_M_MASK 0x1C
+#define PM8XXX_PWM_SIZE_SHIFT 1
+#define PM8XXX_PWM_SIZE_MASK 0x02
+#define PM8XXX_PWM_VALUE_BIT0 0x01
+#define PM8XXX_PWM_DISABLE 0x3F
+
+/* PM8XXX LPG PWM */
#define SSBI_REG_ADDR_LPG_CTL_BASE 0x13C
#define SSBI_REG_ADDR_LPG_CTL(n) (SSBI_REG_ADDR_LPG_CTL_BASE + (n))
#define SSBI_REG_ADDR_LPG_BANK_SEL 0x143
@@ -38,7 +59,7 @@
#define SSBI_REG_ADDR_LPG_LUT_CFG0 0x145
#define SSBI_REG_ADDR_LPG_LUT_CFG1 0x146
-/* Control 0 */
+/* LPG Control 0 */
#define PM8XXX_PWM_1KHZ_COUNT_MASK 0xF0
#define PM8XXX_PWM_1KHZ_COUNT_SHIFT 4
@@ -54,51 +75,51 @@
#define PM8XXX_PWM_RAMP_GEN_START (PM8XXX_PWM_RAMP_GEN_EN \
| PM8XXX_PWM_RAMP_START)
-/* Control 1 */
+/* LPG Control 1 */
#define PM8XXX_PWM_REVERSE_EN 0x80
#define PM8XXX_PWM_BYPASS_LUT 0x40
#define PM8XXX_PWM_HIGH_INDEX_MASK 0x3F
-/* Control 2 */
+/* LPG Control 2 */
#define PM8XXX_PWM_LOOP_EN 0x80
#define PM8XXX_PWM_RAMP_UP 0x40
#define PM8XXX_PWM_LOW_INDEX_MASK 0x3F
-/* Control 3 */
+/* LPG Control 3 */
#define PM8XXX_PWM_VALUE_BIT7_0 0xFF
#define PM8XXX_PWM_VALUE_BIT5_0 0x3F
-/* Control 4 */
+/* LPG Control 4 */
#define PM8XXX_PWM_VALUE_BIT8 0x80
-#define PM8XXX_PWM_CLK_SEL_MASK 0x60
-#define PM8XXX_PWM_CLK_SEL_SHIFT 5
+#define PM8XXX_LPG_PWM_CLK_SEL_MASK 0x60
+#define PM8XXX_LPG_PWM_CLK_SEL_SHIFT 5
#define PM8XXX_PWM_CLK_SEL_NO 0
#define PM8XXX_PWM_CLK_SEL_1KHZ 1
#define PM8XXX_PWM_CLK_SEL_32KHZ 2
#define PM8XXX_PWM_CLK_SEL_19P2MHZ 3
-#define PM8XXX_PWM_PREDIVIDE_MASK 0x18
-#define PM8XXX_PWM_PREDIVIDE_SHIFT 3
+#define PM8XXX_LPG_PWM_PREDIVIDE_MASK 0x18
+#define PM8XXX_LPG_PWM_PREDIVIDE_SHIFT 3
#define PM8XXX_PWM_PREDIVIDE_2 0
#define PM8XXX_PWM_PREDIVIDE_3 1
#define PM8XXX_PWM_PREDIVIDE_5 2
#define PM8XXX_PWM_PREDIVIDE_6 3
-#define PM8XXX_PWM_M_MASK 0x07
+#define PM8XXX_LPG_PWM_M_MASK 0x07
#define PM8XXX_PWM_M_MIN 0
#define PM8XXX_PWM_M_MAX 7
-/* Control 5 */
+/* LPG Control 5 */
#define PM8XXX_PWM_PAUSE_COUNT_HI_MASK 0xFC
#define PM8XXX_PWM_PAUSE_COUNT_HI_SHIFT 2
#define PM8XXX_PWM_PAUSE_ENABLE_HIGH 0x02
#define PM8XXX_PWM_SIZE_9_BIT 0x01
-/* Control 6 */
+/* LPG Control 6 */
#define PM8XXX_PWM_PAUSE_COUNT_LO_MASK 0xFC
#define PM8XXX_PWM_PAUSE_COUNT_LO_SHIFT 2
@@ -107,11 +128,10 @@
#define PM8XXX_PWM_PAUSE_COUNT_MAX 56 /* < 2^6 = 64 */
-/* LUT_CFG1 */
+/* LPG LUT_CFG1 */
#define PM8XXX_PWM_LUT_READ 0x40
-
/*
* PWM Frequency = Clock Frequency / (N * T)
* or
@@ -132,7 +152,8 @@
#define CLK_PERIOD_MIN NSEC_19P2MHZ
#define CLK_PERIOD_MAX NSEC_1000HZ
-#define NUM_PRE_DIVIDE 3 /* No default support for pre-divide = 6 */
+#define NUM_LPG_PRE_DIVIDE 3 /* No default support for pre-divide = 6 */
+#define NUM_PWM_PRE_DIVIDE 2
#define PRE_DIVIDE_0 2
#define PRE_DIVIDE_1 3
@@ -141,7 +162,7 @@
#define PRE_DIVIDE_MIN PRE_DIVIDE_0
#define PRE_DIVIDE_MAX PRE_DIVIDE_2
-static unsigned int pt_t[NUM_PRE_DIVIDE][NUM_CLOCKS] = {
+static unsigned int pt_t[NUM_LPG_PRE_DIVIDE][NUM_CLOCKS] = {
{ PRE_DIVIDE_0 * NSEC_1000HZ,
PRE_DIVIDE_0 * NSEC_32768HZ,
PRE_DIVIDE_0 * NSEC_19P2MHZ,
@@ -170,17 +191,22 @@
int pwm_value;
int pwm_period;
int pwm_duty;
- u8 pwm_ctl[PM8XXX_LPG_CTL_REGS];
+ u8 pwm_lpg_ctl[PM8XXX_LPG_CTL_REGS];
+ u8 pwm_ctl1;
+ u8 pwm_ctl2;
int irq;
struct pm8xxx_pwm_chip *chip;
int bypass_lut;
};
struct pm8xxx_pwm_chip {
- struct pwm_device pwm_dev[PM8XXX_PWM_CHANNELS];
+ struct pwm_device *pwm_dev;
+ u8 pwm_channels;
+ u8 pwm_total_pre_divs;
u8 bank_mask;
struct mutex pwm_mutex;
struct device *dev;
+ bool is_lpg_supported;
};
static struct pm8xxx_pwm_chip *pwm_chip;
@@ -255,13 +281,13 @@
u8 reg;
if (start) {
- reg = pwm->pwm_ctl[0] | PM8XXX_PWM_PWM_START;
+ reg = pwm->pwm_lpg_ctl[0] | PM8XXX_PWM_PWM_START;
if (ramp_start)
reg |= PM8XXX_PWM_RAMP_GEN_START;
else
reg &= ~PM8XXX_PWM_RAMP_GEN_START;
} else {
- reg = pwm->pwm_ctl[0] & ~PM8XXX_PWM_PWM_START;
+ reg = pwm->pwm_lpg_ctl[0] & ~PM8XXX_PWM_PWM_START;
reg &= ~PM8XXX_PWM_RAMP_GEN_START;
}
@@ -270,7 +296,40 @@
if (rc)
pr_err("pm8xxx_writeb(): rc=%d (Enable PWM Ctl 0)\n", rc);
else
- pwm->pwm_ctl[0] = reg;
+ pwm->pwm_lpg_ctl[0] = reg;
+ return rc;
+}
+
+static int pm8xxx_pwm_disable(struct pwm_device *pwm)
+{
+ int rc;
+ u8 reg;
+
+ reg = pwm->pwm_ctl1 & PM8XXX_PWM_DISABLE;
+
+ rc = pm8xxx_writeb(pwm->chip->dev->parent,
+ SSBI_REG_ADDR_PWM_CTL1(pwm->pwm_id), reg);
+
+ if (rc)
+ pr_err("pm8xxx_writeb(): rc=%d (Disable PWM Ctl %d)\n", rc,
+ pwm->pwm_id);
+ return rc;
+}
+
+static int pm8xxx_pwm_enable(struct pwm_device *pwm)
+{
+ /**
+ * A kind of best Effort: Just write the clock information that
+ * we have in the register.
+ */
+ int rc;
+
+ rc = pm8xxx_writeb(pwm->chip->dev->parent,
+ SSBI_REG_ADDR_PWM_CTL1(pwm->pwm_id), pwm->pwm_ctl1);
+
+ if (rc)
+ pr_err("pm8xxx_writeb(): rc=%d (Enable PWM Ctl %d)\n", rc,
+ pwm->pwm_id);
return rc;
}
@@ -304,7 +363,7 @@
best_clk = 0;
best_div = 0;
for (clk = 0; clk < NUM_CLOCKS; clk++) {
- for (div = 0; div < NUM_PRE_DIVIDE; div++) {
+ for (div = 0; div < pwm_chip->pwm_total_pre_divs; div++) {
tmp_p = period_n;
last_p = tmp_p;
for (m = 0; m <= PM8XXX_PWM_M_MAX; m++) {
@@ -384,7 +443,7 @@
int i, pwm_size;
int rc = 0;
- pwm_size = (pwm->pwm_ctl[5] & PM8XXX_PWM_SIZE_9_BIT) ? 9 : 6;
+ pwm_size = (pwm->pwm_lpg_ctl[5] & PM8XXX_PWM_SIZE_9_BIT) ? 9 : 6;
max_pwm_value = (1 << pwm_size) - 1;
for (i = 0; i < len; i++) {
if (raw_value)
@@ -414,44 +473,65 @@
static void pm8xxx_pwm_save_index(struct pwm_device *pwm,
int low_idx, int high_idx, int flags)
{
- pwm->pwm_ctl[1] = high_idx & PM8XXX_PWM_HIGH_INDEX_MASK;
- pwm->pwm_ctl[2] = low_idx & PM8XXX_PWM_LOW_INDEX_MASK;
+ pwm->pwm_lpg_ctl[1] = high_idx & PM8XXX_PWM_HIGH_INDEX_MASK;
+ pwm->pwm_lpg_ctl[2] = low_idx & PM8XXX_PWM_LOW_INDEX_MASK;
if (flags & PM_PWM_LUT_REVERSE)
- pwm->pwm_ctl[1] |= PM8XXX_PWM_REVERSE_EN;
+ pwm->pwm_lpg_ctl[1] |= PM8XXX_PWM_REVERSE_EN;
if (flags & PM_PWM_LUT_RAMP_UP)
- pwm->pwm_ctl[2] |= PM8XXX_PWM_RAMP_UP;
+ pwm->pwm_lpg_ctl[2] |= PM8XXX_PWM_RAMP_UP;
if (flags & PM_PWM_LUT_LOOP)
- pwm->pwm_ctl[2] |= PM8XXX_PWM_LOOP_EN;
+ pwm->pwm_lpg_ctl[2] |= PM8XXX_PWM_LOOP_EN;
}
static void pm8xxx_pwm_save_period(struct pwm_device *pwm)
{
u8 mask, val;
- val = ((pwm->period.clk + 1) << PM8XXX_PWM_CLK_SEL_SHIFT)
- & PM8XXX_PWM_CLK_SEL_MASK;
- val |= (pwm->period.pre_div << PM8XXX_PWM_PREDIVIDE_SHIFT)
- & PM8XXX_PWM_PREDIVIDE_MASK;
- val |= pwm->period.pre_div_exp & PM8XXX_PWM_M_MASK;
- mask = PM8XXX_PWM_CLK_SEL_MASK | PM8XXX_PWM_PREDIVIDE_MASK |
- PM8XXX_PWM_M_MASK;
- pm8xxx_pwm_save(&pwm->pwm_ctl[4], mask, val);
+ if (pwm_chip->is_lpg_supported) {
+ val = ((pwm->period.clk + 1) << PM8XXX_LPG_PWM_CLK_SEL_SHIFT)
+ & PM8XXX_LPG_PWM_CLK_SEL_MASK;
+ val |= (pwm->period.pre_div << PM8XXX_LPG_PWM_PREDIVIDE_SHIFT)
+ & PM8XXX_LPG_PWM_PREDIVIDE_MASK;
+ val |= pwm->period.pre_div_exp & PM8XXX_LPG_PWM_M_MASK;
+ mask = PM8XXX_LPG_PWM_CLK_SEL_MASK |
+ PM8XXX_LPG_PWM_PREDIVIDE_MASK | PM8XXX_LPG_PWM_M_MASK;
+ pm8xxx_pwm_save(&pwm->pwm_lpg_ctl[4], mask, val);
- val = (pwm->period.pwm_size > 6) ? PM8XXX_PWM_SIZE_9_BIT : 0;
- mask = PM8XXX_PWM_SIZE_9_BIT;
- pm8xxx_pwm_save(&pwm->pwm_ctl[5], mask, val);
+ val = (pwm->period.pwm_size > 6) ? PM8XXX_PWM_SIZE_9_BIT : 0;
+ mask = PM8XXX_PWM_SIZE_9_BIT;
+ pm8xxx_pwm_save(&pwm->pwm_lpg_ctl[5], mask, val);
+ } else {
+ val = ((pwm->period.clk + 1) << PM8XXX_PWM_CLK_SEL_SHIFT)
+ & PM8XXX_PWM_CLK_SEL_MASK;
+ val |= (pwm->period.pre_div << PM8XXX_PWM_PREDIVIDE_SHIFT)
+ & PM8XXX_PWM_PREDIVIDE_MASK;
+ val |= (pwm->period.pre_div_exp << PM8XXX_PWM_M_SHIFT)
+ & PM8XXX_PWM_M_MASK;
+ val |= (((pwm->period.pwm_size > 6) ? PM8XXX_PWM_SIZE_9_BIT : 0)
+ << PM8XXX_PWM_SIZE_SHIFT) & PM8XXX_PWM_SIZE_MASK;
+
+ mask = PM8XXX_PWM_CLK_SEL_MASK | PM8XXX_PWM_PREDIVIDE_MASK |
+ PM8XXX_PWM_M_MASK | PM8XXX_PWM_SIZE_MASK;
+ pm8xxx_pwm_save(&pwm->pwm_ctl1, mask, val);
+ }
}
static void pm8xxx_pwm_save_pwm_value(struct pwm_device *pwm)
{
u8 mask, val;
- pwm->pwm_ctl[3] = pwm->pwm_value;
-
- val = (pwm->period.pwm_size > 6) ? (pwm->pwm_value >> 1) : 0;
- mask = PM8XXX_PWM_VALUE_BIT8;
- pm8xxx_pwm_save(&pwm->pwm_ctl[4], mask, val);
+ if (pwm_chip->is_lpg_supported) {
+ val = (pwm->period.pwm_size > 6) ? (pwm->pwm_value >> 1) : 0;
+ pwm->pwm_lpg_ctl[3] = pwm->pwm_value;
+ mask = PM8XXX_PWM_VALUE_BIT8;
+ pm8xxx_pwm_save(&pwm->pwm_lpg_ctl[4], mask, val);
+ } else {
+ val = (pwm->period.pwm_size > 6) ? (pwm->pwm_value >> 8) : 0;
+ pwm->pwm_ctl2 = pwm->pwm_value;
+ mask = PM8XXX_PWM_VALUE_BIT0;
+ pm8xxx_pwm_save(&pwm->pwm_ctl1, mask, val);
+ }
}
static void pm8xxx_pwm_save_duty_time(struct pwm_device *pwm,
@@ -468,7 +548,7 @@
val = i << PM8XXX_PWM_1KHZ_COUNT_SHIFT;
mask = PM8XXX_PWM_1KHZ_COUNT_MASK;
- pm8xxx_pwm_save(&pwm->pwm_ctl[0], mask, val);
+ pm8xxx_pwm_save(&pwm->pwm_lpg_ctl[0], mask, val);
}
static void pm8xxx_pwm_save_pause(struct pwm_device *pwm,
@@ -477,7 +557,7 @@
int i, pause_cnt, time_cnt;
u8 mask, val;
- time_cnt = (pwm->pwm_ctl[0] & PM8XXX_PWM_1KHZ_COUNT_MASK)
+ time_cnt = (pwm->pwm_lpg_ctl[0] & PM8XXX_PWM_1KHZ_COUNT_MASK)
>> PM8XXX_PWM_1KHZ_COUNT_SHIFT;
if (lut->flags & PM_PWM_LUT_PAUSE_HI_EN) {
pause_cnt = (lut->lut_pause_hi + duty_msec[time_cnt] / 2)
@@ -495,7 +575,7 @@
}
mask = PM8XXX_PWM_PAUSE_COUNT_HI_MASK | PM8XXX_PWM_PAUSE_ENABLE_HIGH;
- pm8xxx_pwm_save(&pwm->pwm_ctl[5], mask, val);
+ pm8xxx_pwm_save(&pwm->pwm_lpg_ctl[5], mask, val);
if (lut->flags & PM_PWM_LUT_PAUSE_LO_EN) {
/* Linear search for pause time */
@@ -513,10 +593,35 @@
}
mask = PM8XXX_PWM_PAUSE_COUNT_LO_MASK | PM8XXX_PWM_PAUSE_ENABLE_LOW;
- pm8xxx_pwm_save(&pwm->pwm_ctl[6], mask, val);
+ pm8xxx_pwm_save(&pwm->pwm_lpg_ctl[6], mask, val);
}
-static int pm8xxx_pwm_write(struct pwm_device *pwm, int start, int end)
+static int pm8xxx_pwm_write(struct pwm_device *pwm)
+{
+ int rc = 0;
+
+ rc = pm8xxx_writeb(pwm->chip->dev->parent,
+ SSBI_REG_ADDR_PWM_CTL1(pwm->pwm_id),
+ pwm->pwm_ctl1);
+ if (rc) {
+ pr_err("pm8xxx_writeb() failed: rc=%d (PWM Ctl1[%d])\n",
+ rc, pwm->pwm_id);
+ return rc;
+ }
+
+ rc = pm8xxx_writeb(pwm->chip->dev->parent,
+ SSBI_REG_ADDR_PWM_CTL2(pwm->pwm_id),
+ pwm->pwm_ctl2);
+ if (rc) {
+ pr_err("pm8xxx_writeb() failed: rc=%d (PWM Ctl2[%d])\n",
+ rc, pwm->pwm_id);
+ return rc;
+ }
+
+ return rc;
+}
+
+static int pm8xxx_lpg_pwm_write(struct pwm_device *pwm, int start, int end)
{
int i, rc;
@@ -524,7 +629,7 @@
for (i = end - 1; i >= start; i--) {
rc = pm8xxx_writeb(pwm->chip->dev->parent,
SSBI_REG_ADDR_LPG_CTL(i),
- pwm->pwm_ctl[i]);
+ pwm->pwm_lpg_ctl[i]);
if (rc) {
pr_err("pm8xxx_writeb(): rc=%d (PWM Ctl[%d])\n", rc, i);
return rc;
@@ -543,10 +648,10 @@
lut->lut_hi_index, lut->flags);
pm8xxx_pwm_save_duty_time(pwm, lut);
pm8xxx_pwm_save_pause(pwm, lut);
- pm8xxx_pwm_save(&pwm->pwm_ctl[1], PM8XXX_PWM_BYPASS_LUT, 0);
+ pm8xxx_pwm_save(&pwm->pwm_lpg_ctl[1], PM8XXX_PWM_BYPASS_LUT, 0);
pm8xxx_pwm_bank_sel(pwm);
- rc = pm8xxx_pwm_write(pwm, 0, 7);
+ rc = pm8xxx_lpg_pwm_write(pwm, 0, 7);
return rc;
}
@@ -561,16 +666,17 @@
{
struct pwm_device *pwm;
- if (pwm_id > PM8XXX_PWM_CHANNELS || pwm_id < 0) {
- pr_err("Invalid pwm_id: %d with %s\n",
- pwm_id, label ? label : ".");
- return ERR_PTR(-EINVAL);
- }
if (pwm_chip == NULL) {
pr_err("No pwm_chip\n");
return ERR_PTR(-ENODEV);
}
+ if (pwm_id >= pwm_chip->pwm_channels || pwm_id < 0) {
+ pr_err("Invalid pwm_id: %d with %s\n",
+ pwm_id, label ? label : ".");
+ return ERR_PTR(-EINVAL);
+ }
+
mutex_lock(&pwm_chip->pwm_mutex);
pwm = &pwm_chip->pwm_dev[pwm_id];
if (!pwm->in_use) {
@@ -598,13 +704,17 @@
mutex_lock(&pwm->chip->pwm_mutex);
if (pwm->in_use) {
- pm8xxx_pwm_bank_sel(pwm);
- pm8xxx_pwm_start(pwm, 0, 0);
-
+ if (pwm_chip->is_lpg_supported) {
+ pm8xxx_pwm_bank_sel(pwm);
+ pm8xxx_pwm_start(pwm, 0, 0);
+ } else {
+ pm8xxx_pwm_disable(pwm);
+ }
pwm->in_use = 0;
pwm->label = NULL;
}
- pm8xxx_pwm_bank_enable(pwm, 0);
+ if (pwm_chip->is_lpg_supported)
+ pm8xxx_pwm_bank_enable(pwm, 0);
mutex_unlock(&pwm->chip->pwm_mutex);
}
EXPORT_SYMBOL_GPL(pwm_free);
@@ -618,7 +728,7 @@
int pwm_config(struct pwm_device *pwm, int duty_us, int period_us)
{
struct pm8xxx_pwm_period *period;
- int rc;
+ int rc = 0;
if (pwm == NULL || IS_ERR(pwm) ||
duty_us > period_us ||
@@ -649,11 +759,16 @@
pm8xxx_pwm_calc_pwm_value(pwm, period_us, duty_us);
pm8xxx_pwm_save_pwm_value(pwm);
- pm8xxx_pwm_save(&pwm->pwm_ctl[1],
- PM8XXX_PWM_BYPASS_LUT, PM8XXX_PWM_BYPASS_LUT);
- pm8xxx_pwm_bank_sel(pwm);
- rc = pm8xxx_pwm_write(pwm, 1, 6);
+ if (pwm_chip->is_lpg_supported) {
+ pm8xxx_pwm_save(&pwm->pwm_lpg_ctl[1],
+ PM8XXX_PWM_BYPASS_LUT, PM8XXX_PWM_BYPASS_LUT);
+
+ pm8xxx_pwm_bank_sel(pwm);
+ rc = pm8xxx_lpg_pwm_write(pwm, 1, 6);
+ } else {
+ rc = pm8xxx_pwm_write(pwm);
+ }
pr_debug("duty/period=%u/%u usec: pwm_value=%d (of %d)\n",
(unsigned)duty_us, (unsigned)period_us,
@@ -671,7 +786,7 @@
*/
int pwm_enable(struct pwm_device *pwm)
{
- int rc;
+ int rc = 0;
if (pwm == NULL || IS_ERR(pwm)) {
pr_err("Invalid pwm handle\n");
@@ -687,10 +802,13 @@
pr_err("pwm_id: %d: stale handle?\n", pwm->pwm_id);
rc = -EINVAL;
} else {
- rc = pm8xxx_pwm_bank_enable(pwm, 1);
-
- pm8xxx_pwm_bank_sel(pwm);
- pm8xxx_pwm_start(pwm, 1, 0);
+ if (pwm_chip->is_lpg_supported) {
+ rc = pm8xxx_pwm_bank_enable(pwm, 1);
+ pm8xxx_pwm_bank_sel(pwm);
+ pm8xxx_pwm_start(pwm, 1, 0);
+ } else {
+ pm8xxx_pwm_enable(pwm);
+ }
}
mutex_unlock(&pwm->chip->pwm_mutex);
return rc;
@@ -710,10 +828,13 @@
mutex_lock(&pwm->chip->pwm_mutex);
if (pwm->in_use) {
- pm8xxx_pwm_bank_sel(pwm);
- pm8xxx_pwm_start(pwm, 0, 0);
-
- pm8xxx_pwm_bank_enable(pwm, 0);
+ if (pwm_chip->is_lpg_supported) {
+ pm8xxx_pwm_bank_sel(pwm);
+ pm8xxx_pwm_start(pwm, 0, 0);
+ pm8xxx_pwm_bank_enable(pwm, 0);
+ } else {
+ pm8xxx_pwm_disable(pwm);
+ }
}
mutex_unlock(&pwm->chip->pwm_mutex);
}
@@ -748,8 +869,14 @@
pwm->period.pre_div_exp = period->pre_div_exp;
pm8xxx_pwm_save_period(pwm);
- pm8xxx_pwm_bank_sel(pwm);
- rc = pm8xxx_pwm_write(pwm, 4, 6);
+
+ if (pwm_chip->is_lpg_supported) {
+ pm8xxx_pwm_bank_sel(pwm);
+ rc = pm8xxx_lpg_pwm_write(pwm, 4, 6);
+ } else {
+ rc = pm8xxx_pwm_write(pwm);
+ }
+
out_unlock:
mutex_unlock(&pwm->chip->pwm_mutex);
@@ -784,11 +911,15 @@
pwm->pwm_value = pwm_value;
pm8xxx_pwm_save_pwm_value(pwm);
- pm8xxx_pwm_save(&pwm->pwm_ctl[1],
- PM8XXX_PWM_BYPASS_LUT, PM8XXX_PWM_BYPASS_LUT);
- pm8xxx_pwm_bank_sel(pwm);
- rc = pm8xxx_pwm_write(pwm, 1, 6);
+ if (pwm_chip->is_lpg_supported) {
+ pm8xxx_pwm_save(&pwm->pwm_lpg_ctl[1],
+ PM8XXX_PWM_BYPASS_LUT, PM8XXX_PWM_BYPASS_LUT);
+ pm8xxx_pwm_bank_sel(pwm);
+ rc = pm8xxx_lpg_pwm_write(pwm, 1, 6);
+ } else {
+ rc = pm8xxx_pwm_write(pwm);
+ }
if (rc)
pr_err("[%d]: pm8xxx_pwm_write: rc=%d\n", pwm->pwm_id, rc);
@@ -832,6 +963,12 @@
pr_err("No pwm_chip\n");
return -ENODEV;
}
+
+ if (pwm->chip->is_lpg_supported == 0) {
+ pr_err("LPG module isn't supported\n");
+ return -EINVAL;
+ }
+
if (idx_len >= PM_PWM_LUT_SIZE && start_idx) {
pr_err("Wrong LUT size or index\n");
return -EINVAL;
@@ -904,6 +1041,10 @@
pr_err("No pwm_chip\n");
return -ENODEV;
}
+ if (pwm->chip->is_lpg_supported == 0) {
+ pr_err("LPG module isn't supported\n");
+ return -EINVAL;
+ }
mutex_lock(&pwm->chip->pwm_mutex);
if (start) {
@@ -940,7 +1081,7 @@
struct device *dev;
struct dentry *dent;
- struct pm8xxx_pwm_user user[PM8XXX_PWM_CHANNELS];
+ struct pm8xxx_pwm_user *user;
};
static struct pm8xxx_pwm_dbg_device *pmic_dbg_device;
@@ -1101,6 +1242,14 @@
return -ENOMEM;
}
+ dbgdev->user = kcalloc(pwm_chip->pwm_channels,
+ sizeof(struct pm8xxx_pwm_user), GFP_KERNEL);
+ if (dbgdev->user == NULL) {
+ pr_err("kcalloc() failed.\n");
+ kfree(dbgdev);
+ return -ENOMEM;
+ }
+
mutex_init(&dbgdev->dbg_mutex);
dbgdev->dev = dev;
@@ -1113,7 +1262,7 @@
dbgdev->dent = dent;
- for (i = 0; i < PM8XXX_PWM_CHANNELS; i++) {
+ for (i = 0; i < pwm_chip->pwm_channels; i++) {
char pwm_ch[] = "0";
pwm_ch[0] = '0' + i;
@@ -1160,6 +1309,7 @@
static int __devexit pm8xxx_pwm_dbg_remove(void)
{
if (pmic_dbg_device) {
+ kfree(pmic_dbg_device->user);
debugfs_remove_recursive(pmic_dbg_device->dent);
kfree(pmic_dbg_device);
}
@@ -1184,6 +1334,7 @@
{
struct pm8xxx_pwm_chip *chip;
int i;
+ enum pm8xxx_version version;
chip = kzalloc(sizeof *chip, GFP_KERNEL);
if (chip == NULL) {
@@ -1191,15 +1342,39 @@
return -ENOMEM;
}
- for (i = 0; i < PM8XXX_PWM_CHANNELS; i++) {
- chip->pwm_dev[i].pwm_id = i;
- chip->pwm_dev[i].chip = chip;
- }
-
mutex_init(&chip->pwm_mutex);
chip->dev = &pdev->dev;
pwm_chip = chip;
+
+ version = pm8xxx_get_version(chip->dev->parent);
+
+ if (version == PM8XXX_VERSION_8921 ||
+ version == PM8XXX_VERSION_8058) {
+ chip->is_lpg_supported = 1;
+ }
+ if (chip->is_lpg_supported) {
+ chip->pwm_channels = PM8XXX_LPG_PWM_CHANNELS;
+ chip->pwm_total_pre_divs = NUM_LPG_PRE_DIVIDE;
+ } else {
+ chip->pwm_channels = PM8XXX_PWM_CHANNELS;
+ chip->pwm_total_pre_divs = NUM_PWM_PRE_DIVIDE;
+ }
+
+ chip->pwm_dev = kcalloc(chip->pwm_channels, sizeof(struct pwm_device),
+ GFP_KERNEL);
+ if (chip->pwm_dev == NULL) {
+ pr_err("kcalloc() failed.\n");
+ mutex_destroy(&chip->pwm_mutex);
+ kfree(chip);
+ return -ENOMEM;
+ }
+
+ for (i = 0; i < chip->pwm_channels; i++) {
+ chip->pwm_dev[i].pwm_id = i;
+ chip->pwm_dev[i].chip = chip;
+ }
+
platform_set_drvdata(pdev, chip);
if (pm8xxx_pwm_dbg_probe(&pdev->dev) < 0)
@@ -1214,6 +1389,7 @@
struct pm8xxx_pwm_chip *chip = dev_get_drvdata(pdev->dev.parent);
pm8xxx_pwm_dbg_remove();
+ kfree(chip->pwm_dev);
mutex_destroy(&chip->pwm_mutex);
platform_set_drvdata(pdev, NULL);
kfree(chip);
diff --git a/drivers/mfd/timpani-codec.c b/drivers/mfd/timpani-codec.c
index 364670e..b9ae84e 100644
--- a/drivers/mfd/timpani-codec.c
+++ b/drivers/mfd/timpani-codec.c
@@ -48,6 +48,7 @@
IGNORE = 2,
};
#define TIMPANI_ARRAY_SIZE (TIMPANI_A_CDC_COMP_HALT + 1)
+#define MAX_SHADOW_RIGISTERS TIMPANI_A_CDC_COMP_HALT
static u8 timpani_shadow[TIMPANI_ARRAY_SIZE];
@@ -2765,6 +2766,19 @@
int rc = 0;
u8 new_val;
+ if (reg > MAX_SHADOW_RIGISTERS) {
+ pr_debug("register number is out of bound for shadow"
+ " registers reg = %d\n", reg);
+ new_val = (val & mask);
+ rc = marimba_write_bit_mask(adie_codec.pdrv_ptr, reg, &new_val,
+ 1, 0xFF);
+ if (IS_ERR_VALUE(rc)) {
+ pr_err("%s: fail to write reg %x\n", __func__, reg);
+ rc = -EIO;
+ goto error;
+ }
+ return rc;
+ }
new_val = (val & mask) | (timpani_shadow[reg] & ~mask);
if (!(timpani_register_is_cacheable(reg) &&
(new_val == timpani_shadow[reg]))) {
diff --git a/drivers/mfd/wcd9310-core.c b/drivers/mfd/wcd9310-core.c
index aef0754..8eca7aa 100644
--- a/drivers/mfd/wcd9310-core.c
+++ b/drivers/mfd/wcd9310-core.c
@@ -573,6 +573,7 @@
int ret = 0;
int sgla_retry_cnt;
+ dev_info(&slim->dev, "Initialized slim device %s\n", slim->name);
pdata = slim->dev.platform_data;
if (!pdata) {
@@ -727,17 +728,35 @@
.remove = tabla_slim_remove,
.id_table = slimtest_id,
};
+
+static const struct slim_device_id slimtest2x_id[] = {
+ {"tabla2x-slim", 0},
+ {}
+};
+
+static struct slim_driver tabla2x_slim_driver = {
+ .driver = {
+ .name = "tabla2x-slim",
+ .owner = THIS_MODULE,
+ },
+ .probe = tabla_slim_probe,
+ .remove = tabla_slim_remove,
+ .id_table = slimtest2x_id,
+};
+
static int __init tabla_init(void)
{
- int ret;
+ int ret1, ret2;
- ret = slim_driver_register(&tabla_slim_driver);
- if (ret != 0) {
- pr_err("Failed to register tabla SB driver: %d\n", ret);
- goto err;
- }
-err:
- return ret;
+ ret1 = slim_driver_register(&tabla_slim_driver);
+ if (ret1 != 0)
+ pr_err("Failed to register tabla SB driver: %d\n", ret1);
+
+ ret2 = slim_driver_register(&tabla2x_slim_driver);
+ if (ret2 != 0)
+ pr_err("Failed to register tabla2x SB driver: %d\n", ret2);
+
+ return (ret1 && ret2) ? -1 : 0;
}
module_init(tabla_init);
diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
index 008f881..93e1ec6 100644
--- a/drivers/mmc/core/core.c
+++ b/drivers/mmc/core/core.c
@@ -153,7 +153,7 @@
if (mrq->done)
mrq->done(mrq);
- mmc_host_clk_gate(host);
+ mmc_host_clk_release(host);
}
}
@@ -215,7 +215,7 @@
host->perf.start = ktime_get();
#endif
}
- mmc_host_clk_ungate(host);
+ mmc_host_clk_hold(host);
led_trigger_event(host->led, LED_FULL);
host->ops->request(host, mrq);
}
@@ -669,15 +669,17 @@
*/
void mmc_set_chip_select(struct mmc_host *host, int mode)
{
+ mmc_host_clk_hold(host);
host->ios.chip_select = mode;
mmc_set_ios(host);
+ mmc_host_clk_release(host);
}
/*
* Sets the host clock to the highest possible frequency that
* is below "hz".
*/
-void mmc_set_clock(struct mmc_host *host, unsigned int hz)
+static void __mmc_set_clock(struct mmc_host *host, unsigned int hz)
{
WARN_ON(hz < host->f_min);
@@ -688,6 +690,13 @@
mmc_set_ios(host);
}
+void mmc_set_clock(struct mmc_host *host, unsigned int hz)
+{
+ mmc_host_clk_hold(host);
+ __mmc_set_clock(host, hz);
+ mmc_host_clk_release(host);
+}
+
#ifdef CONFIG_MMC_CLKGATE
/*
* This gates the clock by setting it to 0 Hz.
@@ -720,7 +729,7 @@
if (host->clk_old) {
BUG_ON(host->ios.clock);
/* This call will also set host->clk_gated to false */
- mmc_set_clock(host, host->clk_old);
+ __mmc_set_clock(host, host->clk_old);
}
}
@@ -748,8 +757,10 @@
*/
void mmc_set_bus_mode(struct mmc_host *host, unsigned int mode)
{
+ mmc_host_clk_hold(host);
host->ios.bus_mode = mode;
mmc_set_ios(host);
+ mmc_host_clk_release(host);
}
/*
@@ -757,8 +768,10 @@
*/
void mmc_set_bus_width(struct mmc_host *host, unsigned int width)
{
+ mmc_host_clk_hold(host);
host->ios.bus_width = width;
mmc_set_ios(host);
+ mmc_host_clk_release(host);
}
/**
@@ -956,8 +969,10 @@
ocr &= 3 << bit;
+ mmc_host_clk_hold(host);
host->ios.vdd = bit;
mmc_set_ios(host);
+ mmc_host_clk_release(host);
} else {
pr_warning("%s: host doesn't support card's voltages\n",
mmc_hostname(host));
@@ -1004,8 +1019,10 @@
*/
void mmc_set_timing(struct mmc_host *host, unsigned int timing)
{
+ mmc_host_clk_hold(host);
host->ios.timing = timing;
mmc_set_ios(host);
+ mmc_host_clk_release(host);
}
/*
@@ -1013,8 +1030,10 @@
*/
void mmc_set_driver_type(struct mmc_host *host, unsigned int drv_type)
{
+ mmc_host_clk_hold(host);
host->ios.drv_type = drv_type;
mmc_set_ios(host);
+ mmc_host_clk_release(host);
}
/*
@@ -1032,6 +1051,8 @@
{
int bit;
+ mmc_host_clk_hold(host);
+
/* If ocr is set, we use it */
if (host->ocr)
bit = ffs(host->ocr) - 1;
@@ -1067,10 +1088,14 @@
* time required to reach a stable voltage.
*/
mmc_delay(10);
+
+ mmc_host_clk_release(host);
}
static void mmc_power_off(struct mmc_host *host)
{
+ mmc_host_clk_hold(host);
+
host->ios.clock = 0;
host->ios.vdd = 0;
@@ -1088,6 +1113,8 @@
host->ios.bus_width = MMC_BUS_WIDTH_1;
host->ios.timing = MMC_TIMING_LEGACY;
mmc_set_ios(host);
+
+ mmc_host_clk_release(host);
}
/*
diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c
index 3dead90..5441006 100644
--- a/drivers/mmc/core/host.c
+++ b/drivers/mmc/core/host.c
@@ -53,6 +53,31 @@
static DEFINE_SPINLOCK(mmc_host_lock);
#ifdef CONFIG_MMC_CLKGATE
+static ssize_t clkgate_delay_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mmc_host *host = cls_dev_to_mmc_host(dev);
+ return snprintf(buf, PAGE_SIZE, "%lu millisecs\n",
+ host->clkgate_delay);
+}
+
+static ssize_t clkgate_delay_store(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ struct mmc_host *host = cls_dev_to_mmc_host(dev);
+ unsigned long flags, value;
+
+ if (kstrtoul(buf, 0, &value))
+ return -EINVAL;
+
+ spin_lock_irqsave(&host->clk_lock, flags);
+ host->clkgate_delay = value;
+ spin_unlock_irqrestore(&host->clk_lock, flags);
+
+ pr_info("%s: clock gate delay set to %lu ms\n",
+ mmc_hostname(host), value);
+ return count;
+}
/*
* Enabling clock gating will make the core call out to the host
@@ -94,7 +119,7 @@
spin_unlock_irqrestore(&host->clk_lock, flags);
return;
}
- mmc_claim_host(host);
+ mutex_lock(&host->clk_gate_mutex);
spin_lock_irqsave(&host->clk_lock, flags);
if (!host->clk_requests) {
spin_unlock_irqrestore(&host->clk_lock, flags);
@@ -104,7 +129,7 @@
pr_debug("%s: gated MCI clock\n", mmc_hostname(host));
}
spin_unlock_irqrestore(&host->clk_lock, flags);
- mmc_release_host(host);
+ mutex_unlock(&host->clk_gate_mutex);
}
/*
@@ -113,24 +138,26 @@
static void mmc_host_clk_gate_work(struct work_struct *work)
{
struct mmc_host *host = container_of(work, struct mmc_host,
- clk_gate_work);
+ clk_gate_work.work);
mmc_host_clk_gate_delayed(host);
}
/**
- * mmc_host_clk_ungate - ungate hardware MCI clocks
+ * mmc_host_clk_hold - ungate hardware MCI clocks
* @host: host to ungate.
*
* Makes sure the host ios.clock is restored to a non-zero value
* past this call. Increase clock reference count and ungate clock
* if we're the first user.
*/
-void mmc_host_clk_ungate(struct mmc_host *host)
+void mmc_host_clk_hold(struct mmc_host *host)
{
unsigned long flags;
- mmc_claim_host(host);
+ /* cancel any clock gating work scheduled by mmc_host_clk_release() */
+ cancel_delayed_work_sync(&host->clk_gate_work);
+ mutex_lock(&host->clk_gate_mutex);
spin_lock_irqsave(&host->clk_lock, flags);
if (host->clk_gated) {
spin_unlock_irqrestore(&host->clk_lock, flags);
@@ -140,7 +167,7 @@
}
host->clk_requests++;
spin_unlock_irqrestore(&host->clk_lock, flags);
- mmc_release_host(host);
+ mutex_unlock(&host->clk_gate_mutex);
}
/**
@@ -164,14 +191,14 @@
}
/**
- * mmc_host_clk_gate - gate off hardware MCI clocks
+ * mmc_host_clk_release - gate off hardware MCI clocks
* @host: host to gate.
*
* Calls the host driver with ios.clock set to zero as often as possible
* in order to gate off hardware MCI clocks. Decrease clock reference
* count and schedule disabling of clock.
*/
-void mmc_host_clk_gate(struct mmc_host *host)
+void mmc_host_clk_release(struct mmc_host *host)
{
unsigned long flags;
@@ -179,7 +206,8 @@
host->clk_requests--;
if (mmc_host_may_gate_card(host->card) &&
!host->clk_requests)
- schedule_work(&host->clk_gate_work);
+ queue_delayed_work(system_nrt_wq, &host->clk_gate_work,
+ msecs_to_jiffies(host->clkgate_delay));
spin_unlock_irqrestore(&host->clk_lock, flags);
}
@@ -212,9 +240,15 @@
host->clk_requests = 0;
/* Hold MCI clock for 8 cycles by default */
host->clk_delay = 8;
+ /*
+ * Default clock gating delay is value is 200ms.
+ * This value can be tuned by writing into sysfs entry.
+ */
+ host->clkgate_delay = 200;
host->clk_gated = false;
- INIT_WORK(&host->clk_gate_work, mmc_host_clk_gate_work);
+ INIT_DELAYED_WORK(&host->clk_gate_work, mmc_host_clk_gate_work);
spin_lock_init(&host->clk_lock);
+ mutex_init(&host->clk_gate_mutex);
}
/**
@@ -227,14 +261,25 @@
* Wait for any outstanding gate and then make sure we're
* ungated before exiting.
*/
- if (cancel_work_sync(&host->clk_gate_work))
+ if (cancel_delayed_work_sync(&host->clk_gate_work))
mmc_host_clk_gate_delayed(host);
if (host->clk_gated)
- mmc_host_clk_ungate(host);
+ mmc_host_clk_hold(host);
/* There should be only one user now */
WARN_ON(host->clk_requests > 1);
}
+static inline void mmc_host_clk_sysfs_init(struct mmc_host *host)
+{
+ host->clkgate_delay_attr.show = clkgate_delay_show;
+ host->clkgate_delay_attr.store = clkgate_delay_store;
+ sysfs_attr_init(&host->clkgate_delay_attr.attr);
+ host->clkgate_delay_attr.attr.name = "clkgate_delay";
+ host->clkgate_delay_attr.attr.mode = S_IRUGO | S_IWUSR;
+ if (device_create_file(&host->class_dev, &host->clkgate_delay_attr))
+ pr_err("%s: Failed to create clkgate_delay sysfs entry\n",
+ mmc_hostname(host));
+}
#else
static inline void mmc_host_clk_init(struct mmc_host *host)
@@ -245,6 +290,9 @@
{
}
+static inline void mmc_host_clk_sysfs_init(struct mmc_host *host)
+{
+}
#endif
/**
@@ -397,6 +445,8 @@
#ifdef CONFIG_DEBUG_FS
mmc_add_host_debugfs(host);
#endif
+ mmc_host_clk_sysfs_init(host);
+
err = sysfs_create_group(&host->parent->kobj, &dev_attr_grp);
if (err)
pr_err("%s: failed to create sysfs group with err %d\n",
diff --git a/drivers/mmc/core/host.h b/drivers/mmc/core/host.h
index de199f9..fb8a5cd 100644
--- a/drivers/mmc/core/host.h
+++ b/drivers/mmc/core/host.h
@@ -16,16 +16,16 @@
void mmc_unregister_host_class(void);
#ifdef CONFIG_MMC_CLKGATE
-void mmc_host_clk_ungate(struct mmc_host *host);
-void mmc_host_clk_gate(struct mmc_host *host);
+void mmc_host_clk_hold(struct mmc_host *host);
+void mmc_host_clk_release(struct mmc_host *host);
unsigned int mmc_host_clk_rate(struct mmc_host *host);
#else
-static inline void mmc_host_clk_ungate(struct mmc_host *host)
+static inline void mmc_host_clk_hold(struct mmc_host *host)
{
}
-static inline void mmc_host_clk_gate(struct mmc_host *host)
+static inline void mmc_host_clk_release(struct mmc_host *host)
{
}
diff --git a/drivers/mmc/host/msm_sdcc.c b/drivers/mmc/host/msm_sdcc.c
index c1df55e..6181758 100644
--- a/drivers/mmc/host/msm_sdcc.c
+++ b/drivers/mmc/host/msm_sdcc.c
@@ -132,6 +132,8 @@
static void
msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd,
u32 c);
+static inline void msmsdcc_delay(struct msmsdcc_host *host);
+
#ifdef CONFIG_MMC_MSM_SPS_SUPPORT
static int msmsdcc_sps_reset_ep(struct msmsdcc_host *host,
@@ -207,77 +209,83 @@
* @host - Pointer to driver's host structure
*
*/
-static void msmsdcc_soft_reset_and_restore(struct msmsdcc_host *host)
+static void msmsdcc_soft_reset(struct msmsdcc_host *host)
{
- if (host->is_sps_mode) {
- /* Reset DML first */
- msmsdcc_dml_reset(host);
- /*
- * delay the SPS pipe reset in thread context as
- * sps_connect/sps_disconnect APIs can be called
- * only from non-atomic context.
- */
- host->sps.pipe_reset_pending = true;
- }
/*
* Reset SDCC controller's DPSM (data path state machine
* and CPSM (command path state machine).
*/
- mb();
writel_relaxed(0, host->base + MMCICOMMAND);
+ msmsdcc_delay(host);
writel_relaxed(0, host->base + MMCIDATACTRL);
- mb();
+ msmsdcc_delay(host);
+}
- pr_debug("%s: Applied soft reset to Controller\n",
- mmc_hostname(host->mmc));
+static void msmsdcc_hard_reset(struct msmsdcc_host *host)
+{
+ int ret;
- if (host->is_sps_mode)
- msmsdcc_dml_init(host);
+ /* Reset the controller */
+ ret = clk_reset(host->clk, CLK_RESET_ASSERT);
+ if (ret)
+ pr_err("%s: Clock assert failed at %u Hz"
+ " with err %d\n", mmc_hostname(host->mmc),
+ host->clk_rate, ret);
+
+ ret = clk_reset(host->clk, CLK_RESET_DEASSERT);
+ if (ret)
+ pr_err("%s: Clock deassert failed at %u Hz"
+ " with err %d\n", mmc_hostname(host->mmc),
+ host->clk_rate, ret);
+
+ /* Give some delay for clock reset to propogate to controller */
+ msmsdcc_delay(host);
}
static void msmsdcc_reset_and_restore(struct msmsdcc_host *host)
{
if (host->plat->sdcc_v4_sup) {
- msmsdcc_soft_reset_and_restore(host);
+ if (host->is_sps_mode) {
+ /* Reset DML first */
+ msmsdcc_dml_reset(host);
+ /*
+ * delay the SPS pipe reset in thread context as
+ * sps_connect/sps_disconnect APIs can be called
+ * only from non-atomic context.
+ */
+ host->sps.pipe_reset_pending = true;
+ }
+ mb();
+ msmsdcc_soft_reset(host);
+
+ pr_debug("%s: Applied soft reset to Controller\n",
+ mmc_hostname(host->mmc));
+
+ if (host->is_sps_mode)
+ msmsdcc_dml_init(host);
} else {
/* Give Clock reset (hard reset) to controller */
u32 mci_clk = 0;
u32 mci_mask0 = 0;
- int ret;
/* Save the controller state */
mci_clk = readl_relaxed(host->base + MMCICLOCK);
mci_mask0 = readl_relaxed(host->base + MMCIMASK0);
-
mb();
- /* Reset the controller */
- ret = clk_reset(host->clk, CLK_RESET_ASSERT);
- if (ret)
- pr_err("%s: Clock assert failed at %u Hz"
- " with err %d\n", mmc_hostname(host->mmc),
- host->clk_rate, ret);
- ret = clk_reset(host->clk, CLK_RESET_DEASSERT);
- if (ret)
- pr_err("%s: Clock deassert failed at %u Hz"
- " with err %d\n", mmc_hostname(host->mmc),
- host->clk_rate, ret);
-
+ msmsdcc_hard_reset(host);
pr_debug("%s: Controller has been reinitialized\n",
mmc_hostname(host->mmc));
- mb();
/* Restore the contoller state */
writel_relaxed(host->pwr, host->base + MMCIPOWER);
+ msmsdcc_delay(host);
writel_relaxed(mci_clk, host->base + MMCICLOCK);
+ msmsdcc_delay(host);
writel_relaxed(mci_mask0, host->base + MMCIMASK0);
- ret = clk_set_rate(host->clk, host->clk_rate);
- if (ret)
- pr_err("%s: Failed to set clk rate %u Hz. err %d\n",
- mmc_hostname(host->mmc),
- host->clk_rate, ret);
- mb();
+ mb(); /* no delay required after writing to MASK0 register */
}
+
if (host->dummy_52_needed)
host->dummy_52_needed = 0;
}
@@ -310,8 +318,6 @@
return retval;
}
-static inline void msmsdcc_delay(struct msmsdcc_host *host);
-
static void
msmsdcc_stop_data(struct msmsdcc_host *host)
{
@@ -361,8 +367,13 @@
msmsdcc_start_command_exec(struct msmsdcc_host *host, u32 arg, u32 c)
{
writel_relaxed(arg, host->base + MMCIARGUMENT);
- msmsdcc_delay(host);
writel_relaxed(c, host->base + MMCICOMMAND);
+ /*
+ * As after sending the command, we don't write any of the
+ * controller registers and just wait for the
+ * CMD_RESPOND_END/CMD_SENT/Command failure notication
+ * from Controller.
+ */
mb();
}
@@ -374,7 +385,6 @@
writel_relaxed(host->cmd_timeout, host->base + MMCIDATATIMER);
writel_relaxed((unsigned int)host->curr.xfer_size,
host->base + MMCIDATALENGTH);
- msmsdcc_delay(host); /* Allow data parms to be applied */
writel_relaxed(host->cmd_datactrl, host->base + MMCIDATACTRL);
msmsdcc_delay(host); /* Force delay prior to ADM or command */
@@ -607,6 +617,7 @@
host->dummy_52_sent = 1;
msmsdcc_start_command(host, &dummy52cmd,
MCI_CPSM_PROGENA);
+ spin_unlock_irqrestore(&host->lock, flags);
return;
}
msmsdcc_stop_data(host);
@@ -931,7 +942,7 @@
}
}
- if (host->prog_scan && (cmd->opcode == 12)) {
+ if ((cmd->flags & MMC_RSP_R1B) == MMC_RSP_R1B) {
*c |= MCI_CPSM_PROGENA;
host->prog_enable = 1;
}
@@ -1013,6 +1024,8 @@
if (data->flags & MMC_DATA_READ)
datactrl |= (MCI_DPSM_DIRECTION | MCI_RX_DATA_PEND);
+ else if (data->flags & MMC_DATA_WRITE)
+ datactrl |= MCI_DATA_PEND;
clks = (unsigned long long)data->timeout_ns * host->clk_rate;
do_div(clks, 1000000000UL);
@@ -1029,8 +1042,6 @@
host->dma.hdr.exec_func = msmsdcc_dma_exec_func;
host->dma.hdr.user = (void *)host;
host->dma.busy = 1;
- if ((data->flags & MMC_DATA_WRITE) && !host->curr.mrq->sbc)
- host->prog_scan = 1;
if (cmd) {
msmsdcc_start_command_deferred(host, cmd, &c);
@@ -1043,8 +1054,6 @@
msm_dmov_enqueue_cmd_ext(host->dma.channel, &host->dma.hdr);
} else {
/* SPS-BAM mode or PIO mode */
- if ((data->flags & MMC_DATA_WRITE) && !host->curr.mrq->sbc)
- host->prog_scan = 1;
writel_relaxed(timeout, base + MMCIDATATIMER);
writel_relaxed(host->curr.xfer_size, base + MMCIDATALENGTH);
@@ -1052,8 +1061,14 @@
writel_relaxed((readl_relaxed(host->base + MMCIMASK0) &
(~(MCI_IRQ_PIO))) | pio_irqmask,
host->base + MMCIMASK0);
- msmsdcc_delay(host); /* Allow parms to be applied */
writel_relaxed(datactrl, base + MMCIDATACTRL);
+ /*
+ * We don't need delay after writing to DATA_CTRL register
+ * if we are not writing to CMD register immediately after
+ * this. As we already have delay before sending the
+ * command, we just need mb() here.
+ */
+ mb();
if (cmd) {
msmsdcc_delay(host); /* Delay between data/command */
@@ -1239,8 +1254,10 @@
(~(MCI_IRQ_PIO))) | MCI_RXDATAAVLBLMASK,
host->base + MMCIMASK0);
if (!host->curr.xfer_remain) {
- /* Delay needed (same port was just written) */
- msmsdcc_delay(host);
+ /*
+ * back to back write to MASK0 register don't need
+ * synchronization delay.
+ */
writel_relaxed((readl_relaxed(host->base + MMCIMASK0) &
(~(MCI_IRQ_PIO))) | 0, host->base + MMCIMASK0);
}
@@ -1329,16 +1346,12 @@
} else { /* host->data == NULL */
if (!cmd->error && host->prog_enable) {
if (status & MCI_PROGDONE) {
- host->prog_scan = 0;
host->prog_enable = 0;
- msmsdcc_request_end(host, cmd->mrq);
+ msmsdcc_request_end(host, cmd->mrq);
} else
host->curr.cmd = cmd;
} else {
- if (host->prog_enable) {
- host->prog_scan = 0;
- host->prog_enable = 0;
- }
+ host->prog_enable = 0;
if (host->dummy_52_needed)
host->dummy_52_needed = 0;
if (cmd->data && cmd->error)
@@ -1351,9 +1364,6 @@
msmsdcc_start_command(host, host->curr.mrq->cmd, 0);
else
msmsdcc_request_start(host, host->curr.mrq);
- } else if (cmd->data) {
- if (!(cmd->data->flags & MMC_DATA_READ))
- msmsdcc_start_data(host, cmd->data, NULL, 0);
}
}
@@ -1560,9 +1570,9 @@
static void
msmsdcc_request_start(struct msmsdcc_host *host, struct mmc_request *mrq)
{
- if (mrq->data && mrq->data->flags & MMC_DATA_READ) {
+ if (mrq->data) {
/* Queue/read data, daisy-chain command when data starts */
- if (mrq->sbc)
+ if (mrq->sbc && (mrq->data->flags & MMC_DATA_READ))
msmsdcc_start_data(host, mrq->data, mrq->sbc, 0);
else
msmsdcc_start_data(host, mrq->data, mrq->cmd, 0);
@@ -1672,16 +1682,20 @@
{
int rc = 0;
- rc = regulator_set_optimum_mode(vreg->reg, uA_load);
- if (rc < 0)
- pr_err("%s: regulator_set_optimum_mode(reg=%s, uA_load=%d)"
- " failed. rc=%d\n", __func__, vreg->name,
- uA_load, rc);
- else
- /* regulator_set_optimum_mode() can return non zero value
- * even for success case.
- */
- rc = 0;
+ /* regulators that do not support regulator_set_voltage also
+ do not support regulator_set_optimum_mode */
+ if (vreg->set_voltage_sup) {
+ rc = regulator_set_optimum_mode(vreg->reg, uA_load);
+ if (rc < 0)
+ pr_err("%s: regulator_set_optimum_mode(reg=%s, "
+ "uA_load=%d) failed. rc=%d\n", __func__,
+ vreg->name, uA_load, rc);
+ else
+ /* regulator_set_optimum_mode() can return non zero
+ * value even for success case.
+ */
+ rc = 0;
+ }
return rc;
}
@@ -1922,7 +1936,9 @@
if (!IS_ERR(host->pclk))
clk_enable(host->pclk);
clk_enable(host->clk);
+ msmsdcc_delay(host);
} else {
+ msmsdcc_delay(host);
clk_disable(host->clk);
if (!IS_ERR(host->pclk))
clk_disable(host->pclk);
@@ -2120,6 +2136,10 @@
writel_relaxed(host->mci_irqenable,
host->base + MMCIMASK0);
}
+ } else {
+ writel_relaxed(host->mci_irqenable,
+ host->base + MMCIMASK0);
+ mb();
}
}
spin_unlock_irqrestore(&host->lock, flags);
@@ -2222,6 +2242,7 @@
msmsdcc_setup_pins(host, false);
break;
case MMC_POWER_UP:
+ /* writing PWR_UP bit is redundant */
pwr |= MCI_PWR_UP;
if (host->sdcc_irq_disabled) {
if (host->plat->cfg_mpm_sdiowakeup)
@@ -2255,7 +2276,7 @@
if (host->pwr != pwr) {
host->pwr = pwr;
writel_relaxed(pwr, host->base + MMCIPOWER);
- mb();
+ msmsdcc_delay(host);
}
if (!host->clks_on) {
/* force the clocks to be off */
@@ -2279,7 +2300,7 @@
writel_relaxed(MCI_SDIOINTMASK,
host->base + MMCIMASK0);
}
- msmsdcc_delay(host);
+ mb();
}
msmsdcc_setup_clocks(host, false);
host->clks_on = 0;
@@ -2299,7 +2320,7 @@
else
clk &= ~MCI_CLK_PWRSAVE;
writel_relaxed(clk, host->base + MMCICLOCK);
- mb();
+ msmsdcc_delay(host);
return 0;
}
@@ -2446,7 +2467,7 @@
/* Stop SD CLK output. */
writel_relaxed((readl_relaxed(host->base + MMCICLOCK) |
MCI_CLK_PWRSAVE), host->base + MMCICLOCK);
-
+ msmsdcc_delay(host);
spin_unlock_irqrestore(&host->lock, flags);
/*
@@ -2460,6 +2481,7 @@
spin_lock_irqsave(&host->lock, flags);
writel_relaxed((readl_relaxed(host->base + MMCICLOCK) |
IO_PAD_PWR_SWITCH), host->base + MMCICLOCK);
+ msmsdcc_delay(host);
host->io_pad_pwr_switch = 1;
spin_unlock_irqrestore(&host->lock, flags);
@@ -2470,6 +2492,7 @@
/* Start SD CLK output. */
writel_relaxed((readl_relaxed(host->base + MMCICLOCK)
& ~MCI_CLK_PWRSAVE), host->base + MMCICLOCK);
+ msmsdcc_delay(host);
spin_unlock_irqrestore(&host->lock, flags);
/*
@@ -2683,6 +2706,7 @@
*/
writel_relaxed((readl_relaxed(host->base + MMCICLOCK)
& ~MCI_CLK_PWRSAVE), host->base + MMCICLOCK);
+ msmsdcc_delay(host);
/* first of all reset the tuning block */
rc = msmsdcc_init_cm_sdc4_dll(host);
if (rc)
@@ -2757,6 +2781,7 @@
/* re-enable PWESAVE */
writel_relaxed((readl_relaxed(host->base + MMCICLOCK) |
MCI_CLK_PWRSAVE), host->base + MMCICLOCK);
+ msmsdcc_delay(host);
host->cmd19_tuning_in_progress = 0;
return rc;
}
@@ -3463,10 +3488,7 @@
msmsdcc_request_end(host, mrq);
}
} else {
- if (host->prog_enable) {
- host->prog_scan = 0;
- host->prog_enable = 0;
- }
+ host->prog_enable = 0;
msmsdcc_reset_and_restore(host);
msmsdcc_request_end(host, mrq);
}
@@ -3678,6 +3700,8 @@
msmsdcc_get_min_sup_clk_rate(host)));
host->clks_on = 1;
+ /* Apply Hard reset to SDCC to put it in power on default state */
+ msmsdcc_hard_reset(host);
ret = msmsdcc_vreg_init(host, true);
if (ret) {
@@ -3709,6 +3733,7 @@
mmc->caps |= plat->mmc_bus_width;
mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
+ mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
/*
* If we send the CMD23 before multi block write/read command
@@ -3749,8 +3774,6 @@
writel_relaxed(0, host->base + MMCIMASK0);
writel_relaxed(MCI_CLEAR_STATIC_MASK, host->base + MMCICLEAR);
- /* Delay needed (MMCIMASK0 was just written above) */
- msmsdcc_delay(host);
writel_relaxed(MCI_IRQENABLE, host->base + MMCIMASK0);
mb();
host->mci_irqenable = MCI_IRQENABLE;
@@ -4143,12 +4166,14 @@
* part of LPM), then clocks should be turned on before
* calling mmc_suspend_host() because mmc_suspend_host might
* send some commands to the card. The clocks will be turned
- * off again after mmc_suspend_host. Thus for SD/MMC/SDIO
+ * off again after mmc_suspend_host. Thus for SDIO
* cards, clocks will be turned on before mmc_suspend_host
* and turned off after mmc_suspend_host.
*/
- mmc->ios.clock = host->clk_rate;
- mmc->ops->set_ios(host->mmc, &host->mmc->ios);
+ if (mmc->card && mmc_card_sdio(mmc->card)) {
+ mmc->ios.clock = host->clk_rate;
+ mmc->ops->set_ios(host->mmc, &host->mmc->ios);
+ }
/*
* MMC core thinks that host is disabled by now since
@@ -4217,26 +4242,26 @@
enable_irq(host->core_irqres->start);
host->sdcc_irq_disabled = 0;
}
- }
- mmc->ios.clock = host->clk_rate;
- mmc->ops->set_ios(host->mmc, &host->mmc->ios);
+ mmc->ios.clock = host->clk_rate;
+ mmc->ops->set_ios(host->mmc, &host->mmc->ios);
- spin_lock_irqsave(&host->lock, flags);
- writel_relaxed(host->mci_irqenable, host->base + MMCIMASK0);
- mb();
+ spin_lock_irqsave(&host->lock, flags);
+ writel_relaxed(host->mci_irqenable,
+ host->base + MMCIMASK0);
+ mb();
- if (mmc->card && (mmc->card->type == MMC_TYPE_SDIO) &&
- (mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ) &&
- !host->sdio_irq_disabled) {
+ if ((mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ) &&
+ !host->sdio_irq_disabled) {
if (host->plat->sdiowakeup_irq) {
disable_irq_nosync(
host->plat->sdiowakeup_irq);
msmsdcc_disable_irq_wake(host);
host->sdio_irq_disabled = 1;
}
- }
+ }
- spin_unlock_irqrestore(&host->lock, flags);
+ spin_unlock_irqrestore(&host->lock, flags);
+ }
mmc_resume_host(mmc);
diff --git a/drivers/mmc/host/msm_sdcc.h b/drivers/mmc/host/msm_sdcc.h
index 31ece6e..590c293 100644
--- a/drivers/mmc/host/msm_sdcc.h
+++ b/drivers/mmc/host/msm_sdcc.h
@@ -77,6 +77,7 @@
#define MCI_DPSM_DIRECTION (1 << 1)
#define MCI_DPSM_MODE (1 << 2)
#define MCI_DPSM_DMAENABLE (1 << 3)
+#define MCI_DATA_PEND (1 << 17)
#define MCI_AUTO_PROG_DONE (1 << 19)
#define MCI_RX_DATA_PEND (1 << 20)
@@ -208,7 +209,7 @@
#define NR_SG 32
-#define MSM_MMC_IDLE_TIMEOUT 10000 /* msecs */
+#define MSM_MMC_IDLE_TIMEOUT 5000 /* msecs */
/*
* Set the request timeout to 10secs to allow
@@ -332,7 +333,6 @@
struct tasklet_struct dma_tlet;
- unsigned int prog_scan;
unsigned int prog_enable;
/* Command parameters */
diff --git a/drivers/net/msm_rmnet_bam.c b/drivers/net/msm_rmnet_bam.c
index 8a3e427..aeb85dc 100644
--- a/drivers/net/msm_rmnet_bam.c
+++ b/drivers/net/msm_rmnet_bam.c
@@ -28,6 +28,7 @@
#include <linux/wakelock.h>
#include <linux/if_arp.h>
#include <linux/msm_rmnet.h>
+#include <linux/platform_device.h>
#ifdef CONFIG_HAS_EARLYSUSPEND
#include <linux/earlysuspend.h>
@@ -82,6 +83,7 @@
u32 operation_mode; /* IOCTL specified mode (protocol, QoS header) */
uint8_t device_up;
uint8_t waiting_for_ul;
+ uint8_t in_reset;
};
static uint8_t ul_is_connected;
@@ -618,6 +620,51 @@
dev->watchdog_timeo = 1000; /* 10 seconds? */
}
+static struct net_device *netdevs[RMNET_DEVICE_COUNT];
+static struct platform_driver bam_rmnet_drivers[RMNET_DEVICE_COUNT];
+
+static int bam_rmnet_probe(struct platform_device *pdev)
+{
+ int i;
+ char name[BAM_DMUX_CH_NAME_MAX_LEN];
+ struct rmnet_private *p;
+
+ for (i = 0; i < RMNET_DEVICE_COUNT; ++i) {
+ scnprintf(name, BAM_DMUX_CH_NAME_MAX_LEN, "bam_dmux_ch_%d", i);
+ if (!strncmp(pdev->name, name, BAM_DMUX_CH_NAME_MAX_LEN))
+ break;
+ }
+
+ p = netdev_priv(netdevs[i]);
+ if (p->in_reset) {
+ p->in_reset = 0;
+ msm_bam_dmux_open(p->ch_id, netdevs[i], bam_notify);
+ netif_carrier_on(netdevs[i]);
+ netif_start_queue(netdevs[i]);
+ }
+
+ return 0;
+}
+
+static int bam_rmnet_remove(struct platform_device *pdev)
+{
+ int i;
+ char name[BAM_DMUX_CH_NAME_MAX_LEN];
+ struct rmnet_private *p;
+
+ for (i = 0; i < RMNET_DEVICE_COUNT; ++i) {
+ scnprintf(name, BAM_DMUX_CH_NAME_MAX_LEN, "bam_dmux_ch_%d", i);
+ if (!strncmp(pdev->name, name, BAM_DMUX_CH_NAME_MAX_LEN))
+ break;
+ }
+
+ p = netdev_priv(netdevs[i]);
+ p->in_reset = 1;
+ msm_bam_dmux_close(p->ch_id);
+ netif_carrier_off(netdevs[i]);
+ netif_stop_queue(netdevs[i]);
+ return 0;
+}
static int __init rmnet_init(void)
{
@@ -626,6 +673,7 @@
struct net_device *dev;
struct rmnet_private *p;
unsigned n;
+ char *tempname;
pr_info("%s: BAM devices[%d]\n", __func__, RMNET_DEVICE_COUNT);
@@ -643,12 +691,14 @@
if (!dev)
return -ENOMEM;
+ netdevs[n] = dev;
d = &(dev->dev);
p = netdev_priv(dev);
/* Initial config uses Ethernet */
p->operation_mode = RMNET_MODE_LLP_ETH;
p->ch_id = n;
p->waiting_for_ul = 0;
+ p->in_reset = 0;
spin_lock_init(&p->lock);
#ifdef CONFIG_MSM_RMNET_DEBUG
p->timeout_us = timeout_us;
@@ -677,6 +727,18 @@
rmnet0 = d;
#endif
#endif
+ bam_rmnet_drivers[n].probe = bam_rmnet_probe;
+ bam_rmnet_drivers[n].remove = bam_rmnet_remove;
+ tempname = kmalloc(BAM_DMUX_CH_NAME_MAX_LEN, GFP_KERNEL);
+ if (tempname == NULL)
+ return -ENOMEM;
+ scnprintf(tempname, BAM_DMUX_CH_NAME_MAX_LEN, "bam_dmux_ch_%d",
+ n);
+ bam_rmnet_drivers[n].driver.name = tempname;
+ bam_rmnet_drivers[n].driver.owner = THIS_MODULE;
+ ret = platform_driver_register(&bam_rmnet_drivers[n]);
+ if (!ret)
+ return ret;
}
return 0;
}
diff --git a/drivers/net/wireless/libra/qcomwlan7x27a_pwrif.c b/drivers/net/wireless/libra/qcomwlan7x27a_pwrif.c
index 5da7a42..82625b5 100644
--- a/drivers/net/wireless/libra/qcomwlan7x27a_pwrif.c
+++ b/drivers/net/wireless/libra/qcomwlan7x27a_pwrif.c
@@ -32,7 +32,8 @@
struct wlan_vreg_info {
const char *vreg_id;
- unsigned int vreg_level;
+ unsigned int level_min;
+ unsigned int level_max;
unsigned int pmapp_id;
unsigned int is_vreg_pin_controlled;
struct regulator *reg;
@@ -40,12 +41,12 @@
static struct wlan_vreg_info vreg_info[] = {
- {"bt", 3050000, 21, 1, NULL},
- {"msme1", 1800000, 2, 0, NULL},
- {"wlan_tcx0", 1800000, 53, 0, NULL},
- {"wlan4", 1200000, 23, 0, NULL},
- {"wlan2", 1350000, 9, 1, NULL},
- {"wlan3", 1200000, 10, 1, NULL},
+ {"bt", 3050000, 3050000, 21, 1, NULL},
+ {"msme1", 1800000, 1800000, 2, 0, NULL},
+ {"wlan_tcx0", 1800000, 1800000, 53, 0, NULL},
+ {"wlan4", 1200000, 1200000, 23, 0, NULL},
+ {"wlan2", 1350000, 1350000, 9, 1, NULL},
+ {"wlan3", 1200000, 1200000, 10, 1, NULL},
};
static int qrf6285_init_regs(void)
@@ -55,8 +56,8 @@
for (i = 0; i < ARRAY_SIZE(regs); i++) {
regs[i].supply = vreg_info[i].vreg_id;
- regs[i].min_uV = vreg_info[i].vreg_level;
- regs[i].max_uV = vreg_info[i].vreg_level;
+ regs[i].min_uV = vreg_info[i].level_min;
+ regs[i].max_uV = vreg_info[i].level_max;
}
rc = regulator_bulk_get(NULL, ARRAY_SIZE(regs), regs);
@@ -128,8 +129,8 @@
if (on) {
rc = regulator_set_voltage(vreg_info[index].reg,
- vreg_info[index].vreg_level,
- vreg_info[index].vreg_level);
+ vreg_info[index].level_min,
+ vreg_info[index].level_max);
if (rc) {
pr_err("%s:%s set voltage failed %d\n",
__func__, vreg_info[index].vreg_id, rc);
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index 179a4ac..cca1035 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -261,7 +261,8 @@
config ISL9519_CHARGER
tristate "isl9519 charger"
- depends on BATTERY_MSM8X60
+ depends on (BATTERY_MSM8X60 || PM8921_CHARGER)
+ depends on I2C
default n
help
The isl9519q charger chip from intersil is connected to an external
diff --git a/drivers/power/isl9519q.c b/drivers/power/isl9519q.c
index a45d286..733de45 100644
--- a/drivers/power/isl9519q.c
+++ b/drivers/power/isl9519q.c
@@ -20,9 +20,11 @@
#include <linux/workqueue.h>
#include <linux/interrupt.h>
#include <linux/msm-charger.h>
+#include <linux/mfd/pm8xxx/pm8921-charger.h>
#include <linux/slab.h>
#include <linux/i2c/isl9519.h>
#include <linux/msm_adc.h>
+#include <linux/spinlock.h>
#define CHG_CURRENT_REG 0x14
#define MAX_SYS_VOLTAGE_REG 0x15
@@ -34,7 +36,7 @@
#define TRCKL_CHG_STATUS_BIT 0x80
-#define ISL9519_CHG_PERIOD ((HZ) * 150)
+#define ISL9519_CHG_PERIOD_SEC 150
struct isl9519q_struct {
struct i2c_client *client;
@@ -52,6 +54,10 @@
struct msm_hardware_charger adapter_hw_chg;
int suspended;
int charge_at_resume;
+ struct ext_chg_pm8921 ext_chg;
+ spinlock_t lock;
+ bool notify_by_pmic;
+ bool trickle;
};
static int isl9519q_read_reg(struct i2c_client *client, int reg,
@@ -70,6 +76,8 @@
} else
*val = ret;
+ pr_debug("%s.reg=0x%x.val=0x%x.\n", __func__, reg, *val);
+
return 0;
}
@@ -79,6 +87,8 @@
int ret;
struct isl9519q_struct *isl_chg;
+ pr_debug("%s.reg=0x%x.val=0x%x.\n", __func__, reg, val);
+
isl_chg = i2c_get_clientdata(client);
ret = i2c_smbus_write_word_data(isl_chg->client, reg, val);
@@ -91,6 +101,14 @@
return 0;
}
+/**
+ * Read charge-current via ADC.
+ *
+ * The ISL CCMON (charge-current-monitor) pin is connected to
+ * the PMIC MPP#X pin.
+ * This not required when notify_by_pmic is used where the PMIC
+ * uses BMS to notify the ISL on charging-done / charge-resume.
+ */
static int isl_read_adc(int channel, int *mv_reading)
{
int ret;
@@ -136,98 +154,129 @@
out:
*mv_reading = 0;
pr_debug("%s: done with error for %d\n", __func__, channel);
- return -EINVAL;
+ return -EINVAL;
}
-static void isl9519q_charge(struct work_struct *isl9519_work)
+static bool is_trickle_charging(struct isl9519q_struct *isl_chg)
{
- u16 temp;
+ u16 ctrl = 0;
int ret;
+
+ ret = isl9519q_read_reg(isl_chg->client, CONTROL_REG, &ctrl);
+
+ if (!ret) {
+ pr_debug("%s.control_reg=0x%x.\n", __func__, ctrl);
+ } else {
+ dev_err(&isl_chg->client->dev,
+ "%s couldnt read cntrl reg\n", __func__);
+ }
+
+ if (ctrl & TRCKL_CHG_STATUS_BIT)
+ return true;
+
+ return false;
+}
+
+static void isl_adapter_check_ichg(struct isl9519q_struct *isl_chg)
+{
+ int ichg; /* isl charger current */
+ int mv_reading = 0;
+
+ ichg = isl_read_adc(CHANNEL_ADC_BATT_AMON, &mv_reading);
+
+ dev_dbg(&isl_chg->client->dev, "%s mv_reading=%d\n",
+ __func__, mv_reading);
+ dev_dbg(&isl_chg->client->dev, "%s isl_charger_current=%d\n",
+ __func__, ichg);
+
+ if (ichg >= 0 && ichg <= isl_chg->term_current)
+ msm_charger_notify_event(&isl_chg->adapter_hw_chg,
+ CHG_DONE_EVENT);
+
+ isl_chg->trickle = is_trickle_charging(isl_chg);
+ if (isl_chg->trickle)
+ msm_charger_notify_event(&isl_chg->adapter_hw_chg,
+ CHG_BATT_BEGIN_FAST_CHARGING);
+}
+
+/**
+ * isl9519q_worker
+ *
+ * Periodic task required to kick the ISL HW watchdog to keep
+ * charging.
+ *
+ * @isl9519_work: work context.
+ */
+static void isl9519q_worker(struct work_struct *isl9519_work)
+{
struct isl9519q_struct *isl_chg;
- int isl_charger_current;
- int mv_reading;
isl_chg = container_of(isl9519_work, struct isl9519q_struct,
charge_work.work);
dev_dbg(&isl_chg->client->dev, "%s\n", __func__);
- if (isl_chg->charging) {
- isl_charger_current = isl_read_adc(CHANNEL_ADC_BATT_AMON,
- &mv_reading);
- dev_dbg(&isl_chg->client->dev, "%s mv_reading=%d\n",
- __func__, mv_reading);
- dev_dbg(&isl_chg->client->dev, "%s isl_charger_current=%d\n",
- __func__, isl_charger_current);
- if (isl_charger_current >= 0
- && isl_charger_current <= isl_chg->term_current) {
- msm_charger_notify_event(
- &isl_chg->adapter_hw_chg,
- CHG_DONE_EVENT);
- }
- isl9519q_write_reg(isl_chg->client, CHG_CURRENT_REG,
- isl_chg->chgcurrent);
- ret = isl9519q_read_reg(isl_chg->client, CONTROL_REG, &temp);
- if (!ret) {
- if (!(temp & TRCKL_CHG_STATUS_BIT))
- msm_charger_notify_event(
- &isl_chg->adapter_hw_chg,
- CHG_BATT_BEGIN_FAST_CHARGING);
- } else {
- dev_err(&isl_chg->client->dev,
- "%s couldnt read cntrl reg\n", __func__);
- }
- schedule_delayed_work(&isl_chg->charge_work,
- ISL9519_CHG_PERIOD);
+ if (!isl_chg->charging) {
+ pr_info("%s.stop charging.\n", __func__);
+ isl9519q_write_reg(isl_chg->client, CHG_CURRENT_REG, 0);
+ return; /* Stop periodic worker */
}
+
+ /* Kick the dog by writting to CHG_CURRENT_REG */
+ isl9519q_write_reg(isl_chg->client, CHG_CURRENT_REG,
+ isl_chg->chgcurrent);
+
+ if (isl_chg->notify_by_pmic)
+ isl_chg->trickle = is_trickle_charging(isl_chg);
+ else
+ isl_adapter_check_ichg(isl_chg);
+
+ schedule_delayed_work(&isl_chg->charge_work,
+ (ISL9519_CHG_PERIOD_SEC * HZ));
}
-static int isl9519q_start_charging(struct msm_hardware_charger *hw_chg,
- int chg_voltage, int chg_current)
+static int isl9519q_start_charging(struct isl9519q_struct *isl_chg,
+ int chg_voltage, int chg_current)
{
- struct isl9519q_struct *isl_chg;
int ret = 0;
- isl_chg = container_of(hw_chg, struct isl9519q_struct, adapter_hw_chg);
- if (isl_chg->charging)
- /* we are already charging */
+ pr_info("%s.\n", __func__);
+
+ if (isl_chg->charging) {
+ pr_warn("%s.already charging.\n", __func__);
return 0;
+ }
if (isl_chg->suspended) {
+ pr_warn("%s.suspended - can't start charging.\n", __func__);
isl_chg->charge_at_resume = 1;
return 0;
}
- dev_dbg(&isl_chg->client->dev, "%s\n", __func__);
+ dev_dbg(&isl_chg->client->dev,
+ "%s starting timed work.period=%d seconds.\n",
+ __func__, (int) ISL9519_CHG_PERIOD_SEC);
- ret = isl9519q_write_reg(isl_chg->client, CHG_CURRENT_REG,
- isl_chg->chgcurrent);
- if (ret) {
- dev_err(&isl_chg->client->dev,
- "%s coulnt write to current_reg\n", __func__);
- goto out;
- }
+ /*
+ * The ISL will start charging from the worker context.
+ * This API might be called from interrupt context.
+ */
+ schedule_delayed_work(&isl_chg->charge_work, 1);
- dev_dbg(&isl_chg->client->dev, "%s starting timed work\n",
- __func__);
- schedule_delayed_work(&isl_chg->charge_work,
- ISL9519_CHG_PERIOD);
isl_chg->charging = true;
-out:
return ret;
}
-static int isl9519q_stop_charging(struct msm_hardware_charger *hw_chg)
+static int isl9519q_stop_charging(struct isl9519q_struct *isl_chg)
{
- struct isl9519q_struct *isl_chg;
- int ret = 0;
+ pr_info("%s.\n", __func__);
- isl_chg = container_of(hw_chg, struct isl9519q_struct, adapter_hw_chg);
- if (!(isl_chg->charging))
- /* we arent charging */
+ if (!(isl_chg->charging)) {
+ pr_warn("%s.already not charging.\n", __func__);
return 0;
+ }
if (isl_chg->suspended) {
isl_chg->charge_at_resume = 0;
@@ -236,17 +285,71 @@
dev_dbg(&isl_chg->client->dev, "%s\n", __func__);
- ret = isl9519q_write_reg(isl_chg->client, CHG_CURRENT_REG, 0);
- if (ret) {
- dev_err(&isl_chg->client->dev,
- "%s coulnt write to current_reg\n", __func__);
- goto out;
- }
-
isl_chg->charging = false;
- cancel_delayed_work(&isl_chg->charge_work);
-out:
- return ret;
+ isl_chg->trickle = false;
+ /*
+ * The ISL will stop charging from the worker context.
+ * This API might be called from interrupt context.
+ */
+ schedule_delayed_work(&isl_chg->charge_work, 1);
+
+ return 0;
+}
+
+static int isl_ext_start_charging(void *ctx)
+{
+ int rc;
+ struct isl9519q_struct *isl_chg = ctx;
+ unsigned long flags;
+
+ spin_lock_irqsave(&isl_chg->lock, flags);
+ rc = isl9519q_start_charging(isl_chg, 0, isl_chg->chgcurrent);
+ spin_unlock_irqrestore(&isl_chg->lock, flags);
+
+ return rc;
+}
+
+static int isl_ext_stop_charging(void *ctx)
+{
+ int rc;
+ struct isl9519q_struct *isl_chg = ctx;
+ unsigned long flags;
+
+ spin_lock_irqsave(&isl_chg->lock, flags);
+ rc = isl9519q_stop_charging(isl_chg);
+ spin_unlock_irqrestore(&isl_chg->lock, flags);
+
+ return rc;
+}
+
+static bool isl_ext_is_trickle(void *ctx)
+{
+ struct isl9519q_struct *isl_chg = ctx;
+
+ return isl_chg->trickle;
+}
+
+static int isl_adapter_start_charging(struct msm_hardware_charger *hw_chg,
+ int chg_voltage, int chg_current)
+{
+ int rc;
+ struct isl9519q_struct *isl_chg;
+
+ isl_chg = container_of(hw_chg, struct isl9519q_struct, adapter_hw_chg);
+ rc = isl9519q_start_charging(isl_chg, chg_voltage, chg_current);
+
+ return rc;
+}
+
+static int isl_adapter_stop_charging(struct msm_hardware_charger *hw_chg)
+{
+ int rc;
+ struct isl9519q_struct *isl_chg;
+
+ isl_chg = container_of(hw_chg, struct isl9519q_struct, adapter_hw_chg);
+ rc = isl9519q_stop_charging(isl_chg);
+
+ return rc;
}
static int isl9519q_charging_switched(struct msm_hardware_charger *hw_chg)
@@ -296,6 +399,93 @@
#define DEFAULT_MAX_VOLTAGE_REG_VALUE 0x1070
#define DEFAULT_MIN_VOLTAGE_REG_VALUE 0x0D00
+static int __devinit isl9519q_init_adapter(struct isl9519q_struct *isl_chg)
+{
+ int ret;
+ struct isl_platform_data *pdata = isl_chg->client->dev.platform_data;
+ struct i2c_client *client = isl_chg->client;
+
+ isl_chg->adapter_hw_chg.type = CHG_TYPE_AC;
+ isl_chg->adapter_hw_chg.rating = 2;
+ isl_chg->adapter_hw_chg.name = "isl-adapter";
+ isl_chg->adapter_hw_chg.start_charging = isl_adapter_start_charging;
+ isl_chg->adapter_hw_chg.stop_charging = isl_adapter_stop_charging;
+ isl_chg->adapter_hw_chg.charging_switched = isl9519q_charging_switched;
+
+ ret = gpio_request(pdata->valid_n_gpio, "isl_charger_valid");
+ if (ret) {
+ dev_err(&client->dev, "%s gpio_request failed "
+ "for %d ret=%d\n",
+ __func__, pdata->valid_n_gpio, ret);
+ goto out;
+ }
+
+ ret = msm_charger_register(&isl_chg->adapter_hw_chg);
+ if (ret) {
+ dev_err(&client->dev,
+ "%s msm_charger_register failed for ret =%d\n",
+ __func__, ret);
+ goto free_gpio;
+ }
+
+ ret = request_threaded_irq(client->irq, NULL,
+ isl_valid_handler,
+ IRQF_TRIGGER_FALLING |
+ IRQF_TRIGGER_RISING,
+ "isl_charger_valid", client);
+ if (ret) {
+ dev_err(&client->dev,
+ "%s request_threaded_irq failed "
+ "for %d ret =%d\n",
+ __func__, client->irq, ret);
+ goto unregister;
+ }
+ irq_set_irq_wake(client->irq, 1);
+
+ ret = gpio_get_value_cansleep(isl_chg->valid_n_gpio);
+ if (ret < 0) {
+ dev_err(&client->dev,
+ "%s gpio_get_value failed for %d ret=%d\n",
+ __func__, pdata->valid_n_gpio, ret);
+ /* assume absent */
+ ret = 1;
+ }
+ if (!ret) {
+ msm_charger_notify_event(&isl_chg->adapter_hw_chg,
+ CHG_INSERTED_EVENT);
+ isl_chg->present = 1;
+ }
+
+ return 0;
+
+unregister:
+ msm_charger_unregister(&isl_chg->adapter_hw_chg);
+free_gpio:
+ gpio_free(pdata->valid_n_gpio);
+out:
+ return ret;
+
+}
+
+static int __devinit isl9519q_init_ext_chg(struct isl9519q_struct *isl_chg)
+{
+ int ret;
+
+ isl_chg->ext_chg.name = "isl9519q";
+ isl_chg->ext_chg.ctx = isl_chg;
+ isl_chg->ext_chg.start_charging = isl_ext_start_charging;
+ isl_chg->ext_chg.stop_charging = isl_ext_stop_charging;
+ isl_chg->ext_chg.is_trickle = isl_ext_is_trickle;
+ ret = register_external_dc_charger(&isl_chg->ext_chg);
+ if (ret) {
+ pr_err("%s.failed to register external dc charger.ret=%d.\n",
+ __func__, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
static int __devinit isl9519q_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
@@ -306,6 +496,8 @@
ret = 0;
pdata = client->dev.platform_data;
+ pr_info("%s.\n", __func__);
+
if (pdata == NULL) {
dev_err(&client->dev, "%s no platform data\n", __func__);
ret = -EINVAL;
@@ -324,7 +516,9 @@
goto out;
}
- INIT_DELAYED_WORK(&isl_chg->charge_work, isl9519q_charge);
+ spin_lock_init(&isl_chg->lock);
+
+ INIT_DELAYED_WORK(&isl_chg->charge_work, isl9519q_worker);
isl_chg->client = client;
isl_chg->chgcurrent = pdata->chgcurrent;
isl_chg->term_current = pdata->term_current;
@@ -337,12 +531,14 @@
isl_chg->chgcurrent &= ~0x7F;
isl_chg->input_current &= ~0x7F;
- isl_chg->adapter_hw_chg.type = CHG_TYPE_AC;
- isl_chg->adapter_hw_chg.rating = 2;
- isl_chg->adapter_hw_chg.name = "isl-adapter";
- isl_chg->adapter_hw_chg.start_charging = isl9519q_start_charging;
- isl_chg->adapter_hw_chg.stop_charging = isl9519q_stop_charging;
- isl_chg->adapter_hw_chg.charging_switched = isl9519q_charging_switched;
+ /**
+ * ISL is Notified by PMIC to start/stop charging, rather than
+ * handling interrupt from ISL for End-Of-Chargring, and
+ * monitoring the charge-current periodically. The valid_n_gpio
+ * is also not used, dc-present is detected by PMIC.
+ */
+ isl_chg->notify_by_pmic = (client->irq == 0);
+ i2c_set_clientdata(client, isl_chg);
if (pdata->chg_detection_config) {
ret = pdata->chg_detection_config();
@@ -353,35 +549,6 @@
}
}
- ret = gpio_request(pdata->valid_n_gpio, "isl_charger_valid");
- if (ret) {
- dev_err(&client->dev, "%s gpio_request failed for %d ret=%d\n",
- __func__, pdata->valid_n_gpio, ret);
- goto free_isl_chg;
- }
-
- i2c_set_clientdata(client, isl_chg);
-
- ret = msm_charger_register(&isl_chg->adapter_hw_chg);
- if (ret) {
- dev_err(&client->dev,
- "%s msm_charger_register failed for ret =%d\n",
- __func__, ret);
- goto free_gpio;
- }
-
- ret = request_threaded_irq(client->irq, NULL,
- isl_valid_handler,
- IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
- "isl_charger_valid", client);
- if (ret) {
- dev_err(&client->dev,
- "%s request_threaded_irq failed for %d ret =%d\n",
- __func__, client->irq, ret);
- goto unregister;
- }
- irq_set_irq_wake(client->irq, 1);
-
isl_chg->max_system_voltage &= MAX_VOLTAGE_REG_MASK;
isl_chg->min_system_voltage &= MIN_VOLTAGE_REG_MASK;
if (isl_chg->max_system_voltage == 0)
@@ -391,57 +558,34 @@
ret = isl9519q_write_reg(isl_chg->client, MAX_SYS_VOLTAGE_REG,
isl_chg->max_system_voltage);
- if (ret) {
- dev_err(&client->dev,
- "%s couldnt write to MAX_SYS_VOLTAGE_REG ret=%d\n",
- __func__, ret);
- goto free_irq;
- }
+ if (ret)
+ goto free_isl_chg;
ret = isl9519q_write_reg(isl_chg->client, MIN_SYS_VOLTAGE_REG,
isl_chg->min_system_voltage);
- if (ret) {
- dev_err(&client->dev,
- "%s couldnt write to MIN_SYS_VOLTAGE_REG ret=%d\n",
- __func__, ret);
- goto free_irq;
- }
+ if (ret)
+ goto free_isl_chg;
if (isl_chg->input_current) {
ret = isl9519q_write_reg(isl_chg->client,
INPUT_CURRENT_REG,
isl_chg->input_current);
- if (ret) {
- dev_err(&client->dev,
- "%s couldnt write INPUT_CURRENT_REG ret=%d\n",
- __func__, ret);
- goto free_irq;
- }
+ if (ret)
+ goto free_isl_chg;
}
- ret = gpio_get_value_cansleep(isl_chg->valid_n_gpio);
- if (ret < 0) {
- dev_err(&client->dev,
- "%s gpio_get_value failed for %d ret=%d\n", __func__,
- pdata->valid_n_gpio, ret);
- /* assume absent */
- ret = 1;
- }
- if (!ret) {
- msm_charger_notify_event(&isl_chg->adapter_hw_chg,
- CHG_INSERTED_EVENT);
- isl_chg->present = 1;
- }
+ if (isl_chg->notify_by_pmic)
+ ret = isl9519q_init_ext_chg(isl_chg);
+ else
+ ret = isl9519q_init_adapter(isl_chg);
- pr_debug("%s OK chg_present=%d\n", __func__, isl_chg->present);
+ if (ret)
+ goto free_isl_chg;
+
+ pr_info("%s OK.\n", __func__);
+
return 0;
-free_irq:
- free_irq(client->irq, NULL);
-unregister:
- msm_charger_unregister(&isl_chg->adapter_hw_chg);
-free_gpio:
- gpio_free(pdata->valid_n_gpio);
free_isl_chg:
kfree(isl_chg);
out:
@@ -493,7 +637,7 @@
isl_chg->suspended = 0;
if (isl_chg->charge_at_resume) {
isl_chg->charge_at_resume = 0;
- isl9519q_start_charging(&isl_chg->adapter_hw_chg, 0, 0);
+ isl9519q_start_charging(isl_chg, 0, 0);
}
return 0;
}
@@ -519,10 +663,12 @@
static int __init isl9519q_init(void)
{
+ pr_info("%s. isl9519q SW rev 1.01\n", __func__);
+
return i2c_add_driver(&isl9519q_driver);
}
-module_init(isl9519q_init);
+late_initcall_sync(isl9519q_init);
static void __exit isl9519q_exit(void)
{
diff --git a/drivers/power/pm8921-bms.c b/drivers/power/pm8921-bms.c
index e666bfc..2d0f7cd 100644
--- a/drivers/power/pm8921-bms.c
+++ b/drivers/power/pm8921-bms.c
@@ -23,6 +23,7 @@
#include <linux/bitops.h>
#include <linux/debugfs.h>
#include <linux/slab.h>
+#include <linux/delay.h>
#define BMS_CONTROL 0x224
#define BMS_OUTPUT0 0x230
@@ -35,14 +36,19 @@
#define CCADC_DATA1 0x245
#define CCADC_OFFSET_TRIM1 0x34A
#define CCADC_OFFSET_TRIM0 0x34B
+#define CCADC_FULLSCALE_TRIM1 0x34C
+#define CCADC_FULLSCALE_TRIM0 0x34D
#define ADC_ARB_SECP_CNTRL 0x190
#define ADC_ARB_SECP_AMUX_CNTRL 0x191
#define ADC_ARB_SECP_ANA_PARAM 0x192
+#define ADC_ARB_SECP_DIG_PARAM 0x193
#define ADC_ARB_SECP_RSV 0x194
#define ADC_ARB_SECP_DATA1 0x195
#define ADC_ARB_SECP_DATA0 0x196
+#define ADC_ARB_BMS_CNTRL 0x18D
+
enum pmic_bms_interrupts {
PM8921_BMS_SBI_WRITE_OK,
PM8921_BMS_CC_THR,
@@ -51,19 +57,10 @@
PM8921_BMS_OCV_FOR_R,
PM8921_BMS_GOOD_OCV,
PM8921_BMS_VSENSE_AVG,
+ PM8921_BMS_CCADC_EOC,
PM_BMS_MAX_INTS,
};
-/**
- * struct pm8921_bms_chip -device information
- * @dev: device pointer to access the parent
- * @dent: debugfs directory
- * @r_sense: batt sense resistance value
- * @i_test: peak current
- * @v_failure: battery dead voltage
- * @fcc: battery capacity
- *
- */
struct pm8921_bms_chip {
struct device *dev;
struct dentry *dent;
@@ -76,7 +73,10 @@
struct pc_temp_ocv_lut *pc_temp_ocv_lut;
struct pc_sf_lut *pc_sf_lut;
struct work_struct calib_hkadc_work;
+ struct delayed_work calib_ccadc_work;
unsigned int calib_delay_ms;
+ int ccadc_gain_uv;
+ u16 ccadc_result_offset;
unsigned int revision;
unsigned int xoadc_v0625;
unsigned int xoadc_v125;
@@ -88,30 +88,122 @@
unsigned int pmic_bms_irq[PM_BMS_MAX_INTS];
DECLARE_BITMAP(enabled_irqs, PM_BMS_MAX_INTS);
spinlock_t bms_output_lock;
+ struct single_row_lut *adjusted_fcc_temp_lut;
};
static struct pm8921_bms_chip *the_chip;
#define DEFAULT_RBATT_MOHMS 128
-#define DEFAULT_UNUSABLE_CHARGE_MAH 10
#define DEFAULT_OCV_MICROVOLTS 3900000
-#define DEFAULT_REMAINING_CHARGE_MAH 990
-#define DEFAULT_COULUMB_COUNTER 0
#define DEFAULT_CHARGE_CYCLES 0
+static int last_chargecycles = DEFAULT_CHARGE_CYCLES;
+static int last_charge_increase;
+module_param(last_chargecycles, int, 0644);
+module_param(last_charge_increase, int, 0644);
+
static int last_rbatt = -EINVAL;
static int last_ocv_uv = -EINVAL;
static int last_soc = -EINVAL;
static int last_real_fcc = -EINVAL;
+static int last_real_fcc_batt_temp = -EINVAL;
-static int last_chargecycles = DEFAULT_CHARGE_CYCLES;
-static int last_charge_increase;
+static int bms_ops_set(const char *val, const struct kernel_param *kp)
+{
+ if (*(int *)kp->arg == -EINVAL)
+ return param_set_int(val, kp);
+ else
+ return 0;
+}
-module_param(last_rbatt, int, 0644);
-module_param(last_ocv_uv, int, 0644);
-module_param(last_chargecycles, int, 0644);
-module_param(last_charge_increase, int, 0644);
-module_param(last_real_fcc, int, 0644);
+static struct kernel_param_ops bms_param_ops = {
+ .set = bms_ops_set,
+ .get = param_get_int,
+};
+
+module_param_cb(last_rbatt, &bms_param_ops, &last_rbatt, 0644);
+module_param_cb(last_ocv_uv, &bms_param_ops, &last_ocv_uv, 0644);
+module_param_cb(last_soc, &bms_param_ops, &last_soc, 0644);
+
+static int interpolate_fcc(struct pm8921_bms_chip *chip, int batt_temp);
+static void readjust_fcc_table(void)
+{
+ struct single_row_lut *temp, *old;
+ int i, fcc, ratio;
+
+ if (!the_chip->fcc_temp_lut) {
+ pr_err("The static fcc lut table is NULL\n");
+ return;
+ }
+
+ temp = kzalloc(sizeof(struct single_row_lut), GFP_KERNEL);
+ if (!temp) {
+ pr_err("Cannot allocate memory for adjusted fcc table\n");
+ return;
+ }
+
+ fcc = interpolate_fcc(the_chip, last_real_fcc_batt_temp);
+
+ temp->cols = the_chip->fcc_temp_lut->cols;
+ for (i = 0; i < the_chip->fcc_temp_lut->cols; i++) {
+ temp->x[i] = the_chip->fcc_temp_lut->x[i];
+ ratio = div_u64(the_chip->fcc_temp_lut->y[i] * 1000, fcc);
+ temp->y[i] = (ratio * last_real_fcc);
+ temp->y[i] /= 1000;
+ pr_debug("temp=%d, staticfcc=%d, adjfcc=%d, ratio=%d\n",
+ temp->x[i], the_chip->fcc_temp_lut->y[i],
+ temp->y[i], ratio);
+ }
+
+ old = the_chip->adjusted_fcc_temp_lut;
+ the_chip->adjusted_fcc_temp_lut = temp;
+ kfree(old);
+}
+
+static int bms_last_real_fcc_set(const char *val,
+ const struct kernel_param *kp)
+{
+ int rc = 0;
+
+ if (last_real_fcc == -EINVAL)
+ rc = param_set_int(val, kp);
+ if (rc) {
+ pr_err("Failed to set last_real_fcc rc=%d\n", rc);
+ return rc;
+ }
+ if (last_real_fcc_batt_temp != -EINVAL)
+ readjust_fcc_table();
+ return rc;
+}
+static struct kernel_param_ops bms_last_real_fcc_param_ops = {
+ .set = bms_last_real_fcc_set,
+ .get = param_get_int,
+};
+module_param_cb(last_real_fcc, &bms_last_real_fcc_param_ops,
+ &last_real_fcc, 0644);
+
+static int bms_last_real_fcc_batt_temp_set(const char *val,
+ const struct kernel_param *kp)
+{
+ int rc = 0;
+
+ if (last_real_fcc_batt_temp == -EINVAL)
+ rc = param_set_int(val, kp);
+ if (rc) {
+ pr_err("Failed to set last_real_fcc_batt_temp rc=%d\n", rc);
+ return rc;
+ }
+ if (last_real_fcc != -EINVAL)
+ readjust_fcc_table();
+ return rc;
+}
+
+static struct kernel_param_ops bms_last_real_fcc_batt_temp_param_ops = {
+ .set = bms_last_real_fcc_batt_temp_set,
+ .get = param_get_int,
+};
+module_param_cb(last_real_fcc_batt_temp, &bms_last_real_fcc_batt_temp_param_ops,
+ &last_real_fcc_batt_temp, 0644);
static int pm_bms_get_rt_status(struct pm8921_bms_chip *chip, int irq_id)
{
@@ -247,25 +339,34 @@
return 0;
}
-#define V_PER_BIT_MUL_FACTOR 293
-#define INTRINSIC_OFFSET 0x6000
-static int vbatt_to_microvolt(unsigned int a)
+#define V_PER_BIT_MUL_FACTOR 97656
+#define V_PER_BIT_DIV_FACTOR 1000
+#define XOADC_INTRINSIC_OFFSET 0x6000
+static int xoadc_reading_to_microvolt(unsigned int a)
{
- if (a <= INTRINSIC_OFFSET)
+ if (a <= XOADC_INTRINSIC_OFFSET)
return 0;
- return (a - INTRINSIC_OFFSET) * V_PER_BIT_MUL_FACTOR;
+ return (a - XOADC_INTRINSIC_OFFSET)
+ * V_PER_BIT_MUL_FACTOR / V_PER_BIT_DIV_FACTOR;
}
#define XOADC_CALIB_UV 625000
-static int adjust_xo_reading(struct pm8921_bms_chip *chip, unsigned int uv)
+#define VBATT_MUL_FACTOR 3
+static int adjust_xo_vbatt_reading(struct pm8921_bms_chip *chip,
+ unsigned int uv)
{
- u64 numerator = ((u64)uv - chip->xoadc_v0625) * XOADC_CALIB_UV;
- u64 denominator = chip->xoadc_v125 - chip->xoadc_v0625;
+ u64 numerator, denominator;
+ if (uv == 0)
+ return 0;
+
+ numerator = ((u64)uv - chip->xoadc_v0625) * XOADC_CALIB_UV;
+ denominator = chip->xoadc_v125 - chip->xoadc_v0625;
if (denominator == 0)
- return uv;
- return XOADC_CALIB_UV + div_u64(numerator, denominator);
+ return uv * VBATT_MUL_FACTOR;
+ return (XOADC_CALIB_UV + div_u64(numerator, denominator))
+ * VBATT_MUL_FACTOR;
}
#define CC_RESOLUTION_N_V1 1085069
@@ -288,11 +389,61 @@
* resolution (the value of a single bit) was changed after revision 2.0
* for more accurate readings
*/
- return (chip->revision < PM8XXX_REVISION_8901_2p0) ?
+ return (chip->revision < PM8XXX_REVISION_8921_2p0) ?
cc_to_microvolt_v1((s64)cc) :
cc_to_microvolt_v2((s64)cc);
}
+#define CCADC_READING_RESOLUTION_N_V1 1085069
+#define CCADC_READING_RESOLUTION_D_V1 100000
+#define CCADC_READING_RESOLUTION_N_V2 542535
+#define CCADC_READING_RESOLUTION_D_V2 100000
+static s64 ccadc_reading_to_microvolt_v1(s64 cc)
+{
+ return div_s64(cc * CCADC_READING_RESOLUTION_N_V1,
+ CCADC_READING_RESOLUTION_D_V1);
+}
+
+static s64 ccadc_reading_to_microvolt_v2(s64 cc)
+{
+ return div_s64(cc * CCADC_READING_RESOLUTION_N_V2,
+ CCADC_READING_RESOLUTION_D_V2);
+}
+
+static s64 ccadc_reading_to_microvolt(struct pm8921_bms_chip *chip, s64 cc)
+{
+ /*
+ * resolution (the value of a single bit) was changed after revision 2.0
+ * for more accurate readings
+ */
+ return (chip->revision < PM8XXX_REVISION_8921_2p0) ?
+ ccadc_reading_to_microvolt_v1((s64)cc) :
+ ccadc_reading_to_microvolt_v2((s64)cc);
+}
+
+static s64 microvolt_to_ccadc_reading_v1(s64 uv)
+{
+ return div_s64(uv * CCADC_READING_RESOLUTION_D_V1,
+ CCADC_READING_RESOLUTION_N_V1);
+}
+
+static s64 microvolt_to_ccadc_reading_v2(s64 uv)
+{
+ return div_s64(uv * CCADC_READING_RESOLUTION_D_V2,
+ CCADC_READING_RESOLUTION_N_V2);
+}
+
+static s64 microvolt_to_ccadc_reading(struct pm8921_bms_chip *chip, s64 cc)
+{
+ /*
+ * resolution (the value of a single bit) was changed after revision 2.0
+ * for more accurate readings
+ */
+ return (chip->revision < PM8XXX_REVISION_8921_2p0) ?
+ microvolt_to_ccadc_reading_v1((s64)cc) :
+ microvolt_to_ccadc_reading_v2((s64)cc);
+}
+
#define CC_READING_TICKS 55
#define SLEEP_CLK_HZ 32768
#define SECONDS_PER_HOUR 3600
@@ -302,6 +453,19 @@
SLEEP_CLK_HZ * SECONDS_PER_HOUR);
}
+#define GAIN_REFERENCE_UV 25000
+/*
+ * gain compensation for ccadc readings - common for vsense based and
+ * couloumb counter based readings
+ */
+static s64 cc_adjust_for_gain(struct pm8921_bms_chip *chip, s64 cc)
+{
+ if (chip->ccadc_gain_uv == 0)
+ return cc;
+
+ return div_s64(cc * GAIN_REFERENCE_UV, chip->ccadc_gain_uv);
+}
+
/* returns the signed value read from the hardware */
static int read_cc(struct pm8921_bms_chip *chip, int *result)
{
@@ -333,8 +497,12 @@
pr_err("fail to read LAST_GOOD_OCV_VALUE rc = %d\n", rc);
return rc;
}
- *result = vbatt_to_microvolt(reading);
- pr_debug("raw = %04x ocv_microV = %u\n", reading, *result);
+ *result = xoadc_reading_to_microvolt(reading);
+ pr_debug("raw = %04x ocv_uV = %u\n", reading, *result);
+ *result = adjust_xo_vbatt_reading(chip, *result);
+ pr_debug("after adj ocv_uV = %u\n", *result);
+ if (*result != 0)
+ last_ocv_uv = *result;
return 0;
}
@@ -348,8 +516,10 @@
pr_err("fail to read VBATT_FOR_RBATT rc = %d\n", rc);
return rc;
}
- *result = vbatt_to_microvolt(reading);
+ *result = xoadc_reading_to_microvolt(reading);
pr_debug("raw = %04x vbatt_for_r_microV = %u\n", reading, *result);
+ *result = adjust_xo_vbatt_reading(chip, *result);
+ pr_debug("after adj vbatt_for_r_uV = %u\n", *result);
return 0;
}
@@ -363,8 +533,10 @@
pr_err("fail to read VSENSE_FOR_RBATT rc = %d\n", rc);
return rc;
}
- *result = cc_to_microvolt(chip, reading);
- pr_debug("raw = %04x vsense_for_r_microV = %u\n", reading, *result);
+ *result = ccadc_reading_to_microvolt(chip, reading);
+ pr_debug("raw = %04x vsense_for_r_uV = %u\n", reading, *result);
+ *result = cc_adjust_for_gain(chip, *result);
+ pr_debug("after adj vsense_for_r_uV = %u\n", *result);
return 0;
}
@@ -378,8 +550,10 @@
pr_err("fail to read OCV_FOR_RBATT rc = %d\n", rc);
return rc;
}
- *result = vbatt_to_microvolt(reading);
- pr_debug("read = %04x ocv_for_r_microV = %u\n", reading, *result);
+ *result = xoadc_reading_to_microvolt(reading);
+ pr_debug("raw = %04x ocv_for_r_uV = %u\n", reading, *result);
+ *result = adjust_xo_vbatt_reading(chip, *result);
+ pr_debug("after adj ocv_for_r_uV = %u\n", *result);
return 0;
}
@@ -393,8 +567,10 @@
pr_err("fail to read VSENSE_AVG rc = %d\n", rc);
return rc;
}
- *result = cc_to_microvolt(chip, reading);
- pr_debug("read = %04x vsense = %d\n", reading, *result);
+ *result = ccadc_reading_to_microvolt(chip, reading);
+ pr_debug("raw = %04x vsense = %d\n", reading, *result);
+ *result = cc_adjust_for_gain(the_chip, (s64)*result);
+ pr_debug("after adj vsense = %d\n", *result);
return 0;
}
@@ -444,6 +620,11 @@
return interpolate_single_lut(chip->fcc_temp_lut, batt_temp);
}
+static int interpolate_fcc_adjusted(struct pm8921_bms_chip *chip, int batt_temp)
+{
+ return interpolate_single_lut(chip->adjusted_fcc_temp_lut, batt_temp);
+}
+
static int interpolate_scalingfactor_fcc(struct pm8921_bms_chip *chip,
int cycles)
{
@@ -642,14 +823,12 @@
pr_err("fail to read ocv_for_rbatt rc = %d\n", rc);
ocv = 0;
}
- ocv = adjust_xo_reading(chip, ocv);
rc = read_vbatt_for_rbatt(chip, &vbatt);
if (rc) {
pr_err("fail to read vbatt_for_rbatt rc = %d\n", rc);
ocv = 0;
}
- vbatt = adjust_xo_reading(chip, vbatt);
rc = read_vsense_for_rbatt(chip, &vsense);
if (rc) {
@@ -665,6 +844,7 @@
return -EINVAL;
}
r_batt = ((ocv - vbatt) * chip->r_sense) / vsense;
+ last_rbatt = r_batt;
pr_debug("r_batt = %umilliOhms", r_batt);
return r_batt;
}
@@ -674,16 +854,18 @@
{
int initfcc, result, scalefactor = 0;
- initfcc = interpolate_fcc(chip, batt_temp);
- pr_debug("intfcc = %umAh batt_temp = %d\n", initfcc, batt_temp);
+ if (chip->adjusted_fcc_temp_lut == NULL) {
+ initfcc = interpolate_fcc(chip, batt_temp);
- scalefactor = interpolate_scalingfactor_fcc(chip, chargecycles);
- pr_debug("scalefactor = %d batt_temp = %d\n", scalefactor, batt_temp);
+ scalefactor = interpolate_scalingfactor_fcc(chip, chargecycles);
- /* Multiply the initial FCC value by the scale factor. */
- result = (initfcc * scalefactor) / 100;
- pr_debug("fcc mAh = %d\n", result);
- return result;
+ /* Multiply the initial FCC value by the scale factor. */
+ result = (initfcc * scalefactor) / 100;
+ pr_debug("fcc mAh = %d\n", result);
+ return result;
+ } else {
+ return interpolate_fcc_adjusted(chip, batt_temp);
+ }
}
static int get_battery_uvolts(struct pm8921_bms_chip *chip, int *uvolts)
@@ -711,20 +893,18 @@
rc = get_battery_uvolts(chip, &vbatt);
if (rc) {
pr_err("failed to read vbatt from adc rc = %d\n", rc);
- last_ocv_uv = DEFAULT_OCV_MICROVOLTS;
return rc;
}
rc = pm8921_bms_get_battery_current(&ibatt);
if (rc) {
pr_err("failed to read batt current rc = %d\n", rc);
- last_ocv_uv = DEFAULT_OCV_MICROVOLTS;
return rc;
}
rbatt = calculate_rbatt(the_chip);
if (rbatt < 0)
- rbatt = DEFAULT_RBATT_MOHMS;
+ rbatt = (last_rbatt < 0) ? DEFAULT_RBATT_MOHMS : last_rbatt;
*ocv = vbatt + ibatt * rbatt;
return 0;
}
@@ -755,6 +935,7 @@
rc = read_cc(the_chip, coulumb_counter);
cc_voltage_uv = (int64_t)*coulumb_counter;
cc_voltage_uv = cc_to_microvolt(chip, cc_voltage_uv);
+ cc_voltage_uv = cc_adjust_for_gain(chip, cc_voltage_uv);
pr_debug("cc_voltage_uv = %lld microvolts\n", cc_voltage_uv);
cc_uvh = ccmicrovolt_to_uvh(cc_voltage_uv);
pr_debug("cc_uvh = %lld micro_volt_hour\n", cc_uvh);
@@ -771,8 +952,6 @@
if (rbatt < 0) {
rbatt = (last_rbatt < 0) ? DEFAULT_RBATT_MOHMS : last_rbatt;
pr_debug("rbatt unavailable assuming %d\n", rbatt);
- } else {
- last_rbatt = rbatt;
}
/* calculate unusable charge */
@@ -800,9 +979,6 @@
if (ocv == 0) {
ocv = last_ocv_uv;
pr_debug("ocv not available using last_ocv_uv=%d\n", ocv);
- } else {
- /* update the usespace param since a good ocv is available */
- last_ocv_uv = ocv;
}
pc = calculate_pc(chip, ocv, batt_temp, chargecycles);
@@ -941,7 +1117,8 @@
#define HKADC_V_PER_BIT_DIV_FACTOR 10
static int calib_hkadc_convert_microvolt(unsigned int phy)
{
- return phy * HKADC_V_PER_BIT_MUL_FACTOR / HKADC_V_PER_BIT_DIV_FACTOR;
+ return (phy - 0x6000) *
+ HKADC_V_PER_BIT_MUL_FACTOR / HKADC_V_PER_BIT_DIV_FACTOR;
}
static void calib_hkadc(struct pm8921_bms_chip *chip)
@@ -954,10 +1131,10 @@
pr_err("ADC failed for 1.25volts rc = %d\n", rc);
return;
}
- voltage = calib_hkadc_convert_microvolt(result.physical);
+ voltage = calib_hkadc_convert_microvolt(result.adc_code);
- pr_debug("result 1.25v = 0x%llx, voltage = %dmV adc_meas = %lld\n",
- result.physical, voltage, result.measurement);
+ pr_debug("result 1.25v = 0x%x, voltage = %duV adc_meas = %lld\n",
+ result.adc_code, voltage, result.measurement);
/* check for valid range */
if (voltage > XOADC_MAX_1P25V)
@@ -971,9 +1148,9 @@
pr_err("ADC failed for 1.25volts rc = %d\n", rc);
return;
}
- voltage = calib_hkadc_convert_microvolt(result.physical);
- pr_debug("result 0.625V = 0x%llx, voltage = %dmV adc_mead = %lld\n",
- result.physical, voltage, result.measurement);
+ voltage = calib_hkadc_convert_microvolt(result.adc_code);
+ pr_debug("result 0.625V = 0x%x, voltage = %duV adc_mead = %lld\n",
+ result.adc_code, voltage, result.measurement);
/* check for valid range */
if (voltage > XOADC_MAX_0P625V)
voltage = XOADC_MAX_0P625V;
@@ -991,6 +1168,391 @@
calib_hkadc(chip);
}
+#define START_CONV_BIT BIT(7)
+#define EOC_CONV_BIT BIT(6)
+#define SEL_CCADC_BIT BIT(1)
+#define EN_ARB_BIT BIT(0)
+
+#define CCADC_CALIB_DIG_PARAM 0xE3
+#define CCADC_CALIB_RSV_GND 0x40
+#define CCADC_CALIB_RSV_25MV 0x80
+#define CCADC_CALIB_ANA_PARAM 0x1B
+#define SAMPLE_COUNT 16
+#define ADC_WAIT_COUNT 10
+
+#define CCADC_MAX_25MV 30000
+#define CCADC_MIN_25MV 20000
+#define CCADC_MAX_0UV -4000
+#define CCADC_MIN_0UV -7000
+
+#define CCADC_INTRINSIC_OFFSET 0xC000
+
+#define REG_SBI_CONFIG 0x04F
+#define PAGE3_ENABLE_MASK 0x6
+
+static int calib_ccadc_enable_trim_access(struct pm8921_bms_chip *chip,
+ u8 *sbi_config)
+{
+ u8 reg;
+ int rc;
+
+ rc = pm8xxx_readb(chip->dev->parent, REG_SBI_CONFIG, sbi_config);
+ if (rc) {
+ pr_err("error = %d reading sbi config reg\n", rc);
+ return rc;
+ }
+
+ reg = *sbi_config | PAGE3_ENABLE_MASK;
+ return pm8xxx_writeb(chip->dev->parent, REG_SBI_CONFIG, reg);
+}
+
+static int calib_ccadc_restore_trim_access(struct pm8921_bms_chip *chip,
+ u8 sbi_config)
+{
+ return pm8xxx_writeb(chip->dev->parent, REG_SBI_CONFIG, sbi_config);
+}
+
+static int calib_ccadc_enable_arbiter(struct pm8921_bms_chip *chip)
+{
+ int rc;
+
+ /* enable Arbiter, must be sent twice */
+ rc = pm_bms_masked_write(chip, ADC_ARB_SECP_CNTRL,
+ SEL_CCADC_BIT | EN_ARB_BIT, SEL_CCADC_BIT | EN_ARB_BIT);
+ if (rc < 0) {
+ pr_err("error = %d enabling arbiter for offset\n", rc);
+ return rc;
+ }
+ rc = pm_bms_masked_write(chip, ADC_ARB_SECP_CNTRL,
+ SEL_CCADC_BIT | EN_ARB_BIT, SEL_CCADC_BIT | EN_ARB_BIT);
+ if (rc < 0) {
+ pr_err("error = %d writing ADC_ARB_SECP_CNTRL\n", rc);
+ return rc;
+ }
+ return 0;
+}
+
+static int calib_start_conv(struct pm8921_bms_chip *chip,
+ u16 *result)
+{
+ int rc, i;
+ u8 data_msb, data_lsb, reg;
+
+ /* Start conversion */
+ rc = pm_bms_masked_write(chip, ADC_ARB_SECP_CNTRL,
+ START_CONV_BIT, START_CONV_BIT);
+ if (rc < 0) {
+ pr_err("error = %d starting offset meas\n", rc);
+ return rc;
+ }
+
+ /* Wait for End of conversion */
+ for (i = 0; i < ADC_WAIT_COUNT; i++) {
+ rc = pm8xxx_readb(chip->dev->parent,
+ ADC_ARB_SECP_CNTRL, ®);
+ if (rc < 0) {
+ pr_err("error = %d read eoc for offset\n", rc);
+ return rc;
+ }
+ if ((reg & (START_CONV_BIT | EOC_CONV_BIT)) != EOC_CONV_BIT)
+ msleep(60);
+ else
+ break;
+ }
+ if (i == ADC_WAIT_COUNT) {
+ pr_err("waited too long for offset eoc\n");
+ return rc;
+ }
+
+ rc = pm8xxx_readb(chip->dev->parent, ADC_ARB_SECP_DATA0, &data_lsb);
+ if (rc < 0) {
+ pr_err("error = %d reading offset lsb\n", rc);
+ return rc;
+ }
+
+ rc = pm8xxx_readb(chip->dev->parent, ADC_ARB_SECP_DATA1, &data_msb);
+ if (rc < 0) {
+ pr_err("error = %d reading offset msb\n", rc);
+ return rc;
+ }
+
+ *result = (data_msb << 8) | data_lsb;
+ return 0;
+}
+
+static int calib_ccadc_read_trim(struct pm8921_bms_chip *chip,
+ int addr, u8 *data_msb, u8 *data_lsb)
+{
+ int rc;
+ u8 sbi_config;
+
+ calib_ccadc_enable_trim_access(chip, &sbi_config);
+ rc = pm8xxx_readb(chip->dev->parent, addr, data_msb);
+ if (rc < 0) {
+ pr_err("error = %d read msb\n", rc);
+ return rc;
+ }
+ rc = pm8xxx_readb(chip->dev->parent, addr + 1, data_lsb);
+ if (rc < 0) {
+ pr_err("error = %d read lsb\n", rc);
+ return rc;
+ }
+ calib_ccadc_restore_trim_access(chip, sbi_config);
+ return 0;
+}
+
+static int calib_ccadc_read_gain_uv(struct pm8921_bms_chip *chip)
+{
+ s8 data_msb;
+ u8 data_lsb;
+ int rc, gain, offset;
+
+ rc = calib_ccadc_read_trim(chip, CCADC_FULLSCALE_TRIM1,
+ &data_msb, &data_lsb);
+ gain = (data_msb << 8) | data_lsb;
+
+ rc = calib_ccadc_read_trim(chip, CCADC_OFFSET_TRIM1,
+ &data_msb, &data_lsb);
+ offset = (data_msb << 8) | data_lsb;
+
+ pr_debug("raw gain trim = 0x%x offset trim =0x%x\n", gain, offset);
+ gain = ccadc_reading_to_microvolt(chip, (s64)gain - offset);
+ return gain;
+}
+
+#define CCADC_PROGRAM_TRIM_COUNT 2
+#define ADC_ARB_BMS_CNTRL_CCADC_SHIFT 4
+#define ADC_ARB_BMS_CNTRL_CONV_MASK 0x03
+#define BMS_CONV_IN_PROGRESS 0x2
+
+static int calib_ccadc_program_trim(struct pm8921_bms_chip *chip,
+ int addr, u8 data_msb, u8 data_lsb,
+ int wait)
+{
+ int i, rc, loop;
+ u8 cntrl, sbi_config;
+ bool in_progress = 0;
+
+ loop = wait ? CCADC_PROGRAM_TRIM_COUNT : 0;
+
+ calib_ccadc_enable_trim_access(chip, &sbi_config);
+
+ for (i = 0; i < loop; i++) {
+ rc = pm8xxx_readb(chip->dev->parent, ADC_ARB_BMS_CNTRL, &cntrl);
+ if (rc < 0) {
+ pr_err("error = %d reading ADC_ARB_BMS_CNTRL\n", rc);
+ return rc;
+ }
+
+ /* break if a ccadc conversion is not happening */
+ in_progress = (((cntrl >> ADC_ARB_BMS_CNTRL_CCADC_SHIFT)
+ & ADC_ARB_BMS_CNTRL_CONV_MASK) == BMS_CONV_IN_PROGRESS);
+
+ if (!in_progress)
+ break;
+ }
+
+ if (in_progress) {
+ pr_debug("conv in progress cannot write trim,returing EBUSY\n");
+ return -EBUSY;
+ }
+
+ rc = pm8xxx_writeb(chip->dev->parent, addr, data_msb);
+ if (rc < 0) {
+ pr_err("error = %d write msb = 0x%x\n", rc, data_msb);
+ return rc;
+ }
+ rc = pm8xxx_writeb(chip->dev->parent, addr + 1, data_lsb);
+ if (rc < 0) {
+ pr_err("error = %d write lsb = 0x%x\n", rc, data_lsb);
+ return rc;
+ }
+ calib_ccadc_restore_trim_access(chip, sbi_config);
+ return 0;
+}
+
+static void calib_ccadc(struct pm8921_bms_chip *chip)
+{
+ u8 data_msb, data_lsb, sec_cntrl;
+ int result_offset, voltage_offset, result_gain;
+ u16 result;
+ int i, rc;
+
+ rc = pm8xxx_readb(chip->dev->parent, ADC_ARB_SECP_CNTRL, &sec_cntrl);
+ if (rc < 0) {
+ pr_err("error = %d reading ADC_ARB_SECP_CNTRL\n", rc);
+ return;
+ }
+
+ rc = calib_ccadc_enable_arbiter(chip);
+ if (rc < 0) {
+ pr_err("error = %d enabling arbiter for offset\n", rc);
+ goto bail;
+ }
+
+ /*
+ * Set decimation ratio to 4k, lower ratio may be used in order to speed
+ * up, pending verification through bench
+ */
+ rc = pm8xxx_writeb(chip->dev->parent, ADC_ARB_SECP_DIG_PARAM,
+ CCADC_CALIB_DIG_PARAM);
+ if (rc < 0) {
+ pr_err("error = %d writing ADC_ARB_SECP_DIG_PARAM\n", rc);
+ goto bail;
+ }
+
+ result_offset = 0;
+ for (i = 0; i < SAMPLE_COUNT; i++) {
+ /* Short analog inputs to CCADC internally to ground */
+ rc = pm8xxx_writeb(chip->dev->parent, ADC_ARB_SECP_RSV,
+ CCADC_CALIB_RSV_GND);
+ if (rc < 0) {
+ pr_err("error = %d selecting gnd voltage\n", rc);
+ goto bail;
+ }
+
+ /* Enable CCADC */
+ rc = pm8xxx_writeb(chip->dev->parent, ADC_ARB_SECP_ANA_PARAM,
+ CCADC_CALIB_ANA_PARAM);
+ if (rc < 0) {
+ pr_err("error = %d enabling ccadc\n", rc);
+ goto bail;
+ }
+
+ rc = calib_start_conv(chip, &result);
+ if (rc < 0) {
+ pr_err("error = %d for zero volt measurement\n", rc);
+ goto bail;
+ }
+
+ result_offset += result;
+ }
+
+ result_offset = result_offset / SAMPLE_COUNT;
+
+ voltage_offset = ccadc_reading_to_microvolt(chip,
+ ((s64)result_offset - CCADC_INTRINSIC_OFFSET));
+
+ pr_debug("offset result_offset = 0x%x, voltage = %d microVolts\n",
+ result_offset, voltage_offset);
+
+ /* Sanity Check */
+ if (voltage_offset > CCADC_MAX_0UV) {
+ pr_err("offset voltage = %d is huge limiting to %d\n",
+ voltage_offset, CCADC_MAX_0UV);
+ result_offset = CCADC_INTRINSIC_OFFSET
+ + microvolt_to_ccadc_reading(chip, (s64)CCADC_MAX_0UV);
+ } else if (voltage_offset < CCADC_MIN_0UV) {
+ pr_err("offset voltage = %d is too low limiting to %d\n",
+ voltage_offset, CCADC_MIN_0UV);
+ result_offset = CCADC_INTRINSIC_OFFSET
+ + microvolt_to_ccadc_reading(chip, (s64)CCADC_MIN_0UV);
+ }
+
+ chip->ccadc_result_offset = result_offset;
+ data_msb = chip->ccadc_result_offset >> 8;
+ data_lsb = chip->ccadc_result_offset;
+
+ rc = calib_ccadc_program_trim(chip, CCADC_OFFSET_TRIM1,
+ data_msb, data_lsb, 1);
+ if (rc) {
+ pr_debug("error = %d programming offset trim 0x%02x 0x%02x\n",
+ rc, data_msb, data_lsb);
+ /* enable the interrupt and write it when it fires */
+ pm8921_bms_enable_irq(chip, PM8921_BMS_CCADC_EOC);
+ }
+
+ rc = calib_ccadc_enable_arbiter(chip);
+ if (rc < 0) {
+ pr_err("error = %d enabling arbiter for gain\n", rc);
+ goto bail;
+ }
+
+ /*
+ * Set decimation ratio to 4k, lower ratio may be used in order to speed
+ * up, pending verification through bench
+ */
+ rc = pm8xxx_writeb(chip->dev->parent, ADC_ARB_SECP_DIG_PARAM,
+ CCADC_CALIB_DIG_PARAM);
+ if (rc < 0) {
+ pr_err("error = %d enabling decimation ration for gain\n", rc);
+ goto bail;
+ }
+
+ result_gain = 0;
+ for (i = 0; i < SAMPLE_COUNT; i++) {
+ rc = pm8xxx_writeb(chip->dev->parent,
+ ADC_ARB_SECP_RSV, CCADC_CALIB_RSV_25MV);
+ if (rc < 0) {
+ pr_err("error = %d selecting 25mV for gain\n", rc);
+ goto bail;
+ }
+
+ /* Enable CCADC */
+ rc = pm8xxx_writeb(chip->dev->parent, ADC_ARB_SECP_ANA_PARAM,
+ CCADC_CALIB_ANA_PARAM);
+ if (rc < 0) {
+ pr_err("error = %d enabling ccadc\n", rc);
+ goto bail;
+ }
+
+ rc = calib_start_conv(chip, &result);
+ if (rc < 0) {
+ pr_err("error = %d for adc reading 25mV\n", rc);
+ goto bail;
+ }
+
+ result_gain += result;
+ }
+ result_gain = result_gain / SAMPLE_COUNT;
+
+ /*
+ * result_offset includes INTRINSIC OFFSET
+ * chip->ccadc_gain_uv will be the actual voltage
+ * measured for 25000UV
+ */
+ chip->ccadc_gain_uv = ccadc_reading_to_microvolt(chip,
+ ((s64)result_gain - result_offset));
+
+ pr_debug("gain result_gain = 0x%x, voltage = %d microVolts\n",
+ result_gain,
+ chip->ccadc_gain_uv);
+ /* Sanity Check */
+ if (chip->ccadc_gain_uv > CCADC_MAX_25MV) {
+ pr_err("gain voltage = %d is huge limiting to %d\n",
+ chip->ccadc_gain_uv, CCADC_MAX_25MV);
+ chip->ccadc_gain_uv = CCADC_MAX_25MV;
+ result_gain = result_offset +
+ microvolt_to_ccadc_reading(chip, CCADC_MAX_25MV);
+ } else if (chip->ccadc_gain_uv < CCADC_MIN_25MV) {
+ pr_err("gain voltage = %d is too low limiting to %d\n",
+ chip->ccadc_gain_uv, CCADC_MIN_25MV);
+ chip->ccadc_gain_uv = CCADC_MIN_25MV;
+ result_gain = result_offset +
+ microvolt_to_ccadc_reading(chip, CCADC_MIN_25MV);
+ }
+
+ data_msb = result_gain >> 8;
+ data_lsb = result_gain;
+ rc = calib_ccadc_program_trim(chip, CCADC_FULLSCALE_TRIM1,
+ data_msb, data_lsb, 0);
+ if (rc)
+ pr_debug("error = %d programming gain trim\n", rc);
+bail:
+ pm8xxx_writeb(chip->dev->parent, ADC_ARB_SECP_CNTRL, sec_cntrl);
+}
+
+static void calibrate_ccadc_work(struct work_struct *work)
+{
+ struct pm8921_bms_chip *chip = container_of(work,
+ struct pm8921_bms_chip, calib_ccadc_work.work);
+
+ calib_ccadc(chip);
+ schedule_delayed_work(&chip->calib_ccadc_work,
+ round_jiffies_relative(msecs_to_jiffies
+ (chip->calib_delay_ms)));
+}
+
int pm8921_bms_get_vsense_avg(int *result)
{
int rc = -EINVAL;
@@ -1012,6 +1574,7 @@
int pm8921_bms_get_battery_current(int *result)
{
unsigned long flags;
+ int vsense;
if (!the_chip) {
pr_err("called before initialization\n");
@@ -1024,12 +1587,13 @@
spin_lock_irqsave(&the_chip->bms_output_lock, flags);
pm_bms_lock_output_data(the_chip);
- read_vsense_avg(the_chip, result);
+ read_vsense_avg(the_chip, &vsense);
pm_bms_unlock_output_data(the_chip);
spin_unlock_irqrestore(&the_chip->bms_output_lock, flags);
- pr_debug("vsense=%d\n", *result);
+ pr_debug("vsense=%d\n", vsense);
/* cast for signed division */
- *result = *result / (int)the_chip->r_sense;
+ *result = vsense / (int)the_chip->r_sense;
+
return 0;
}
EXPORT_SYMBOL(pm8921_bms_get_battery_current);
@@ -1107,6 +1671,8 @@
batt_temp = (int)result.physical;
last_real_fcc = calculate_real_fcc(the_chip,
batt_temp, last_chargecycles);
+ last_real_fcc_batt_temp = batt_temp;
+ readjust_fcc_table();
}
charge_cycle_calculation:
@@ -1174,6 +1740,23 @@
return IRQ_HANDLED;
}
+static irqreturn_t pm8921_bms_ccadc_eoc_handler(int irq, void *data)
+{
+ u8 data_msb, data_lsb;
+ struct pm8921_bms_chip *chip = data;
+ int rc;
+
+ pr_debug("irq = %d triggered\n", irq);
+ data_msb = chip->ccadc_result_offset >> 8;
+ data_lsb = chip->ccadc_result_offset;
+
+ rc = calib_ccadc_program_trim(chip, CCADC_OFFSET_TRIM1,
+ data_msb, data_lsb, 0);
+ pm8921_bms_disable_irq(chip, PM8921_BMS_CCADC_EOC);
+
+ return IRQ_HANDLED;
+}
+
struct pm_bms_irq_init_data {
unsigned int irq_id;
char *name;
@@ -1204,6 +1787,8 @@
pm8921_bms_good_ocv_handler),
BMS_IRQ(PM8921_BMS_VSENSE_AVG, IRQF_TRIGGER_RISING,
pm8921_bms_vsense_avg_handler),
+ BMS_IRQ(PM8921_BMS_CCADC_EOC, IRQF_TRIGGER_RISING,
+ pm8921_bms_ccadc_eoc_handler),
};
static void free_irqs(struct pm8921_bms_chip *chip)
@@ -1272,13 +1857,19 @@
int ocv, rc;
/*
- * Check if a last_good_ocv is available,
- * if not compute it here at boot time.
+ * Check if a ocv is available in bms hw,
+ * if not compute it here at boot time and save it
+ * in the last_ocv_uv.
*/
+ ocv = 0;
rc = read_last_good_ocv(chip, &ocv);
if (rc || ocv == 0) {
- rc = adc_based_ocv(chip, &last_ocv_uv);
- pr_err("failed to read ocv from adc and bms rc = %d\n", rc);
+ rc = adc_based_ocv(chip, &ocv);
+ if (rc) {
+ pr_err("failed to read adc based ocv rc = %d\n", rc);
+ ocv = DEFAULT_OCV_MICROVOLTS;
+ }
+ last_ocv_uv = ocv;
}
pr_debug("ocv = %d last_ocv_uv = %d\n", ocv, last_ocv_uv);
}
@@ -1336,6 +1927,7 @@
CALC_PC,
CALC_SOC,
CALIB_HKADC,
+ CALIB_CCADC,
};
static int test_batt_temp = 5;
@@ -1411,6 +2003,11 @@
*val = 0;
calib_hkadc(the_chip);
break;
+ case CALIB_CCADC:
+ /* reading this will trigger calibration */
+ *val = 0;
+ calib_ccadc(the_chip);
+ break;
default:
ret = -EINVAL;
}
@@ -1562,6 +2159,8 @@
(void *)CALC_SOC, &calc_fops);
debugfs_create_file("calib_hkadc", 0644, chip->dent,
(void *)CALIB_HKADC, &calc_fops);
+ debugfs_create_file("calib_ccadc", 0644, chip->dent,
+ (void *)CALIB_CCADC, &calc_fops);
for (i = 0; i < ARRAY_SIZE(bms_irq_data); i++) {
if (chip->pmic_bms_irq[bms_irq_data[i].irq_id])
@@ -1575,9 +2174,11 @@
static int __devinit pm8921_bms_probe(struct platform_device *pdev)
{
int rc = 0;
+ int vbatt;
struct pm8921_bms_chip *chip;
const struct pm8921_bms_platform_data *pdata
= pdev->dev.platform_data;
+
if (!pdata) {
pr_err("missing platform data\n");
return -EINVAL;
@@ -1608,32 +2209,44 @@
chip->revision = pm8xxx_get_revision(chip->dev->parent);
INIT_WORK(&chip->calib_hkadc_work, calibrate_hkadc_work);
- rc = pm8921_bms_hw_init(chip);
- if (rc) {
- pr_err("couldn't init hardware rc = %d\n", rc);
- goto free_chip;
- }
-
rc = request_irqs(chip, pdev);
if (rc) {
pr_err("couldn't register interrupts rc = %d\n", rc);
goto free_chip;
}
+ rc = pm8921_bms_hw_init(chip);
+ if (rc) {
+ pr_err("couldn't init hardware rc = %d\n", rc);
+ goto free_irqs;
+ }
+
platform_set_drvdata(pdev, chip);
the_chip = chip;
create_debugfs_entries(chip);
check_initial_ocv(chip);
+ chip->ccadc_gain_uv = calib_ccadc_read_gain_uv(chip);
+ INIT_DELAYED_WORK(&chip->calib_ccadc_work, calibrate_ccadc_work);
+ /* begin calibration only on chips > 2.0 */
+ if (chip->revision >= PM8XXX_REVISION_8921_2p0)
+ calibrate_ccadc_work(&(chip->calib_ccadc_work.work));
+
+ /* initial hkadc calibration */
+ schedule_work(&chip->calib_hkadc_work);
/* enable the vbatt reading interrupts for scheduling hkadc calib */
pm8921_bms_enable_irq(chip, PM8921_BMS_GOOD_OCV);
pm8921_bms_enable_irq(chip, PM8921_BMS_OCV_FOR_R);
- pr_info("OK battery_capacity_at_boot=%d\n",
- pm8921_bms_get_percent_charge());
+ get_battery_uvolts(chip, &vbatt);
+ pr_info("OK battery_capacity_at_boot=%d volt = %d ocv = %d\n",
+ pm8921_bms_get_percent_charge(),
+ vbatt, last_ocv_uv);
return 0;
+free_irqs:
+ free_irqs(chip);
free_chip:
kfree(chip);
return rc;
@@ -1644,6 +2257,7 @@
struct pm8921_bms_chip *chip = platform_get_drvdata(pdev);
free_irqs(chip);
+ kfree(chip->adjusted_fcc_temp_lut);
platform_set_drvdata(pdev, NULL);
the_chip = NULL;
kfree(chip);
diff --git a/drivers/power/pm8921-charger.c b/drivers/power/pm8921-charger.c
index 82582c4..303dd99 100644
--- a/drivers/power/pm8921-charger.c
+++ b/drivers/power/pm8921-charger.c
@@ -2229,7 +2229,7 @@
}
if (chip->ttrkl_time != 0) {
- rc = pm_chg_ttrkl_max_set(chip, chip->safety_time);
+ rc = pm_chg_ttrkl_max_set(chip, chip->ttrkl_time);
if (rc) {
pr_err("Failed to set trkl time to %d minutes rc=%d\n",
chip->safety_time, rc);
diff --git a/drivers/slimbus/slim-msm-ctrl.c b/drivers/slimbus/slim-msm-ctrl.c
index 937bfe7..1e4302b 100644
--- a/drivers/slimbus/slim-msm-ctrl.c
+++ b/drivers/slimbus/slim-msm-ctrl.c
@@ -21,7 +21,6 @@
#include <linux/delay.h>
#include <linux/kthread.h>
#include <linux/clk.h>
-#include <linux/pm_runtime.h>
#include <mach/sps.h>
/* Per spec.max 40 bytes per received message */
@@ -45,7 +44,6 @@
#define MSM_SLIM_PERF_SUMM_THRESHOLD 0x8000
#define MSM_SLIM_NCHANS 32
#define MSM_SLIM_NPORTS 24
-#define MSM_SLIM_AUTOSUSPEND MSEC_PER_SEC
/*
* Need enough descriptors to receive present messages from slaves
@@ -186,12 +184,6 @@
REF_CLK_GEAR = 15,
};
-enum msm_ctrl_state {
- MSM_CTRL_AWAKE,
- MSM_CTRL_SLEEPING,
- MSM_CTRL_ASLEEP,
-};
-
struct msm_slim_sps_bam {
u32 hdl;
void __iomem *base;
@@ -234,11 +226,10 @@
struct mutex tx_lock;
u8 pgdla;
bool use_rx_msgqs;
+ int suspended;
int pipe_b;
struct completion reconf;
bool reconf_busy;
- bool chan_active;
- enum msm_ctrl_state state;
};
struct msm_slim_sat {
@@ -459,11 +450,6 @@
* before exiting ISR
*/
mb();
- if (dev->ctrl.sched.usedslots == 0 &&
- dev->state != MSM_CTRL_SLEEPING) {
- dev->chan_active = false;
- pm_runtime_put(dev->dev);
- }
complete(&dev->reconf);
}
pstat = readl_relaxed(dev->base + PGD_PORT_INT_ST_EEn + (16 * dev->ee));
@@ -663,36 +649,17 @@
u8 *puc;
int timeout;
u8 la = txn->la;
- /*
- * Voting for runtime PM: Slimbus has 2 possible use cases:
- * 1. messaging
- * 2. Data channels
- * Messaging case goes through messaging slots and data channels
- * use their own slots
- * This "get" votes for messaging bandwidth
- */
- if (dev->state != MSM_CTRL_SLEEPING)
- pm_runtime_get_sync(dev->dev);
mutex_lock(&dev->tx_lock);
- if (dev->state == MSM_CTRL_ASLEEP) {
- dev_err(dev->dev, "runtime or system PM suspended state");
- mutex_unlock(&dev->tx_lock);
- pm_runtime_put(dev->dev);
- return -EBUSY;
- }
if (txn->mt == SLIM_MSG_MT_CORE &&
- txn->mc == SLIM_MSG_MC_BEGIN_RECONFIGURATION) {
- if (dev->reconf_busy) {
+ txn->mc == SLIM_MSG_MC_BEGIN_RECONFIGURATION &&
+ dev->reconf_busy) {
wait_for_completion(&dev->reconf);
dev->reconf_busy = false;
- }
- /* This "get" votes for data channels */
- if (dev->ctrl.sched.usedslots != 0 &&
- !dev->chan_active) {
- dev->chan_active = true;
- if (dev->state != MSM_CTRL_SLEEPING)
- pm_runtime_get(dev->dev);
- }
+ }
+ if (dev->suspended) {
+ dev_err(dev->dev, "No transaction in suspended state");
+ mutex_unlock(&dev->tx_lock);
+ return -EBUSY;
}
txn->rl--;
pbuf = msm_get_msg_buf(ctrl, txn->rl);
@@ -701,8 +668,6 @@
if (txn->dt == SLIM_MSG_DEST_ENUMADDR) {
mutex_unlock(&dev->tx_lock);
- if (dev->state != MSM_CTRL_SLEEPING)
- pm_runtime_put(dev->dev);
return -EPROTONOSUPPORT;
}
if (txn->mt == SLIM_MSG_MT_CORE && txn->la == 0xFF &&
@@ -750,15 +715,11 @@
*/
dev->pipes[*puc].connected = false;
mutex_unlock(&dev->tx_lock);
- if (dev->state != MSM_CTRL_SLEEPING)
- pm_runtime_put(dev->dev);
return 0;
}
if (dev->err) {
dev_err(dev->dev, "pipe-port connect err:%d", dev->err);
mutex_unlock(&dev->tx_lock);
- if (dev->state != MSM_CTRL_SLEEPING)
- pm_runtime_put(dev->dev);
return dev->err;
}
*(puc) = *(puc) + dev->pipe_b;
@@ -769,22 +730,10 @@
dev->wr_comp = &done;
msm_send_msg_buf(ctrl, pbuf, txn->rl);
timeout = wait_for_completion_timeout(&done, HZ);
-
- if (dev->state == MSM_CTRL_SLEEPING &&
- txn->mc == SLIM_MSG_MC_RECONFIGURE_NOW &&
- txn->mt == SLIM_MSG_MT_CORE && timeout) {
- timeout = wait_for_completion_timeout(&dev->reconf, HZ);
- if (timeout)
- dev->reconf_busy = false;
- }
- mutex_unlock(&dev->tx_lock);
- if (!txn->rbuf && dev->state != MSM_CTRL_SLEEPING)
- pm_runtime_put(dev->dev);
-
if (!timeout)
dev_err(dev->dev, "TX timed out:MC:0x%x,mt:0x%x", txn->mc,
txn->mt);
-
+ mutex_unlock(&dev->tx_lock);
return timeout ? dev->err : -ETIMEDOUT;
}
@@ -814,7 +763,6 @@
static int msm_clk_pause_wakeup(struct slim_controller *ctrl)
{
struct msm_slim_ctrl *dev = slim_get_ctrldata(ctrl);
- enable_irq(dev->irq);
clk_enable(dev->rclk);
writel_relaxed(1, dev->base + FRM_WAKEUP);
/* Make sure framer wakeup write goes through before exiting function */
@@ -965,7 +913,6 @@
u8 e_addr[6];
for (i = 0; i < 6; i++)
e_addr[i] = buf[7-i];
- pm_runtime_get_sync(dev->dev);
ret = slim_assign_laddr(&dev->ctrl, e_addr, 6, &laddr);
/* Is this Qualcomm ported generic device? */
@@ -974,7 +921,6 @@
e_addr[1] == QC_DEVID_PGD &&
e_addr[2] != QC_CHIPID_SL)
dev->pgdla = laddr;
- pm_runtime_put(dev->dev);
} else if (mc == SLIM_MSG_MC_REPLY_INFORMATION ||
mc == SLIM_MSG_MC_REPLY_VALUE) {
@@ -982,7 +928,6 @@
dev_dbg(dev->dev, "tid:%d, len:%d\n", tid, len - 4);
slim_msg_response(&dev->ctrl, &buf[4], tid,
len - 4);
- pm_runtime_put(dev->dev);
} else if (mc == SLIM_MSG_MC_REPORT_INFORMATION) {
u8 l_addr = buf[2];
u16 ele = (u16)buf[4] << 4;
@@ -1035,19 +980,11 @@
for (i = 0; i < 6; i++)
e_addr[i] = buf[7-i];
- pm_runtime_get_sync(dev->dev);
slim_assign_laddr(&dev->ctrl, e_addr, 6, &laddr);
sat->satcl.laddr = laddr;
- } else if (mt != SLIM_MSG_MT_CORE &&
- mc != SLIM_MSG_MC_REPORT_PRESENT)
- pm_runtime_get_sync(dev->dev);
+ }
switch (mc) {
case SLIM_MSG_MC_REPORT_PRESENT:
- /* Remove runtime_pm vote once satellite acks */
- if (mt != SLIM_MSG_MT_CORE) {
- pm_runtime_put(dev->dev);
- continue;
- }
/* send a Manager capability msg */
if (sat->sent_capability)
continue;
@@ -1148,11 +1085,8 @@
default:
break;
}
- if (!gen_ack) {
- if (mc != SLIM_MSG_MC_REPORT_PRESENT)
- pm_runtime_put(dev->dev);
+ if (!gen_ack)
continue;
- }
wbuf[0] = tid;
if (!ret)
wbuf[1] = MSM_SAT_SUCCSS;
@@ -1165,7 +1099,6 @@
txn.wbuf = wbuf;
txn.mt = SLIM_MSG_MT_SRC_REFERRED_USER;
msm_xfer_msg(&dev->ctrl, &txn);
- pm_runtime_put(dev->dev);
}
}
@@ -1769,10 +1702,6 @@
* function
*/
mb();
- pm_runtime_use_autosuspend(&pdev->dev);
- pm_runtime_set_autosuspend_delay(&pdev->dev, MSM_SLIM_AUTOSUSPEND);
- pm_runtime_set_active(&pdev->dev);
- pm_runtime_enable(&pdev->dev);
dev_dbg(dev->dev, "MSM SB controller is up!\n");
return 0;
@@ -1806,13 +1735,12 @@
struct resource *slew_mem = dev->slew_mem;
struct msm_slim_sat *sat = dev->satd;
slim_remove_device(&sat->satcl);
- pm_runtime_disable(&pdev->dev);
- pm_runtime_set_suspended(&pdev->dev);
kfree(sat->satch);
destroy_workqueue(sat->wq);
kfree(sat);
free_irq(dev->irq, dev);
slim_del_controller(&dev->ctrl);
+ clk_disable(dev->rclk);
clk_put(dev->rclk);
msm_slim_sps_exit(dev);
kthread_stop(dev->rx_msgq_thread);
@@ -1832,91 +1760,79 @@
return 0;
}
-#ifdef CONFIG_PM_RUNTIME
-static int msm_slim_runtime_idle(struct device *device)
+#ifdef CONFIG_PM
+static int msm_slim_suspend(struct device *device)
{
struct platform_device *pdev = to_platform_device(device);
struct msm_slim_ctrl *dev = platform_get_drvdata(pdev);
- dev_dbg(device, "pm_runtime: idle...\n");
- pm_runtime_mark_last_busy(dev->dev);
- pm_request_autosuspend(device);
- return -EAGAIN;
-}
-#endif
-
-/*
- * If PM_RUNTIME is not defined, these 2 functions become helper
- * functions to be called from system suspend/resume. So they are not
- * inside ifdef CONFIG_PM_RUNTIME
- */
-static int msm_slim_runtime_suspend(struct device *device)
-{
- struct platform_device *pdev = to_platform_device(device);
- struct msm_slim_ctrl *dev = platform_get_drvdata(pdev);
- int ret;
- dev_dbg(device, "pm_runtime: suspending...\n");
- dev->state = MSM_CTRL_SLEEPING;
- ret = slim_ctrl_clk_pause(&dev->ctrl, false, SLIM_CLK_UNSPECIFIED);
+ int ret = slim_ctrl_clk_pause(&dev->ctrl, false, SLIM_CLK_UNSPECIFIED);
/* Make sure clock pause goes through */
+ mutex_lock(&dev->tx_lock);
+ if (!ret && dev->reconf_busy) {
+ wait_for_completion(&dev->reconf);
+ dev->reconf_busy = false;
+ }
+ mutex_unlock(&dev->tx_lock);
if (!ret) {
clk_disable(dev->rclk);
disable_irq(dev->irq);
- dev->state = MSM_CTRL_ASLEEP;
- } else
- dev->state = MSM_CTRL_AWAKE;
- return ret;
-}
-
-static int msm_slim_runtime_resume(struct device *device)
-{
- struct platform_device *pdev = to_platform_device(device);
- struct msm_slim_ctrl *dev = platform_get_drvdata(pdev);
- int ret = 0;
- dev_dbg(device, "pm_runtime: resuming...\n");
- mutex_lock(&dev->tx_lock);
- if (dev->state == MSM_CTRL_ASLEEP) {
- mutex_unlock(&dev->tx_lock);
- ret = slim_ctrl_clk_pause(&dev->ctrl, true, 0);
- if (!ret)
- dev->state = MSM_CTRL_AWAKE;
- return ret;
- }
- mutex_unlock(&dev->tx_lock);
- return ret;
-}
-
-#ifdef CONFIG_PM_SLEEP
-static int msm_slim_suspend(struct device *dev)
-{
- int ret = 0;
- if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) {
- dev_dbg(dev, "system suspend");
- ret = msm_slim_runtime_suspend(dev);
- }
- if (ret == -EBUSY) {
+ dev->suspended = 1;
+ } else if (ret == -EBUSY) {
/*
- * If the clock pause failed due to active channels, there is
- * a possibility that some audio stream is active during suspend
- * We dont want to return suspend failure in that case so that
- * display and relevant components can still go to suspend.
- * If there is some other error, then it should be passed-on
- * to system level suspend
- */
+ * If the clock pause failed due to active channels, there is
+ * a possibility that some audio stream is active during suspend
+ * We dont want to return suspend failure in that case so that
+ * display and relevant components can still go to suspend.
+ * If there is some other error, then it should be passed-on
+ * to system level suspend
+ */
ret = 0;
}
return ret;
}
-static int msm_slim_resume(struct device *dev)
+static int msm_slim_resume(struct device *device)
{
- /* If runtime_pm is enabled, this resume shouldn't do anything */
- if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) {
- dev_dbg(dev, "system resume");
- return msm_slim_runtime_resume(dev);
+ struct platform_device *pdev = to_platform_device(device);
+ struct msm_slim_ctrl *dev = platform_get_drvdata(pdev);
+ mutex_lock(&dev->tx_lock);
+ if (dev->suspended) {
+ dev->suspended = 0;
+ mutex_unlock(&dev->tx_lock);
+ enable_irq(dev->irq);
+ return slim_ctrl_clk_pause(&dev->ctrl, true, 0);
}
+ mutex_unlock(&dev->tx_lock);
return 0;
}
-#endif /* CONFIG_PM_SLEEP */
+#else
+#define msm_slim_suspend NULL
+#define msm_slim_resume NULL
+#endif /* CONFIG_PM */
+
+#ifdef CONFIG_PM_RUNTIME
+static int msm_slim_runtime_idle(struct device *dev)
+{
+ dev_dbg(dev, "pm_runtime: idle...\n");
+ return 0;
+}
+
+static int msm_slim_runtime_suspend(struct device *dev)
+{
+ dev_dbg(dev, "pm_runtime: suspending...\n");
+ return 0;
+}
+
+static int msm_slim_runtime_resume(struct device *dev)
+{
+ dev_dbg(dev, "pm_runtime: resuming...\n");
+ return 0;
+}
+#else
+#define msm_slim_runtime_idle NULL
+#define msm_slim_runtime_suspend NULL
+#define msm_slim_runtime_resume NULL
+#endif
static const struct dev_pm_ops msm_slim_dev_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(
diff --git a/drivers/thermal/msm8960_tsens.c b/drivers/thermal/msm8960_tsens.c
index 12b3a42e..742bae5 100644
--- a/drivers/thermal/msm8960_tsens.c
+++ b/drivers/thermal/msm8960_tsens.c
@@ -722,7 +722,7 @@
static int tsens_calib_sensors(void)
{
- int rc;
+ int rc = -ENODEV;
if (tmdev->hw_type == MSM_8660)
rc = tsens_calib_sensors8660();
diff --git a/drivers/tty/serial/msm_serial_hs.c b/drivers/tty/serial/msm_serial_hs.c
index 06d614b..bc1a25b 100644
--- a/drivers/tty/serial/msm_serial_hs.c
+++ b/drivers/tty/serial/msm_serial_hs.c
@@ -262,7 +262,10 @@
gsbi_resource = platform_get_resource_byname(pdev,
IORESOURCE_MEM,
"gsbi_resource");
- size = gsbi_resource->end - gsbi_resource->start + 1;
+ if (unlikely(!gsbi_resource))
+ return;
+
+ size = resource_size(gsbi_resource);
release_mem_region(gsbi_resource->start, size);
iounmap(msm_uport->mapped_gsbi);
msm_uport->mapped_gsbi = NULL;
@@ -280,7 +283,7 @@
IORESOURCE_MEM,
"gsbi_resource");
if (gsbi_resource) {
- size = gsbi_resource->end - gsbi_resource->start + 1;
+ size = resource_size(gsbi_resource);
if (unlikely(!request_mem_region(gsbi_resource->start, size,
"msm_serial_hs")))
return -EBUSY;
diff --git a/drivers/tty/serial/msm_serial_hs_hwreg.h b/drivers/tty/serial/msm_serial_hs_hwreg.h
index 001d555..fa7d518 100644
--- a/drivers/tty/serial/msm_serial_hs_hwreg.h
+++ b/drivers/tty/serial/msm_serial_hs_hwreg.h
@@ -32,6 +32,28 @@
#define ADM1_CRCI_GSBI6_RX_SEL 0x800
#define ADM1_CRCI_GSBI6_TX_SEL 0x400
+enum msm_hsl_regs {
+ UARTDM_MR1,
+ UARTDM_MR2,
+ UARTDM_IMR,
+ UARTDM_SR,
+ UARTDM_CR,
+ UARTDM_CSR,
+ UARTDM_IPR,
+ UARTDM_ISR,
+ UARTDM_RX_TOTAL_SNAP,
+ UARTDM_RFWR,
+ UARTDM_TFWR,
+ UARTDM_RF,
+ UARTDM_TF,
+ UARTDM_MISR,
+ UARTDM_DMRX,
+ UARTDM_NCF_TX,
+ UARTDM_DMEN,
+ UARTDM_BCR,
+ UARTDM_LAST
+};
+
#define UARTDM_MR1_ADDR 0x0
#define UARTDM_MR2_ADDR 0x4
diff --git a/drivers/tty/serial/msm_serial_hs_lite.c b/drivers/tty/serial/msm_serial_hs_lite.c
index ad085f9..9ba7d2f 100644
--- a/drivers/tty/serial/msm_serial_hs_lite.c
+++ b/drivers/tty/serial/msm_serial_hs_lite.c
@@ -22,6 +22,7 @@
#define SUPPORT_SYSRQ
#endif
+#include <linux/atomic.h>
#include <linux/hrtimer.h>
#include <linux/module.h>
#include <linux/io.h>
@@ -40,6 +41,8 @@
#include <linux/pm_runtime.h>
#include <linux/gpio.h>
#include <linux/debugfs.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
#include <mach/board.h>
#include <mach/msm_serial_hs_lite.h>
#include <asm/mach-types.h>
@@ -57,11 +60,63 @@
unsigned int *mapped_gsbi;
int is_uartdm;
unsigned int old_snap_state;
+ unsigned int ver_id;
};
+#define UARTDM_VERSION_11_13 0
+#define UARTDM_VERSION_14 1
+
#define UART_TO_MSM(uart_port) ((struct msm_hsl_port *) uart_port)
#define is_console(port) ((port)->cons && \
(port)->cons->index == (port)->line)
+
+static const unsigned int regmap[][UARTDM_LAST] = {
+ [UARTDM_VERSION_11_13] = {
+ [UARTDM_MR1] = UARTDM_MR1_ADDR,
+ [UARTDM_MR2] = UARTDM_MR2_ADDR,
+ [UARTDM_IMR] = UARTDM_IMR_ADDR,
+ [UARTDM_SR] = UARTDM_SR_ADDR,
+ [UARTDM_CR] = UARTDM_CR_ADDR,
+ [UARTDM_CSR] = UARTDM_CSR_ADDR,
+ [UARTDM_IPR] = UARTDM_IPR_ADDR,
+ [UARTDM_ISR] = UARTDM_ISR_ADDR,
+ [UARTDM_RX_TOTAL_SNAP] = UARTDM_RX_TOTAL_SNAP_ADDR,
+ [UARTDM_TFWR] = UARTDM_TFWR_ADDR,
+ [UARTDM_RFWR] = UARTDM_RFWR_ADDR,
+ [UARTDM_RF] = UARTDM_RF_ADDR,
+ [UARTDM_TF] = UARTDM_TF_ADDR,
+ [UARTDM_MISR] = UARTDM_MISR_ADDR,
+ [UARTDM_DMRX] = UARTDM_DMRX_ADDR,
+ [UARTDM_NCF_TX] = UARTDM_NCF_TX_ADDR,
+ [UARTDM_DMEN] = UARTDM_DMEN_ADDR,
+ },
+ [UARTDM_VERSION_14] = {
+ [UARTDM_MR1] = 0x0,
+ [UARTDM_MR2] = 0x4,
+ [UARTDM_IMR] = 0xb0,
+ [UARTDM_SR] = 0xa4,
+ [UARTDM_CR] = 0xa8,
+ [UARTDM_CSR] = 0xa0,
+ [UARTDM_IPR] = 0x18,
+ [UARTDM_ISR] = 0xb4,
+ [UARTDM_RX_TOTAL_SNAP] = 0xbc,
+ [UARTDM_TFWR] = 0x1c,
+ [UARTDM_RFWR] = 0x20,
+ [UARTDM_RF] = 0x140,
+ [UARTDM_TF] = 0x100,
+ [UARTDM_MISR] = 0xac,
+ [UARTDM_DMRX] = 0x34,
+ [UARTDM_NCF_TX] = 0x40,
+ [UARTDM_DMEN] = 0x3c,
+ },
+};
+
+static struct of_device_id msm_hsl_match_table[] = {
+ { .compatible = "qcom,msm-lsuart-v14",
+ .data = (void *)UARTDM_VERSION_14
+ },
+ {}
+};
static struct dentry *debug_base;
static inline void wait_for_xmitr(struct uart_port *port, int bits);
static inline void msm_hsl_write(struct uart_port *port,
@@ -109,6 +164,7 @@
{
struct msm_hsl_port *msm_hsl_port = data;
struct uart_port *port = &(msm_hsl_port->uart);
+ unsigned int vid;
unsigned long flags;
int ret = 0;
@@ -120,17 +176,18 @@
return -EINVAL;
}
+ vid = msm_hsl_port->ver_id;
if (val) {
spin_lock_irqsave(&port->lock, flags);
- ret = msm_hsl_read(port, UARTDM_MR2_ADDR);
+ ret = msm_hsl_read(port, regmap[vid][UARTDM_MR2]);
ret |= UARTDM_MR2_LOOP_MODE_BMSK;
- msm_hsl_write(port, ret, UARTDM_MR2_ADDR);
+ msm_hsl_write(port, ret, regmap[vid][UARTDM_MR2]);
spin_unlock_irqrestore(&port->lock, flags);
} else {
spin_lock_irqsave(&port->lock, flags);
- ret = msm_hsl_read(port, UARTDM_MR2_ADDR);
+ ret = msm_hsl_read(port, regmap[vid][UARTDM_MR2]);
ret &= ~UARTDM_MR2_LOOP_MODE_BMSK;
- msm_hsl_write(port, ret, UARTDM_MR2_ADDR);
+ msm_hsl_write(port, ret, regmap[vid][UARTDM_MR2]);
spin_unlock_irqrestore(&port->lock, flags);
}
@@ -153,7 +210,7 @@
}
spin_lock_irqsave(&port->lock, flags);
- ret = msm_hsl_read(port, UARTDM_MR2_ADDR);
+ ret = msm_hsl_read(port, regmap[msm_hsl_port->ver_id][UARTDM_MR2]);
spin_unlock_irqrestore(&port->lock, flags);
clk_en(port, 0);
@@ -191,7 +248,8 @@
clk_en(port, 1);
msm_hsl_port->imr &= ~UARTDM_ISR_TXLEV_BMSK;
- msm_hsl_write(port, msm_hsl_port->imr, UARTDM_IMR_ADDR);
+ msm_hsl_write(port, msm_hsl_port->imr,
+ regmap[msm_hsl_port->ver_id][UARTDM_IMR]);
clk_en(port, 0);
}
@@ -203,7 +261,8 @@
clk_en(port, 1);
msm_hsl_port->imr |= UARTDM_ISR_TXLEV_BMSK;
- msm_hsl_write(port, msm_hsl_port->imr, UARTDM_IMR_ADDR);
+ msm_hsl_write(port, msm_hsl_port->imr,
+ regmap[msm_hsl_port->ver_id][UARTDM_IMR]);
clk_en(port, 0);
}
@@ -216,7 +275,8 @@
msm_hsl_port->imr &= ~(UARTDM_ISR_RXLEV_BMSK |
UARTDM_ISR_RXSTALE_BMSK);
- msm_hsl_write(port, msm_hsl_port->imr, UARTDM_IMR_ADDR);
+ msm_hsl_write(port, msm_hsl_port->imr,
+ regmap[msm_hsl_port->ver_id][UARTDM_IMR]);
clk_en(port, 0);
}
@@ -228,7 +288,8 @@
clk_en(port, 1);
msm_hsl_port->imr |= UARTDM_ISR_DELTA_CTS_BMSK;
- msm_hsl_write(port, msm_hsl_port->imr, UARTDM_IMR_ADDR);
+ msm_hsl_write(port, msm_hsl_port->imr,
+ regmap[msm_hsl_port->ver_id][UARTDM_IMR]);
clk_en(port, 0);
}
@@ -236,26 +297,31 @@
static void handle_rx(struct uart_port *port, unsigned int misr)
{
struct tty_struct *tty = port->state->port.tty;
+ unsigned int vid;
unsigned int sr;
int count = 0;
struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
+ vid = msm_hsl_port->ver_id;
/*
* Handle overrun. My understanding of the hardware is that overrun
* is not tied to the RX buffer, so we handle the case out of band.
*/
- if ((msm_hsl_read(port, UARTDM_SR_ADDR) & UARTDM_SR_OVERRUN_BMSK)) {
+ if ((msm_hsl_read(port, regmap[vid][UARTDM_SR]) &
+ UARTDM_SR_OVERRUN_BMSK)) {
port->icount.overrun++;
tty_insert_flip_char(tty, 0, TTY_OVERRUN);
- msm_hsl_write(port, RESET_ERROR_STATUS, UARTDM_CR_ADDR);
+ msm_hsl_write(port, RESET_ERROR_STATUS,
+ regmap[vid][UARTDM_CR]);
}
if (misr & UARTDM_ISR_RXSTALE_BMSK) {
- count = msm_hsl_read(port, UARTDM_RX_TOTAL_SNAP_ADDR) -
+ count = msm_hsl_read(port,
+ regmap[vid][UARTDM_RX_TOTAL_SNAP]) -
msm_hsl_port->old_snap_state;
msm_hsl_port->old_snap_state = 0;
} else {
- count = 4 * (msm_hsl_read(port, UARTDM_RFWR_ADDR));
+ count = 4 * (msm_hsl_read(port, regmap[vid][UARTDM_RFWR]));
msm_hsl_port->old_snap_state += count;
}
@@ -264,13 +330,12 @@
unsigned int c;
char flag = TTY_NORMAL;
- sr = msm_hsl_read(port, UARTDM_SR_ADDR);
- if ((sr &
- UARTDM_SR_RXRDY_BMSK) == 0) {
+ sr = msm_hsl_read(port, regmap[vid][UARTDM_SR]);
+ if ((sr & UARTDM_SR_RXRDY_BMSK) == 0) {
msm_hsl_port->old_snap_state -= count;
break;
}
- c = msm_hsl_read(port, UARTDM_RF_ADDR);
+ c = msm_hsl_read(port, regmap[vid][UARTDM_RF]);
if (sr & UARTDM_SR_RX_BREAK_BMSK) {
port->icount.brk++;
if (uart_handle_break(port))
@@ -305,7 +370,9 @@
int tx_count;
int x;
unsigned int tf_pointer = 0;
+ unsigned int vid;
+ vid = UART_TO_MSM(port)->ver_id;
tx_count = uart_circ_chars_pending(xmit);
if (tx_count > (UART_XMIT_SIZE - xmit->tail))
@@ -316,13 +383,14 @@
/* Handle x_char */
if (port->x_char) {
wait_for_xmitr(port, UARTDM_ISR_TX_READY_BMSK);
- msm_hsl_write(port, tx_count + 1, UARTDM_NCF_TX_ADDR);
- msm_hsl_write(port, port->x_char, UARTDM_TF_ADDR);
+ msm_hsl_write(port, tx_count + 1,
+ regmap[vid][UARTDM_NCF_TX]);
+ msm_hsl_write(port, port->x_char, regmap[vid][UARTDM_TF]);
port->icount.tx++;
port->x_char = 0;
} else if (tx_count) {
wait_for_xmitr(port, UARTDM_ISR_TX_READY_BMSK);
- msm_hsl_write(port, tx_count, UARTDM_NCF_TX_ADDR);
+ msm_hsl_write(port, tx_count, regmap[vid][UARTDM_NCF_TX]);
}
if (!tx_count) {
msm_hsl_stop_tx(port);
@@ -330,7 +398,7 @@
}
while (tf_pointer < tx_count) {
- if (unlikely(!(msm_hsl_read(port, UARTDM_SR_ADDR) &
+ if (unlikely(!(msm_hsl_read(port, regmap[vid][UARTDM_SR]) &
UARTDM_SR_TXRDY_BMSK)))
continue;
switch (tx_count - tf_pointer) {
@@ -358,7 +426,7 @@
break;
}
}
- msm_hsl_write(port, x, UARTDM_TF_ADDR);
+ msm_hsl_write(port, x, regmap[vid][UARTDM_TF]);
xmit->tail = ((tx_count - tf_pointer < 4) ?
(tx_count - tf_pointer + xmit->tail) :
(xmit->tail + 4)) & (UART_XMIT_SIZE - 1);
@@ -376,7 +444,9 @@
static void handle_delta_cts(struct uart_port *port)
{
- msm_hsl_write(port, RESET_CTS, UARTDM_CR_ADDR);
+ unsigned int vid = UART_TO_MSM(port)->ver_id;
+
+ msm_hsl_write(port, RESET_CTS, regmap[vid][UARTDM_CR]);
port->icount.cts++;
wake_up_interruptible(&port->state->port.delta_msr_wait);
}
@@ -385,20 +455,24 @@
{
struct uart_port *port = dev_id;
struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
+ unsigned int vid;
unsigned int misr;
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
clk_en(port, 1);
- misr = msm_hsl_read(port, UARTDM_MISR_ADDR);
- msm_hsl_write(port, 0, UARTDM_IMR_ADDR); /* disable interrupt */
+ vid = msm_hsl_port->ver_id;
+ misr = msm_hsl_read(port, regmap[vid][UARTDM_MISR]);
+ /* disable interrupt */
+ msm_hsl_write(port, 0, regmap[vid][UARTDM_IMR]);
if (misr & (UARTDM_ISR_RXSTALE_BMSK | UARTDM_ISR_RXLEV_BMSK)) {
handle_rx(port, misr);
if (misr & (UARTDM_ISR_RXSTALE_BMSK))
- msm_hsl_write(port, RESET_STALE_INT, UARTDM_CR_ADDR);
- msm_hsl_write(port, 6500, UARTDM_DMRX_ADDR);
- msm_hsl_write(port, STALE_EVENT_ENABLE, UARTDM_CR_ADDR);
+ msm_hsl_write(port, RESET_STALE_INT,
+ regmap[vid][UARTDM_CR]);
+ msm_hsl_write(port, 6500, regmap[vid][UARTDM_DMRX]);
+ msm_hsl_write(port, STALE_EVENT_ENABLE, regmap[vid][UARTDM_CR]);
}
if (misr & UARTDM_ISR_TXLEV_BMSK)
handle_tx(port);
@@ -407,7 +481,7 @@
handle_delta_cts(port);
/* restore interrupt */
- msm_hsl_write(port, msm_hsl_port->imr, UARTDM_IMR_ADDR);
+ msm_hsl_write(port, msm_hsl_port->imr, regmap[vid][UARTDM_IMR]);
clk_en(port, 0);
spin_unlock_irqrestore(&port->lock, flags);
@@ -416,10 +490,11 @@
static unsigned int msm_hsl_tx_empty(struct uart_port *port)
{
+ unsigned int vid = UART_TO_MSM(port)->ver_id;
unsigned int ret;
clk_en(port, 1);
- ret = (msm_hsl_read(port, UARTDM_SR_ADDR) &
+ ret = (msm_hsl_read(port, regmap[vid][UARTDM_SR]) &
UARTDM_SR_TXEMT_BMSK) ? TIOCSER_TEMT : 0;
clk_en(port, 0);
@@ -428,13 +503,15 @@
static void msm_hsl_reset(struct uart_port *port)
{
+ unsigned int vid = UART_TO_MSM(port)->ver_id;
+
/* reset everything */
- msm_hsl_write(port, RESET_RX, UARTDM_CR_ADDR);
- msm_hsl_write(port, RESET_TX, UARTDM_CR_ADDR);
- msm_hsl_write(port, RESET_ERROR_STATUS, UARTDM_CR_ADDR);
- msm_hsl_write(port, RESET_BREAK_INT, UARTDM_CR_ADDR);
- msm_hsl_write(port, RESET_CTS, UARTDM_CR_ADDR);
- msm_hsl_write(port, RFR_LOW, UARTDM_CR_ADDR);
+ msm_hsl_write(port, RESET_RX, regmap[vid][UARTDM_CR]);
+ msm_hsl_write(port, RESET_TX, regmap[vid][UARTDM_CR]);
+ msm_hsl_write(port, RESET_ERROR_STATUS, regmap[vid][UARTDM_CR]);
+ msm_hsl_write(port, RESET_BREAK_INT, regmap[vid][UARTDM_CR]);
+ msm_hsl_write(port, RESET_CTS, regmap[vid][UARTDM_CR]);
+ msm_hsl_write(port, RFR_LOW, regmap[vid][UARTDM_CR]);
}
static unsigned int msm_hsl_get_mctrl(struct uart_port *port)
@@ -444,34 +521,35 @@
static void msm_hsl_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
+ unsigned int vid = UART_TO_MSM(port)->ver_id;
unsigned int mr;
unsigned int loop_mode;
clk_en(port, 1);
- mr = msm_hsl_read(port, UARTDM_MR1_ADDR);
+ mr = msm_hsl_read(port, regmap[vid][UARTDM_MR1]);
if (!(mctrl & TIOCM_RTS)) {
mr &= ~UARTDM_MR1_RX_RDY_CTL_BMSK;
- msm_hsl_write(port, mr, UARTDM_MR1_ADDR);
- msm_hsl_write(port, RFR_HIGH, UARTDM_CR_ADDR);
+ msm_hsl_write(port, mr, regmap[vid][UARTDM_MR1]);
+ msm_hsl_write(port, RFR_HIGH, regmap[vid][UARTDM_CR]);
} else {
mr |= UARTDM_MR1_RX_RDY_CTL_BMSK;
- msm_hsl_write(port, mr, UARTDM_MR1_ADDR);
+ msm_hsl_write(port, mr, regmap[vid][UARTDM_MR1]);
}
loop_mode = TIOCM_LOOP & mctrl;
if (loop_mode) {
- mr = msm_hsl_read(port, UARTDM_MR2_ADDR);
+ mr = msm_hsl_read(port, regmap[vid][UARTDM_MR2]);
mr |= UARTDM_MR2_LOOP_MODE_BMSK;
- msm_hsl_write(port, mr, UARTDM_MR2_ADDR);
+ msm_hsl_write(port, mr, regmap[vid][UARTDM_MR2]);
/* Reset TX */
msm_hsl_reset(port);
/* Turn on Uart Receiver & Transmitter*/
msm_hsl_write(port, UARTDM_CR_RX_EN_BMSK
- | UARTDM_CR_TX_EN_BMSK, UARTDM_CR_ADDR);
+ | UARTDM_CR_TX_EN_BMSK, regmap[vid][UARTDM_CR]);
}
clk_en(port, 0);
@@ -479,12 +557,14 @@
static void msm_hsl_break_ctl(struct uart_port *port, int break_ctl)
{
+ unsigned int vid = UART_TO_MSM(port)->ver_id;
+
clk_en(port, 1);
if (break_ctl)
- msm_hsl_write(port, START_BREAK, UARTDM_CR_ADDR);
+ msm_hsl_write(port, START_BREAK, regmap[vid][UARTDM_CR]);
else
- msm_hsl_write(port, STOP_BREAK, UARTDM_CR_ADDR);
+ msm_hsl_write(port, STOP_BREAK, regmap[vid][UARTDM_CR]);
clk_en(port, 0);
}
@@ -493,6 +573,7 @@
{
unsigned int baud_code, rxstale, watermark;
unsigned int data;
+ unsigned int vid;
struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
switch (baud) {
@@ -558,12 +639,16 @@
break;
}
- msm_hsl_write(port, baud_code, UARTDM_CSR_ADDR);
+ vid = msm_hsl_port->ver_id;
+ msm_hsl_write(port, baud_code, regmap[vid][UARTDM_CSR]);
+
+ if (vid == UARTDM_VERSION_14)
+ rxstale = 5000;
/* RX stale watermark */
watermark = UARTDM_IPR_STALE_LSB_BMSK & rxstale;
watermark |= UARTDM_IPR_STALE_TIMEOUT_MSB_BMSK & (rxstale << 2);
- msm_hsl_write(port, watermark, UARTDM_IPR_ADDR);
+ msm_hsl_write(port, watermark, regmap[vid][UARTDM_IPR]);
/* Set RX watermark
* Configure Rx Watermark as 3/4 size of Rx FIFO.
@@ -572,26 +657,26 @@
* Hence configuring Rx Watermark as 12 Words.
*/
watermark = (port->fifosize * 3) / (4*4);
- msm_hsl_write(port, watermark, UARTDM_RFWR_ADDR);
+ msm_hsl_write(port, watermark, regmap[vid][UARTDM_RFWR]);
/* set TX watermark */
- msm_hsl_write(port, 0, UARTDM_TFWR_ADDR);
+ msm_hsl_write(port, 0, regmap[vid][UARTDM_TFWR]);
- msm_hsl_write(port, CR_PROTECTION_EN, UARTDM_CR_ADDR);
+ msm_hsl_write(port, CR_PROTECTION_EN, regmap[vid][UARTDM_CR]);
msm_hsl_reset(port);
data = UARTDM_CR_TX_EN_BMSK;
data |= UARTDM_CR_RX_EN_BMSK;
/* enable TX & RX */
- msm_hsl_write(port, data, UARTDM_CR_ADDR);
+ msm_hsl_write(port, data, regmap[vid][UARTDM_CR]);
msm_hsl_write(port, RESET_STALE_INT, UARTDM_CR_ADDR);
/* turn on RX and CTS interrupts */
msm_hsl_port->imr = UARTDM_ISR_RXSTALE_BMSK
| UARTDM_ISR_DELTA_CTS_BMSK | UARTDM_ISR_RXLEV_BMSK;
- msm_hsl_write(port, msm_hsl_port->imr, UARTDM_IMR_ADDR);
- msm_hsl_write(port, 6500, UARTDM_DMRX_ADDR);
- msm_hsl_write(port, STALE_EVENT_ENABLE, UARTDM_CR_ADDR);
+ msm_hsl_write(port, msm_hsl_port->imr, regmap[vid][UARTDM_IMR]);
+ msm_hsl_write(port, 6500, regmap[vid][UARTDM_DMRX]);
+ msm_hsl_write(port, STALE_EVENT_ENABLE, regmap[vid][UARTDM_CR]);
}
static void msm_hsl_init_clock(struct uart_port *port)
@@ -611,6 +696,7 @@
const struct msm_serial_hslite_platform_data *pdata =
pdev->dev.platform_data;
unsigned int data, rfr_level;
+ unsigned int vid;
int ret;
unsigned long flags;
@@ -665,13 +751,14 @@
spin_lock_irqsave(&port->lock, flags);
+ vid = msm_hsl_port->ver_id;
/* set automatic RFR level */
- data = msm_hsl_read(port, UARTDM_MR1_ADDR);
+ data = msm_hsl_read(port, regmap[vid][UARTDM_MR1]);
data &= ~UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK;
data &= ~UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK;
data |= UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK & (rfr_level << 2);
data |= UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK & rfr_level;
- msm_hsl_write(port, data, UARTDM_MR1_ADDR);
+ msm_hsl_write(port, data, regmap[vid][UARTDM_MR1]);
spin_unlock_irqrestore(&port->lock, flags);
ret = request_irq(port->irq, msm_hsl_irq, IRQF_TRIGGER_HIGH,
@@ -693,7 +780,8 @@
clk_en(port, 1);
msm_hsl_port->imr = 0;
- msm_hsl_write(port, 0, UARTDM_IMR_ADDR); /* disable interrupts */
+ /* disable interrupts */
+ msm_hsl_write(port, 0, regmap[msm_hsl_port->ver_id][UARTDM_IMR]);
clk_en(port, 0);
@@ -718,6 +806,7 @@
{
unsigned long flags;
unsigned int baud, mr;
+ unsigned int vid;
spin_lock_irqsave(&port->lock, flags);
clk_en(port, 1);
@@ -727,8 +816,9 @@
msm_hsl_set_baud_rate(port, baud);
+ vid = UART_TO_MSM(port)->ver_id;
/* calculate parity */
- mr = msm_hsl_read(port, UARTDM_MR2_ADDR);
+ mr = msm_hsl_read(port, regmap[vid][UARTDM_MR2]);
mr &= ~UARTDM_MR2_PARITY_MODE_BMSK;
if (termios->c_cflag & PARENB) {
if (termios->c_cflag & PARODD)
@@ -765,16 +855,16 @@
mr |= STOP_BIT_ONE;
/* set parity, bits per char, and stop bit */
- msm_hsl_write(port, mr, UARTDM_MR2_ADDR);
+ msm_hsl_write(port, mr, regmap[vid][UARTDM_MR2]);
/* calculate and set hardware flow control */
- mr = msm_hsl_read(port, UARTDM_MR1_ADDR);
+ mr = msm_hsl_read(port, regmap[vid][UARTDM_MR1]);
mr &= ~(UARTDM_MR1_CTS_CTL_BMSK | UARTDM_MR1_RX_RDY_CTL_BMSK);
if (termios->c_cflag & CRTSCTS) {
mr |= UARTDM_MR1_CTS_CTL_BMSK;
mr |= UARTDM_MR1_RX_RDY_CTL_BMSK;
}
- msm_hsl_write(port, mr, UARTDM_MR1_ADDR);
+ msm_hsl_write(port, mr, regmap[vid][UARTDM_MR1]);
/* Configure status bits to ignore based on termio flags. */
port->read_status_mask = 0;
@@ -799,11 +889,12 @@
struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
struct platform_device *pdev = to_platform_device(port->dev);
struct resource *uart_resource;
- struct resource *gsbi_resource;
resource_size_t size;
uart_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM,
"uartdm_resource");
+ if (!uart_resource)
+ uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (unlikely(!uart_resource))
return;
size = uart_resource->end - uart_resource->start + 1;
@@ -815,11 +906,6 @@
if (msm_serial_hsl_has_gsbi(port)) {
iowrite32(GSBI_PROTOCOL_IDLE, msm_hsl_port->mapped_gsbi +
GSBI_CONTROL_ADDR);
- gsbi_resource = platform_get_resource_byname(pdev,
- IORESOURCE_MEM,
- "gsbi_resource");
-
- size = gsbi_resource->end - gsbi_resource->start + 1;
iounmap(msm_hsl_port->mapped_gsbi);
msm_hsl_port->mapped_gsbi = NULL;
}
@@ -835,6 +921,8 @@
uart_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM,
"uartdm_resource");
+ if (!uart_resource)
+ uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (unlikely(!uart_resource)) {
pr_err("%s: can't get uartdm resource\n", __func__);
return -ENXIO;
@@ -857,6 +945,9 @@
gsbi_resource = platform_get_resource_byname(pdev,
IORESOURCE_MEM,
"gsbi_resource");
+ if (!gsbi_resource)
+ gsbi_resource = platform_get_resource(pdev,
+ IORESOURCE_MEM, 1);
if (unlikely(!gsbi_resource)) {
pr_err("%s: can't get gsbi resource\n", __func__);
return -ENXIO;
@@ -988,28 +1079,35 @@
* Derived from wait_for_xmitr in 8250 serial driver by Russell King */
void wait_for_xmitr(struct uart_port *port, int bits)
{
- if (!(msm_hsl_read(port, UARTDM_SR_ADDR) & UARTDM_SR_TXEMT_BMSK)) {
- while ((msm_hsl_read(port, UARTDM_ISR_ADDR) & bits) != bits) {
+ unsigned int vid = UART_TO_MSM(port)->ver_id;
+
+ if (!(msm_hsl_read(port, regmap[vid][UARTDM_SR]) &
+ UARTDM_SR_TXEMT_BMSK)) {
+ while ((msm_hsl_read(port, regmap[vid][UARTDM_ISR]) &
+ bits) != bits) {
udelay(1);
touch_nmi_watchdog();
cpu_relax();
}
- msm_hsl_write(port, CLEAR_TX_READY, UARTDM_CR_ADDR);
+ msm_hsl_write(port, CLEAR_TX_READY, regmap[vid][UARTDM_CR]);
}
}
#ifdef CONFIG_SERIAL_MSM_HSL_CONSOLE
static void msm_hsl_console_putchar(struct uart_port *port, int ch)
{
- wait_for_xmitr(port, UARTDM_ISR_TX_READY_BMSK);
- msm_hsl_write(port, 1, UARTDM_NCF_TX_ADDR);
+ unsigned int vid = UART_TO_MSM(port)->ver_id;
- while (!(msm_hsl_read(port, UARTDM_SR_ADDR) & UARTDM_SR_TXRDY_BMSK)) {
+ wait_for_xmitr(port, UARTDM_ISR_TX_READY_BMSK);
+ msm_hsl_write(port, 1, regmap[vid][UARTDM_NCF_TX]);
+
+ while (!(msm_hsl_read(port, regmap[vid][UARTDM_SR]) &
+ UARTDM_SR_TXRDY_BMSK)) {
udelay(1);
touch_nmi_watchdog();
}
- msm_hsl_write(port, ch, UARTDM_TF_ADDR);
+ msm_hsl_write(port, ch, regmap[vid][UARTDM_TF]);
}
static void msm_hsl_console_write(struct console *co, const char *s,
@@ -1017,12 +1115,14 @@
{
struct uart_port *port;
struct msm_hsl_port *msm_hsl_port;
+ unsigned int vid;
int locked;
BUG_ON(co->index < 0 || co->index >= UART_NR);
port = get_port_from_line(co->index);
msm_hsl_port = UART_TO_MSM(port);
+ vid = msm_hsl_port->ver_id;
/* not pretty, but we can end up here via various convoluted paths */
if (port->sysrq || oops_in_progress)
@@ -1031,9 +1131,9 @@
locked = 1;
spin_lock(&port->lock);
}
- msm_hsl_write(port, 0, UARTDM_IMR_ADDR);
+ msm_hsl_write(port, 0, regmap[vid][UARTDM_IMR]);
uart_console_write(port, s, count, msm_hsl_console_putchar);
- msm_hsl_write(port, msm_hsl_port->imr, UARTDM_IMR_ADDR);
+ msm_hsl_write(port, msm_hsl_port->imr, regmap[vid][UARTDM_IMR]);
if (locked == 1)
spin_unlock(&port->lock);
}
@@ -1041,6 +1141,7 @@
static int __init msm_hsl_console_setup(struct console *co, char *options)
{
struct uart_port *port;
+ unsigned int vid;
int baud = 0, flow, bits, parity;
int ret;
@@ -1048,6 +1149,7 @@
return -ENXIO;
port = get_port_from_line(co->index);
+ vid = UART_TO_MSM(port)->ver_id;
if (unlikely(!port->membase))
return -ENXIO;
@@ -1068,7 +1170,7 @@
parity = 'n';
flow = 'n';
msm_hsl_write(port, UARTDM_MR2_BITS_PER_CHAR_8 | STOP_BIT_ONE,
- UARTDM_MR2_ADDR); /* 8N1 */
+ regmap[vid][UARTDM_MR2]); /* 8N1 */
if (baud < 300 || baud > 115200)
baud = 115200;
@@ -1077,8 +1179,8 @@
ret = uart_set_options(port, co, baud, parity, bits, flow);
msm_hsl_reset(port);
/* Enable transmitter */
- msm_hsl_write(port, CR_PROTECTION_EN, UARTDM_CR_ADDR);
- msm_hsl_write(port, UARTDM_CR_TX_EN_BMSK, UARTDM_CR_ADDR);
+ msm_hsl_write(port, CR_PROTECTION_EN, regmap[vid][UARTDM_CR]);
+ msm_hsl_write(port, UARTDM_CR_TX_EN_BMSK, regmap[vid][UARTDM_CR]);
printk(KERN_INFO "msm_serial_hsl: console setup on port #%d\n",
port->line);
@@ -1112,14 +1214,20 @@
.cons = MSM_HSL_CONSOLE,
};
+static atomic_t msm_serial_hsl_next_id = ATOMIC_INIT(0);
+
static int __devinit msm_serial_hsl_probe(struct platform_device *pdev)
{
struct msm_hsl_port *msm_hsl_port;
struct resource *uart_resource;
struct resource *gsbi_resource;
struct uart_port *port;
+ const struct of_device_id *match;
int ret;
+ if (pdev->id == -1)
+ pdev->id = atomic_inc_return(&msm_serial_hsl_next_id) - 1;
+
if (unlikely(pdev->id < 0 || pdev->id >= UART_NR))
return -ENXIO;
@@ -1129,9 +1237,17 @@
port->dev = &pdev->dev;
msm_hsl_port = UART_TO_MSM(port);
+ match = of_match_device(msm_hsl_match_table, &pdev->dev);
+ if (!match)
+ msm_hsl_port->ver_id = UARTDM_VERSION_11_13;
+ else
+ msm_hsl_port->ver_id = (unsigned int)match->data;
+
gsbi_resource = platform_get_resource_byname(pdev,
IORESOURCE_MEM,
"gsbi_resource");
+ if (!gsbi_resource)
+ gsbi_resource = platform_get_resource(pdev, IORESOURCE_MEM, 1);
msm_hsl_port->clk = clk_get(&pdev->dev, "core_clk");
if (gsbi_resource) {
msm_hsl_port->is_uartdm = 1;
@@ -1150,10 +1266,11 @@
return PTR_ERR(msm_hsl_port->pclk);
}
-
uart_resource = platform_get_resource_byname(pdev,
IORESOURCE_MEM,
"uartdm_resource");
+ if (!uart_resource)
+ uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (unlikely(!uart_resource)) {
printk(KERN_ERR "getting uartdm_resource failed\n");
return -ENXIO;
@@ -1281,6 +1398,7 @@
.name = "msm_serial_hsl",
.owner = THIS_MODULE,
.pm = &msm_hsl_dev_pm_ops,
+ .of_match_table = msm_hsl_match_table,
},
};
diff --git a/drivers/usb/gadget/android.c b/drivers/usb/gadget/android.c
index 8d58833..fdd0ba8 100644
--- a/drivers/usb/gadget/android.c
+++ b/drivers/usb/gadget/android.c
@@ -817,6 +817,7 @@
&common->luns[0].dev.kobj,
"lun");
if (err) {
+ fsg_common_release(&common->ref);
kfree(config);
return err;
}
diff --git a/drivers/usb/gadget/ci13xxx_udc.c b/drivers/usb/gadget/ci13xxx_udc.c
index 7dc7377..11bfe9f 100644
--- a/drivers/usb/gadget/ci13xxx_udc.c
+++ b/drivers/usb/gadget/ci13xxx_udc.c
@@ -1857,6 +1857,11 @@
dbg_event(0xFF, "BUS RST", 0);
spin_unlock(udc->lock);
+
+ /*stop charging upon reset */
+ if (udc->transceiver)
+ otg_set_power(udc->transceiver, 0);
+
retval = _gadget_stop_activity(&udc->gadget);
if (retval)
goto done;
diff --git a/drivers/usb/gadget/f_rmnet.c b/drivers/usb/gadget/f_rmnet.c
index 69f158a..6f0fb07 100644
--- a/drivers/usb/gadget/f_rmnet.c
+++ b/drivers/usb/gadget/f_rmnet.c
@@ -444,7 +444,7 @@
event->wIndex = cpu_to_le16(dev->ifc_id);
event->wLength = cpu_to_le16(0);
- status = usb_ep_queue(dev->notify, dev->notify_req, GFP_KERNEL);
+ status = usb_ep_queue(dev->notify, dev->notify_req, GFP_ATOMIC);
if (status < 0) {
if (!atomic_read(&dev->online))
return;
@@ -789,8 +789,12 @@
spin_lock_irqsave(&dev->lock, flags);
dev->cdev = c->cdev;
f = &dev->port.func;
- f->name = kasprintf(GFP_KERNEL, "rmnet%d", portno);
+ f->name = kasprintf(GFP_ATOMIC, "rmnet%d", portno);
spin_unlock_irqrestore(&dev->lock, flags);
+ if (!f->name) {
+ pr_err("%s: cannot allocate memory for name\n", __func__);
+ return -ENOMEM;
+ }
f->strings = rmnet_strings;
f->bind = frmnet_bind;
diff --git a/drivers/usb/gadget/f_rmnet_sdio.c b/drivers/usb/gadget/f_rmnet_sdio.c
index b15c221..f63d939 100644
--- a/drivers/usb/gadget/f_rmnet_sdio.c
+++ b/drivers/usb/gadget/f_rmnet_sdio.c
@@ -1358,17 +1358,20 @@
struct rmnet_sdio_dev *dev = container_of(f, struct rmnet_sdio_dev,
function);
+ cancel_delayed_work_sync(&dev->sdio_open_work);
destroy_workqueue(dev->wq);
- rmnet_sdio_free_buf(dev);
dev->epout = dev->epin = dev->epnotify = NULL; /* release endpoints */
- msm_sdio_dmux_close(rmnet_sdio_data_ch);
- sdio_cmux_close(rmnet_sdio_ctl_ch);
+ if (test_bit(RMNET_SDIO_CH_OPEN, &dev->data_ch_status)) {
+ msm_sdio_dmux_close(rmnet_sdio_data_ch);
+ clear_bit(RMNET_SDIO_CH_OPEN, &dev->data_ch_status);
+ }
-
- clear_bit(RMNET_SDIO_CH_OPEN, &dev->data_ch_status);
- clear_bit(RMNET_SDIO_CH_OPEN, &dev->ctrl_ch_status);
+ if (test_bit(RMNET_SDIO_CH_OPEN, &dev->ctrl_ch_status)) {
+ sdio_cmux_close(rmnet_sdio_ctl_ch);
+ clear_bit(RMNET_SDIO_CH_OPEN, &dev->ctrl_ch_status);
+ }
debugfs_remove_recursive(dev->dent);
@@ -1454,7 +1457,7 @@
static void rmnet_sdio_debugfs_init(struct rmnet_sdio_dev *dev)
{
- dev->dent = debugfs_create_dir("usb_rmnet", 0);
+ dev->dent = debugfs_create_dir("usb_rmnet_sdio", 0);
if (IS_ERR(dev->dent))
return;
diff --git a/drivers/usb/gadget/f_rmnet_smd.c b/drivers/usb/gadget/f_rmnet_smd.c
index b8dd3a5..f59b683 100644
--- a/drivers/usb/gadget/f_rmnet_smd.c
+++ b/drivers/usb/gadget/f_rmnet_smd.c
@@ -42,6 +42,11 @@
#include "gadget_chips.h"
+#ifndef CONFIG_MSM_SMD
+#define CONFIG_RMNET_SMD_CTL_CHANNEL ""
+#define CONFIG_RMNET_SMD_DATA_CHANNEL ""
+#endif
+
static char *rmnet_ctl_ch = CONFIG_RMNET_SMD_CTL_CHANNEL;
module_param(rmnet_ctl_ch, charp, S_IRUGO);
MODULE_PARM_DESC(rmnet_ctl_ch, "RmNet control SMD channel");
@@ -1218,7 +1223,7 @@
static void rmnet_smd_debugfs_init(struct rmnet_smd_dev *dev)
{
- dent_smd = debugfs_create_dir("usb_rmnet", 0);
+ dent_smd = debugfs_create_dir("usb_rmnet_smd", 0);
if (IS_ERR(dent_smd))
return;
diff --git a/drivers/usb/gadget/f_rmnet_smd_sdio.c b/drivers/usb/gadget/f_rmnet_smd_sdio.c
index eda547a..2ddbd7c 100644
--- a/drivers/usb/gadget/f_rmnet_smd_sdio.c
+++ b/drivers/usb/gadget/f_rmnet_smd_sdio.c
@@ -1071,7 +1071,7 @@
spin_lock(&dev->lock);
if (!ctrl_dev->opened) {
spin_unlock(&dev->lock);
- kfree(cpkt);
+ rmnet_mux_free_ctrl_pkt(cpkt);
dev->cpkts_drp_cnt++;
pr_err_ratelimited(
"%s: ctrl pkts dropped: cpkts_drp_cnt: %lu\n",
diff --git a/drivers/usb/gadget/u_sdio.c b/drivers/usb/gadget/u_sdio.c
index fd01dbf..6ba7543 100644
--- a/drivers/usb/gadget/u_sdio.c
+++ b/drivers/usb/gadget/u_sdio.c
@@ -1107,7 +1107,6 @@
struct usb_cdc_line_coding coding;
int i;
int ret = 0;
- struct sdio_port_info *port_info;
pr_debug("%s: gadget:(%p) count:%d\n", __func__, g, count);
@@ -1139,7 +1138,6 @@
__func__);
goto free_sdio_ports;
}
- port_info++;
#ifdef DEBUG
/* REVISIT: create one file per port
diff --git a/drivers/usb/host/ehci-msm-hsic.c b/drivers/usb/host/ehci-msm-hsic.c
index 1b8b5d6..093a170 100644
--- a/drivers/usb/host/ehci-msm-hsic.c
+++ b/drivers/usb/host/ehci-msm-hsic.c
@@ -34,6 +34,7 @@
#include <linux/gpio.h>
#include <mach/clk.h>
#include <mach/msm_iomap.h>
+#include <mach/msm_xo.h>
#define MSM_USB_BASE (hcd->regs)
@@ -48,6 +49,7 @@
struct regulator *hsic_vddcx;
bool async_int;
atomic_t in_lpm;
+ struct msm_xo_voter *xo_handle;
struct wake_lock wlock;
};
@@ -145,6 +147,81 @@
return 0;
}
+#define HSIC_HUB_VDD_VOL_MIN 1650000 /* uV */
+#define HSIC_HUB_VDD_VOL_MAX 1950000 /* uV */
+#define HSIC_HUB_VDD_LOAD 36000 /* uA */
+static int msm_hsic_config_hub(struct msm_hsic_hcd *mehci, int init)
+{
+ int ret = 0;
+ struct msm_hsic_host_platform_data *pdata;
+ static struct regulator *hsic_hub_reg;
+
+ pdata = mehci->dev->platform_data;
+ if (!pdata->hub_reset)
+ return ret;
+
+ if (!init)
+ goto disable_reg;
+
+ hsic_hub_reg = regulator_get(mehci->dev, "EXT_HUB_VDDIO");
+ if (IS_ERR(hsic_hub_reg)) {
+ dev_err(mehci->dev, "unable to get ext hub vddcx\n");
+ return PTR_ERR(hsic_hub_reg);
+ }
+
+ ret = gpio_request(pdata->hub_reset, "HSIC_HUB_RESET_GPIO");
+ if (ret < 0) {
+ dev_err(mehci->dev, "gpio request failed for GPIO%d\n",
+ pdata->hub_reset);
+ goto gpio_req_fail;
+ }
+
+ ret = regulator_set_voltage(hsic_hub_reg,
+ HSIC_HUB_VDD_VOL_MIN,
+ HSIC_HUB_VDD_VOL_MAX);
+ if (ret) {
+ dev_err(mehci->dev, "unable to set the voltage"
+ "for hsic hub reg\n");
+ goto reg_set_voltage_fail;
+ }
+
+ ret = regulator_set_optimum_mode(hsic_hub_reg,
+ HSIC_HUB_VDD_LOAD);
+ if (ret < 0) {
+ pr_err("%s: Unable to set optimum mode of the regulator:"
+ "VDDCX\n", __func__);
+ goto reg_optimum_mode_fail;
+ }
+
+ ret = regulator_enable(hsic_hub_reg);
+ if (ret) {
+ dev_err(mehci->dev, "unable to enable ext hub vddcx\n");
+ goto reg_enable_fail;
+ }
+
+ gpio_direction_output(pdata->hub_reset, 0);
+ /* Hub reset should be asserted for minimum 2usec before deasserting */
+ udelay(5);
+ gpio_direction_output(pdata->hub_reset, 1);
+
+ return 0;
+
+disable_reg:
+ regulator_disable(hsic_hub_reg);
+reg_enable_fail:
+ regulator_set_optimum_mode(hsic_hub_reg, 0);
+reg_optimum_mode_fail:
+ regulator_set_voltage(hsic_hub_reg, 0,
+ HSIC_HUB_VDD_VOL_MIN);
+reg_set_voltage_fail:
+ gpio_free(pdata->hub_reset);
+gpio_req_fail:
+ regulator_put(hsic_hub_reg);
+
+ return ret;
+
+}
+
static int msm_hsic_config_gpios(struct msm_hsic_hcd *mehci, int gpio_en)
{
int rc = 0;
@@ -294,8 +371,9 @@
static int msm_hsic_suspend(struct msm_hsic_hcd *mehci)
{
struct usb_hcd *hcd = hsic_to_hcd(mehci);
- int cnt = 0;
+ int cnt = 0, ret;
u32 val;
+ struct msm_hsic_host_platform_data *pdata;
if (atomic_read(&mehci->in_lpm)) {
dev_dbg(mehci->dev, "%s called in lpm\n", __func__);
@@ -345,6 +423,13 @@
clk_disable(mehci->hsic_clk);
clk_disable(mehci->cal_clk);
clk_disable(mehci->ahb_clk);
+ pdata = mehci->dev->platform_data;
+ if (pdata->hub_reset) {
+ ret = msm_xo_mode_vote(mehci->xo_handle, MSM_XO_MODE_OFF);
+ if (ret)
+ pr_err("%s failed to devote for"
+ "TCXO D1 buffer%d\n", __func__, ret);
+ }
atomic_set(&mehci->in_lpm, 1);
enable_irq(hcd->irq);
@@ -358,8 +443,9 @@
static int msm_hsic_resume(struct msm_hsic_hcd *mehci)
{
struct usb_hcd *hcd = hsic_to_hcd(mehci);
- int cnt = 0;
+ int cnt = 0, ret;
unsigned temp;
+ struct msm_hsic_host_platform_data *pdata;
if (!atomic_read(&mehci->in_lpm)) {
dev_dbg(mehci->dev, "%s called in !in_lpm\n", __func__);
@@ -368,6 +454,13 @@
wake_lock(&mehci->wlock);
+ pdata = mehci->dev->platform_data;
+ if (pdata->hub_reset) {
+ ret = msm_xo_mode_vote(mehci->xo_handle, MSM_XO_MODE_ON);
+ if (ret)
+ pr_err("%s failed to vote for"
+ "TCXO D1 buffer%d\n", __func__, ret);
+ }
clk_enable(mehci->sys_clk);
clk_enable(mehci->hsic_clk);
clk_enable(mehci->cal_clk);
@@ -598,6 +691,7 @@
struct usb_hcd *hcd;
struct resource *res;
struct msm_hsic_hcd *mehci;
+ struct msm_hsic_host_platform_data *pdata;
int ret;
dev_dbg(&pdev->dev, "ehci_msm-hsic probe\n");
@@ -649,10 +743,34 @@
goto deinit_clocks;
}
+ pdata = mehci->dev->platform_data;
+ if (pdata->hub_reset) {
+ mehci->xo_handle = msm_xo_get(MSM_XO_TCXO_D1, "hsic");
+ if (IS_ERR(mehci->xo_handle)) {
+ pr_err(" %s not able to get the handle"
+ "to vote for TCXO D1 buffer\n", __func__);
+ ret = PTR_ERR(mehci->xo_handle);
+ goto deinit_vddcx;
+ }
+
+ ret = msm_xo_mode_vote(mehci->xo_handle, MSM_XO_MODE_ON);
+ if (ret) {
+ pr_err("%s failed to vote for TCXO"
+ "D1 buffer%d\n", __func__, ret);
+ goto free_xo_handle;
+ }
+ }
+
+ ret = msm_hsic_config_hub(mehci, 1);
+ if (ret) {
+ dev_err(&pdev->dev, "unable to initialize hsic hub");
+ goto free_xo_handle;
+ }
+
ret = msm_hsic_reset(mehci);
if (ret) {
dev_err(&pdev->dev, "unable to initialize PHY\n");
- goto deinit_vddcx;
+ goto deinit_hub;
}
ret = usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
@@ -676,6 +794,11 @@
unconfig_gpio:
msm_hsic_config_gpios(mehci, 0);
+deinit_hub:
+ msm_hsic_config_hub(mehci, 0);
+free_xo_handle:
+ if (pdata->hub_reset)
+ msm_xo_put(mehci->xo_handle);
deinit_vddcx:
msm_hsic_init_vddcx(mehci, 0);
deinit_clocks:
@@ -692,6 +815,7 @@
{
struct usb_hcd *hcd = platform_get_drvdata(pdev);
struct msm_hsic_hcd *mehci = hcd_to_hsic(hcd);
+ struct msm_hsic_host_platform_data *pdata;
device_init_wakeup(&pdev->dev, 0);
pm_runtime_disable(&pdev->dev);
@@ -699,6 +823,10 @@
usb_remove_hcd(hcd);
msm_hsic_config_gpios(mehci, 0);
+ msm_hsic_config_hub(mehci, 0);
+ pdata = mehci->dev->platform_data;
+ if (pdata->hub_reset)
+ msm_xo_put(mehci->xo_handle);
msm_hsic_init_vddcx(mehci, 0);
msm_hsic_init_clocks(mehci, 0);
diff --git a/drivers/usb/misc/Kconfig b/drivers/usb/misc/Kconfig
index 1135806..98e57d5 100644
--- a/drivers/usb/misc/Kconfig
+++ b/drivers/usb/misc/Kconfig
@@ -283,7 +283,7 @@
config USB_QCOM_DUN_BRIDGE
tristate "USB Qualcomm modem DUN bridge driver"
- depends on USB && !USB_SERIAL_QUALCOMM
+ depends on USB
help
Say Y here if you have a Qualcomm modem device connected via USB that
will be bridged in kernel space. This driver will enable bridging
diff --git a/drivers/usb/otg/msm72k_otg.c b/drivers/usb/otg/msm72k_otg.c
index 88d6b5b..84b8472 100644
--- a/drivers/usb/otg/msm72k_otg.c
+++ b/drivers/usb/otg/msm72k_otg.c
@@ -750,6 +750,16 @@
atomic_set(&dev->in_lpm, 1);
+ /*
+ * TODO: put regulators in low power mode by assuming that
+ * regulators are brought back to active state before PHY
+ * becomes active. But this assumption becomes wrong in case of
+ * ACA charger where PHY itself will generate the wakeup
+ * interrupt. This creates a small window where PHY regulators
+ * are in LPM but PHY is in active state and this patch assumes
+ * that there is no harm with this. Till hw folks confirms this
+ * put regulators in lpm.
+ */
if (!host_bus_suspend && dev->pmic_vbus_notif_supp) {
pr_debug("phy can power collapse: (%d)\n",
can_phy_power_collapse(dev));
@@ -849,6 +859,9 @@
struct msm_otg *dev = container_of(w, struct msm_otg, otg_resume_work);
unsigned long timeout;
+ if (can_phy_power_collapse(dev) && dev->pdata->ldo_enable)
+ dev->pdata->ldo_enable(1);
+
msm_otg_get_resume(dev);
if (!is_phy_clk_disabled())
diff --git a/drivers/usb/otg/msm_otg.c b/drivers/usb/otg/msm_otg.c
index 4658469..6c60cc9 100644
--- a/drivers/usb/otg/msm_otg.c
+++ b/drivers/usb/otg/msm_otg.c
@@ -215,12 +215,12 @@
{
int ret = 0;
- if (!hsusb_1p8 || IS_ERR(hsusb_1p8)) {
+ if (IS_ERR(hsusb_1p8)) {
pr_err("%s: HSUSB_1p8 is not initialized\n", __func__);
return -ENODEV;
}
- if (!hsusb_3p3 || IS_ERR(hsusb_3p3)) {
+ if (IS_ERR(hsusb_3p3)) {
pr_err("%s: HSUSB_3p3 is not initialized\n", __func__);
return -ENODEV;
}
diff --git a/drivers/usb/serial/qcserial.c b/drivers/usb/serial/qcserial.c
index 54a9dab..9788db4 100644
--- a/drivers/usb/serial/qcserial.c
+++ b/drivers/usb/serial/qcserial.c
@@ -39,7 +39,6 @@
{USB_DEVICE(0x19d2, 0xfff3)}, /* ONDA Gobi Modem device */
{USB_DEVICE(0x19d2, 0xfff2)}, /* ONDA Gobi QDL device */
{USB_DEVICE(0x1557, 0x0a80)}, /* OQO Gobi QDL device */
- {USB_DEVICE(0x05c6, 0x9001)}, /* Generic Gobi Modem device */
{USB_DEVICE(0x05c6, 0x9002)}, /* Generic Gobi Modem device */
{USB_DEVICE(0x05c6, 0x9202)}, /* Generic Gobi Modem device */
{USB_DEVICE(0x05c6, 0x9203)}, /* Generic Gobi Modem device */
diff --git a/drivers/video/msm/hdmi_msm.c b/drivers/video/msm/hdmi_msm.c
index 63c2147..9805b6c 100644
--- a/drivers/video/msm/hdmi_msm.c
+++ b/drivers/video/msm/hdmi_msm.c
@@ -1231,8 +1231,12 @@
* Configure the Threshold */
HDMI_OUTP_ND(0x0220, (10 << 16) | (2 << 0));
- /* 0x0224 HDMI_DDC_SETUP */
- HDMI_OUTP_ND(0x0224, 0);
+ /*
+ * 0x0224 HDMI_DDC_SETUP
+ * Setting 31:24 bits : Time units to wait before timeout
+ * when clock is being stalled by external sink device
+ */
+ HDMI_OUTP_ND(0x0224, 0xff000000);
/* 0x027C HDMI_DDC_REF
[6] REFTIMER_ENABLE Enable the timer
diff --git a/drivers/video/msm/mdp.c b/drivers/video/msm/mdp.c
index 936b5d4..ca3c079 100644
--- a/drivers/video/msm/mdp.c
+++ b/drivers/video/msm/mdp.c
@@ -1442,6 +1442,10 @@
}
#endif
+ if (mdp_rev >= MDP_REV_40)
+ mfd->cursor_update = mdp_hw_cursor_sync_update;
+ else
+ mfd->cursor_update = mdp_hw_cursor_update;
break;
case MIPI_CMD_PANEL:
diff --git a/drivers/video/msm/mdp.h b/drivers/video/msm/mdp.h
index d2a2cf8..590fd13 100644
--- a/drivers/video/msm/mdp.h
+++ b/drivers/video/msm/mdp.h
@@ -680,7 +680,16 @@
#endif
int mdp_hw_cursor_update(struct fb_info *info, struct fb_cursor *cursor);
+#if defined(CONFIG_FB_MSM_OVERLAY) && defined(CONFIG_FB_MSM_MDP40)
int mdp_hw_cursor_sync_update(struct fb_info *info, struct fb_cursor *cursor);
+#else
+static inline int mdp_hw_cursor_sync_update(struct fb_info *info,
+ struct fb_cursor *cursor)
+{
+ return 0;
+}
+#endif
+
void mdp_enable_irq(uint32 term);
void mdp_disable_irq(uint32 term);
void mdp_disable_irq_nosync(uint32 term);
diff --git a/drivers/video/msm/mdp4_overlay_dsi_video.c b/drivers/video/msm/mdp4_overlay_dsi_video.c
index 93933f3..5cf79c1 100644
--- a/drivers/video/msm/mdp4_overlay_dsi_video.c
+++ b/drivers/video/msm/mdp4_overlay_dsi_video.c
@@ -555,6 +555,10 @@
void mdp4_overlay0_done_dsi_video(struct mdp_dma_data *dma)
{
spin_lock(&mdp_spin_lock);
+ if (dsi_pipe->blt_addr == 0) {
+ spin_unlock(&mdp_spin_lock);
+ return;
+ }
dma->busy = FALSE;
mdp4_dsi_video_blt_dmap_update(dsi_pipe);
dsi_pipe->dmap_cnt++;
diff --git a/drivers/video/msm/mdp4_overlay_lcdc.c b/drivers/video/msm/mdp4_overlay_lcdc.c
index e840230..0eda69a 100644
--- a/drivers/video/msm/mdp4_overlay_lcdc.c
+++ b/drivers/video/msm/mdp4_overlay_lcdc.c
@@ -451,6 +451,10 @@
void mdp4_overlay0_done_lcdc(struct mdp_dma_data *dma)
{
spin_lock(&mdp_spin_lock);
+ if (lcdc_pipe->blt_addr == 0) {
+ spin_unlock(&mdp_spin_lock);
+ return;
+ }
dma->busy = FALSE;
mdp4_lcdc_blt_dmap_update(lcdc_pipe);
lcdc_pipe->dmap_cnt++;
diff --git a/drivers/video/msm/mdp4_util.c b/drivers/video/msm/mdp4_util.c
index 99607e7..3d78a13 100644
--- a/drivers/video/msm/mdp4_util.c
+++ b/drivers/video/msm/mdp4_util.c
@@ -419,6 +419,55 @@
spin_unlock(&mdp_spin_lock);
}
#endif
+
+#ifdef CONFIG_FB_MSM_OVERLAY
+ if (isr & INTR_OVERLAY0_DONE) {
+ mdp4_stat.intr_overlay0++;
+ dma = &dma2_data;
+ if (panel & (MDP4_PANEL_LCDC | MDP4_PANEL_DSI_VIDEO)) {
+ /* disable LCDC interrupt */
+ spin_lock(&mdp_spin_lock);
+ mdp_intr_mask &= ~INTR_OVERLAY0_DONE;
+ outp32(MDP_INTR_ENABLE, mdp_intr_mask);
+ dma->waiting = FALSE;
+ spin_unlock(&mdp_spin_lock);
+ if (panel & MDP4_PANEL_LCDC)
+ mdp4_overlay0_done_lcdc(dma);
+#ifdef CONFIG_FB_MSM_MIPI_DSI
+ else if (panel & MDP4_PANEL_DSI_VIDEO)
+ mdp4_overlay0_done_dsi_video(dma);
+#endif
+ } else { /* MDDI, DSI_CMD */
+#ifdef CONFIG_FB_MSM_MIPI_DSI
+ if (panel & MDP4_PANEL_DSI_CMD)
+ mdp4_overlay0_done_dsi_cmd(dma);
+#else
+ if (panel & MDP4_PANEL_MDDI)
+ mdp4_overlay0_done_mddi(dma);
+#endif
+ }
+ mdp_hw_cursor_done();
+ }
+ if (isr & INTR_OVERLAY1_DONE) {
+ mdp4_stat.intr_overlay1++;
+ /* disable DTV interrupt */
+ dma = &dma_e_data;
+ spin_lock(&mdp_spin_lock);
+ mdp_intr_mask &= ~INTR_OVERLAY1_DONE;
+ outp32(MDP_INTR_ENABLE, mdp_intr_mask);
+ dma->waiting = FALSE;
+ spin_unlock(&mdp_spin_lock);
+#if defined(CONFIG_FB_MSM_DTV)
+ if (panel & MDP4_PANEL_DTV)
+ mdp4_overlay1_done_dtv();
+#endif
+#if defined(CONFIG_FB_MSM_TVOUT)
+ if (panel & MDP4_PANEL_ATV)
+ mdp4_overlay1_done_atv();
+#endif
+ }
+#endif /* OVERLAY */
+
if (isr & INTR_DMA_P_DONE) {
mdp4_stat.intr_dma_p++;
dma = &dma2_data;
@@ -488,53 +537,6 @@
}
spin_unlock(&mdp_spin_lock);
}
-#ifdef CONFIG_FB_MSM_OVERLAY
- if (isr & INTR_OVERLAY0_DONE) {
- mdp4_stat.intr_overlay0++;
- dma = &dma2_data;
- if (panel & (MDP4_PANEL_LCDC | MDP4_PANEL_DSI_VIDEO)) {
- /* disable LCDC interrupt */
- spin_lock(&mdp_spin_lock);
- mdp_intr_mask &= ~INTR_OVERLAY0_DONE;
- outp32(MDP_INTR_ENABLE, mdp_intr_mask);
- dma->waiting = FALSE;
- spin_unlock(&mdp_spin_lock);
- if (panel & MDP4_PANEL_LCDC)
- mdp4_overlay0_done_lcdc(dma);
-#ifdef CONFIG_FB_MSM_MIPI_DSI
- else if (panel & MDP4_PANEL_DSI_VIDEO)
- mdp4_overlay0_done_dsi_video(dma);
-#endif
- } else { /* MDDI, DSI_CMD */
-#ifdef CONFIG_FB_MSM_MIPI_DSI
- if (panel & MDP4_PANEL_DSI_CMD)
- mdp4_overlay0_done_dsi_cmd(dma);
-#else
- if (panel & MDP4_PANEL_MDDI)
- mdp4_overlay0_done_mddi(dma);
-#endif
- }
- mdp_hw_cursor_done();
- }
- if (isr & INTR_OVERLAY1_DONE) {
- mdp4_stat.intr_overlay1++;
- /* disable DTV interrupt */
- dma = &dma_e_data;
- spin_lock(&mdp_spin_lock);
- mdp_intr_mask &= ~INTR_OVERLAY1_DONE;
- outp32(MDP_INTR_ENABLE, mdp_intr_mask);
- dma->waiting = FALSE;
- spin_unlock(&mdp_spin_lock);
-#if defined(CONFIG_FB_MSM_DTV)
- if (panel & MDP4_PANEL_DTV)
- mdp4_overlay1_done_dtv();
-#endif
-#if defined(CONFIG_FB_MSM_TVOUT)
- if (panel & MDP4_PANEL_ATV)
- mdp4_overlay1_done_atv();
-#endif
- }
-#endif /* OVERLAY */
if (isr & INTR_DMA_P_HISTOGRAM) {
isr = inpdw(MDP_DMA_P_HIST_INTR_STATUS);
mask = inpdw(MDP_DMA_P_HIST_INTR_ENABLE);
diff --git a/drivers/video/msm/mipi_chimei_wxga_pt.c b/drivers/video/msm/mipi_chimei_wxga_pt.c
index fe7035a..4729d83 100644
--- a/drivers/video/msm/mipi_chimei_wxga_pt.c
+++ b/drivers/video/msm/mipi_chimei_wxga_pt.c
@@ -168,7 +168,12 @@
pinfo->mipi.stream = false; /* dma_p */
pinfo->mipi.mdp_trigger = DSI_CMD_TRIGGER_NONE;
pinfo->mipi.dma_trigger = DSI_CMD_TRIGGER_SW;
- pinfo->mipi.fixed_packet_size = 4;
+ /*
+ * toshiba d2l chip does not need max_pkt_szie dcs cmd
+ * client reply len is directly configure through
+ * RDPKTLN register (0x0404)
+ */
+ pinfo->mipi.no_max_pkt_size = 1;
pinfo->mipi.force_clk_lane_hs = 1;
ret = mipi_tc358764_dsi2lvds_register(pinfo, MIPI_DSI_PRIM,
diff --git a/drivers/video/msm/mipi_dsi_host.c b/drivers/video/msm/mipi_dsi_host.c
index 600aac5..8d07e56 100644
--- a/drivers/video/msm/mipi_dsi_host.c
+++ b/drivers/video/msm/mipi_dsi_host.c
@@ -1159,20 +1159,22 @@
struct dsi_buf *tp, struct dsi_buf *rp,
struct dsi_cmd_desc *cmds, int rlen)
{
- int i , cnt, len, diff, pkt_size;
+ int cnt, len, diff, pkt_size;
unsigned long flag;
char cmd;
+ if (mfd->panel_info.mipi.no_max_pkt_size) {
+ /* Only support rlen = 4*n */
+ rlen += 3;
+ rlen &= 0x03;
+ }
+
len = rlen;
diff = 0;
if (len <= 2)
cnt = 4; /* short read */
- else if (mfd->panel_info.mipi.fixed_packet_size) {
- len = mfd->panel_info.mipi.fixed_packet_size;
- pkt_size = len; /* Avoid command to the device */
- cnt = (len + 6 + 3) & ~0x03; /* Add padding for align */
- } else {
+ else {
if (len > MIPI_DSI_LEN)
len = MIPI_DSI_LEN; /* 8 bytes at most */
@@ -1203,7 +1205,7 @@
dsi_mdp_busy = TRUE;
spin_unlock_irqrestore(&dsi_mdp_lock, flag);
- if (!mfd->panel_info.mipi.fixed_packet_size) {
+ if (!mfd->panel_info.mipi.no_max_pkt_size) {
/* packet size need to be set at every read */
pkt_size = len;
max_pktsize[0] = pkt_size;
@@ -1223,10 +1225,15 @@
* at RDBK_DATA register already
*/
mipi_dsi_buf_init(rp);
- mipi_dsi_cmd_dma_rx(rp, cnt);
+ if (mfd->panel_info.mipi.no_max_pkt_size) {
+ /*
+ * expect rlen = n * 4
+ * short alignement for start addr
+ */
+ rp->data += 2;
+ }
- for (i = 0; i < cnt ; i++)
- pr_debug("%s.rp->data[%d]=0x%x.\n", __func__, i, rp->data[i]);
+ mipi_dsi_cmd_dma_rx(rp, cnt);
spin_lock_irqsave(&dsi_mdp_lock, flag);
dsi_mdp_busy = FALSE;
@@ -1234,12 +1241,16 @@
complete(&dsi_mdp_comp);
spin_unlock_irqrestore(&dsi_mdp_lock, flag);
- /* Remove leading padding zeros if exist */
- for (i = 0; i < cnt ; i++)
- if (rp->data[0] == 0)
- rp->data++;
- else
- break;
+ if (mfd->panel_info.mipi.no_max_pkt_size) {
+ /*
+ * remove extra 2 bytes from previous
+ * rx transaction at shift register
+ * which was inserted during copy
+ * shift registers to rx buffer
+ * rx payload start from long alignment addr
+ */
+ rp->data += 2;
+ }
cmd = rp->data[0];
switch (cmd) {
diff --git a/drivers/video/msm/msm_fb.c b/drivers/video/msm/msm_fb.c
index b3d5573..d21910b 100644
--- a/drivers/video/msm/msm_fb.c
+++ b/drivers/video/msm/msm_fb.c
@@ -2936,6 +2936,9 @@
break;
case MSMFB_HISTOGRAM:
+ if (!mfd->panel_power_on)
+ return -EPERM;
+
if (!mfd->do_histogram)
return -ENODEV;
diff --git a/drivers/video/msm/msm_fb_panel.h b/drivers/video/msm/msm_fb_panel.h
index 4c415b6..16979b1 100644
--- a/drivers/video/msm/msm_fb_panel.h
+++ b/drivers/video/msm/msm_fb_panel.h
@@ -122,7 +122,7 @@
char dma_trigger;
uint32 dsi_pclk_rate;
/* The packet-size should not bet changed */
- char fixed_packet_size;
+ char no_max_pkt_size;
/* Clock required during LP commands */
char force_clk_lane_hs;
/* Pad width */
diff --git a/include/linux/cyttsp.h b/include/linux/cyttsp.h
index 8d69031..0e5cac7 100644
--- a/include/linux/cyttsp.h
+++ b/include/linux/cyttsp.h
@@ -87,9 +87,11 @@
#define CY_TMA300_VTG_MAX_UV 5500000
#define CY_TMA300_VTG_MIN_UV 1710000
#define CY_TMA300_CURR_24HZ_UA 17500
+#define CY_TMA300_SLEEP_CURR_UA 10
#define CY_I2C_VTG_MAX_UV 1800000
#define CY_I2C_VTG_MIN_UV 1800000
#define CY_I2C_CURR_UA 9630
+#define CY_I2C_SLEEP_CURR_UA 10
/* define for inclusion of TTSP App Update Load File
@@ -445,9 +447,10 @@
struct cyttsp_regulator {
const char *name;
- u32 min_uV;
u32 max_uV;
- u32 load_uA;
+ u32 min_uV;
+ u32 hpm_load_uA;
+ u32 lpm_load_uA;
};
struct cyttsp_platform_data {
@@ -484,6 +487,7 @@
#ifdef CY_USE_I2C_DRIVER
s32 (*init)(struct i2c_client *client);
s32 (*resume)(struct i2c_client *client);
+ s32 (*suspend)(struct i2c_client *client);
#endif
#ifdef CY_USE_SPI_DRIVER
s32 (*init)(struct spi_device *spi);
diff --git a/include/linux/ion.h b/include/linux/ion.h
index ece819d..4b7b8b7d1 100644
--- a/include/linux/ion.h
+++ b/include/linux/ion.h
@@ -57,11 +57,15 @@
ION_HEAP_SYSTEM_CONTIG_ID,
ION_HEAP_EBI_ID,
ION_HEAP_SMI_ID,
+ ION_HEAP_ADSP_ID,
+ ION_HEAP_AUDIO_ID,
};
#define ION_KMALLOC_HEAP_NAME "kmalloc"
#define ION_VMALLOC_HEAP_NAME "vmalloc"
#define ION_EBI1_HEAP_NAME "EBI1"
+#define ION_ADSP_HEAP_NAME "adsp"
+#define ION_SMI_HEAP_NAME "smi"
#define CACHED 1
#define UNCACHED 0
@@ -73,6 +77,7 @@
#define ION_IS_CACHED(__flags) ((__flags) & (1 << ION_CACHE_SHIFT))
#ifdef __KERNEL__
+#include <linux/err.h>
#include <mach/ion.h>
struct ion_device;
struct ion_heap;
@@ -118,6 +123,8 @@
struct ion_platform_heap heaps[];
};
+#ifdef CONFIG_ION
+
/**
* ion_client_create() - allocate a client and returns it
* @dev: the global ion device
@@ -269,6 +276,93 @@
* the handle to use to refer to it further.
*/
struct ion_handle *ion_import_fd(struct ion_client *client, int fd);
+
+/**
+ * ion_handle_get_flags - get the flags for a given handle
+ *
+ * @client - client who allocated the handle
+ * @handle - handle to get the flags
+ * @flags - pointer to store the flags
+ *
+ * Gets the current flags for a handle. These flags indicate various options
+ * of the buffer (caching, security, etc.)
+ */
+int ion_handle_get_flags(struct ion_client *client, struct ion_handle *handle,
+ unsigned long *flags);
+
+#else
+static inline struct ion_client *ion_client_create(struct ion_device *dev,
+ unsigned int heap_mask, const char *name)
+{
+ return ERR_PTR(-ENODEV);
+}
+
+static inline struct ion_client *msm_ion_client_create(unsigned int heap_mask,
+ const char *name)
+{
+ return ERR_PTR(-ENODEV);
+}
+
+static inline void ion_client_destroy(struct ion_client *client) { }
+
+static inline struct ion_handle *ion_alloc(struct ion_client *client,
+ size_t len, size_t align, unsigned int flags)
+{
+ return ERR_PTR(-ENODEV);
+}
+
+static inline void ion_free(struct ion_client *client,
+ struct ion_handle *handle) { }
+
+
+static inline int ion_phys(struct ion_client *client,
+ struct ion_handle *handle, ion_phys_addr_t *addr, size_t *len)
+{
+ return -ENODEV;
+}
+
+static inline void *ion_map_kernel(struct ion_client *client,
+ struct ion_handle *handle, unsigned long flags)
+{
+ return ERR_PTR(-ENODEV);
+}
+
+static inline void ion_unmap_kernel(struct ion_client *client,
+ struct ion_handle *handle) { }
+
+static inline struct scatterlist *ion_map_dma(struct ion_client *client,
+ struct ion_handle *handle, unsigned long flags)
+{
+ return ERR_PTR(-ENODEV);
+}
+
+static inline void ion_unmap_dma(struct ion_client *client,
+ struct ion_handle *handle) { }
+
+static inline struct ion_buffer *ion_share(struct ion_client *client,
+ struct ion_handle *handle)
+{
+ return ERR_PTR(-ENODEV);
+}
+
+static inline struct ion_handle *ion_import(struct ion_client *client,
+ struct ion_buffer *buffer)
+{
+ return ERR_PTR(-ENODEV);
+}
+
+static inline struct ion_handle *ion_import_fd(struct ion_client *client,
+ int fd)
+{
+ return ERR_PTR(-ENODEV);
+}
+
+static inline int ion_handle_get_flags(struct ion_client *client,
+ struct ion_handle *handle, unsigned long *flags)
+{
+ return -ENODEV;
+}
+#endif /* CONFIG_ION */
#endif /* __KERNEL__ */
/**
@@ -350,6 +444,20 @@
unsigned int offset;
unsigned int length;
};
+
+/* struct ion_flag_data - information about flags for this buffer
+ *
+ * @handle: handle to get flags from
+ * @flags: flags of this handle
+ *
+ * Takes handle as an input and outputs the flags from the handle
+ * in the flag field.
+ */
+struct ion_flag_data {
+ struct ion_handle *handle;
+ unsigned long flags;
+};
+
#define ION_IOC_MAGIC 'I'
/**
@@ -428,4 +536,13 @@
*/
#define ION_IOC_CLEAN_INV_CACHES _IOWR(ION_IOC_MAGIC, 9, \
struct ion_flush_data)
+
+/**
+ * DOC: ION_IOC_GET_FLAGS - get the flags of the handle
+ *
+ * Gets the flags of the current handle which indicate cachability,
+ * secure state etc.
+ */
+#define ION_IOC_GET_FLAGS _IOWR(ION_IOC_MAGIC, 10, \
+ struct ion_flag_data)
#endif /* _LINUX_ION_H */
diff --git a/include/linux/mfd/pm8xxx/misc.h b/include/linux/mfd/pm8xxx/misc.h
index 17ec31b..2374d11 100644
--- a/include/linux/mfd/pm8xxx/misc.h
+++ b/include/linux/mfd/pm8xxx/misc.h
@@ -28,6 +28,13 @@
int priority;
};
+enum pm8xxx_uart_path_sel {
+ UART_NONE,
+ UART_TX1_RX1,
+ UART_TX2_RX2,
+ UART_TX3_RX3,
+};
+
#if defined(CONFIG_MFD_PM8XXX_MISC) || defined(CONFIG_MFD_PM8XXX_MISC_MODULE)
/**
@@ -39,6 +46,8 @@
*/
int pm8xxx_reset_pwr_off(int reset);
+int pm8xxx_uart_gpio_mux_ctrl(enum pm8xxx_uart_path_sel uart_path_sel);
+
#else
static inline int pm8xxx_reset_pwr_off(int reset)
@@ -46,6 +55,12 @@
return -ENODEV;
}
+static inline int
+pm8xxx_uart_gpio_mux_ctrl(enum pm8xxx_uart_path_sel uart_path_sel)
+{
+ return -ENODEV;
+}
+
#endif
#endif
diff --git a/include/linux/mfd/pm8xxx/pm8921-adc.h b/include/linux/mfd/pm8xxx/pm8921-adc.h
index 2d81134..c66ae84 100644
--- a/include/linux/mfd/pm8xxx/pm8921-adc.h
+++ b/include/linux/mfd/pm8xxx/pm8921-adc.h
@@ -221,6 +221,8 @@
* @offset: Offset with respect to the actual curve
* @dy: Numerator slope to calculate the gain
* @dx: Denominator slope to calculate the gain
+ * @adc_vref: A/D word of the Voltage reference used for the channel
+ * @adc_gnd: A/D word of the Ground reference used for the channel
*
* Each ADC device has different offset and gain parameters which are computed
* to calibrate the device.
@@ -229,6 +231,8 @@
int32_t offset;
int32_t dy;
int32_t dx;
+ int32_t adc_vref;
+ int32_t adc_gnd;
};
/**
@@ -453,8 +457,8 @@
* levels once the thresholds are reached
*/
struct pm8921_adc_arb_btm_param {
- uint32_t low_thr_temp;
- uint32_t high_thr_temp;
+ int32_t low_thr_temp;
+ int32_t high_thr_temp;
uint64_t low_thr_voltage;
uint64_t high_thr_voltage;
int32_t interval;
@@ -462,8 +466,9 @@
void (*btm_cool_fn) (bool);
};
-int32_t pm8921_adc_batt_scaler(struct pm8921_adc_arb_btm_param *);
-
+int32_t pm8921_adc_batt_scaler(struct pm8921_adc_arb_btm_param *,
+ const struct pm8921_adc_properties *adc_prop,
+ const struct pm8921_adc_chan_properties *chan_prop);
/**
* struct pm8921_adc_platform_data - PM8921 ADC platform data
* @adc_prop: ADC specific parameters, voltage and channel setup
diff --git a/include/linux/mfd/pm8xxx/pm8921-charger.h b/include/linux/mfd/pm8xxx/pm8921-charger.h
index aeb88b2..73067b7 100644
--- a/include/linux/mfd/pm8xxx/pm8921-charger.h
+++ b/include/linux/mfd/pm8xxx/pm8921-charger.h
@@ -35,8 +35,10 @@
/**
* struct pm8921_charger_platform_data -
- * @safety_time: max charging time in minutes
+ * @safety_time: max charging time in minutes incl. fast and trkl
+ * valid range 4 to 512 min. PON default 120 min
* @ttrkl_time: max trckl charging time in minutes
+ * valid range 1 to 64 mins. PON default 15 min
* @update_time: how often the userland be updated of the charging (msec)
* @max_voltage: the max voltage (mV) the battery should be charged up to
* @min_voltage: the voltage (mV) where charging method switches from
diff --git a/include/linux/mfd/wcd9310/pdata.h b/include/linux/mfd/wcd9310/pdata.h
index 13d52fb..9ca6a8c 100644
--- a/include/linux/mfd/wcd9310/pdata.h
+++ b/include/linux/mfd/wcd9310/pdata.h
@@ -25,6 +25,23 @@
#define TABLA_CFILT2_SEL 0x1
#define TABLA_CFILT3_SEL 0x2
+#define MAX_AMIC_CHANNEL 7
+
+struct tabla_amic {
+ /*legacy mode, txfe_enable and txfe_buff take 7 input
+ * each bit represent the channel / TXFE number
+ * and numbered as below
+ * bit 0 = channel 1 / TXFE1_ENABLE / TXFE1_BUFF
+ * bit 1 = channel 2 / TXFE2_ENABLE / TXFE2_BUFF
+ * ...
+ * bit 7 = channel 7 / TXFE7_ENABLE / TXFE7_BUFF
+ */
+ u8 legacy_mode:MAX_AMIC_CHANNEL;
+ u8 txfe_enable:MAX_AMIC_CHANNEL;
+ u8 txfe_buff:MAX_AMIC_CHANNEL;
+ u8 use_pdata:MAX_AMIC_CHANNEL;
+};
+
/* Each micbias can be assigned to one of three cfilters
* Vbatt_min >= .15V + ldoh_v
* ldoh_v >= .15v + cfiltx_mv
@@ -50,6 +67,7 @@
int irq_base;
int num_irqs;
int reset_gpio;
+ struct tabla_amic amic_settings;
struct slim_device slimbus_slave_device;
struct tabla_micbias_setting micbias;
};
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index fd62a22..312b17b 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -218,9 +218,12 @@
int clk_requests; /* internal reference counter */
unsigned int clk_delay; /* number of MCI clk hold cycles */
bool clk_gated; /* clock gated */
- struct work_struct clk_gate_work; /* delayed clock gate */
+ struct delayed_work clk_gate_work; /* delayed clock gate */
unsigned int clk_old; /* old clock value cache */
spinlock_t clk_lock; /* lock for clk fields */
+ struct mutex clk_gate_mutex; /* mutex for clock gating */
+ struct device_attribute clkgate_delay_attr;
+ unsigned long clkgate_delay;
#endif
/* host specific block data */
diff --git a/include/linux/msm_kgsl.h b/include/linux/msm_kgsl.h
index b55cfe1..84e8564 100644
--- a/include/linux/msm_kgsl.h
+++ b/include/linux/msm_kgsl.h
@@ -41,7 +41,8 @@
enum kgsl_user_mem_type {
KGSL_USER_MEM_TYPE_PMEM = 0x00000000,
KGSL_USER_MEM_TYPE_ASHMEM = 0x00000001,
- KGSL_USER_MEM_TYPE_ADDR = 0x00000002
+ KGSL_USER_MEM_TYPE_ADDR = 0x00000002,
+ KGSL_USER_MEM_TYPE_ION = 0x00000003,
};
struct kgsl_devinfo {
diff --git a/include/linux/of.h b/include/linux/of.h
index bd716f8..6a1272c 100644
--- a/include/linux/of.h
+++ b/include/linux/of.h
@@ -253,6 +253,13 @@
return -ENOSYS;
}
+static inline const void *of_get_property(const struct device_node *node,
+ const char *name,
+ int *lenp)
+{
+ return NULL;
+}
+
#endif /* CONFIG_OF */
static inline int of_property_read_u32(const struct device_node *np,
diff --git a/include/linux/tcp.h b/include/linux/tcp.h
index e64f4c6..3cd86ea 100644
--- a/include/linux/tcp.h
+++ b/include/linux/tcp.h
@@ -68,18 +68,18 @@
#define tcp_flag_word(tp) ( ((union tcp_word_hdr *)(tp))->words [3])
-enum {
- TCP_FLAG_CWR = __cpu_to_be32(0x00800000),
- TCP_FLAG_ECE = __cpu_to_be32(0x00400000),
- TCP_FLAG_URG = __cpu_to_be32(0x00200000),
- TCP_FLAG_ACK = __cpu_to_be32(0x00100000),
- TCP_FLAG_PSH = __cpu_to_be32(0x00080000),
- TCP_FLAG_RST = __cpu_to_be32(0x00040000),
- TCP_FLAG_SYN = __cpu_to_be32(0x00020000),
- TCP_FLAG_FIN = __cpu_to_be32(0x00010000),
- TCP_RESERVED_BITS = __cpu_to_be32(0x0F000000),
- TCP_DATA_OFFSET = __cpu_to_be32(0xF0000000)
-};
+enum {
+ TCP_FLAG_CWR = __constant_htonl(0x00800000),
+ TCP_FLAG_ECE = __constant_htonl(0x00400000),
+ TCP_FLAG_URG = __constant_htonl(0x00200000),
+ TCP_FLAG_ACK = __constant_htonl(0x00100000),
+ TCP_FLAG_PSH = __constant_htonl(0x00080000),
+ TCP_FLAG_RST = __constant_htonl(0x00040000),
+ TCP_FLAG_SYN = __constant_htonl(0x00020000),
+ TCP_FLAG_FIN = __constant_htonl(0x00010000),
+ TCP_RESERVED_BITS = __constant_htonl(0x0F000000),
+ TCP_DATA_OFFSET = __constant_htonl(0xF0000000)
+};
/*
* TCP general constants
@@ -134,6 +134,7 @@
__u8 tcpi_backoff;
__u8 tcpi_options;
__u8 tcpi_snd_wscale : 4, tcpi_rcv_wscale : 4;
+ __u8 tcpi_count;
__u32 tcpi_rto;
__u32 tcpi_ato;
diff --git a/include/linux/usb/hcd.h b/include/linux/usb/hcd.h
index 0097136..b43a097 100644
--- a/include/linux/usb/hcd.h
+++ b/include/linux/usb/hcd.h
@@ -379,9 +379,18 @@
extern struct usb_hcd *usb_get_hcd(struct usb_hcd *hcd);
extern void usb_put_hcd(struct usb_hcd *hcd);
extern int usb_hcd_is_primary_hcd(struct usb_hcd *hcd);
+#ifdef CONFIG_USB
extern int usb_add_hcd(struct usb_hcd *hcd,
unsigned int irqnum, unsigned long irqflags);
extern void usb_remove_hcd(struct usb_hcd *hcd);
+#else
+static inline int
+usb_add_hcd(struct usb_hcd *hcd, unsigned int irqnum, unsigned long irqflags)
+{
+ return 0;
+}
+static inline void usb_remove_hcd(struct usb_hcd *hcd) {}
+#endif
struct platform_device;
extern void usb_hcd_platform_shutdown(struct platform_device *dev);
diff --git a/include/linux/usb/msm_hsusb.h b/include/linux/usb/msm_hsusb.h
index d776718..62d58de 100644
--- a/include/linux/usb/msm_hsusb.h
+++ b/include/linux/usb/msm_hsusb.h
@@ -240,6 +240,7 @@
struct msm_hsic_host_platform_data {
unsigned strobe;
unsigned data;
+ unsigned hub_reset;
};
#endif
diff --git a/include/media/msm_camera.h b/include/media/msm_camera.h
index 1ebbf88..fa19613 100644
--- a/include/media/msm_camera.h
+++ b/include/media/msm_camera.h
@@ -381,9 +381,11 @@
#define CMD_AXI_CFG_ZSL 43
#define CMD_AXI_CFG_SNAP_VPE 44
#define CMD_AXI_CFG_SNAP_THUMB_VPE 45
-#define CMD_CONFIG_PING_ADDR 46
-#define CMD_CONFIG_PONG_ADDR 47
-#define CMD_CONFIG_FREE_BUF_ADDR 48
+#define CMD_AXI_CFG_VIDEO_ALL_CHNLS 46
+#define CMD_AXI_CFG_ZSL_ALL_CHNLS 47
+#define CMD_CONFIG_PING_ADDR 48
+#define CMD_CONFIG_PONG_ADDR 49
+#define CMD_CONFIG_FREE_BUF_ADDR 50
/* vfe config command: config command(from config thread)*/
struct msm_vfe_cfg_cmd {
@@ -469,7 +471,9 @@
#define OUTPUT_1_AND_CAMIF_TO_AXI_VIA_OUTPUT_2 5
#define OUTPUT_2_AND_CAMIF_TO_AXI_VIA_OUTPUT_1 6
#define OUTPUT_1_2_AND_3 7
-#define LAST_AXI_OUTPUT_MODE_ENUM = OUTPUT_1_2_AND_3 7
+#define OUTPUT_ALL_CHNLS 8
+#define OUTPUT_ZSL_ALL_CHNLS 9
+#define LAST_AXI_OUTPUT_MODE_ENUM OUTPUT_ZSL_ALL_CHNLS
#define MSM_FRAME_PREV_1 0
#define MSM_FRAME_PREV_2 1
@@ -726,6 +730,89 @@
#define CAMERA_EFFECT_NEON 11
#define CAMERA_EFFECT_MAX 12
+/* QRD */
+#define CAMERA_EFFECT_BW 10
+#define CAMERA_EFFECT_BLUISH 12
+#define CAMERA_EFFECT_REDDISH 13
+#define CAMERA_EFFECT_GREENISH 14
+
+/* QRD */
+#define CAMERA_ANTIBANDING_OFF 0
+#define CAMERA_ANTIBANDING_50HZ 2
+#define CAMERA_ANTIBANDING_60HZ 1
+#define CAMERA_ANTIBANDING_AUTO 3
+
+#define CAMERA_CONTRAST_LV0 0
+#define CAMERA_CONTRAST_LV1 1
+#define CAMERA_CONTRAST_LV2 2
+#define CAMERA_CONTRAST_LV3 3
+#define CAMERA_CONTRAST_LV4 4
+#define CAMERA_CONTRAST_LV5 5
+#define CAMERA_CONTRAST_LV6 6
+#define CAMERA_CONTRAST_LV7 7
+#define CAMERA_CONTRAST_LV8 8
+#define CAMERA_CONTRAST_LV9 9
+
+#define CAMERA_BRIGHTNESS_LV0 0
+#define CAMERA_BRIGHTNESS_LV1 1
+#define CAMERA_BRIGHTNESS_LV2 2
+#define CAMERA_BRIGHTNESS_LV3 3
+#define CAMERA_BRIGHTNESS_LV4 4
+#define CAMERA_BRIGHTNESS_LV5 5
+#define CAMERA_BRIGHTNESS_LV6 6
+#define CAMERA_BRIGHTNESS_LV7 7
+#define CAMERA_BRIGHTNESS_LV8 8
+
+
+#define CAMERA_SATURATION_LV0 0
+#define CAMERA_SATURATION_LV1 1
+#define CAMERA_SATURATION_LV2 2
+#define CAMERA_SATURATION_LV3 3
+#define CAMERA_SATURATION_LV4 4
+#define CAMERA_SATURATION_LV5 5
+#define CAMERA_SATURATION_LV6 6
+#define CAMERA_SATURATION_LV7 7
+#define CAMERA_SATURATION_LV8 8
+
+#define CAMERA_SHARPNESS_LV0 0
+#define CAMERA_SHARPNESS_LV1 3
+#define CAMERA_SHARPNESS_LV2 6
+#define CAMERA_SHARPNESS_LV3 9
+#define CAMERA_SHARPNESS_LV4 12
+#define CAMERA_SHARPNESS_LV5 15
+#define CAMERA_SHARPNESS_LV6 18
+#define CAMERA_SHARPNESS_LV7 21
+#define CAMERA_SHARPNESS_LV8 24
+#define CAMERA_SHARPNESS_LV9 27
+#define CAMERA_SHARPNESS_LV10 30
+
+#define CAMERA_SETAE_AVERAGE 0
+#define CAMERA_SETAE_CENWEIGHT 1
+
+#define CFG_SET_SATURATION 30
+#define CFG_SET_SHARPNESS 31
+#define CFG_SET_TOUCHAEC 32
+#define CFG_SET_AUTO_FOCUS 33
+#define CFG_SET_AUTOFLASH 34
+/* QRD */
+#define CFG_SET_EXPOSURE_COMPENSATION 35
+
+#define CAMERA_WB_AUTO 1 /* This list must match aeecamera.h */
+#define CAMERA_WB_CUSTOM 2
+#define CAMERA_WB_INCANDESCENT 3
+#define CAMERA_WB_FLUORESCENT 4
+#define CAMERA_WB_DAYLIGHT 5
+#define CAMERA_WB_CLOUDY_DAYLIGHT 6
+#define CAMERA_WB_TWILIGHT 7
+#define CAMERA_WB_SHADE 8
+
+#define CAMERA_EXPOSURE_COMPENSATION_LV0 12
+#define CAMERA_EXPOSURE_COMPENSATION_LV1 6
+#define CAMERA_EXPOSURE_COMPENSATION_LV2 0
+#define CAMERA_EXPOSURE_COMPENSATION_LV3 -6
+#define CAMERA_EXPOSURE_COMPENSATION_LV4 -12
+
+
struct sensor_pict_fps {
uint16_t prevfps;
uint16_t pictfps;
@@ -836,6 +923,16 @@
uint16_t index;
};
+struct mirror_flip {
+ int32_t x_mirror;
+ int32_t y_flip;
+};
+
+struct cord {
+ uint32_t x;
+ uint32_t y;
+};
+
struct sensor_cfg_data {
int cfgtype;
int mode;
@@ -861,6 +958,18 @@
struct sensor_calib_data calib_info;
struct sensor_output_info_t output_info;
struct sensor_eeprom_data_t eeprom_data;
+ /* QRD */
+ uint16_t antibanding;
+ uint8_t contrast;
+ uint8_t saturation;
+ uint8_t sharpness;
+ int8_t brightness;
+ int ae_mode;
+ uint8_t wb_val;
+ int8_t exp_compensation;
+ struct cord aec_cord;
+ int is_autoflash;
+ struct mirror_flip mirror_flip;
} cfg;
};
diff --git a/include/media/msm_isp.h b/include/media/msm_isp.h
index b7fd30f..b4e1981 100644
--- a/include/media/msm_isp.h
+++ b/include/media/msm_isp.h
@@ -165,6 +165,13 @@
#define VFE_CMD_CLF_CHROMA_UPDATE 119
#define VFE_CMD_PCA_ROLL_OFF_CFG 120
#define VFE_CMD_PCA_ROLL_OFF_UPDATE 121
+#define VFE_CMD_GET_REG_DUMP 122
+#define VFE_CMD_GET_LINEARIZATON_TABLE 123
+#define VFE_CMD_GET_MESH_ROLLOFF_TABLE 124
+#define VFE_CMD_GET_PCA_ROLLOFF_TABLE 125
+#define VFE_CMD_GET_RGB_G_TABLE 126
+#define VFE_CMD_GET_LA_TABLE 127
+#define VFE_CMD_DEMOSAICV3_UPDATE 128
struct msm_isp_cmd {
int32_t id;
diff --git a/include/media/radio-iris.h b/include/media/radio-iris.h
index 359668b..d9687ba 100644
--- a/include/media/radio-iris.h
+++ b/include/media/radio-iris.h
@@ -128,6 +128,7 @@
#define HCI_OCF_FM_RDS_GRP_PROCESS 0x0013
#define HCI_OCF_FM_EN_WAN_AVD_CTRL 0x0014
#define HCI_OCF_FM_EN_NOTCH_CTRL 0x0015
+#define HCI_OCF_FM_SET_EVENT_MASK 0x0016
/* HCI trans control commans opcode*/
#define HCI_OCF_FM_ENABLE_TRANS_REQ 0x0001
@@ -145,6 +146,7 @@
#define HCI_OCF_FM_RESET 0x0004
#define HCI_OCF_FM_GET_FEATURE_LIST 0x0005
#define HCI_OCF_FM_DO_CALIBRATION 0x0006
+#define HCI_OCF_FM_SET_CALIBRATION 0x0007
/*HCI Status parameters commands*/
#define HCI_OCF_FM_READ_GRP_COUNTERS 0x0001
@@ -546,9 +548,12 @@
V4L2_CID_PRIVATE_IRIS_TX_TONE,
V4L2_CID_PRIVATE_IRIS_RDS_GRP_COUNTERS,
V4L2_CID_PRIVATE_IRIS_SET_NOTCH_FILTER,/*0x8000028*/
+ /*0x8000029 is used for tavarua specific ioctl*/
+ V4L2_CID_PRIVATE_IRIS_DO_CALIBRATION = 0x800002a,
V4L2_CID_PRIVATE_IRIS_READ_DEFAULT = 0x00980928,/*using private CIDs
under userclass*/
V4L2_CID_PRIVATE_IRIS_WRITE_DEFAULT,
+ V4L2_CID_PRIVATE_IRIS_SET_CALIBRATION,
};
@@ -616,6 +621,7 @@
IRIS_BUF_SSBI_PEEK,
IRIS_BUF_RDS_CNTRS,
IRIS_BUF_RD_DEFAULT,
+ IRIS_BUF_CAL_DATA,
IRIS_BUF_MAX
};
@@ -712,7 +718,33 @@
#define RIVA_PEEK_PARAM 0x6
#define RIVA_PEEK_LEN_OFSET 0x6
#define SSBI_PEEK_LEN 0x01
+/*Calibration data*/
+#define PROCS_CALIB_MODE 1
+#define PROCS_CALIB_SIZE 23
+#define DC_CALIB_MODE 2
+#define DC_CALIB_SIZE 48
+#define RSB_CALIB_MODE 3
+#define RSB_CALIB_SIZE 4
+#define CALIB_DATA_OFSET 2
+#define CALIB_MODE_OFSET 1
+#define MAX_CALIB_SIZE 75
+struct hci_fm_set_cal_req {
+ __u8 mode;
+ /*Max calibration data size*/
+ __u8 data[MAX_CALIB_SIZE];
+} __packed;
+struct hci_cc_do_calibration_rsp {
+ __u8 status;
+ __u8 mode;
+ __u8 data[MAX_CALIB_SIZE];
+} __packed;
+
+/* Low Power mode*/
+#define SIG_LEVEL_INTR (1 << 0)
+#define RDS_SYNC_INTR (1 << 1)
+#define AUDIO_CTRL_INTR (1 << 2)
+#define AF_JUMP_ENABLE (1 << 4)
int hci_def_data_read(struct hci_fm_def_data_rd_req *arg,
struct radio_hci_dev *hdev);
int hci_def_data_write(struct hci_fm_def_data_wr_req *arg,
diff --git a/include/net/bluetooth/bluetooth.h b/include/net/bluetooth/bluetooth.h
index 643a497..155c6fd 100644
--- a/include/net/bluetooth/bluetooth.h
+++ b/include/net/bluetooth/bluetooth.h
@@ -66,12 +66,12 @@
#define BT_DEFER_SETUP 7
-#define BT_POWER 8
+#define BT_POWER 9
struct bt_power {
__u8 force_active;
};
-#define BT_AMP_POLICY 9
+#define BT_AMP_POLICY 10
/* Require BR/EDR (default policy)
* AMP controllers cannot be used
@@ -80,6 +80,13 @@
*/
#define BT_AMP_POLICY_REQUIRE_BR_EDR 0
+/* Prefer BR/EDR
+ * Allow use of AMP controllers
+ * If the L2CAP channel is currently on AMP, move it to BR/EDR
+ * Channel move requests from the remote device are allowed
+ */
+#define BT_AMP_POLICY_PREFER_BR_EDR 1
+
/* Prefer AMP
* Allow use of AMP controllers
* If the L2CAP channel is currently on BR/EDR and AMP controller
@@ -89,14 +96,7 @@
* and configure the channel directly on an AMP controller rather
* than BR/EDR
*/
-#define BT_AMP_POLICY_PREFER_AMP 1
-
-/* Prefer BR/EDR
- * Allow use of AMP controllers
- * If the L2CAP channel is currently on AMP, move it to BR/EDR
- * Channel move requests from the remote device are allowed
- */
-#define BT_AMP_POLICY_PREFER_BR_EDR 2
+#define BT_AMP_POLICY_PREFER_AMP 2
#define BT_INFO(fmt, arg...) printk(KERN_INFO "Bluetooth: " fmt "\n" , ## arg)
#define BT_ERR(fmt, arg...) printk(KERN_ERR "%s: " fmt "\n" , __func__ , ## arg)
diff --git a/include/net/bluetooth/hci.h b/include/net/bluetooth/hci.h
index b67803a..744eb72 100644
--- a/include/net/bluetooth/hci.h
+++ b/include/net/bluetooth/hci.h
@@ -124,7 +124,7 @@
#define HCI_PAIRING_TIMEOUT (60000) /* 60 seconds */
#define HCI_IDLE_TIMEOUT (6000) /* 6 seconds */
#define HCI_INIT_TIMEOUT (10000) /* 10 seconds */
-#define HCI_CMD_TIMEOUT (1000) /* 1 seconds */
+#define HCI_CMD_TIMEOUT (5000) /* 5 seconds */
/* HCI data types */
#define HCI_COMMAND_PKT 0x01
diff --git a/include/net/bluetooth/hci_core.h b/include/net/bluetooth/hci_core.h
index d0da174..74e14fb 100644
--- a/include/net/bluetooth/hci_core.h
+++ b/include/net/bluetooth/hci_core.h
@@ -91,7 +91,8 @@
struct link_key_data {
bdaddr_t bdaddr;
- u8 type;
+ u8 addr_type;
+ u8 key_type;
u8 val[16];
u8 pin_len;
u8 auth;
@@ -102,7 +103,8 @@
struct link_key {
struct list_head list;
bdaddr_t bdaddr;
- u8 type;
+ u8 addr_type;
+ u8 key_type;
u8 val[16];
u8 pin_len;
u8 auth;
@@ -689,7 +691,7 @@
struct link_key *hci_find_ltk(struct hci_dev *hdev, __le16 ediv, u8 rand[8]);
struct link_key *hci_find_link_key_type(struct hci_dev *hdev,
bdaddr_t *bdaddr, u8 type);
-int hci_add_ltk(struct hci_dev *hdev, int new_key, bdaddr_t *bdaddr,
+int hci_add_ltk(struct hci_dev *hdev, int new_key, bdaddr_t *bdaddr, u8 type,
u8 auth, u8 key_size, __le16 ediv, u8 rand[8], u8 ltk[16]);
int hci_remove_link_key(struct hci_dev *hdev, bdaddr_t *bdaddr);
diff --git a/include/net/bluetooth/mgmt.h b/include/net/bluetooth/mgmt.h
index 208c157..ce7ecf1 100644
--- a/include/net/bluetooth/mgmt.h
+++ b/include/net/bluetooth/mgmt.h
@@ -100,7 +100,8 @@
struct mgmt_key_info {
bdaddr_t bdaddr;
- u8 type;
+ u8 addr_type;
+ u8 key_type;
u8 val[16];
u8 pin_len;
u8 auth;
@@ -218,6 +219,15 @@
#define MGMT_OP_SET_LIMIT_DISCOVERABLE 0x001F
+#define MGMT_OP_SET_CONNECTION_PARAMS 0x0020
+struct mgmt_cp_set_connection_params {
+ bdaddr_t bdaddr;
+ __le16 interval_min;
+ __le16 interval_max;
+ __le16 slave_latency;
+ __le16 timeout_multiplier;
+} __packed;
+
#define MGMT_EV_CMD_COMPLETE 0x0001
struct mgmt_ev_cmd_complete {
__le16 opcode;
diff --git a/include/sound/apr_audio.h b/include/sound/apr_audio.h
index d2a7dba..aff1ce8 100644
--- a/include/sound/apr_audio.h
+++ b/include/sound/apr_audio.h
@@ -768,6 +768,11 @@
u16 dtx_mode;
};
+struct asm_amrwb_read_cfg {
+ u16 mode;
+ u16 dtx_mode;
+};
+
struct asm_evrc_read_cfg {
u16 max_rate;
u16 min_rate;
@@ -819,6 +824,7 @@
struct asm_evrc_read_cfg evrc;
struct asm_qcelp13_read_cfg qcelp13;
struct asm_sbc_read_cfg sbc;
+ struct asm_amrwb_read_cfg amrwb;
} __attribute__((packed)) cfg;
};
@@ -849,6 +855,7 @@
#define MP3 0x00010BE9
#define MPEG4_AAC 0x00010BEA
#define AMRNB_FS 0x00010BEB
+#define AMRWB_FS 0x00010BEC
#define V13K_FS 0x00010BED
#define EVRC_FS 0x00010BEE
#define EVRCB_FS 0x00010BEF
diff --git a/include/sound/q6asm.h b/include/sound/q6asm.h
index fc7e521..f146684 100644
--- a/include/sound/q6asm.h
+++ b/include/sound/q6asm.h
@@ -236,6 +236,9 @@
int q6asm_enc_cfg_blk_amrnb(struct audio_client *ac, uint32_t frames_per_buf,
uint16_t band_mode, uint16_t dtx_enable);
+int q6asm_enc_cfg_blk_amrwb(struct audio_client *ac, uint32_t frames_per_buf,
+ uint16_t band_mode, uint16_t dtx_enable);
+
int q6asm_media_format_block_pcm(struct audio_client *ac,
uint32_t rate, uint32_t channels);
@@ -281,4 +284,8 @@
int q6asm_get_apr_service_id(int session_id);
#endif
+/* Common format block without any payload
+*/
+int q6asm_media_format_block(struct audio_client *ac, uint32_t format);
+
#endif /* __Q6_ASM_H__ */
diff --git a/kernel/power/wakelock.c b/kernel/power/wakelock.c
index e9f49b5..b257424 100644
--- a/kernel/power/wakelock.c
+++ b/kernel/power/wakelock.c
@@ -19,6 +19,7 @@
#include <linux/suspend.h>
#include <linux/syscalls.h> /* sys_sync */
#include <linux/wakelock.h>
+#include <linux/syscore_ops.h>
#ifdef CONFIG_WAKELOCK_STAT
#include <linux/proc_fs.h>
#endif
@@ -391,15 +392,8 @@
return ret;
}
-static int power_resume_early(struct device *dev)
-{
- msm_suspend_check_done = 0;
- return 0;
-}
-
static struct dev_pm_ops power_driver_pm_ops = {
.suspend_noirq = power_suspend_late,
- .resume_noirq = power_resume_early,
};
static struct platform_driver power_driver = {
@@ -410,6 +404,14 @@
.name = "power",
};
+static void power_resume_early(void)
+{
+ msm_suspend_check_done = 0;
+}
+static struct syscore_ops wakelock_syscore_ops = {
+ .resume = power_resume_early,
+};
+
void wake_lock_init(struct wake_lock *lock, int type, const char *name)
{
unsigned long irqflags = 0;
@@ -661,6 +663,7 @@
proc_create("wakelocks", S_IRUGO, NULL, &wakelock_stats_fops);
#endif
+ register_syscore_ops(&wakelock_syscore_ops);
return 0;
err_suspend_work_queue:
diff --git a/mm/memory_hotplug.c b/mm/memory_hotplug.c
index 4a73744..8487c49 100644
--- a/mm/memory_hotplug.c
+++ b/mm/memory_hotplug.c
@@ -617,9 +617,9 @@
BUG_ON(!res);
ret = arch_physical_remove_memory(start, size);
- if (ret) {
+ if (!ret) {
kfree(res);
- return ret;
+ return 0;
}
res->name = "System RAM";
@@ -628,8 +628,11 @@
res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
res_old = locate_resource(&iomem_resource, res);
- if (res_old)
- release_memory_resource(res_old);
+ if (res_old) {
+ release_resource(res_old);
+ if (PageSlab(virt_to_head_page(res_old)))
+ kfree(res_old);
+ }
kfree(res);
return ret;
diff --git a/mm/page_alloc.c b/mm/page_alloc.c
index fef8dc3..18f239c 100644
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
@@ -4652,6 +4652,9 @@
unsigned long totalpages = early_calculate_totalpages();
int usable_nodes = nodes_weight(node_states[N_HIGH_MEMORY]);
+#ifdef CONFIG_FIX_MOVABLE_ZONE
+ required_movablecore = movable_reserved_size >> PAGE_SHIFT;
+#endif
/*
* If movablecore was specified, calculate what size of
* kernelcore that corresponds so that memory usable for
diff --git a/mm/slub.c b/mm/slub.c
index 35f351f..adf609e 100644
--- a/mm/slub.c
+++ b/mm/slub.c
@@ -557,10 +557,10 @@
memset(p + s->objsize, val, s->inuse - s->objsize);
}
-static u8 *check_bytes(u8 *start, unsigned int value, unsigned int bytes)
+static u8 *check_bytes8(u8 *start, u8 value, unsigned int bytes)
{
while (bytes) {
- if (*start != (u8)value)
+ if (*start != value)
return start;
start++;
bytes--;
@@ -568,6 +568,38 @@
return NULL;
}
+static u8 *check_bytes(u8 *start, u8 value, unsigned int bytes)
+{
+ u64 value64;
+ unsigned int words, prefix;
+
+ if (bytes <= 16)
+ return check_bytes8(start, value, bytes);
+
+ value64 = value | value << 8 | value << 16 | value << 24;
+ value64 = (value64 & 0xffffffff) | value64 << 32;
+ prefix = 8 - ((unsigned long)start) % 8;
+
+ if (prefix) {
+ u8 *r = check_bytes8(start, value, prefix);
+ if (r)
+ return r;
+ start += prefix;
+ bytes -= prefix;
+ }
+
+ words = bytes / 8;
+
+ while (words) {
+ if (*(u64 *)start != value64)
+ return check_bytes8(start, value, 8);
+ start += 8;
+ words--;
+ }
+
+ return check_bytes8(start, value, bytes % 8);
+}
+
static void restore_bytes(struct kmem_cache *s, char *message, u8 data,
void *from, void *to)
{
diff --git a/net/bluetooth/hci_conn.c b/net/bluetooth/hci_conn.c
index 733e9d2..5e67829 100644
--- a/net/bluetooth/hci_conn.c
+++ b/net/bluetooth/hci_conn.c
@@ -631,6 +631,7 @@
if (type == LE_LINK) {
struct adv_entry *entry;
+ struct link_key *key;
le = hci_conn_hash_lookup_ba(hdev, LE_LINK, dst);
if (le) {
@@ -638,11 +639,17 @@
return le;
}
- entry = hci_find_adv_entry(hdev, dst);
- if (!entry)
- le = hci_le_conn_add(hdev, dst, 0);
- else
- le = hci_le_conn_add(hdev, dst, entry->bdaddr_type);
+ key = hci_find_link_key_type(hdev, dst, KEY_TYPE_LTK);
+ if (!key) {
+ entry = hci_find_adv_entry(hdev, dst);
+ if (entry)
+ le = hci_le_conn_add(hdev, dst,
+ entry->bdaddr_type);
+ else
+ le = hci_le_conn_add(hdev, dst, 0);
+ } else {
+ le = hci_le_conn_add(hdev, dst, key->addr_type);
+ }
if (!le)
return ERR_PTR(-ENOMEM);
diff --git a/net/bluetooth/hci_core.c b/net/bluetooth/hci_core.c
index 699284a..b7bbe02 100644
--- a/net/bluetooth/hci_core.c
+++ b/net/bluetooth/hci_core.c
@@ -193,6 +193,7 @@
/* Reset device */
set_bit(HCI_RESET, &hdev->flags);
+ memset(&hdev->features, 0, sizeof(hdev->features));
hci_send_cmd(hdev, HCI_OP_RESET, 0, NULL);
}
@@ -1065,7 +1066,7 @@
k = list_entry(p, struct link_key, list);
- if (k->type != KEY_TYPE_LTK)
+ if (k->key_type != KEY_TYPE_LTK)
continue;
if (k->dlen != sizeof(*id))
@@ -1091,7 +1092,7 @@
k = list_entry(p, struct link_key, list);
- if ((k->type == type) && (bacmp(bdaddr, &k->bdaddr) == 0))
+ if ((k->key_type == type) && (bacmp(bdaddr, &k->bdaddr) == 0))
return k;
}
@@ -1109,7 +1110,7 @@
old_key = hci_find_link_key(hdev, bdaddr);
if (old_key) {
- old_key_type = old_key->type;
+ old_key_type = old_key->key_type;
key = old_key;
} else {
old_key_type = 0xff;
@@ -1124,7 +1125,7 @@
bacpy(&key->bdaddr, bdaddr);
memcpy(key->val, val, 16);
key->auth = 0x01;
- key->type = type;
+ key->key_type = type;
key->pin_len = pin_len;
conn = hci_conn_hash_lookup_ba(hdev, ACL_LINK, bdaddr);
@@ -1142,8 +1143,8 @@
if (conn) {
if ((conn->remote_auth > 0x01) ||
(conn->auth_initiator && conn->auth_type > 0x01) ||
- (key->type < 0x03) ||
- (key->type == 0x06 && old_key_type != 0xff))
+ (key->key_type < 0x03) ||
+ (key->key_type == 0x06 && old_key_type != 0xff))
bonded = 1;
}
@@ -1151,19 +1152,20 @@
mgmt_new_key(hdev->id, key, bonded);
if (type == 0x06)
- key->type = old_key_type;
+ key->key_type = old_key_type;
return 0;
}
int hci_add_ltk(struct hci_dev *hdev, int new_key, bdaddr_t *bdaddr,
- u8 key_size, u8 auth, __le16 ediv, u8 rand[8],
- u8 ltk[16])
+ u8 addr_type, u8 key_size, u8 auth,
+ __le16 ediv, u8 rand[8], u8 ltk[16])
{
struct link_key *key, *old_key;
struct key_master_id *id;
- BT_DBG("%s Auth: %2.2X addr %s", hdev->name, auth, batostr(bdaddr));
+ BT_DBG("%s Auth: %2.2X addr %s type: %d", hdev->name, auth,
+ batostr(bdaddr), addr_type);
old_key = hci_find_link_key_type(hdev, bdaddr, KEY_TYPE_LTK);
if (old_key) {
@@ -1178,8 +1180,9 @@
key->dlen = sizeof(*id);
bacpy(&key->bdaddr, bdaddr);
+ key->addr_type = addr_type;
memcpy(key->val, ltk, sizeof(key->val));
- key->type = KEY_TYPE_LTK;
+ key->key_type = KEY_TYPE_LTK;
key->pin_len = key_size;
key->auth = auth;
diff --git a/net/bluetooth/hci_event.c b/net/bluetooth/hci_event.c
index da8b780..a6e3485 100644
--- a/net/bluetooth/hci_event.c
+++ b/net/bluetooth/hci_event.c
@@ -224,13 +224,11 @@
if (!sent)
return;
+ if (!status)
+ memcpy(hdev->dev_name, sent, HCI_MAX_NAME_LENGTH);
+
if (test_bit(HCI_MGMT, &hdev->flags))
mgmt_set_local_name_complete(hdev->id, sent, status);
-
- if (status)
- return;
-
- memcpy(hdev->dev_name, sent, HCI_MAX_NAME_LENGTH);
}
static void hci_cc_read_local_name(struct hci_dev *hdev, struct sk_buff *skb)
@@ -2486,10 +2484,10 @@
goto not_found;
}
- BT_DBG("%s found key type %u for %s", hdev->name, key->type,
+ BT_DBG("%s found key type %u for %s", hdev->name, key->key_type,
batostr(&ev->bdaddr));
- if (!test_bit(HCI_DEBUG_KEYS, &hdev->flags) && key->type == 0x03) {
+ if (!test_bit(HCI_DEBUG_KEYS, &hdev->flags) && key->key_type == 0x03) {
BT_DBG("%s ignoring debug key", hdev->name);
goto not_found;
}
@@ -2507,7 +2505,7 @@
goto not_found;
}
- if (key->type == 0x04 && conn && conn->auth_type != 0xff &&
+ if (key->key_type == 0x04 && conn && conn->auth_type != 0xff &&
(conn->auth_type & 0x01)) {
BT_DBG("%s ignoring unauthenticated key", hdev->name);
goto not_found;
diff --git a/net/bluetooth/l2cap_core.c b/net/bluetooth/l2cap_core.c
index 7ca920e..abc3ef7 100644
--- a/net/bluetooth/l2cap_core.c
+++ b/net/bluetooth/l2cap_core.c
@@ -1345,16 +1345,21 @@
lock_sock(sk);
l2cap_ertm_send(sk);
release_sock(sk);
+ sock_put(sk);
}
static void l2cap_skb_destructor(struct sk_buff *skb)
{
struct sock *sk = skb->sk;
int queued;
+ int keep_sk = 0;
queued = atomic_sub_return(1, &l2cap_pi(sk)->ertm_queued);
if (queued < L2CAP_MIN_ERTM_QUEUED)
- queue_work(_l2cap_wq, &l2cap_pi(sk)->tx_work);
+ keep_sk = queue_work(_l2cap_wq, &l2cap_pi(sk)->tx_work);
+
+ if (!keep_sk)
+ sock_put(sk);
}
void l2cap_do_send(struct sock *sk, struct sk_buff *skb)
@@ -1440,6 +1445,7 @@
*/
tx_skb = skb_clone(skb, GFP_ATOMIC);
+ sock_hold(sk);
tx_skb->sk = sk;
tx_skb->destructor = l2cap_skb_destructor;
atomic_inc(&pi->ertm_queued);
@@ -2604,6 +2610,7 @@
if (l2cap_pi(sk)->amp_move_state != L2CAP_AMP_STATE_RESEGMENT) {
release_sock(sk);
+ sock_put(sk);
return;
}
@@ -2622,6 +2629,7 @@
l2cap_ertm_send(sk);
release_sock(sk);
+ sock_put(sk);
}
static int l2cap_setup_resegment(struct sock *sk)
@@ -2638,10 +2646,12 @@
return -ENOMEM;
INIT_WORK(&seg_work->work, l2cap_resegment_worker);
+ sock_hold(sk);
seg_work->sk = sk;
if (!queue_work(_l2cap_wq, &seg_work->work)) {
kfree(seg_work);
+ sock_put(sk);
return -ENOMEM;
}
@@ -5815,6 +5825,7 @@
if (pi->fcs == L2CAP_FCS_CRC16)
apply_fcs(tx_skb);
+ sock_hold(sk);
tx_skb->sk = sk;
tx_skb->destructor = l2cap_skb_destructor;
atomic_inc(&pi->ertm_queued);
diff --git a/net/bluetooth/l2cap_sock.c b/net/bluetooth/l2cap_sock.c
index 361c984..9beea74 100644
--- a/net/bluetooth/l2cap_sock.c
+++ b/net/bluetooth/l2cap_sock.c
@@ -750,7 +750,7 @@
break;
}
- if ((opt > BT_AMP_POLICY_PREFER_BR_EDR) ||
+ if ((opt > BT_AMP_POLICY_PREFER_AMP) ||
((l2cap_pi(sk)->mode != L2CAP_MODE_ERTM) &&
(l2cap_pi(sk)->mode != L2CAP_MODE_STREAMING))) {
err = -EINVAL;
diff --git a/net/bluetooth/mgmt.c b/net/bluetooth/mgmt.c
index ea72708..094bfdb 100644
--- a/net/bluetooth/mgmt.c
+++ b/net/bluetooth/mgmt.c
@@ -1099,19 +1099,20 @@
i += sizeof(*key);
- if (key->type == KEY_TYPE_LTK) {
+ if (key->key_type == KEY_TYPE_LTK) {
struct key_master_id *id = (void *) key->data;
if (key->dlen != sizeof(struct key_master_id))
continue;
- hci_add_ltk(hdev, 0, &key->bdaddr, key->pin_len,
- key->auth, id->ediv, id->rand, key->val);
+ hci_add_ltk(hdev, 0, &key->bdaddr, key->addr_type,
+ key->pin_len, key->auth, id->ediv,
+ id->rand, key->val);
continue;
}
- hci_add_link_key(hdev, 0, &key->bdaddr, key->val, key->type,
+ hci_add_link_key(hdev, 0, &key->bdaddr, key->val, key->key_type,
key->pin_len);
}
@@ -1698,6 +1699,48 @@
return err;
}
+static int set_connection_params(struct sock *sk, u16 index,
+ unsigned char *data, u16 len)
+{
+ struct mgmt_cp_set_connection_params *cp = (void *) data;
+ struct hci_dev *hdev;
+ struct hci_conn *conn;
+ int err;
+
+ BT_DBG("");
+
+ if (len != sizeof(*cp))
+ return cmd_status(sk, index, MGMT_OP_SET_CONNECTION_PARAMS,
+ EINVAL);
+
+ hdev = hci_dev_get(index);
+ if (!hdev)
+ return cmd_status(sk, index, MGMT_OP_SET_CONNECTION_PARAMS,
+ ENODEV);
+
+ hci_dev_lock(hdev);
+
+ conn = hci_conn_hash_lookup_ba(hdev, LE_LINK, &cp->bdaddr);
+ if (!conn) {
+ err = cmd_status(sk, index, MGMT_OP_SET_CONNECTION_PARAMS,
+ ENOTCONN);
+ goto failed;
+ }
+
+ hci_le_conn_update(conn, le16_to_cpu(cp->interval_min),
+ le16_to_cpu(cp->interval_max),
+ le16_to_cpu(cp->slave_latency),
+ le16_to_cpu(cp->timeout_multiplier));
+
+ err = cmd_status(sk, index, MGMT_OP_SET_CONNECTION_PARAMS, 0);
+
+failed:
+ hci_dev_unlock(hdev);
+ hci_dev_put(hdev);
+
+ return err;
+}
+
static int set_local_name(struct sock *sk, u16 index, unsigned char *data,
u16 len)
{
@@ -2261,6 +2304,9 @@
case MGMT_OP_RESOLVE_NAME:
err = resolve_name(sk, index, buf + sizeof(*hdr), len);
break;
+ case MGMT_OP_SET_CONNECTION_PARAMS:
+ err = set_connection_params(sk, index, buf + sizeof(*hdr), len);
+ break;
case MGMT_OP_READ_LOCAL_OOB_DATA:
err = read_local_oob_data(sk, index);
break;
@@ -2393,7 +2439,8 @@
return -ENOMEM;
bacpy(&ev->key.bdaddr, &key->bdaddr);
- ev->key.type = key->type;
+ ev->key.addr_type = key->addr_type;
+ ev->key.key_type = key->key_type;
memcpy(ev->key.val, key->val, 16);
ev->key.pin_len = key->pin_len;
ev->key.auth = key->auth;
diff --git a/net/bluetooth/smp.c b/net/bluetooth/smp.c
index 94d0f06..a88f4a5 100644
--- a/net/bluetooth/smp.c
+++ b/net/bluetooth/smp.c
@@ -31,6 +31,11 @@
#define SMP_TIMEOUT 30000 /* 30 seconds */
+#define SMP_MIN_CONN_INTERVAL 40 /* 50ms (40 * 1.25ms) */
+#define SMP_MAX_CONN_INTERVAL 56 /* 70ms (56 * 1.25ms) */
+#define SMP_MAX_CONN_LATENCY 0 /* 0ms (0 * 1.25ms) */
+#define SMP_SUPERVISION_TIMEOUT 500 /* 5 seconds (500 * 10ms) */
+
#ifndef FALSE
#define FALSE 0
#define TRUE (!FALSE)
@@ -637,13 +642,35 @@
memset(stk + hcon->smp_key_size, 0,
SMP_MAX_ENC_KEY_SIZE - hcon->smp_key_size);
- hci_add_ltk(conn->hcon->hdev, 0, conn->dst, hcon->smp_key_size,
- hcon->auth, ediv, rand, stk);
+ hci_add_ltk(conn->hcon->hdev, 0, conn->dst, hcon->dst_type,
+ hcon->smp_key_size, hcon->auth, ediv, rand, stk);
}
return 0;
}
+static int smp_encrypt_link(struct hci_conn *hcon, struct link_key *key)
+{
+ struct key_master_id *master;
+ u8 zerobuf[8];
+
+ if (!hcon || !key || !key->data)
+ return -EINVAL;
+
+ memset(zerobuf, 0, sizeof(zerobuf));
+
+ master = (void *) key->data;
+
+ if (!master->ediv && !memcmp(master->rand, zerobuf, sizeof(zerobuf)))
+ return -EINVAL;
+
+ hcon->enc_key_size = key->pin_len;
+ hcon->sec_req = TRUE;
+ hci_le_start_enc(hcon, master->ediv, master->rand, key->val);
+
+ return 0;
+}
+
static u8 smp_cmd_security_req(struct l2cap_conn *conn, struct sk_buff *skb)
{
struct hci_conn *hcon = conn->hcon;
@@ -659,20 +686,25 @@
key = hci_find_link_key_type(hcon->hdev, conn->dst, KEY_TYPE_LTK);
if (key && ((key->auth & SMP_AUTH_MITM) ||
!(rp->auth_req & SMP_AUTH_MITM))) {
- struct key_master_id *master = (void *) key->data;
- hci_le_start_enc(hcon, master->ediv, master->rand,
- key->val);
- hcon->enc_key_size = key->pin_len;
+ if (smp_encrypt_link(hcon, key) < 0)
+ goto invalid_key;
- hcon->sec_req = TRUE;
- hcon->sec_level = authreq_to_seclevel(rp->auth_req);
+ hcon->sec_level = authreq_to_seclevel(key->auth);
+
+ if (!(hcon->link_mode & HCI_LM_ENCRYPT))
+ hci_conn_hold(hcon);
return 0;
}
+invalid_key:
hcon->sec_req = FALSE;
+ /* Switch to Pairing Connection Parameters */
+ hci_le_conn_update(hcon, SMP_MIN_CONN_INTERVAL, SMP_MAX_CONN_INTERVAL,
+ SMP_MAX_CONN_LATENCY, SMP_SUPERVISION_TIMEOUT);
+
skb_pull(skb, sizeof(*rp));
memset(&cp, 0, sizeof(cp));
@@ -730,17 +762,9 @@
key = hci_find_link_key_type(hcon->hdev, conn->dst,
KEY_TYPE_LTK);
- if (key) {
- struct key_master_id *master = (void *) key->data;
- hci_le_start_enc(hcon, master->ediv, master->rand,
- key->val);
- hcon->enc_key_size = key->pin_len;
-
- hcon->sec_req = TRUE;
-
+ if (smp_encrypt_link(hcon, key) == 0)
goto done;
- }
}
hcon->sec_req = FALSE;
@@ -748,6 +772,11 @@
if (hcon->link_mode & HCI_LM_MASTER) {
struct smp_cmd_pairing cp;
+ /* Switch to Pairing Connection Parameters */
+ hci_le_conn_update(hcon, SMP_MIN_CONN_INTERVAL,
+ SMP_MAX_CONN_INTERVAL, SMP_MAX_CONN_LATENCY,
+ SMP_SUPERVISION_TIMEOUT);
+
build_pairing_cmd(conn, &cp, NULL, authreq);
hcon->preq[0] = SMP_CMD_PAIRING_REQ;
memcpy(&hcon->preq[1], &cp, sizeof(cp));
@@ -782,8 +811,8 @@
memset(rand, 0, sizeof(rand));
- err = hci_add_ltk(hcon->hdev, 0, conn->dst, 0, 0, 0,
- rand, rp->ltk);
+ err = hci_add_ltk(hcon->hdev, 0, conn->dst, hcon->dst_type,
+ 0, 0, 0, rand, rp->ltk);
if (err)
return SMP_UNSPECIFIED;
@@ -811,8 +840,9 @@
BT_DBG("keydist 0x%x", *keydist);
- hci_add_ltk(hcon->hdev, 1, conn->dst, hcon->smp_key_size,
- hcon->auth, rp->ediv, rp->rand, key->val);
+ hci_add_ltk(hcon->hdev, 1, conn->dst, hcon->dst_type,
+ hcon->smp_key_size, hcon->auth, rp->ediv,
+ rp->rand, key->val);
*keydist &= ~SMP_DIST_ENC_KEY;
if (hcon->out) {
@@ -949,8 +979,9 @@
smp_send_cmd(conn, SMP_CMD_ENCRYPT_INFO, sizeof(enc), &enc);
- hci_add_ltk(hcon->hdev, 1, conn->dst, hcon->smp_key_size,
- hcon->auth, ediv, ident.rand, enc.ltk);
+ hci_add_ltk(hcon->hdev, 1, conn->dst, hcon->dst_type,
+ hcon->smp_key_size, hcon->auth, ediv,
+ ident.rand, enc.ltk);
ident.ediv = cpu_to_le16(ediv);
diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c
index f2d9813..e5f1113 100644
--- a/net/ipv4/tcp.c
+++ b/net/ipv4/tcp.c
@@ -2504,6 +2504,15 @@
info->tcpi_rcv_space = tp->rcvq_space.space;
info->tcpi_total_retrans = tp->total_retrans;
+
+ /*
+ * Expose reference count for socket.
+ */
+ if (NULL != sk->sk_socket) {
+ struct file *filep = sk->sk_socket->file;
+ if (NULL != filep)
+ info->tcpi_count = atomic_read(&filep->f_count);
+ }
}
EXPORT_SYMBOL_GPL(tcp_get_info);
diff --git a/sound/soc/codecs/wcd9310.c b/sound/soc/codecs/wcd9310.c
index 620822c..ad8190c 100644
--- a/sound/soc/codecs/wcd9310.c
+++ b/sound/soc/codecs/wcd9310.c
@@ -2801,6 +2801,12 @@
struct snd_soc_codec *codec = tabla->codec;
struct tabla_pdata *pdata = tabla->pdata;
int k1, k2, k3, rc = 0;
+ u8 leg_mode = pdata->amic_settings.legacy_mode;
+ u8 txfe_bypass = pdata->amic_settings.txfe_enable;
+ u8 txfe_buff = pdata->amic_settings.txfe_buff;
+ u8 flag = pdata->amic_settings.use_pdata;
+ u8 i = 0, j = 0;
+ u8 val_txfe = 0, value = 0;
if (!pdata) {
rc = -ENODEV;
@@ -2850,6 +2856,38 @@
snd_soc_update_bits(codec, TABLA_A_MICB_4_CTL, 0x60,
(pdata->micbias.bias4_cfilt_sel << 5));
+ for (i = 0; i < 6; j++, i += 2) {
+ if (flag & (0x01 << i)) {
+ value = (leg_mode & (0x01 << i)) ? 0x10 : 0x00;
+ val_txfe = (txfe_bypass & (0x01 << i)) ? 0x20 : 0x00;
+ val_txfe = val_txfe |
+ ((txfe_buff & (0x01 << i)) ? 0x10 : 0x00);
+ snd_soc_update_bits(codec, TABLA_A_TX_1_2_EN + j * 10,
+ 0x10, value);
+ snd_soc_update_bits(codec,
+ TABLA_A_TX_1_2_TEST_EN + j * 10,
+ 0x30, val_txfe);
+ }
+ if (flag & (0x01 << (i + 1))) {
+ value = (leg_mode & (0x01 << (i + 1))) ? 0x01 : 0x00;
+ val_txfe = (txfe_bypass &
+ (0x01 << (i + 1))) ? 0x02 : 0x00;
+ val_txfe |= (txfe_buff &
+ (0x01 << (i + 1))) ? 0x01 : 0x00;
+ snd_soc_update_bits(codec, TABLA_A_TX_1_2_EN + j * 10,
+ 0x01, value);
+ snd_soc_update_bits(codec,
+ TABLA_A_TX_1_2_TEST_EN + j * 10,
+ 0x03, val_txfe);
+ }
+ }
+ if (flag & 0x40) {
+ value = (leg_mode & 0x40) ? 0x10 : 0x00;
+ value = value | ((txfe_bypass & 0x40) ? 0x02 : 0x00);
+ value = value | ((txfe_buff & 0x40) ? 0x01 : 0x00);
+ snd_soc_update_bits(codec, TABLA_A_TX_7_MBHC_EN,
+ 0x13, value);
+ }
done:
return rc;
}
@@ -2919,6 +2957,8 @@
static const struct tabla_reg_mask_val tabla_codec_reg_init_val[] = {
+ {TABLA_A_QFUSE_CTL, 0xFF, 0x03},
+
/* Initialize gain registers to use register gain */
{TABLA_A_RX_HPH_L_GAIN, 0x10, 0x10},
{TABLA_A_RX_HPH_R_GAIN, 0x10, 0x10},
@@ -3010,16 +3050,15 @@
tabla->codec = codec;
tabla->pdata = dev_get_platdata(codec->dev->parent);
- ret = tabla_handle_pdata(tabla);
+ tabla_update_reg_defaults(codec);
+ tabla_codec_init_reg(codec);
+ ret = tabla_handle_pdata(tabla);
if (IS_ERR_VALUE(ret)) {
pr_err("%s: bad pdata\n", __func__);
goto err_pdata;
}
- tabla_update_reg_defaults(codec);
- tabla_codec_init_reg(codec);
-
/* TODO only enable bandgap when necessary in order to save power */
tabla_codec_enable_bandgap(codec, TABLA_BANDGAP_AUDIO_MODE);
tabla_codec_enable_clock_block(codec, 0);
diff --git a/sound/soc/msm/msm8960.c b/sound/soc/msm/msm8960.c
index 0f08682..f5f5893 100644
--- a/sound/soc/msm/msm8960.c
+++ b/sound/soc/msm/msm8960.c
@@ -577,6 +577,8 @@
pr_debug("%s()\n", __func__);
+ rtd->pmdown_time = 0;
+
err = snd_soc_add_controls(codec, tabla_msm8960_controls,
ARRAY_SIZE(tabla_msm8960_controls));
if (err < 0)
diff --git a/sound/soc/msm/qdsp6/q6asm.c b/sound/soc/msm/qdsp6/q6asm.c
index 9fcee70..fd59a44 100644
--- a/sound/soc/msm/qdsp6/q6asm.c
+++ b/sound/soc/msm/qdsp6/q6asm.c
@@ -1081,6 +1081,10 @@
open.uMode = BUFFER_META_ENABLE | STREAM_PRIORITY_HIGH;
open.format = AMRNB_FS;
break;
+ case FORMAT_AMRWB:
+ open.uMode = BUFFER_META_ENABLE | STREAM_PRIORITY_HIGH;
+ open.format = AMRWB_FS;
+ break;
default:
pr_err("Invalid format[%d]\n", format);
goto fail_cmd;
@@ -1205,6 +1209,27 @@
case FORMAT_WMA_V10PRO:
open.write_format = WMA_V10PRO;
break;
+ case FORMAT_AMRNB:
+ open.write_format = AMRNB_FS;
+ break;
+ case FORMAT_AMRWB:
+ open.write_format = AMRWB_FS;
+ break;
+ case FORMAT_V13K:
+ open.write_format = V13K_FS;
+ break;
+ case FORMAT_EVRC:
+ open.write_format = EVRC_FS;
+ break;
+ case FORMAT_EVRCB:
+ open.write_format = EVRCB_FS;
+ break;
+ case FORMAT_EVRCWB:
+ open.write_format = EVRCWB_FS;
+ break;
+ case FORMAT_MP3:
+ open.write_format = MP3;
+ break;
default:
pr_err("Invalid format[%d]\n", wr_format);
goto fail_cmd;
@@ -1226,6 +1251,9 @@
case FORMAT_AMRNB:
open.read_format = AMRNB_FS;
break;
+ case FORMAT_AMRWB:
+ open.read_format = AMRWB_FS;
+ break;
default:
pr_err("Invalid format[%d]\n", rd_format);
goto fail_cmd;
@@ -1597,6 +1625,44 @@
return -EINVAL;
}
+int q6asm_enc_cfg_blk_amrwb(struct audio_client *ac, uint32_t frames_per_buf,
+ uint16_t band_mode, uint16_t dtx_enable)
+{
+ struct asm_stream_cmd_encdec_cfg_blk enc_cfg;
+ int rc = 0;
+
+ pr_debug("%s:session[%d]frames[%d]band_mode[0x%4x]dtx_enable[0x%4x]",
+ __func__, ac->session, frames_per_buf, band_mode, dtx_enable);
+
+ q6asm_add_hdr(ac, &enc_cfg.hdr, sizeof(enc_cfg), TRUE);
+
+ enc_cfg.hdr.opcode = ASM_STREAM_CMD_SET_ENCDEC_PARAM;
+
+ enc_cfg.param_id = ASM_ENCDEC_CFG_BLK_ID;
+ enc_cfg.param_size = sizeof(struct asm_encode_cfg_blk);
+
+ enc_cfg.enc_blk.frames_per_buf = frames_per_buf;
+ enc_cfg.enc_blk.format_id = AMRWB_FS;
+ enc_cfg.enc_blk.cfg_size = sizeof(struct asm_amrwb_read_cfg);
+ enc_cfg.enc_blk.cfg.amrwb.mode = band_mode;
+ enc_cfg.enc_blk.cfg.amrwb.dtx_mode = dtx_enable;
+
+ rc = apr_send_pkt(ac->apr, (uint32_t *) &enc_cfg);
+ if (rc < 0) {
+ pr_err("Comamnd %d failed\n", ASM_STREAM_CMD_SET_ENCDEC_PARAM);
+ goto fail_cmd;
+ }
+ rc = wait_event_timeout(ac->cmd_wait,
+ (atomic_read(&ac->cmd_state) == 0), 5*HZ);
+ if (!rc) {
+ pr_err("timeout. waited for FORMAT_UPDATE\n");
+ goto fail_cmd;
+ }
+ return 0;
+fail_cmd:
+ return -EINVAL;
+}
+
int q6asm_media_format_block_pcm(struct audio_client *ac,
uint32_t rate, uint32_t channels)
{
@@ -1732,6 +1798,37 @@
}
+
+int q6asm_media_format_block(struct audio_client *ac, uint32_t format)
+{
+
+ struct asm_stream_media_format_update fmt;
+ int rc = 0;
+
+ pr_debug("%s:session[%d] format[0x%x]\n", __func__,
+ ac->session, format);
+
+ q6asm_add_hdr(ac, &fmt.hdr, sizeof(fmt), TRUE);
+ fmt.hdr.opcode = ASM_DATA_CMD_MEDIA_FORMAT_UPDATE;
+ fmt.format = format;
+ fmt.cfg_size = 0;
+
+ rc = apr_send_pkt(ac->apr, (uint32_t *) &fmt);
+ if (rc < 0) {
+ pr_err("%s:Comamnd open failed\n", __func__);
+ goto fail_cmd;
+ }
+ rc = wait_event_timeout(ac->cmd_wait,
+ (atomic_read(&ac->cmd_state) == 0), 5*HZ);
+ if (!rc) {
+ pr_err("%s:timeout. waited for FORMAT_UPDATE\n", __func__);
+ goto fail_cmd;
+ }
+ return 0;
+fail_cmd:
+ return -EINVAL;
+}
+
int q6asm_media_format_block_wma(struct audio_client *ac,
void *cfg)
{
diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c
index fa709a7..ee66479 100644
--- a/sound/soc/soc-core.c
+++ b/sound/soc/soc-core.c
@@ -794,9 +794,15 @@
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
/* start delayed pop wq here for playback streams */
- codec_dai->pop_wait = 1;
- schedule_delayed_work(&rtd->delayed_work,
+ if (rtd->pmdown_time) {
+ codec_dai->pop_wait = 1;
+ schedule_delayed_work(&rtd->delayed_work,
msecs_to_jiffies(rtd->pmdown_time));
+ } else {
+ snd_soc_dapm_stream_event(rtd,
+ codec_dai->driver->playback.stream_name,
+ SND_SOC_DAPM_STREAM_STOP);
+ }
} else {
/* capture streams can be powered down now */
snd_soc_dapm_stream_event(rtd,