power: qpnp-bms: add a delay for timing requirement
A delay of 2 sleep clock cycles (~60 microseconds) is found to be needed
between locking the bms output registers and reading the coulomb counter.
Without this delay, there can be a potential SPMI transaction failure
where the peripheral fails to respond.
As a safety measure, also add error handling code to abort the current SOC
calculation if a read fails.
CRs-Fixed: 720880
Change-Id: Ia632e31202791afa82ff4b49a8eaa334fd22da8f
Signed-off-by: Xiaozhe Shi <xiaozhes@codeaurora.org>
1 file changed