Merge "msm: rotator: add check for buffers boundaries" into msm-3.0
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b2dbee3..184026a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -24,7 +24,7 @@
select HAVE_PERF_EVENTS
select PERF_USE_VMALLOC
select HAVE_REGS_AND_STACK_ACCESS_API
- select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
+ #select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
select HAVE_C_RECORDMCOUNT
select HAVE_GENERIC_HARDIRQS
select HAVE_SPARSE_IRQ
diff --git a/arch/arm/boot/dts/skeleton.dtsi b/arch/arm/boot/dts/skeleton.dtsi
new file mode 100644
index 0000000..b41d241
--- /dev/null
+++ b/arch/arm/boot/dts/skeleton.dtsi
@@ -0,0 +1,13 @@
+/*
+ * Skeleton device tree; the bare minimum needed to boot; just include and
+ * add a compatible value. The bootloader will typically populate the memory
+ * node.
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ chosen { };
+ aliases { };
+ memory { device_type = "memory"; reg = <0 0>; };
+};
diff --git a/arch/arm/configs/apq8064_defconfig b/arch/arm/configs/apq8064_defconfig
index d04e6a4..2f3d37a 100644
--- a/arch/arm/configs/apq8064_defconfig
+++ b/arch/arm/configs/apq8064_defconfig
@@ -214,3 +214,11 @@
# CONFIG_CRYPTO_HW is not set
CONFIG_CRC_CCITT=y
CONFIG_LIBCRC32C=y
+CONFIG_MSM_SMD=y
+CONFIG_MSM_SMD_PKG4=y
+CONFIG_MSM_SMD_PKT=y
+CONFIG_MSM_SMD_DEBUG=y
+CONFIG_MSM_SMD_TTY=y
+CONFIG_MSM_N_WAY_SMD=y
+CONFIG_MSM_N_WAY_SMSM=y
+CONFIG_MSM_SMD_LOGGING=y
diff --git a/arch/arm/configs/fsm9xxx-perf_defconfig b/arch/arm/configs/fsm9xxx-perf_defconfig
index 50145f9..60d8a32 100644
--- a/arch/arm/configs/fsm9xxx-perf_defconfig
+++ b/arch/arm/configs/fsm9xxx-perf_defconfig
@@ -7,6 +7,7 @@
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_BLK_DEV_INITRD=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_ASHMEM=y
CONFIG_EMBEDDED=y
# CONFIG_PERF_EVENTS is not set
diff --git a/arch/arm/configs/fsm9xxx_defconfig b/arch/arm/configs/fsm9xxx_defconfig
index 4019a4f..6913409 100644
--- a/arch/arm/configs/fsm9xxx_defconfig
+++ b/arch/arm/configs/fsm9xxx_defconfig
@@ -7,6 +7,7 @@
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_BLK_DEV_INITRD=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_KALLSYMS_ALL=y
CONFIG_ASHMEM=y
CONFIG_EMBEDDED=y
diff --git a/arch/arm/configs/msm-copper_defconfig b/arch/arm/configs/msm-copper_defconfig
new file mode 100644
index 0000000..9fb4615
--- /dev/null
+++ b/arch/arm/configs/msm-copper_defconfig
@@ -0,0 +1,147 @@
+CONFIG_EXPERIMENTAL=y
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_DEBUG=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_SCHED=y
+# CONFIG_FAIR_GROUP_SCHED is not set
+CONFIG_RT_GROUP_SCHED=y
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_ASHMEM=y
+CONFIG_EMBEDDED=y
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=m
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_ARCH_MSM=y
+CONFIG_ARCH_MSMCOPPER=y
+CONFIG_MSM_KRAIT_TBB_ABORT_HANDLER=y
+# CONFIG_MSM_STACKED_MEMORY is not set
+CONFIG_CPU_HAS_L2_PMU=y
+# CONFIG_MSM_JTAG_V7 is not set
+# CONFIG_MSM_FIQ_SUPPORT is not set
+# CONFIG_MSM_PROC_COMM is not set
+# CONFIG_MSM_DALRPC is not set
+# CONFIG_MSM_HW3D is not set
+CONFIG_MSM_DIRECT_SCLK_ACCESS=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_SMP=y
+# CONFIG_SMP_ON_UP is not set
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+CONFIG_VMALLOC_RESERVE=0x19000000
+CONFIG_USE_OF=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IPV6=y
+CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+CONFIG_IPV6_OPTIMISTIC_DAD=y
+CONFIG_IPV6_MIP6=y
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_MISC_DEVICES=y
+CONFIG_SCSI=y
+CONFIG_SCSI_TGT=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_CHR_DEV_SCH=y
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_NETDEVICES=y
+# CONFIG_MSM_RMNET is not set
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_EVBUG=m
+CONFIG_INPUT_JOYSTICK=y
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_UINPUT=y
+CONFIG_SERIAL_MSM_HSL=y
+CONFIG_SERIAL_MSM_HSL_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_DCC_TTY=y
+CONFIG_DEBUG_GPIO=y
+CONFIG_GPIO_SYSFS=y
+# CONFIG_HWMON is not set
+# CONFIG_MFD_SUPPORT is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+# CONFIG_LEDS_MSM_PMIC is not set
+CONFIG_SWITCH=y
+CONFIG_STAGING=y
+CONFIG_ANDROID=y
+CONFIG_ANDROID_BINDER_IPC=y
+CONFIG_ANDROID_LOGGER=y
+CONFIG_ANDROID_RAM_CONSOLE=y
+CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION=y
+CONFIG_ANDROID_TIMED_GPIO=y
+CONFIG_ANDROID_LOW_MEMORY_KILLER=y
+CONFIG_MSM_SSBI=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT4_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_PRINTK_TIME=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_PREEMPT is not set
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_DEBUG_USER=y
+CONFIG_KEYS=y
+CONFIG_CRYPTO_AUTHENC=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRC_CCITT=y
+CONFIG_LIBCRC32C=y
diff --git a/arch/arm/configs/msm7627-perf_defconfig b/arch/arm/configs/msm7627-perf_defconfig
index 1cc4b97..78eeadd 100644
--- a/arch/arm/configs/msm7627-perf_defconfig
+++ b/arch/arm/configs/msm7627-perf_defconfig
@@ -11,6 +11,7 @@
CONFIG_CGROUP_SCHED=y
CONFIG_RT_GROUP_SCHED=y
CONFIG_BLK_DEV_INITRD=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_KALLSYMS_ALL=y
CONFIG_ASHMEM=y
CONFIG_EMBEDDED=y
diff --git a/arch/arm/configs/msm7627_defconfig b/arch/arm/configs/msm7627_defconfig
index 6f0cb31..7da4daf 100644
--- a/arch/arm/configs/msm7627_defconfig
+++ b/arch/arm/configs/msm7627_defconfig
@@ -11,6 +11,7 @@
CONFIG_CGROUP_SCHED=y
CONFIG_RT_GROUP_SCHED=y
CONFIG_BLK_DEV_INITRD=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_ASHMEM=y
CONFIG_EMBEDDED=y
CONFIG_SLAB=y
diff --git a/arch/arm/configs/msm7627a-perf_defconfig b/arch/arm/configs/msm7627a-perf_defconfig
index 8be0165..06d04f7 100644
--- a/arch/arm/configs/msm7627a-perf_defconfig
+++ b/arch/arm/configs/msm7627a-perf_defconfig
@@ -12,6 +12,7 @@
CONFIG_CGROUP_SCHED=y
CONFIG_RT_GROUP_SCHED=y
CONFIG_BLK_DEV_INITRD=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_KALLSYMS_ALL=y
CONFIG_ASHMEM=y
CONFIG_EMBEDDED=y
@@ -157,6 +158,7 @@
CONFIG_BT_MSM_SLEEP=y
CONFIG_MSM_BT_POWER=y
CONFIG_RFKILL=y
+CONFIG_RFKILL_PM=y
CONFIG_MTD=y
CONFIG_MTD_TESTS=m
CONFIG_MTD_CMDLINE_PARTS=y
@@ -182,6 +184,8 @@
CONFIG_SMSC911X=y
# CONFIG_NETDEV_10000 is not set
CONFIG_LIBRA_SDIOIF=m
+CONFIG_CFG80211=y
+CONFIG_CFG80211_WEXT=n
# CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_EVDEV=y
CONFIG_INPUT_EVBUG=m
@@ -231,7 +235,7 @@
CONFIG_FB_MSM_TRIPLE_BUFFER=y
CONFIG_FB_MSM_MDP30=y
CONFIG_FB_MSM_MDP303=y
-CONFIG_FB_MSM_MIPI_RENESAS_CMD_FWVGA_PT_PANEL=y
+CONFIG_FB_MSM_MIPI_PANEL_DETECT=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_SOUND=y
diff --git a/arch/arm/configs/msm7627a_defconfig b/arch/arm/configs/msm7627a_defconfig
index ed4fd41..909a0bf 100644
--- a/arch/arm/configs/msm7627a_defconfig
+++ b/arch/arm/configs/msm7627a_defconfig
@@ -12,6 +12,7 @@
CONFIG_CGROUP_SCHED=y
CONFIG_RT_GROUP_SCHED=y
CONFIG_BLK_DEV_INITRD=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_ASHMEM=y
CONFIG_EMBEDDED=y
CONFIG_SLAB=y
@@ -155,6 +156,7 @@
CONFIG_BT_MSM_SLEEP=y
CONFIG_MSM_BT_POWER=y
CONFIG_RFKILL=y
+CONFIG_RFKILL_PM=y
CONFIG_MTD=y
CONFIG_MTD_TESTS=m
CONFIG_MTD_CMDLINE_PARTS=y
@@ -180,6 +182,8 @@
CONFIG_SMSC911X=y
# CONFIG_NETDEV_10000 is not set
CONFIG_LIBRA_SDIOIF=m
+CONFIG_CFG80211=y
+CONFIG_CFG80211_WEXT=n
# CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_EVDEV=y
CONFIG_INPUT_EVBUG=m
@@ -229,7 +233,7 @@
CONFIG_FB_MSM_TRIPLE_BUFFER=y
CONFIG_FB_MSM_MDP30=y
CONFIG_FB_MSM_MDP303=y
-CONFIG_FB_MSM_MIPI_RENESAS_CMD_FWVGA_PT_PANEL=y
+CONFIG_FB_MSM_MIPI_PANEL_DETECT=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_SOUND=y
diff --git a/arch/arm/configs/msm7630-perf_defconfig b/arch/arm/configs/msm7630-perf_defconfig
index cc86af8..5b52404 100644
--- a/arch/arm/configs/msm7630-perf_defconfig
+++ b/arch/arm/configs/msm7630-perf_defconfig
@@ -11,6 +11,7 @@
CONFIG_CGROUP_SCHED=y
CONFIG_RT_GROUP_SCHED=y
CONFIG_BLK_DEV_INITRD=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_ASHMEM=y
CONFIG_EMBEDDED=y
CONFIG_SLAB=y
diff --git a/arch/arm/configs/msm7630_defconfig b/arch/arm/configs/msm7630_defconfig
index 9645211..9ad0b5a 100644
--- a/arch/arm/configs/msm7630_defconfig
+++ b/arch/arm/configs/msm7630_defconfig
@@ -11,6 +11,7 @@
CONFIG_CGROUP_SCHED=y
CONFIG_RT_GROUP_SCHED=y
CONFIG_BLK_DEV_INITRD=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_ASHMEM=y
CONFIG_EMBEDDED=y
CONFIG_SLAB=y
diff --git a/arch/arm/configs/msm8660-perf_defconfig b/arch/arm/configs/msm8660-perf_defconfig
index 3315171..0f41c0a 100644
--- a/arch/arm/configs/msm8660-perf_defconfig
+++ b/arch/arm/configs/msm8660-perf_defconfig
@@ -18,6 +18,7 @@
CONFIG_BLK_DEV_INITRD=y
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_PANIC_TIMEOUT=5
CONFIG_ASHMEM=y
CONFIG_EMBEDDED=y
@@ -213,6 +214,7 @@
CONFIG_MSM_BT_POWER=y
# CONFIG_WIRELESS_EXT_SYSFS is not set
CONFIG_RFKILL=y
+CONFIG_RFKILL_PM=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_MISC_DEVICES=y
@@ -247,6 +249,8 @@
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
CONFIG_LIBRA_SDIOIF=m
+CONFIG_CFG80211=y
+CONFIG_CFG80211_WEXT=n
CONFIG_PPP=y
CONFIG_PPP_ASYNC=y
CONFIG_PPP_DEFLATE=y
diff --git a/arch/arm/configs/msm8660_defconfig b/arch/arm/configs/msm8660_defconfig
index 698855a..e900062 100644
--- a/arch/arm/configs/msm8660_defconfig
+++ b/arch/arm/configs/msm8660_defconfig
@@ -18,6 +18,7 @@
CONFIG_BLK_DEV_INITRD=y
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_PANIC_TIMEOUT=5
CONFIG_ASHMEM=y
CONFIG_EMBEDDED=y
@@ -204,6 +205,7 @@
CONFIG_MSM_BT_POWER=y
# CONFIG_WIRELESS_EXT_SYSFS is not set
CONFIG_RFKILL=y
+CONFIG_RFKILL_PM=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_MISC_DEVICES=y
@@ -240,6 +242,8 @@
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
CONFIG_LIBRA_SDIOIF=m
+CONFIG_CFG80211=y
+CONFIG_CFG80211_WEXT=n
CONFIG_PPP=y
CONFIG_PPP_ASYNC=y
CONFIG_PPP_DEFLATE=y
diff --git a/arch/arm/configs/msm8960_defconfig b/arch/arm/configs/msm8960_defconfig
index 7564020..73d0756 100755
--- a/arch/arm/configs/msm8960_defconfig
+++ b/arch/arm/configs/msm8960_defconfig
@@ -19,6 +19,7 @@
CONFIG_BLK_DEV_INITRD=y
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_PANIC_TIMEOUT=5
CONFIG_KALLSYMS_ALL=y
CONFIG_ASHMEM=y
@@ -325,6 +326,7 @@
CONFIG_USB_STORAGE_KARMA=y
CONFIG_USB_STORAGE_CYPRESS_ATACB=y
CONFIG_USB_EHSET_TEST_FIXTURE=y
+CONFIG_USB_QCOM_DUN_BRIDGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DEBUG_FILES=y
CONFIG_USB_GADGET_CI13XXX_MSM=y
diff --git a/arch/arm/configs/msm9615_defconfig b/arch/arm/configs/msm9615_defconfig
index 52a4d20..f8ccbb3 100644
--- a/arch/arm/configs/msm9615_defconfig
+++ b/arch/arm/configs/msm9615_defconfig
@@ -20,6 +20,8 @@
CONFIG_BLK_DEV_INITRD=y
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_PANIC_TIMEOUT=5
CONFIG_KALLSYMS_ALL=y
CONFIG_EMBEDDED=y
# CONFIG_PERF_EVENTS is not set
@@ -39,8 +41,11 @@
# CONFIG_MSM_PROC_COMM is not set
CONFIG_MSM_SMD=y
CONFIG_MSM_SMD_PKG4=y
+CONFIG_MSM_IPC_ROUTER=y
+CONFIG_MSM_IPC_ROUTER_SMD_XPRT=y
CONFIG_MSM_DIRECT_SCLK_ACCESS=y
CONFIG_MSM_WATCHDOG=y
+CONFIG_MSM_DLOAD_MODE=y
CONFIG_SWP_EMULATE=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
@@ -80,8 +85,10 @@
# CONFIG_SERIAL_MSM_CLOCK_CONTROL is not set
CONFIG_SERIAL_MSM_HSL=y
CONFIG_SERIAL_MSM_HSL_CONSOLE=y
+CONFIG_DIAG_CHAR=y
CONFIG_HVC_DCC=y
CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_MSM=y
CONFIG_DCC_TTY=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
@@ -99,7 +106,26 @@
# CONFIG_MFD_PM8XXX_PWM is not set
CONFIG_REGULATOR=y
# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_CI13XXX_MSM=y
+CONFIG_USB_G_ANDROID=y
+CONFIG_SWITCH=y
+CONFIG_NET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+CONFIG_IPV6=y
+# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET6_XFRM_MODE_BEET is not set
+# CONFIG_IPV6_SIT is not set
+# CONFIG_ANDROID_PARANOID_NETWORK is not set
+# CONFIG_WIRELESS is not set
CONFIG_MMC=y
# CONFIG_MMC_DEBUG is not set
CONFIG_MMC_PERF_PROFILING=y
@@ -132,7 +158,11 @@
# CONFIG_MMC_MSM_SDC3_SUPPORT is not set
# CONFIG_MMC_MSM_SDC4_SUPPORT is not set
# CONFIG_MMC_MSM_SDC5_SUPPORT is not set
-# CONFIG_MMC_MSM_SPS_SUPPORT is not set
+CONFIG_MMC_MSM_SPS_SUPPORT=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_INTF_ALARM is not set
+# CONFIG_RTC_DRV_MSM is not set
+CONFIG_RTC_DRV_PM8XXX=y
CONFIG_MSM_SSBI=y
CONFIG_SPS=y
CONFIG_SPS_SUPPORT_BAMDMA=y
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index 946f4d7..ae744a8 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -70,4 +70,11 @@
#define MACHINE_END \
};
+#define DT_MACHINE_START(_name, _namestr) \
+static const struct machine_desc __mach_desc_##_name \
+ __used \
+ __attribute__((__section__(".arch.info.init"))) = { \
+ .nr = ~0, \
+ .name = _namestr,
+
#endif
diff --git a/arch/arm/kernel/perf_event_msm_krait_l2.c b/arch/arm/kernel/perf_event_msm_krait_l2.c
index e1c3fb5..0512e64 100644
--- a/arch/arm/kernel/perf_event_msm_krait_l2.c
+++ b/arch/arm/kernel/perf_event_msm_krait_l2.c
@@ -10,7 +10,7 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
-#ifdef CONFIG_CPU_HAS_L2_PMU
+#ifdef CONFIG_ARCH_MSM_KRAIT
#include <linux/irq.h>
diff --git a/arch/arm/kernel/perf_event_msm_l2.c b/arch/arm/kernel/perf_event_msm_l2.c
index db8481f..3cb251b 100644
--- a/arch/arm/kernel/perf_event_msm_l2.c
+++ b/arch/arm/kernel/perf_event_msm_l2.c
@@ -10,7 +10,7 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
-#ifdef CONFIG_CPU_HAS_L2_PMU
+#ifdef CONFIG_ARCH_MSM8x60
#include <linux/irq.h>
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index a595612..ad07bbb 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -15,6 +15,7 @@
select MSM_VIC
select CPU_V6
select MSM_REMOTE_SPINLOCK_SWP
+ select MULTI_IRQ_HANDLER
config ARCH_MSM7X27
bool "MSM7x27"
@@ -27,6 +28,7 @@
select MSM_REMOTE_SPINLOCK_SWP if MSM_SOC_REV_NONE
select MSM_GPIOMUX
select REGULATOR
+ select MULTI_IRQ_HANDLER
config ARCH_MSM7X30
bool "MSM7x30"
@@ -48,6 +50,7 @@
select MSM_SPM_V1
select REGULATOR
select MSM_PROC_COMM_REGULATOR
+ select MULTI_IRQ_HANDLER
config ARCH_QSD8X50
bool "QSD8X50"
@@ -229,6 +232,7 @@
bool
select MSM_DALRPC
select MSM_PROC_COMM_REGULATOR
+ select MULTI_IRQ_HANDLER
config MSM_VIC
bool
@@ -1534,7 +1538,7 @@
config MSM_IOMMU
bool "MSM IOMMU Support"
- depends on ARCH_MSM8X60 || ARCH_MSM8960
+ depends on ARCH_MSM8X60 || ARCH_MSM8960 || ARCH_APQ8064
select IOMMU_API
default n
help
@@ -1598,7 +1602,7 @@
config MSM_DLOAD_MODE
bool "Enable download mode on crashes"
- depends on ARCH_MSM8X60 || ARCH_MSM8960
+ depends on ARCH_MSM8X60 || ARCH_MSM8960 || ARCH_MSM9615
default n
help
This makes the SoC enter download mode when it resets
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 0072100..025f1c7 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -204,6 +204,7 @@
obj-$(CONFIG_MACH_MSM7X27A_RUMI3) += board-msm7x27a.o
obj-$(CONFIG_MACH_MSM7X27A_SURF) += board-msm7x27a.o
obj-$(CONFIG_MACH_MSM7X27A_FFA) += board-msm7x27a.o
+obj-$(CONFIG_MACH_MSM7627A_QRD1) += board-qrd7627a.o
obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o memory_topology.o
obj-$(CONFIG_ARCH_MSM7X30) += clock-local.o clock-7x30.o acpuclock-7x30.o
obj-$(CONFIG_MACH_MSM7X25_SURF) += board-msm7x27.o devices-msm7x25.o
diff --git a/arch/arm/mach-msm/acpuclock-8960.c b/arch/arm/mach-msm/acpuclock-8960.c
index d827dd1..cfc7dd0 100644
--- a/arch/arm/mach-msm/acpuclock-8960.c
+++ b/arch/arm/mach-msm/acpuclock-8960.c
@@ -71,6 +71,9 @@
#define SECCLKAGD BIT(4)
+/* PTE EFUSE register. */
+#define QFPROM_PTE_EFUSE_ADDR (MSM_QFPROM_BASE + 0x00C0)
+
enum scalables {
CPU0 = 0,
CPU1,
@@ -398,6 +401,10 @@
/* Wait for switch to complete. */
mb();
udelay(1);
+
+ /* Re-enable secondary source clock gating. */
+ regval &= ~SECCLKAGD;
+ set_l2_indirect_reg(sc->l2cpmr_iaddr, regval);
}
/* Enable an already-configured HFPLL. */
@@ -975,6 +982,30 @@
/* Select frequency tables. */
if (cpu_is_msm8960()) {
+ uint32_t pte_efuse, pvs;
+
+ pte_efuse = readl_relaxed(QFPROM_PTE_EFUSE_ADDR);
+ pvs = (pte_efuse >> 10) & 0x7;
+ if (pvs == 0x7)
+ pvs = (pte_efuse >> 13) & 0x7;
+
+ switch (pvs) {
+ case 0x0:
+ case 0x7:
+ pr_info("ACPU PVS: Slow\n");
+ break;
+ case 0x1:
+ pr_info("ACPU PVS: Nominal\n");
+ break;
+ case 0x3:
+ pr_info("ACPU PVS: Fast\n");
+ break;
+ default:
+ pr_warn("ACPU PVS: Unknown. Defaulting to slow.\n");
+ break;
+ }
+
+ /* TODO: Select tables based on PVS data. */
scalable = scalable_8960;
acpu_freq_tbl = acpu_freq_tbl_8960;
l2_freq_tbl = l2_freq_tbl_8960;
diff --git a/arch/arm/mach-msm/bam_dmux.c b/arch/arm/mach-msm/bam_dmux.c
index 5ed4456..304a687 100644
--- a/arch/arm/mach-msm/bam_dmux.c
+++ b/arch/arm/mach-msm/bam_dmux.c
@@ -24,6 +24,7 @@
#include <linux/sched.h>
#include <linux/skbuff.h>
#include <linux/debugfs.h>
+#include <linux/clk.h>
#include <mach/sps.h>
#include <mach/bam_dmux.h>
@@ -119,6 +120,7 @@
#define BUFFER_SIZE 2048
#define NUM_BUFFERS 32
static struct sps_bam_props a2_props;
+static u32 a2_device_handle;
static struct sps_pipe *bam_tx_pipe;
static struct sps_pipe *bam_rx_pipe;
static struct sps_connect tx_connection;
@@ -155,6 +157,26 @@
static struct workqueue_struct *bam_mux_rx_workqueue;
static struct workqueue_struct *bam_mux_tx_workqueue;
+/* A2 power collaspe */
+#define UL_TIMEOUT_DELAY 1000 /* in ms */
+static void toggle_apps_ack(void);
+static void reconnect_to_bam(void);
+static void disconnect_to_bam(void);
+static void ul_wakeup(void);
+static void ul_timeout(struct work_struct *work);
+static void vote_dfab(void);
+static void unvote_dfab(void);
+
+static int bam_is_connected;
+static DEFINE_MUTEX(wakeup_lock);
+static struct completion ul_wakeup_ack_completion;
+static struct completion bam_connection_completion;
+static struct delayed_work ul_timeout_work;
+static int ul_packet_written;
+static struct clk *dfab_clk;
+static DEFINE_RWLOCK(ul_wakeup_lock);
+/* End A2 power collaspe */
+
#define bam_ch_is_open(x) \
(bam_ch[(x)].status == (BAM_CH_LOCAL_OPEN | BAM_CH_REMOTE_OPEN))
@@ -316,6 +338,7 @@
pkt, SPS_IOVEC_FLAG_INT | SPS_IOVEC_FLAG_EOT);
mutex_unlock(&bam_mux_lock);
+ ul_packet_written = 1;
return rc;
}
@@ -365,6 +388,10 @@
}
spin_unlock_irqrestore(&bam_ch[id].lock, flags);
+ read_lock(&ul_wakeup_lock);
+ if (!bam_is_connected)
+ ul_wakeup();
+
/* if skb do not have any tailroom for padding,
copy the skb into a new expanded skb */
if ((skb->len & 0x3) && (skb_tailroom(skb) < (4 - (skb->len & 0x3)))) {
@@ -421,6 +448,8 @@
INIT_WORK(&pkt->work, bam_mux_write_done);
rc = sps_transfer_one(bam_tx_pipe, dma_address, skb->len,
pkt, SPS_IOVEC_FLAG_INT | SPS_IOVEC_FLAG_EOT);
+ ul_packet_written = 1;
+ read_unlock(&ul_wakeup_lock);
return rc;
}
@@ -464,6 +493,10 @@
bam_ch[id].status |= BAM_CH_LOCAL_OPEN;
spin_unlock_irqrestore(&bam_ch[id].lock, flags);
+ read_lock(&ul_wakeup_lock);
+ if (!bam_is_connected)
+ ul_wakeup();
+
hdr->magic_num = BAM_MUX_HDR_MAGIC_NO;
hdr->cmd = BAM_MUX_HDR_CMD_OPEN;
hdr->reserved = 0;
@@ -472,6 +505,7 @@
hdr->pad_len = 0;
rc = bam_mux_write_cmd((void *)hdr, sizeof(struct bam_mux_hdr));
+ read_unlock(&ul_wakeup_lock);
open_done:
DBG("%s: opened ch %d\n", __func__, id);
@@ -491,6 +525,10 @@
return -ENODEV;
spin_lock_irqsave(&bam_ch[id].lock, flags);
+ read_lock(&ul_wakeup_lock);
+ if (!bam_is_connected)
+ ul_wakeup();
+
bam_ch[id].notify = NULL;
bam_ch[id].priv = NULL;
bam_ch[id].status &= ~BAM_CH_LOCAL_OPEN;
@@ -509,6 +547,7 @@
hdr->pad_len = 0;
rc = bam_mux_write_cmd((void *)hdr, sizeof(struct bam_mux_hdr));
+ read_unlock(&ul_wakeup_lock);
DBG("%s: closed ch %d\n", __func__, id);
return rc;
@@ -708,6 +747,101 @@
#endif
+static void ul_timeout(struct work_struct *work)
+{
+ write_lock(&ul_wakeup_lock);
+ if (ul_packet_written) {
+ ul_packet_written = 0;
+ schedule_delayed_work(&ul_timeout_work,
+ msecs_to_jiffies(UL_TIMEOUT_DELAY));
+ } else {
+ smsm_change_state(SMSM_APPS_STATE, SMSM_A2_POWER_CONTROL, 0);
+ bam_is_connected = 0;
+ }
+ write_unlock(&ul_wakeup_lock);
+}
+static void ul_wakeup(void)
+{
+ mutex_lock(&wakeup_lock);
+ if (bam_is_connected) { /* bam got connected before lock grabbed */
+ mutex_unlock(&wakeup_lock);
+ return;
+ }
+ INIT_COMPLETION(ul_wakeup_ack_completion);
+ smsm_change_state(SMSM_APPS_STATE, 0, SMSM_A2_POWER_CONTROL);
+ wait_for_completion_interruptible_timeout(&ul_wakeup_ack_completion,
+ HZ);
+ wait_for_completion_interruptible_timeout(&bam_connection_completion,
+ HZ);
+
+ bam_is_connected = 1;
+ schedule_delayed_work(&ul_timeout_work,
+ msecs_to_jiffies(UL_TIMEOUT_DELAY));
+ mutex_unlock(&wakeup_lock);
+}
+
+static void reconnect_to_bam(void)
+{
+ int i;
+
+ vote_dfab();
+ i = sps_device_reset(a2_device_handle);
+ if (i)
+ pr_err("%s: device reset failed rc = %d\n", __func__, i);
+ i = sps_connect(bam_tx_pipe, &tx_connection);
+ if (i)
+ pr_err("%s: tx connection failed rc = %d\n", __func__, i);
+ i = sps_connect(bam_rx_pipe, &rx_connection);
+ if (i)
+ pr_err("%s: rx connection failed rc = %d\n", __func__, i);
+ i = sps_register_event(bam_tx_pipe, &tx_register_event);
+ if (i)
+ pr_err("%s: tx event reg failed rc = %d\n", __func__, i);
+ i = sps_register_event(bam_rx_pipe, &rx_register_event);
+ if (i)
+ pr_err("%s: rx event reg failed rc = %d\n", __func__, i);
+ for (i = 0; i < NUM_BUFFERS; ++i)
+ queue_rx();
+ toggle_apps_ack();
+ complete_all(&bam_connection_completion);
+}
+
+static void disconnect_to_bam(void)
+{
+ struct list_head *node;
+ struct rx_pkt_info *info;
+
+ INIT_COMPLETION(bam_connection_completion);
+ sps_disconnect(bam_tx_pipe);
+ sps_disconnect(bam_rx_pipe);
+ unvote_dfab();
+ __memzero(rx_desc_mem_buf.base, rx_desc_mem_buf.size);
+ __memzero(tx_desc_mem_buf.base, tx_desc_mem_buf.size);
+ while (!list_empty(&bam_rx_pool)) {
+ node = bam_rx_pool.next;
+ list_del(node);
+ info = container_of(node, struct rx_pkt_info, list_node);
+ dma_unmap_single(NULL, info->dma_address, BUFFER_SIZE,
+ DMA_FROM_DEVICE);
+ dev_kfree_skb_any(info->skb);
+ kfree(info);
+ }
+}
+
+static void vote_dfab(void)
+{
+ int rc;
+
+ rc = clk_enable(dfab_clk);
+ if (rc)
+ pr_err("bam_dmux vote for dfab failed rc = %d\n", rc);
+}
+
+static void unvote_dfab(void)
+{
+ clk_disable(dfab_clk);
+}
+
static void bam_init(void)
{
u32 h;
@@ -716,6 +850,7 @@
void *a2_virt_addr;
int i;
+ vote_dfab();
/* init BAM */
a2_virt_addr = ioremap_nocache(A2_PHYS_BASE, A2_PHYS_SIZE);
if (!a2_virt_addr) {
@@ -735,6 +870,7 @@
pr_err("%s: register bam error %d\n", __func__, ret);
goto register_bam_failed;
}
+ a2_device_handle = h;
bam_tx_pipe = sps_alloc_endpoint();
if (bam_tx_pipe == NULL) {
@@ -836,6 +972,8 @@
bam_mux_initialized = 1;
for (i = 0; i < NUM_BUFFERS; ++i)
queue_rx();
+ toggle_apps_ack();
+ complete_all(&bam_connection_completion);
return;
rx_event_reg_failed:
@@ -860,11 +998,22 @@
return;
}
+static void toggle_apps_ack(void)
+{
+ static unsigned int clear_bit; /* 0 = set the bit, else clear bit */
+ smsm_change_state(SMSM_APPS_STATE,
+ clear_bit & SMSM_A2_POWER_CONTROL_ACK,
+ ~clear_bit & SMSM_A2_POWER_CONTROL_ACK);
+ clear_bit = ~clear_bit;
+}
+
static void bam_dmux_smsm_cb(void *priv, uint32_t old_state, uint32_t new_state)
{
DBG("%s: smsm activity\n", __func__);
- if (bam_mux_initialized)
- pr_err("%s: bam_dmux already initialized\n", __func__);
+ if (bam_mux_initialized && new_state & SMSM_A2_POWER_CONTROL)
+ reconnect_to_bam();
+ else if (bam_mux_initialized && !(new_state & SMSM_A2_POWER_CONTROL))
+ disconnect_to_bam();
else if (new_state & SMSM_A2_POWER_CONTROL)
bam_init();
else
@@ -872,6 +1021,12 @@
}
+static void bam_dmux_smsm_ack_cb(void *priv, uint32_t old_state,
+ uint32_t new_state)
+{
+ complete_all(&ul_wakeup_ack_completion);
+}
+
static int bam_dmux_probe(struct platform_device *pdev)
{
int rc;
@@ -880,6 +1035,16 @@
if (bam_mux_initialized)
return 0;
+ dfab_clk = clk_get(&pdev->dev, "dfab_clk");
+ if (IS_ERR(dfab_clk)) {
+ pr_err("%s: did not get dfab clock\n", __func__);
+ return -EFAULT;
+ }
+
+ rc = clk_set_rate(dfab_clk, 64000000);
+ if (rc)
+ pr_err("%s: unable to set dfab clock rate\n", __func__);
+
bam_mux_rx_workqueue = create_singlethread_workqueue("bam_dmux_rx");
if (!bam_mux_rx_workqueue)
return -ENOMEM;
@@ -904,6 +1069,10 @@
}
}
+ init_completion(&ul_wakeup_ack_completion);
+ init_completion(&bam_connection_completion);
+ INIT_DELAYED_WORK(&ul_timeout_work, ul_timeout);
+
rc = smsm_state_cb_register(SMSM_MODEM_STATE, SMSM_A2_POWER_CONTROL,
bam_dmux_smsm_cb, NULL);
@@ -914,6 +1083,22 @@
return -ENOMEM;
}
+ rc = smsm_state_cb_register(SMSM_MODEM_STATE, SMSM_A2_POWER_CONTROL_ACK,
+ bam_dmux_smsm_ack_cb, NULL);
+
+ if (rc) {
+ destroy_workqueue(bam_mux_rx_workqueue);
+ destroy_workqueue(bam_mux_tx_workqueue);
+ smsm_state_cb_deregister(SMSM_MODEM_STATE,
+ SMSM_A2_POWER_CONTROL,
+ bam_dmux_smsm_cb, NULL);
+ pr_err("%s: smsm ack cb register failed, rc: %d\n", __func__,
+ rc);
+ for (rc = 0; rc < BAM_DMUX_NUM_CHANNELS; ++rc)
+ platform_device_put(bam_ch[rc].pdev);
+ return -ENOMEM;
+ }
+
return 0;
}
diff --git a/arch/arm/mach-msm/board-9615-regulator.c b/arch/arm/mach-msm/board-9615-regulator.c
index 2cef2bb..d7d630d 100644
--- a/arch/arm/mach-msm/board-9615-regulator.c
+++ b/arch/arm/mach-msm/board-9615-regulator.c
@@ -12,6 +12,7 @@
*/
#include <linux/regulator/pm8018-regulator.h>
+#include <mach/rpm-regulator.h>
#include "board-9615.h"
@@ -155,34 +156,130 @@
.pin_ctrl = _pin_ctrl, \
}
+#define RPM_INIT(_id, _min_uV, _max_uV, _modes, _ops, _apply_uV, _default_uV, \
+ _peak_uA, _avg_uA, _pull_down, _pin_ctrl, _freq, _pin_fn, \
+ _force_mode, _power_mode, _state, _sleep_selectable, \
+ _always_on, _supply_regulator, _system_uA) \
+ { \
+ .init_data = { \
+ .constraints = { \
+ .valid_modes_mask = _modes, \
+ .valid_ops_mask = _ops, \
+ .min_uV = _min_uV, \
+ .max_uV = _max_uV, \
+ .input_uV = _min_uV, \
+ .apply_uV = _apply_uV, \
+ .always_on = _always_on, \
+ }, \
+ .num_consumer_supplies = \
+ ARRAY_SIZE(vreg_consumers_##_id), \
+ .consumer_supplies = vreg_consumers_##_id, \
+ .supply_regulator = _supply_regulator, \
+ }, \
+ .id = RPM_VREG_ID_PM8018_##_id, \
+ .default_uV = _default_uV, \
+ .peak_uA = _peak_uA, \
+ .avg_uA = _avg_uA, \
+ .pull_down_enable = _pull_down, \
+ .pin_ctrl = _pin_ctrl, \
+ .freq = RPM_VREG_FREQ_##_freq, \
+ .pin_fn = _pin_fn, \
+ .force_mode = _force_mode, \
+ .power_mode = _power_mode, \
+ .state = _state, \
+ .sleep_selectable = _sleep_selectable, \
+ .system_uA = _system_uA, \
+ }
+
+#define RPM_LDO(_id, _always_on, _pd, _sleep_selectable, _min_uV, _max_uV, \
+ _supply_regulator, _system_uA, _init_peak_uA) \
+ RPM_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_NORMAL \
+ | REGULATOR_MODE_IDLE, REGULATOR_CHANGE_VOLTAGE \
+ | REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE \
+ | REGULATOR_CHANGE_DRMS, 0, _max_uV, _init_peak_uA, 0, _pd, \
+ RPM_VREG_PIN_CTRL_NONE, NONE, RPM_VREG_PIN_FN_9615_NONE, \
+ RPM_VREG_FORCE_MODE_9615_NONE, RPM_VREG_POWER_MODE_9615_PWM, \
+ RPM_VREG_STATE_OFF, _sleep_selectable, _always_on, \
+ _supply_regulator, _system_uA)
+
+#define RPM_SMPS(_id, _always_on, _pd, _sleep_selectable, _min_uV, _max_uV, \
+ _supply_regulator, _system_uA, _freq) \
+ RPM_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_NORMAL \
+ | REGULATOR_MODE_IDLE, REGULATOR_CHANGE_VOLTAGE \
+ | REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE \
+ | REGULATOR_CHANGE_DRMS, 0, _max_uV, _system_uA, 0, _pd, \
+ RPM_VREG_PIN_CTRL_NONE, _freq, RPM_VREG_PIN_FN_9615_NONE, \
+ RPM_VREG_FORCE_MODE_9615_NONE, RPM_VREG_POWER_MODE_9615_PWM, \
+ RPM_VREG_STATE_OFF, _sleep_selectable, _always_on, \
+ _supply_regulator, _system_uA)
+
+#define RPM_VS(_id, _always_on, _pd, _sleep_selectable, _supply_regulator) \
+ RPM_INIT(_id, 0, 0, 0, REGULATOR_CHANGE_STATUS, 0, 0, 1000, 1000, _pd, \
+ RPM_VREG_PIN_CTRL_NONE, NONE, RPM_VREG_PIN_FN_9615_NONE, \
+ RPM_VREG_FORCE_MODE_9615_NONE, RPM_VREG_POWER_MODE_9615_PWM, \
+ RPM_VREG_STATE_OFF, _sleep_selectable, _always_on, \
+ _supply_regulator, 0)
+
+/* Pin control initialization */
+#define RPM_PC_INIT(_id, _always_on, _pin_fn, _pin_ctrl, _supply_regulator) \
+ { \
+ .init_data = { \
+ .constraints = { \
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS, \
+ .always_on = _always_on, \
+ }, \
+ .num_consumer_supplies = \
+ ARRAY_SIZE(vreg_consumers_##_id##_PC), \
+ .consumer_supplies = vreg_consumers_##_id##_PC, \
+ .supply_regulator = _supply_regulator, \
+ }, \
+ .id = RPM_VREG_ID_PM8018_##_id##_PC, \
+ .pin_fn = RPM_VREG_PIN_FN_9615_##_pin_fn, \
+ .pin_ctrl = _pin_ctrl, \
+ }
+
+
/* PM8018 regulator constraints */
struct pm8018_regulator_platform_data
msm_pm8018_regulator_pdata[] __devinitdata = {
- /* ID a_on pd min_uV max_uV en_t supply sys_uA */
- PM8018_VREG_INIT_SMPS(S1, 1, 1, 1150000, 1150000, 500, NULL, 100000),
- PM8018_VREG_INIT_SMPS(S2, 0, 1, 1225000, 1300000, 500, NULL, 0),
- PM8018_VREG_INIT_SMPS(S3, 1, 1, 1800000, 1800000, 500, NULL, 100000),
- PM8018_VREG_INIT_SMPS(S4, 0, 1, 2100000, 2200000, 500, NULL, 0),
- PM8018_VREG_INIT_SMPS(S5, 1, 1, 1350000, 1350000, 500, NULL, 100000),
+};
- PM8018_VREG_INIT_LDO(L2, 1, 1, 1800000, 1800000, 200, NULL, 10000),
- PM8018_VREG_INIT_LDO(L3, 0, 1, 1800000, 1800000, 200, NULL, 0),
- PM8018_VREG_INIT_LDO(L4, 0, 1, 3075000, 3075000, 200, NULL, 0),
- PM8018_VREG_INIT_LDO(L5, 0, 1, 2850000, 2850000, 200, NULL, 0),
- PM8018_VREG_INIT_LDO(L6, 0, 1, 1800000, 2850000, 200, NULL, 0),
- PM8018_VREG_INIT_LDO(L7, 0, 1, 1850000, 1900000, 200, "8018_s4", 0),
- PM8018_VREG_INIT_LDO(L8, 0, 1, 1200000, 1200000, 200, "8018_s3", 0),
- PM8018_VREG_INIT_LDO(L9, 1, 1, 1150000, 1150000, 200, "8018_s5",
- 10000),
- PM8018_VREG_INIT_LDO(L10, 0, 1, 1050000, 1050000, 200, "8018_s5", 0),
- PM8018_VREG_INIT_LDO(L11, 0, 1, 1050000, 1050000, 200, "8018_s5", 0),
- PM8018_VREG_INIT_LDO(L12, 0, 1, 1050000, 1050000, 200, "8018_s5", 0),
- PM8018_VREG_INIT_LDO(L13, 0, 1, 2950000, 2950000, 200, NULL, 0),
- PM8018_VREG_INIT_LDO(L14, 0, 1, 2850000, 2850000, 200, NULL, 0),
+static struct rpm_regulator_init_data
+msm_rpm_regulator_init_data[] __devinitdata = {
+ /* ID a_on pd ss min_uV max_uV supply sys_uA freq */
+ RPM_SMPS(S1, 1, 1, 1, 1150000, 1150000, NULL, 100000, 1p60),
+ RPM_SMPS(S2, 0, 1, 0, 1225000, 1300000, NULL, 0, 1p60),
+ RPM_SMPS(S3, 1, 1, 0, 1800000, 1800000, NULL, 100000, 1p60),
+ RPM_SMPS(S4, 0, 1, 0, 2100000, 2200000, NULL, 0, 1p60),
+ RPM_SMPS(S5, 1, 1, 0, 1350000, 1350000, NULL, 100000, 1p60),
- /* ID a_on pd en_t supply */
- PM8018_VREG_INIT_VS(LVS1, 0, 1, 0, "8018_s3"),
+ /* ID a_on pd ss min_uV max_uV supply sys_uA init_ip */
+ RPM_LDO(L2, 1, 1, 0, 1800000, 1800000, NULL, 0, 10000),
+ RPM_LDO(L3, 0, 1, 0, 1800000, 1800000, NULL, 0, 0),
+ RPM_LDO(L4, 0, 1, 0, 3075000, 3075000, NULL, 0, 0),
+ RPM_LDO(L5, 0, 1, 0, 2850000, 2850000, NULL, 0, 0),
+ RPM_LDO(L6, 0, 1, 0, 1800000, 2850000, NULL, 0, 0),
+ RPM_LDO(L7, 0, 1, 0, 1850000, 1900000, "8018_s4", 0, 0),
+ RPM_LDO(L8, 0, 1, 0, 1200000, 1200000, "8018_s3", 0, 0),
+ RPM_LDO(L9, 1, 1, 1, 1150000, 1150000, "8018_s5", 10000, 10000),
+ RPM_LDO(L10, 0, 1, 0, 1050000, 1050000, "8018_s5", 0, 0),
+ RPM_LDO(L11, 0, 1, 0, 1050000, 1050000, "8018_s5", 0, 0),
+ RPM_LDO(L12, 0, 1, 0, 1050000, 1050000, "8018_s5", 0, 0),
+ RPM_LDO(L13, 0, 1, 0, 2950000, 2950000, NULL, 0, 0),
+ RPM_LDO(L14, 0, 1, 0, 2850000, 2850000, NULL, 0, 0),
+
+ /* ID a_on pd ss supply */
+ RPM_VS(LVS1, 0, 1, 0, "8018_s3"),
};
int msm_pm8018_regulator_pdata_len __devinitdata =
ARRAY_SIZE(msm_pm8018_regulator_pdata);
+
+struct rpm_regulator_platform_data
+msm_rpm_regulator_9615_pdata __devinitdata = {
+ .init_data = msm_rpm_regulator_init_data,
+ .num_regulators = ARRAY_SIZE(msm_rpm_regulator_init_data),
+ .version = RPM_VREG_VERSION_9615,
+ .vreg_id_vdd_mem = RPM_VREG_ID_PM8018_L9,
+ .vreg_id_vdd_dig = RPM_VREG_ID_PM8018_S1,
+};
diff --git a/arch/arm/mach-msm/board-9615.c b/arch/arm/mach-msm/board-9615.c
index 87ff559..40cbee0 100644
--- a/arch/arm/mach-msm/board-9615.c
+++ b/arch/arm/mach-msm/board-9615.c
@@ -22,34 +22,14 @@
#include <mach/gpio.h>
#include <mach/gpiomux.h>
#include <mach/msm_spi.h>
+#include <linux/usb/android.h>
+#include <linux/usb/msm_hsusb.h>
#include "timer.h"
#include "devices.h"
#include "board-9615.h"
#include "cpuidle.h"
#include "pm.h"
-
-static struct platform_device *common_devices[] = {
- &msm9615_device_dmov,
- &msm_device_smd,
- &msm9615_device_uart_gsbi4,
- &msm9615_device_ssbi_pmic1,
- &msm9615_device_qup_i2c_gsbi5,
- &msm9615_device_qup_spi_gsbi3,
- &msm_device_sps,
- &msm9615_device_tsens,
- &msm_device_nand,
- &msm_rpm_device,
-
-#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
- defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
- &qcrypto_device,
-#endif
-
-#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
- defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
- &qcedev_device,
-#endif
-};
+#include "acpuclock.h"
static struct pm8xxx_irq_platform_data pm8xxx_irq_pdata __devinitdata = {
.irq_base = PM8018_IRQ_BASE,
@@ -67,6 +47,7 @@
static struct pm8xxx_rtc_platform_data pm8xxx_rtc_pdata __devinitdata = {
.rtc_write_enable = false,
+ .rtc_alarm_powerup = false,
};
static struct pm8xxx_pwrkey_platform_data pm8xxx_pwrkey_pdata = {
@@ -97,6 +78,14 @@
},
};
+static struct platform_device msm9615_device_rpm_regulator __devinitdata = {
+ .name = "rpm-regulator",
+ .id = -1,
+ .dev = {
+ .platform_data = &msm_rpm_regulator_9615_pdata,
+ },
+};
+
static struct gpiomux_setting ps_hold = {
.func = GPIOMUX_FUNC_1,
.drv = GPIOMUX_DRV_8MA,
@@ -206,117 +195,6 @@
},
};
-#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
- defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE) || \
- defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
- defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
-
-#define QCE_SIZE 0x10000
-#define QCE_0_BASE 0x18500000
-
-#define QCE_HW_KEY_SUPPORT 0
-#define QCE_SHA_HMAC_SUPPORT 1
-#define QCE_SHARE_CE_RESOURCE 1
-#define QCE_CE_SHARED 0
-
-static struct resource qcrypto_resources[] = {
- [0] = {
- .start = QCE_0_BASE,
- .end = QCE_0_BASE + QCE_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "crypto_channels",
- .start = DMOV_CE_IN_CHAN,
- .end = DMOV_CE_OUT_CHAN,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .name = "crypto_crci_in",
- .start = DMOV_CE_IN_CRCI,
- .end = DMOV_CE_IN_CRCI,
- .flags = IORESOURCE_DMA,
- },
- [3] = {
- .name = "crypto_crci_out",
- .start = DMOV_CE_OUT_CRCI,
- .end = DMOV_CE_OUT_CRCI,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct resource qcedev_resources[] = {
- [0] = {
- .start = QCE_0_BASE,
- .end = QCE_0_BASE + QCE_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "crypto_channels",
- .start = DMOV_CE_IN_CHAN,
- .end = DMOV_CE_OUT_CHAN,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .name = "crypto_crci_in",
- .start = DMOV_CE_IN_CRCI,
- .end = DMOV_CE_IN_CRCI,
- .flags = IORESOURCE_DMA,
- },
- [3] = {
- .name = "crypto_crci_out",
- .start = DMOV_CE_OUT_CRCI,
- .end = DMOV_CE_OUT_CRCI,
- .flags = IORESOURCE_DMA,
- },
-};
-
-#endif
-
-#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
- defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
-
-static struct msm_ce_hw_support qcrypto_ce_hw_suppport = {
- .ce_shared = QCE_CE_SHARED,
- .shared_ce_resource = QCE_SHARE_CE_RESOURCE,
- .hw_key_support = QCE_HW_KEY_SUPPORT,
- .sha_hmac = QCE_SHA_HMAC_SUPPORT,
-};
-
-static struct platform_device qcrypto_device = {
- .name = "qcrypto",
- .id = 0,
- .num_resources = ARRAY_SIZE(qcrypto_resources),
- .resource = qcrypto_resources,
- .dev = {
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &qcrypto_ce_hw_suppport,
- },
-};
-#endif
-
-#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
- defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
-
-static struct msm_ce_hw_support qcedev_ce_hw_suppport = {
- .ce_shared = QCE_CE_SHARED,
- .shared_ce_resource = QCE_SHARE_CE_RESOURCE,
- .hw_key_support = QCE_HW_KEY_SUPPORT,
- .sha_hmac = QCE_SHA_HMAC_SUPPORT,
-};
-
-static struct platform_device qcedev_device = {
- .name = "qce",
- .id = 0,
- .num_resources = ARRAY_SIZE(qcedev_resources),
- .resource = qcedev_resources,
- .dev = {
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &qcedev_ce_hw_suppport,
- },
-};
-#endif
-
#if (defined(CONFIG_MMC_MSM_SDC1_SUPPORT)\
|| defined(CONFIG_MMC_MSM_SDC2_SUPPORT))
@@ -610,6 +488,59 @@
.src_clk_rate = 24000000,
};
+static struct msm_otg_platform_data msm_otg_pdata = {
+ .mode = USB_PERIPHERAL,
+ .otg_control = OTG_NO_CONTROL,
+ .phy_type = SNPS_28NM_INTEGRATED_PHY,
+ .pclk_src_name = "dfab_usb_hs_clk",
+};
+
+static int usb_diag_update_pid_and_serial_num(uint32_t pid, const char *snum)
+{
+ return 0;
+}
+
+static struct android_usb_platform_data android_usb_pdata = {
+ .update_pid_and_serial_num = usb_diag_update_pid_and_serial_num,
+};
+
+static struct platform_device android_usb_device = {
+ .name = "android_usb",
+ .id = -1,
+ .dev = {
+ .platform_data = &android_usb_pdata,
+ },
+};
+
+static struct platform_device *common_devices[] = {
+ &msm9615_device_dmov,
+ &msm_device_smd,
+ &msm_device_otg,
+ &msm_device_gadget_peripheral,
+ &android_usb_device,
+ &msm9615_device_uart_gsbi4,
+ &msm9615_device_ssbi_pmic1,
+ &msm9615_device_qup_i2c_gsbi5,
+ &msm9615_device_qup_spi_gsbi3,
+ &msm_device_sps,
+ &msm9615_device_tsens,
+ &msm_device_nand,
+ &msm_rpm_device,
+#ifdef CONFIG_HW_RANDOM_MSM
+ &msm_device_rng,
+#endif
+
+#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
+ defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
+ &msm9615_qcrypto_device,
+#endif
+
+#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
+ defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
+ &msm9615_qcedev_device,
+#endif
+};
+
static void __init msm9615_i2c_init(void)
{
msm9615_device_qup_i2c_gsbi5.dev.platform_data =
@@ -622,13 +553,20 @@
gpiomux_init();
msm9615_i2c_init();
regulator_suppress_info_printing();
+ platform_device_register(&msm9615_device_rpm_regulator);
msm9615_device_qup_spi_gsbi3.dev.platform_data =
&msm9615_qup_spi_gsbi3_pdata;
msm9615_device_ssbi_pmic1.dev.platform_data =
&msm9615_ssbi_pm8018_pdata;
pm8018_platform_data.num_regulators = msm_pm8018_regulator_pdata_len;
+
+ msm_device_otg.dev.platform_data = &msm_otg_pdata;
+ msm_device_gadget_peripheral.dev.parent = &msm_device_otg.dev;
platform_add_devices(common_devices, ARRAY_SIZE(common_devices));
+ msm_clock_init(&msm9615_clock_init_data);
+ acpuclk_init(&acpuclk_9615_soc_data);
+
msm9615_init_mmc();
msm_pm_set_platform_data(msm_pm_data, ARRAY_SIZE(msm_pm_data));
msm_pm_set_rpm_wakeup_irq(RPM_APCC_CPU0_WAKE_UP_IRQ);
diff --git a/arch/arm/mach-msm/board-9615.h b/arch/arm/mach-msm/board-9615.h
index d8e74fe..0d9fae7 100644
--- a/arch/arm/mach-msm/board-9615.h
+++ b/arch/arm/mach-msm/board-9615.h
@@ -29,4 +29,7 @@
extern int msm_pm8018_regulator_pdata_len __devinitdata;
+extern struct rpm_regulator_platform_data
+msm_rpm_regulator_9615_pdata __devinitdata;
+
#endif
diff --git a/arch/arm/mach-msm/board-apq8064.c b/arch/arm/mach-msm/board-apq8064.c
index d37fb7b..4328b85 100644
--- a/arch/arm/mach-msm/board-apq8064.c
+++ b/arch/arm/mach-msm/board-apq8064.c
@@ -36,6 +36,18 @@
#include "board-apq8064.h"
+static struct platform_device android_usb_device = {
+ .name = "android_usb",
+ .id = -1,
+};
+
+static struct msm_otg_platform_data msm_otg_pdata = {
+ .mode = USB_PERIPHERAL,
+ .otg_control = OTG_PHY_CONTROL,
+ .phy_type = SNPS_28NM_INTEGRATED_PHY,
+ .pclk_src_name = "dfab_usb_hs_clk",
+};
+
/* APQ8064 have 4 SDCC controllers */
enum sdcc_controllers {
SDCC1,
@@ -310,6 +322,9 @@
&apq8064_device_ssbi_pmic1,
&apq8064_device_ssbi_pmic2,
&msm_device_smd_apq8064,
+ &apq8064_device_otg,
+ &apq8064_device_gadget_peripheral,
+ &android_usb_device,
};
static struct platform_device *sim_devices[] __initdata = {
@@ -326,13 +341,6 @@
.max_clock_speed = 26000000,
};
-static struct msm_otg_platform_data msm_otg_pdata = {
- .mode = USB_PERIPHERAL,
- .otg_control = OTG_PHY_CONTROL,
- .phy_type = SNPS_28NM_INTEGRATED_PHY,
- .pclk_src_name = "dfab_usb_hs_clk",
-};
-
#define KS8851_IRQ_GPIO 43
static struct spi_board_info spi_board_info[] __initdata = {
diff --git a/arch/arm/mach-msm/board-msm7x27.c b/arch/arm/mach-msm/board-msm7x27.c
index 9629b5c..22de352 100644
--- a/arch/arm/mach-msm/board-msm7x27.c
+++ b/arch/arm/mach-msm/board-msm7x27.c
@@ -1862,6 +1862,7 @@
.init_machine = msm7x2x_init,
.timer = &msm_timer,
.init_early = msm7x27_init_early,
+ .handle_irq = vic_handle_irq,
MACHINE_END
MACHINE_START(MSM7X27_FFA, "QCT MSM7x27 FFA")
@@ -1872,6 +1873,7 @@
.init_machine = msm7x2x_init,
.timer = &msm_timer,
.init_early = msm7x27_init_early,
+ .handle_irq = vic_handle_irq,
MACHINE_END
MACHINE_START(MSM7X25_SURF, "QCT MSM7x25 SURF")
@@ -1882,6 +1884,7 @@
.init_machine = msm7x2x_init,
.timer = &msm_timer,
.init_early = msm7x27_init_early,
+ .handle_irq = vic_handle_irq,
MACHINE_END
MACHINE_START(MSM7X25_FFA, "QCT MSM7x25 FFA")
@@ -1892,4 +1895,5 @@
.init_machine = msm7x2x_init,
.timer = &msm_timer,
.init_early = msm7x27_init_early,
+ .handle_irq = vic_handle_irq,
MACHINE_END
diff --git a/arch/arm/mach-msm/board-msm7x27a.c b/arch/arm/mach-msm/board-msm7x27a.c
index 67b1dcc..44939e7 100644
--- a/arch/arm/mach-msm/board-msm7x27a.c
+++ b/arch/arm/mach-msm/board-msm7x27a.c
@@ -1841,10 +1841,16 @@
static int msm_fb_detect_panel(const char *name)
{
- if (!strncmp(name, MIPI_CMD_RENESAS_FWVGA_PANEL_NAME,
- strnlen(MIPI_CMD_RENESAS_FWVGA_PANEL_NAME,
- PANEL_NAME_MAX_LEN)))
- return 0;
+ int ret = -ENODEV;
+
+ if (machine_is_msm7x27a_surf() || machine_is_msm7625a_surf()) {
+ if (!strncmp(name, "lcdc_toshiba_fwvga_pt", 21) ||
+ !strncmp(name, "mipi_cmd_renesas_fwvga", 22))
+ ret = 0;
+ } else if (machine_is_msm7x27a_ffa()) {
+ if (!strncmp(name, "mipi_cmd_renesas_fwvga", 22))
+ ret = 0;
+ }
#if !defined(CONFIG_FB_MSM_LCDC_AUTO_DETECT) && \
!defined(CONFIG_FB_MSM_MIPI_PANEL_AUTO_DETECT) && \
@@ -1857,7 +1863,7 @@
return 0;
}
#endif
- return -ENODEV;
+ return ret;
}
static struct msm_fb_platform_data msm_fb_pdata = {
@@ -1916,6 +1922,7 @@
SND(FM_DIGITAL_STEREO_HEADSET, 26),
SND(FM_DIGITAL_SPEAKER_PHONE, 27),
SND(FM_DIGITAL_BT_A2DP_HEADSET, 28),
+ SND(STEREO_HEADSET_AND_SPEAKER, 31),
SND(CURRENT, 0x7FFFFFFE),
SND(FM_ANALOG_STEREO_HEADSET, 35),
SND(FM_ANALOG_STEREO_HEADSET_CODEC, 36),
@@ -3249,6 +3256,7 @@
.init_machine = msm7627a_rumi3_init,
.timer = &msm_timer,
.init_early = msm7x2x_init_early,
+ .handle_irq = vic_handle_irq,
MACHINE_END
MACHINE_START(MSM7X27A_SURF, "QCT MSM7x27a SURF")
.boot_params = PHYS_OFFSET + 0x100,
@@ -3258,6 +3266,7 @@
.init_machine = msm7x2x_init,
.timer = &msm_timer,
.init_early = msm7x2x_init_early,
+ .handle_irq = vic_handle_irq,
MACHINE_END
MACHINE_START(MSM7X27A_FFA, "QCT MSM7x27a FFA")
.boot_params = PHYS_OFFSET + 0x100,
@@ -3267,6 +3276,7 @@
.init_machine = msm7x2x_init,
.timer = &msm_timer,
.init_early = msm7x2x_init_early,
+ .handle_irq = vic_handle_irq,
MACHINE_END
MACHINE_START(MSM7625A_SURF, "QCT MSM7625a SURF")
.boot_params = PHYS_OFFSET + 0x100,
@@ -3276,6 +3286,7 @@
.init_machine = msm7x2x_init,
.timer = &msm_timer,
.init_early = msm7x2x_init_early,
+ .handle_irq = vic_handle_irq,
MACHINE_END
MACHINE_START(MSM7625A_FFA, "QCT MSM7625a FFA")
.boot_params = PHYS_OFFSET + 0x100,
@@ -3285,4 +3296,5 @@
.init_machine = msm7x2x_init,
.timer = &msm_timer,
.init_early = msm7x2x_init_early,
+ .handle_irq = vic_handle_irq,
MACHINE_END
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
index fa53e3d..b71061a 100644
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ b/arch/arm/mach-msm/board-msm7x30.c
@@ -7229,6 +7229,7 @@
.init_machine = msm7x30_init,
.timer = &msm_timer,
.init_early = msm7x30_init_early,
+ .handle_irq = vic_handle_irq,
MACHINE_END
MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA")
@@ -7239,6 +7240,7 @@
.init_machine = msm7x30_init,
.timer = &msm_timer,
.init_early = msm7x30_init_early,
+ .handle_irq = vic_handle_irq,
MACHINE_END
MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID")
@@ -7249,6 +7251,7 @@
.init_machine = msm7x30_init,
.timer = &msm_timer,
.init_early = msm7x30_init_early,
+ .handle_irq = vic_handle_irq,
MACHINE_END
MACHINE_START(MSM8X55_SURF, "QCT MSM8X55 SURF")
@@ -7259,6 +7262,7 @@
.init_machine = msm7x30_init,
.timer = &msm_timer,
.init_early = msm7x30_init_early,
+ .handle_irq = vic_handle_irq,
MACHINE_END
MACHINE_START(MSM8X55_FFA, "QCT MSM8X55 FFA")
@@ -7269,6 +7273,7 @@
.init_machine = msm7x30_init,
.timer = &msm_timer,
.init_early = msm7x30_init_early,
+ .handle_irq = vic_handle_irq,
MACHINE_END
MACHINE_START(MSM8X55_SVLTE_SURF, "QCT MSM8X55 SVLTE SURF")
.boot_params = PHYS_OFFSET + 0x100,
@@ -7278,6 +7283,7 @@
.init_machine = msm7x30_init,
.timer = &msm_timer,
.init_early = msm7x30_init_early,
+ .handle_irq = vic_handle_irq,
MACHINE_END
MACHINE_START(MSM8X55_SVLTE_FFA, "QCT MSM8X55 SVLTE FFA")
.boot_params = PHYS_OFFSET + 0x100,
@@ -7287,4 +7293,5 @@
.init_machine = msm7x30_init,
.timer = &msm_timer,
.init_early = msm7x30_init_early,
+ .handle_irq = vic_handle_irq,
MACHINE_END
diff --git a/arch/arm/mach-msm/board-msm8960-regulator.c b/arch/arm/mach-msm/board-msm8960-regulator.c
index e3f0e31..ca24e79 100644
--- a/arch/arm/mach-msm/board-msm8960-regulator.c
+++ b/arch/arm/mach-msm/board-msm8960-regulator.c
@@ -146,6 +146,7 @@
REGULATOR_SUPPLY("8921_s3", NULL),
REGULATOR_SUPPLY("HSUSB_VDDCX", "msm_otg"),
REGULATOR_SUPPLY("riva_vddcx", "wcnss_wlan.0"),
+ REGULATOR_SUPPLY("HSIC_VDDCX", "msm_hsic_host"),
};
VREG_CONSUMERS(S4) = {
REGULATOR_SUPPLY("8921_s4", NULL),
diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c
index 058bc47..10d1cd5 100644
--- a/arch/arm/mach-msm/board-msm8960.c
+++ b/arch/arm/mach-msm/board-msm8960.c
@@ -233,7 +233,13 @@
.pull = GPIOMUX_PULL_DOWN,
};
-static struct gpiomux_setting gsbi3 = {
+static struct gpiomux_setting gsbi3_suspended_cfg = {
+ .func = GPIOMUX_FUNC_1,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_KEEPER,
+};
+
+static struct gpiomux_setting gsbi3_active_cfg = {
.func = GPIOMUX_FUNC_1,
.drv = GPIOMUX_DRV_8MA,
.pull = GPIOMUX_PULL_NONE,
@@ -347,13 +353,15 @@
{
.gpio = 16, /* GSBI3 I2C QUP SDA */
.settings = {
- [GPIOMUX_SUSPENDED] = &gsbi3,
+ [GPIOMUX_SUSPENDED] = &gsbi3_suspended_cfg,
+ [GPIOMUX_ACTIVE] = &gsbi3_active_cfg,
},
},
{
.gpio = 17, /* GSBI3 I2C QUP SCL */
.settings = {
- [GPIOMUX_SUSPENDED] = &gsbi3,
+ [GPIOMUX_SUSPENDED] = &gsbi3_suspended_cfg,
+ [GPIOMUX_ACTIVE] = &gsbi3_active_cfg,
},
},
{
@@ -703,6 +711,37 @@
},
};
+#ifdef CONFIG_USB_EHCI_MSM_HSIC
+static struct gpiomux_setting hsic_act_cfg = {
+ .func = GPIOMUX_FUNC_1,
+ .drv = GPIOMUX_DRV_12MA,
+ .pull = GPIOMUX_PULL_NONE,
+};
+
+static struct gpiomux_setting hsic_sus_cfg = {
+ .func = GPIOMUX_FUNC_GPIO,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_DOWN,
+};
+
+static struct msm_gpiomux_config msm8960_hsic_configs[] = {
+ {
+ .gpio = 150, /*HSIC_STROBE */
+ .settings = {
+ [GPIOMUX_ACTIVE] = &hsic_act_cfg,
+ [GPIOMUX_SUSPENDED] = &hsic_sus_cfg,
+ },
+ },
+ {
+ .gpio = 151, /* HSIC_DATA */
+ .settings = {
+ [GPIOMUX_ACTIVE] = &hsic_act_cfg,
+ [GPIOMUX_SUSPENDED] = &hsic_sus_cfg,
+ },
+ },
+};
+#endif
+
#if defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)
enum {
SX150X_CAM,
@@ -2537,6 +2576,11 @@
msm_gpiomux_install(wcnss_5wire_interface,
ARRAY_SIZE(wcnss_5wire_interface));
+#ifdef CONFIG_USB_EHCI_MSM_HSIC
+ msm_gpiomux_install(msm8960_hsic_configs,
+ ARRAY_SIZE(msm8960_hsic_configs));
+#endif
+
return 0;
}
@@ -2964,6 +3008,15 @@
};
#endif
+#ifdef CONFIG_USB_EHCI_MSM_HSIC
+static struct msm_hsic_host_platform_data msm_hsic_pdata = {
+ .strobe = 150,
+ .data = 151,
+};
+#else
+static struct msm_hsic_host_platform_data msm_hsic_pdata;
+#endif
+
#define PID_MAGIC_ID 0x71432909
#define SERIAL_NUM_MAGIC_ID 0x61945374
#define SERIAL_NUMBER_LENGTH 127
@@ -3275,46 +3328,46 @@
/* configuration data */
static const u8 mxt_config_data[] = {
/* T6 Object */
- 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0,
/* T38 Object */
- 11, 0, 0, 6, 9, 11, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0,
+ 11, 1, 0, 20, 10, 11, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0,
/* T7 Object */
- 10, 10, 50,
+ 100, 16, 50,
/* T8 Object */
- 8, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 8, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* T9 Object */
- 131, 0, 0, 26, 42, 0, 32, 60, 2, 5,
- 0, 5, 5, 34, 10, 10, 10, 10, 85, 5,
- 255, 2, 8, 9, 9, 9, 0, 0, 5, 20,
- 0, 5, 45, 46,
+ 131, 0, 0, 26, 42, 0, 32, 60, 2, 5,
+ 0, 5, 5, 34, 10, 10, 10, 10, 255, 2,
+ 85, 5, 18, 18, 18, 18, 0, 0, 5, 20,
+ 0, 5, 45, 46,
/* T15 Object */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0,
/* T22 Object */
- 0, 0, 0, 0, 0, 0, 0, 0, 30, 0,
- 0, 0, 255, 255, 255, 255, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 30, 0,
+ 0, 0, 255, 255, 255, 255, 0,
/* T24 Object */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* T25 Object */
- 3, 0, 188, 52, 52, 33, 0, 0, 0, 0,
- 0, 0, 0, 0,
+ 3, 0, 188, 52, 52, 33, 0, 0, 0, 0,
+ 0, 0, 0, 0,
/* T27 Object */
- 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0,
/* T28 Object */
- 0, 0, 0, 8, 8, 8,
+ 0, 0, 0, 8, 8, 60,
/* T40 Object */
- 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0,
/* T41 Object */
- 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0,
/* T43 Object */
- 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0,
};
#define MXT_TS_GPIO_IRQ 11
@@ -3382,15 +3435,10 @@
static struct mxt_platform_data mxt_platform_data = {
.config = mxt_config_data,
.config_length = ARRAY_SIZE(mxt_config_data),
- .x_line = 26,
- .y_line = 42,
- .x_size = 767,
- .y_size = 1365,
- .blen = 32,
- .threshold = 40,
- .voltage = 3300000, /* 3.3V */
- .orient = MXT_ROTATED_90,
+ .x_size = 1365,
+ .y_size = 767,
.irqflags = IRQF_TRIGGER_FALLING,
+ .i2c_pull_up = true,
};
static struct i2c_board_info mxt_device_info[] __initdata = {
@@ -4426,6 +4474,7 @@
msm8960_device_otg.dev.platform_data = &msm_otg_pdata;
msm8960_device_gadget_peripheral.dev.parent = &msm8960_device_otg.dev;
msm_device_hsusb_host.dev.parent = &msm8960_device_otg.dev;
+ msm_device_hsic_host.dev.platform_data = &msm_hsic_pdata;
gpiomux_init();
if (machine_is_msm8960_cdp())
fpga_init();
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index dab800f..6141e1f 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -2548,19 +2548,15 @@
*/
if (machine_is_msm8x60_fluid()) {
/* fluid has different firmware, gpios */
- peripheral_dsps.name = DSPS_PIL_FLUID_NAME;
pdata->pil_name = DSPS_PIL_FLUID_NAME;
pdata->gpios = dsps_fluid_gpios;
pdata->gpios_num = ARRAY_SIZE(dsps_fluid_gpios);
} else {
- peripheral_dsps.name = DSPS_PIL_GENERIC_NAME;
pdata->pil_name = DSPS_PIL_GENERIC_NAME;
pdata->gpios = dsps_surf_gpios;
pdata->gpios_num = ARRAY_SIZE(dsps_surf_gpios);
}
- msm_pil_add_device(&peripheral_dsps);
-
platform_device_register(&msm_dsps_device);
}
#endif /* CONFIG_MSM_DSPS */
diff --git a/arch/arm/mach-msm/board-qrd7627a.c b/arch/arm/mach-msm/board-qrd7627a.c
index b09352c..ff392eb 100644
--- a/arch/arm/mach-msm/board-qrd7627a.c
+++ b/arch/arm/mach-msm/board-qrd7627a.c
@@ -13,7 +13,7 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/gpio_event.h>
-#include <linux/usb/android_composite.h>
+#include <linux/usb/android.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/gpio.h>
@@ -957,100 +957,8 @@
#endif
-static char *usb_functions_default[] = {
- "diag",
- "modem",
- "nmea",
- "rmnet",
- "usb_mass_storage",
-};
-
-static char *usb_functions_default_adb[] = {
- "diag",
- "adb",
- "modem",
- "nmea",
- "rmnet",
- "usb_mass_storage",
-};
-
-static char *usb_functions_rndis[] = {
- "rndis",
-};
-
-static char *usb_functions_rndis_adb[] = {
- "rndis",
- "adb",
-};
-
-static char *usb_functions_all[] = {
-#ifdef CONFIG_USB_ANDROID_RNDIS
- "rndis",
-#endif
-#ifdef CONFIG_USB_ANDROID_DIAG
- "diag",
-#endif
- "adb",
-#ifdef CONFIG_USB_F_SERIAL
- "modem",
- "nmea",
-#endif
-#ifdef CONFIG_USB_ANDROID_RMNET
- "rmnet",
-#endif
- "usb_mass_storage",
-};
-
-static struct android_usb_product usb_products[] = {
- {
- .product_id = 0x9026,
- .num_functions = ARRAY_SIZE(usb_functions_default),
- .functions = usb_functions_default,
- },
- {
- .product_id = 0x9025,
- .num_functions = ARRAY_SIZE(usb_functions_default_adb),
- .functions = usb_functions_default_adb,
- },
- {
- .product_id = 0xf00e,
- .num_functions = ARRAY_SIZE(usb_functions_rndis),
- .functions = usb_functions_rndis,
- },
- {
- .product_id = 0x9024,
- .num_functions = ARRAY_SIZE(usb_functions_rndis_adb),
- .functions = usb_functions_rndis_adb,
- },
-};
-
-static struct usb_mass_storage_platform_data mass_storage_pdata = {
- .nluns = 1,
- .vendor = "Qualcomm Incorporated",
- .product = "Mass storage",
- .release = 0x0100,
-
-};
-
-static struct platform_device usb_mass_storage_device = {
- .name = "usb_mass_storage",
- .id = -1,
- .dev = {
- .platform_data = &mass_storage_pdata,
- },
-};
-
static struct android_usb_platform_data android_usb_pdata = {
- .vendor_id = 0x05C6,
- .product_id = 0x9026,
- .version = 0x0100,
- .product_name = "Qualcomm HSUSB Device",
- .manufacturer_name = "Qualcomm Incorporated",
- .num_products = ARRAY_SIZE(usb_products),
- .products = usb_products,
- .num_functions = ARRAY_SIZE(usb_functions_all),
- .functions = usb_functions_all,
- .serial_number = "1234567890ABCDEF",
+ .update_pid_and_serial_num = usb_diag_update_pid_and_serial_num,
};
static struct platform_device android_usb_device = {
@@ -1061,38 +969,6 @@
},
};
-static struct usb_ether_platform_data rndis_pdata = {
- .vendorID = 0x05C6,
- .vendorDescr = "Qualcomm Incorporated",
-};
-
-static struct platform_device rndis_device = {
- .name = "rndis",
- .id = -1,
- .dev = {
- .platform_data = &rndis_pdata,
- },
-};
-
-static int __init board_serialno_setup(char *serialno)
-{
- int i;
- char *src = serialno;
-
- /* create a fake MAC address from our serial number.
- * first byte is 0x02 to signify locally administered.
- */
- rndis_pdata.ethaddr[0] = 0x02;
- for (i = 0; *src; i++) {
- /* XOR the USB serial across the remaining bytes */
- rndis_pdata.ethaddr[i % (ETH_ALEN - 1) + 1] ^= *src++;
- }
-
- android_usb_pdata.serial_number = serialno;
- return 1;
-}
-__setup("androidboot.serialno=", board_serialno_setup);
-
#ifdef CONFIG_USB_EHCI_MSM_72K
static void msm_hsusb_vbus_power(unsigned phy_info, int on)
{
@@ -1579,6 +1455,57 @@
early_param("fb_size", fb_size_setup);
+static struct resource msm_fb_resources[] = {
+ {
+ .flags = IORESOURCE_DMA,
+ }
+};
+
+static int msm_fb_detect_panel(const char *name)
+{
+ int ret;
+
+ if (!strncmp(name, "mipi_video_truly_wvga", 21))
+ ret = 0;
+ else
+ ret = -ENODEV;
+
+ return ret;
+}
+
+static int mipi_truly_set_bl(int on)
+{
+ gpio_set_value_cansleep(GPIO_BACKLIGHT_EN, !!on);
+
+ return 1;
+}
+
+static struct msm_fb_platform_data msm_fb_pdata = {
+ .detect_client = msm_fb_detect_panel,
+};
+
+static struct platform_device msm_fb_device = {
+ .name = "msm_fb",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(msm_fb_resources),
+ .resource = msm_fb_resources,
+ .dev = {
+ .platform_data = &msm_fb_pdata,
+ }
+};
+
+static struct msm_panel_common_pdata mipi_truly_pdata = {
+ .pmic_backlight = mipi_truly_set_bl,
+};
+
+static struct platform_device mipi_dsi_truly_panel_device = {
+ .name = "mipi_truly",
+ .id = 0,
+ .dev = {
+ .platform_data = &mipi_truly_pdata,
+ }
+};
+
static void __init msm7627a_init_mmc(void)
{
vreg_emmc = vreg_get(NULL, "emmc");
@@ -1637,7 +1564,8 @@
SND(FM_DIGITAL_STEREO_HEADSET, 26),
SND(FM_DIGITAL_SPEAKER_PHONE, 27),
SND(FM_DIGITAL_BT_A2DP_HEADSET, 28),
- SND(CURRENT, 34),
+ SND(STEREO_HEADSET_AND_SPEAKER, 31),
+ SND(CURRENT, 0x7FFFFFFE),
SND(FM_ANALOG_STEREO_HEADSET, 35),
SND(FM_ANALOG_STEREO_HEADSET_CODEC, 36),
};
@@ -1824,10 +1752,7 @@
&android_usb_device,
&android_pmem_device,
&android_pmem_adsp_device,
- &usb_mass_storage_device,
- &rndis_device,
- &usb_diag_device,
- &usb_gadget_fserial_device,
+ &msm_fb_device,
&android_pmem_audio_device,
&msm_device_snd,
&msm_device_adspdec,
@@ -1836,6 +1761,7 @@
#ifdef CONFIG_BT
&msm_bt_power_device,
#endif
+ &mipi_dsi_truly_panel_device,
&msm_wlan_ar6000_pm_device,
&asoc_msm_pcm,
&asoc_msm_dai0,
@@ -1860,7 +1786,15 @@
static void __init msm_msm7627a_allocate_memory_regions(void)
{
- pr_info("Dummy allocation for fb\n");
+ void *addr;
+ unsigned long size;
+
+ size = fb_size ? : MSM_FB_SIZE;
+ addr = alloc_bootmem_align(size, 0x1000);
+ msm_fb_resources[0].start = __pa(addr);
+ msm_fb_resources[0].end = msm_fb_resources[0].start + size - 1;
+ pr_info("allocating %lu bytes at %p (%lx physical) for fb\n", size,
+ addr, __pa(addr));
}
static struct memtype_reserve msm7627a_reserve_table[] __initdata = {
@@ -1874,6 +1808,159 @@
},
};
+static struct msm_panel_common_pdata mdp_pdata = {
+ .gpio = 97,
+ .mdp_rev = MDP_REV_303,
+};
+
+#define GPIO_LCDC_BRDG_PD 128
+#define GPIO_LCDC_BRDG_RESET_N 129
+#define GPIO_LCD_DSI_SEL 125
+
+static unsigned mipi_dsi_gpio[] = {
+ GPIO_CFG(GPIO_LCDC_BRDG_RESET_N, 0, GPIO_CFG_OUTPUT,
+ GPIO_CFG_NO_PULL, GPIO_CFG_2MA), /* LCDC_BRDG_RESET_N */
+ GPIO_CFG(GPIO_LCDC_BRDG_PD, 0, GPIO_CFG_OUTPUT,
+ GPIO_CFG_NO_PULL, GPIO_CFG_2MA), /* LCDC_BRDG_PD */
+};
+
+static unsigned lcd_dsi_sel_gpio[] = {
+ GPIO_CFG(GPIO_LCD_DSI_SEL, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP,
+ GPIO_CFG_2MA),
+};
+
+enum {
+ DSI_SINGLE_LANE = 1,
+ DSI_TWO_LANES,
+};
+
+static int msm_fb_get_lane_config(void)
+{
+ pr_info("DSI_TWO_LANES\n");
+ return DSI_TWO_LANES;
+}
+
+static int mipi_truly_sel_mode(int video_mode)
+{
+ int rc = 0;
+
+ rc = gpio_request(GPIO_LCD_DSI_SEL, "lcd_dsi_sel");
+ if (rc < 0)
+ goto gpio_error;
+
+ rc = gpio_tlmm_config(lcd_dsi_sel_gpio[0], GPIO_CFG_ENABLE);
+ if (rc)
+ goto gpio_error;
+
+ rc = gpio_direction_output(GPIO_LCD_DSI_SEL, 1);
+ if (!rc) {
+ gpio_set_value_cansleep(GPIO_LCD_DSI_SEL, video_mode);
+ return rc;
+ } else {
+ goto gpio_error;
+ }
+
+gpio_error:
+ pr_err("mipi_truly_sel_mode failed\n");
+ gpio_free(GPIO_LCD_DSI_SEL);
+ return rc;
+}
+
+static int msm_fb_dsi_client_qrd1_reset(void)
+{
+ int rc = 0;
+
+ rc = gpio_request(GPIO_LCDC_BRDG_RESET_N, "lcdc_brdg_reset_n");
+ if (rc < 0) {
+ pr_err("failed to request lcd brdg reset_n\n");
+ return rc;
+ }
+
+ rc = gpio_tlmm_config(mipi_dsi_gpio[0], GPIO_CFG_ENABLE);
+ if (rc < 0) {
+ pr_err("Failed to enable LCDC Bridge reset enable\n");
+ return rc;
+ }
+
+ rc = gpio_direction_output(GPIO_LCDC_BRDG_RESET_N, 1);
+ if (rc < 0) {
+ pr_err("Failed GPIO bridge pd\n");
+ gpio_free(GPIO_LCDC_BRDG_RESET_N);
+ return rc;
+ }
+
+ mipi_truly_sel_mode(1);
+
+ return rc;
+}
+
+static int msm_fb_dsi_client_reset(void)
+{
+ int rc = 0;
+
+ rc = msm_fb_dsi_client_qrd1_reset();
+ return rc;
+}
+
+static int dsi_gpio_initialized;
+
+static int mipi_dsi_panel_qrd1_power(int on)
+{
+ int rc = 0;
+
+ if (!dsi_gpio_initialized) {
+ rc = gpio_request(GPIO_BACKLIGHT_EN, "gpio_bkl_en");
+ if (rc < 0)
+ return rc;
+
+ rc = gpio_direction_output(GPIO_BACKLIGHT_EN, 1);
+ if (rc < 0) {
+ pr_err("failed to enable backlight\n");
+ gpio_free(GPIO_BACKLIGHT_EN);
+ return rc;
+ }
+ dsi_gpio_initialized = 1;
+ }
+
+ gpio_set_value_cansleep(GPIO_BACKLIGHT_EN, !!on);
+
+ if (!on) {
+ gpio_set_value_cansleep(GPIO_LCDC_BRDG_RESET_N, 1);
+ msleep(20);
+ gpio_set_value_cansleep(GPIO_LCDC_BRDG_RESET_N, 0);
+ msleep(20);
+ gpio_set_value_cansleep(GPIO_LCDC_BRDG_RESET_N, 1);
+
+ }
+
+ return rc;
+}
+
+static int mipi_dsi_panel_power(int on)
+{
+ int rc = 0;
+
+ rc = mipi_dsi_panel_qrd1_power(on);
+ return rc;
+}
+
+#define MDP_303_VSYNC_GPIO 97
+
+#ifdef CONFIG_FB_MSM_MDP303
+static struct mipi_dsi_platform_data mipi_dsi_pdata = {
+ .vsync_gpio = MDP_303_VSYNC_GPIO,
+ .dsi_power_save = mipi_dsi_panel_power,
+ .dsi_client_reset = msm_fb_dsi_client_reset,
+ .get_lane_config = msm_fb_get_lane_config,
+};
+#endif
+
+static void __init msm_fb_add_devices(void)
+{
+ msm_fb_register_device("mdp", &mdp_pdata);
+ msm_fb_register_device("mipi_dsi", &mipi_dsi_pdata);
+}
+
static void __init size_pmem_devices(void)
{
#ifdef CONFIG_ANDROID_PMEM
@@ -1966,6 +2053,7 @@
#endif
msm_pm_set_platform_data(msm7627a_pm_data,
ARRAY_SIZE(msm7627a_pm_data));
+ msm_fb_add_devices();
#if defined(CONFIG_BT) && defined(CONFIG_MARIMBA_CORE)
i2c_register_board_info(MSM_GSBI1_QUP_I2C_BUS_ID,
@@ -1993,4 +2081,5 @@
.init_machine = msm_qrd1_init,
.timer = &msm_timer,
.init_early = qrd7627a_init_early,
+ .handle_irq = vic_handle_irq,
MACHINE_END
diff --git a/arch/arm/mach-msm/clock-8960.c b/arch/arm/mach-msm/clock-8960.c
index ea2d9d2..ee122ec 100644
--- a/arch/arm/mach-msm/clock-8960.c
+++ b/arch/arm/mach-msm/clock-8960.c
@@ -297,6 +297,11 @@
#define LCC_PCM_MD_REG REG_LPA(0x0058)
#define LCC_PCM_NS_REG REG_LPA(0x0054)
#define LCC_PCM_STATUS_REG REG_LPA(0x005C)
+#define LCC_PLL0_MODE_REG REG_LPA(0x0000)
+#define LCC_PLL0_L_VAL_REG REG_LPA(0x0004)
+#define LCC_PLL0_M_VAL_REG REG_LPA(0x0008)
+#define LCC_PLL0_N_VAL_REG REG_LPA(0x000C)
+#define LCC_PLL0_CONFIG_REG REG_LPA(0x0014)
#define LCC_PLL0_STATUS_REG REG_LPA(0x0018)
#define LCC_SPARE_I2S_MIC_MD_REG REG_LPA(0x007C)
#define LCC_SPARE_I2S_MIC_NS_REG REG_LPA(0x0078)
@@ -308,6 +313,7 @@
#define LCC_SLIMBUS_MD_REG REG_LPA(0x00D0)
#define LCC_SLIMBUS_STATUS_REG REG_LPA(0x00D4)
#define LCC_AHBEX_BRANCH_CTL_REG REG_LPA(0x00E4)
+#define LCC_PRI_PLL_CLK_CTL_REG REG_LPA(0x00C4)
#define GCC_APCS_CLK_DIAG REG_GCC(0x001C)
@@ -326,7 +332,7 @@
#define pll0_to_mm_mux 3
#define pll15_to_mm_mux 3 /* or MM_PLL3 */
#define gnd_to_mm_mux 4
-#define pll3_to_mm_mux 5 /* used in 8960 */
+#define pll3_to_mm_mux 3 /* or MMCC_PLL2 */
#define hdmi_pll_to_mm_mux 3
#define cxo_to_xo_mux 0
#define pxo_to_xo_mux 1
@@ -4939,7 +4945,7 @@
CLK_LOOKUP("cxo", cxo_clk.c, NULL),
CLK_LOOKUP("pll2", pll2_clk.c, NULL),
CLK_LOOKUP("pll8", pll8_clk.c, NULL),
- CLK_DUMMY("pll4", PLL4, NULL, 0),
+ CLK_LOOKUP("pll4", pll4_clk.c, NULL),
CLK_LOOKUP("measure", measure_clk.c, "debug"),
CLK_DUMMY("afab_clk", AFAB_CLK, NULL, 0),
@@ -4982,12 +4988,12 @@
CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
CLK_LOOKUP("tsif_ref_clk", tsif_ref_clk.c, NULL),
CLK_LOOKUP("tssc_clk", tssc_clk.c, NULL),
- CLK_DUMMY("usb_hs_clk", USB_HS1_XCVR_CLK, NULL, OFF),
+ CLK_LOOKUP("usb_hs_clk", usb_hs1_xcvr_clk.c, NULL),
CLK_LOOKUP("core_clk", usb_hs3_xcvr_clk.c, NULL),
CLK_LOOKUP("core_clk", usb_hs4_xcvr_clk.c, NULL),
- CLK_DUMMY("usb_fs_src_clk", USB_FS1_SRC_CLK, NULL, OFF),
- CLK_DUMMY("usb_fs_clk", USB_FS1_XCVR_CLK, NULL, OFF),
- CLK_DUMMY("usb_fs_sys_clk", USB_FS1_SYS_CLK, NULL, OFF),
+ CLK_LOOKUP("usb_fs_src_clk", usb_fs1_src_clk.c, NULL),
+ CLK_LOOKUP("usb_fs_clk", usb_fs1_xcvr_clk.c, NULL),
+ CLK_LOOKUP("usb_fs_sys_clk", usb_fs1_sys_clk.c, NULL),
CLK_LOOKUP("ce_pclk", ce1_p_clk.c, NULL),
CLK_LOOKUP("ce_clk", ce1_core_clk.c, NULL),
CLK_LOOKUP("sata_phy_ref_clk", sata_phy_ref_clk.c, NULL),
@@ -5001,8 +5007,8 @@
CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, NULL),
CLK_LOOKUP("tsif_pclk", tsif_p_clk.c, NULL),
- CLK_DUMMY("usb_fs_pclk", USB_FS1_P_CLK, NULL, OFF),
- CLK_DUMMY("usb_hs_pclk", USB_HS1_P_CLK, NULL, OFF),
+ CLK_LOOKUP("usb_fs_pclk", usb_fs1_p_clk.c, NULL),
+ CLK_LOOKUP("usb_hs_pclk", usb_hs1_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", usb_hs3_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", usb_hs4_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"),
@@ -5098,17 +5104,18 @@
CLK_LOOKUP("iface_clk", vcodec_p_clk.c, NULL),
CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, NULL),
CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, NULL),
- CLK_DUMMY("mi2s_osr_clk", MI2S_OSR_CLK, NULL, OFF),
- CLK_DUMMY("mi2s_bit_clk", MI2S_BIT_CLK, NULL, OFF),
- CLK_DUMMY("i2s_mic_osr_clk", CODEC_I2S_MIC_OSR_CLK, NULL, OFF),
- CLK_DUMMY("i2s_mic_bit_clk", CODEC_I2S_MIC_BIT_CLK, NULL, OFF),
- CLK_DUMMY("i2s_mic_osr_clk", SPARE_I2S_MIC_OSR_CLK, NULL, OFF),
- CLK_DUMMY("i2s_mic_bit_clk", SPARE_I2S_MIC_BIT_CLK, NULL, OFF),
- CLK_DUMMY("i2s_spkr_osr_clk", CODEC_I2S_SPKR_OSR_CLK, NULL, OFF),
- CLK_DUMMY("i2s_spkr_bit_clk", CODEC_I2S_SPKR_BIT_CLK, NULL, OFF),
- CLK_DUMMY("i2s_spkr_osr_clk", SPARE_I2S_SPKR_OSR_CLK, NULL, OFF),
- CLK_DUMMY("i2s_spkr_bit_clk", SPARE_I2S_SPKR_BIT_CLK, NULL, OFF),
- CLK_DUMMY("pcm_clk", PCM_CLK, NULL, OFF),
+ CLK_LOOKUP("mi2s_bit_clk", mi2s_bit_clk.c, NULL),
+ CLK_LOOKUP("mi2s_osr_clk", mi2s_osr_clk.c, NULL),
+ CLK_LOOKUP("i2s_mic_bit_clk", codec_i2s_mic_bit_clk.c, NULL),
+ CLK_LOOKUP("i2s_mic_osr_clk", codec_i2s_mic_osr_clk.c, NULL),
+ CLK_LOOKUP("i2s_mic_bit_clk", spare_i2s_mic_bit_clk.c, NULL),
+ CLK_LOOKUP("i2s_mic_osr_clk", spare_i2s_mic_osr_clk.c, NULL),
+ CLK_LOOKUP("i2s_spkr_bit_clk", codec_i2s_spkr_bit_clk.c, NULL),
+ CLK_LOOKUP("i2s_spkr_osr_clk", codec_i2s_spkr_osr_clk.c, NULL),
+ CLK_LOOKUP("i2s_spkr_bit_clk", spare_i2s_spkr_bit_clk.c, NULL),
+ CLK_LOOKUP("i2s_spkr_osr_clk", spare_i2s_spkr_osr_clk.c, NULL),
+ CLK_LOOKUP("pcm_clk", pcm_clk.c, NULL),
+ CLK_DUMMY("sps_slimbus_clk", SPS_SLIMBUS_CLK, NULL, OFF),
CLK_DUMMY("audio_slimbus_clk", AUDIO_SLIMBUS_CLK, NULL, OFF),
CLK_LOOKUP("core_clk", jpegd_axi_clk.c, NULL),
CLK_LOOKUP("core_clk", vpe_axi_clk.c, NULL),
@@ -5152,6 +5159,7 @@
CLK_LOOKUP("afab_a_clk", afab_a_clk.c, NULL),
CLK_LOOKUP("cfpb_clk", cfpb_clk.c, NULL),
CLK_LOOKUP("cfpb_a_clk", cfpb_a_clk.c, NULL),
+ CLK_LOOKUP("cfpb_a_clk", cfpb_a_clk.c, "clock-8960"),
CLK_LOOKUP("dfab_clk", dfab_clk.c, NULL),
CLK_LOOKUP("dfab_a_clk", dfab_a_clk.c, NULL),
CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL),
@@ -5190,6 +5198,8 @@
CLK_LOOKUP("core_clk", gsbi10_qup_clk.c, "qup_i2c.10"),
CLK_LOOKUP("core_clk", gsbi11_qup_clk.c, NULL),
CLK_LOOKUP("core_clk", gsbi12_qup_clk.c, "qup_i2c.12"),
+ CLK_LOOKUP("tsif_pclk", tsif_p_clk.c, NULL),
+ CLK_LOOKUP("tsif_ref_clk", tsif_ref_clk.c, NULL),
CLK_LOOKUP("pdm_clk", pdm_clk.c, NULL),
CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_sps"),
CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"),
@@ -5445,13 +5455,19 @@
/* Deassert MM SW_RESET_ALL signal. */
writel_relaxed(0, SW_RESET_ALL_REG);
+ /*
+ * Some bits are only used on either 8960 or 8064 and are marked as
+ * reserved bits on the other SoC. Writing to these reserved bits
+ * should have no effect.
+ */
/* Initialize MM AHB registers: Enable the FPB clock and disable HW
* gating for all clocks. Also set VFE_AHB's FORCE_CORE_ON bit to
* prevent its memory from being collapsed when the clock is halted.
* The sleep and wake-up delays are set to safe values. */
rmwreg(0x00000003, AHB_EN_REG, 0x6C000103);
writel_relaxed(0x000007F9, AHB_EN2_REG);
- rmwreg(0x00000000, AHB_EN3_REG, 0x00000001);
+ if (cpu_is_apq8064())
+ rmwreg(0x00000000, AHB_EN3_REG, 0x00000001);
/* Deassert all locally-owned MM AHB resets. */
rmwreg(0, SW_RESET_AHB_REG, 0xFFF7DFFF);
@@ -5465,7 +5481,8 @@
rmwreg(0x3027FCFF, MAXI_EN2_REG, 0x3A3FFFFF);
rmwreg(0x0027FCFF, MAXI_EN3_REG, 0x003FFFFF);
rmwreg(0x0027FCFF, MAXI_EN4_REG, 0x017FFFFF);
- rmwreg(0x009FE4FF, MAXI_EN5_REG, 0x01FFEFFF);
+ if (cpu_is_apq8064())
+ rmwreg(0x009FE4FF, MAXI_EN5_REG, 0x01FFEFFF);
rmwreg(0x000003C7, SAXI_EN_REG, 0x00003FFF);
/* Initialize MM CC registers: Set MM FORCE_CORE_ON bits so that core
@@ -5477,22 +5494,26 @@
rmwreg(0x80FF0000, DSI2_BYTE_CC_REG, 0xE0FF0010);
rmwreg(0x80FF0000, DSI_PIXEL_CC_REG, 0xE0FF0010);
rmwreg(0x80FF0000, DSI2_PIXEL_CC_REG, 0xE0FF0010);
- rmwreg(0x80FF0000, GFX2D0_CC_REG, 0xE0FF0010);
- rmwreg(0x80FF0000, GFX2D1_CC_REG, 0xE0FF0010);
rmwreg(0x80FF0000, GFX3D_CC_REG, 0xE0FF0010);
rmwreg(0x80FF0000, IJPEG_CC_REG, 0xE0FF0010);
rmwreg(0x80FF0000, JPEGD_CC_REG, 0xE0FF0010);
rmwreg(0x80FF0000, MDP_CC_REG, 0xE1FF0010);
rmwreg(0x80FF0000, MDP_LUT_CC_REG, 0xE0FF0010);
rmwreg(0x80FF0000, ROT_CC_REG, 0xE0FF0010);
- rmwreg(0x80FF0000, TV_CC_REG, 0xE1FFC010);
rmwreg(0x000004FF, TV_CC2_REG, 0x000007FF);
rmwreg(0xC0FF0000, VCODEC_CC_REG, 0xE0FF0010);
rmwreg(0x80FF0000, VFE_CC_REG, 0xE0FF4010);
rmwreg(0x800000FF, VFE_CC2_REG, 0xE00000FF);
rmwreg(0x80FF0000, VPE_CC_REG, 0xE0FF0010);
- if (cpu_is_apq8064())
+ if (cpu_is_msm8960()) {
+ rmwreg(0x80FF0000, GFX2D0_CC_REG, 0xE0FF0010);
+ rmwreg(0x80FF0000, GFX2D1_CC_REG, 0xE0FF0010);
+ rmwreg(0x80FF0000, TV_CC_REG, 0xE1FFC010);
+ }
+ if (cpu_is_apq8064()) {
+ rmwreg(0x00000000, TV_CC_REG, 0x00004010);
rmwreg(0x80FF0000, VCAP_CC_REG, 0xE0FF1010);
+ }
/*
* Initialize USB_HS_HCLK_FS registers: Set FORCE_C_ON bits so that
@@ -5500,8 +5521,10 @@
* and wake-up value to max.
*/
rmwreg(0x0000004F, USB_HS1_HCLK_FS_REG, 0x0000007F);
- rmwreg(0x0000004F, USB_HS3_HCLK_FS_REG, 0x0000007F);
- rmwreg(0x0000004F, USB_HS4_HCLK_FS_REG, 0x0000007F);
+ if (cpu_is_apq8064()) {
+ rmwreg(0x0000004F, USB_HS3_HCLK_FS_REG, 0x0000007F);
+ rmwreg(0x0000004F, USB_HS4_HCLK_FS_REG, 0x0000007F);
+ }
/* De-assert MM AXI resets to all hardware blocks. */
writel_relaxed(0, SW_RESET_AXI_REG);
@@ -5527,7 +5550,8 @@
writel_relaxed(BIT(15), PDM_CLK_NS_REG);
/* Source SLIMBus xo src from slimbus reference clock */
- writel_relaxed(0x3, SLIMBUS_XO_SRC_CLK_CTL_REG);
+ if (cpu_is_msm8960())
+ writel_relaxed(0x3, SLIMBUS_XO_SRC_CLK_CTL_REG);
/* Source the dsi_byte_clks from the DSI PHY PLLs */
rmwreg(0x1, DSI1_BYTE_NS_REG, 0x7);
@@ -5671,6 +5695,33 @@
regval = readl_relaxed(MM_PLL3_TEST_CTL_REG);
regval |= BIT(12);
writel_relaxed(regval, MM_PLL3_TEST_CTL_REG);
+
+ /* Check if PLL4 is active */
+ is_pll_enabled = readl_relaxed(LCC_PLL0_STATUS_REG) & BIT(16);
+ if (!is_pll_enabled) {
+ /* Ref clk = 24.5MHz and program pll4 to 393.2160MHz */
+ writel_relaxed(0x10, LCC_PLL0_L_VAL_REG);
+ writel_relaxed(0x130, LCC_PLL0_M_VAL_REG);
+ writel_relaxed(0x17ED, LCC_PLL0_N_VAL_REG);
+
+ regval = readl_relaxed(LCC_PLL0_CONFIG_REG);
+
+ /* Enable the main output and the MN accumulator */
+ regval |= BIT(23) | BIT(22);
+
+ /* Set pre-divider and post-divider values to 1 and 1 */
+ regval &= ~BIT(19);
+ regval &= ~BM(21, 20);
+
+ /* Set VCO frequency */
+ regval &= ~BM(17, 16);
+ writel_relaxed(regval, LCC_PLL0_CONFIG_REG);
+
+ set_fsm_mode(LCC_PLL0_MODE_REG);
+ }
+
+ /* Enable PLL4 source on the LPASS Primary PLL Mux */
+ writel_relaxed(0x1, LCC_PRI_PLL_CLK_CTL_REG);
}
}
@@ -5744,13 +5795,18 @@
clk_set_rate(&usb_hsic_hsio_cal_clk.c, 9000000);
/*
- * The halt status bits for PDM and TSSC may be incorrect at boot.
+ * The halt status bits for these clocks may be incorrect at boot.
* Toggle these clocks on and off to refresh them.
*/
rcg_clk_enable(&pdm_clk.c);
rcg_clk_disable(&pdm_clk.c);
rcg_clk_enable(&tssc_clk.c);
rcg_clk_disable(&tssc_clk.c);
+ if (cpu_is_msm8960() &&
+ SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 2) {
+ clk_enable(&usb_hsic_hsic_clk.c);
+ clk_disable(&usb_hsic_hsic_clk.c);
+ }
if (machine_is_msm8960_sim()) {
clk_set_rate(&sdc1_clk.c, 48000000);
@@ -5766,6 +5822,7 @@
{
int rc;
struct clk *mmfpb_a_clk = clk_get_sys("clock-8960", "mmfpb_a_clk");
+ struct clk *cfpb_a_clk = clk_get_sys("clock-8960", "cfpb_a_clk");
/* Vote for MMFPB to be at least 76.8MHz when an Apps CPU is active. */
if (WARN(IS_ERR(mmfpb_a_clk), "mmfpb_a_clk not found (%ld)\n",
@@ -5778,6 +5835,16 @@
if (WARN(rc, "mmfpb_a_clk not enabled (%d)\n", rc))
return rc;
+ /* Vote for CFPB to be at least 64MHz when an Apps CPU is active. */
+ if (WARN(IS_ERR(cfpb_a_clk), "cfpb_a_clk not found (%ld)\n",
+ PTR_ERR(cfpb_a_clk)))
+ return PTR_ERR(cfpb_a_clk);
+ rc = clk_set_min_rate(cfpb_a_clk, 64000000);
+ if (WARN(rc, "cfpb_a_clk rate was not set (%d)\n", rc))
+ return rc;
+ rc = clk_enable(cfpb_a_clk);
+ if (WARN(rc, "cfpb_a_clk not enabled (%d)\n", rc))
+ return rc;
return local_unvote_sys_vdd(HIGH);
}
diff --git a/arch/arm/mach-msm/clock-9615.c b/arch/arm/mach-msm/clock-9615.c
index 9b9ac4a..63d3f72 100644
--- a/arch/arm/mach-msm/clock-9615.c
+++ b/arch/arm/mach-msm/clock-9615.c
@@ -27,6 +27,7 @@
#include <mach/clk.h>
#include <mach/msm_xo.h>
#include <mach/rpm-9615.h>
+#include <mach/rpm-regulator.h>
#include "clock-local.h"
#include "clock-voter.h"
@@ -290,17 +291,14 @@
/* Update the sys_vdd voltage given a level. */
static int msm9615_update_sys_vdd(enum sys_vdd_level level)
{
- /* TODO: Implement when rpm-regulator is ready.
static const int vdd_uv[] = {
- [NONE...LOW] = 945000,
- [NOMINAL] = 1050000,
+ [NONE...LOW] = 1150000,
+ [NOMINAL] = 1150000,
[HIGH] = 1150000,
};
- return rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S3, RPM_VREG_VOTER3,
+ return rpm_vreg_set_voltage(RPM_VREG_ID_PM8018_S1, RPM_VREG_VOTER3,
vdd_uv[level], vdd_uv[HIGH], 1);
- */
- return 0;
}
static int soc_clk_reset(struct clk *clk, enum clk_reset_action action)
@@ -1524,7 +1522,7 @@
CLK_LOOKUP("pdm_clk", pdm_clk.c, NULL),
CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_sps"),
- CLK_LOOKUP("prng_clk", prng_clk.c, NULL),
+ CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"),
CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
CLK_LOOKUP("ce_pclk", ce1_p_clk.c, NULL),
diff --git a/arch/arm/mach-msm/cpufreq.c b/arch/arm/mach-msm/cpufreq.c
index 637832d..2477221 100644
--- a/arch/arm/mach-msm/cpufreq.c
+++ b/arch/arm/mach-msm/cpufreq.c
@@ -190,7 +190,9 @@
cur_freq = acpuclk_get_rate(policy->cpu);
if (cpufreq_frequency_table_target(policy, table, cur_freq,
- CPUFREQ_RELATION_H, &index)) {
+ CPUFREQ_RELATION_H, &index) &&
+ cpufreq_frequency_table_target(policy, table, cur_freq,
+ CPUFREQ_RELATION_L, &index)) {
pr_info("cpufreq: cpu%d at invalid freq: %d\n",
policy->cpu, cur_freq);
return -EINVAL;
@@ -278,6 +280,11 @@
static SYSDEV_CLASS_ATTR(mfreq, 0200, NULL, store_mfreq);
+static struct freq_attr *msm_freq_attr[] = {
+ &cpufreq_freq_attr_scaling_available_freqs,
+ NULL,
+};
+
static struct cpufreq_driver msm_cpufreq_driver = {
/* lps calculations are handled here. */
.flags = CPUFREQ_STICKY | CPUFREQ_CONST_LOOPS,
@@ -285,6 +292,7 @@
.verify = msm_cpufreq_verify,
.target = msm_cpufreq_target,
.name = "msm",
+ .attr = msm_freq_attr,
};
static struct notifier_block msm_cpufreq_pm_notifier = {
diff --git a/arch/arm/mach-msm/devices-8064.c b/arch/arm/mach-msm/devices-8064.c
index 99e8d23..3606c41 100644
--- a/arch/arm/mach-msm/devices-8064.c
+++ b/arch/arm/mach-msm/devices-8064.c
@@ -21,6 +21,7 @@
#include <mach/msm_iomap.h>
#include <mach/usbdiag.h>
#include <mach/msm_sps.h>
+#include <mach/dma.h>
#include "clock.h"
#include "devices.h"
@@ -53,13 +54,21 @@
#define MSM_HSUSB_PHYS 0x12500000
#define MSM_HSUSB_SIZE SZ_4K
-
static struct resource msm_dmov_resource[] = {
{
.start = ADM_0_SCSS_0_IRQ,
- .end = (resource_size_t)MSM_DMOV_BASE,
.flags = IORESOURCE_IRQ,
},
+ {
+ .start = 0x18300000,
+ .end = 0x18300000 + SZ_1M - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct msm_dmov_pdata msm_dmov_pdata = {
+ .sd = 0,
+ .sd_size = 0x800,
};
struct platform_device apq8064_device_dmov = {
@@ -67,6 +76,9 @@
.id = -1,
.resource = msm_dmov_resource,
.num_resources = ARRAY_SIZE(msm_dmov_resource),
+ .dev = {
+ .platform_data = &msm_dmov_pdata,
+ },
};
static struct resource resources_uart_gsbi1[] = {
diff --git a/arch/arm/mach-msm/devices-8960.c b/arch/arm/mach-msm/devices-8960.c
index a92324c..e81e2e8 100644
--- a/arch/arm/mach-msm/devices-8960.c
+++ b/arch/arm/mach-msm/devices-8960.c
@@ -81,6 +81,9 @@
#define MSM_PMIC2_SSBI_CMD_PHYS 0x00C00000
#define MSM_PMIC_SSBI_SIZE SZ_4K
+#define MSM8960_HSUSB_PHYS 0x12500000
+#define MSM8960_HSUSB_SIZE SZ_4K
+
static struct resource resources_otg[] = {
{
.start = MSM8960_HSUSB_PHYS,
@@ -154,8 +157,8 @@
static struct resource resources_hsic_host[] = {
{
- .start = MSM_HSIC_PHYS,
- .end = MSM_HSIC_PHYS + MSM_HSIC_SIZE - 1,
+ .start = 0x12520000,
+ .end = 0x12520000 + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
{
@@ -800,9 +803,18 @@
static struct resource msm_dmov_resource[] = {
{
.start = ADM_0_SCSS_1_IRQ,
- .end = (resource_size_t)MSM_DMOV_BASE,
.flags = IORESOURCE_IRQ,
},
+ {
+ .start = 0x18320000,
+ .end = 0x18320000 + SZ_1M - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct msm_dmov_pdata msm_dmov_pdata = {
+ .sd = 1,
+ .sd_size = 0x800,
};
struct platform_device msm8960_device_dmov = {
@@ -810,6 +822,9 @@
.id = -1,
.resource = msm_dmov_resource,
.num_resources = ARRAY_SIZE(msm_dmov_resource),
+ .dev = {
+ .platform_data = &msm_dmov_pdata,
+ },
};
static struct platform_device *msm_sdcc_devices[] __initdata = {
diff --git a/arch/arm/mach-msm/devices-9615.c b/arch/arm/mach-msm/devices-9615.c
index d542b96..74e7871 100644
--- a/arch/arm/mach-msm/devices-9615.c
+++ b/arch/arm/mach-msm/devices-9615.c
@@ -16,10 +16,13 @@
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/msm_tsens.h>
+#include <linux/platform_data/qcom_crypto_device.h>
+#include <linux/dma-mapping.h>
#include <asm/hardware/gic.h>
#include <asm/mach/flash.h>
#include <mach/board.h>
#include <mach/msm_iomap.h>
+#include <mach/msm_hsusb.h>
#include <mach/irqs.h>
#include <mach/socinfo.h>
#include <mach/rpm.h>
@@ -27,7 +30,6 @@
#include <mach/msm_sps.h>
#include <mach/dma.h>
#include "devices.h"
-#include "acpuclock.h"
#include "mpm.h"
#include "spm.h"
#include "pm.h"
@@ -57,9 +59,18 @@
static struct resource msm_dmov_resource[] = {
{
.start = ADM_0_SCSS_1_IRQ,
- .end = (resource_size_t)MSM_DMOV_BASE,
.flags = IORESOURCE_IRQ,
},
+ {
+ .start = 0x18320000,
+ .end = 0x18320000 + SZ_1M - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct msm_dmov_pdata msm_dmov_pdata = {
+ .sd = 1,
+ .sd_size = 0x800,
};
struct platform_device msm9615_device_dmov = {
@@ -67,6 +78,55 @@
.id = -1,
.resource = msm_dmov_resource,
.num_resources = ARRAY_SIZE(msm_dmov_resource),
+ .dev = {
+ .platform_data = &msm_dmov_pdata,
+ },
+};
+
+static struct resource resources_otg[] = {
+ {
+ .start = MSM9615_HSUSB_PHYS,
+ .end = MSM9615_HSUSB_PHYS + MSM9615_HSUSB_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = USB1_HS_IRQ,
+ .end = USB1_HS_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device msm_device_otg = {
+ .name = "msm_otg",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(resources_otg),
+ .resource = resources_otg,
+ .dev = {
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+};
+
+static struct resource resources_hsusb[] = {
+ {
+ .start = MSM9615_HSUSB_PHYS,
+ .end = MSM9615_HSUSB_PHYS + MSM9615_HSUSB_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = USB1_HS_IRQ,
+ .end = USB1_HS_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device msm_device_gadget_peripheral = {
+ .name = "msm_hsusb",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(resources_hsusb),
+ .resource = resources_hsusb,
+ .dev = {
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
};
static struct resource resources_uart_gsbi4[] = {
@@ -257,6 +317,133 @@
.id = -1,
};
+#ifdef CONFIG_HW_RANDOM_MSM
+/* PRNG device */
+#define MSM_PRNG_PHYS 0x1A500000
+static struct resource rng_resources = {
+ .flags = IORESOURCE_MEM,
+ .start = MSM_PRNG_PHYS,
+ .end = MSM_PRNG_PHYS + SZ_512 - 1,
+};
+
+struct platform_device msm_device_rng = {
+ .name = "msm_rng",
+ .id = 0,
+ .num_resources = 1,
+ .resource = &rng_resources,
+};
+#endif
+
+#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
+ defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE) || \
+ defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
+ defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
+
+#define QCE_SIZE 0x10000
+#define QCE_0_BASE 0x18500000
+
+#define QCE_HW_KEY_SUPPORT 0
+#define QCE_SHA_HMAC_SUPPORT 1
+#define QCE_SHARE_CE_RESOURCE 1
+#define QCE_CE_SHARED 0
+
+static struct resource qcrypto_resources[] = {
+ [0] = {
+ .start = QCE_0_BASE,
+ .end = QCE_0_BASE + QCE_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .name = "crypto_channels",
+ .start = DMOV_CE_IN_CHAN,
+ .end = DMOV_CE_OUT_CHAN,
+ .flags = IORESOURCE_DMA,
+ },
+ [2] = {
+ .name = "crypto_crci_in",
+ .start = DMOV_CE_IN_CRCI,
+ .end = DMOV_CE_IN_CRCI,
+ .flags = IORESOURCE_DMA,
+ },
+ [3] = {
+ .name = "crypto_crci_out",
+ .start = DMOV_CE_OUT_CRCI,
+ .end = DMOV_CE_OUT_CRCI,
+ .flags = IORESOURCE_DMA,
+ },
+};
+
+static struct resource qcedev_resources[] = {
+ [0] = {
+ .start = QCE_0_BASE,
+ .end = QCE_0_BASE + QCE_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .name = "crypto_channels",
+ .start = DMOV_CE_IN_CHAN,
+ .end = DMOV_CE_OUT_CHAN,
+ .flags = IORESOURCE_DMA,
+ },
+ [2] = {
+ .name = "crypto_crci_in",
+ .start = DMOV_CE_IN_CRCI,
+ .end = DMOV_CE_IN_CRCI,
+ .flags = IORESOURCE_DMA,
+ },
+ [3] = {
+ .name = "crypto_crci_out",
+ .start = DMOV_CE_OUT_CRCI,
+ .end = DMOV_CE_OUT_CRCI,
+ .flags = IORESOURCE_DMA,
+ },
+};
+
+#endif
+
+#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
+ defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
+
+static struct msm_ce_hw_support qcrypto_ce_hw_suppport = {
+ .ce_shared = QCE_CE_SHARED,
+ .shared_ce_resource = QCE_SHARE_CE_RESOURCE,
+ .hw_key_support = QCE_HW_KEY_SUPPORT,
+ .sha_hmac = QCE_SHA_HMAC_SUPPORT,
+};
+
+struct platform_device msm9615_qcrypto_device = {
+ .name = "qcrypto",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(qcrypto_resources),
+ .resource = qcrypto_resources,
+ .dev = {
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .platform_data = &qcrypto_ce_hw_suppport,
+ },
+};
+#endif
+
+#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
+ defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
+
+static struct msm_ce_hw_support qcedev_ce_hw_suppport = {
+ .ce_shared = QCE_CE_SHARED,
+ .shared_ce_resource = QCE_SHARE_CE_RESOURCE,
+ .hw_key_support = QCE_HW_KEY_SUPPORT,
+ .sha_hmac = QCE_SHA_HMAC_SUPPORT,
+};
+
+struct platform_device msm9615_qcedev_device = {
+ .name = "qce",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(qcedev_resources),
+ .resource = qcedev_resources,
+ .dev = {
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .platform_data = &qcedev_ce_hw_suppport,
+ },
+};
+#endif
#define MSM_SDC1_BASE 0x12180000
#define MSM_SDC1_DML_BASE (MSM_SDC1_BASE + 0x800)
@@ -603,8 +790,6 @@
void __init msm9615_device_init(void)
{
msm_spm_init(msm_spm_data, ARRAY_SIZE(msm_spm_data));
- msm_clock_init(&msm9615_clock_init_data);
- acpuclk_init(&acpuclk_9615_soc_data);
BUG_ON(msm_rpm_init(&msm_rpm_data));
BUG_ON(msm_rpmrs_levels_init(msm_rpmrs_levels,
ARRAY_SIZE(msm_rpmrs_levels)));
diff --git a/arch/arm/mach-msm/devices-fsm9xxx.c b/arch/arm/mach-msm/devices-fsm9xxx.c
index 426be10..d46e4d6 100644
--- a/arch/arm/mach-msm/devices-fsm9xxx.c
+++ b/arch/arm/mach-msm/devices-fsm9xxx.c
@@ -232,12 +232,21 @@
* ADM
*/
-struct resource msm_dmov_resource[] = {
+static struct resource msm_dmov_resource[] = {
{
.start = INT_ADM_AARM,
- .end = (resource_size_t) MSM_DMOV_BASE,
.flags = IORESOURCE_IRQ,
},
+ {
+ .start = 0x94610000,
+ .end = 0x94610000 + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct msm_dmov_pdata msm_dmov_pdata = {
+ .sd = 3,
+ .sd_size = 0x400,
};
struct platform_device msm_device_dmov = {
@@ -245,6 +254,9 @@
.id = -1,
.resource = msm_dmov_resource,
.num_resources = ARRAY_SIZE(msm_dmov_resource),
+ .dev = {
+ .platform_data = &msm_dmov_pdata,
+ },
};
/*
diff --git a/arch/arm/mach-msm/devices-iommu.c b/arch/arm/mach-msm/devices-iommu.c
index a945349..73c96fb 100644
--- a/arch/arm/mach-msm/devices-iommu.c
+++ b/arch/arm/mach-msm/devices-iommu.c
@@ -15,6 +15,9 @@
#include <linux/bootmem.h>
#include <mach/irqs.h>
#include <mach/iommu.h>
+#include <mach/socinfo.h>
+#include <mach/irqs-8960.h>
+#include <mach/irqs-8064.h>
static struct resource msm_iommu_jpegd_resources[] = {
{
@@ -226,6 +229,27 @@
},
};
+static struct resource msm_iommu_gfx3d1_resources[] = {
+ {
+ .start = 0x07D00000,
+ .end = 0x07D00000 + SZ_1M - 1,
+ .name = "physbase",
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "nonsecure_irq",
+ .start = SMMU_GFX3D1_CB_SC_NON_SECURE_IRQ,
+ .end = SMMU_GFX3D1_CB_SC_NON_SECURE_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .name = "secure_irq",
+ .start = SMMU_GFX3D1_CB_SC_SECURE_IRQ,
+ .end = SMMU_GFX3D1_CB_SC_SECURE_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
static struct resource msm_iommu_gfx2d0_resources[] = {
{
.start = 0x07D00000,
@@ -268,6 +292,27 @@
},
};
+static struct resource msm_iommu_vcap_resources[] = {
+ {
+ .start = 0x07200000,
+ .end = 0x07200000 + SZ_1M - 1,
+ .name = "physbase",
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "nonsecure_irq",
+ .start = SMMU_VCAP_CB_SC_NON_SECURE_IRQ,
+ .end = SMMU_VCAP_CB_SC_NON_SECURE_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .name = "secure_irq",
+ .start = SMMU_VCAP_CB_SC_SECURE_IRQ,
+ .end = SMMU_VCAP_CB_SC_SECURE_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
static struct platform_device msm_root_iommu_dev = {
.name = "msm_iommu",
.id = -1,
@@ -323,6 +368,11 @@
.ncb = 3,
};
+static struct msm_iommu_dev gfx3d1_iommu = {
+ .name = "gfx3d1",
+ .ncb = 3,
+};
+
static struct msm_iommu_dev gfx2d0_iommu = {
.name = "gfx2d0",
.ncb = 2,
@@ -333,6 +383,11 @@
.ncb = 2,
};
+static struct msm_iommu_dev vcap_iommu = {
+ .name = "vcap",
+ .ncb = 2,
+};
+
static struct platform_device msm_device_iommu_jpegd = {
.name = "msm_iommu",
.id = 0,
@@ -433,6 +488,16 @@
.resource = msm_iommu_gfx3d_resources,
};
+static struct platform_device msm_device_iommu_gfx3d1 = {
+ .name = "msm_iommu",
+ .id = 10,
+ .dev = {
+ .parent = &msm_root_iommu_dev.dev,
+ },
+ .num_resources = ARRAY_SIZE(msm_iommu_gfx3d1_resources),
+ .resource = msm_iommu_gfx3d1_resources,
+};
+
static struct platform_device msm_device_iommu_gfx2d0 = {
.name = "msm_iommu",
.id = 10,
@@ -443,7 +508,7 @@
.resource = msm_iommu_gfx2d0_resources,
};
-struct platform_device msm_device_iommu_gfx2d1 = {
+static struct platform_device msm_device_iommu_gfx2d1 = {
.name = "msm_iommu",
.id = 11,
.dev = {
@@ -453,6 +518,16 @@
.resource = msm_iommu_gfx2d1_resources,
};
+static struct platform_device msm_device_iommu_vcap = {
+ .name = "msm_iommu",
+ .id = 11,
+ .dev = {
+ .parent = &msm_root_iommu_dev.dev,
+ },
+ .num_resources = ARRAY_SIZE(msm_iommu_vcap_resources),
+ .resource = msm_iommu_vcap_resources,
+};
+
static struct msm_iommu_ctx_dev jpegd_src_ctx = {
.name = "jpegd_src",
.num = 0,
@@ -568,6 +643,19 @@
31, -1}
};
+static struct msm_iommu_ctx_dev gfx3d1_user_ctx = {
+ .name = "gfx3d1_user",
+ .num = 0,
+ .mids = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
+};
+
+static struct msm_iommu_ctx_dev gfx3d1_priv_ctx = {
+ .name = "gfx3d1_priv",
+ .num = 1,
+ .mids = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30,
+ 31, -1}
+};
+
static struct msm_iommu_ctx_dev gfx2d0_2d0_ctx = {
.name = "gfx2d0_2d0",
.num = 0,
@@ -580,6 +668,18 @@
.mids = {0, 1, 2, 3, 4, 5, 6, 7, -1}
};
+static struct msm_iommu_ctx_dev vcap_vc_ctx = {
+ .name = "vcap_vc",
+ .num = 0,
+ .mids = {0, -1}
+};
+
+static struct msm_iommu_ctx_dev vcap_vp_ctx = {
+ .name = "vcap_vp",
+ .num = 1,
+ .mids = {1, -1}
+};
+
static struct platform_device msm_device_jpegd_src_ctx = {
.name = "msm_iommu_ctx",
.id = 0,
@@ -732,6 +832,22 @@
},
};
+static struct platform_device msm_device_gfx3d1_user_ctx = {
+ .name = "msm_iommu_ctx",
+ .id = 19,
+ .dev = {
+ .parent = &msm_device_iommu_gfx3d1.dev,
+ },
+};
+
+static struct platform_device msm_device_gfx3d1_priv_ctx = {
+ .name = "msm_iommu_ctx",
+ .id = 20,
+ .dev = {
+ .parent = &msm_device_iommu_gfx3d1.dev,
+ },
+};
+
static struct platform_device msm_device_gfx2d0_2d0_ctx = {
.name = "msm_iommu_ctx",
.id = 19,
@@ -748,7 +864,23 @@
},
};
-static struct platform_device *msm_iommu_devs[] = {
+static struct platform_device msm_device_vcap_vc_ctx = {
+ .name = "msm_iommu_ctx",
+ .id = 21,
+ .dev = {
+ .parent = &msm_device_iommu_vcap.dev,
+ },
+};
+
+static struct platform_device msm_device_vcap_vp_ctx = {
+ .name = "msm_iommu_ctx",
+ .id = 22,
+ .dev = {
+ .parent = &msm_device_iommu_vcap.dev,
+ },
+};
+
+static struct platform_device *msm_iommu_common_devs[] = {
&msm_device_iommu_jpegd,
&msm_device_iommu_vpe,
&msm_device_iommu_mdp0,
@@ -759,11 +891,19 @@
&msm_device_iommu_vcodec_a,
&msm_device_iommu_vcodec_b,
&msm_device_iommu_gfx3d,
+};
+
+static struct platform_device *msm_iommu_gfx2d_devs[] = {
&msm_device_iommu_gfx2d0,
&msm_device_iommu_gfx2d1,
};
-static struct msm_iommu_dev *msm_iommu_data[] = {
+static struct platform_device *msm_iommu_8064_devs[] = {
+ &msm_device_iommu_gfx3d1,
+ &msm_device_iommu_vcap,
+};
+
+static struct msm_iommu_dev *msm_iommu_common_data[] = {
&jpegd_iommu,
&vpe_iommu,
&mdp0_iommu,
@@ -774,11 +914,19 @@
&vcodec_a_iommu,
&vcodec_b_iommu,
&gfx3d_iommu,
+};
+
+static struct msm_iommu_dev *msm_iommu_gfx2d_data[] = {
&gfx2d0_iommu,
&gfx2d1_iommu,
};
-static struct platform_device *msm_iommu_ctx_devs[] = {
+static struct msm_iommu_dev *msm_iommu_8064_data[] = {
+ &gfx3d1_iommu,
+ &vcap_iommu,
+};
+
+static struct platform_device *msm_iommu_common_ctx_devs[] = {
&msm_device_jpegd_src_ctx,
&msm_device_jpegd_dst_ctx,
&msm_device_vpe_src_ctx,
@@ -798,11 +946,21 @@
&msm_device_vcodec_b_mm2_ctx,
&msm_device_gfx3d_user_ctx,
&msm_device_gfx3d_priv_ctx,
+};
+
+static struct platform_device *msm_iommu_gfx2d_ctx_devs[] = {
&msm_device_gfx2d0_2d0_ctx,
&msm_device_gfx2d1_2d1_ctx,
};
-static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = {
+static struct platform_device *msm_iommu_8064_ctx_devs[] = {
+ &msm_device_gfx3d1_user_ctx,
+ &msm_device_gfx3d1_priv_ctx,
+ &msm_device_vcap_vc_ctx,
+ &msm_device_vcap_vp_ctx,
+};
+
+static struct msm_iommu_ctx_dev *msm_iommu_common_ctx_data[] = {
&jpegd_src_ctx,
&jpegd_dst_ctx,
&vpe_src_ctx,
@@ -822,31 +980,35 @@
&vcodec_b_mm2_ctx,
&gfx3d_user_ctx,
&gfx3d_priv_ctx,
+};
+
+static struct msm_iommu_ctx_dev *msm_iommu_gfx2d_ctx_data[] = {
&gfx2d0_2d0_ctx,
&gfx2d1_2d1_ctx,
};
-static int __init msm8x60_iommu_init(void)
+static struct msm_iommu_ctx_dev *msm_iommu_8064_ctx_data[] = {
+ &gfx3d1_user_ctx,
+ &gfx3d1_priv_ctx,
+ &vcap_vc_ctx,
+ &vcap_vp_ctx,
+};
+
+static int iommu_init_devs(struct platform_device *devs[],
+ struct msm_iommu_dev *data[], int size)
{
int ret, i;
- ret = platform_device_register(&msm_root_iommu_dev);
- if (ret != 0) {
- pr_err("Failed to register root IOMMU device!\n");
- goto failure;
- }
-
- for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); i++) {
- ret = platform_device_add_data(msm_iommu_devs[i],
- msm_iommu_data[i],
- sizeof(struct msm_iommu_dev));
+ for (i = 0; i < size; i++) {
+ ret = platform_device_add_data(devs[i],
+ data[i], sizeof(struct msm_iommu_dev));
if (ret != 0) {
pr_err("platform_device_add_data failed, "
"i = %d\n", i);
goto failure_unwind;
}
- ret = platform_device_register(msm_iommu_devs[i]);
+ ret = platform_device_register(devs[i]);
if (ret != 0) {
pr_err("platform_device_register iommu failed, "
@@ -854,53 +1016,139 @@
goto failure_unwind;
}
}
+ return 0;
- for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++) {
- ret = platform_device_add_data(msm_iommu_ctx_devs[i],
- msm_iommu_ctx_data[i],
- sizeof(*msm_iommu_ctx_devs[i]));
+failure_unwind:
+ while (--i >= 0)
+ platform_device_unregister(devs[i]);
+
+ return ret;
+}
+
+
+static int iommu_init_ctx_devs(struct platform_device *ctx_devs[],
+ struct msm_iommu_ctx_dev *ctx_data[], int size)
+{
+ int ret, i;
+
+ for (i = 0; i < size; i++) {
+ ret = platform_device_add_data(ctx_devs[i],
+ ctx_data[i], sizeof(struct msm_iommu_ctx_dev));
if (ret != 0) {
pr_err("platform_device_add_data iommu failed, "
"i = %d\n", i);
- goto failure_unwind2;
+ goto failure_unwind;
}
- ret = platform_device_register(msm_iommu_ctx_devs[i]);
+ ret = platform_device_register(ctx_devs[i]);
if (ret != 0) {
pr_err("platform_device_register ctx failed, "
"i = %d\n", i);
- goto failure_unwind2;
+ goto failure_unwind;
}
}
return 0;
-failure_unwind2:
- while (--i >= 0)
- platform_device_unregister(msm_iommu_ctx_devs[i]);
failure_unwind:
while (--i >= 0)
- platform_device_unregister(msm_iommu_devs[i]);
+ platform_device_unregister(ctx_devs[i]);
+ return ret;
+}
+
+static int __init iommu_init(void)
+{
+ int ret;
+
+ ret = platform_device_register(&msm_root_iommu_dev);
+ if (ret != 0) {
+ pr_err("Failed to register root IOMMU device!\n");
+ goto failure;
+ }
+
+ /* Initialize common devs */
+ ret = iommu_init_devs(msm_iommu_common_devs,
+ msm_iommu_common_data,
+ ARRAY_SIZE(msm_iommu_common_devs));
+ if (ret != 0)
+ goto failure2;
+
+ /* Initialize soc-specific devs */
+ if (cpu_is_apq8064()) {
+ ret = iommu_init_devs(msm_iommu_8064_devs,
+ msm_iommu_8064_data,
+ ARRAY_SIZE(msm_iommu_8064_devs));
+ } else {
+ ret = iommu_init_devs(msm_iommu_gfx2d_devs,
+ msm_iommu_gfx2d_data,
+ ARRAY_SIZE(msm_iommu_gfx2d_devs));
+ }
+ if (ret != 0)
+ goto failure2;
+
+ /* Initialize common ctx_devs */
+ ret = iommu_init_ctx_devs(msm_iommu_common_ctx_devs,
+ msm_iommu_common_ctx_data,
+ ARRAY_SIZE(msm_iommu_common_ctx_devs));
+ if (ret != 0)
+ goto failure2;
+
+ /* Initialize soc-specific ctx_devs */
+ if (cpu_is_apq8064()) {
+ ret = iommu_init_ctx_devs(msm_iommu_8064_ctx_devs,
+ msm_iommu_8064_ctx_data,
+ ARRAY_SIZE(msm_iommu_8064_ctx_devs));
+ } else {
+ ret = iommu_init_ctx_devs(msm_iommu_gfx2d_ctx_devs,
+ msm_iommu_gfx2d_ctx_data,
+ ARRAY_SIZE(msm_iommu_gfx2d_ctx_devs));
+ }
+ if (ret != 0)
+ goto failure2;
+
+ return 0;
+
+failure2:
platform_device_unregister(&msm_root_iommu_dev);
failure:
return ret;
}
-static void __exit msm8x60_iommu_exit(void)
+static void __exit iommu_exit(void)
{
int i;
- for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++)
- platform_device_unregister(msm_iommu_ctx_devs[i]);
+ /* Common ctx_devs */
+ for (i = 0; i < ARRAY_SIZE(msm_iommu_common_ctx_devs); i++)
+ platform_device_unregister(msm_iommu_common_ctx_devs[i]);
- for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); ++i)
- platform_device_unregister(msm_iommu_devs[i]);
+ /* soc-specific ctx_devs. */
+ if (cpu_is_apq8064()) {
+ for (i = 0; i < ARRAY_SIZE(msm_iommu_8064_ctx_devs); i++)
+ platform_device_unregister(msm_iommu_8064_ctx_devs[i]);
+ } else {
+ for (i = 0; i < ARRAY_SIZE(msm_iommu_gfx2d_ctx_devs); i++)
+ platform_device_unregister(msm_iommu_gfx2d_ctx_devs[i]);
+ }
+
+ /* Common devs. */
+ for (i = 0; i < ARRAY_SIZE(msm_iommu_common_devs); ++i)
+ platform_device_unregister(msm_iommu_common_devs[i]);
+
+ /* soc-specific devs. */
+ if (cpu_is_apq8064()) {
+ for (i = 0; i < ARRAY_SIZE(msm_iommu_8064_devs); i++)
+ platform_device_unregister(msm_iommu_8064_devs[i]);
+ } else {
+ for (i = 0; i < ARRAY_SIZE(msm_iommu_gfx2d_devs); i++)
+ platform_device_unregister(msm_iommu_gfx2d_devs[i]);
+ }
platform_device_unregister(&msm_root_iommu_dev);
}
-subsys_initcall(msm8x60_iommu_init);
-module_exit(msm8x60_iommu_exit);
+subsys_initcall(iommu_init);
+module_exit(iommu_exit);
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Stepan Moskovchenko <stepanm@codeaurora.org>");
diff --git a/arch/arm/mach-msm/devices-msm7x01a.c b/arch/arm/mach-msm/devices-msm7x01a.c
index 9ed6fd1..1b9eb86 100644
--- a/arch/arm/mach-msm/devices-msm7x01a.c
+++ b/arch/arm/mach-msm/devices-msm7x01a.c
@@ -384,12 +384,21 @@
.id = -1,
};
-struct resource msm_dmov_resource[] = {
+static struct resource msm_dmov_resource[] = {
{
.start = INT_ADM_AARM,
- .end = (resource_size_t)MSM_DMOV_BASE,
.flags = IORESOURCE_IRQ,
},
+ {
+ .start = 0xA9700000,
+ .end = 0xA9700000 + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct msm_dmov_pdata msm_dmov_pdata = {
+ .sd = 3,
+ .sd_size = 0x400,
};
struct platform_device msm_device_dmov = {
@@ -397,6 +406,9 @@
.id = -1,
.resource = msm_dmov_resource,
.num_resources = ARRAY_SIZE(msm_dmov_resource),
+ .dev = {
+ .platform_data = &msm_dmov_pdata,
+ },
};
#define MSM_SDC1_BASE 0xA0400000
diff --git a/arch/arm/mach-msm/devices-msm7x25.c b/arch/arm/mach-msm/devices-msm7x25.c
index ca3caa2..c166c8d 100644
--- a/arch/arm/mach-msm/devices-msm7x25.c
+++ b/arch/arm/mach-msm/devices-msm7x25.c
@@ -407,12 +407,21 @@
.id = -1,
};
-struct resource msm_dmov_resource[] = {
+static struct resource msm_dmov_resource[] = {
{
.start = INT_ADM_AARM,
- .end = (resource_size_t)MSM_DMOV_BASE,
.flags = IORESOURCE_IRQ,
},
+ {
+ .start = 0xA9700000,
+ .end = 0xA9700000 + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct msm_dmov_pdata msm_dmov_pdata = {
+ .sd = 3,
+ .sd_size = 0x400,
};
struct platform_device msm_device_dmov = {
@@ -420,6 +429,9 @@
.id = -1,
.resource = msm_dmov_resource,
.num_resources = ARRAY_SIZE(msm_dmov_resource),
+ .dev = {
+ .platform_data = &msm_dmov_pdata,
+ },
};
#define MSM_SDC1_BASE 0xA0400000
diff --git a/arch/arm/mach-msm/devices-msm7x27.c b/arch/arm/mach-msm/devices-msm7x27.c
index 3772884..1bb9a21 100644
--- a/arch/arm/mach-msm/devices-msm7x27.c
+++ b/arch/arm/mach-msm/devices-msm7x27.c
@@ -372,12 +372,21 @@
.id = -1,
};
-struct resource msm_dmov_resource[] = {
+static struct resource msm_dmov_resource[] = {
{
.start = INT_ADM_AARM,
- .end = (resource_size_t)MSM_DMOV_BASE,
.flags = IORESOURCE_IRQ,
},
+ {
+ .start = 0xA9700000,
+ .end = 0xA9700000 + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct msm_dmov_pdata msm_dmov_pdata = {
+ .sd = 3,
+ .sd_size = 0x400,
};
struct platform_device msm_device_dmov = {
@@ -385,6 +394,9 @@
.id = -1,
.resource = msm_dmov_resource,
.num_resources = ARRAY_SIZE(msm_dmov_resource),
+ .dev = {
+ .platform_data = &msm_dmov_pdata,
+ },
};
#define MSM_SDC1_BASE 0xA0400000
diff --git a/arch/arm/mach-msm/devices-msm7x27a.c b/arch/arm/mach-msm/devices-msm7x27a.c
index 488db75..7008bd5 100644
--- a/arch/arm/mach-msm/devices-msm7x27a.c
+++ b/arch/arm/mach-msm/devices-msm7x27a.c
@@ -188,17 +188,29 @@
static struct resource msm_dmov_resource[] = {
{
- .start = INT_ADM_AARM,
- .end = (resource_size_t)MSM_DMOV_BASE,
- .flags = IORESOURCE_IRQ,
+ .start = INT_ADM_AARM,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = 0xA9700000,
+ .end = 0xA9700000 + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
},
};
+static struct msm_dmov_pdata msm_dmov_pdata = {
+ .sd = 3,
+ .sd_size = 0x400,
+};
+
struct platform_device msm_device_dmov = {
- .name = "msm_dmov",
- .id = -1,
- .resource = msm_dmov_resource,
- .num_resources = ARRAY_SIZE(msm_dmov_resource),
+ .name = "msm_dmov",
+ .id = -1,
+ .resource = msm_dmov_resource,
+ .num_resources = ARRAY_SIZE(msm_dmov_resource),
+ .dev = {
+ .platform_data = &msm_dmov_pdata,
+ },
};
struct platform_device msm_device_smd = {
diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c
index d7832a3..d7fc93e 100644
--- a/arch/arm/mach-msm/devices-msm7x30.c
+++ b/arch/arm/mach-msm/devices-msm7x30.c
@@ -585,12 +585,21 @@
.id = -1,
};
-struct resource msm_dmov_resource[] = {
+static struct resource msm_dmov_resource[] = {
{
.start = INT_ADM_AARM,
- .end = (resource_size_t)MSM_DMOV_BASE,
.flags = IORESOURCE_IRQ,
},
+ {
+ .start = 0xAC400000,
+ .end = 0xAC400000 + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct msm_dmov_pdata msm_dmov_pdata = {
+ .sd = 2,
+ .sd_size = 0x400,
};
struct platform_device msm_device_dmov = {
@@ -598,6 +607,9 @@
.id = -1,
.resource = msm_dmov_resource,
.num_resources = ARRAY_SIZE(msm_dmov_resource),
+ .dev = {
+ .platform_data = &msm_dmov_pdata,
+ },
};
#define MSM_SDC1_BASE 0xA0400000
diff --git a/arch/arm/mach-msm/devices-msm8x60.c b/arch/arm/mach-msm/devices-msm8x60.c
index 2582024..9f3e03d 100644
--- a/arch/arm/mach-msm/devices-msm8x60.c
+++ b/arch/arm/mach-msm/devices-msm8x60.c
@@ -527,7 +527,7 @@
},
{
ARRAY_SIZE(grp3d_low_vectors),
- grp3d_init_vectors,
+ grp3d_low_vectors,
},
{
ARRAY_SIZE(grp3d_nominal_low_vectors),
@@ -1833,20 +1833,38 @@
.id = -1,
};
-struct resource msm_dmov_resource_adm0[] = {
+static struct resource msm_dmov_resource_adm0[] = {
{
.start = INT_ADM0_AARM,
- .end = (resource_size_t)MSM_DMOV_ADM0_BASE,
.flags = IORESOURCE_IRQ,
},
+ {
+ .start = 0x18320000,
+ .end = 0x18320000 + SZ_1M - 1,
+ .flags = IORESOURCE_MEM,
+ },
};
-struct resource msm_dmov_resource_adm1[] = {
+static struct resource msm_dmov_resource_adm1[] = {
{
.start = INT_ADM1_AARM,
- .end = (resource_size_t)MSM_DMOV_ADM1_BASE,
.flags = IORESOURCE_IRQ,
},
+ {
+ .start = 0x18420000,
+ .end = 0x18420000 + SZ_1M - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct msm_dmov_pdata msm_dmov_pdata_adm0 = {
+ .sd = 1,
+ .sd_size = 0x800,
+};
+
+static struct msm_dmov_pdata msm_dmov_pdata_adm1 = {
+ .sd = 1,
+ .sd_size = 0x800,
};
struct platform_device msm_device_dmov_adm0 = {
@@ -1854,6 +1872,9 @@
.id = 0,
.resource = msm_dmov_resource_adm0,
.num_resources = ARRAY_SIZE(msm_dmov_resource_adm0),
+ .dev = {
+ .platform_data = &msm_dmov_pdata_adm0,
+ },
};
struct platform_device msm_device_dmov_adm1 = {
@@ -1861,6 +1882,9 @@
.id = 1,
.resource = msm_dmov_resource_adm1,
.num_resources = ARRAY_SIZE(msm_dmov_resource_adm1),
+ .dev = {
+ .platform_data = &msm_dmov_pdata_adm1,
+ },
};
/* MSM Video core device */
diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c
index 5ae5b8b..2367719 100644
--- a/arch/arm/mach-msm/devices-qsd8x50.c
+++ b/arch/arm/mach-msm/devices-qsd8x50.c
@@ -438,12 +438,21 @@
.id = -1,
};
-struct resource msm_dmov_resource[] = {
+static struct resource msm_dmov_resource[] = {
{
.start = INT_ADM_AARM,
- .end = (resource_size_t)MSM_DMOV_BASE,
.flags = IORESOURCE_IRQ,
},
+ {
+ .start = 0xA9700000,
+ .end = 0xA9700000 + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct msm_dmov_pdata msm_dmov_pdata = {
+ .sd = 3,
+ .sd_size = 0x400,
};
struct platform_device msm_device_dmov = {
@@ -451,6 +460,9 @@
.id = -1,
.resource = msm_dmov_resource,
.num_resources = ARRAY_SIZE(msm_dmov_resource),
+ .dev = {
+ .platform_data = &msm_dmov_pdata,
+ },
};
#define MSM_SDC1_BASE 0xA0300000
diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h
index 4a82b33..1748838 100644
--- a/arch/arm/mach-msm/devices.h
+++ b/arch/arm/mach-msm/devices.h
@@ -187,9 +187,19 @@
struct platform_device *msm_add_gsbi9_uart(void);
extern struct platform_device msm_device_touchscreen;
-extern struct pil_device peripheral_dsps;
extern struct platform_device led_pdev;
extern struct platform_device ion_dev;
extern struct platform_device msm_rpm_device;
+extern struct platform_device msm_device_rng;
+
+#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
+ defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
+extern struct platform_device msm9615_qcrypto_device;
+#endif
+
+#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
+ defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
+extern struct platform_device msm9615_qcedev_device;
+#endif
#endif
diff --git a/arch/arm/mach-msm/dma.c b/arch/arm/mach-msm/dma.c
index ddf7732..ad1aecd 100644
--- a/arch/arm/mach-msm/dma.c
+++ b/arch/arm/mach-msm/dma.c
@@ -57,6 +57,8 @@
struct msm_dmov_crci_conf *crci_conf;
struct msm_dmov_chan_conf *chan_conf;
int channel_active;
+ int sd;
+ size_t sd_size;
struct list_head ready_commands[MSM_DMOV_CHANNEL_COUNT];
struct list_head active_commands[MSM_DMOV_CHANNEL_COUNT];
spinlock_t lock;
@@ -185,7 +187,8 @@
#endif
#define MSM_DMOV_ID_COUNT (MSM_DMOV_CHANNEL_COUNT * ARRAY_SIZE(dmov_conf))
-#define DMOV_REG(name, adm) ((name) + (dmov_conf[adm].base))
+#define DMOV_REG(name, adm) ((name) + (dmov_conf[adm].base) +\
+ (dmov_conf[adm].sd * dmov_conf[adm].sd_size))
#define DMOV_ID_TO_ADM(id) ((id) / MSM_DMOV_CHANNEL_COUNT)
#define DMOV_ID_TO_CHAN(id) ((id) % MSM_DMOV_CHANNEL_COUNT)
#define DMOV_CHAN_ADM_TO_ID(ch, adm) ((ch) + (adm) * MSM_DMOV_CHANNEL_COUNT)
@@ -620,33 +623,46 @@
int adm = (pdev->id >= 0) ? pdev->id : 0;
int i;
int ret;
- struct resource *res =
+ struct msm_dmov_pdata *pdata = pdev->dev.platform_data;
+ struct resource *irqres =
platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+ struct resource *mres =
+ platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (res) {
- dmov_conf[adm].irq = res->start;
- dmov_conf[adm].base = (void *)res->end;
+ if (pdata) {
+ dmov_conf[adm].sd = pdata->sd;
+ dmov_conf[adm].sd_size = pdata->sd_size;
}
- if (!dmov_conf[adm].base || !dmov_conf[adm].irq)
+ if (!dmov_conf[adm].sd_size)
return -ENXIO;
+ if (!irqres || !irqres->start)
+ return -ENXIO;
+ dmov_conf[adm].irq = irqres->start;
+
+ if (!mres || !mres->start)
+ return -ENXIO;
+ dmov_conf[adm].base = ioremap_nocache(mres->start, resource_size(mres));
+ if (!dmov_conf[adm].base)
+ return -ENOMEM;
+
ret = request_irq(dmov_conf[adm].irq, msm_datamover_irq_handler,
0, "msmdatamover", NULL);
if (ret) {
PRINT_ERROR("Requesting ADM%d irq %d failed\n", adm,
dmov_conf[adm].irq);
- return ret;
+ goto out_map;
}
disable_irq(dmov_conf[adm].irq);
ret = msm_dmov_init_clocks(pdev);
if (ret) {
PRINT_ERROR("Requesting ADM%d clocks failed\n", adm);
- return -ENOENT;
+ goto out_irq;
}
ret = msm_dmov_clk_toggle(adm, 1);
if (ret) {
PRINT_ERROR("Enabling ADM%d clocks failed\n", adm);
- return -ENOENT;
+ goto out_irq;
}
config_datamover(adm);
@@ -661,6 +677,11 @@
wmb();
msm_dmov_clk_toggle(adm, 0);
return ret;
+out_irq:
+ free_irq(dmov_conf[adm].irq, NULL);
+out_map:
+ iounmap(dmov_conf[adm].base);
+ return ret;
}
static struct platform_driver msm_dmov_driver = {
diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h
index df6a64c..bc41915 100644
--- a/arch/arm/mach-msm/include/mach/board.h
+++ b/arch/arm/mach-msm/include/mach/board.h
@@ -415,10 +415,12 @@
void __init msm_map_qsd8x50_io(void);
void __init msm_map_msm8x60_io(void);
void __init msm_map_msm8960_io(void);
+void __init msm_map_msm8930_io(void);
void __init msm_map_apq8064_io(void);
void __init msm_map_msm7x30_io(void);
void __init msm_map_fsm9xxx_io(void);
void __init msm_init_irq(void);
+void vic_handle_irq(struct pt_regs *regs);
struct mmc_platform_data;
int __init msm_add_sdcc(unsigned int controller,
diff --git a/arch/arm/mach-msm/include/mach/dma-fsm9xxx.h b/arch/arm/mach-msm/include/mach/dma-fsm9xxx.h
index 300ee87..e284267 100644
--- a/arch/arm/mach-msm/include/mach/dma-fsm9xxx.h
+++ b/arch/arm/mach-msm/include/mach/dma-fsm9xxx.h
@@ -13,12 +13,6 @@
#ifndef __ASM_ARCH_MSM_DMA_FSM9XXX_H
#define __ASM_ARCH_MSM_DMA_FSM9XXX_H
-#define DMOV_SD_SIZE 0x1400
-#define DMOV_SD_MASTER 0
-#define DMOV_SD_AARM 3
-#define DMOV_SD_MASTER_ADDR(off, ch) DMOV_ADDR(off, ch, DMOV_SD_MASTER)
-#define DMOV_SD_AARM_ADDR(off, ch) DMOV_ADDR(off, ch, DMOV_SD_AARM)
-
/* DMA channels allocated to Scorpion */
#define DMOV_GP_CHAN 4
#define DMOV_CE1_IN_CHAN 5
diff --git a/arch/arm/mach-msm/include/mach/dma.h b/arch/arm/mach-msm/include/mach/dma.h
index 9c331a4..1474fcb 100644
--- a/arch/arm/mach-msm/include/mach/dma.h
+++ b/arch/arm/mach-msm/include/mach/dma.h
@@ -38,6 +38,11 @@
void *user; /* Pointer for caller's reference */
};
+struct msm_dmov_pdata {
+ int sd;
+ size_t sd_size;
+};
+
void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd);
void msm_dmov_enqueue_cmd_ext(unsigned id, struct msm_dmov_cmd *cmd);
void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful);
@@ -46,64 +51,37 @@
#define DMOV_CRCIS_PER_CONF 10
-#define DMOV_ADDR(off, ch, sd) ((DMOV_SD_SIZE*(sd)) + (off) + ((ch) << 2))
-#define DMOV_SD0(off, ch) DMOV_ADDR(off, ch, 0)
-#define DMOV_SD1(off, ch) DMOV_ADDR(off, ch, 1)
-#define DMOV_SD2(off, ch) DMOV_ADDR(off, ch, 2)
-#define DMOV_SD3(off, ch) DMOV_ADDR(off, ch, 3)
+#define DMOV_ADDR(off, ch) ((off) + ((ch) << 2))
-#if defined(CONFIG_ARCH_MSM7X30)
-#define DMOV_SD_SIZE 0x400
-#define DMOV_SD_AARM 2
-#elif defined(CONFIG_ARCH_MSM8960) || defined(CONFIG_ARCH_MSM9615)
-#define DMOV_SD_SIZE 0x800
-#define DMOV_SD_AARM 1
-#elif defined(CONFIG_ARCH_APQ8064)
-#define DMOV_SD_SIZE 0x800
-#define DMOV_SD_AARM 0
-#elif defined(CONFIG_MSM_ADM3)
-#define DMOV_SD_SIZE 0x800
-#define DMOV_SD_MASTER 1
-#define DMOV_SD_AARM 1
-#define DMOV_SD_MASTER_ADDR(off, ch) DMOV_ADDR(off, ch, DMOV_SD_MASTER)
-#elif defined(CONFIG_ARCH_FSM9XXX)
-/* defined in dma-fsm9xxx.h */
-#else
-#define DMOV_SD_SIZE 0x400
-#define DMOV_SD_AARM 3
-#endif
-
-#define DMOV_SD_AARM_ADDR(off, ch) DMOV_ADDR(off, ch, DMOV_SD_AARM)
-
-#define DMOV_CMD_PTR(ch) DMOV_SD_AARM_ADDR(0x000, ch)
+#define DMOV_CMD_PTR(ch) DMOV_ADDR(0x000, ch)
#define DMOV_CMD_LIST (0 << 29) /* does not work */
#define DMOV_CMD_PTR_LIST (1 << 29) /* works */
#define DMOV_CMD_INPUT_CFG (2 << 29) /* untested */
#define DMOV_CMD_OUTPUT_CFG (3 << 29) /* untested */
#define DMOV_CMD_ADDR(addr) ((addr) >> 3)
-#define DMOV_RSLT(ch) DMOV_SD_AARM_ADDR(0x040, ch)
+#define DMOV_RSLT(ch) DMOV_ADDR(0x040, ch)
#define DMOV_RSLT_VALID (1 << 31) /* 0 == host has empties result fifo */
#define DMOV_RSLT_ERROR (1 << 3)
#define DMOV_RSLT_FLUSH (1 << 2)
#define DMOV_RSLT_DONE (1 << 1) /* top pointer done */
#define DMOV_RSLT_USER (1 << 0) /* command with FR force result */
-#define DMOV_FLUSH0(ch) DMOV_SD_AARM_ADDR(0x080, ch)
-#define DMOV_FLUSH1(ch) DMOV_SD_AARM_ADDR(0x0C0, ch)
-#define DMOV_FLUSH2(ch) DMOV_SD_AARM_ADDR(0x100, ch)
-#define DMOV_FLUSH3(ch) DMOV_SD_AARM_ADDR(0x140, ch)
-#define DMOV_FLUSH4(ch) DMOV_SD_AARM_ADDR(0x180, ch)
-#define DMOV_FLUSH5(ch) DMOV_SD_AARM_ADDR(0x1C0, ch)
+#define DMOV_FLUSH0(ch) DMOV_ADDR(0x080, ch)
+#define DMOV_FLUSH1(ch) DMOV_ADDR(0x0C0, ch)
+#define DMOV_FLUSH2(ch) DMOV_ADDR(0x100, ch)
+#define DMOV_FLUSH3(ch) DMOV_ADDR(0x140, ch)
+#define DMOV_FLUSH4(ch) DMOV_ADDR(0x180, ch)
+#define DMOV_FLUSH5(ch) DMOV_ADDR(0x1C0, ch)
#define DMOV_FLUSH_TYPE (1 << 31)
-#define DMOV_STATUS(ch) DMOV_SD_AARM_ADDR(0x200, ch)
+#define DMOV_STATUS(ch) DMOV_ADDR(0x200, ch)
#define DMOV_STATUS_RSLT_COUNT(n) (((n) >> 29))
#define DMOV_STATUS_CMD_COUNT(n) (((n) >> 27) & 3)
#define DMOV_STATUS_RSLT_VALID (1 << 1)
#define DMOV_STATUS_CMD_PTR_RDY (1 << 0)
-#define DMOV_CONF(ch) DMOV_SD_MASTER_ADDR(0x240, ch)
+#define DMOV_CONF(ch) DMOV_ADDR(0x240, ch)
#define DMOV_CONF_SD(sd) (((sd & 4) << 11) | ((sd & 3) << 4))
#define DMOV_CONF_IRQ_EN (1 << 6)
#define DMOV_CONF_FORCE_RSLT_EN (1 << 7)
@@ -111,28 +89,28 @@
#define DMOV_CONF_MPU_DISABLE (1 << 11)
#define DMOV_CONF_PRIORITY(n) (n << 0)
-#define DMOV_DBG_ERR(ci) DMOV_SD_MASTER_ADDR(0x280, ci)
+#define DMOV_DBG_ERR(ci) DMOV_ADDR(0x280, ci)
-#define DMOV_RSLT_CONF(ch) DMOV_SD_AARM_ADDR(0x300, ch)
+#define DMOV_RSLT_CONF(ch) DMOV_ADDR(0x300, ch)
#define DMOV_RSLT_CONF_FORCE_TOP_PTR_RSLT (1 << 2)
#define DMOV_RSLT_CONF_FORCE_FLUSH_RSLT (1 << 1)
#define DMOV_RSLT_CONF_IRQ_EN (1 << 0)
-#define DMOV_ISR DMOV_SD_AARM_ADDR(0x380, 0)
+#define DMOV_ISR DMOV_ADDR(0x380, 0)
-#define DMOV_CI_CONF(ci) DMOV_SD_MASTER_ADDR(0x390, ci)
+#define DMOV_CI_CONF(ci) DMOV_ADDR(0x390, ci)
#define DMOV_CI_CONF_RANGE_END(n) ((n) << 24)
#define DMOV_CI_CONF_RANGE_START(n) ((n) << 16)
#define DMOV_CI_CONF_MAX_BURST(n) ((n) << 0)
-#define DMOV_CI_DBG_ERR(ci) DMOV_SD_MASTER_ADDR(0x3B0, ci)
+#define DMOV_CI_DBG_ERR(ci) DMOV_ADDR(0x3B0, ci)
-#define DMOV_CRCI_CONF0 DMOV_SD_MASTER_ADDR(0x3D0, 0)
-#define DMOV_CRCI_CONF1 DMOV_SD_MASTER_ADDR(0x3D4, 0)
+#define DMOV_CRCI_CONF0 DMOV_ADDR(0x3D0, 0)
+#define DMOV_CRCI_CONF1 DMOV_ADDR(0x3D4, 0)
#define DMOV_CRCI_CONF0_SD(crci, sd) (sd << (crci*3))
#define DMOV_CRCI_CONF1_SD(crci, sd) (sd << ((crci-DMOV_CRCIS_PER_CONF)*3))
-#define DMOV_CRCI_CTL(crci) DMOV_SD_AARM_ADDR(0x400, crci)
+#define DMOV_CRCI_CTL(crci) DMOV_ADDR(0x400, crci)
#define DMOV_CRCI_CTL_BLK_SZ(n) ((n) << 0)
#define DMOV_CRCI_CTL_RST (1 << 17)
#define DMOV_CRCI_MUX (1 << 18)
diff --git a/arch/arm/mach-msm/include/mach/entry-macro.S b/arch/arm/mach-msm/include/mach/entry-macro.S
index eb5921f..d384366 100644
--- a/arch/arm/mach-msm/include/mach/entry-macro.S
+++ b/arch/arm/mach-msm/include/mach/entry-macro.S
@@ -10,11 +10,15 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
-
-#if defined(CONFIG_MSM_VIC)
+#if defined(CONFIG_MSM_VIC) && !defined(CONFIG_MULTI_IRQ_HANDLER)
#include <mach/entry-macro-vic.S>
#elif defined(CONFIG_ARM_GIC)
#include <mach/entry-macro-qgic.S>
#else
-#error "No interrupt controller selected!"
+ .macro disable_fiq
+ .endm
+
+ .macro arch_ret_to_user, tmp1, tmp2
+ .endm
+
#endif
diff --git a/arch/arm/mach-msm/include/mach/irqs-8064.h b/arch/arm/mach-msm/include/mach/irqs-8064.h
index 25dcd3f..8597111 100644
--- a/arch/arm/mach-msm/include/mach/irqs-8064.h
+++ b/arch/arm/mach-msm/include/mach/irqs-8064.h
@@ -280,7 +280,7 @@
#define CS3_BAM_XPU_IRQ (GIC_SPI_START + 234)
#define CE3_IRQ (GIC_SPI_START + 235)
#define SMMU_VCAP_CB_SC_SECURE_IRQ (GIC_SPI_START + 236)
-#define SMMU_VCAM_CP_SC_NON_SECURE_IRQ (GIC_SPI_START + 237)
+#define SMMU_VCAP_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 237)
#define PCIE20_INT_MSI (GIC_SPI_START + 238)
#define PCIE20_INTA (GIC_SPI_START + 239)
#define PCIE20_INTB (GIC_SPI_START + 240)
diff --git a/arch/arm/mach-msm/include/mach/irqs-8930.h b/arch/arm/mach-msm/include/mach/irqs-8930.h
new file mode 100644
index 0000000..ed927bd
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/irqs-8930.h
@@ -0,0 +1,292 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_MSM_IRQS_8930_H
+#define __ASM_ARCH_MSM_IRQS_8930_H
+
+/* MSM ACPU Interrupt Numbers */
+
+/* 0-15: STI/SGI (software triggered/generated interrupts)
+ 16-31: PPI (private peripheral interrupts)
+ 32+: SPI (shared peripheral interrupts) */
+
+#define GIC_PPI_START 16
+#define GIC_SPI_START 32
+
+#define INT_VGIC (GIC_PPI_START + 0)
+#define INT_DEBUG_TIMER_EXP (GIC_PPI_START + 1)
+#define INT_GP_TIMER_EXP (GIC_PPI_START + 2)
+#define INT_GP_TIMER2_EXP (GIC_PPI_START + 3)
+#define WDT0_ACCSCSSNBARK_INT (GIC_PPI_START + 4)
+#define WDT1_ACCSCSSNBARK_INT (GIC_PPI_START + 5)
+#define AVS_SVICINT (GIC_PPI_START + 6)
+#define AVS_SVICINTSWDONE (GIC_PPI_START + 7)
+#define CPU_DBGCPUXCOMMRXFULL (GIC_PPI_START + 8)
+#define CPU_DBGCPUXCOMMTXEMPTY (GIC_PPI_START + 9)
+#define INT_ARMQC_PERFMON (GIC_PPI_START + 10)
+#define SC_AVSCPUXDOWN (GIC_PPI_START + 11)
+#define SC_AVSCPUXUP (GIC_PPI_START + 12)
+#define SC_SICCPUXACGIRPTREQ (GIC_PPI_START + 13)
+#define SC_SICCPUXEXTFAULTIRPTREQ (GIC_PPI_START + 14)
+/* PPI 15 is unused */
+
+#define APCC_QGICACGIRPTREQ (GIC_SPI_START + 0)
+#define APCC_QGICL2PERFMONIRPTREQ (GIC_SPI_START + 1)
+#define SC_SICL2PERFMONIRPTREQ APCC_QGICL2PERFMONIRPTREQ
+#define APCC_QGICL2IRPTREQ (GIC_SPI_START + 2)
+#define APCC_QGICMPUIRPTREQ (GIC_SPI_START + 3)
+#define TLMM_MSM_DIR_CONN_IRQ_0 (GIC_SPI_START + 4)
+#define TLMM_MSM_DIR_CONN_IRQ_1 (GIC_SPI_START + 5)
+#define TLMM_MSM_DIR_CONN_IRQ_2 (GIC_SPI_START + 6)
+#define TLMM_MSM_DIR_CONN_IRQ_3 (GIC_SPI_START + 7)
+#define TLMM_MSM_DIR_CONN_IRQ_4 (GIC_SPI_START + 8)
+#define TLMM_MSM_DIR_CONN_IRQ_5 (GIC_SPI_START + 9)
+#define TLMM_MSM_DIR_CONN_IRQ_6 (GIC_SPI_START + 10)
+#define TLMM_MSM_DIR_CONN_IRQ_7 (GIC_SPI_START + 11)
+#define TLMM_MSM_DIR_CONN_IRQ_8 (GIC_SPI_START + 12)
+#define TLMM_MSM_DIR_CONN_IRQ_9 (GIC_SPI_START + 13)
+#define PM8921_SEC_IRQ_103 (GIC_SPI_START + 14)
+#define PM8018_SEC_IRQ_106 (GIC_SPI_START + 15)
+#define TLMM_MSM_SUMMARY_IRQ (GIC_SPI_START + 16)
+#define SPDM_RT_1_IRQ (GIC_SPI_START + 17)
+#define SPDM_DIAG_IRQ (GIC_SPI_START + 18)
+#define RPM_APCC_CPU0_GP_HIGH_IRQ (GIC_SPI_START + 19)
+#define RPM_APCC_CPU0_GP_MEDIUM_IRQ (GIC_SPI_START + 20)
+#define RPM_APCC_CPU0_GP_LOW_IRQ (GIC_SPI_START + 21)
+#define RPM_APCC_CPU0_WAKE_UP_IRQ (GIC_SPI_START + 22)
+#define RPM_APCC_CPU1_GP_HIGH_IRQ (GIC_SPI_START + 23)
+#define RPM_APCC_CPU1_GP_MEDIUM_IRQ (GIC_SPI_START + 24)
+#define RPM_APCC_CPU1_GP_LOW_IRQ (GIC_SPI_START + 25)
+#define RPM_APCC_CPU1_WAKE_UP_IRQ (GIC_SPI_START + 26)
+#define SSBI2_2_SC_CPU0_SECURE_IRQ (GIC_SPI_START + 27)
+#define SSBI2_2_SC_CPU0_NON_SECURE_IRQ (GIC_SPI_START + 28)
+#define SSBI2_1_SC_CPU0_SECURE_IRQ (GIC_SPI_START + 29)
+#define SSBI2_1_SC_CPU0_NON_SECURE_IRQ (GIC_SPI_START + 30)
+#define MSMC_SC_SEC_CE_IRQ (GIC_SPI_START + 31)
+#define MSMC_SC_PRI_CE_IRQ (GIC_SPI_START + 32)
+#define SLIMBUS0_CORE_EE1_IRQ (GIC_SPI_START + 33)
+#define SLIMBUS0_BAM_EE1_IRQ (GIC_SPI_START + 34)
+#define Q6FW_WDOG_EXPIRED_IRQ (GIC_SPI_START + 35)
+#define Q6SW_WDOG_EXPIRED_IRQ (GIC_SPI_START + 36)
+#define MSS_TO_APPS_IRQ_0 (GIC_SPI_START + 37)
+#define MSS_TO_APPS_IRQ_1 (GIC_SPI_START + 38)
+#define MSS_TO_APPS_IRQ_2 (GIC_SPI_START + 39)
+#define MSS_TO_APPS_IRQ_3 (GIC_SPI_START + 40)
+#define MSS_TO_APPS_IRQ_4 (GIC_SPI_START + 41)
+#define MSS_TO_APPS_IRQ_5 (GIC_SPI_START + 42)
+#define MSS_TO_APPS_IRQ_6 (GIC_SPI_START + 43)
+#define MSS_TO_APPS_IRQ_7 (GIC_SPI_START + 44)
+#define MSS_TO_APPS_IRQ_8 (GIC_SPI_START + 45)
+#define MSS_TO_APPS_IRQ_9 (GIC_SPI_START + 46)
+#define VPE_IRQ (GIC_SPI_START + 47)
+#define VFE_IRQ (GIC_SPI_START + 48)
+#define VCODEC_IRQ (GIC_SPI_START + 49)
+/* SPI IRQ 50 is unused */
+#define SMMU_VPE_CB_SC_SECURE_IRQ (GIC_SPI_START + 51)
+#define SMMU_VPE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 52)
+#define SMMU_VFE_CB_SC_SECURE_IRQ (GIC_SPI_START + 53)
+#define SMMU_VFE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 54)
+#define SMMU_VCODEC_B_CB_SC_SECURE_IRQ (GIC_SPI_START + 55)
+#define SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 56)
+#define SMMU_VCODEC_A_CB_SC_SECURE_IRQ (GIC_SPI_START + 57)
+#define SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 58)
+#define SMMU_ROT_CB_SC_SECURE_IRQ (GIC_SPI_START + 59)
+#define SMMU_ROT_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 60)
+#define SMMU_MDP1_CB_SC_SECURE_IRQ (GIC_SPI_START + 61)
+#define SMMU_MDP1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 62)
+#define SMMU_MDP0_CB_SC_SECURE_IRQ (GIC_SPI_START + 63)
+#define SMMU_MDP0_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 64)
+/* SPI IRQ 65 is unused */
+/* SPI IRQ 66 is unused */
+#define SMMU_IJPEG_CB_SC_SECURE_IRQ (GIC_SPI_START + 67)
+#define SMMU_IJPEG_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 68)
+#define SMMU_GFX3D_CB_SC_SECURE_IRQ (GIC_SPI_START + 69)
+#define SMMU_GFX3D_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 70)
+/* SPI IRQ 71 is unused */
+/* SPI IRQ 72 is unused */
+#define ROT_IRQ (GIC_SPI_START + 73)
+#define MMSS_FABRIC_IRQ (GIC_SPI_START + 74)
+#define MDP_IRQ (GIC_SPI_START + 75)
+/* SPI IRQ 76 is unused */
+#define JPEG_IRQ (GIC_SPI_START + 77)
+#define MMSS_IMEM_IRQ (GIC_SPI_START + 78)
+#define HDMI_IRQ (GIC_SPI_START + 79)
+#define GFX3D_IRQ (GIC_SPI_START + 80)
+/* SPI IRQ 81 is unused */
+#define DSI1_IRQ (GIC_SPI_START + 82)
+#define CSI_1_IRQ (GIC_SPI_START + 83)
+#define CSI_0_IRQ (GIC_SPI_START + 84)
+#define LPASS_SCSS_AUDIO_IF_OUT0_IRQ (GIC_SPI_START + 85)
+#define LPASS_SCSS_MIDI_IRQ (GIC_SPI_START + 86)
+#define LPASS_Q6SS_WDOG_EXPIRED (GIC_SPI_START + 87)
+#define LPASS_SCSS_GP_LOW_IRQ (GIC_SPI_START + 88)
+#define LPASS_SCSS_GP_MEDIUM_IRQ (GIC_SPI_START + 89)
+#define LPASS_SCSS_GP_HIGH_IRQ (GIC_SPI_START + 90)
+#define TOP_IMEM_IRQ (GIC_SPI_START + 91)
+#define FABRIC_SYS_IRQ (GIC_SPI_START + 92)
+#define FABRIC_APPS_IRQ (GIC_SPI_START + 93)
+#define USB1_HS_BAM_IRQ (GIC_SPI_START + 94)
+#define SDC4_BAM_IRQ (GIC_SPI_START + 95)
+#define SDC3_BAM_IRQ (GIC_SPI_START + 96)
+#define SDC2_BAM_IRQ (GIC_SPI_START + 97)
+#define SDC1_BAM_IRQ (GIC_SPI_START + 98)
+#define FABRIC_SPS_IRQ (GIC_SPI_START + 99)
+#define USB1_HS_IRQ (GIC_SPI_START + 100)
+#define SDC4_IRQ_0 (GIC_SPI_START + 101)
+#define SDC3_IRQ_0 (GIC_SPI_START + 102)
+#define SDC2_IRQ_0 (GIC_SPI_START + 103)
+#define SDC1_IRQ_0 (GIC_SPI_START + 104)
+#define SPS_BAM_DMA_IRQ (GIC_SPI_START + 105)
+#define SPS_SEC_VIOL_IRQ (GIC_SPI_START + 106)
+#define SPS_MTI_0 (GIC_SPI_START + 107)
+#define SPS_MTI_1 (GIC_SPI_START + 108)
+#define SPS_MTI_2 (GIC_SPI_START + 109)
+#define SPS_MTI_3 (GIC_SPI_START + 110)
+#define GPS_PPS_OUT (GIC_SPI_START + 111)
+#define SPS_MTI_5 (GIC_SPI_START + 112)
+#define SPS_MTI_6 (GIC_SPI_START + 113)
+#define SPS_MTI_7 (GIC_SPI_START + 114)
+#define SPS_MTI_8 (GIC_SPI_START + 115)
+#define TLMM_MSM_DIR_CONN_IRQ_11 (GIC_SPI_START + 116)
+#define TLMM_MSM_DIR_CONN_IRQ_10 (GIC_SPI_START + 117)
+#define BAM_DMA1 (GIC_SPI_START + 118)
+#define BAM_DMA2 (GIC_SPI_START + 119)
+#define SDC1_IRQ (GIC_SPI_START + 120)
+#define SDC2_IRQ (GIC_SPI_START + 121)
+#define SDC3_IRQ (GIC_SPI_START + 122)
+#define SPS_MTI_16 (GIC_SPI_START + 123)
+#define SPS_MTI_17 (GIC_SPI_START + 124)
+#define SPS_MTI_18 (GIC_SPI_START + 125)
+#define SPS_MTI_19 (GIC_SPI_START + 126)
+#define SPS_MTI_20 (GIC_SPI_START + 127)
+#define SPS_MTI_21 (GIC_SPI_START + 128)
+#define SPS_MTI_22 (GIC_SPI_START + 129)
+#define SPS_MTI_23 (GIC_SPI_START + 130)
+#define SPS_MTI_24 (GIC_SPI_START + 131)
+#define SPS_MTI_25 (GIC_SPI_START + 132)
+#define SPS_MTI_26 (GIC_SPI_START + 133)
+#define SPS_MTI_27 (GIC_SPI_START + 134)
+#define SPS_MTI_28 (GIC_SPI_START + 135)
+#define SPS_MTI_29 (GIC_SPI_START + 136)
+#define SPS_MTI_30 (GIC_SPI_START + 137)
+#define SPS_MTI_31 (GIC_SPI_START + 138)
+#define CSIPHY_4LN_IRQ (GIC_SPI_START + 139)
+#define MSM8930_CSIPHY_2LN_IRQ (GIC_SPI_START + 140)
+#define USB2_IRQ (GIC_SPI_START + 141)
+#define USB1_IRQ (GIC_SPI_START + 142)
+#define TSSC_SSBI_IRQ (GIC_SPI_START + 143)
+#define TSSC_SAMPLE_IRQ (GIC_SPI_START + 144)
+#define TSSC_PENUP_IRQ (GIC_SPI_START + 145)
+#define MSM8930_GSBI1_UARTDM_IRQ (GIC_SPI_START + 146)
+#define MSM8930_GSBI1_QUP_IRQ (GIC_SPI_START + 147)
+#define MSM8930_GSBI2_UARTDM_IRQ (GIC_SPI_START + 148)
+#define MSM8930_GSBI2_QUP_IRQ (GIC_SPI_START + 149)
+#define GSBI3_UARTDM_IRQ (GIC_SPI_START + 150)
+#define GSBI3_QUP_IRQ (GIC_SPI_START + 151)
+#define GSBI4_UARTDM_IRQ (GIC_SPI_START + 152)
+#define GSBI4_QUP_IRQ (GIC_SPI_START + 153)
+#define GSBI5_UARTDM_IRQ (GIC_SPI_START + 154)
+#define GSBI5_QUP_IRQ (GIC_SPI_START + 155)
+#define GSBI6_UARTDM_IRQ (GIC_SPI_START + 156)
+#define GSBI6_QUP_IRQ (GIC_SPI_START + 157)
+#define GSBI7_UARTDM_IRQ (GIC_SPI_START + 158)
+#define GSBI7_QUP_IRQ (GIC_SPI_START + 159)
+#define GSBI8_UARTDM_IRQ (GIC_SPI_START + 160)
+#define GSBI8_QUP_IRQ (GIC_SPI_START + 161)
+#define TSIF_TSPP_IRQ (GIC_SPI_START + 162)
+#define TSIF_BAM_IRQ (GIC_SPI_START + 163)
+#define TSIF2_IRQ (GIC_SPI_START + 164)
+#define TSIF1_IRQ (GIC_SPI_START + 165)
+/* SPI IRQ 166 is unused */
+#define ISPIF_IRQ (GIC_SPI_START + 167)
+#define MSMC_SC_SEC_TMR_IRQ (GIC_SPI_START + 168)
+#define MSMC_SC_SEC_WDOG_BARK_IRQ (GIC_SPI_START + 169)
+#define ADM_0_SCSS_0_IRQ (GIC_SPI_START + 170)
+#define ADM_0_SCSS_1_IRQ (GIC_SPI_START + 171)
+#define ADM_0_SCSS_2_IRQ (GIC_SPI_START + 172)
+#define ADM_0_SCSS_3_IRQ (GIC_SPI_START + 173)
+#define CC_SCSS_WDT1CPU1BITEEXPIRED (GIC_SPI_START + 174)
+#define CC_SCSS_WDT1CPU0BITEEXPIRED (GIC_SPI_START + 175)
+#define CC_SCSS_WDT0CPU1BITEEXPIRED (GIC_SPI_START + 176)
+#define CC_SCSS_WDT0CPU0BITEEXPIRED (GIC_SPI_START + 177)
+#define TSENS_UPPER_LOWER_INT (GIC_SPI_START + 178)
+#define SSBI2_2_SC_CPU1_SECURE_INT (GIC_SPI_START + 179)
+#define SSBI2_2_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 180)
+#define SSBI2_1_SC_CPU1_SECURE_INT (GIC_SPI_START + 181)
+#define SSBI2_1_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 182)
+#define XPU_SUMMARY_IRQ (GIC_SPI_START + 183)
+#define BUS_EXCEPTION_SUMMARY_IRQ (GIC_SPI_START + 184)
+#define HSDDRX_EBI1CH0_IRQ (GIC_SPI_START + 185)
+/* SPI IRQ 186 is unused */
+#define SDC5_BAM_IRQ (GIC_SPI_START + 187)
+#define SDC5_IRQ_0 (GIC_SPI_START + 188)
+#define GSBI9_UARTDM_IRQ (GIC_SPI_START + 189)
+#define GSBI9_QUP_IRQ (GIC_SPI_START + 190)
+#define GSBI10_UARTDM_IRQ (GIC_SPI_START + 191)
+#define GSBI10_QUP_IRQ (GIC_SPI_START + 192)
+#define GSBI11_UARTDM_IRQ (GIC_SPI_START + 193)
+#define GSBI11_QUP_IRQ (GIC_SPI_START + 194)
+#define GSBI12_UARTDM_IRQ (GIC_SPI_START + 195)
+#define GSBI12_QUP_IRQ (GIC_SPI_START + 196)
+#define RIVA_APSS_LTECOEX_IRQ (GIC_SPI_START + 197)
+#define RIVA_APSS_SPARE_IRQ (GIC_SPI_START + 198)
+#define RIVA_APSS_WDOG_BITE_RESET_RDY_IRQ (GIC_SPI_START + 199)
+#define RIVA_APSS_RESET_DONE_IRQ (GIC_SPI_START + 200)
+#define RIVA_APSS_ASIC_IRQ (GIC_SPI_START + 201)
+#define RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ (GIC_SPI_START + 202)
+#define RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ (GIC_SPI_START + 203)
+#define RIVA_APPS_WLAN_SMSM_IRQ (GIC_SPI_START + 204)
+#define RIVA_APPS_LOG_CTRL_IRQ (GIC_SPI_START + 205)
+#define RIVA_APPS_FM_CTRL_IRQ (GIC_SPI_START + 206)
+#define RIVA_APPS_HCI_IRQ (GIC_SPI_START + 207)
+#define RIVA_APPS_WLAN_CTRL_IRQ (GIC_SPI_START + 208)
+#define A2_BAM_IRQ (GIC_SPI_START + 209)
+/* SPI IRQ 210 is unused */
+/* SPI IRQ 211 is unused */
+/* SPI IRQ 212 is unused */
+#define PPSS_WDOG_TIMER_IRQ (GIC_SPI_START + 213)
+#define SPS_SLIMBUS_CORE_EE0_IRQ (GIC_SPI_START + 214)
+#define SPS_SLIMBUS_BAM_EE0_IRQ (GIC_SPI_START + 215)
+#define QDSS_ETB_IRQ (GIC_SPI_START + 216)
+#define QDSS_CTI2KPSS_CPU1_IRQ (GIC_SPI_START + 217)
+#define QDSS_CTI2KPSS_CPU0_IRQ (GIC_SPI_START + 218)
+#define TLMM_MSM_DIR_CONN_IRQ_16 (GIC_SPI_START + 219)
+#define TLMM_MSM_DIR_CONN_IRQ_17 (GIC_SPI_START + 220)
+#define TLMM_MSM_DIR_CONN_IRQ_18 (GIC_SPI_START + 221)
+#define TLMM_MSM_DIR_CONN_IRQ_19 (GIC_SPI_START + 222)
+#define TLMM_MSM_DIR_CONN_IRQ_20 (GIC_SPI_START + 223)
+#define TLMM_MSM_DIR_CONN_IRQ_21 (GIC_SPI_START + 224)
+#define PM8921_SEC_IRQ_104 (GIC_SPI_START + 225)
+#define PM8018_SEC_IRQ_107 (GIC_SPI_START + 226)
+#define USB_HSIC_IRQ (GIC_SPI_START + 229)
+#define CE2_BAM_XPU_IRQ (GIC_SPI_START + 230)
+#define CE1_BAM_XPU_IRQ (GIC_SPI_START + 231)
+#define GFX3D_VBIF_IRPT (GIC_SPI_START + 232)
+#define RBIF_IRQ_0 (GIC_SPI_START + 233)
+#define RBIF_IRQ_1 (GIC_SPI_START + 234)
+#define RBIF_IRQ_2 (GIC_SPI_START + 235)
+
+/* Backwards compatible IRQ macros. */
+#define INT_ADM_AARM ADM_0_SCSS_0_IRQ
+
+/* smd/smsm interrupts */
+#define INT_A9_M2A_0 (GIC_SPI_START + 37) /*MSS_TO_APPS_IRQ_0*/
+#define INT_A9_M2A_5 (GIC_SPI_START + 38) /*MSS_TO_APPS_IRQ_1*/
+#define INT_ADSP_A11 LPASS_SCSS_GP_HIGH_IRQ
+#define INT_ADSP_A11_SMSM LPASS_SCSS_GP_MEDIUM_IRQ
+#define INT_DSPS_A11 SPS_MTI_31
+#define INT_DSPS_A11_SMSM SPS_MTI_30
+#define INT_WCNSS_A11 RIVA_APSS_SPARE_IRQ
+#define INT_WCNSS_A11_SMSM RIVA_APPS_WLAN_SMSM_IRQ
+
+#endif
+
diff --git a/arch/arm/mach-msm/include/mach/irqs.h b/arch/arm/mach-msm/include/mach/irqs.h
index f38eddb..b086bff 100644
--- a/arch/arm/mach-msm/include/mach/irqs.h
+++ b/arch/arm/mach-msm/include/mach/irqs.h
@@ -19,12 +19,17 @@
#define MSM_IRQ_BIT(irq) (1 << ((irq) & 31))
-#if defined(CONFIG_ARCH_MSM8960) || defined(CONFIG_ARCH_APQ8064)
+#if defined(CONFIG_ARCH_MSM8960) || defined(CONFIG_ARCH_APQ8064) || \
+ defined(CONFIG_ARCH_MSM8930)
#ifdef CONFIG_ARCH_MSM8960
#include "irqs-8960.h"
#endif
+#ifdef CONFIG_ARCH_MSM8930
+#include "irqs-8930.h"
+#endif
+
#ifdef CONFIG_ARCH_APQ8064
#include "irqs-8064.h"
#endif
diff --git a/arch/arm/mach-msm/include/mach/msm-krait-l2-accessors.h b/arch/arm/mach-msm/include/mach/msm-krait-l2-accessors.h
index 507d717..f835e82 100644
--- a/arch/arm/mach-msm/include/mach/msm-krait-l2-accessors.h
+++ b/arch/arm/mach-msm/include/mach/msm-krait-l2-accessors.h
@@ -13,24 +13,8 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
-#ifdef CONFIG_ARCH_MSM_KRAIT
extern void set_l2_indirect_reg(u32 reg_addr, u32 val);
extern u32 get_l2_indirect_reg(u32 reg_addr);
extern u32 set_get_l2_indirect_reg(u32 reg_addr, u32 val);
-#else
-void set_l2_indirect_reg(u32 reg_addr, u32 val)
-{
-}
-
-u32 set_get_l2_indirect_reg(u32 reg_addr, u32 val)
-{
- return 0;
-}
-
-u32 get_l2_indirect_reg(u32 reg_addr)
-{
- return 0;
-}
-#endif
#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_bus_board.h b/arch/arm/mach-msm/include/mach/msm_bus_board.h
index add2836..644e1b1 100644
--- a/arch/arm/mach-msm/include/mach/msm_bus_board.h
+++ b/arch/arm/mach-msm/include/mach/msm_bus_board.h
@@ -35,6 +35,7 @@
const unsigned int nmasters;
const unsigned int nslaves;
const unsigned int ntieredslaves;
+ bool il_flag;
};
enum msm_bus_bw_tier_type {
@@ -59,6 +60,7 @@
*fabreg, int fabid);
int msm_bus_board_get_iid(int id);
void msm_bus_rpm_set_mt_mask(void);
+int msm_bus_board_rpm_get_il_ids(uint16_t *id);
/*
* These macros specify the convention followed for allocating
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
index 571391b..d1aef0a 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
@@ -58,10 +58,6 @@
#define MSM_GPT_BASE MSM_TMR_BASE
#define MSM_DGT_BASE (MSM_TMR_BASE + 0x10)
-#define MSM_DMOV_BASE IOMEM(0xF8002000)
-#define MSM_DMOV_PHYS 0xA9700000
-#define MSM_DMOV_SIZE SZ_4K
-
#define MSM_GPIO1_BASE IOMEM(0xF8003000)
#define MSM_GPIO1_PHYS 0xA9200000
#define MSM_GPIO1_SIZE SZ_4K
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
index fce9e35..e49e870 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
@@ -47,10 +47,6 @@
#define MSM_TMR_BASE MSM_CSR_BASE
#define MSM_TMR_SIZE SZ_4K
-#define MSM_DMOV_BASE IOMEM(0xFA002000)
-#define MSM_DMOV_PHYS 0xAC400000
-#define MSM_DMOV_SIZE SZ_4K
-
#define MSM_GPIO1_BASE IOMEM(0xFA003000)
#define MSM_GPIO1_PHYS 0xAC001000
#define MSM_GPIO1_SIZE SZ_4K
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7xxx.h b/arch/arm/mach-msm/include/mach/msm_iomap-7xxx.h
index 1fb9d0e..da0c54c 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7xxx.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7xxx.h
@@ -47,10 +47,6 @@
#define MSM_TMR_BASE MSM_CSR_BASE
#define MSM_TMR_SIZE SZ_4K
-#define MSM_DMOV_BASE IOMEM(0xFA002000)
-#define MSM_DMOV_PHYS 0xA9700000
-#define MSM_DMOV_SIZE SZ_4K
-
#define MSM_GPIO1_BASE IOMEM(0xFA003000)
#define MSM_GPIO1_PHYS 0xA9200000
#define MSM_GPIO1_SIZE SZ_4K
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8064.h b/arch/arm/mach-msm/include/mach/msm_iomap-8064.h
index 665ccd0..7f5bd75 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8064.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8064.h
@@ -44,9 +44,6 @@
#define APQ8064_QGIC_CPU_PHYS 0x02002000
#define APQ8064_QGIC_CPU_SIZE SZ_4K
-#define APQ8064_DMOV_PHYS 0x18300000
-#define APQ8064_DMOV_SIZE SZ_1M
-
#define APQ8064_TLMM_PHYS 0x00800000
#define APQ8064_TLMM_SIZE SZ_16K
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8930.h b/arch/arm/mach-msm/include/mach/msm_iomap-8930.h
new file mode 100644
index 0000000..8e50824
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8930.h
@@ -0,0 +1,116 @@
+/*
+ * Copyright (C) 2007 Google, Inc.
+ * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
+ * Author: Brian Swetland <swetland@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *
+ * The MSM peripherals are spread all over across 768MB of physical
+ * space, which makes just having a simple IO_ADDRESS macro to slide
+ * them into the right virtual location rough. Instead, we will
+ * provide a master phys->virt mapping for peripherals here.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_IOMAP_8930_H
+#define __ASM_ARCH_MSM_IOMAP_8930_H
+
+/* Physical base address and size of peripherals.
+ * Ordered by the virtual base addresses they will be mapped at.
+ *
+ * If you add or remove entries here, you'll want to edit the
+ * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
+ * changes.
+ *
+ */
+
+#define MSM8930_TMR_PHYS 0x0200A000
+#define MSM8930_TMR_SIZE SZ_4K
+
+#define MSM8930_TMR0_PHYS 0x0208A000
+#define MSM8930_TMR0_SIZE SZ_4K
+
+#define MSM8930_RPM_PHYS 0x00108000
+#define MSM8930_RPM_SIZE SZ_4K
+
+#define MSM8930_RPM_MPM_PHYS 0x00200000
+#define MSM8930_RPM_MPM_SIZE SZ_4K
+
+#define MSM8930_TCSR_PHYS 0x1A400000
+#define MSM8930_TCSR_SIZE SZ_4K
+
+#define MSM8930_APCS_GCC_PHYS 0x02011000
+#define MSM8930_APCS_GCC_SIZE SZ_4K
+
+#define MSM8930_SAW_L2_PHYS 0x02012000
+#define MSM8930_SAW_L2_SIZE SZ_4K
+
+#define MSM8930_SAW0_PHYS 0x02089000
+#define MSM8930_SAW0_SIZE SZ_4K
+
+#define MSM8930_SAW1_PHYS 0x02099000
+#define MSM8930_SAW1_SIZE SZ_4K
+
+#define MSM8930_IMEM_PHYS 0x2A03F000
+#define MSM8930_IMEM_SIZE SZ_4K
+
+#define MSM8930_ACC0_PHYS 0x02088000
+#define MSM8930_ACC0_SIZE SZ_4K
+
+#define MSM8930_ACC1_PHYS 0x02098000
+#define MSM8930_ACC1_SIZE SZ_4K
+
+#define MSM8930_QGIC_DIST_PHYS 0x02000000
+#define MSM8930_QGIC_DIST_SIZE SZ_4K
+
+#define MSM8930_QGIC_CPU_PHYS 0x02002000
+#define MSM8930_QGIC_CPU_SIZE SZ_4K
+
+#define MSM8930_CLK_CTL_PHYS 0x00900000
+#define MSM8930_CLK_CTL_SIZE SZ_16K
+
+#define MSM8930_MMSS_CLK_CTL_PHYS 0x04000000
+#define MSM8930_MMSS_CLK_CTL_SIZE SZ_4K
+
+#define MSM8930_LPASS_CLK_CTL_PHYS 0x28000000
+#define MSM8930_LPASS_CLK_CTL_SIZE SZ_4K
+
+#define MSM8930_HFPLL_PHYS 0x00903000
+#define MSM8930_HFPLL_SIZE SZ_4K
+
+#define MSM8930_TLMM_PHYS 0x00800000
+#define MSM8930_TLMM_SIZE SZ_16K
+
+#define MSM8930_DMOV_PHYS 0x18320000
+#define MSM8930_DMOV_SIZE SZ_1M
+
+#define MSM8930_SIC_NON_SECURE_PHYS 0x12100000
+#define MSM8930_SIC_NON_SECURE_SIZE SZ_64K
+
+#define MSM_GPT_BASE (MSM_TMR_BASE + 0x4)
+#define MSM_DGT_BASE (MSM_TMR_BASE + 0x24)
+
+#define MSM8930_HDMI_PHYS 0x04A00000
+#define MSM8930_HDMI_SIZE SZ_4K
+
+#ifdef CONFIG_MSM_DEBUG_UART
+#define MSM_DEBUG_UART_BASE IOMEM(0xFA740000)
+#define MSM_DEBUG_UART_SIZE SZ_4K
+
+#ifdef CONFIG_MSM_DEBUG_UART1
+#define MSM_DEBUG_UART_PHYS 0x16440000
+#endif
+#endif
+
+#define MSM8930_QFPROM_PHYS 0x00700000
+#define MSM8930_QFPROM_SIZE SZ_4K
+
+#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
index e6b7beb..24505ae 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
@@ -89,21 +89,12 @@
#define MSM8960_TLMM_PHYS 0x00800000
#define MSM8960_TLMM_SIZE SZ_16K
-#define MSM8960_DMOV_PHYS 0x18320000
-#define MSM8960_DMOV_SIZE SZ_1M
-
#define MSM8960_SIC_NON_SECURE_PHYS 0x12100000
#define MSM8960_SIC_NON_SECURE_SIZE SZ_64K
#define MSM_GPT_BASE (MSM_TMR_BASE + 0x4)
#define MSM_DGT_BASE (MSM_TMR_BASE + 0x24)
-#define MSM8960_HSUSB_PHYS 0x12500000
-#define MSM8960_HSUSB_SIZE SZ_4K
-
-#define MSM_HSIC_PHYS 0x12520000
-#define MSM_HSIC_SIZE SZ_4K
-
#define MSM8960_HDMI_PHYS 0x04A00000
#define MSM8960_HDMI_SIZE SZ_4K
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
index cab4027..a073d6a 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
@@ -47,10 +47,6 @@
#define MSM_TMR_BASE MSM_CSR_BASE
#define MSM_TMR_SIZE SZ_4K
-#define MSM_DMOV_BASE IOMEM(0xFA002000)
-#define MSM_DMOV_PHYS 0xA9700000
-#define MSM_DMOV_SIZE SZ_4K
-
#define MSM_GPIO1_BASE IOMEM(0xFA003000)
#define MSM_GPIO1_PHYS 0xA9000000
#define MSM_GPIO1_SIZE SZ_4K
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
index 4b91733..c1cf221 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
@@ -106,14 +106,6 @@
#define MSM_SAW1_PHYS 0x02052000
#define MSM_SAW1_SIZE SZ_4K
-#define MSM_DMOV_ADM0_BASE IOMEM(0xFA400000)
-#define MSM_DMOV_ADM0_PHYS 0x18320000
-#define MSM_DMOV_ADM0_SIZE SZ_1M
-
-#define MSM_DMOV_ADM1_BASE IOMEM(0xFA500000)
-#define MSM_DMOV_ADM1_PHYS 0x18420000
-#define MSM_DMOV_ADM1_SIZE SZ_1M
-
#define MSM_SIC_NON_SECURE_BASE IOMEM(0xFA600000)
#define MSM_SIC_NON_SECURE_PHYS 0x12100000
#define MSM_SIC_NON_SECURE_SIZE SZ_64K
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-9615.h b/arch/arm/mach-msm/include/mach/msm_iomap-9615.h
index e842f8e..dda5f50 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-9615.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-9615.h
@@ -41,9 +41,6 @@
#define MSM9615_QGIC_CPU_PHYS 0x02002000
#define MSM9615_QGIC_CPU_SIZE SZ_4K
-#define MSM9615_DMOV_PHYS 0x18320000
-#define MSM9615_DMOV_SIZE SZ_1M
-
#define MSM9615_TLMM_PHYS 0x00800000
#define MSM9615_TLMM_SIZE SZ_1M
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-fsm9xxx.h b/arch/arm/mach-msm/include/mach/msm_iomap-fsm9xxx.h
index 5261bcc..57bfd58 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-fsm9xxx.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-fsm9xxx.h
@@ -64,24 +64,6 @@
#define MSM_GRFC_PHYS 0x94038000
#define MSM_GRFC_SIZE SZ_4K
-#define MSM_DMOV_SD0_BASE IOMEM(0xFA00A000)
-#define MSM_DMOV_SD0_PHYS 0x94310000
-#define MSM_DMOV_SD0_SIZE SZ_4K
-
-#define MSM_DMOV_SD1_BASE IOMEM(0xFA00B000)
-#define MSM_DMOV_SD1_PHYS 0x94410000
-#define MSM_DMOV_SD1_SIZE SZ_4K
-
-#define MSM_DMOV_SD2_BASE IOMEM(0xFA00C000)
-#define MSM_DMOV_SD2_PHYS 0x94510000
-#define MSM_DMOV_SD2_SIZE SZ_4K
-
-#define MSM_DMOV_SD3_BASE IOMEM(0xFA00D000)
-#define MSM_DMOV_SD3_PHYS 0x94610000
-#define MSM_DMOV_SD3_SIZE SZ_4K
-
-#define MSM_DMOV_BASE MSM_DMOV_SD0_BASE
-
#define MSM_QFP_FUSE_BASE IOMEM(0xFA010000)
#define MSM_QFP_FUSE_PHYS 0x80000000
#define MSM_QFP_FUSE_SIZE SZ_32K
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
index df19606..426dbad 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap.h
@@ -43,8 +43,8 @@
#define IOMEM(x) ((void __force __iomem *)(x))
#endif
-#if defined(CONFIG_ARCH_MSM8960) || defined(CONFIG_ARCH_APQ8064) \
- || defined(CONFIG_ARCH_MSM9615)
+#if defined(CONFIG_ARCH_MSM8960) || defined(CONFIG_ARCH_APQ8064) || \
+ defined(CONFIG_ARCH_MSM8930) || defined(CONFIG_ARCH_MSM9615)
/* Unified iomap */
#define MSM_TMR_BASE IOMEM(0xFA000000) /* 4K */
@@ -67,7 +67,6 @@
#define MSM_HFPLL_BASE IOMEM(0xFA016000) /* 4K */
#define MSM_TLMM_BASE IOMEM(0xFA017000) /* 16K */
#define MSM_SHARED_RAM_BASE IOMEM(0xFA300000) /* 2M */
-#define MSM_DMOV_BASE IOMEM(0xFA500000) /* 1M */
#define MSM_SIC_NON_SECURE_BASE IOMEM(0xFA600000) /* 64K */
#define MSM_HDMI_BASE IOMEM(0xFA800000) /* 4K */
#define MSM_RPM_BASE IOMEM(0xFA801000) /* 4K */
@@ -83,6 +82,7 @@
#endif
#include "msm_iomap-8960.h"
+#include "msm_iomap-8930.h"
#include "msm_iomap-8064.h"
#include "msm_iomap-9615.h"
diff --git a/arch/arm/mach-msm/include/mach/usb_dun_bridge.h b/arch/arm/mach-msm/include/mach/usb_dun_bridge.h
new file mode 100644
index 0000000..b4a8eef
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/usb_dun_bridge.h
@@ -0,0 +1,113 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __USB_DUN_BRIDGE_H
+#define __USB_DUN_BRIDGE_H
+
+/**
+ * struct dun_bridge_ops - context and callbacks for DUN bridge
+ *
+ * @ctxt: caller private context
+ * @read_complete: called when read is completed. buf and len correspond
+ * to original passed-in values. actual length of buffer returned, or
+ * negative error value.
+ * @write_complete: called when write is completed. buf and len correspond
+ * to original passed-in values. actual length of buffer returned, or
+ * negative error value.
+ * @ctrl_status: asynchronous notification of control status. ctrl_bits
+ * is a bitfield of CDC ACM control status bits.
+ */
+struct dun_bridge_ops {
+ void *ctxt;
+ void (*read_complete)(void *ctxt, char *buf, size_t len, size_t actual);
+ void (*write_complete)(void *ctxt, char *buf,
+ size_t len, size_t actual);
+ void (*ctrl_status)(void *ctxt, unsigned int ctrl_bits);
+};
+
+#ifdef CONFIG_USB_QCOM_DUN_BRIDGE
+
+/**
+ * dun_bridge_open - Open the DUN bridge
+ *
+ * @ops: pointer to ops struct containing private context and callback
+ * pointers
+ */
+int dun_bridge_open(struct dun_bridge_ops *ops);
+
+/**
+ * dun_bridge_close - Closes the DUN bridge
+ */
+int dun_bridge_close(void);
+
+/**
+ * dun_bridge_read - Request to read data from the DUN bridge. This call is
+ * asynchronous: user's read callback (ops->read_complete) will be called
+ * when data is returned.
+ *
+ * @data: pointer to caller-allocated buffer to fill in
+ * @len: size of the buffer
+ */
+int dun_bridge_read(void *data, int len);
+
+/**
+ * dun_bridge_write - Request to write data to the DUN bridge. This call is
+ * asynchronous: user's write callback (ops->write_complete) will be called
+ * upon completion of the write indicating status and number of bytes
+ * written.
+ *
+ * @data: pointer to caller-allocated buffer to write
+ * @len: length of the data in buffer
+ */
+int dun_bridge_write(void *data, int len);
+
+/**
+ * dun_bridge_send_ctrl_bits - Request to write line control data to the DUN
+ * bridge. This call is asynchronous, however no callback will be issued
+ * upon completion.
+ *
+ * @ctrl_bits: CDC ACM line control bits
+ */
+int dun_bridge_send_ctrl_bits(unsigned ctrl_bits);
+
+#else
+
+#include <linux/errno.h>
+
+static int __maybe_unused dun_bridge_open(struct dun_bridge_ops *ops)
+{
+ return -ENODEV;
+}
+
+static int __maybe_unused dun_bridge_close(void)
+{
+ return -ENODEV;
+}
+
+static int __maybe_unused dun_bridge_read(void *data, int len)
+{
+ return -ENODEV;
+}
+
+static int __maybe_unused dun_bridge_write(void *data, int len)
+{
+ return -ENODEV;
+}
+
+static int __maybe_unused dun_bridge_send_ctrl_bits(unsigned ctrl_bits)
+{
+ return -ENODEV;
+}
+
+#endif
+
+#endif
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 3bb10fb..72acab8 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -61,7 +61,6 @@
MSM_DEVICE(VIC),
MSM_DEVICE(CSR),
MSM_DEVICE(TMR),
- MSM_DEVICE(DMOV),
MSM_DEVICE(GPIO1),
MSM_DEVICE(GPIO2),
MSM_DEVICE(CLK_CTL),
@@ -106,7 +105,6 @@
MSM_DEVICE(VIC),
MSM_DEVICE(CSR),
MSM_DEVICE(TMR),
- MSM_DEVICE(DMOV),
MSM_DEVICE(GPIO1),
MSM_DEVICE(GPIO2),
MSM_DEVICE(CLK_CTL),
@@ -145,8 +143,6 @@
MSM_DEVICE(SAW1),
MSM_DEVICE(GCC),
MSM_DEVICE(TLMM),
- MSM_DEVICE(DMOV_ADM0),
- MSM_DEVICE(DMOV_ADM1),
MSM_DEVICE(SCPLL),
MSM_DEVICE(RPM),
MSM_DEVICE(CLK_CTL),
@@ -186,7 +182,6 @@
MSM_CHIP_DEVICE(MMSS_CLK_CTL, MSM8960),
MSM_CHIP_DEVICE(LPASS_CLK_CTL, MSM8960),
MSM_CHIP_DEVICE(RPM, MSM8960),
- MSM_CHIP_DEVICE(DMOV, MSM8960),
MSM_CHIP_DEVICE(TLMM, MSM8960),
MSM_CHIP_DEVICE(HFPLL, MSM8960),
MSM_CHIP_DEVICE(SAW0, MSM8960),
@@ -213,13 +208,51 @@
}
#endif /* CONFIG_ARCH_MSM8960 */
+#ifdef CONFIG_ARCH_MSM8930
+static struct map_desc msm8930_io_desc[] __initdata = {
+ MSM_CHIP_DEVICE(QGIC_DIST, MSM8930),
+ MSM_CHIP_DEVICE(QGIC_CPU, MSM8930),
+ MSM_CHIP_DEVICE(ACC0, MSM8930),
+ MSM_CHIP_DEVICE(ACC1, MSM8930),
+ MSM_CHIP_DEVICE(TMR, MSM8930),
+ MSM_CHIP_DEVICE(TMR0, MSM8930),
+ MSM_CHIP_DEVICE(RPM_MPM, MSM8930),
+ MSM_CHIP_DEVICE(CLK_CTL, MSM8930),
+ MSM_CHIP_DEVICE(MMSS_CLK_CTL, MSM8930),
+ MSM_CHIP_DEVICE(LPASS_CLK_CTL, MSM8930),
+ MSM_CHIP_DEVICE(RPM, MSM8930),
+ MSM_CHIP_DEVICE(TLMM, MSM8930),
+ MSM_CHIP_DEVICE(HFPLL, MSM8930),
+ MSM_CHIP_DEVICE(SAW0, MSM8930),
+ MSM_CHIP_DEVICE(SAW1, MSM8930),
+ MSM_CHIP_DEVICE(SAW_L2, MSM8930),
+ MSM_CHIP_DEVICE(SIC_NON_SECURE, MSM8930),
+ MSM_CHIP_DEVICE(APCS_GCC, MSM8930),
+ MSM_CHIP_DEVICE(IMEM, MSM8930),
+ MSM_CHIP_DEVICE(HDMI, MSM8930),
+ {
+ .virtual = (unsigned long) MSM_SHARED_RAM_BASE,
+ .length = MSM_SHARED_RAM_SIZE,
+ .type = MT_DEVICE,
+ },
+#ifdef CONFIG_MSM_DEBUG_UART
+ MSM_DEVICE(DEBUG_UART),
+#endif
+ MSM_CHIP_DEVICE(QFPROM, MSM8930),
+};
+
+void __init msm_map_msm8930_io(void)
+{
+ msm_map_io(msm8930_io_desc, ARRAY_SIZE(msm8930_io_desc));
+}
+#endif /* CONFIG_ARCH_MSM8930 */
+
#ifdef CONFIG_ARCH_APQ8064
static struct map_desc apq8064_io_desc[] __initdata = {
MSM_CHIP_DEVICE(QGIC_DIST, APQ8064),
MSM_CHIP_DEVICE(QGIC_CPU, APQ8064),
MSM_CHIP_DEVICE(TMR, APQ8064),
MSM_CHIP_DEVICE(TMR0, APQ8064),
- MSM_CHIP_DEVICE(DMOV, APQ8064),
MSM_CHIP_DEVICE(TLMM, APQ8064),
MSM_CHIP_DEVICE(ACC0, APQ8064),
MSM_CHIP_DEVICE(ACC1, APQ8064),
@@ -249,7 +282,6 @@
MSM_DEVICE(VIC),
MSM_DEVICE(CSR),
MSM_DEVICE(TMR),
- MSM_DEVICE(DMOV),
MSM_DEVICE(GPIO1),
MSM_DEVICE(GPIO2),
MSM_DEVICE(CLK_CTL),
@@ -288,10 +320,6 @@
MSM_DEVICE(SAW),
MSM_DEVICE(GCC),
MSM_DEVICE(GRFC),
- MSM_DEVICE(DMOV_SD0),
- MSM_DEVICE(DMOV_SD1),
- MSM_DEVICE(DMOV_SD2),
- MSM_DEVICE(DMOV_SD3),
MSM_DEVICE(QFP_FUSE),
MSM_DEVICE(HH),
#ifdef CONFIG_MSM_DEBUG_UART
@@ -316,7 +344,6 @@
MSM_CHIP_DEVICE(QGIC_CPU, MSM9615),
MSM_CHIP_DEVICE(ACC0, MSM9615),
MSM_CHIP_DEVICE(TMR, MSM9615),
- MSM_CHIP_DEVICE(DMOV, MSM9615),
MSM_CHIP_DEVICE(TLMM, MSM9615),
MSM_CHIP_DEVICE(SAW0, MSM9615),
MSM_CHIP_DEVICE(APCS_GCC, MSM9615),
diff --git a/arch/arm/mach-msm/irq-vic.c b/arch/arm/mach-msm/irq-vic.c
index 109231a..660d530 100644
--- a/arch/arm/mach-msm/irq-vic.c
+++ b/arch/arm/mach-msm/irq-vic.c
@@ -610,6 +610,33 @@
mb();
}
+static inline void msm_vic_handle_irq(void __iomem *base_addr, struct pt_regs
+ *regs)
+{
+ u32 irqnr;
+
+ do {
+ /* 0xD0 has irq# or old irq# if the irq has been handled
+ * 0xD4 has irq# or -1 if none pending *but* if you just
+ * read 0xD4 you never get the first irq for some reason
+ */
+ irqnr = readl_relaxed(base_addr + 0xD0);
+ irqnr = readl_relaxed(base_addr + 0xD4);
+ if (irqnr == -1)
+ break;
+ handle_IRQ(irqnr, regs);
+ } while (1);
+}
+
+/* enable imprecise aborts */
+#define local_cpsie_enable() __asm__ __volatile__("cpsie a @ enable")
+
+asmlinkage void __exception_irq_entry vic_handle_irq(struct pt_regs *regs)
+{
+ local_cpsie_enable();
+ msm_vic_handle_irq((void __iomem *)MSM_VIC_BASE, regs);
+}
+
#if defined(CONFIG_MSM_FIQ_SUPPORT)
void msm_trigger_irq(int irq)
{
diff --git a/arch/arm/mach-msm/msm-krait-l2-accessors.c b/arch/arm/mach-msm/msm-krait-l2-accessors.c
index 61b5228..b03e2d2 100644
--- a/arch/arm/mach-msm/msm-krait-l2-accessors.c
+++ b/arch/arm/mach-msm/msm-krait-l2-accessors.c
@@ -12,6 +12,7 @@
*/
#include <linux/spinlock.h>
+#include <linux/module.h>
#include <asm/mach-types.h>
DEFINE_RAW_SPINLOCK(l2_access_lock);
@@ -40,6 +41,7 @@
return ret_val;
}
+EXPORT_SYMBOL(set_get_l2_indirect_reg);
void set_l2_indirect_reg(u32 reg_addr, u32 val)
{
@@ -58,6 +60,7 @@
isb();
raw_spin_unlock_irqrestore(&l2_access_lock, flags);
}
+EXPORT_SYMBOL(set_l2_indirect_reg);
u32 get_l2_indirect_reg(u32 reg_addr)
{
@@ -77,3 +80,4 @@
return val;
}
+EXPORT_SYMBOL(get_l2_indirect_reg);
diff --git a/arch/arm/mach-msm/msm_bus/msm_bus_board_8660.c b/arch/arm/mach-msm/msm_bus/msm_bus_board_8660.c
index ddf56c8..13b59ed 100644
--- a/arch/arm/mach-msm/msm_bus/msm_bus_board_8660.c
+++ b/arch/arm/mach-msm/msm_bus/msm_bus_board_8660.c
@@ -906,3 +906,7 @@
SLAVE_ID_KEY]);
}
+int msm_bus_board_rpm_get_il_ids(uint16_t id[])
+{
+ return -ENXIO;
+}
diff --git a/arch/arm/mach-msm/msm_bus/msm_bus_board_8960.c b/arch/arm/mach-msm/msm_bus/msm_bus_board_8960.c
index 1819d95..8ab1899 100644
--- a/arch/arm/mach-msm/msm_bus/msm_bus_board_8960.c
+++ b/arch/arm/mach-msm/msm_bus/msm_bus_board_8960.c
@@ -939,3 +939,9 @@
SLAVE_ID_KEY]);
}
+int msm_bus_board_rpm_get_il_ids(uint16_t id[])
+{
+ id[0] = MSM_RPM_STATUS_ID_EBI1_CH0_RANGE;
+ id[1] = MSM_RPM_STATUS_ID_EBI1_CH1_RANGE;
+ return 0;
+}
diff --git a/arch/arm/mach-msm/msm_bus/msm_bus_core.h b/arch/arm/mach-msm/msm_bus/msm_bus_core.h
index cc1eb78..56a5b8da 100644
--- a/arch/arm/mach-msm/msm_bus/msm_bus_core.h
+++ b/arch/arm/mach-msm/msm_bus/msm_bus_core.h
@@ -170,6 +170,7 @@
long int add_bw);
void msm_bus_rpm_fill_cdata_buffer(int *curr, char *buf, const int max_size,
void *cdata, int nmasters, int nslaves, int ntslaves);
+bool msm_bus_rpm_is_mem_interleaved(void);
#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_MSM_BUS_SCALING)
void msm_bus_dbg_client_data(struct msm_bus_scale_pdata *pdata, int index,
diff --git a/arch/arm/mach-msm/msm_bus/msm_bus_fabric.c b/arch/arm/mach-msm/msm_bus/msm_bus_fabric.c
index d8323e3..fe6dbed 100644
--- a/arch/arm/mach-msm/msm_bus/msm_bus_fabric.c
+++ b/arch/arm/mach-msm/msm_bus/msm_bus_fabric.c
@@ -650,6 +650,7 @@
pdata = (struct msm_bus_fabric_registration *)pdev->dev.platform_data;
fabric->fabdev.name = pdata->name;
fabric->fabdev.algo = &msm_bus_algo;
+ pdata->il_flag = msm_bus_rpm_is_mem_interleaved();
fabric->ahb = pdata->ahb;
fabric->pdata = pdata;
msm_bus_board_assign_iids(fabric->pdata, fabric->fabdev.id);
diff --git a/arch/arm/mach-msm/msm_bus/msm_bus_rpm.c b/arch/arm/mach-msm/msm_bus/msm_bus_rpm.c
index ec0db42..332d3c1 100644
--- a/arch/arm/mach-msm/msm_bus/msm_bus_rpm.c
+++ b/arch/arm/mach-msm/msm_bus/msm_bus_rpm.c
@@ -22,6 +22,10 @@
#include "msm_bus_core.h"
#include "../rpm_resources.h"
+#define INTERLEAVED_BW(fab_pdata, bw, ports) \
+ ((fab_pdata->il_flag) ? ((bw) / (ports)) : (bw))
+#define INTERLEAVED_VAL(fab_pdata, n) \
+ ((fab_pdata->il_flag) ? (n) : 1)
void msm_bus_rpm_set_mt_mask()
{
@@ -35,6 +39,47 @@
#endif
}
+bool msm_bus_rpm_is_mem_interleaved(void)
+{
+ int status = 0;
+ struct msm_rpm_iv_pair il[2];
+ uint16_t id[2];
+
+ il[0].value = 0;
+ il[1].value = 0;
+ status = msm_bus_board_rpm_get_il_ids(id);
+ if (status) {
+ MSM_BUS_DBG("Dynamic check not supported, "
+ "default: Interleaved memory\n");
+ goto inter;
+ }
+
+ il[0].id = id[0];
+ il[1].id = id[1];
+ status = msm_rpm_get_status(il, ARRAY_SIZE(il));
+ if (status) {
+ MSM_BUS_ERR("Status read for interleaving returned: %d\n"
+ "Using interleaved memory by default\n",
+ status);
+ goto inter;
+ }
+
+ /*
+ * If the start address of EBI1-CH0 is the same as
+ * the start address of EBI1-CH1, the memory is interleaved.
+ * The start addresses are stored in the 16 MSBs of the status
+ * register
+ */
+ if ((il[0].value & 0xFFFF0000) != (il[1].value & 0xFFFF0000)) {
+ MSM_BUS_DBG("Non-interleaved memory\n");
+ return false;
+ }
+
+inter:
+ MSM_BUS_DBG("Interleaved memory\n");
+ return true;
+}
+
#ifndef CONFIG_MSM_BUS_RPM_MULTI_TIER_ENABLED
struct commit_data {
uint16_t *bwsum;
@@ -198,13 +243,14 @@
void *sel_cdata, int *master_tiers,
long int add_bw)
{
- int index, i, j;
+ int index, i, j, tiers, ports;
struct commit_data *sel_cd = (struct commit_data *)sel_cdata;
- add_bw /= info->node_info->num_mports;
- for (i = 0; i < hop->node_info->num_tiers; i++) {
- for (j = 0; j < info->node_info->num_mports; j++) {
-
+ add_bw = INTERLEAVED_BW(fab_pdata, add_bw, info->node_info->num_mports);
+ ports = INTERLEAVED_VAL(fab_pdata, info->node_info->num_mports);
+ tiers = INTERLEAVED_VAL(fab_pdata, hop->node_info->num_tiers);
+ for (i = 0; i < tiers; i++) {
+ for (j = 0; j < ports; j++) {
uint16_t hop_tier;
/*
* For interleaved gateway ports and slave ports,
@@ -246,8 +292,9 @@
&& hop->node_info->num_sports > 1)
tieredbw += add_bw;
else
- tieredbw += add_bw/
- hop->node_info->num_sports;
+ tieredbw += INTERLEAVED_BW(fab_pdata,
+ add_bw, hop->node_info->
+ num_sports);
/* If bw is 0, update tier to default */
if (!tieredbw)
@@ -265,7 +312,8 @@
}
/* Update bwsum for slaves on fabric */
- for (i = 0; i < hop->node_info->num_sports; i++) {
+ ports = INTERLEAVED_VAL(fab_pdata, hop->node_info->num_sports);
+ for (i = 0; i < ports; i++) {
sel_cd->bwsum[hop->node_info->slavep[i]]
= (uint16_t)msm_bus_create_bw_tier_pair_bytes(0,
(*hop->link_info.sel_bw/hop->node_info->num_sports));
@@ -627,13 +675,14 @@
void *sel_cdata, int *master_tiers,
long int add_bw)
{
- int index, i, j;
+ int index, i, j, tiers, ports;
struct commit_data *sel_cd = (struct commit_data *)sel_cdata;
- add_bw /= info->node_info->num_mports;
- for (i = 0; i < hop->node_info->num_tiers; i++) {
- for (j = 0; j < info->node_info->num_mports; j++) {
-
+ add_bw = INTERLEAVED_BW(fab_pdata, add_bw, info->node_info->num_mports);
+ ports = INTERLEAVED_VAL(fab_pdata, info->node_info->num_mports);
+ tiers = INTERLEAVED_VAL(fab_pdata, hop->node_info->num_tiers);
+ for (i = 0; i < tiers; i++) {
+ for (j = 0; j < ports; j++) {
uint16_t hop_tier;
/*
* For interleaved gateway ports and slave ports,
@@ -668,8 +717,9 @@
&& hop->node_info->num_sports > 1)
tieredbw += add_bw;
else
- tieredbw += add_bw/
- hop->node_info->num_sports;
+ tieredbw += INTERLEAVED_BW(fab_pdata,
+ add_bw, hop->node_info->
+ num_sports);
/* Update Arb for fab,get HW Mport from enum */
sel_cd->arb[tier][index] =
@@ -683,7 +733,9 @@
}
/* Update bwsum for slaves on fabric */
- for (i = 0; i < hop->node_info->num_sports; i++) {
+
+ ports = INTERLEAVED_VAL(fab_pdata, hop->node_info->num_sports);
+ for (i = 0; i < ports; i++) {
sel_cd->bwsum[hop->node_info->slavep[i]]
= msm_bus_pack_bwsum_bytes((*hop->link_info.
sel_bw/hop->node_info->num_sports));
diff --git a/arch/arm/mach-msm/msm_rq_stats.c b/arch/arm/mach-msm/msm_rq_stats.c
index 81c8ad5..a39703a 100644
--- a/arch/arm/mach-msm/msm_rq_stats.c
+++ b/arch/arm/mach-msm/msm_rq_stats.c
@@ -13,7 +13,6 @@
/*
* Qualcomm MSM Runqueue Stats Interface for Userspace
*/
-
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
@@ -26,60 +25,11 @@
#include <linux/workqueue.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
+#include <linux/rq_stats.h>
-struct rq_data {
- unsigned int rq_avg;
- unsigned int rq_poll_ms;
- unsigned int def_timer_ms;
- unsigned int def_interval;
- int64_t last_time;
- int64_t total_time;
- int64_t def_start_time;
- struct delayed_work rq_work;
- struct attribute_group *attr_group;
- struct kobject *kobj;
- struct delayed_work def_timer_work;
-};
-
-static struct rq_data rq_info;
-static DEFINE_SPINLOCK(rq_lock);
-static struct workqueue_struct *rq_wq;
-
-static void rq_work_fn(struct work_struct *work)
-{
- int64_t time_diff = 0;
- int64_t rq_avg = 0;
- unsigned long flags = 0;
-
- spin_lock_irqsave(&rq_lock, flags);
-
- if (!rq_info.last_time)
- rq_info.last_time = ktime_to_ns(ktime_get());
- if (!rq_info.rq_avg)
- rq_info.total_time = 0;
-
- rq_avg = nr_running() * 10;
- time_diff = ktime_to_ns(ktime_get()) - rq_info.last_time;
- do_div(time_diff, (1000 * 1000));
-
- if (time_diff && rq_info.total_time) {
- rq_avg = (rq_avg * time_diff) +
- (rq_info.rq_avg * rq_info.total_time);
- do_div(rq_avg, rq_info.total_time + time_diff);
- }
-
- rq_info.rq_avg = (unsigned int)rq_avg;
-
- /* Set the next poll */
- if (rq_info.rq_poll_ms)
- queue_delayed_work(rq_wq, &rq_info.rq_work,
- msecs_to_jiffies(rq_info.rq_poll_ms));
-
- rq_info.total_time += time_diff;
- rq_info.last_time = ktime_to_ns(ktime_get());
-
- spin_unlock_irqrestore(&rq_lock, flags);
-}
+#define MAX_LONG_SIZE 16
+#define DEFAULT_RQ_POLL_JIFFIES 1
+#define DEFAULT_DEF_TIMER_JIFFIES 5
static void def_work_fn(struct work_struct *work)
{
@@ -109,22 +59,24 @@
}
static ssize_t show_run_queue_poll_ms(struct kobject *kobj,
- struct kobj_attribute *attr, char *buf)
+ struct kobj_attribute *attr, char *buf)
{
int ret = 0;
unsigned long flags = 0;
spin_lock_irqsave(&rq_lock, flags);
- ret = sprintf(buf, "%u\n", rq_info.rq_poll_ms);
+ ret = snprintf(buf, MAX_LONG_SIZE, "%u\n",
+ jiffies_to_msecs(rq_info.rq_poll_jiffies));
spin_unlock_irqrestore(&rq_lock, flags);
return ret;
}
static ssize_t store_run_queue_poll_ms(struct kobject *kobj,
- struct kobj_attribute *attr, const char *buf, size_t count)
+ struct kobj_attribute *attr,
+ const char *buf, size_t count)
{
- int val = 0;
+ unsigned int val = 0;
unsigned long flags = 0;
static DEFINE_MUTEX(lock_poll_ms);
@@ -132,15 +84,9 @@
spin_lock_irqsave(&rq_lock, flags);
sscanf(buf, "%u", &val);
- rq_info.rq_poll_ms = val;
+ rq_info.rq_poll_jiffies = msecs_to_jiffies(val);
spin_unlock_irqrestore(&rq_lock, flags);
- if (val <= 0)
- cancel_delayed_work(&rq_info.rq_work);
- else
- queue_delayed_work(rq_wq, &rq_info.rq_work,
- msecs_to_jiffies(val));
-
mutex_unlock(&lock_poll_ms);
return count;
@@ -149,7 +95,8 @@
static ssize_t show_def_timer_ms(struct kobject *kobj,
struct kobj_attribute *attr, char *buf)
{
- return sprintf(buf, "%u\n", rq_info.def_interval);
+ return snprintf(buf, MAX_LONG_SIZE, "%lu\n",
+ rq_info.def_timer_jiffies);
}
static ssize_t store_def_timer_ms(struct kobject *kobj,
@@ -158,16 +105,9 @@
unsigned int val = 0;
sscanf(buf, "%u", &val);
- rq_info.def_timer_ms = val;
+ rq_info.def_timer_jiffies = msecs_to_jiffies(val);
- if (val <= 0)
- cancel_delayed_work(&rq_info.def_timer_work);
- else {
- rq_info.def_start_time = ktime_to_ns(ktime_get());
- queue_delayed_work(rq_wq, &rq_info.def_timer_work,
- msecs_to_jiffies(val));
- }
-
+ rq_info.def_start_time = ktime_to_ns(ktime_get());
return count;
}
@@ -210,7 +150,6 @@
goto rel;
rq_info.rq_avg = 0;
- rq_info.rq_poll_ms = 0;
attribs[0] = MSM_RQ_STATS_RW_ATTRIB(def_timer_ms);
attribs[1] = MSM_RQ_STATS_RO_ATTRIB(run_queue_avg);
@@ -257,8 +196,13 @@
{
rq_wq = create_singlethread_workqueue("rq_stats");
BUG_ON(!rq_wq);
- INIT_DELAYED_WORK_DEFERRABLE(&rq_info.rq_work, rq_work_fn);
- INIT_DELAYED_WORK_DEFERRABLE(&rq_info.def_timer_work, def_work_fn);
+ INIT_WORK(&rq_info.def_timer_work, def_work_fn);
+ spin_lock_init(&rq_lock);
+ rq_info.rq_poll_jiffies = DEFAULT_RQ_POLL_JIFFIES;
+ rq_info.def_timer_jiffies = DEFAULT_DEF_TIMER_JIFFIES;
+ rq_info.rq_poll_last_jiffy = 0;
+ rq_info.def_timer_last_jiffy = 0;
+ rq_info.init = 1;
return init_rq_attribs();
}
late_initcall(msm_rq_stats_init);
diff --git a/arch/arm/mach-msm/peripheral-loader.c b/arch/arm/mach-msm/peripheral-loader.c
index c8f0798..672f332 100644
--- a/arch/arm/mach-msm/peripheral-loader.c
+++ b/arch/arm/mach-msm/peripheral-loader.c
@@ -12,19 +12,29 @@
#include <linux/module.h>
#include <linux/string.h>
-#include <linux/platform_device.h>
+#include <linux/device.h>
#include <linux/firmware.h>
#include <linux/io.h>
#include <linux/debugfs.h>
#include <linux/elf.h>
#include <linux/mutex.h>
#include <linux/memblock.h>
+#include <linux/slab.h>
+
+#include <mach/socinfo.h>
#include <asm/uaccess.h>
#include <asm/setup.h>
#include "peripheral-loader.h"
+struct pil_device {
+ struct pil_desc *desc;
+ int count;
+ struct mutex lock;
+ struct list_head list;
+};
+
static DEFINE_MUTEX(pil_list_lock);
static LIST_HEAD(pil_list);
@@ -33,7 +43,7 @@
struct pil_device *dev;
list_for_each_entry(dev, &pil_list, list)
- if (!strcmp(dev->name, str))
+ if (!strcmp(dev->desc->name, str))
return dev;
return NULL;
}
@@ -63,24 +73,24 @@
const u8 *data;
if (memblock_is_region_memory(phdr->p_paddr, phdr->p_memsz)) {
- dev_err(&pil->pdev.dev, "Kernel memory would be overwritten");
+ dev_err(pil->desc->dev, "Kernel memory would be overwritten");
return -EPERM;
}
if (phdr->p_filesz) {
- snprintf(fw_name, ARRAY_SIZE(fw_name), "%s.b%02d", pil->name,
- num);
- ret = request_firmware(&fw, fw_name, &pil->pdev.dev);
+ snprintf(fw_name, ARRAY_SIZE(fw_name), "%s.b%02d",
+ pil->desc->name, num);
+ ret = request_firmware(&fw, fw_name, pil->desc->dev);
if (ret) {
- dev_err(&pil->pdev.dev, "Failed to locate blob %s\n",
+ dev_err(pil->desc->dev, "Failed to locate blob %s\n",
fw_name);
return ret;
}
if (fw->size != phdr->p_filesz) {
- dev_err(&pil->pdev.dev,
- "Blob size %u doesn't match %u\n",
- fw->size, phdr->p_filesz);
+ dev_err(pil->desc->dev,
+ "Blob size %u doesn't match %u\n", fw->size,
+ phdr->p_filesz);
ret = -EPERM;
goto release_fw;
}
@@ -97,7 +107,7 @@
size = min_t(size_t, IOMAP_SIZE, count);
buf = ioremap(paddr, size);
if (!buf) {
- dev_err(&pil->pdev.dev, "Failed to map memory\n");
+ dev_err(pil->desc->dev, "Failed to map memory\n");
ret = -ENOMEM;
goto release_fw;
}
@@ -118,7 +128,7 @@
size = min_t(size_t, IOMAP_SIZE, count);
buf = ioremap(paddr, size);
if (!buf) {
- dev_err(&pil->pdev.dev, "Failed to map memory\n");
+ dev_err(pil->desc->dev, "Failed to map memory\n");
ret = -ENOMEM;
goto release_fw;
}
@@ -129,9 +139,10 @@
paddr += size;
}
- ret = pil->ops->verify_blob(pil, phdr->p_paddr, phdr->p_memsz);
+ ret = pil->desc->ops->verify_blob(pil->desc, phdr->p_paddr,
+ phdr->p_memsz);
if (ret)
- dev_err(&pil->pdev.dev, "Blob %u failed verification\n", num);
+ dev_err(pil->desc->dev, "Blob %u failed verification\n", num);
release_fw:
release_firmware(fw);
@@ -153,41 +164,41 @@
const struct elf32_phdr *phdr;
const struct firmware *fw;
- snprintf(fw_name, sizeof(fw_name), "%s.mdt", pil->name);
- ret = request_firmware(&fw, fw_name, &pil->pdev.dev);
+ snprintf(fw_name, sizeof(fw_name), "%s.mdt", pil->desc->name);
+ ret = request_firmware(&fw, fw_name, pil->desc->dev);
if (ret) {
- dev_err(&pil->pdev.dev, "Failed to locate %s\n", fw_name);
+ dev_err(pil->desc->dev, "Failed to locate %s\n", fw_name);
goto out;
}
if (fw->size < sizeof(*ehdr)) {
- dev_err(&pil->pdev.dev, "Not big enough to be an elf header\n");
+ dev_err(pil->desc->dev, "Not big enough to be an elf header\n");
ret = -EIO;
goto release_fw;
}
ehdr = (struct elf32_hdr *)fw->data;
if (memcmp(ehdr->e_ident, ELFMAG, SELFMAG)) {
- dev_err(&pil->pdev.dev, "Not an elf header\n");
+ dev_err(pil->desc->dev, "Not an elf header\n");
ret = -EIO;
goto release_fw;
}
if (ehdr->e_phnum == 0) {
- dev_err(&pil->pdev.dev, "No loadable segments\n");
+ dev_err(pil->desc->dev, "No loadable segments\n");
ret = -EIO;
goto release_fw;
}
if (sizeof(struct elf32_phdr) * ehdr->e_phnum +
sizeof(struct elf32_hdr) > fw->size) {
- dev_err(&pil->pdev.dev, "Program headers not within mdt\n");
+ dev_err(pil->desc->dev, "Program headers not within mdt\n");
ret = -EIO;
goto release_fw;
}
- ret = pil->ops->init_image(pil, fw->data, fw->size);
+ ret = pil->desc->ops->init_image(pil->desc, fw->data, fw->size);
if (ret) {
- dev_err(&pil->pdev.dev, "Invalid firmware metadata\n");
+ dev_err(pil->desc->dev, "Invalid firmware metadata\n");
goto release_fw;
}
@@ -198,15 +209,15 @@
ret = load_segment(phdr, i, pil);
if (ret) {
- dev_err(&pil->pdev.dev, "Failed to load segment %d\n",
+ dev_err(pil->desc->dev, "Failed to load segment %d\n",
i);
goto release_fw;
}
}
- ret = pil->ops->auth_and_reset(pil);
+ ret = pil->desc->ops->auth_and_reset(pil->desc);
if (ret) {
- dev_err(&pil->pdev.dev, "Failed to bring out of reset\n");
+ dev_err(pil->desc->dev, "Failed to bring out of reset\n");
goto release_fw;
}
@@ -232,13 +243,17 @@
struct pil_device *pil_d;
void *retval;
+ /* PIL is not yet supported on 8064. */
+ if (cpu_is_apq8064())
+ return NULL;
+
pil = retval = find_peripheral(name);
if (!pil)
return ERR_PTR(-ENODEV);
- pil_d = find_peripheral(pil->depends_on);
+ pil_d = find_peripheral(pil->desc->depends_on);
if (pil_d) {
- void *p = pil_get(pil_d->name);
+ void *p = pil_get(pil_d->desc->name);
if (IS_ERR(p))
return p;
}
@@ -284,11 +299,11 @@
if (pil->count)
pil->count--;
if (pil->count == 0)
- pil->ops->shutdown(pil);
+ pil->desc->ops->shutdown(pil->desc);
unlock:
mutex_unlock(&pil->lock);
- pil_d = find_peripheral(pil->depends_on);
+ pil_d = find_peripheral(pil->desc->depends_on);
if (pil_d)
pil_put(pil_d);
}
@@ -304,7 +319,7 @@
mutex_lock(&pil->lock);
if (!WARN(!pil->count, "%s: Reference count mismatch\n", __func__))
- pil->ops->shutdown(pil);
+ pil->desc->ops->shutdown(pil->desc);
mutex_unlock(&pil->lock);
}
EXPORT_SYMBOL(pil_force_shutdown);
@@ -360,7 +375,7 @@
return -EFAULT;
if (!strncmp(buf, "get", 3)) {
- if (IS_ERR(pil_get(pil->name)))
+ if (IS_ERR(pil_get(pil->desc->name)))
return -EIO;
} else if (!strncmp(buf, "put", 3))
pil_put(pil);
@@ -395,8 +410,8 @@
if (!pil_base_dir)
return -ENOMEM;
- if (!debugfs_create_file(pil->name, S_IRUGO | S_IWUSR, pil_base_dir,
- pil, &msm_pil_debugfs_fops))
+ if (!debugfs_create_file(pil->desc->name, S_IRUGO | S_IWUSR,
+ pil_base_dir, pil, &msm_pil_debugfs_fops))
return -ENOMEM;
return 0;
}
@@ -410,29 +425,30 @@
mutex_lock(&pil_list_lock);
list_for_each_entry(pil, &pil_list, list)
- pil->ops->shutdown(pil);
+ pil->desc->ops->shutdown(pil->desc);
mutex_unlock(&pil_list_lock);
return 0;
}
late_initcall(msm_pil_shutdown_at_boot);
-int msm_pil_add_device(struct pil_device *pil)
+int msm_pil_register(struct pil_desc *desc)
{
- int ret;
- ret = platform_device_register(&pil->pdev);
- if (ret)
- return ret;
+ struct pil_device *pil = kzalloc(sizeof(*pil), GFP_KERNEL);
+ if (!pil)
+ return -ENOMEM;
mutex_init(&pil->lock);
+ INIT_LIST_HEAD(&pil->list);
+ pil->desc = desc;
mutex_lock(&pil_list_lock);
list_add(&pil->list, &pil_list);
mutex_unlock(&pil_list_lock);
- msm_pil_debugfs_add(pil);
- return 0;
+ return msm_pil_debugfs_add(pil);
}
+EXPORT_SYMBOL(msm_pil_register);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Load peripheral images and bring peripherals out of reset");
diff --git a/arch/arm/mach-msm/peripheral-loader.h b/arch/arm/mach-msm/peripheral-loader.h
index 097d9d7..3d4b4b2 100644
--- a/arch/arm/mach-msm/peripheral-loader.h
+++ b/arch/arm/mach-msm/peripheral-loader.h
@@ -12,28 +12,23 @@
#ifndef __MSM_PERIPHERAL_LOADER_H
#define __MSM_PERIPHERAL_LOADER_H
-#include <linux/list.h>
-#include <linux/mutex.h>
-#include <linux/platform_device.h>
+struct device;
-struct pil_device {
+struct pil_desc {
const char *name;
const char *depends_on;
- int count;
- struct mutex lock;
- struct platform_device pdev;
- struct list_head list;
- struct pil_reset_ops *ops;
+ struct device *dev;
+ const struct pil_reset_ops *ops;
};
struct pil_reset_ops {
- int (*init_image)(struct pil_device *pil, const u8 *metadata,
+ int (*init_image)(struct pil_desc *pil, const u8 *metadata,
size_t size);
- int (*verify_blob)(struct pil_device *pil, u32 phy_addr, size_t size);
- int (*auth_and_reset)(struct pil_device *pil);
- int (*shutdown)(struct pil_device *pil);
+ int (*verify_blob)(struct pil_desc *pil, u32 phy_addr, size_t size);
+ int (*auth_and_reset)(struct pil_desc *pil);
+ int (*shutdown)(struct pil_desc *pil);
};
-extern int msm_pil_add_device(struct pil_device *pil);
+extern int msm_pil_register(struct pil_desc *desc);
#endif
diff --git a/arch/arm/mach-msm/peripheral-reset-8960.c b/arch/arm/mach-msm/peripheral-reset-8960.c
index 2c47ee0..b964417 100644
--- a/arch/arm/mach-msm/peripheral-reset-8960.c
+++ b/arch/arm/mach-msm/peripheral-reset-8960.c
@@ -18,6 +18,7 @@
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/regulator/consumer.h>
+#include <linux/platform_device.h>
#include <asm/mach-types.h>
@@ -167,25 +168,25 @@
static void __iomem *msm_riva_base;
static unsigned long riva_start;
-static int init_image_lpass_q6_trusted(struct pil_device *pil,
+static int init_image_lpass_q6_trusted(struct pil_desc *pil,
const u8 *metadata, size_t size)
{
return pas_init_image(PAS_Q6, metadata, size);
}
-static int init_image_modem_fw_q6_trusted(struct pil_device *pil,
+static int init_image_modem_fw_q6_trusted(struct pil_desc *pil,
const u8 *metadata, size_t size)
{
return pas_init_image(PAS_MODEM_FW, metadata, size);
}
-static int init_image_modem_sw_q6_trusted(struct pil_device *pil,
+static int init_image_modem_sw_q6_trusted(struct pil_desc *pil,
const u8 *metadata, size_t size)
{
return pas_init_image(PAS_MODEM_SW, metadata, size);
}
-static int init_image_lpass_q6_untrusted(struct pil_device *pil,
+static int init_image_lpass_q6_untrusted(struct pil_desc *pil,
const u8 *metadata, size_t size)
{
const struct elf32_hdr *ehdr = (struct elf32_hdr *)metadata;
@@ -193,7 +194,7 @@
return 0;
}
-static int init_image_modem_fw_q6_untrusted(struct pil_device *pil,
+static int init_image_modem_fw_q6_untrusted(struct pil_desc *pil,
const u8 *metadata, size_t size)
{
const struct elf32_hdr *ehdr = (struct elf32_hdr *)metadata;
@@ -201,7 +202,7 @@
return 0;
}
-static int init_image_modem_sw_q6_untrusted(struct pil_device *pil,
+static int init_image_modem_sw_q6_untrusted(struct pil_desc *pil,
const u8 *metadata, size_t size)
{
const struct elf32_hdr *ehdr = (struct elf32_hdr *)metadata;
@@ -209,7 +210,7 @@
return 0;
}
-static int verify_blob(struct pil_device *pil, u32 phy_addr, size_t size)
+static int verify_blob(struct pil_desc *pil, u32 phy_addr, size_t size)
{
return 0;
}
@@ -245,17 +246,17 @@
return pas_auth_and_reset(id);
}
-static int reset_lpass_q6_trusted(struct pil_device *pil)
+static int reset_lpass_q6_trusted(struct pil_desc *pil)
{
return reset_q6_trusted(PAS_Q6, &q6_lpass);
}
-static int reset_modem_fw_q6_trusted(struct pil_device *pil)
+static int reset_modem_fw_q6_trusted(struct pil_desc *pil)
{
return reset_q6_trusted(PAS_MODEM_FW, &q6_modem_fw);
}
-static int reset_modem_sw_q6_trusted(struct pil_device *pil)
+static int reset_modem_sw_q6_trusted(struct pil_desc *pil)
{
return reset_q6_trusted(PAS_MODEM_SW, &q6_modem_sw);
}
@@ -364,17 +365,17 @@
return 0;
}
-static int reset_lpass_q6_untrusted(struct pil_device *pil)
+static int reset_lpass_q6_untrusted(struct pil_desc *pil)
{
return reset_q6_untrusted(&q6_lpass);
}
-static int reset_modem_fw_q6_untrusted(struct pil_device *pil)
+static int reset_modem_fw_q6_untrusted(struct pil_desc *pil)
{
return reset_q6_untrusted(&q6_modem_fw);
}
-static int reset_modem_sw_q6_untrusted(struct pil_device *pil)
+static int reset_modem_sw_q6_untrusted(struct pil_desc *pil)
{
return reset_q6_untrusted(&q6_modem_sw);
}
@@ -395,17 +396,17 @@
return ret;
}
-static int shutdown_lpass_q6_trusted(struct pil_device *pil)
+static int shutdown_lpass_q6_trusted(struct pil_desc *pil)
{
return shutdown_q6_trusted(PAS_Q6, &q6_lpass);
}
-static int shutdown_modem_fw_q6_trusted(struct pil_device *pil)
+static int shutdown_modem_fw_q6_trusted(struct pil_desc *pil)
{
return shutdown_q6_trusted(PAS_MODEM_FW, &q6_modem_fw);
}
-static int shutdown_modem_sw_q6_trusted(struct pil_device *pil)
+static int shutdown_modem_sw_q6_trusted(struct pil_desc *pil)
{
return shutdown_q6_trusted(PAS_MODEM_SW, &q6_modem_sw);
}
@@ -438,22 +439,22 @@
return 0;
}
-static int shutdown_lpass_q6_untrusted(struct pil_device *pil)
+static int shutdown_lpass_q6_untrusted(struct pil_desc *pil)
{
return shutdown_q6_untrusted(&q6_lpass);
}
-static int shutdown_modem_fw_q6_untrusted(struct pil_device *pil)
+static int shutdown_modem_fw_q6_untrusted(struct pil_desc *pil)
{
return shutdown_q6_untrusted(&q6_modem_fw);
}
-static int shutdown_modem_sw_q6_untrusted(struct pil_device *pil)
+static int shutdown_modem_sw_q6_untrusted(struct pil_desc *pil)
{
return shutdown_q6_untrusted(&q6_modem_sw);
}
-static int init_image_riva_untrusted(struct pil_device *pil, const u8 *metadata,
+static int init_image_riva_untrusted(struct pil_desc *pil, const u8 *metadata,
size_t size)
{
const struct elf32_hdr *ehdr = (struct elf32_hdr *)metadata;
@@ -461,7 +462,7 @@
return 0;
}
-static int reset_riva_untrusted(struct pil_device *pil)
+static int reset_riva_untrusted(struct pil_desc *pil)
{
u32 reg;
bool xo;
@@ -552,7 +553,7 @@
return 0;
}
-static int shutdown_riva_untrusted(struct pil_device *pil)
+static int shutdown_riva_untrusted(struct pil_desc *pil)
{
u32 reg;
/* Put riva into reset */
@@ -562,23 +563,23 @@
return 0;
}
-static int init_image_riva_trusted(struct pil_device *pil, const u8 *metadata,
+static int init_image_riva_trusted(struct pil_desc *pil, const u8 *metadata,
size_t size)
{
return pas_init_image(PAS_RIVA, metadata, size);
}
-static int reset_riva_trusted(struct pil_device *pil)
+static int reset_riva_trusted(struct pil_desc *pil)
{
return pas_auth_and_reset(PAS_RIVA);
}
-static int shutdown_riva_trusted(struct pil_device *pil)
+static int shutdown_riva_trusted(struct pil_desc *pil)
{
return pas_shutdown(PAS_RIVA);
}
-static int init_image_dsps_untrusted(struct pil_device *pil, const u8 *metadata,
+static int init_image_dsps_untrusted(struct pil_desc *pil, const u8 *metadata,
size_t size)
{
/* Bring memory and bus interface out of reset */
@@ -587,7 +588,7 @@
return 0;
}
-static int reset_dsps_untrusted(struct pil_device *pil)
+static int reset_dsps_untrusted(struct pil_desc *pil)
{
writel_relaxed(0x10, PPSS_PROC_CLK_CTL);
/* Bring DSPS out of reset */
@@ -595,41 +596,41 @@
return 0;
}
-static int shutdown_dsps_untrusted(struct pil_device *pil)
+static int shutdown_dsps_untrusted(struct pil_desc *pil)
{
writel_relaxed(0x2, PPSS_RESET);
writel_relaxed(0x0, PPSS_PROC_CLK_CTL);
return 0;
}
-static int init_image_dsps_trusted(struct pil_device *pil, const u8 *metadata,
+static int init_image_dsps_trusted(struct pil_desc *pil, const u8 *metadata,
size_t size)
{
return pas_init_image(PAS_DSPS, metadata, size);
}
-static int reset_dsps_trusted(struct pil_device *pil)
+static int reset_dsps_trusted(struct pil_desc *pil)
{
return pas_auth_and_reset(PAS_DSPS);
}
-static int shutdown_dsps_trusted(struct pil_device *pil)
+static int shutdown_dsps_trusted(struct pil_desc *pil)
{
return pas_shutdown(PAS_DSPS);
}
-static int init_image_tzapps(struct pil_device *pil, const u8 *metadata,
+static int init_image_tzapps(struct pil_desc *pil, const u8 *metadata,
size_t size)
{
return pas_init_image(PAS_TZAPPS, metadata, size);
}
-static int reset_tzapps(struct pil_device *pil)
+static int reset_tzapps(struct pil_desc *pil)
{
return pas_auth_and_reset(PAS_TZAPPS);
}
-static int shutdown_tzapps(struct pil_device *pil)
+static int shutdown_tzapps(struct pil_desc *pil)
{
return pas_shutdown(PAS_TZAPPS);
}
@@ -676,59 +677,65 @@
.shutdown = shutdown_tzapps,
};
-static struct pil_device pil_lpass_q6 = {
+static struct platform_device pil_lpass_q6 = {
+ .name = "pil_lpass_q6",
+};
+
+static struct pil_desc pil_lpass_q6_desc = {
.name = "q6",
- .pdev = {
- .name = "pil_lpass_q6",
- .id = -1,
- },
+ .dev = &pil_lpass_q6.dev,
.ops = &pil_lpass_q6_ops,
};
-static struct pil_device pil_modem_fw_q6 = {
+static struct platform_device pil_modem_fw_q6 = {
+ .name = "pil_modem_fw_q6",
+};
+
+static struct pil_desc pil_modem_fw_q6_desc = {
.name = "modem_fw",
.depends_on = "q6",
- .pdev = {
- .name = "pil_modem_fw_q6",
- .id = -1,
- },
+ .dev = &pil_modem_fw_q6.dev,
.ops = &pil_modem_fw_q6_ops,
};
-static struct pil_device pil_modem_sw_q6 = {
+static struct platform_device pil_modem_sw_q6 = {
+ .name = "pil_modem_sw_q6",
+};
+
+static struct pil_desc pil_modem_sw_q6_desc = {
.name = "modem",
.depends_on = "modem_fw",
- .pdev = {
- .name = "pil_modem_sw_q6",
- .id = -1,
- },
+ .dev = &pil_modem_sw_q6.dev,
.ops = &pil_modem_sw_q6_ops,
};
-static struct pil_device pil_riva = {
+static struct platform_device pil_riva = {
+ .name = "pil_riva",
+};
+
+static struct pil_desc pil_riva_desc = {
.name = "wcnss",
- .pdev = {
- .name = "pil_riva",
- .id = -1,
- },
+ .dev = &pil_riva.dev,
.ops = &pil_riva_ops,
};
-static struct pil_device pil_dsps = {
+static struct platform_device pil_dsps = {
+ .name = "pil_dsps",
+};
+
+static struct pil_desc pil_dsps_desc = {
.name = "dsps",
- .pdev = {
- .name = "pil_dsps",
- .id = -1,
- },
+ .dev = &pil_dsps.dev,
.ops = &pil_dsps_ops,
};
-static struct pil_device pil_tzapps = {
+static struct platform_device pil_tzapps = {
+ .name = "pil_tzapps",
+};
+
+static struct pil_desc pil_tzapps_desc = {
.name = "tzapps",
- .pdev = {
- .name = "pil_tzapps",
- .id = -1,
- },
+ .dev = &pil_tzapps.dev,
.ops = &pil_tzapps_ops,
};
@@ -807,7 +814,8 @@
err = q6_reset_init(&q6_lpass);
if (err)
return err;
- msm_pil_add_device(&pil_lpass_q6);
+ BUG_ON(platform_device_register(&pil_lpass_q6));
+ BUG_ON(msm_pil_register(&pil_lpass_q6_desc));
mss_enable_reg = ioremap(MSM_MSS_ENABLE_PHYS, 4);
if (!mss_enable_reg)
@@ -818,20 +826,29 @@
iounmap(mss_enable_reg);
return err;
}
- msm_pil_add_device(&pil_modem_fw_q6);
+ BUG_ON(platform_device_register(&pil_modem_fw_q6));
+ if (err) {
+ iounmap(mss_enable_reg);
+ return err;
+ }
+ BUG_ON(msm_pil_register(&pil_modem_fw_q6_desc));
err = q6_reset_init(&q6_modem_sw);
if (err)
return err;
- msm_pil_add_device(&pil_modem_sw_q6);
+ BUG_ON(platform_device_register(&pil_modem_sw_q6));
+ BUG_ON(msm_pil_register(&pil_modem_sw_q6_desc));
- msm_pil_add_device(&pil_dsps);
- msm_pil_add_device(&pil_tzapps);
+ BUG_ON(platform_device_register(&pil_dsps));
+ BUG_ON(msm_pil_register(&pil_dsps_desc));
+ BUG_ON(platform_device_register(&pil_tzapps));
+ BUG_ON(msm_pil_register(&pil_tzapps_desc));
msm_riva_base = ioremap(MSM_RIVA_PHYS, SZ_256);
if (!msm_riva_base)
return -ENOMEM;
- msm_pil_add_device(&pil_riva);
+ BUG_ON(platform_device_register(&pil_riva));
+ BUG_ON(msm_pil_register(&pil_riva_desc));
return 0;
}
diff --git a/arch/arm/mach-msm/peripheral-reset.c b/arch/arm/mach-msm/peripheral-reset.c
index 5456e14..f3f5388 100644
--- a/arch/arm/mach-msm/peripheral-reset.c
+++ b/arch/arm/mach-msm/peripheral-reset.c
@@ -20,6 +20,9 @@
#include <linux/clk.h>
#include <linux/timer.h>
#include <linux/jiffies.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach-types.h>
#include <mach/scm.h>
#include <mach/msm_iomap.h>
@@ -68,13 +71,13 @@
static void __iomem *msm_mms_regs_base;
static void __iomem *msm_lpass_qdsp6ss_base;
-static int init_image_modem_trusted(struct pil_device *pil, const u8 *metadata,
+static int init_image_modem_trusted(struct pil_desc *pil, const u8 *metadata,
size_t size)
{
return pas_init_image(PAS_MODEM, metadata, size);
}
-static int init_image_modem_untrusted(struct pil_device *pil,
+static int init_image_modem_untrusted(struct pil_desc *pil,
const u8 *metadata, size_t size)
{
struct elf32_hdr *ehdr = (struct elf32_hdr *)metadata;
@@ -82,13 +85,13 @@
return 0;
}
-static int init_image_q6_trusted(struct pil_device *pil,
+static int init_image_q6_trusted(struct pil_desc *pil,
const u8 *metadata, size_t size)
{
return pas_init_image(PAS_Q6, metadata, size);
}
-static int init_image_q6_untrusted(struct pil_device *pil, const u8 *metadata,
+static int init_image_q6_untrusted(struct pil_desc *pil, const u8 *metadata,
size_t size)
{
struct elf32_hdr *ehdr = (struct elf32_hdr *)metadata;
@@ -96,13 +99,13 @@
return 0;
}
-static int init_image_dsps_trusted(struct pil_device *pil, const u8 *metadata,
+static int init_image_dsps_trusted(struct pil_desc *pil, const u8 *metadata,
size_t size)
{
return pas_init_image(PAS_DSPS, metadata, size);
}
-static int init_image_dsps_untrusted(struct pil_device *pil, const u8 *metadata,
+static int init_image_dsps_untrusted(struct pil_desc *pil, const u8 *metadata,
size_t size)
{
struct elf32_hdr *ehdr = (struct elf32_hdr *)metadata;
@@ -113,7 +116,7 @@
return 0;
}
-static int verify_blob(struct pil_device *pil, u32 phy_addr, size_t size)
+static int verify_blob(struct pil_desc *pil, u32 phy_addr, size_t size)
{
return 0;
}
@@ -142,7 +145,7 @@
remove_modem_proxy_votes(0);
}
-static int reset_modem_untrusted(struct pil_device *pil)
+static int reset_modem_untrusted(struct pil_desc *pil)
{
u32 reg;
@@ -221,7 +224,7 @@
return 0;
}
-static int reset_modem_trusted(struct pil_device *pil)
+static int reset_modem_trusted(struct pil_desc *pil)
{
int ret;
@@ -234,7 +237,7 @@
return ret;
}
-static int shutdown_modem_untrusted(struct pil_device *pil)
+static int shutdown_modem_untrusted(struct pil_desc *pil)
{
u32 reg;
@@ -275,7 +278,7 @@
return 0;
}
-static int shutdown_modem_trusted(struct pil_device *pil)
+static int shutdown_modem_trusted(struct pil_desc *pil)
{
int ret;
@@ -343,7 +346,7 @@
remove_q6_proxy_votes(0);
}
-static int reset_q6_untrusted(struct pil_device *pil)
+static int reset_q6_untrusted(struct pil_desc *pil)
{
u32 reg;
@@ -389,14 +392,14 @@
return 0;
}
-static int reset_q6_trusted(struct pil_device *pil)
+static int reset_q6_trusted(struct pil_desc *pil)
{
make_q6_proxy_votes();
return pas_auth_and_reset(PAS_Q6);
}
-static int shutdown_q6_untrusted(struct pil_device *pil)
+static int shutdown_q6_untrusted(struct pil_desc *pil)
{
u32 reg;
@@ -423,7 +426,7 @@
return 0;
}
-static int shutdown_q6_trusted(struct pil_device *pil)
+static int shutdown_q6_trusted(struct pil_desc *pil)
{
int ret;
@@ -436,7 +439,7 @@
return 0;
}
-static int reset_dsps_untrusted(struct pil_device *pil)
+static int reset_dsps_untrusted(struct pil_desc *pil)
{
__raw_writel(0x10, PPSS_PROC_CLK_CTL);
while (__raw_readl(CLK_HALT_DFAB_STATE) & BIT(18))
@@ -447,35 +450,35 @@
return 0;
}
-static int reset_dsps_trusted(struct pil_device *pil)
+static int reset_dsps_trusted(struct pil_desc *pil)
{
return pas_auth_and_reset(PAS_DSPS);
}
-static int shutdown_dsps_trusted(struct pil_device *pil)
+static int shutdown_dsps_trusted(struct pil_desc *pil)
{
return pas_shutdown(PAS_DSPS);
}
-static int shutdown_dsps_untrusted(struct pil_device *pil)
+static int shutdown_dsps_untrusted(struct pil_desc *pil)
{
__raw_writel(0x2, PPSS_RESET);
__raw_writel(0x0, PPSS_PROC_CLK_CTL);
return 0;
}
-static int init_image_playready(struct pil_device *pil, const u8 *metadata,
+static int init_image_playready(struct pil_desc *pil, const u8 *metadata,
size_t size)
{
return pas_init_image(PAS_PLAYREADY, metadata, size);
}
-static int reset_playready(struct pil_device *pil)
+static int reset_playready(struct pil_desc *pil)
{
return pas_auth_and_reset(PAS_PLAYREADY);
}
-static int shutdown_playready(struct pil_device *pil)
+static int shutdown_playready(struct pil_desc *pil)
{
return pas_shutdown(PAS_PLAYREADY);
}
@@ -508,47 +511,49 @@
.shutdown = shutdown_playready,
};
-static struct pil_device peripherals[] = {
- {
- .name = "modem",
- .depends_on = "q6",
- .pdev = {
- .name = "pil_modem",
- .id = -1,
- },
- .ops = &pil_modem_ops,
- },
- {
- .name = "q6",
- .pdev = {
- .name = "pil_q6",
- .id = -1,
- },
- .ops = &pil_q6_ops,
- },
- {
- .name = "tzapps",
- .pdev = {
- .name = "pil_playready",
- .id = -1,
- },
- .ops = &pil_playready_ops,
- },
+static struct platform_device pil_modem = {
+ .name = "pil_modem",
};
-struct pil_device peripheral_dsps = {
+static struct pil_desc pil_modem_desc = {
+ .name = "modem",
+ .depends_on = "q6",
+ .dev = &pil_modem.dev,
+ .ops = &pil_modem_ops,
+};
+
+static struct platform_device pil_q6 = {
+ .name = "pil_q6",
+};
+
+static struct pil_desc pil_q6_desc = {
+ .name = "q6",
+ .dev = &pil_q6.dev,
+ .ops = &pil_q6_ops,
+};
+
+static struct platform_device pil_playready = {
+ .name = "pil_playready",
+};
+
+static struct pil_desc pil_playready_desc = {
+ .name = "tzapps",
+ .dev = &pil_playready.dev,
+ .ops = &pil_playready_ops,
+};
+
+static struct platform_device pil_dsps = {
+ .name = "pil_dsps",
+};
+
+static struct pil_desc pil_dsps_desc = {
.name = "dsps",
- .pdev = {
- .name = "pil_dsps",
- .id = -1,
- },
+ .dev = &pil_dsps.dev,
.ops = &pil_dsps_ops,
};
static int __init msm_peripheral_reset_init(void)
{
- unsigned i;
-
msm_mms_regs_base = ioremap(MSM_MMS_REGS_BASE, SZ_256);
if (!msm_mms_regs_base)
goto err;
@@ -583,8 +588,17 @@
pil_dsps_ops.shutdown = shutdown_dsps_trusted;
}
- for (i = 0; i < ARRAY_SIZE(peripherals); i++)
- msm_pil_add_device(&peripherals[i]);
+ BUG_ON(platform_device_register(&pil_q6));
+ BUG_ON(msm_pil_register(&pil_q6_desc));
+ BUG_ON(platform_device_register(&pil_modem));
+ BUG_ON(msm_pil_register(&pil_modem_desc));
+ BUG_ON(platform_device_register(&pil_playready));
+ BUG_ON(msm_pil_register(&pil_playready_desc));
+
+ if (machine_is_msm8x60_fluid())
+ pil_dsps_desc.name = "dsps_fluid";
+ BUG_ON(platform_device_register(&pil_dsps));
+ BUG_ON(msm_pil_register(&pil_dsps_desc));
return 0;
diff --git a/arch/arm/mach-msm/pm-8x60.c b/arch/arm/mach-msm/pm-8x60.c
index a929659..c831d4b 100644
--- a/arch/arm/mach-msm/pm-8x60.c
+++ b/arch/arm/mach-msm/pm-8x60.c
@@ -279,6 +279,12 @@
ret = 0;
mode_sysfs_add_cpu_exit:
+ if (!ret) {
+ if (mode && mode->kobj)
+ kobject_del(mode->kobj);
+ kfree(mode);
+ }
+
return ret;
}
diff --git a/arch/arm/mach-msm/qdsp5v2/audio_a2dp_in.c b/arch/arm/mach-msm/qdsp5v2/audio_a2dp_in.c
index 519d785..6166de2 100644
--- a/arch/arm/mach-msm/qdsp5v2/audio_a2dp_in.c
+++ b/arch/arm/mach-msm/qdsp5v2/audio_a2dp_in.c
@@ -42,6 +42,7 @@
#include <mach/msm_adsp.h>
#include <mach/msm_memtypes.h>
#include <mach/msm_subsystem_map.h>
+#include <mach/socinfo.h>
#include <mach/qdsp5v2/qdsp5audreccmdi.h>
#include <mach/qdsp5v2/qdsp5audrecmsg.h>
#include <mach/qdsp5v2/audpreproc.h>
@@ -114,6 +115,7 @@
int running;
int stopped; /* set when stopped, cleared on flush */
int abort; /* set when error, like sample rate mismatch */
+ char *build_id;
};
static struct audio_a2dp_in the_audio_a2dp_in;
@@ -368,7 +370,13 @@
struct audpreproc_audrec_cmd_enc_cfg cmd;
memset(&cmd, 0, sizeof(cmd));
- cmd.cmd_id = AUDPREPROC_AUDREC_CMD_ENC_CFG_2;
+ if (audio->build_id[17] == '1') {
+ cmd.cmd_id = AUDPREPROC_AUDREC_CMD_ENC_CFG_2;
+ MM_ERR("sending AUDPREPROC_AUDREC_CMD_ENC_CFG_2 command");
+ } else {
+ cmd.cmd_id = AUDPREPROC_AUDREC_CMD_ENC_CFG;
+ MM_ERR("sending AUDPREPROC_AUDREC_CMD_ENC_CFG command");
+ }
cmd.stream_id = audio->enc_id;
if (enable)
@@ -941,6 +949,8 @@
MM_ERR("failed to register device event listener\n");
goto evt_error;
}
+ audio->build_id = socinfo_get_build_id();
+ MM_ERR("build id used is = %s\n", audio->build_id);
file->private_data = audio;
audio->opened = 1;
rc = 0;
diff --git a/arch/arm/mach-msm/qdsp5v2/audio_aac_in.c b/arch/arm/mach-msm/qdsp5v2/audio_aac_in.c
index f378297..da77140 100644
--- a/arch/arm/mach-msm/qdsp5v2/audio_aac_in.c
+++ b/arch/arm/mach-msm/qdsp5v2/audio_aac_in.c
@@ -39,6 +39,7 @@
#include <mach/qdsp5v2/audpreproc.h>
#include <mach/qdsp5v2/audio_dev_ctl.h>
#include <mach/debug_mm.h>
+#include <mach/socinfo.h>
/* FRAME_NUM must be a power of two */
#define FRAME_NUM (8)
@@ -141,6 +142,7 @@
int running;
int stopped; /* set when stopped, cleared on flush */
int abort; /* set when error, like sample rate mismatch */
+ char *build_id;
};
struct audio_frame {
@@ -573,7 +575,14 @@
{
struct audpreproc_audrec_cmd_enc_cfg cmd;
memset(&cmd, 0, sizeof(cmd));
- cmd.cmd_id = AUDPREPROC_AUDREC_CMD_ENC_CFG_2;
+ MM_ERR("build_id[17] = %c", audio->build_id[17]);
+ if (audio->build_id[17] == '1') {
+ cmd.cmd_id = AUDPREPROC_AUDREC_CMD_ENC_CFG_2;
+ MM_ERR("sending AUDPREPROC_AUDREC_CMD_ENC_CFG_2 command");
+ } else {
+ cmd.cmd_id = AUDPREPROC_AUDREC_CMD_ENC_CFG;
+ MM_ERR("sending AUDPREPROC_AUDREC_CMD_ENC_CFG command");
+ }
cmd.stream_id = audio->enc_id;
if (enable)
@@ -1403,6 +1412,9 @@
MM_DBG("write buf: phy addr 0x%08x kernel addr 0x%08x\n",
audio->out_phys, (int)audio->out_data);
}
+ MM_ERR("trying to get the build id\n");
+ audio->build_id = socinfo_get_build_id();
+ MM_ERR("build id used is = %s\n", audio->build_id);
/* Initialize buffer */
audio->out[0].data = audio->out_data + 0;
diff --git a/arch/arm/mach-msm/qdsp5v2/audio_acdb.c b/arch/arm/mach-msm/qdsp5v2/audio_acdb.c
index 36ace7f..ec275b4 100644
--- a/arch/arm/mach-msm/qdsp5v2/audio_acdb.c
+++ b/arch/arm/mach-msm/qdsp5v2/audio_acdb.c
@@ -31,6 +31,7 @@
#include <mach/msm_subsystem_map.h>
#include <mach/qdsp5v2/audio_dev_ctl.h>
#include <mach/qdsp5v2/audpp.h>
+#include <mach/socinfo.h>
#include <mach/qdsp5v2/audpreproc.h>
#include <mach/qdsp5v2/qdsp5audppcmdi.h>
#include <mach/qdsp5v2/qdsp5audpreproccmdi.h>
@@ -130,6 +131,7 @@
unsigned long get_blk_paddr;
u8 *get_blk_kvaddr;
struct msm_mapped_buffer *map_v_get_blk;
+ char *build_id;
};
static struct acdb_data acdb_data;
@@ -1109,23 +1111,26 @@
rtc_acdb.set_iid = 0;
rtc_acdb.valid_abid = false;
rtc_acdb.tx_rx_ctl = 0;
- snprintf(name, sizeof name, "get_set_abid");
- get_set_abid_dentry = debugfs_create_file(name,
+ if (acdb_data.build_id[17] == '1') {
+ snprintf(name, sizeof name, "get_set_abid");
+ get_set_abid_dentry = debugfs_create_file(name,
S_IFREG | S_IRUGO | S_IWUGO,
NULL, NULL, &rtc_acdb_debug_fops);
- if (IS_ERR(get_set_abid_dentry)) {
- MM_ERR("SET GET ABID debugfs_create_file failed\n");
- return false;
- }
+ if (IS_ERR(get_set_abid_dentry)) {
+ MM_ERR("SET GET ABID debugfs_create_file failed\n");
+ return false;
+ }
- snprintf(name1, sizeof name1, "get_set_abid_data");
- get_set_abid_data_dentry = debugfs_create_file(name1,
- S_IFREG | S_IRUGO | S_IWUGO,
- NULL, NULL,
- &rtc_acdb_data_debug_fops);
- if (IS_ERR(get_set_abid_data_dentry)) {
- MM_ERR("SET GET ABID DATA debugfs_create_file failed\n");
- return false;
+ snprintf(name1, sizeof name1, "get_set_abid_data");
+ get_set_abid_data_dentry = debugfs_create_file(name1,
+ S_IFREG | S_IRUGO | S_IWUGO,
+ NULL, NULL,
+ &rtc_acdb_data_debug_fops);
+ if (IS_ERR(get_set_abid_data_dentry)) {
+ MM_ERR("SET GET ABID DATA"
+ " debugfs_create_file failed\n");
+ return false;
+ }
}
rtc_read->phys = allocate_contiguous_ebi_nomap(PMEM_RTC_ACDB_QUERY_MEM,
@@ -2332,18 +2337,20 @@
MM_DBG("AUDPREPROC is calibrated"
" with calib_gain_tx\n");
}
- acdb_rmc = get_rmc_blk();
- if (acdb_rmc != NULL) {
- result = afe_config_rmc_block(acdb_rmc);
- if (result) {
- MM_ERR("ACDB=> Failed to send rmc"
- " data to afe\n");
- result = -EINVAL;
- goto done;
+ if (acdb_data.build_id[17] != '0') {
+ acdb_rmc = get_rmc_blk();
+ if (acdb_rmc != NULL) {
+ result = afe_config_rmc_block(acdb_rmc);
+ if (result) {
+ MM_ERR("ACDB=> Failed to send rmc"
+ " data to afe\n");
+ result = -EINVAL;
+ goto done;
+ } else
+ MM_DBG("AFE is calibrated with rmc params\n");
} else
- MM_DBG("AFE is calibrated with rmc params\n");
- } else
- MM_DBG("RMC block was not found\n");
+ MM_DBG("RMC block was not found\n");
+ }
if (!acdb_data.fleuce_feature_status[acdb_data.preproc_stream_id]) {
result = acdb_fill_audpreproc_fluence();
if (!(IS_ERR_VALUE(result))) {
@@ -3050,9 +3057,11 @@
MM_INFO("audpreproc is routed to pseudo device\n");
return result;
}
- if (session_info[stream_id].sampling_freq)
- acdb_data.device_info->sample_rate =
+ if (acdb_data.build_id[17] == '1') {
+ if (session_info[stream_id].sampling_freq)
+ acdb_data.device_info->sample_rate =
session_info[stream_id].sampling_freq;
+ }
if (!(acdb_data.acdb_state & CAL_DATA_READY)) {
result = check_tx_acdb_values_cached();
if (result) {
@@ -3110,17 +3119,19 @@
callback at this scenario we should not access
device information
*/
- if (acdb_data.device_info &&
- session_info[stream_id].sampling_freq) {
- acdb_data.device_info->sample_rate =
+ if (acdb_data.build_id[17] != '0') {
+ if (acdb_data.device_info &&
+ session_info[stream_id].sampling_freq) {
+ acdb_data.device_info->sample_rate =
session_info[stream_id].sampling_freq;
- result = check_tx_acdb_values_cached();
- if (!result) {
- MM_INFO("acdb values for the stream is" \
- " querried from modem");
- acdb_data.acdb_state |= CAL_DATA_READY;
- } else {
- acdb_data.acdb_state &= ~CAL_DATA_READY;
+ result = check_tx_acdb_values_cached();
+ if (!result) {
+ MM_INFO("acdb values for the stream is" \
+ " querried from modem");
+ acdb_data.acdb_state |= CAL_DATA_READY;
+ } else {
+ acdb_data.acdb_state &= ~CAL_DATA_READY;
+ }
}
}
if (acdb_data.preproc_stream_id == 0)
@@ -3195,6 +3206,7 @@
if (result)
goto err4;
+
return result;
err4:
@@ -3276,10 +3288,12 @@
result = acdb_initialize_data();
if (result)
goto done;
-
- result = initialize_modem_acdb();
- if (result < 0)
- MM_ERR("failed to initialize modem ACDB\n");
+ MM_ERR("acdb_data.build_id[17] = %c\n", acdb_data.build_id[17]);
+ if (acdb_data.build_id[17] != '0') {
+ result = initialize_modem_acdb();
+ if (result < 0)
+ MM_ERR("failed to initialize modem ACDB\n");
+ }
while (!kthread_should_stop()) {
MM_DBG("Waiting for call back events\n");
@@ -3375,6 +3389,10 @@
result = -ENODEV;
goto err;
}
+
+ acdb_data.build_id = socinfo_get_build_id();
+ MM_INFO("build id used is = %s\n", acdb_data.build_id);
+
#ifdef CONFIG_DEBUG_FS
/*This is RTC specific INIT used only with debugfs*/
if (!rtc_acdb_init())
diff --git a/arch/arm/mach-msm/qdsp5v2/audio_amrnb_in.c b/arch/arm/mach-msm/qdsp5v2/audio_amrnb_in.c
index db56a0b..e1af44f 100644
--- a/arch/arm/mach-msm/qdsp5v2/audio_amrnb_in.c
+++ b/arch/arm/mach-msm/qdsp5v2/audio_amrnb_in.c
@@ -34,6 +34,7 @@
#include <mach/iommu_domains.h>
#include <mach/msm_subsystem_map.h>
#include <mach/msm_adsp.h>
+#include <mach/socinfo.h>
#include <mach/qdsp5v2/qdsp5audreccmdi.h>
#include <mach/qdsp5v2/qdsp5audrecmsg.h>
#include <mach/qdsp5v2/audpreproc.h>
@@ -104,6 +105,7 @@
int enabled;
int running;
int stopped; /* set when stopped, cleared on flush */
+ char *build_id;
};
struct audio_frame {
@@ -337,7 +339,13 @@
struct audpreproc_audrec_cmd_enc_cfg cmd;
memset(&cmd, 0, sizeof(cmd));
- cmd.cmd_id = AUDPREPROC_AUDREC_CMD_ENC_CFG_2;
+ if (audio->build_id[17] == '1') {
+ cmd.cmd_id = AUDPREPROC_AUDREC_CMD_ENC_CFG_2;
+ MM_ERR("sending AUDPREPROC_AUDREC_CMD_ENC_CFG_2 command");
+ } else {
+ cmd.cmd_id = AUDPREPROC_AUDREC_CMD_ENC_CFG;
+ MM_ERR("sending AUDPREPROC_AUDREC_CMD_ENC_CFG command");
+ }
cmd.stream_id = audio->enc_id;
if (enable)
@@ -854,6 +862,9 @@
MM_ERR("failed to register device event listener\n");
goto evt_error;
}
+ audio->build_id = socinfo_get_build_id();
+ MM_ERR("build id used is = %s\n", audio->build_id);
+
file->private_data = audio;
audio->opened = 1;
done:
diff --git a/arch/arm/mach-msm/qdsp5v2/audio_evrc_in.c b/arch/arm/mach-msm/qdsp5v2/audio_evrc_in.c
index ec31b65..c086153 100644
--- a/arch/arm/mach-msm/qdsp5v2/audio_evrc_in.c
+++ b/arch/arm/mach-msm/qdsp5v2/audio_evrc_in.c
@@ -34,6 +34,7 @@
#include <mach/iommu.h>
#include <mach/iommu_domains.h>
#include <mach/msm_subsystem_map.h>
+#include <mach/socinfo.h>
#include <mach/qdsp5v2/qdsp5audreccmdi.h>
#include <mach/qdsp5v2/qdsp5audrecmsg.h>
#include <mach/qdsp5v2/audpreproc.h>
@@ -136,6 +137,7 @@
int enabled;
int running;
int stopped; /* set when stopped, cleared on flush */
+ char *build_id;
};
struct audio_frame {
@@ -558,7 +560,13 @@
struct audpreproc_audrec_cmd_enc_cfg cmd;
memset(&cmd, 0, sizeof(cmd));
- cmd.cmd_id = AUDPREPROC_AUDREC_CMD_ENC_CFG_2;
+ if (audio->build_id[17] == '1') {
+ cmd.cmd_id = AUDPREPROC_AUDREC_CMD_ENC_CFG_2;
+ MM_ERR("sending AUDPREPROC_AUDREC_CMD_ENC_CFG_2 command");
+ } else {
+ cmd.cmd_id = AUDPREPROC_AUDREC_CMD_ENC_CFG;
+ MM_ERR("sending AUDPREPROC_AUDREC_CMD_ENC_CFG command");
+ }
cmd.stream_id = audio->enc_id;
if (enable)
@@ -1461,6 +1469,9 @@
file->private_data = audio;
audio->opened = 1;
audio->out_frame_cnt++;
+ audio->build_id = socinfo_get_build_id();
+ MM_ERR("build id used is = %s\n", audio->build_id);
+
done:
mutex_unlock(&audio->lock);
return rc;
diff --git a/arch/arm/mach-msm/qdsp5v2/audio_lpa.c b/arch/arm/mach-msm/qdsp5v2/audio_lpa.c
index 9baf521..c38fefc 100644
--- a/arch/arm/mach-msm/qdsp5v2/audio_lpa.c
+++ b/arch/arm/mach-msm/qdsp5v2/audio_lpa.c
@@ -603,16 +603,14 @@
temp = audio->bytecount_head;
used_buf = list_first_entry(&audio->out_queue,
struct audlpa_buffer_node, list);
- if ((audio->bytecount_head + used_buf->buf.data_len) <
- audio->bytecount_consumed) {
- audio->bytecount_head += used_buf->buf.data_len;
- temp = audio->bytecount_head;
- list_del(&used_buf->list);
- evt_payload.aio_buf = used_buf->buf;
- audlpa_post_event(audio, AUDIO_EVENT_WRITE_DONE,
- evt_payload);
- kfree(used_buf);
- }
+
+ audio->bytecount_head += used_buf->buf.data_len;
+ temp = audio->bytecount_head;
+ list_del(&used_buf->list);
+ evt_payload.aio_buf = used_buf->buf;
+ audlpa_post_event(audio, AUDIO_EVENT_WRITE_DONE,
+ evt_payload);
+ kfree(used_buf);
audio->drv_status &= ~ADRV_STATUS_OBUF_GIVEN;
}
}
diff --git a/arch/arm/mach-msm/qdsp5v2/audio_pcm_in.c b/arch/arm/mach-msm/qdsp5v2/audio_pcm_in.c
index 6422dca..43f3d26 100644
--- a/arch/arm/mach-msm/qdsp5v2/audio_pcm_in.c
+++ b/arch/arm/mach-msm/qdsp5v2/audio_pcm_in.c
@@ -36,6 +36,7 @@
#include <mach/msm_subsystem_map.h>
#include <mach/msm_adsp.h>
+#include <mach/socinfo.h>
#include <mach/qdsp5v2/qdsp5audreccmdi.h>
#include <mach/qdsp5v2/qdsp5audrecmsg.h>
#include <mach/qdsp5v2/audpreproc.h>
@@ -120,6 +121,7 @@
int stopped; /* set when stopped, cleared on flush */
int abort; /* set when error, like sample rate mismatch */
int dual_mic_config;
+ char *build_id;
};
static struct audio_in the_audio_in;
@@ -370,7 +372,13 @@
struct audpreproc_audrec_cmd_enc_cfg cmd;
memset(&cmd, 0, sizeof(cmd));
- cmd.cmd_id = AUDPREPROC_AUDREC_CMD_ENC_CFG_2;
+ if (audio->build_id[17] == '1') {
+ cmd.cmd_id = AUDPREPROC_AUDREC_CMD_ENC_CFG_2;
+ MM_ERR("sending AUDPREPROC_AUDREC_CMD_ENC_CFG_2 command");
+ } else {
+ cmd.cmd_id = AUDPREPROC_AUDREC_CMD_ENC_CFG;
+ MM_ERR("sending AUDPREPROC_AUDREC_CMD_ENC_CFG command");
+ }
cmd.stream_id = audio->enc_id;
if (enable)
@@ -630,30 +638,52 @@
rc = -EFAULT;
break;
}
- if (cfg.channel_count == 1) {
- cfg.channel_count = AUDREC_CMD_MODE_MONO;
- if ((cfg.buffer_size == MONO_DATA_SIZE_256) ||
- (cfg.buffer_size == MONO_DATA_SIZE_512) ||
- (cfg.buffer_size == MONO_DATA_SIZE_1024)) {
- audio->buffer_size = cfg.buffer_size;
+ MM_ERR("build_id[17] = %c\n", audio->build_id[17]);
+ if (audio->build_id[17] == '1') {
+ audio->enc_type = ENC_TYPE_EXT_WAV | audio->mode;
+ if (cfg.channel_count == 1) {
+ cfg.channel_count = AUDREC_CMD_MODE_MONO;
+ if ((cfg.buffer_size == MONO_DATA_SIZE_256) ||
+ (cfg.buffer_size ==
+ MONO_DATA_SIZE_512) ||
+ (cfg.buffer_size ==
+ MONO_DATA_SIZE_1024)) {
+ audio->buffer_size = cfg.buffer_size;
+ } else {
+ rc = -EINVAL;
+ break;
+ }
+ } else if (cfg.channel_count == 2) {
+ cfg.channel_count = AUDREC_CMD_MODE_STEREO;
+ if ((cfg.buffer_size ==
+ STEREO_DATA_SIZE_256) ||
+ (cfg.buffer_size ==
+ STEREO_DATA_SIZE_512) ||
+ (cfg.buffer_size ==
+ STEREO_DATA_SIZE_1024)) {
+ audio->buffer_size = cfg.buffer_size;
+ } else {
+ rc = -EINVAL;
+ break;
+ }
} else {
rc = -EINVAL;
break;
}
- } else if (cfg.channel_count == 2) {
- cfg.channel_count = AUDREC_CMD_MODE_STEREO;
- if ((cfg.buffer_size == STEREO_DATA_SIZE_256) ||
- (cfg.buffer_size == STEREO_DATA_SIZE_512) ||
- (cfg.buffer_size == STEREO_DATA_SIZE_1024)) {
- audio->buffer_size = cfg.buffer_size;
- } else {
- rc = -EINVAL;
- break;
+ } else if (audio->build_id[17] == '0') {
+ audio->enc_type = ENC_TYPE_WAV | audio->mode;
+ if (cfg.channel_count == 1) {
+ cfg.channel_count = AUDREC_CMD_MODE_MONO;
+ audio->buffer_size = MONO_DATA_SIZE_1024;
+ } else if (cfg.channel_count == 2) {
+ cfg.channel_count = AUDREC_CMD_MODE_STEREO;
+ audio->buffer_size = STEREO_DATA_SIZE_1024;
}
} else {
- rc = -EINVAL;
- break;
+ MM_ERR("wrong build_id = %s\n", audio->build_id);
+ return -ENODEV;
}
+ MM_ERR("buffer size configured is = %d\n", audio->buffer_size);
audio->samp_rate = cfg.sample_rate;
audio->channel_mode = cfg.channel_count;
break;
@@ -910,6 +940,8 @@
file->private_data = audio;
audio->opened = 1;
rc = 0;
+ audio->build_id = socinfo_get_build_id();
+ MM_ERR("build id used is = %s\n", audio->build_id);
done:
mutex_unlock(&audio->lock);
return rc;
diff --git a/arch/arm/mach-msm/qdsp5v2/audio_qcelp_in.c b/arch/arm/mach-msm/qdsp5v2/audio_qcelp_in.c
index 36fc3dcf..11599f8 100644
--- a/arch/arm/mach-msm/qdsp5v2/audio_qcelp_in.c
+++ b/arch/arm/mach-msm/qdsp5v2/audio_qcelp_in.c
@@ -34,6 +34,7 @@
#include <mach/iommu.h>
#include <mach/iommu_domains.h>
#include <mach/msm_subsystem_map.h>
+#include <mach/socinfo.h>
#include <mach/qdsp5v2/qdsp5audreccmdi.h>
#include <mach/qdsp5v2/qdsp5audrecmsg.h>
#include <mach/qdsp5v2/audpreproc.h>
@@ -139,6 +140,7 @@
int enabled;
int running;
int stopped; /* set when stopped, cleared on flush */
+ char *build_id;
};
struct audio_frame {
@@ -562,7 +564,13 @@
struct audpreproc_audrec_cmd_enc_cfg cmd;
memset(&cmd, 0, sizeof(cmd));
- cmd.cmd_id = AUDPREPROC_AUDREC_CMD_ENC_CFG_2;
+ if (audio->build_id[17] == '1') {
+ cmd.cmd_id = AUDPREPROC_AUDREC_CMD_ENC_CFG_2;
+ MM_ERR("sending AUDPREPROC_AUDREC_CMD_ENC_CFG_2 command");
+ } else {
+ cmd.cmd_id = AUDPREPROC_AUDREC_CMD_ENC_CFG;
+ MM_ERR("sending AUDPREPROC_AUDREC_CMD_ENC_CFG command");
+ }
cmd.stream_id = audio->enc_id;
if (enable)
@@ -1466,6 +1474,8 @@
file->private_data = audio;
audio->opened = 1;
audio->out_frame_cnt++;
+ audio->build_id = socinfo_get_build_id();
+ MM_ERR("build id used is = %s\n", audio->build_id);
done:
mutex_unlock(&audio->lock);
return rc;
diff --git a/arch/arm/mach-msm/qdsp6v2/audio_multi_aac.c b/arch/arm/mach-msm/qdsp6v2/audio_multi_aac.c
index 553a2e4..169e348 100644
--- a/arch/arm/mach-msm/qdsp6v2/audio_multi_aac.c
+++ b/arch/arm/mach-msm/qdsp6v2/audio_multi_aac.c
@@ -18,6 +18,8 @@
#include <linux/msm_audio_aac.h>
#include "audio_utils_aio.h"
+#define AUDIO_AAC_DUAL_MONO_INVALID -1
+
/* Default number of pre-allocated event packets */
#define PCM_BUFSZ_MIN_AACM ((8*1024) + sizeof(struct dec_meta_out))
@@ -35,6 +37,7 @@
case ASM_DATA_CMD_MEDIA_FORMAT_UPDATE:
case ASM_STREAM_CMD_SET_ENCDEC_PARAM:
case ASM_DATA_EVENT_SR_CM_CHANGE_NOTIFY:
+ case ASM_DATA_EVENT_ENC_SR_CM_NOTIFY:
audio_aio_cb(opcode, token, payload, audio);
break;
default:
@@ -65,8 +68,8 @@
if (audio->feedback == NON_TUNNEL_MODE) {
/* Configure PCM output block */
rc = q6asm_enc_cfg_blk_pcm(audio->ac,
- audio->pcm_cfg.sample_rate,
- audio->pcm_cfg.channel_count);
+ 0, /*native sampling rate*/
+ (audio->pcm_cfg.channel_count <= 2) ? 0 : 2);
if (rc < 0) {
pr_err("pcm output block config failed\n");
break;
@@ -145,10 +148,52 @@
break;
}
case AUDIO_SET_AAC_CONFIG: {
+ struct msm_audio_aac_config *aac_config;
if (copy_from_user(audio->codec_cfg, (void *)arg,
sizeof(struct msm_audio_aac_config))) {
rc = -EFAULT;
- break;
+ } else {
+ uint16_t sce_left = 1, sce_right = 2;
+ aac_config = audio->codec_cfg;
+ if ((aac_config->dual_mono_mode <
+ AUDIO_AAC_DUAL_MONO_PL_PR) ||
+ (aac_config->dual_mono_mode >
+ AUDIO_AAC_DUAL_MONO_PL_SR)) {
+ pr_err("%s:AUDIO_SET_AAC_CONFIG: Invalid"
+ "dual_mono mode =%d\n", __func__,
+ aac_config->dual_mono_mode);
+ } else {
+ /* convert the data from user into sce_left
+ * and sce_right based on the definitions
+ */
+ pr_debug("%s: AUDIO_SET_AAC_CONFIG: modify"
+ "dual_mono mode =%d\n", __func__,
+ aac_config->dual_mono_mode);
+ switch (aac_config->dual_mono_mode) {
+ case AUDIO_AAC_DUAL_MONO_PL_PR:
+ sce_left = 1;
+ sce_right = 1;
+ break;
+ case AUDIO_AAC_DUAL_MONO_SL_SR:
+ sce_left = 2;
+ sce_right = 2;
+ break;
+ case AUDIO_AAC_DUAL_MONO_SL_PR:
+ sce_left = 2;
+ sce_right = 1;
+ break;
+ case AUDIO_AAC_DUAL_MONO_PL_SR:
+ default:
+ sce_left = 1;
+ sce_right = 2;
+ break;
+ }
+ rc = q6asm_cfg_dual_mono_aac(audio->ac,
+ sce_left, sce_right);
+ if (rc < 0)
+ pr_err("%s: asm cmd dualmono failed"
+ " rc=%d\n", __func__, rc);
+ } break;
}
break;
}
@@ -164,6 +209,7 @@
{
struct q6audio_aio *audio = NULL;
int rc = 0;
+ struct msm_audio_aac_config *aac_config = NULL;
#ifdef CONFIG_DEBUG_FS
/* 4 bytes represents decoder number, 1 byte for terminate string */
@@ -185,7 +231,10 @@
return -ENOMEM;
}
+ aac_config = audio->codec_cfg;
+
audio->pcm_cfg.buffer_size = PCM_BUFSZ_MIN_AACM;
+ aac_config->dual_mono_mode = AUDIO_AAC_DUAL_MONO_INVALID;
audio->ac = q6asm_audio_client_alloc((app_cb) q6_audio_aac_cb,
(void *)audio);
diff --git a/arch/arm/mach-msm/qdsp6v2/lpa_if_hdmi.c b/arch/arm/mach-msm/qdsp6v2/lpa_if_hdmi.c
index 11fff28..cd1fe4c 100644
--- a/arch/arm/mach-msm/qdsp6v2/lpa_if_hdmi.c
+++ b/arch/arm/mach-msm/qdsp6v2/lpa_if_hdmi.c
@@ -28,17 +28,6 @@
#include <sound/dai.h>
#include "q6core.h"
-#define NUM_FRA_IN_BLOCK 192
-#define NUM_SAMP_PER_CH_PER_AC3_FRAME 1536
-#define AC3_REP_PER 1536 /* num of 60958 Frames */
-#define FRAME_60958_SZ 8 /* bytes */
-#define PREABLE_61937_SZ_16_BIT 4 /* in 16 bit words */
-
-
-#define MAX_AC3_FRA_SZ_16_BIT 1920 /* in 16 bit words */
-#define DMA_PERIOD_SZ (AC3_REP_PER * FRAME_60958_SZ)
-#define DMA_BUF_SZ (DMA_PERIOD_SZ * 2)
-#define USER_BUF_SZ DMA_PERIOD_SZ
#define DMA_ALLOC_BUF_SZ (SZ_4K * 6)
#define HDMI_AUDIO_FIFO_WATER_MARK 4
@@ -62,6 +51,7 @@
u32 dma_ch;
wait_queue_head_t wait;
u32 config;
+ u32 dma_period_sz;
};
static struct lpa_if *lpa_if_ptr;
@@ -127,12 +117,11 @@
dma_params.src_start = lpa_if->buffer_phys;
dma_params.buffer = lpa_if->buffer;
- dma_params.buffer_size = DMA_BUF_SZ;
- dma_params.period_size = DMA_PERIOD_SZ;
+ dma_params.buffer_size = lpa_if->dma_period_sz * 2;
+ dma_params.period_size = lpa_if->dma_period_sz;
dma_params.channels = 2;
lpa_if->dma_ch = 0;
-
dai_set_params(lpa_if->dma_ch, &dma_params);
register_dma_irq_handler(lpa_if->dma_ch, lpa_if_irq, (void *)lpa_if);
@@ -195,7 +184,33 @@
rc = -EFAULT;
}
break;
+ case AUDIO_SET_CONFIG:
+ pr_debug("AUDIO_SET_CONFIG\n");
+ if (copy_from_user(&lpa_if->dma_period_sz, (void *) arg,
+ sizeof(unsigned int))) {
+ pr_debug("%s:failed to copy from user\n", __func__);
+ rc = -EFAULT;
+ }
+ if (lpa_if->dma_period_sz > DMA_ALLOC_BUF_SZ) {
+ pr_err("Dma buffer size greater than allocated size\n");
+ return -EINVAL;
+ }
+ pr_debug("Dma_period_sz %d\n", lpa_if->dma_period_sz);
+ lpa_if->cfg.buffer_count = 2;
+ lpa_if->cfg.buffer_size = lpa_if->dma_period_sz * 2;
+ lpa_if->audio_buf[0].phys = lpa_if->buffer_phys;
+ lpa_if->audio_buf[0].data = lpa_if->buffer;
+ lpa_if->audio_buf[0].size = lpa_if->dma_period_sz;
+ lpa_if->audio_buf[0].used = 0;
+
+ lpa_if->audio_buf[1].phys =
+ lpa_if->buffer_phys + lpa_if->dma_period_sz;
+ lpa_if->audio_buf[1].data =
+ lpa_if->buffer + lpa_if->dma_period_sz;
+ lpa_if->audio_buf[1].size = lpa_if->dma_period_sz;
+ lpa_if->audio_buf[1].used = 0;
+ break;
default:
pr_err("UnKnown Ioctl\n");
rc = -EINVAL;
@@ -209,26 +224,9 @@
static int lpa_if_open(struct inode *inode, struct file *file)
{
- struct lpa_if *lpa_if;
-
pr_debug("\n");
file->private_data = lpa_if_ptr;
- lpa_if = lpa_if_ptr;
-
- lpa_if->cfg.buffer_count = 2;
- lpa_if->cfg.buffer_size = USER_BUF_SZ;
-
- lpa_if->audio_buf[0].phys = lpa_if->buffer_phys;
- lpa_if->audio_buf[0].data = lpa_if->buffer;
- lpa_if->audio_buf[0].size = DMA_PERIOD_SZ;
- lpa_if->audio_buf[0].used = 0;
-
- lpa_if->audio_buf[1].phys = lpa_if->buffer_phys + DMA_PERIOD_SZ;
- lpa_if->audio_buf[1].data = lpa_if->buffer + DMA_PERIOD_SZ;
- lpa_if->audio_buf[1].size = DMA_PERIOD_SZ;
- lpa_if->audio_buf[1].used = 0;
-
dma_buf_index = 0;
core_req_bus_bandwith(AUDIO_IF_BUS_ID, 100000, 0);
@@ -287,8 +285,8 @@
xfer = count;
- if (xfer > USER_BUF_SZ)
- xfer = USER_BUF_SZ;
+ if (xfer > lpa_if->dma_period_sz)
+ xfer = lpa_if->dma_period_sz;
if (copy_from_user(ab->data, buf, xfer)) {
pr_err("copy from user failed\n");
diff --git a/arch/arm/mach-msm/sdio_al.c b/arch/arm/mach-msm/sdio_al.c
index 8267fad..ace437b 100644
--- a/arch/arm/mach-msm/sdio_al.c
+++ b/arch/arm/mach-msm/sdio_al.c
@@ -108,6 +108,7 @@
* packet) rx data.
*/
#define DEFAULT_READ_THRESHOLD (1024)
+#define LOW_LATENCY_THRESHOLD (1)
/* Extra bytes to ensure getting the rx threshold interrupt on stream channels
when restoring the threshold after sleep */
@@ -119,7 +120,6 @@
#define THRESHOLD_DISABLE_VAL (0xFFFFFFFF)
-
/** Mailbox polling time for packet channels */
#define DEFAULT_POLL_DELAY_MSEC 10
/** Mailbox polling time for streaming channels */
@@ -986,7 +986,7 @@
continue;
}
if (ch->is_packet_mode == false) {
- ch->read_threshold = 1;
+ ch->read_threshold = LOW_LATENCY_THRESHOLD;
set_pipe_threshold(sdio_al_dev,
ch->rx_pipe_index,
ch->read_threshold);
@@ -1156,13 +1156,22 @@
sdio_al_dev->host->index);
}
ch->read_avail = read_avail;
- /* Restore default thresh for non packet channels */
+
+ /*
+ * Restore default thresh for non packet channels.
+ * in case it IS low latency channel then read_threshold
+ * and def_read_threshold are both
+ * LOW_LATENCY_THRESHOLD
+ */
if ((ch->read_threshold != ch->def_read_threshold) &&
(read_avail >= ch->threshold_change_cnt)) {
- ch->read_threshold = ch->def_read_threshold;
- set_pipe_threshold(sdio_al_dev,
- ch->rx_pipe_index,
- ch->read_threshold);
+ if (!ch->is_low_latency_ch) {
+ ch->read_threshold =
+ ch->def_read_threshold;
+ set_pipe_threshold(sdio_al_dev,
+ ch->rx_pipe_index,
+ ch->read_threshold);
+ }
}
}
@@ -1968,14 +1977,18 @@
goto exit_err;
}
- /* Aggregation up to 90% of the maximum size */
- ch->read_threshold = (ch_config->max_rx_threshold * 9) / 10;
+ ch->read_threshold = LOW_LATENCY_THRESHOLD;
+ ch->is_low_latency_ch = ch_config->is_low_latency_ch;
/* Threshold on 50% of the maximum size , sdioc uses double-buffer */
ch->write_threshold = (ch_config->max_tx_threshold * 5) / 10;
ch->threshold_change_cnt = ch->ch_config.max_rx_threshold -
ch->read_threshold + THRESHOLD_CHANGE_EXTRA_BYTES;
- ch->def_read_threshold = ch->read_threshold;
+ if (ch->is_low_latency_ch)
+ ch->def_read_threshold = LOW_LATENCY_THRESHOLD;
+ else /* Aggregation up to 90% of the maximum size */
+ ch->def_read_threshold = (ch_config->max_rx_threshold * 9) / 10;
+
ch->is_packet_mode = ch_config->is_packet_mode;
if (!ch->is_packet_mode) {
ch->poll_delay_msec = DEFAULT_POLL_DELAY_NOPACKET_MSEC;
diff --git a/arch/arm/mach-msm/sdio_al_private.h b/arch/arm/mach-msm/sdio_al_private.h
index f352499..36d9ec1 100644
--- a/arch/arm/mach-msm/sdio_al_private.h
+++ b/arch/arm/mach-msm/sdio_al_private.h
@@ -66,7 +66,8 @@
u32 is_host_ok_to_sleep;
u32 is_packet_mode;
u32 peer_operation;
- u32 reserved[24];
+ u32 is_low_latency_ch;
+ u32 reserved[23];
};
@@ -173,6 +174,7 @@
int min_write_avail;
int poll_delay_msec;
int is_packet_mode;
+ int is_low_latency_ch;
struct peer_sdioc_channel_config ch_config;
diff --git a/arch/arm/mach-msm/subsystem_restart.c b/arch/arm/mach-msm/subsystem_restart.c
index 4d6f4b1..b862ad4 100644
--- a/arch/arm/mach-msm/subsystem_restart.c
+++ b/arch/arm/mach-msm/subsystem_restart.c
@@ -10,6 +10,8 @@
* GNU General Public License for more details.
*/
+#define pr_fmt(fmt) "subsys-restart: %s(): " fmt, __func__
+
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/uaccess.h>
@@ -32,12 +34,6 @@
#include "smd_private.h"
-#if defined(SUBSYS_RESTART_DEBUG)
-#define dprintk(msg...) printk(msg)
-#else
-#define dprintk(msg...)
-#endif
-
struct subsys_soc_restart_order {
const char * const *subsystem_list;
int count;
@@ -152,12 +148,11 @@
case RESET_SOC:
case RESET_SUBSYS_COUPLED:
case RESET_SUBSYS_INDEPENDENT:
- pr_info("Subsystem Restart: Phase %d behavior activated.\n",
- restart_level);
+ pr_info("Phase %d behavior activated.\n", restart_level);
break;
case RESET_SUBSYS_MIXED:
- pr_info("Subsystem Restart: Phase 2+ behavior activated.\n");
+ pr_info("Phase 2+ behavior activated.\n");
break;
default:
@@ -277,10 +272,10 @@
}
if (!n) {
time_first = &r_log->time;
- pr_debug("time_first: %ld", time_first->tv_sec);
+ pr_debug("Time_first: %ld\n", time_first->tv_sec);
}
n++;
- pr_debug("restart_time: %ld\n", r_log->time.tv_sec);
+ pr_debug("Restart_time: %ld\n", r_log->time.tv_sec);
}
if (time_first && n >= max_restarts_check) {
@@ -327,8 +322,7 @@
shutdown_lock = &soc_restart_order->shutdown_lock;
}
- dprintk("%s[%p]: Attempting to get shutdown lock!\n", __func__,
- current);
+ pr_debug("[%p]: Attempting to get shutdown lock!\n", current);
/* Try to acquire shutdown_lock. If this fails, these subsystems are
* already being restarted - return.
@@ -338,8 +332,7 @@
do_exit(0);
}
- dprintk("%s[%p]: Attempting to get powerup lock!\n", __func__,
- current);
+ pr_debug("[%p]: Attempting to get powerup lock!\n", current);
/* Now that we've acquired the shutdown lock, either we're the first to
* restart these subsystems or some other thread is doing the powerup
@@ -347,7 +340,8 @@
* out, since a subsystem died in its powerup sequence.
*/
if (!mutex_trylock(powerup_lock))
- panic("%s: Subsystem died during powerup!", __func__);
+ panic("%s[%p]: Subsystem died during powerup!",
+ __func__, current);
do_epoch_check(subsys);
@@ -357,8 +351,8 @@
*/
mutex_lock(&soc_order_reg_lock);
- dprintk("%s: Starting restart sequence for %s\n", __func__,
- r_work->subsys->name);
+ pr_debug("[%p]: Starting restart sequence for %s\n", current,
+ r_work->subsys->name);
_send_notification_to_order(restart_list,
restart_list_count,
@@ -369,12 +363,12 @@
if (!restart_list[i])
continue;
- pr_info("subsys-restart: Shutting down %s\n",
+ pr_info("[%p]: Shutting down %s\n", current,
restart_list[i]->name);
if (restart_list[i]->shutdown(subsys) < 0)
- panic("%s: Failed to shutdown %s!\n", __func__,
- restart_list[i]->name);
+ panic("subsys-restart: %s[%p]: Failed to shutdown %s!",
+ __func__, current, restart_list[i]->name);
}
_send_notification_to_order(restart_list, restart_list_count,
@@ -395,8 +389,8 @@
if (restart_list[i]->ramdump)
if (restart_list[i]->ramdump(enable_ramdumps,
subsys) < 0)
- pr_warn("%s(%s): Ramdump failed.", __func__,
- restart_list[i]->name);
+ pr_warn("%s[%p]: Ramdump failed.\n",
+ restart_list[i]->name, current);
}
_send_notification_to_order(restart_list,
@@ -408,26 +402,26 @@
if (!restart_list[i])
continue;
- pr_info("subsys-restart: Powering up %s\n",
- restart_list[i]->name);
+ pr_info("[%p]: Powering up %s\n", current,
+ restart_list[i]->name);
if (restart_list[i]->powerup(subsys) < 0)
- panic("%s: Failed to powerup %s!", __func__,
- restart_list[i]->name);
+ panic("%s[%p]: Failed to powerup %s!", __func__,
+ current, restart_list[i]->name);
}
_send_notification_to_order(restart_list,
restart_list_count,
SUBSYS_AFTER_POWERUP);
- pr_info("%s: Restart sequence for %s completed.", __func__,
- r_work->subsys->name);
+ pr_info("[%p]: Restart sequence for %s completed.\n",
+ current, r_work->subsys->name);
mutex_unlock(powerup_lock);
mutex_unlock(&soc_order_reg_lock);
- dprintk("%s: Released powerup lock!\n", __func__);
+ pr_debug("[%p]: Released powerup lock!\n", current);
kfree(data);
do_exit(0);
@@ -440,11 +434,11 @@
struct restart_thread_data *data = NULL;
if (!subsys_name) {
- pr_err("%s: Invalid subsystem name.", __func__);
+ pr_err("Invalid subsystem name.\n");
return -EINVAL;
}
- pr_info("Subsystem Restart: Restart sequence requested for %s\n",
+ pr_info("Restart sequence requested for %s\n",
subsys_name);
/* List of subsystems is protected by a lock. New subsystems can
@@ -453,8 +447,7 @@
subsys = _find_subsystem(subsys_name);
if (!subsys) {
- pr_warn("%s: Unregistered subsystem %s!", __func__,
- subsys_name);
+ pr_warn("Unregistered subsystem %s!\n", subsys_name);
return -EINVAL;
}
@@ -462,8 +455,7 @@
data = kzalloc(sizeof(struct restart_thread_data), GFP_KERNEL);
if (!data) {
restart_level = RESET_SOC;
- pr_warn("%s: Failed to alloc restart data. Resetting.",
- __func__);
+ pr_warn("Failed to alloc restart data. Resetting.\n");
} else {
if (restart_level == RESET_SUBSYS_COUPLED ||
restart_level == RESET_SUBSYS_MIXED)
@@ -480,8 +472,8 @@
case RESET_SUBSYS_COUPLED:
case RESET_SUBSYS_MIXED:
case RESET_SUBSYS_INDEPENDENT:
- dprintk("%s: Restarting %s [level=%d]!\n", __func__,
- subsys_name, restart_level);
+ pr_debug("Restarting %s [level=%d]!\n", subsys_name,
+ restart_level);
/* Let the kthread handle the actual restarting. Using a
* workqueue will not work since all restart requests are
@@ -490,7 +482,7 @@
* sequence.
*/
tsk = kthread_run(subsystem_restart_thread, data,
- "subsystem_subsystem_restart_thread");
+ "subsystem_restart_thread");
if (IS_ERR(tsk))
panic("%s: Unable to create thread to restart %s",
__func__, subsys->name);
diff --git a/arch/arm/mach-msm/sysmon.h b/arch/arm/mach-msm/sysmon.h
index 5fb75bc..429a155 100644
--- a/arch/arm/mach-msm/sysmon.h
+++ b/arch/arm/mach-msm/sysmon.h
@@ -17,6 +17,9 @@
#include <mach/subsystem_notif.h>
+/**
+ * enum subsys_id - Destination subsystems for events.
+ */
enum subsys_id {
SYSMON_SS_MODEM,
SYSMON_SS_LPASS,
@@ -26,6 +29,20 @@
SYSMON_NUM_SS
};
+
+/**
+ * sysmon_send_event() - Notify a subsystem of another's state change.
+ * @dest_ss: ID of subsystem the notification should be sent to.
+ * @event_ss: String name of the subsystem that generated the notification.
+ * @notif: ID of the notification type (ex. SUBSYS_BEFORE_SHUTDOWN)
+ *
+ * Returns 0 for success, -EINVAL for invalid destination or notification IDs,
+ * -ENODEV if the SMD channel is not open, -ETIMEDOUT if the destination
+ * subsystem does not respond, and -ENOSYS if the destination subsystem
+ * responds, but with something other than an acknowledgement.
+ *
+ * If CONFIG_MSM_SYSMON_COMM is not defined, always return success (0).
+ */
#ifdef CONFIG_MSM_SYSMON_COMM
int sysmon_send_event(enum subsys_id dest_ss, const char *event_ss,
enum subsys_notif_type notif);
diff --git a/drivers/bluetooth/hci_smd.c b/drivers/bluetooth/hci_smd.c
index 31634ff..66bab6b 100644
--- a/drivers/bluetooth/hci_smd.c
+++ b/drivers/bluetooth/hci_smd.c
@@ -302,6 +302,7 @@
break;
}
+ kfree_skb(skb);
wake_unlock(&hs.wake_lock_tx);
return ret;
}
diff --git a/drivers/char/diag/diagchar_core.c b/drivers/char/diag/diagchar_core.c
index 6fa043c..eabdb4f 100644
--- a/drivers/char/diag/diagchar_core.c
+++ b/drivers/char/diag/diagchar_core.c
@@ -253,7 +253,18 @@
return -ENOMEM;
}
-void diag_fill_reg_table(int j, struct bindpkt_params *params,
+void diag_clear_reg(int proc_num)
+{
+ int i;
+
+ for (i = 0; i < diag_max_registration; i++) {
+ if (driver->table[i].client_id == proc_num) {
+ driver->table[i].process_id = 0;
+ }
+ }
+}
+
+void diag_add_reg(int j, struct bindpkt_params *params,
int *success, int *count_entries)
{
*success = 1;
@@ -284,7 +295,7 @@
mutex_lock(&driver->diagchar_mutex);
for (i = 0; i < diag_max_registration; i++) {
if (driver->table[i].process_id == 0) {
- diag_fill_reg_table(i, pkt_params->params,
+ diag_add_reg(i, pkt_params->params,
&success, &count_entries);
if (pkt_params->count > count_entries) {
pkt_params->params++;
@@ -315,7 +326,7 @@
driver->table = temp_buf;
}
for (j = i; j < diag_max_registration; j++) {
- diag_fill_reg_table(j, pkt_params->params,
+ diag_add_reg(j, pkt_params->params,
&success, &count_entries);
if (pkt_params->count > count_entries) {
pkt_params->params++;
diff --git a/drivers/char/diag/diagfwd.c b/drivers/char/diag/diagfwd.c
index e49d57c..caf3901 100644
--- a/drivers/char/diag/diagfwd.c
+++ b/drivers/char/diag/diagfwd.c
@@ -70,7 +70,7 @@
#define CHK_OVERFLOW(bufStart, start, end, length) \
((bufStart <= start) && (end - start >= length)) ? 1 : 0
-int chk_config_get_id()
+int chk_config_get_id(void)
{
switch (socinfo_get_id()) {
case APQ8060_MACHINE_ID:
@@ -78,6 +78,23 @@
return APQ8060_TOOLS_ID;
case AO8960_MACHINE_ID:
return AO8960_TOOLS_ID;
+ case APQ8064_MACHINE_ID:
+ return APQ8064_TOOLS_ID;
+ default:
+ return 0;
+ }
+}
+
+/*
+ * This will return TRUE for targets which support apps only mode.
+ * This applies to 8960 and newer targets.
+ */
+int chk_apps_only(void)
+{
+ switch (socinfo_get_id()) {
+ case AO8960_MACHINE_ID:
+ case APQ8064_MACHINE_ID:
+ return 1;
default:
return 0;
}
@@ -576,8 +593,8 @@
diag_update_event_mask(buf+1, 0, 0);
diag_update_userspace_clients(EVENT_MASKS_TYPE);
#if defined(CONFIG_DIAG_OVER_USB)
- /* Check for Apps Only 8960 */
- if (!(driver->ch) && (chk_config_get_id() == AO8960_TOOLS_ID)) {
+ /* Check for Apps Only */
+ if (!(driver->ch) && chk_apps_only()) {
/* echo response back for apps only DIAG */
driver->apps_rsp_buf[0] = 0x60;
driver->apps_rsp_buf[1] = 0x0;
@@ -594,8 +611,8 @@
diag_update_log_mask(*(int *)buf, buf+8, *(int *)(buf+4));
diag_update_userspace_clients(LOG_MASKS_TYPE);
#if defined(CONFIG_DIAG_OVER_USB)
- /* Check for Apps Only 8960 */
- if (!(driver->ch) && (chk_config_get_id() == AO8960_TOOLS_ID)) {
+ /* Check for Apps Only */
+ if (!(driver->ch) && chk_apps_only()) {
/* echo response back for Apps only DIAG */
driver->apps_rsp_buf[0] = 0x73;
*(int *)(driver->apps_rsp_buf + 4) = 0x3; /* op. ID */
@@ -617,7 +634,7 @@
diag_update_msg_mask(ssid_first, ssid_last , buf + 8);
diag_update_userspace_clients(MSG_MASKS_TYPE);
#if defined(CONFIG_DIAG_OVER_USB)
- if (!(driver->ch) && (chk_config_get_id() == AO8960_TOOLS_ID)) {
+ if (!(driver->ch) && chk_apps_only()) {
/* echo response back for apps only DIAG */
for (i = 0; i < 8 + ssid_range; i++)
*(driver->apps_rsp_buf + i) = *(buf+i);
@@ -627,9 +644,8 @@
#endif
}
#if defined(CONFIG_DIAG_OVER_USB)
- /* Check for Apps Only 8960 & get event mask request */
- else if (!(driver->ch) && (chk_config_get_id() == AO8960_TOOLS_ID)
- && *buf == 0x81) {
+ /* Check for Apps Only & get event mask request */
+ else if (!(driver->ch) && chk_apps_only() && *buf == 0x81) {
driver->apps_rsp_buf[0] = 0x81;
driver->apps_rsp_buf[1] = 0x0;
*(uint16_t *)(driver->apps_rsp_buf + 2) = 0x0;
@@ -639,8 +655,8 @@
ENCODE_RSP_AND_SEND(6 + EVENT_LAST_ID/8);
return 0;
}
- /* Get log ID range & Check for Apps Only 8960 */
- else if (!(driver->ch) && (chk_config_get_id() == AO8960_TOOLS_ID)
+ /* Get log ID range & Check for Apps Only */
+ else if (!(driver->ch) && chk_apps_only()
&& (*buf == 0x73) && *(int *)(buf+4) == 1) {
driver->apps_rsp_buf[0] = 0x73;
*(int *)(driver->apps_rsp_buf + 4) = 0x1; /* operation ID */
@@ -665,7 +681,7 @@
return 0;
}
/* Respond to Get SSID Range request message */
- else if (!(driver->ch) && (chk_config_get_id() == AO8960_TOOLS_ID)
+ else if (!(driver->ch) && chk_apps_only()
&& (*buf == 0x7d) && (*(buf+1) == 0x1)) {
driver->apps_rsp_buf[0] = 0x7d;
driver->apps_rsp_buf[1] = 0x1;
@@ -713,8 +729,8 @@
ENCODE_RSP_AND_SEND(83);
return 0;
}
- /* Check for AO8960 Respond to Get Subsys Build mask */
- else if (!(driver->ch) && (chk_config_get_id() == AO8960_TOOLS_ID)
+ /* Check for Apps Only Respond to Get Subsys Build mask */
+ else if (!(driver->ch) && chk_apps_only()
&& (*buf == 0x7d) && (*(buf+1) == 0x2)) {
ssid_first = *(uint16_t *)(buf + 2);
ssid_last = *(uint16_t *)(buf + 4);
@@ -901,13 +917,13 @@
driver->debug_flag = 0;
}
/* send error responses from APPS for Central Routing */
- if (type == 1 && chk_config_get_id() == AO8960_TOOLS_ID) {
+ if (type == 1 && chk_apps_only()) {
diag_send_error_rsp(hdlc.dest_idx);
type = 0;
}
/* implies this packet is NOT meant for apps */
if (!(driver->ch) && type == 1) {
- if (chk_config_get_id() == AO8960_TOOLS_ID) {
+ if (chk_apps_only()) {
diag_send_error_rsp(hdlc.dest_idx);
} else { /* APQ 8060, Let Q6 respond */
if (driver->chqdsp)
@@ -1129,7 +1145,11 @@
static void diag_smd_notify(void *ctxt, unsigned event)
{
- queue_work(driver->diag_wq, &(driver->diag_read_smd_work));
+ if (event == SMD_EVENT_CLOSE) {
+ pr_info("diag: clean modem registration\n");
+ diag_clear_reg(MODEM_PROC);
+ } else
+ queue_work(driver->diag_wq, &(driver->diag_read_smd_work));
}
#if defined(CONFIG_MSM_N_WAY_SMD)
diff --git a/drivers/char/diag/diagfwd.h b/drivers/char/diag/diagfwd.h
index cc24cbc..6dacab7 100644
--- a/drivers/char/diag/diagfwd.h
+++ b/drivers/char/diag/diagfwd.h
@@ -26,7 +26,8 @@
long diagchar_ioctl(struct file *, unsigned int, unsigned long);
int diag_device_write(void *, int, struct diag_request *);
int mask_request_validate(unsigned char mask_buf[]);
-int chk_config_get_id(void);
+void diag_clear_reg(int);
+int chk_apps_only(void);
/* State for diag forwarding */
#ifdef CONFIG_DIAG_OVER_USB
int diagfwd_connect(void);
diff --git a/drivers/char/diag/diagfwd_cntl.c b/drivers/char/diag/diagfwd_cntl.c
index 2b88a9f..534c016 100644
--- a/drivers/char/diag/diagfwd_cntl.c
+++ b/drivers/char/diag/diagfwd_cntl.c
@@ -138,7 +138,7 @@
int r = 0;
/* open control ports only on 8960 */
- if (chk_config_get_id() == AO8960_TOOLS_ID) {
+ if (chk_apps_only()) {
if (pdev->id == SMD_APPS_MODEM)
r = smd_open("DIAG_CNTL", &driver->ch_cntl, driver,
diag_smd_cntl_notify);
diff --git a/drivers/char/hw_random/msm_rng.c b/drivers/char/hw_random/msm_rng.c
index 3a2cd9a..5937c78 100644
--- a/drivers/char/hw_random/msm_rng.c
+++ b/drivers/char/hw_random/msm_rng.c
@@ -22,6 +22,7 @@
#include <linux/io.h>
#include <linux/err.h>
#include <linux/types.h>
+#include <mach/socinfo.h>
#define DRIVER_NAME "msm_rng"
@@ -78,11 +79,11 @@
/* read random data from h/w */
do {
/* check status bit if data is available */
- if (!(readl(base + PRNG_STATUS_OFFSET) & 0x00000001))
+ if (!(readl_relaxed(base + PRNG_STATUS_OFFSET) & 0x00000001))
break; /* no data to read so just bail */
/* read FIFO */
- val = readl(base + PRNG_DATA_OUT_OFFSET);
+ val = readl_relaxed(base + PRNG_DATA_OUT_OFFSET);
if (!val)
break; /* no data to read so just bail */
@@ -106,6 +107,45 @@
.read = msm_rng_read,
};
+static int __devinit msm_rng_enable_hw(struct msm_rng_device *msm_rng_dev)
+{
+ unsigned long val = 0;
+ int ret = 0;
+ int error = 0;
+
+ ret = clk_enable(msm_rng_dev->prng_clk);
+ if (ret) {
+ dev_err(&(msm_rng_dev->pdev)->dev,
+ "failed to enable clock in probe\n");
+ error = -EPERM;
+ return error;
+ }
+
+ /* enable PRNG h/w*/
+ val = readl_relaxed(msm_rng_dev->base + PRNG_LFSR_CFG_OFFSET) &
+ PRNG_LFSR_CFG_MASK;
+ val |= PRNG_LFSR_CFG_MASK;
+ writel_relaxed(val, msm_rng_dev->base + PRNG_LFSR_CFG_OFFSET);
+
+ /* The PRNG CONFIG register should be read after writing to the
+ * PRNG_LFSR_CFG register.
+ */
+ mb();
+ val = readl_relaxed(msm_rng_dev->base + PRNG_CONFIG_OFFSET) &
+ PRNG_CONFIG_MASK;
+ val |= PRNG_CONFIG_ENABLE;
+ writel_relaxed(val, msm_rng_dev->base + PRNG_CONFIG_OFFSET);
+
+ /* The PRNG clk should be disabled only after we have enabled the
+ * PRNG H/W by writting to the PRNG_CONFIG register.
+ */
+ mb();
+
+ clk_disable(msm_rng_dev->prng_clk);
+
+ return error;
+}
+
static int __devinit msm_rng_probe(struct platform_device *pdev)
{
struct resource *res;
@@ -147,18 +187,25 @@
msm_rng_dev->pdev = pdev;
platform_set_drvdata(pdev, msm_rng_dev);
+ /* Enable rng h/w */
+ if (cpu_is_msm9615())
+ error = msm_rng_enable_hw(msm_rng_dev);
+
+ if (error)
+ goto rollback_clk;
+
/* register with hwrng framework */
msm_rng.priv = (unsigned long) msm_rng_dev;
error = hwrng_register(&msm_rng);
if (error) {
dev_err(&pdev->dev, "failed to register hwrng\n");
error = -EPERM;
- goto err_hw_register;
+ goto rollback_clk;
}
return 0;
-err_hw_register:
+rollback_clk:
clk_put(msm_rng_dev->prng_clk);
err_clk_get:
iounmap(msm_rng_dev->base);
diff --git a/drivers/crypto/msm/qcedev.c b/drivers/crypto/msm/qcedev.c
index 9d315d2..405d021 100644
--- a/drivers/crypto/msm/qcedev.c
+++ b/drivers/crypto/msm/qcedev.c
@@ -1440,11 +1440,6 @@
}
#else
-static int qcedev_pmem_ablk_cipher_max_xfer(struct qcedev_async_req *areq,
- struct qcedev_handle *handle)
-{
- return -EPERM;
-}
static int qcedev_pmem_ablk_cipher(struct qcedev_async_req *qcedev_areq,
struct qcedev_handle *handle)
{
@@ -1850,7 +1845,7 @@
podev))
return -EINVAL;
- if ((qcedev_areq.cipher_op_req.use_pmem) && (QCEDEV_USE_PMEM))
+ if (qcedev_areq.cipher_op_req.use_pmem)
err = qcedev_pmem_ablk_cipher(&qcedev_areq, handle);
else
err = qcedev_vbuf_ablk_cipher(&qcedev_areq, handle);
diff --git a/drivers/gpu/msm/adreno_postmortem.c b/drivers/gpu/msm/adreno_postmortem.c
index 7c7f0dc..cc69360 100644
--- a/drivers/gpu/msm/adreno_postmortem.c
+++ b/drivers/gpu/msm/adreno_postmortem.c
@@ -25,6 +25,7 @@
#include "a2xx_reg.h"
#define INVALID_RB_CMD 0xaaaaaaaa
+#define NUM_DWORDS_OF_RINGBUFFER_HISTORY 100
struct pm_id_name {
uint32_t id;
@@ -536,7 +537,12 @@
kgsl_regread(device, REG_CP_RB_RPTR_ADDR, &r3);
KGSL_LOG_DUMP(device,
"CP_RB: BASE = %08X | CNTL = %08X | RPTR_ADDR = %08X"
- "\n", cp_rb_base, r2, r3);
+ " | rb_count = %08X\n", cp_rb_base, r2, r3, rb_count);
+ {
+ struct adreno_ringbuffer *rb = &adreno_dev->ringbuffer;
+ if (rb->sizedwords != rb_count)
+ rb_count = rb->sizedwords;
+ }
kgsl_regread(device, REG_CP_RB_RPTR, &cp_rb_rptr);
kgsl_regread(device, REG_CP_RB_WPTR, &cp_rb_wptr);
@@ -683,13 +689,13 @@
goto error_vfree;
}
- read_idx = (int)cp_rb_rptr - 64;
+ read_idx = (int)cp_rb_rptr - NUM_DWORDS_OF_RINGBUFFER_HISTORY;
if (read_idx < 0)
read_idx += rb_count;
write_idx = (int)cp_rb_wptr + 16;
if (write_idx > rb_count)
write_idx -= rb_count;
- num_item += 64+16;
+ num_item += NUM_DWORDS_OF_RINGBUFFER_HISTORY+16;
if (num_item > rb_count)
num_item = rb_count;
if (write_idx >= read_idx)
@@ -736,7 +742,7 @@
the process in whose context the GPU hung */
cur_pt_base = pt_base;
- read_idx = (int)cp_rb_rptr - 64;
+ read_idx = (int)cp_rb_rptr - NUM_DWORDS_OF_RINGBUFFER_HISTORY;
if (read_idx < 0)
read_idx += rb_count;
KGSL_LOG_DUMP(device,
@@ -745,13 +751,14 @@
adreno_dump_rb(device, rb_copy, num_item<<2, read_idx, rb_count);
if (adreno_ib_dump_enabled()) {
- for (read_idx = 64; read_idx >= 0; --read_idx) {
+ for (read_idx = NUM_DWORDS_OF_RINGBUFFER_HISTORY;
+ read_idx >= 0; --read_idx) {
uint32_t this_cmd = rb_copy[read_idx];
if (this_cmd == cp_type3_packet(
CP_INDIRECT_BUFFER_PFD, 2)) {
uint32_t ib_addr = rb_copy[read_idx+1];
uint32_t ib_size = rb_copy[read_idx+2];
- if (cp_ib1_bufsz && cp_ib1_base == ib_addr) {
+ if (ib_size && cp_ib1_base == ib_addr) {
KGSL_LOG_DUMP(device,
"IB1: base:%8.8X "
"count:%d\n", ib_addr, ib_size);
@@ -762,9 +769,9 @@
}
}
for (i = 0; i < ib_list.count; ++i) {
- if (cp_ib2_bufsz && cp_ib2_base == ib_list.bases[i]) {
- uint32_t ib_size = ib_list.sizes[i];
- uint32_t ib_offset = ib_list.offsets[i];
+ uint32_t ib_size = ib_list.sizes[i];
+ uint32_t ib_offset = ib_list.offsets[i];
+ if (ib_size && cp_ib2_base == ib_list.bases[i]) {
KGSL_LOG_DUMP(device,
"IB2: base:%8.8X count:%d\n",
cp_ib2_base, ib_size);
diff --git a/drivers/gpu/msm/kgsl.c b/drivers/gpu/msm/kgsl.c
index 165bbbf..7e61a32 100644
--- a/drivers/gpu/msm/kgsl.c
+++ b/drivers/gpu/msm/kgsl.c
@@ -1226,7 +1226,11 @@
entry->memdesc.size = size;
entry->memdesc.physaddr = phys + (offset & PAGE_MASK);
entry->memdesc.hostptr = (void *) (virt + (offset & PAGE_MASK));
- entry->memdesc.ops = &kgsl_contiguous_ops;
+
+ ret = memdesc_sg_phys(&entry->memdesc,
+ phys + (offset & PAGE_MASK), size);
+ if (ret)
+ goto err;
return 0;
err:
@@ -1236,6 +1240,60 @@
return ret;
}
+static int memdesc_sg_virt(struct kgsl_memdesc *memdesc,
+ void *addr, int size)
+{
+ int i;
+ int sglen = PAGE_ALIGN(size) / PAGE_SIZE;
+ unsigned long paddr = (unsigned long) addr;
+
+ memdesc->sg = kmalloc(sglen * sizeof(struct scatterlist),
+ GFP_KERNEL);
+ if (memdesc->sg == NULL)
+ return -ENOMEM;
+
+ memdesc->sglen = sglen;
+ sg_init_table(memdesc->sg, sglen);
+
+ spin_lock(¤t->mm->page_table_lock);
+
+ for (i = 0; i < sglen; i++, paddr += PAGE_SIZE) {
+ struct page *page;
+ pmd_t *ppmd;
+ pte_t *ppte;
+ pgd_t *ppgd = pgd_offset(current->mm, paddr);
+
+ if (pgd_none(*ppgd) || pgd_bad(*ppgd))
+ goto err;
+
+ ppmd = pmd_offset(ppgd, paddr);
+ if (pmd_none(*ppmd) || pmd_bad(*ppmd))
+ goto err;
+
+ ppte = pte_offset_map(ppmd, paddr);
+ if (ppte == NULL)
+ goto err;
+
+ page = pfn_to_page(pte_pfn(*ppte));
+ if (!page)
+ goto err;
+
+ sg_set_page(&memdesc->sg[i], page, PAGE_SIZE, 0);
+ pte_unmap(ppte);
+ }
+
+ spin_unlock(¤t->mm->page_table_lock);
+
+ return 0;
+
+err:
+ spin_unlock(¤t->mm->page_table_lock);
+ kfree(memdesc->sg);
+ memdesc->sg = NULL;
+
+ return -EINVAL;
+}
+
static int kgsl_setup_hostptr(struct kgsl_mem_entry *entry,
struct kgsl_pagetable *pagetable,
void *hostptr, unsigned int offset,
@@ -1285,9 +1343,9 @@
entry->memdesc.pagetable = pagetable;
entry->memdesc.size = size;
entry->memdesc.hostptr = hostptr + (offset & PAGE_MASK);
- entry->memdesc.ops = &kgsl_userptr_ops;
- return 0;
+ return memdesc_sg_virt(&entry->memdesc,
+ hostptr + (offset & PAGE_MASK), size);
}
#ifdef CONFIG_ASHMEM
@@ -1335,11 +1393,13 @@
}
entry->file_ptr = filep;
-
entry->memdesc.pagetable = pagetable;
entry->memdesc.size = ALIGN(size, PAGE_SIZE);
entry->memdesc.hostptr = hostptr;
- entry->memdesc.ops = &kgsl_userptr_ops;
+
+ ret = memdesc_sg_virt(&entry->memdesc, hostptr, size);
+ if (ret)
+ goto err;
return 0;
@@ -1725,7 +1785,7 @@
{
struct kgsl_mem_entry *entry = vma->vm_private_data;
- if (!entry->memdesc.ops->vmfault)
+ if (!entry->memdesc.ops || !entry->memdesc.ops->vmfault)
return VM_FAULT_SIGBUS;
return entry->memdesc.ops->vmfault(&entry->memdesc, vma, vmf);
@@ -1772,7 +1832,9 @@
if (entry == NULL)
return -EINVAL;
- if (!entry->memdesc.ops->vmflags || !entry->memdesc.ops->vmfault)
+ if (!entry->memdesc.ops ||
+ !entry->memdesc.ops->vmflags ||
+ !entry->memdesc.ops->vmfault)
return -EINVAL;
vma->vm_flags |= entry->memdesc.ops->vmflags(&entry->memdesc);
diff --git a/drivers/gpu/msm/kgsl.h b/drivers/gpu/msm/kgsl.h
index 8db2cb4..1480df4 100644
--- a/drivers/gpu/msm/kgsl.h
+++ b/drivers/gpu/msm/kgsl.h
@@ -115,6 +115,8 @@
unsigned int physaddr;
unsigned int size;
unsigned int priv;
+ struct scatterlist *sg;
+ unsigned int sglen;
struct kgsl_memdesc_ops *ops;
};
diff --git a/drivers/gpu/msm/kgsl_drm.c b/drivers/gpu/msm/kgsl_drm.c
index 202783b..cdf9dc4 100644
--- a/drivers/gpu/msm/kgsl_drm.c
+++ b/drivers/gpu/msm/kgsl_drm.c
@@ -293,7 +293,6 @@
}
priv->memdesc.size = obj->size * priv->bufcount;
- priv->memdesc.ops = &kgsl_contiguous_ops;
} else if (TYPE_IS_MEM(priv->type)) {
priv->memdesc.hostptr =
diff --git a/drivers/gpu/msm/kgsl_gpummu.c b/drivers/gpu/msm/kgsl_gpummu.c
index 383b910..fe5677e 100644
--- a/drivers/gpu/msm/kgsl_gpummu.c
+++ b/drivers/gpu/msm/kgsl_gpummu.c
@@ -659,68 +659,45 @@
return 0;
}
+#define SUPERPTE_IS_DIRTY(_p) \
+(((_p) & (GSL_PT_SUPER_PTE - 1)) == 0 && \
+GSL_TLBFLUSH_FILTER_ISDIRTY((_p) / GSL_PT_SUPER_PTE))
+
static int
kgsl_gpummu_map(void *mmu_specific_pt,
struct kgsl_memdesc *memdesc,
unsigned int protflags)
{
- int numpages;
- unsigned int pte, ptefirst, ptelast, physaddr;
- int flushtlb;
- unsigned int offset = 0;
+ unsigned int pte;
struct kgsl_gpummu_pt *gpummu_pt = mmu_specific_pt;
+ struct scatterlist *s;
+ int flushtlb = 0;
+ int i;
- if (!protflags ||
- protflags & ~(GSL_PT_PAGE_RV | GSL_PT_PAGE_WV)) {
- KGSL_CORE_ERR("Invalid protflags for "
- "kgsl_mmu_specific_map: %x", protflags);
- return -EINVAL;
- }
+ pte = kgsl_pt_entry_get(KGSL_PAGETABLE_BASE, memdesc->gpuaddr);
- numpages = (memdesc->size >> PAGE_SHIFT);
-
- ptefirst = kgsl_pt_entry_get(KGSL_PAGETABLE_BASE, memdesc->gpuaddr);
- ptelast = ptefirst + numpages;
-
- pte = ptefirst;
- flushtlb = 0;
-
- /* tlb needs to be flushed when the first and last pte are not at
- * superpte boundaries */
- if ((ptefirst & (GSL_PT_SUPER_PTE - 1)) != 0 ||
- ((ptelast + 1) & (GSL_PT_SUPER_PTE-1)) != 0)
+ /* Flush the TLB if the first PTE isn't at the superpte boundary */
+ if (pte & (GSL_PT_SUPER_PTE - 1))
flushtlb = 1;
- for (pte = ptefirst; pte < ptelast; pte++, offset += PAGE_SIZE) {
-#ifdef VERBOSE_DEBUG
- /* check if PTE exists */
- uint32_t val = kgsl_pt_map_get(gpummu_pt, pte);
- if (val != 0 && val != GSL_PT_PAGE_DIRTY) {
- KGSL_CORE_ERR("pt entry %x is already set with "
- "value %x for pagetable %p\n", pte, val, gpummu_pt);
- return -EINVAL;
- }
-#endif
- if ((pte & (GSL_PT_SUPER_PTE-1)) == 0)
- if (GSL_TLBFLUSH_FILTER_ISDIRTY(pte / GSL_PT_SUPER_PTE))
- flushtlb = 1;
- /* mark pte as in use */
+ for_each_sg(memdesc->sg, s, memdesc->sglen, i) {
+ unsigned int paddr = sg_phys(s);
+ unsigned int j;
- physaddr = memdesc->ops->physaddr(memdesc, offset);
- if (!physaddr) {
- KGSL_CORE_ERR("Failed to convert %x address to "
- "physical", (unsigned int)memdesc->hostptr + offset);
- kgsl_gpummu_unmap(mmu_specific_pt, memdesc);
- return -EFAULT;
+ /* Each sg entry might be multiple pages long */
+ for (j = paddr; j < paddr + s->length; pte++, j += PAGE_SIZE) {
+ if (SUPERPTE_IS_DIRTY(pte))
+ flushtlb = 1;
+ kgsl_pt_map_set(gpummu_pt, pte, j | protflags);
}
- kgsl_pt_map_set(gpummu_pt, pte, physaddr | protflags);
}
- /* Post all writes to the pagetable */
+ /* Flush the TLB if the last PTE isn't at the superpte boundary */
+ if ((pte + 1) & (GSL_PT_SUPER_PTE - 1))
+ flushtlb = 1;
+
wmb();
- /* Invalidate tlb only if current page table used by GPU is the
- * pagetable that we used to allocate */
if (flushtlb) {
/*set all devices as needing flushing*/
gpummu_pt->tlb_flags = UINT_MAX;
diff --git a/drivers/gpu/msm/kgsl_iommu.c b/drivers/gpu/msm/kgsl_iommu.c
index f9b9b4a..f43b96e 100644
--- a/drivers/gpu/msm/kgsl_iommu.c
+++ b/drivers/gpu/msm/kgsl_iommu.c
@@ -257,37 +257,33 @@
struct kgsl_memdesc *memdesc,
unsigned int protflags)
{
- int ret = 0;
- unsigned int physaddr;
+ int ret, i;
+ struct scatterlist *s;
unsigned int iommu_virt_addr;
- unsigned int offset = 0;
int map_order;
- struct iommu_domain *domain = (struct iommu_domain *)
- mmu_specific_pt;
+ struct iommu_domain *domain = mmu_specific_pt;
BUG_ON(NULL == domain);
map_order = get_order(SZ_4K);
- for (iommu_virt_addr = memdesc->gpuaddr;
- iommu_virt_addr < (memdesc->gpuaddr + memdesc->size);
- iommu_virt_addr += SZ_4K, offset += PAGE_SIZE) {
- physaddr = memdesc->ops->physaddr(memdesc, offset);
- if (!physaddr) {
- KGSL_CORE_ERR("Failed to convert %x address to "
- "physical\n", (unsigned int)memdesc->hostptr + offset);
- kgsl_iommu_unmap(mmu_specific_pt, memdesc);
- return -EFAULT;
- }
- ret = iommu_map(domain, iommu_virt_addr, physaddr,
+ iommu_virt_addr = memdesc->gpuaddr;
+
+ for_each_sg(memdesc->sg, s, memdesc->sglen, i) {
+ unsigned int paddr = sg_phys(s), j;
+ for (j = paddr; j < paddr + s->length; j += PAGE_SIZE) {
+ ret = iommu_map(domain, iommu_virt_addr, j,
map_order, MSM_IOMMU_ATTR_NONCACHED);
- if (ret) {
- KGSL_CORE_ERR("iommu_map(%p, %x, %x, %d, %d) "
- "failed with err: %d\n", domain,
- iommu_virt_addr, physaddr, map_order,
- MSM_IOMMU_ATTR_NONCACHED, ret);
- kgsl_iommu_unmap(mmu_specific_pt, memdesc);
- return ret;
+ if (ret) {
+ KGSL_CORE_ERR("iommu_map(%p, %x, %x, %d, %d) "
+ "failed with err: %d\n", domain,
+ iommu_virt_addr, j, map_order,
+ MSM_IOMMU_ATTR_NONCACHED, ret);
+ kgsl_iommu_unmap(mmu_specific_pt, memdesc);
+ return ret;
+ }
+
+ iommu_virt_addr += SZ_4K;
}
}
diff --git a/drivers/gpu/msm/kgsl_mmu.c b/drivers/gpu/msm/kgsl_mmu.c
index 7eec9e5..1879666 100644
--- a/drivers/gpu/msm/kgsl_mmu.c
+++ b/drivers/gpu/msm/kgsl_mmu.c
@@ -525,37 +525,6 @@
*/
}
-unsigned int kgsl_virtaddr_to_physaddr(void *virtaddr)
-{
- unsigned int physaddr = 0;
- pgd_t *pgd_ptr = NULL;
- pmd_t *pmd_ptr = NULL;
- pte_t *pte_ptr = NULL, pte;
-
- pgd_ptr = pgd_offset(current->mm, (unsigned long) virtaddr);
- if (pgd_none(*pgd) || pgd_bad(*pgd)) {
- KGSL_CORE_ERR("Invalid pgd entry\n");
- return 0;
- }
-
- pmd_ptr = pmd_offset(pgd_ptr, (unsigned long) virtaddr);
- if (pmd_none(*pmd_ptr) || pmd_bad(*pmd_ptr)) {
- KGSL_CORE_ERR("Invalid pmd entry\n");
- return 0;
- }
-
- pte_ptr = pte_offset_map(pmd_ptr, (unsigned long) virtaddr);
- if (!pte_ptr) {
- KGSL_CORE_ERR("pt_offset_map failed\n");
- return 0;
- }
- pte = *pte_ptr;
- physaddr = pte_pfn(pte);
- pte_unmap(pte_ptr);
- physaddr <<= PAGE_SHIFT;
- return physaddr;
-}
-
int
kgsl_mmu_map(struct kgsl_pagetable *pagetable,
struct kgsl_memdesc *memdesc,
diff --git a/drivers/gpu/msm/kgsl_pwrscale_idlestats.c b/drivers/gpu/msm/kgsl_pwrscale_idlestats.c
index 923b4fe..d5fa84e 100644
--- a/drivers/gpu/msm/kgsl_pwrscale_idlestats.c
+++ b/drivers/gpu/msm/kgsl_pwrscale_idlestats.c
@@ -14,18 +14,52 @@
#include <linux/slab.h>
#include <linux/timer.h>
#include <linux/idle_stats_device.h>
+#include <linux/cpufreq.h>
+#include <linux/notifier.h>
+#include <linux/cpumask.h>
+#include <linux/tick.h>
#include "kgsl.h"
#include "kgsl_pwrscale.h"
#include "kgsl_device.h"
+#define MAX_CORES 4
+struct _cpu_info {
+ spinlock_t lock;
+ struct notifier_block cpu_nb;
+ u64 start[MAX_CORES];
+ u64 end[MAX_CORES];
+ int curr_freq[MAX_CORES];
+ int max_freq[MAX_CORES];
+};
+
struct idlestats_priv {
char name[32];
struct msm_idle_stats_device idledev;
struct kgsl_device *device;
struct msm_idle_pulse pulse;
+ struct _cpu_info cpu_info;
};
+static int idlestats_cpufreq_notifier(
+ struct notifier_block *nb,
+ unsigned long val, void *data)
+{
+ struct _cpu_info *cpu = container_of(nb,
+ struct _cpu_info, cpu_nb);
+ struct cpufreq_freqs *freq = data;
+
+ if (val != CPUFREQ_POSTCHANGE)
+ return 0;
+
+ spin_lock(&cpu->lock);
+ if (freq->cpu < num_possible_cpus())
+ cpu->curr_freq[freq->cpu] = freq->new / 1000;
+ spin_unlock(&cpu->lock);
+
+ return 0;
+}
+
static void idlestats_get_sample(struct msm_idle_stats_device *idledev,
struct msm_idle_pulse *pulse)
{
@@ -55,14 +89,37 @@
struct kgsl_pwrscale *pwrscale)
{
struct idlestats_priv *priv = pwrscale->priv;
- if (priv->pulse.busy_start_time != 0)
+ int i, busy, nr_cpu = 1;
+
+ if (priv->pulse.busy_start_time != 0) {
+ priv->pulse.wait_interval = 0;
+ /* Calculate the total CPU busy time for this GPU pulse */
+ for (i = 0; i < num_possible_cpus(); i++) {
+ spin_lock(&priv->cpu_info.lock);
+ if (cpu_online(i)) {
+ priv->cpu_info.end[i] =
+ (u64)ktime_to_us(ktime_get()) -
+ get_cpu_idle_time_us(i, NULL);
+ busy = priv->cpu_info.end[i] -
+ priv->cpu_info.start[i];
+ /* Normalize the busy time by frequency */
+ busy = priv->cpu_info.curr_freq[i] *
+ (busy / priv->cpu_info.max_freq[i]);
+ priv->pulse.wait_interval += busy;
+ nr_cpu++;
+ }
+ spin_unlock(&priv->cpu_info.lock);
+ }
+ priv->pulse.wait_interval /= nr_cpu;
msm_idle_stats_idle_end(&priv->idledev, &priv->pulse);
+ }
priv->pulse.busy_start_time = ktime_to_us(ktime_get());
}
static void idlestats_idle(struct kgsl_device *device,
struct kgsl_pwrscale *pwrscale)
{
+ int i, nr_cpu;
struct kgsl_power_stats stats;
struct idlestats_priv *priv = pwrscale->priv;
@@ -78,7 +135,13 @@
}
priv->pulse.busy_interval = stats.busy_time;
- priv->pulse.wait_interval = 0;
+ nr_cpu = num_possible_cpus();
+ for (i = 0; i < nr_cpu; i++)
+ if (cpu_online(i))
+ priv->cpu_info.start[i] =
+ (u64)ktime_to_us(ktime_get()) -
+ get_cpu_idle_time_us(i, NULL);
+
msm_idle_stats_idle_start(&priv->idledev);
}
@@ -93,7 +156,8 @@
struct kgsl_pwrscale *pwrscale)
{
struct idlestats_priv *priv;
- int ret;
+ struct cpufreq_policy cpu_policy;
+ int ret, i;
priv = pwrscale->priv = kzalloc(sizeof(struct idlestats_priv),
GFP_KERNEL);
@@ -108,8 +172,21 @@
priv->idledev.name = (const char *) priv->name;
priv->idledev.get_sample = idlestats_get_sample;
+ spin_lock_init(&priv->cpu_info.lock);
+ priv->cpu_info.cpu_nb.notifier_call =
+ idlestats_cpufreq_notifier;
+ ret = cpufreq_register_notifier(&priv->cpu_info.cpu_nb,
+ CPUFREQ_TRANSITION_NOTIFIER);
+ if (ret)
+ goto err;
+ for (i = 0; i < num_possible_cpus(); i++) {
+ cpufreq_frequency_table_cpuinfo(&cpu_policy,
+ cpufreq_frequency_get_table(i));
+ priv->cpu_info.max_freq[i] = cpu_policy.max / 1000;
+ priv->cpu_info.curr_freq[i] = cpu_policy.max / 1000;
+ }
ret = msm_idle_stats_register_device(&priv->idledev);
-
+err:
if (ret) {
kfree(pwrscale->priv);
pwrscale->priv = NULL;
@@ -126,6 +203,8 @@
if (pwrscale->priv == NULL)
return;
+ cpufreq_unregister_notifier(&priv->cpu_info.cpu_nb,
+ CPUFREQ_TRANSITION_NOTIFIER);
msm_idle_stats_deregister_device(&priv->idledev);
kfree(pwrscale->priv);
diff --git a/drivers/gpu/msm/kgsl_sharedmem.c b/drivers/gpu/msm/kgsl_sharedmem.c
index 09070e4..8f75daa 100644
--- a/drivers/gpu/msm/kgsl_sharedmem.c
+++ b/drivers/gpu/msm/kgsl_sharedmem.c
@@ -207,28 +207,21 @@
break;
}
}
-#endif
-static unsigned long kgsl_vmalloc_physaddr(struct kgsl_memdesc *memdesc,
- unsigned int offset)
+static void outer_cache_range_op_sg(struct scatterlist *sg, int sglen, int op)
{
- unsigned int addr;
+ struct scatterlist *s;
+ int i;
- if (offset > memdesc->size)
- return 0;
-
- addr = vmalloc_to_pfn(memdesc->hostptr + offset);
- return addr << PAGE_SHIFT;
+ for_each_sg(sg, s, sglen, i) {
+ unsigned int paddr = sg_phys(s);
+ _outer_cache_range_op(op, paddr, s->length);
+ }
}
-#ifdef CONFIG_OUTER_CACHE
-static void kgsl_vmalloc_outer_cache(struct kgsl_memdesc *memdesc, int op)
+#else
+static void outer_cache_range_op_sg(struct scatterlist *sg, int sglen, int op)
{
- void *vaddr = memdesc->hostptr;
- for (; vaddr < (memdesc->hostptr + memdesc->size); vaddr += PAGE_SIZE) {
- unsigned long paddr = page_to_phys(vmalloc_to_page(vaddr));
- _outer_cache_range_op(op, paddr, PAGE_SIZE);
- }
}
#endif
@@ -306,88 +299,24 @@
memdesc->hostptr, memdesc->physaddr);
}
-static unsigned long kgsl_contiguous_physaddr(struct kgsl_memdesc *memdesc,
- unsigned int offset)
-{
- if (offset > memdesc->size)
- return 0;
-
- return memdesc->physaddr + offset;
-}
-
-#ifdef CONFIG_OUTER_CACHE
-static void kgsl_contiguous_outer_cache(struct kgsl_memdesc *memdesc, int op)
-{
- _outer_cache_range_op(op, memdesc->physaddr, memdesc->size);
-}
-#endif
-
-#ifdef CONFIG_OUTER_CACHE
-static void kgsl_userptr_outer_cache(struct kgsl_memdesc *memdesc, int op)
-{
- void *vaddr = memdesc->hostptr;
- for (; vaddr < (memdesc->hostptr + memdesc->size); vaddr += PAGE_SIZE) {
- unsigned long paddr = kgsl_virtaddr_to_physaddr(vaddr);
- if (paddr)
- _outer_cache_range_op(op, paddr, PAGE_SIZE);
- }
-}
-#endif
-
-static unsigned long kgsl_userptr_physaddr(struct kgsl_memdesc *memdesc,
- unsigned int offset)
-{
- return kgsl_virtaddr_to_physaddr(memdesc->hostptr + offset);
-}
-
/* Global - also used by kgsl_drm.c */
struct kgsl_memdesc_ops kgsl_vmalloc_ops = {
- .physaddr = kgsl_vmalloc_physaddr,
.free = kgsl_vmalloc_free,
.vmflags = kgsl_vmalloc_vmflags,
.vmfault = kgsl_vmalloc_vmfault,
-#ifdef CONFIG_OUTER_CACHE
- .outer_cache = kgsl_vmalloc_outer_cache,
-#endif
};
EXPORT_SYMBOL(kgsl_vmalloc_ops);
static struct kgsl_memdesc_ops kgsl_ebimem_ops = {
- .physaddr = kgsl_contiguous_physaddr,
.free = kgsl_ebimem_free,
.vmflags = kgsl_contiguous_vmflags,
.vmfault = kgsl_contiguous_vmfault,
-#ifdef CONFIG_OUTER_CACHE
- .outer_cache = kgsl_contiguous_outer_cache,
-#endif
};
static struct kgsl_memdesc_ops kgsl_coherent_ops = {
- .physaddr = kgsl_contiguous_physaddr,
.free = kgsl_coherent_free,
-#ifdef CONFIG_OUTER_CACHE
- .outer_cache = kgsl_contiguous_outer_cache,
-#endif
};
-/* Global - also used by kgsl.c and kgsl_drm.c */
-struct kgsl_memdesc_ops kgsl_contiguous_ops = {
- .physaddr = kgsl_contiguous_physaddr,
-#ifdef CONFIG_OUTER_CACHE
- .outer_cache = kgsl_contiguous_outer_cache
-#endif
-};
-EXPORT_SYMBOL(kgsl_contiguous_ops);
-
-/* Global - also used by kgsl.c */
-struct kgsl_memdesc_ops kgsl_userptr_ops = {
- .physaddr = kgsl_userptr_physaddr,
-#ifdef CONFIG_OUTER_CACHE
- .outer_cache = kgsl_userptr_outer_cache,
-#endif
-};
-EXPORT_SYMBOL(kgsl_userptr_ops);
-
void kgsl_cache_range_op(struct kgsl_memdesc *memdesc, int op)
{
void *addr = memdesc->hostptr;
@@ -405,8 +334,7 @@
break;
}
- if (memdesc->ops->outer_cache)
- memdesc->ops->outer_cache(memdesc, op);
+ outer_cache_range_op_sg(memdesc->sg, memdesc->sglen, op);
}
EXPORT_SYMBOL(kgsl_cache_range_op);
@@ -415,7 +343,9 @@
struct kgsl_pagetable *pagetable,
void *ptr, size_t size, unsigned int protflags)
{
- int result;
+ int order, ret = 0;
+ int sglen = PAGE_ALIGN(size) / PAGE_SIZE;
+ int i;
memdesc->size = size;
memdesc->pagetable = pagetable;
@@ -423,25 +353,44 @@
memdesc->ops = &kgsl_vmalloc_ops;
memdesc->hostptr = (void *) ptr;
- kgsl_cache_range_op(memdesc, KGSL_CACHE_OP_INV);
-
- result = kgsl_mmu_map(pagetable, memdesc, protflags);
-
- if (result) {
- kgsl_sharedmem_free(memdesc);
- } else {
- int order;
-
- KGSL_STATS_ADD(size, kgsl_driver.stats.vmalloc,
- kgsl_driver.stats.vmalloc_max);
-
- order = get_order(size);
-
- if (order < 16)
- kgsl_driver.stats.histogram[order]++;
+ memdesc->sg = kmalloc(sglen * sizeof(struct scatterlist), GFP_KERNEL);
+ if (memdesc->sg == NULL) {
+ ret = -ENOMEM;
+ goto done;
}
- return result;
+ memdesc->sglen = sglen;
+ sg_init_table(memdesc->sg, sglen);
+
+ for (i = 0; i < memdesc->sglen; i++, ptr += PAGE_SIZE) {
+ struct page *page = vmalloc_to_page(ptr);
+ if (!page) {
+ ret = -EINVAL;
+ goto done;
+ }
+ sg_set_page(&memdesc->sg[i], page, PAGE_SIZE, 0);
+ }
+
+ kgsl_cache_range_op(memdesc, KGSL_CACHE_OP_INV);
+
+ ret = kgsl_mmu_map(pagetable, memdesc, protflags);
+
+ if (ret)
+ goto done;
+
+ KGSL_STATS_ADD(size, kgsl_driver.stats.vmalloc,
+ kgsl_driver.stats.vmalloc_max);
+
+ order = get_order(size);
+
+ if (order < 16)
+ kgsl_driver.stats.histogram[order]++;
+
+done:
+ if (ret)
+ kgsl_sharedmem_free(memdesc);
+
+ return ret;
}
int
@@ -494,24 +443,35 @@
int
kgsl_sharedmem_alloc_coherent(struct kgsl_memdesc *memdesc, size_t size)
{
+ int result = 0;
+
size = ALIGN(size, PAGE_SIZE);
+ memdesc->size = size;
+ memdesc->ops = &kgsl_coherent_ops;
+
memdesc->hostptr = dma_alloc_coherent(NULL, size, &memdesc->physaddr,
GFP_KERNEL);
if (memdesc->hostptr == NULL) {
KGSL_CORE_ERR("dma_alloc_coherent(%d) failed\n", size);
- return -ENOMEM;
+ result = -ENOMEM;
+ goto err;
}
- memdesc->size = size;
- memdesc->ops = &kgsl_coherent_ops;
+ result = memdesc_sg_phys(memdesc, memdesc->physaddr, size);
+ if (result)
+ goto err;
/* Record statistics */
KGSL_STATS_ADD(size, kgsl_driver.stats.coherent,
kgsl_driver.stats.coherent_max);
- return 0;
+err:
+ if (result)
+ kgsl_sharedmem_free(memdesc);
+
+ return result;
}
EXPORT_SYMBOL(kgsl_sharedmem_alloc_coherent);
@@ -523,9 +483,11 @@
if (memdesc->gpuaddr)
kgsl_mmu_unmap(memdesc->pagetable, memdesc);
- if (memdesc->ops->free)
+ if (memdesc->ops && memdesc->ops->free)
memdesc->ops->free(memdesc);
+ kfree(memdesc->sg);
+
memset(memdesc, 0, sizeof(*memdesc));
}
EXPORT_SYMBOL(kgsl_sharedmem_free);
@@ -534,8 +496,11 @@
_kgsl_sharedmem_ebimem(struct kgsl_memdesc *memdesc,
struct kgsl_pagetable *pagetable, size_t size)
{
- int result;
+ int result = 0;
+ memdesc->size = size;
+ memdesc->pagetable = pagetable;
+ memdesc->ops = &kgsl_ebimem_ops;
memdesc->physaddr = allocate_contiguous_ebi_nomap(size, SZ_8K);
if (memdesc->physaddr == 0) {
@@ -544,19 +509,24 @@
return -ENOMEM;
}
- memdesc->size = size;
- memdesc->pagetable = pagetable;
- memdesc->ops = &kgsl_ebimem_ops;
+ result = memdesc_sg_phys(memdesc, memdesc->physaddr, size);
+
+ if (result)
+ goto err;
result = kgsl_mmu_map(pagetable, memdesc,
GSL_PT_PAGE_RV | GSL_PT_PAGE_WV);
if (result)
- kgsl_sharedmem_free(memdesc);
+ goto err;
KGSL_STATS_ADD(size, kgsl_driver.stats.coherent,
kgsl_driver.stats.coherent_max);
+err:
+ if (result)
+ kgsl_sharedmem_free(memdesc);
+
return result;
}
diff --git a/drivers/gpu/msm/kgsl_sharedmem.h b/drivers/gpu/msm/kgsl_sharedmem.h
index 9e57e78..a9abcf9 100644
--- a/drivers/gpu/msm/kgsl_sharedmem.h
+++ b/drivers/gpu/msm/kgsl_sharedmem.h
@@ -13,6 +13,7 @@
#ifndef __KGSL_SHAREDMEM_H
#define __KGSL_SHAREDMEM_H
+#include <linux/slab.h>
#include <linux/dma-mapping.h>
struct kgsl_device;
@@ -26,8 +27,6 @@
#define KGSL_MEMFLAGS_CACHED 0x00000001
struct kgsl_memdesc_ops {
- unsigned long (*physaddr)(struct kgsl_memdesc *, unsigned int);
- void (*outer_cache)(struct kgsl_memdesc *, int);
int (*vmflags)(struct kgsl_memdesc *);
int (*vmfault)(struct kgsl_memdesc *, struct vm_area_struct *,
struct vm_fault *);
@@ -35,8 +34,6 @@
};
extern struct kgsl_memdesc_ops kgsl_vmalloc_ops;
-extern struct kgsl_memdesc_ops kgsl_contiguous_ops;
-extern struct kgsl_memdesc_ops kgsl_userptr_ops;
int kgsl_sharedmem_vmalloc(struct kgsl_memdesc *memdesc,
struct kgsl_pagetable *pagetable, size_t size);
@@ -78,6 +75,22 @@
void kgsl_sharedmem_uninit_sysfs(void);
static inline int
+memdesc_sg_phys(struct kgsl_memdesc *memdesc,
+ unsigned int physaddr, unsigned int size)
+{
+ struct page *page = phys_to_page(physaddr);
+
+ memdesc->sg = kmalloc(sizeof(struct scatterlist) * 1, GFP_KERNEL);
+ if (memdesc->sg == NULL)
+ return -ENOMEM;
+
+ memdesc->sglen = 1;
+ sg_init_table(memdesc->sg, 1);
+ sg_set_page(&memdesc->sg[0], page, size, 0);
+ return 0;
+}
+
+static inline int
kgsl_allocate(struct kgsl_memdesc *memdesc,
struct kgsl_pagetable *pagetable, size_t size)
{
diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index f9d671e..f3cd0ad 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -797,6 +797,15 @@
The driver supports reading the HKADC, XOADC and support to set and receive
temperature threshold notifications using the Battery temperature module.
+config SENSORS_PM8XXX_ADC
+ tristate "Support for Qualcomm PM8XXX ADC"
+ depends on MFD_PM8018_CORE
+ help
+ This is the ADC arbiter driver for Qualcomm PM8XXX Chip.
+
+ The driver supports reading the HKADC, XOADC and support to set and receive
+ temperature threshold notifications using the Battery temperature module.
+
config SENSORS_PC87360
tristate "National Semiconductor PC87360 family"
select HWMON_VID
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index c25ffcb..10d0699 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -121,6 +121,7 @@
obj-$(CONFIG_SENSORS_WPCE775X) += wpce775x.o
obj-$(CONFIG_SENSORS_MSM_ADC) += msm_adc.o m_adcproc.o
obj-$(CONFIG_SENSORS_PM8921_ADC) += pm8921-adc.o msmproc_adc.o
+obj-$(CONFIG_SENSORS_PM8XXX_ADC) += pm8xxx-adc.o pm8xxx-adc-scale.o
# PMBus drivers
obj-$(CONFIG_PMBUS) += pmbus_core.o
diff --git a/drivers/hwmon/pm8xxx-adc-scale.c b/drivers/hwmon/pm8xxx-adc-scale.c
new file mode 100644
index 0000000..40ade69
--- /dev/null
+++ b/drivers/hwmon/pm8xxx-adc-scale.c
@@ -0,0 +1,620 @@
+/*
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/module.h>
+#include <linux/mfd/pm8xxx/pm8xxx-adc.h>
+#define KELVINMIL_DEGMIL 273160
+
+static const struct pm8xxx_adc_map_pt adcmap_batttherm[] = {
+ {41001, -30},
+ {40017, -20},
+ {38721, -10},
+ {37186, 0},
+ {35554, 10},
+ {33980, 20},
+ {33253, 25},
+ {32580, 30},
+ {31412, 40},
+ {30481, 50},
+ {29759, 60},
+ {29209, 70},
+ {28794, 80}
+};
+
+static const struct pm8xxx_adc_map_pt adcmap_btm_threshold[] = {
+ {-30, 41001},
+ {-20, 40017},
+ {-10, 38721},
+ {0, 37186},
+ {10, 35554},
+ {11, 35392},
+ {12, 35230},
+ {13, 35070},
+ {14, 34910},
+ {15, 34751},
+ {16, 34594},
+ {17, 34438},
+ {18, 34284},
+ {19, 34131},
+ {20, 33980},
+ {21, 33830},
+ {22, 33683},
+ {23, 33538},
+ {24, 33394},
+ {25, 33253},
+ {26, 33114},
+ {27, 32977},
+ {28, 32842},
+ {29, 32710},
+ {30, 32580},
+ {31, 32452},
+ {32, 32327},
+ {33, 32204},
+ {34, 32084},
+ {35, 31966},
+ {36, 31850},
+ {37, 31737},
+ {38, 31627},
+ {39, 31518},
+ {40, 31412},
+ {41, 31309},
+ {42, 31208},
+ {43, 31109},
+ {44, 31013},
+ {45, 30918},
+ {46, 30827},
+ {47, 30737},
+ {48, 30649},
+ {49, 30564},
+ {50, 30481},
+ {51, 30400},
+ {52, 30321},
+ {53, 30244},
+ {54, 30169},
+ {55, 30096},
+ {56, 30025},
+ {57, 29956},
+ {58, 29889},
+ {59, 29823},
+ {60, 29759},
+ {61, 29697},
+ {62, 29637},
+ {63, 29578},
+ {64, 29521},
+ {65, 29465},
+ {66, 29411},
+ {67, 29359},
+ {68, 29308},
+ {69, 29258},
+ {70, 29209},
+ {71, 29162},
+ {72, 29117},
+ {73, 29072},
+ {74, 29029},
+ {75, 28987},
+ {76, 28946},
+ {77, 28906},
+ {78, 28868},
+ {79, 28830},
+ {80, 28794}
+};
+
+static const struct pm8xxx_adc_map_pt adcmap_pa_therm[] = {
+ {41350, -30},
+ {41282, -29},
+ {41211, -28},
+ {41137, -27},
+ {41060, -26},
+ {40980, -25},
+ {40897, -24},
+ {40811, -23},
+ {40721, -22},
+ {40629, -21},
+ {40533, -20},
+ {40434, -19},
+ {40331, -18},
+ {40226, -17},
+ {40116, -16},
+ {40004, -15},
+ {39888, -14},
+ {39769, -13},
+ {39647, -12},
+ {39521, -11},
+ {39392, -10},
+ {39260, -9},
+ {39124, -8},
+ {38986, -7},
+ {38845, -6},
+ {38700, -5},
+ {38553, -4},
+ {38403, -3},
+ {38250, -2},
+ {38094, -1},
+ {37936, 0},
+ {37776, 1},
+ {37613, 2},
+ {37448, 3},
+ {37281, 4},
+ {37112, 5},
+ {36942, 6},
+ {36770, 7},
+ {36596, 8},
+ {36421, 9},
+ {36245, 10},
+ {36068, 11},
+ {35890, 12},
+ {35712, 13},
+ {35532, 14},
+ {35353, 15},
+ {35173, 16},
+ {34993, 17},
+ {34813, 18},
+ {34634, 19},
+ {34455, 20},
+ {34276, 21},
+ {34098, 22},
+ {33921, 23},
+ {33745, 24},
+ {33569, 25},
+ {33395, 26},
+ {33223, 27},
+ {33051, 28},
+ {32881, 29},
+ {32713, 30},
+ {32547, 31},
+ {32382, 32},
+ {32219, 33},
+ {32058, 34},
+ {31899, 35},
+ {31743, 36},
+ {31588, 37},
+ {31436, 38},
+ {31285, 39},
+ {31138, 40},
+ {30992, 41},
+ {30849, 42},
+ {30708, 43},
+ {30570, 44},
+ {30434, 45},
+ {30300, 46},
+ {30169, 47},
+ {30041, 48},
+ {29915, 49},
+ {29791, 50},
+ {29670, 51},
+ {29551, 52},
+ {29435, 53},
+ {29321, 54},
+ {29210, 55},
+ {29101, 56},
+ {28994, 57},
+ {28890, 58},
+ {28788, 59},
+ {28688, 60},
+ {28590, 61},
+ {28495, 62},
+ {28402, 63},
+ {28311, 64},
+ {28222, 65},
+ {28136, 66},
+ {28051, 67},
+ {27968, 68},
+ {27888, 69},
+ {27809, 70},
+ {27732, 71},
+ {27658, 72},
+ {27584, 73},
+ {27513, 74},
+ {27444, 75},
+ {27376, 76},
+ {27310, 77},
+ {27245, 78},
+ {27183, 79},
+ {27121, 80},
+ {27062, 81},
+ {27004, 82},
+ {26947, 83},
+ {26892, 84},
+ {26838, 85},
+ {26785, 86},
+ {26734, 87},
+ {26684, 88},
+ {26636, 89},
+ {26588, 90}
+};
+
+static const struct pm8xxx_adc_map_pt adcmap_ntcg_104ef_104fb[] = {
+ {696483, -40960},
+ {649148, -39936},
+ {605368, -38912},
+ {564809, -37888},
+ {527215, -36864},
+ {492322, -35840},
+ {460007, -34816},
+ {429982, -33792},
+ {402099, -32768},
+ {376192, -31744},
+ {352075, -30720},
+ {329714, -29696},
+ {308876, -28672},
+ {289480, -27648},
+ {271417, -26624},
+ {254574, -25600},
+ {238903, -24576},
+ {224276, -23552},
+ {210631, -22528},
+ {197896, -21504},
+ {186007, -20480},
+ {174899, -19456},
+ {164521, -18432},
+ {154818, -17408},
+ {145744, -16384},
+ {137265, -15360},
+ {129307, -14336},
+ {121866, -13312},
+ {114896, -12288},
+ {108365, -11264},
+ {102252, -10240},
+ {96499, -9216},
+ {91111, -8192},
+ {86055, -7168},
+ {81308, -6144},
+ {76857, -5120},
+ {72660, -4096},
+ {68722, -3072},
+ {65020, -2048},
+ {61538, -1024},
+ {58261, 0},
+ {55177, 1024},
+ {52274, 2048},
+ {49538, 3072},
+ {46962, 4096},
+ {44531, 5120},
+ {42243, 6144},
+ {40083, 7168},
+ {38045, 8192},
+ {36122, 9216},
+ {34308, 10240},
+ {32592, 11264},
+ {30972, 12288},
+ {29442, 13312},
+ {27995, 14336},
+ {26624, 15360},
+ {25333, 16384},
+ {24109, 17408},
+ {22951, 18432},
+ {21854, 19456},
+ {20807, 20480},
+ {19831, 21504},
+ {18899, 22528},
+ {18016, 23552},
+ {17178, 24576},
+ {16384, 25600},
+ {15631, 26624},
+ {14916, 27648},
+ {14237, 28672},
+ {13593, 29696},
+ {12976, 30720},
+ {12400, 31744},
+ {11848, 32768},
+ {11324, 33792},
+ {10825, 34816},
+ {10354, 35840},
+ {9900, 36864},
+ {9471, 37888},
+ {9062, 38912},
+ {8674, 39936},
+ {8306, 40960},
+ {7951, 41984},
+ {7616, 43008},
+ {7296, 44032},
+ {6991, 45056},
+ {6701, 46080},
+ {6424, 47104},
+ {6160, 48128},
+ {5908, 49152},
+ {5667, 50176},
+ {5439, 51200},
+ {5219, 52224},
+ {5010, 53248},
+ {4810, 54272},
+ {4619, 55296},
+ {4440, 56320},
+ {4263, 57344},
+ {4097, 58368},
+ {3938, 59392},
+ {3785, 60416},
+ {3637, 61440},
+ {3501, 62464},
+ {3368, 63488},
+ {3240, 64512},
+ {3118, 65536},
+ {2998, 66560},
+ {2889, 67584},
+ {2782, 68608},
+ {2680, 69632},
+ {2581, 70656},
+ {2490, 71680},
+ {2397, 72704},
+ {2310, 73728},
+ {2227, 74752},
+ {2147, 75776},
+ {2064, 76800},
+ {1998, 77824},
+ {1927, 78848},
+ {1860, 79872},
+ {1795, 80896},
+ {1736, 81920},
+ {1673, 82944},
+ {1615, 83968},
+ {1560, 84992},
+ {1507, 86016},
+ {1456, 87040},
+ {1407, 88064},
+ {1360, 89088},
+ {1314, 90112},
+ {1271, 91136},
+ {1228, 92160},
+ {1189, 93184},
+ {1150, 94208},
+ {1112, 95232},
+ {1076, 96256},
+ {1042, 97280},
+ {1008, 98304},
+ {976, 99328},
+ {945, 100352},
+ {915, 101376},
+ {886, 102400},
+ {859, 103424},
+ {832, 104448},
+ {807, 105472},
+ {782, 106496},
+ {756, 107520},
+ {735, 108544},
+ {712, 109568},
+ {691, 110592},
+ {670, 111616},
+ {650, 112640},
+ {631, 113664},
+ {612, 114688},
+ {594, 115712},
+ {577, 116736},
+ {560, 117760},
+ {544, 118784},
+ {528, 119808},
+ {513, 120832},
+ {498, 121856},
+ {483, 122880},
+ {470, 123904},
+ {457, 124928},
+ {444, 125952},
+ {431, 126976},
+ {419, 128000}
+};
+
+static int32_t pm8xxx_adc_map_linear(const struct pm8xxx_adc_map_pt *pts,
+ uint32_t tablesize, int32_t input, int64_t *output)
+{
+ bool descending = 1;
+ uint32_t i = 0;
+
+ if ((pts == NULL) || (output == NULL))
+ return -EINVAL;
+
+ /* Check if table is descending or ascending */
+ if (tablesize > 1) {
+ if (pts[0].x < pts[1].x)
+ descending = 0;
+ }
+
+ while (i < tablesize) {
+ if ((descending == 1) && (pts[i].x < input)) {
+ /* table entry is less than measured
+ value and table is descending, stop */
+ break;
+ } else if ((descending == 0) &&
+ (pts[i].x > input)) {
+ /* table entry is greater than measured
+ value and table is ascending, stop */
+ break;
+ } else {
+ i++;
+ }
+ }
+
+ if (i == 0)
+ *output = pts[0].y;
+ else if (i == tablesize)
+ *output = pts[tablesize-1].y;
+ else {
+ /* result is between search_index and search_index-1 */
+ /* interpolate linearly */
+ *output = (((int32_t) ((pts[i].y - pts[i-1].y)*
+ (input - pts[i-1].x))/
+ (pts[i].x - pts[i-1].x))+
+ pts[i-1].y);
+ }
+
+ return 0;
+}
+
+int32_t pm8xxx_adc_scale_default(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_properties,
+ const struct pm8xxx_adc_chan_properties *chan_properties,
+ struct pm8xxx_adc_chan_result *adc_chan_result)
+{
+ bool negative_rawfromoffset = 0;
+ int32_t rawfromoffset = 0;
+
+ if (!chan_properties || !chan_properties->offset_gain_numerator ||
+ !chan_properties->offset_gain_denominator || !adc_properties
+ || !adc_chan_result)
+ return -EINVAL;
+
+ rawfromoffset = adc_code -
+ chan_properties->adc_graph[ADC_CALIB_ABSOLUTE].offset;
+
+ adc_chan_result->adc_code = adc_code;
+ if (rawfromoffset < 0) {
+ if (adc_properties->bipolar) {
+ rawfromoffset = -rawfromoffset;
+ negative_rawfromoffset = 1;
+ } else {
+ rawfromoffset = 0;
+ }
+ }
+
+ if (rawfromoffset >= 1 << adc_properties->bitresolution)
+ rawfromoffset = (1 << adc_properties->bitresolution) - 1;
+
+ adc_chan_result->measurement = (int64_t)rawfromoffset *
+ chan_properties->adc_graph[ADC_CALIB_ABSOLUTE].dx *
+ chan_properties->offset_gain_denominator;
+
+ /* do_div only perform positive integer division! */
+ do_div(adc_chan_result->measurement,
+ chan_properties->adc_graph[ADC_CALIB_ABSOLUTE].dy *
+ chan_properties->offset_gain_numerator);
+
+ if (negative_rawfromoffset)
+ adc_chan_result->measurement = -adc_chan_result->measurement;
+
+ /* Note: adc_chan_result->measurement is in the unit of
+ * adc_properties.adc_reference. For generic channel processing,
+ * channel measurement is a scale/ratio relative to the adc
+ * reference input */
+ adc_chan_result->physical = (int32_t) adc_chan_result->measurement;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(pm8xxx_adc_scale_default);
+
+int32_t pm8xxx_adc_scale_batt_therm(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_properties,
+ const struct pm8xxx_adc_chan_properties *chan_properties,
+ struct pm8xxx_adc_chan_result *adc_chan_result)
+{
+ /* Note: adc_chan_result->measurement is in the unit of
+ adc_properties.adc_reference */
+ adc_chan_result->measurement = adc_code;
+ /* convert mV ---> degC using the table */
+ return pm8xxx_adc_map_linear(
+ adcmap_batttherm,
+ ARRAY_SIZE(adcmap_batttherm),
+ adc_code,
+ &adc_chan_result->physical);
+}
+EXPORT_SYMBOL_GPL(pm8xxx_adc_scale_batt_therm);
+
+int32_t pm8xxx_adc_scale_pa_therm(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_properties,
+ const struct pm8xxx_adc_chan_properties *chan_properties,
+ struct pm8xxx_adc_chan_result *adc_chan_result)
+{
+ /* Note: adc_chan_result->measurement is in the unit of
+ adc_properties.adc_reference */
+ adc_chan_result->measurement = adc_code;
+ /* convert mV ---> degC using the table */
+ return pm8xxx_adc_map_linear(
+ adcmap_pa_therm,
+ ARRAY_SIZE(adcmap_pa_therm),
+ adc_code,
+ &adc_chan_result->physical);
+}
+EXPORT_SYMBOL_GPL(pm8xxx_adc_scale_pa_therm);
+
+int32_t pm8xxx_adc_scale_pmic_therm(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_properties,
+ const struct pm8xxx_adc_chan_properties *chan_properties,
+ struct pm8xxx_adc_chan_result *adc_chan_result)
+{
+ int32_t rawfromoffset;
+
+ if (!chan_properties || !chan_properties->offset_gain_numerator ||
+ !chan_properties->offset_gain_denominator || !adc_properties
+ || !adc_chan_result)
+ return -EINVAL;
+
+ adc_chan_result->adc_code = adc_code;
+ rawfromoffset = adc_code -
+ chan_properties->adc_graph[ADC_CALIB_ABSOLUTE].offset;
+ if (rawfromoffset > 0) {
+ if (rawfromoffset >= 1 << adc_properties->bitresolution)
+ rawfromoffset = (1 << adc_properties->bitresolution)
+ - 1;
+ /* 2mV/K */
+ adc_chan_result->measurement = (int64_t)rawfromoffset*
+ chan_properties->adc_graph[ADC_CALIB_ABSOLUTE].dx *
+ chan_properties->offset_gain_denominator * 1000;
+
+ do_div(adc_chan_result->measurement,
+ chan_properties->adc_graph[ADC_CALIB_ABSOLUTE].dy *
+ chan_properties->offset_gain_numerator*2);
+ } else {
+ adc_chan_result->measurement = 0;
+ }
+ /* Note: adc_chan_result->measurement is in the unit of
+ adc_properties.adc_reference */
+ adc_chan_result->physical = (int32_t)adc_chan_result->measurement;
+ /* Change to .001 deg C */
+ adc_chan_result->physical -= KELVINMIL_DEGMIL;
+ adc_chan_result->measurement <<= 1;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(pm8xxx_adc_scale_pmic_therm);
+
+/* Scales the ADC code to 0.001 degrees C using the map
+ * table for the XO thermistor.
+ */
+int32_t pm8xxx_adc_tdkntcg_therm(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_properties,
+ const struct pm8xxx_adc_chan_properties *chan_properties,
+ struct pm8xxx_adc_chan_result *adc_chan_result)
+{
+ int32_t rt_r25;
+ int32_t offset = chan_properties->adc_graph[ADC_CALIB_ABSOLUTE].offset;
+
+ rt_r25 = adc_code - offset;
+
+ pm8xxx_adc_map_linear(adcmap_ntcg_104ef_104fb,
+ ARRAY_SIZE(adcmap_ntcg_104ef_104fb),
+ rt_r25, &adc_chan_result->physical);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(pm8xxx_adc_tdkntcg_therm);
+
+int32_t pm8xxx_adc_batt_scaler(struct pm8xxx_adc_arb_btm_param *btm_param)
+{
+ int rc;
+
+ rc = pm8xxx_adc_map_linear(
+ adcmap_btm_threshold,
+ ARRAY_SIZE(adcmap_btm_threshold),
+ btm_param->low_thr_temp,
+ &btm_param->low_thr_voltage);
+
+ if (!rc) {
+ rc = pm8xxx_adc_map_linear(
+ adcmap_btm_threshold,
+ ARRAY_SIZE(adcmap_btm_threshold),
+ btm_param->high_thr_temp,
+ &btm_param->high_thr_voltage);
+ }
+
+ return rc;
+}
+EXPORT_SYMBOL_GPL(pm8xxx_adc_batt_scaler);
diff --git a/drivers/hwmon/pm8xxx-adc.c b/drivers/hwmon/pm8xxx-adc.c
new file mode 100644
index 0000000..152eb40
--- /dev/null
+++ b/drivers/hwmon/pm8xxx-adc.c
@@ -0,0 +1,1286 @@
+/*
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Qualcomm's PM8921/PM8018 ADC Arbiter driver
+ */
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/mutex.h>
+#include <linux/hwmon.h>
+#include <linux/module.h>
+#include <linux/debugfs.h>
+#include <linux/wakelock.h>
+#include <linux/interrupt.h>
+#include <linux/completion.h>
+#include <linux/hwmon-sysfs.h>
+#include <linux/mfd/pm8xxx/mpp.h>
+#include <linux/platform_device.h>
+#include <linux/mfd/pm8xxx/core.h>
+#include <linux/regulator/consumer.h>
+#include <linux/mfd/pm8xxx/pm8xxx-adc.h>
+
+/* User Bank register set */
+#define PM8XXX_ADC_ARB_USRP_CNTRL1 0x197
+#define PM8XXX_ADC_ARB_USRP_CNTRL1_EN_ARB BIT(0)
+#define PM8XXX_ADC_ARB_USRP_CNTRL1_RSV1 BIT(1)
+#define PM8XXX_ADC_ARB_USRP_CNTRL1_RSV2 BIT(2)
+#define PM8XXX_ADC_ARB_USRP_CNTRL1_RSV3 BIT(3)
+#define PM8XXX_ADC_ARB_USRP_CNTRL1_RSV4 BIT(4)
+#define PM8XXX_ADC_ARB_USRP_CNTRL1_RSV5 BIT(5)
+#define PM8XXX_ADC_ARB_USRP_CNTRL1_EOC BIT(6)
+#define PM8XXX_ADC_ARB_USRP_CNTRL1_REQ BIT(7)
+
+#define PM8XXX_ADC_ARB_USRP_AMUX_CNTRL 0x198
+#define PM8XXX_ADC_ARB_USRP_AMUX_CNTRL_RSV0 BIT(0)
+#define PM8XXX_ADC_ARB_USRP_AMUX_CNTRL_RSV1 BIT(1)
+#define PM8XXX_ADC_ARB_USRP_AMUX_CNTRL_PREMUX0 BIT(2)
+#define PM8XXX_ADC_ARB_USRP_AMUX_CNTRL_PREMUX1 BIT(3)
+#define PM8XXX_ADC_ARB_USRP_AMUX_CNTRL_SEL0 BIT(4)
+#define PM8XXX_ADC_ARB_USRP_AMUX_CNTRL_SEL1 BIT(5)
+#define PM8XXX_ADC_ARB_USRP_AMUX_CNTRL_SEL2 BIT(6)
+#define PM8XXX_ADC_ARB_USRP_AMUX_CNTRL_SEL3 BIT(7)
+
+#define PM8XXX_ADC_ARB_USRP_ANA_PARAM 0x199
+#define PM8XXX_ADC_ARB_USRP_DIG_PARAM 0x19A
+#define PM8XXX_ADC_ARB_USRP_DIG_PARAM_SEL_SHIFT0 BIT(0)
+#define PM8XXX_ADC_ARB_USRP_DIG_PARAM_SEL_SHIFT1 BIT(1)
+#define PM8XXX_ADC_ARB_USRP_DIG_PARAM_CLK_RATE0 BIT(2)
+#define PM8XXX_ADC_ARB_USRP_DIG_PARAM_CLK_RATE1 BIT(3)
+#define PM8XXX_ADC_ARB_USRP_DIG_PARAM_EOC BIT(4)
+#define PM8XXX_ADC_ARB_USRP_DIG_PARAM_DEC_RATE0 BIT(5)
+#define PM8XXX_ADC_ARB_USRP_DIG_PARAM_DEC_RATE1 BIT(6)
+#define PM8XXX_ADC_ARB_USRP_DIG_PARAM_EN BIT(7)
+
+#define PM8XXX_ADC_ARB_USRP_RSV 0x19B
+#define PM8XXX_ADC_ARB_USRP_RSV_RST BIT(0)
+#define PM8XXX_ADC_ARB_USRP_RSV_DTEST0 BIT(1)
+#define PM8XXX_ADC_ARB_USRP_RSV_DTEST1 BIT(2)
+#define PM8XXX_ADC_ARB_USRP_RSV_OP BIT(3)
+#define PM8XXX_ADC_ARB_USRP_RSV_IP_SEL0 BIT(4)
+#define PM8XXX_ADC_ARB_USRP_RSV_IP_SEL1 BIT(5)
+#define PM8XXX_ADC_ARB_USRP_RSV_IP_SEL2 BIT(6)
+#define PM8XXX_ADC_ARB_USRP_RSV_TRM BIT(7)
+
+#define PM8XXX_ADC_ARB_USRP_DATA0 0x19D
+#define PM8XXX_ADC_ARB_USRP_DATA1 0x19C
+
+#define PM8XXX_ADC_ARB_BTM_CNTRL1 0x17e
+#define PM8XXX_ADC_ARB_BTM_CNTRL1_EN_BTM BIT(0)
+#define PM8XXX_ADC_ARB_BTM_CNTRL1_SEL_OP_MODE BIT(1)
+#define PM8XXX_ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL1 BIT(2)
+#define PM8XXX_ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL2 BIT(3)
+#define PM8XXX_ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL3 BIT(4)
+#define PM8XXX_ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL4 BIT(5)
+#define PM8XXX_ADC_ARB_BTM_CNTRL1_EOC BIT(6)
+#define PM8XXX_ADC_ARB_BTM_CNTRL1_REQ BIT(7)
+
+#define PM8XXX_ADC_ARB_BTM_CNTRL2 0x18c
+#define PM8XXX_ADC_ARB_BTM_AMUX_CNTRL 0x17f
+#define PM8XXX_ADC_ARB_BTM_ANA_PARAM 0x180
+#define PM8XXX_ADC_ARB_BTM_DIG_PARAM 0x181
+#define PM8XXX_ADC_ARB_BTM_RSV 0x182
+#define PM8XXX_ADC_ARB_BTM_DATA1 0x183
+#define PM8XXX_ADC_ARB_BTM_DATA0 0x184
+#define PM8XXX_ADC_ARB_BTM_BAT_COOL_THR1 0x185
+#define PM8XXX_ADC_ARB_BTM_BAT_COOL_THR0 0x186
+#define PM8XXX_ADC_ARB_BTM_BAT_WARM_THR1 0x187
+#define PM8XXX_ADC_ARB_BTM_BAT_WARM_THR0 0x188
+
+#define PM8XXX_ADC_ARB_ANA_DIG 0xa0
+#define PM8XXX_ADC_BTM_RSV 0x10
+#define PM8XXX_ADC_AMUX_MPP_SEL 2
+#define PM8XXX_ADC_AMUX_SEL 4
+#define PM8XXX_ADC_RSV_IP_SEL 4
+#define PM8XXX_ADC_BTM_CHANNEL_SEL 4
+#define PM8XXX_MAX_CHANNEL_PROPERTIES 2
+#define PM8XXX_ADC_IRQ_0 0
+#define PM8XXX_ADC_IRQ_1 1
+#define PM8XXX_ADC_IRQ_2 2
+#define PM8XXX_ADC_BTM_INTERVAL_SEL_MASK 0xF
+#define PM8XXX_ADC_BTM_INTERVAL_SEL_SHIFT 2
+#define PM8XXX_ADC_BTM_DECIMATION_SEL 5
+#define PM8XXX_ADC_MUL 10
+#define PM8XXX_ADC_CONV_TIME_MIN 2000
+#define PM8XXX_ADC_CONV_TIME_MAX 2100
+#define PM8XXX_ADC_MPP_SETTLE_TIME_MIN 200
+#define PM8XXX_ADC_MPP_SETTLE_TIME_MAX 200
+#define PM8XXX_ADC_PA_THERM_VREG_UV_MIN 1800000
+#define PM8XXX_ADC_PA_THERM_VREG_UV_MAX 1800000
+#define PM8XXX_ADC_PA_THERM_VREG_UA_LOAD 100000
+
+struct pm8xxx_adc {
+ struct device *dev;
+ struct pm8xxx_adc_properties *adc_prop;
+ int adc_irq;
+ struct mutex adc_lock;
+ struct mutex mpp_adc_lock;
+ spinlock_t btm_lock;
+ uint32_t adc_num_channel;
+ uint32_t adc_num_board_channel;
+ struct completion adc_rslt_completion;
+ struct pm8xxx_adc_amux *adc_channel;
+ int btm_warm_irq;
+ int btm_cool_irq;
+ struct dentry *dent;
+ struct work_struct warm_work;
+ struct work_struct cool_work;
+ uint32_t mpp_base;
+ struct device *hwmon;
+ struct wake_lock adc_wakelock;
+ int msm_suspend_check;
+ struct pm8xxx_adc_amux_properties *conv;
+ struct pm8xxx_adc_arb_btm_param batt[0];
+ struct sensor_device_attribute sens_attr[0];
+};
+
+struct pm8xxx_adc_amux_properties {
+ uint32_t amux_channel;
+ uint32_t decimation;
+ uint32_t amux_ip_rsv;
+ uint32_t amux_mpp_channel;
+ struct pm8xxx_adc_chan_properties chan_prop[0];
+};
+
+static const struct pm8xxx_adc_scaling_ratio pm8xxx_amux_scaling_ratio[] = {
+ {1, 1},
+ {1, 3},
+ {1, 4},
+ {1, 6}
+};
+
+static struct pm8xxx_adc *pmic_adc;
+
+static struct pm8xxx_adc_scale_fn adc_scale_fn[] = {
+ [ADC_SCALE_DEFAULT] = {pm8xxx_adc_scale_default},
+ [ADC_SCALE_BATT_THERM] = {pm8xxx_adc_scale_batt_therm},
+ [ADC_SCALE_PA_THERM] = {pm8xxx_adc_scale_pa_therm},
+ [ADC_SCALE_PMIC_THERM] = {pm8xxx_adc_scale_pmic_therm},
+ [ADC_SCALE_XOTHERM] = {pm8xxx_adc_tdkntcg_therm},
+};
+
+/* On PM8921 ADC the MPP needs to first be configured
+as an analog input to the AMUX pre-mux channel before
+issuing a read request. PM8921 MPP 8 is mapped to AMUX8
+and is common between remote processor's.
+On PM8018 ADC the MPP is directly connected to the AMUX
+pre-mux. Therefore clients of the PM8018 MPP do not need
+to configure the MPP as an analog input to the pre-mux.
+Clients can directly issue request on the pre-mux AMUX
+channel to read the ADC on the MPP */
+static struct pm8xxx_mpp_config_data pm8xxx_adc_mpp_config = {
+ .type = PM8XXX_MPP_TYPE_A_INPUT,
+ /* AMUX6 is dedicated to be used for apps processor */
+ .level = PM8XXX_MPP_AIN_AMUX_CH6,
+ .control = PM8XXX_MPP_AOUT_CTRL_DISABLE,
+};
+
+/* MPP Configuration for default settings */
+static struct pm8xxx_mpp_config_data pm8xxx_adc_mpp_unconfig = {
+ .type = PM8XXX_MPP_TYPE_SINK,
+ .level = PM8XXX_MPP_AIN_AMUX_CH5,
+ .control = PM8XXX_MPP_AOUT_CTRL_DISABLE,
+};
+
+static bool pm8xxx_adc_calib_first_adc;
+static bool pm8xxx_adc_initialized, pm8xxx_adc_calib_device_init;
+
+static int32_t pm8xxx_adc_arb_cntrl(uint32_t arb_cntrl,
+ uint32_t channel)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ int i, rc;
+ u8 data_arb_cntrl = 0;
+
+ if (arb_cntrl) {
+ if (adc_pmic->msm_suspend_check)
+ pr_err("PM8xxx ADC request made after suspend_noirq "
+ "with channel: %d\n", channel);
+ data_arb_cntrl |= PM8XXX_ADC_ARB_USRP_CNTRL1_EN_ARB;
+ wake_lock(&adc_pmic->adc_wakelock);
+ }
+
+ /* Write twice to the CNTRL register for the arbiter settings
+ to take into effect */
+ for (i = 0; i < 2; i++) {
+ rc = pm8xxx_writeb(adc_pmic->dev->parent,
+ PM8XXX_ADC_ARB_USRP_CNTRL1, data_arb_cntrl);
+ if (rc < 0) {
+ pr_err("PM8xxx arb cntrl write failed with %d\n", rc);
+ return rc;
+ }
+ }
+
+ if (arb_cntrl) {
+ data_arb_cntrl |= PM8XXX_ADC_ARB_USRP_CNTRL1_REQ;
+ rc = pm8xxx_writeb(adc_pmic->dev->parent,
+ PM8XXX_ADC_ARB_USRP_CNTRL1, data_arb_cntrl);
+ } else
+ wake_unlock(&adc_pmic->adc_wakelock);
+
+ return 0;
+}
+
+static int32_t pm8xxx_adc_patherm_power(bool on)
+{
+ static struct regulator *pa_therm;
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ int rc = 0;
+ if (on) {
+ pa_therm = regulator_get(adc_pmic->dev,
+ "pa_therm");
+ if (IS_ERR(pa_therm)) {
+ rc = PTR_ERR(pa_therm);
+ pr_err("failed to request pa_therm vreg "
+ "with error %d\n", rc);
+ return rc;
+ }
+
+ rc = regulator_set_voltage(pa_therm,
+ PM8XXX_ADC_PA_THERM_VREG_UV_MIN,
+ PM8XXX_ADC_PA_THERM_VREG_UV_MAX);
+ if (rc < 0) {
+ pr_err("failed to set the voltage for "
+ "pa_therm with error %d\n", rc);
+ goto fail;
+ }
+
+ rc = regulator_set_optimum_mode(pa_therm,
+ PM8XXX_ADC_PA_THERM_VREG_UA_LOAD);
+ if (rc < 0) {
+ pr_err("failed to set optimum mode for "
+ "pa_therm with error %d\n", rc);
+ goto fail;
+ }
+
+ if (regulator_enable(pa_therm)) {
+ pr_err("failed to enable pa_therm vreg with "
+ "error %d\n", rc);
+ goto fail;
+ }
+ } else {
+ if (pa_therm != NULL) {
+ regulator_disable(pa_therm);
+ regulator_put(pa_therm);
+ }
+ }
+
+ return rc;
+fail:
+ regulator_put(pa_therm);
+ return rc;
+}
+
+static int32_t pm8xxx_adc_channel_power_enable(uint32_t channel,
+ bool power_cntrl)
+{
+ int rc = 0;
+
+ switch (channel)
+ case ADC_MPP_1_AMUX8:
+ pm8xxx_adc_patherm_power(power_cntrl);
+
+ return rc;
+}
+
+
+static uint32_t pm8xxx_adc_read_reg(uint32_t reg, u8 *data)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ int rc;
+
+ rc = pm8xxx_readb(adc_pmic->dev->parent, reg, data);
+ if (rc < 0) {
+ pr_err("PM8xxx adc read reg %d failed with %d\n", reg, rc);
+ return rc;
+ }
+
+ return 0;
+}
+
+static uint32_t pm8xxx_adc_write_reg(uint32_t reg, u8 data)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ int rc;
+
+ rc = pm8xxx_writeb(adc_pmic->dev->parent, reg, data);
+ if (rc < 0) {
+ pr_err("PM8xxx adc write reg %d failed with %d\n", reg, rc);
+ return rc;
+ }
+
+ return 0;
+}
+
+static int32_t pm8xxx_adc_configure(
+ struct pm8xxx_adc_amux_properties *chan_prop)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ u8 data_amux_chan = 0, data_arb_rsv = 0, data_dig_param = 0;
+ int rc;
+
+ data_amux_chan |= chan_prop->amux_channel << PM8XXX_ADC_AMUX_SEL;
+
+ if (chan_prop->amux_mpp_channel)
+ data_amux_chan |= chan_prop->amux_mpp_channel <<
+ PM8XXX_ADC_AMUX_MPP_SEL;
+
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_USRP_AMUX_CNTRL,
+ data_amux_chan);
+ if (rc < 0)
+ return rc;
+
+ data_arb_rsv &= (PM8XXX_ADC_ARB_USRP_RSV_RST |
+ PM8XXX_ADC_ARB_USRP_RSV_DTEST0 |
+ PM8XXX_ADC_ARB_USRP_RSV_DTEST1 |
+ PM8XXX_ADC_ARB_USRP_RSV_OP |
+ PM8XXX_ADC_ARB_USRP_RSV_TRM);
+ data_arb_rsv |= chan_prop->amux_ip_rsv << PM8XXX_ADC_RSV_IP_SEL;
+
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_USRP_RSV, data_arb_rsv);
+ if (rc < 0)
+ return rc;
+
+ rc = pm8xxx_adc_read_reg(PM8XXX_ADC_ARB_USRP_DIG_PARAM,
+ &data_dig_param);
+ if (rc < 0)
+ return rc;
+
+ /* Default 2.4Mhz clock rate */
+ /* Client chooses the decimation */
+ switch (chan_prop->decimation) {
+ case ADC_DECIMATION_TYPE1:
+ data_dig_param |= PM8XXX_ADC_ARB_USRP_DIG_PARAM_DEC_RATE0;
+ break;
+ case ADC_DECIMATION_TYPE2:
+ data_dig_param |= (PM8XXX_ADC_ARB_USRP_DIG_PARAM_DEC_RATE0
+ | PM8XXX_ADC_ARB_USRP_DIG_PARAM_DEC_RATE1);
+ break;
+ default:
+ data_dig_param |= PM8XXX_ADC_ARB_USRP_DIG_PARAM_DEC_RATE0;
+ break;
+ }
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_USRP_DIG_PARAM,
+ PM8XXX_ADC_ARB_ANA_DIG);
+ if (rc < 0)
+ return rc;
+
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_USRP_ANA_PARAM,
+ PM8XXX_ADC_ARB_ANA_DIG);
+ if (rc < 0)
+ return rc;
+
+ if (!pm8xxx_adc_calib_first_adc)
+ enable_irq(adc_pmic->adc_irq);
+
+ rc = pm8xxx_adc_arb_cntrl(1, data_amux_chan);
+ if (rc < 0) {
+ pr_err("Configuring ADC Arbiter"
+ "enable failed with %d\n", rc);
+ return rc;
+ }
+
+ return 0;
+}
+
+static uint32_t pm8xxx_adc_read_adc_code(int32_t *data)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ uint8_t rslt_lsb, rslt_msb;
+ int32_t rc, max_ideal_adc_code = 1 << adc_pmic->adc_prop->bitresolution;
+
+ rc = pm8xxx_readb(adc_pmic->dev->parent,
+ PM8XXX_ADC_ARB_USRP_DATA0, &rslt_lsb);
+ if (rc < 0) {
+ pr_err("PM8xxx adc result read failed with %d\n", rc);
+ return rc;
+ }
+
+ rc = pm8xxx_readb(adc_pmic->dev->parent,
+ PM8XXX_ADC_ARB_USRP_DATA1, &rslt_msb);
+ if (rc < 0) {
+ pr_err("PM8xxx adc result read failed with %d\n", rc);
+ return rc;
+ }
+
+ *data = (rslt_msb << 8) | rslt_lsb;
+
+ /* Use the midpoint to determine underflow or overflow */
+ if (*data > max_ideal_adc_code + (max_ideal_adc_code >> 1))
+ *data |= ((1 << (8 * sizeof(*data) -
+ adc_pmic->adc_prop->bitresolution)) - 1) <<
+ adc_pmic->adc_prop->bitresolution;
+
+ /* Default value for switching off the arbiter after reading
+ the ADC value. Bit 0 set to 0. */
+ rc = pm8xxx_adc_arb_cntrl(0, CHANNEL_NONE);
+ if (rc < 0) {
+ pr_err("%s: Configuring ADC Arbiter disable"
+ "failed\n", __func__);
+ return rc;
+ }
+
+ return 0;
+}
+
+static void pm8xxx_adc_btm_warm_scheduler_fn(struct work_struct *work)
+{
+ struct pm8xxx_adc *adc_pmic = container_of(work, struct pm8xxx_adc,
+ warm_work);
+ unsigned long flags = 0;
+ bool warm_status;
+
+ spin_lock_irqsave(&adc_pmic->btm_lock, flags);
+ warm_status = irq_read_line(adc_pmic->btm_warm_irq);
+ if (adc_pmic->batt->btm_warm_fn != NULL)
+ adc_pmic->batt->btm_warm_fn(warm_status);
+ spin_unlock_irqrestore(&adc_pmic->btm_lock, flags);
+}
+
+static void pm8xxx_adc_btm_cool_scheduler_fn(struct work_struct *work)
+{
+ struct pm8xxx_adc *adc_pmic = container_of(work, struct pm8xxx_adc,
+ cool_work);
+ unsigned long flags = 0;
+ bool cool_status;
+
+ spin_lock_irqsave(&adc_pmic->btm_lock, flags);
+ cool_status = irq_read_line(adc_pmic->btm_cool_irq);
+ if (adc_pmic->batt->btm_cool_fn != NULL)
+ adc_pmic->batt->btm_cool_fn(cool_status);
+ spin_unlock_irqrestore(&adc_pmic->btm_lock, flags);
+}
+
+static irqreturn_t pm8xxx_adc_isr(int irq, void *dev_id)
+{
+ struct pm8xxx_adc *adc_8xxx = dev_id;
+
+ disable_irq_nosync(adc_8xxx->adc_irq);
+
+ if (pm8xxx_adc_calib_first_adc)
+ return IRQ_HANDLED;
+ /* TODO Handle spurius interrupt condition */
+ complete(&adc_8xxx->adc_rslt_completion);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t pm8xxx_btm_warm_isr(int irq, void *dev_id)
+{
+ struct pm8xxx_adc *btm_8xxx = dev_id;
+
+ schedule_work(&btm_8xxx->warm_work);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t pm8xxx_btm_cool_isr(int irq, void *dev_id)
+{
+ struct pm8xxx_adc *btm_8xxx = dev_id;
+
+ schedule_work(&btm_8xxx->cool_work);
+
+ return IRQ_HANDLED;
+}
+
+static uint32_t pm8xxx_adc_calib_device(void)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ struct pm8xxx_adc_amux_properties conv;
+ int rc, offset_adc, slope_adc, calib_read_1, calib_read_2;
+ u8 data_arb_usrp_cntrl1 = 0;
+
+ conv.amux_channel = CHANNEL_125V;
+ conv.decimation = ADC_DECIMATION_TYPE2;
+ conv.amux_ip_rsv = AMUX_RSV1;
+ conv.amux_mpp_channel = PREMUX_MPP_SCALE_0;
+ pm8xxx_adc_calib_first_adc = true;
+ rc = pm8xxx_adc_configure(&conv);
+ if (rc) {
+ pr_err("pm8xxx_adc configure failed with %d\n", rc);
+ goto calib_fail;
+ }
+
+ while (data_arb_usrp_cntrl1 != (PM8XXX_ADC_ARB_USRP_CNTRL1_EOC |
+ PM8XXX_ADC_ARB_USRP_CNTRL1_EN_ARB)) {
+ rc = pm8xxx_adc_read_reg(PM8XXX_ADC_ARB_USRP_CNTRL1,
+ &data_arb_usrp_cntrl1);
+ if (rc < 0)
+ return rc;
+ usleep_range(PM8XXX_ADC_CONV_TIME_MIN,
+ PM8XXX_ADC_CONV_TIME_MAX);
+ }
+ data_arb_usrp_cntrl1 = 0;
+
+ rc = pm8xxx_adc_read_adc_code(&calib_read_1);
+ if (rc) {
+ pr_err("pm8xxx_adc read adc failed with %d\n", rc);
+ pm8xxx_adc_calib_first_adc = false;
+ goto calib_fail;
+ }
+ pm8xxx_adc_calib_first_adc = false;
+
+ conv.amux_channel = CHANNEL_625MV;
+ conv.decimation = ADC_DECIMATION_TYPE2;
+ conv.amux_ip_rsv = AMUX_RSV1;
+ conv.amux_mpp_channel = PREMUX_MPP_SCALE_0;
+ pm8xxx_adc_calib_first_adc = true;
+ rc = pm8xxx_adc_configure(&conv);
+ if (rc) {
+ pr_err("pm8xxx_adc configure failed with %d\n", rc);
+ goto calib_fail;
+ }
+
+ while (data_arb_usrp_cntrl1 != (PM8XXX_ADC_ARB_USRP_CNTRL1_EOC |
+ PM8XXX_ADC_ARB_USRP_CNTRL1_EN_ARB)) {
+ rc = pm8xxx_adc_read_reg(PM8XXX_ADC_ARB_USRP_CNTRL1,
+ &data_arb_usrp_cntrl1);
+ if (rc < 0)
+ return rc;
+ usleep_range(PM8XXX_ADC_CONV_TIME_MIN,
+ PM8XXX_ADC_CONV_TIME_MAX);
+ }
+ data_arb_usrp_cntrl1 = 0;
+
+ rc = pm8xxx_adc_read_adc_code(&calib_read_2);
+ if (rc) {
+ pr_err("pm8xxx_adc read adc failed with %d\n", rc);
+ pm8xxx_adc_calib_first_adc = false;
+ goto calib_fail;
+ }
+ pm8xxx_adc_calib_first_adc = false;
+
+ slope_adc = (((calib_read_1 - calib_read_2) << PM8XXX_ADC_MUL)/
+ PM8XXX_CHANNEL_ADC_625_MV);
+ offset_adc = calib_read_2 -
+ ((slope_adc * PM8XXX_CHANNEL_ADC_625_MV) >>
+ PM8XXX_ADC_MUL);
+
+ adc_pmic->conv->chan_prop->adc_graph[ADC_CALIB_ABSOLUTE].offset
+ = offset_adc;
+ adc_pmic->conv->chan_prop->adc_graph[ADC_CALIB_ABSOLUTE].dy =
+ (calib_read_1 - calib_read_2);
+ adc_pmic->conv->chan_prop->adc_graph[ADC_CALIB_ABSOLUTE].dx
+ = PM8XXX_CHANNEL_ADC_625_MV;
+ rc = pm8xxx_adc_arb_cntrl(0, CHANNEL_NONE);
+ if (rc < 0) {
+ pr_err("%s: Configuring ADC Arbiter disable"
+ "failed\n", __func__);
+ return rc;
+ }
+ /* Ratiometric Calibration */
+ conv.amux_channel = CHANNEL_MUXOFF;
+ conv.decimation = ADC_DECIMATION_TYPE2;
+ conv.amux_ip_rsv = AMUX_RSV5;
+ conv.amux_mpp_channel = PREMUX_MPP_SCALE_0;
+ pm8xxx_adc_calib_first_adc = true;
+ rc = pm8xxx_adc_configure(&conv);
+ if (rc) {
+ pr_err("pm8xxx_adc configure failed with %d\n", rc);
+ goto calib_fail;
+ }
+
+ while (data_arb_usrp_cntrl1 != (PM8XXX_ADC_ARB_USRP_CNTRL1_EOC |
+ PM8XXX_ADC_ARB_USRP_CNTRL1_EN_ARB)) {
+ rc = pm8xxx_adc_read_reg(PM8XXX_ADC_ARB_USRP_CNTRL1,
+ &data_arb_usrp_cntrl1);
+ if (rc < 0)
+ return rc;
+ usleep_range(PM8XXX_ADC_CONV_TIME_MIN,
+ PM8XXX_ADC_CONV_TIME_MAX);
+ }
+ data_arb_usrp_cntrl1 = 0;
+
+ rc = pm8xxx_adc_read_adc_code(&calib_read_1);
+ if (rc) {
+ pr_err("pm8xxx_adc read adc failed with %d\n", rc);
+ pm8xxx_adc_calib_first_adc = false;
+ goto calib_fail;
+ }
+ pm8xxx_adc_calib_first_adc = false;
+
+ conv.amux_channel = CHANNEL_MUXOFF;
+ conv.decimation = ADC_DECIMATION_TYPE2;
+ conv.amux_ip_rsv = AMUX_RSV4;
+ conv.amux_mpp_channel = PREMUX_MPP_SCALE_0;
+ pm8xxx_adc_calib_first_adc = true;
+ rc = pm8xxx_adc_configure(&conv);
+ if (rc) {
+ pr_err("pm8xxx_adc configure failed with %d\n", rc);
+ goto calib_fail;
+ }
+
+ while (data_arb_usrp_cntrl1 != (PM8XXX_ADC_ARB_USRP_CNTRL1_EOC |
+ PM8XXX_ADC_ARB_USRP_CNTRL1_EN_ARB)) {
+ rc = pm8xxx_adc_read_reg(PM8XXX_ADC_ARB_USRP_CNTRL1,
+ &data_arb_usrp_cntrl1);
+ if (rc < 0)
+ return rc;
+ usleep_range(PM8XXX_ADC_CONV_TIME_MIN,
+ PM8XXX_ADC_CONV_TIME_MAX);
+ }
+ data_arb_usrp_cntrl1 = 0;
+
+ rc = pm8xxx_adc_read_adc_code(&calib_read_2);
+ if (rc) {
+ pr_err("pm8xxx_adc read adc failed with %d\n", rc);
+ pm8xxx_adc_calib_first_adc = false;
+ goto calib_fail;
+ }
+ pm8xxx_adc_calib_first_adc = false;
+
+ slope_adc = (((calib_read_1 - calib_read_2) << PM8XXX_ADC_MUL)/
+ adc_pmic->adc_prop->adc_vdd_reference);
+ offset_adc = calib_read_2 -
+ ((slope_adc * adc_pmic->adc_prop->adc_vdd_reference)
+ >> PM8XXX_ADC_MUL);
+
+ adc_pmic->conv->chan_prop->adc_graph[ADC_CALIB_RATIOMETRIC].offset
+ = offset_adc;
+ adc_pmic->conv->chan_prop->adc_graph[ADC_CALIB_RATIOMETRIC].dy =
+ (calib_read_1 - calib_read_2);
+ adc_pmic->conv->chan_prop->adc_graph[ADC_CALIB_RATIOMETRIC].dx =
+ adc_pmic->adc_prop->adc_vdd_reference;
+calib_fail:
+ rc = pm8xxx_adc_arb_cntrl(0, CHANNEL_NONE);
+ if (rc < 0) {
+ pr_err("%s: Configuring ADC Arbiter disable"
+ "failed\n", __func__);
+ }
+
+ return rc;
+}
+
+uint32_t pm8xxx_adc_read(enum pm8xxx_adc_channels channel,
+ struct pm8xxx_adc_chan_result *result)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ int i = 0, rc = 0, rc_fail, amux_prescaling, scale_type;
+ enum pm8xxx_adc_premux_mpp_scale_type mpp_scale;
+
+ if (!pm8xxx_adc_initialized)
+ return -ENODEV;
+
+ if (!pm8xxx_adc_calib_device_init) {
+ if (pm8xxx_adc_calib_device() == 0)
+ pm8xxx_adc_calib_device_init = true;
+ }
+
+ mutex_lock(&adc_pmic->adc_lock);
+
+ for (i = 0; i < adc_pmic->adc_num_channel; i++) {
+ if (channel == adc_pmic->adc_channel[i].channel_name)
+ break;
+ }
+
+ if (i == adc_pmic->adc_num_channel) {
+ rc = -EBADF;
+ goto fail_unlock;
+ }
+
+ if (channel < PM8XXX_CHANNEL_MPP_SCALE1_IDX) {
+ mpp_scale = PREMUX_MPP_SCALE_0;
+ adc_pmic->conv->amux_channel = channel;
+ } else if (channel >= PM8XXX_CHANNEL_MPP_SCALE1_IDX) {
+ mpp_scale = PREMUX_MPP_SCALE_1;
+ adc_pmic->conv->amux_channel = channel %
+ PM8XXX_CHANNEL_MPP_SCALE1_IDX;
+ } else if (channel >= PM8XXX_CHANNEL_MPP_SCALE3_IDX) {
+ mpp_scale = PREMUX_MPP_SCALE_1_DIV3;
+ adc_pmic->conv->amux_channel = channel %
+ PM8XXX_CHANNEL_MPP_SCALE3_IDX;
+ }
+
+ adc_pmic->conv->amux_mpp_channel = mpp_scale;
+ adc_pmic->conv->amux_ip_rsv = adc_pmic->adc_channel[i].adc_rsv;
+ adc_pmic->conv->decimation = adc_pmic->adc_channel[i].adc_decimation;
+ amux_prescaling = adc_pmic->adc_channel[i].chan_path_prescaling;
+
+ adc_pmic->conv->chan_prop->offset_gain_numerator =
+ pm8xxx_amux_scaling_ratio[amux_prescaling].num;
+ adc_pmic->conv->chan_prop->offset_gain_denominator =
+ pm8xxx_amux_scaling_ratio[amux_prescaling].den;
+
+ rc = pm8xxx_adc_channel_power_enable(channel, true);
+ if (rc) {
+ rc = -EINVAL;
+ goto fail_unlock;
+ }
+
+ rc = pm8xxx_adc_configure(adc_pmic->conv);
+ if (rc) {
+ rc = -EINVAL;
+ goto fail;
+ }
+
+ wait_for_completion(&adc_pmic->adc_rslt_completion);
+
+ rc = pm8xxx_adc_read_adc_code(&result->adc_code);
+ if (rc) {
+ rc = -EINVAL;
+ goto fail;
+ }
+
+ scale_type = adc_pmic->adc_channel[i].adc_scale_fn;
+ if (scale_type >= ADC_SCALE_NONE) {
+ rc = -EBADF;
+ goto fail;
+ }
+
+ adc_scale_fn[scale_type].chan(result->adc_code,
+ adc_pmic->adc_prop, adc_pmic->conv->chan_prop, result);
+
+ rc = pm8xxx_adc_channel_power_enable(channel, false);
+ if (rc) {
+ rc = -EINVAL;
+ goto fail_unlock;
+ }
+
+ mutex_unlock(&adc_pmic->adc_lock);
+
+ return 0;
+fail:
+ rc_fail = pm8xxx_adc_channel_power_enable(channel, false);
+ if (rc_fail)
+ pr_err("pm8xxx adc power disable failed\n");
+fail_unlock:
+ mutex_unlock(&adc_pmic->adc_lock);
+ pr_err("pm8xxx adc error with %d\n", rc);
+ return rc;
+}
+EXPORT_SYMBOL_GPL(pm8xxx_adc_read);
+
+uint32_t pm8xxx_adc_mpp_config_read(uint32_t mpp_num,
+ enum pm8xxx_adc_channels channel,
+ struct pm8xxx_adc_chan_result *result)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ int rc = 0;
+
+ if (!adc_pmic->mpp_base) {
+ rc = -EINVAL;
+ pr_info("PM8xxx MPP base invalid with error %d\n", rc);
+ return rc;
+ }
+
+ if (mpp_num == PM8XXX_AMUX_MPP_8) {
+ rc = -EINVAL;
+ pr_info("PM8xxx MPP8 is already configured "
+ "to AMUX8. Use pm8xxx_adc_read() instead.\n");
+ return rc;
+ }
+
+ mutex_lock(&adc_pmic->mpp_adc_lock);
+
+ rc = pm8xxx_mpp_config(((mpp_num - 1) + adc_pmic->mpp_base),
+ &pm8xxx_adc_mpp_config);
+ if (rc < 0) {
+ pr_err("pm8xxx adc mpp config error with %d\n", rc);
+ goto fail;
+ }
+
+ usleep_range(PM8XXX_ADC_MPP_SETTLE_TIME_MIN,
+ PM8XXX_ADC_MPP_SETTLE_TIME_MAX);
+
+ rc = pm8xxx_adc_read(channel, result);
+ if (rc < 0)
+ pr_err("pm8xxx adc read error with %d\n", rc);
+
+ rc = pm8xxx_mpp_config(((mpp_num - 1) + adc_pmic->mpp_base),
+ &pm8xxx_adc_mpp_unconfig);
+ if (rc < 0)
+ pr_err("pm8xxx adc mpp config error with %d\n", rc);
+fail:
+ mutex_unlock(&adc_pmic->mpp_adc_lock);
+
+ return rc;
+}
+EXPORT_SYMBOL_GPL(pm8xxx_adc_mpp_config_read);
+
+uint32_t pm8xxx_adc_btm_configure(struct pm8xxx_adc_arb_btm_param *btm_param)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ u8 data_btm_cool_thr0, data_btm_cool_thr1;
+ u8 data_btm_warm_thr0, data_btm_warm_thr1;
+ u8 arb_btm_cntrl1;
+ unsigned long flags = 0;
+ int rc;
+
+ if (adc_pmic == NULL) {
+ pr_err("PMIC ADC not valid\n");
+ return -EINVAL;
+ }
+
+ if ((btm_param->btm_cool_fn == NULL) &&
+ (btm_param->btm_warm_fn == NULL)) {
+ pr_err("No BTM warm/cool notification??\n");
+ return -EINVAL;
+ }
+
+ rc = pm8xxx_adc_batt_scaler(btm_param);
+ if (rc < 0) {
+ pr_err("Failed to lookup the BTM thresholds\n");
+ return rc;
+ }
+
+ spin_lock_irqsave(&adc_pmic->btm_lock, flags);
+
+ data_btm_cool_thr0 = ((btm_param->low_thr_voltage << 24) >> 24);
+ data_btm_cool_thr1 = ((btm_param->low_thr_voltage << 16) >> 24);
+ data_btm_warm_thr0 = ((btm_param->high_thr_voltage << 24) >> 24);
+ data_btm_warm_thr1 = ((btm_param->high_thr_voltage << 16) >> 24);
+
+ if (btm_param->btm_cool_fn != NULL) {
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_BTM_BAT_COOL_THR0,
+ data_btm_cool_thr0);
+ if (rc < 0)
+ goto write_err;
+
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_BTM_BAT_COOL_THR1,
+ data_btm_cool_thr1);
+ if (rc < 0)
+ goto write_err;
+
+ adc_pmic->batt->btm_cool_fn = btm_param->btm_cool_fn;
+ }
+
+ if (btm_param->btm_warm_fn != NULL) {
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_BTM_BAT_WARM_THR0,
+ data_btm_warm_thr0);
+ if (rc < 0)
+ goto write_err;
+
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_BTM_BAT_WARM_THR1,
+ data_btm_warm_thr1);
+ if (rc < 0)
+ goto write_err;
+
+ adc_pmic->batt->btm_warm_fn = btm_param->btm_warm_fn;
+ }
+
+ rc = pm8xxx_adc_read_reg(PM8XXX_ADC_ARB_BTM_CNTRL1, &arb_btm_cntrl1);
+ if (rc < 0)
+ goto bail_out;
+
+ btm_param->interval &= PM8XXX_ADC_BTM_INTERVAL_SEL_MASK;
+ arb_btm_cntrl1 |=
+ btm_param->interval << PM8XXX_ADC_BTM_INTERVAL_SEL_SHIFT;
+
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_BTM_CNTRL1, arb_btm_cntrl1);
+ if (rc < 0)
+ goto write_err;
+
+ spin_unlock_irqrestore(&adc_pmic->btm_lock, flags);
+
+ return rc;
+bail_out:
+write_err:
+ spin_unlock_irqrestore(&adc_pmic->btm_lock, flags);
+ pr_debug("%s: with error code %d\n", __func__, rc);
+ return rc;
+}
+EXPORT_SYMBOL_GPL(pm8xxx_adc_btm_configure);
+
+static uint32_t pm8xxx_adc_btm_read(uint32_t channel)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ int rc, i;
+ u8 arb_btm_dig_param, arb_btm_ana_param, arb_btm_rsv;
+ u8 arb_btm_amux_cntrl, data_arb_btm_cntrl = 0;
+ unsigned long flags;
+
+ arb_btm_amux_cntrl = channel << PM8XXX_ADC_BTM_CHANNEL_SEL;
+ arb_btm_rsv = adc_pmic->adc_channel[channel].adc_rsv;
+ arb_btm_dig_param = arb_btm_ana_param = PM8XXX_ADC_ARB_ANA_DIG;
+
+ spin_lock_irqsave(&adc_pmic->btm_lock, flags);
+
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_BTM_AMUX_CNTRL,
+ arb_btm_amux_cntrl);
+ if (rc < 0)
+ goto write_err;
+
+ arb_btm_rsv = PM8XXX_ADC_BTM_RSV;
+
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_BTM_RSV, arb_btm_rsv);
+ if (rc < 0)
+ goto write_err;
+
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_BTM_DIG_PARAM,
+ arb_btm_dig_param);
+ if (rc < 0)
+ goto write_err;
+
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_BTM_ANA_PARAM,
+ arb_btm_ana_param);
+ if (rc < 0)
+ goto write_err;
+
+ data_arb_btm_cntrl |= PM8XXX_ADC_ARB_BTM_CNTRL1_EN_BTM;
+
+ for (i = 0; i < 2; i++) {
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_BTM_CNTRL1,
+ data_arb_btm_cntrl);
+ if (rc < 0)
+ goto write_err;
+ }
+
+ data_arb_btm_cntrl |= PM8XXX_ADC_ARB_BTM_CNTRL1_REQ
+ | PM8XXX_ADC_ARB_BTM_CNTRL1_SEL_OP_MODE;
+
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_BTM_CNTRL1,
+ data_arb_btm_cntrl);
+ if (rc < 0)
+ goto write_err;
+
+ if (pmic_adc->batt->btm_warm_fn != NULL)
+ enable_irq(adc_pmic->btm_warm_irq);
+
+ if (pmic_adc->batt->btm_cool_fn != NULL)
+ enable_irq(adc_pmic->btm_cool_irq);
+
+write_err:
+ spin_unlock_irqrestore(&adc_pmic->btm_lock, flags);
+ return rc;
+}
+
+uint32_t pm8xxx_adc_btm_start(void)
+{
+ return pm8xxx_adc_btm_read(CHANNEL_BATT_THERM);
+}
+EXPORT_SYMBOL_GPL(pm8xxx_adc_btm_start);
+
+uint32_t pm8xxx_adc_btm_end(void)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ int i, rc;
+ u8 data_arb_btm_cntrl;
+ unsigned long flags;
+
+ disable_irq_nosync(adc_pmic->btm_warm_irq);
+ disable_irq_nosync(adc_pmic->btm_cool_irq);
+
+ spin_lock_irqsave(&adc_pmic->btm_lock, flags);
+ /* Set BTM registers to Disable mode */
+ rc = pm8xxx_adc_read_reg(PM8XXX_ADC_ARB_BTM_CNTRL1,
+ &data_arb_btm_cntrl);
+ if (rc < 0) {
+ spin_unlock_irqrestore(&adc_pmic->btm_lock, flags);
+ return rc;
+ }
+
+ data_arb_btm_cntrl |= ~PM8XXX_ADC_ARB_BTM_CNTRL1_EN_BTM;
+ /* Write twice to the CNTRL register for the arbiter settings
+ to take into effect */
+ for (i = 0; i < 2; i++) {
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_BTM_CNTRL1,
+ data_arb_btm_cntrl);
+ if (rc < 0) {
+ spin_unlock_irqrestore(&adc_pmic->btm_lock, flags);
+ return rc;
+ }
+ }
+
+ spin_unlock_irqrestore(&adc_pmic->btm_lock, flags);
+
+ return rc;
+}
+EXPORT_SYMBOL_GPL(pm8xxx_adc_btm_end);
+
+static ssize_t pm8xxx_adc_show(struct device *dev,
+ struct device_attribute *devattr, char *buf)
+{
+ struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ struct pm8xxx_adc_chan_result result;
+ int rc = -1;
+
+ if (attr->index < adc_pmic->adc_num_channel)
+ rc = pm8xxx_adc_read(attr->index, &result);
+
+ if (rc)
+ return 0;
+
+ return snprintf(buf, sizeof(struct pm8xxx_adc_chan_result),
+ "Result:%lld Raw:%d\n",
+ result.physical, result.adc_code);
+}
+
+static int get_adc(void *data, u64 *val)
+{
+ struct pm8xxx_adc_chan_result result;
+ int i = (int)data;
+ int rc;
+
+ rc = pm8xxx_adc_read(i, &result);
+ if (!rc)
+ pr_info("ADC value raw:%x physical:%lld\n",
+ result.adc_code, result.physical);
+ *val = result.physical;
+
+ return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(reg_fops, get_adc, NULL, "%llu\n");
+
+static int get_mpp_adc(void *data, u64 *val)
+{
+ struct pm8xxx_adc_chan_result result;
+ int i = (int)data;
+ int rc;
+
+ rc = pm8xxx_adc_mpp_config_read(i,
+ ADC_MPP_1_AMUX6, &result);
+ if (!rc)
+ pr_info("ADC MPP value raw:%x physical:%lld\n",
+ result.adc_code, result.physical);
+ *val = result.physical;
+
+ return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(reg_mpp_fops, get_mpp_adc, NULL, "%llu\n");
+
+#ifdef CONFIG_DEBUG_FS
+static void create_debugfs_entries(void)
+{
+ int i = 0;
+ pmic_adc->dent = debugfs_create_dir("pm8xxx_adc", NULL);
+
+ if (IS_ERR(pmic_adc->dent)) {
+ pr_err("pmic adc debugfs dir not created\n");
+ return;
+ }
+
+ for (i = 0; i < pmic_adc->adc_num_board_channel; i++)
+ debugfs_create_file(pmic_adc->adc_channel[i].name,
+ 0644, pmic_adc->dent,
+ (void *)pmic_adc->adc_channel[i].channel_name,
+ ®_fops);
+}
+#else
+static inline void create_debugfs_entries(void)
+{
+}
+#endif
+static struct sensor_device_attribute pm8xxx_adc_attr =
+ SENSOR_ATTR(NULL, S_IRUGO, pm8xxx_adc_show, NULL, 0);
+
+static int32_t pm8xxx_adc_init_hwmon(struct platform_device *pdev)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ int rc = 0, i;
+
+ for (i = 0; i < pmic_adc->adc_num_board_channel; i++) {
+ pm8xxx_adc_attr.index = adc_pmic->adc_channel[i].channel_name;
+ pm8xxx_adc_attr.dev_attr.attr.name =
+ adc_pmic->adc_channel[i].name;
+ memcpy(&adc_pmic->sens_attr[i], &pm8xxx_adc_attr,
+ sizeof(pm8xxx_adc_attr));
+ rc = device_create_file(&pdev->dev,
+ &adc_pmic->sens_attr[i].dev_attr);
+ if (rc) {
+ dev_err(&pdev->dev, "device_create_file failed for "
+ "dev %s\n",
+ adc_pmic->adc_channel[i].name);
+ goto hwmon_err_sens;
+ }
+ }
+
+ return 0;
+hwmon_err_sens:
+ pr_info("Init HWMON failed for pm8xxx_adc with %d\n", rc);
+ return rc;
+}
+
+#ifdef CONFIG_PM
+static int pm8xxx_adc_suspend_noirq(struct device *dev)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+
+ adc_pmic->msm_suspend_check = 1;
+
+ return 0;
+}
+
+static int pm8xxx_adc_resume_noirq(struct device *dev)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+
+ adc_pmic->msm_suspend_check = 0;
+
+ return 0;
+}
+
+static const struct dev_pm_ops pm8xxx_adc_dev_pm_ops = {
+ .suspend_noirq = pm8xxx_adc_suspend_noirq,
+ .resume_noirq = pm8xxx_adc_resume_noirq,
+};
+
+#define PM8XXX_ADC_DEV_PM_OPS (&pm8xxx_adc_dev_pm_ops)
+#else
+#define PM8XXX_ADC_DEV_PM_OPS NULL
+#endif
+
+static int __devexit pm8xxx_adc_teardown(struct platform_device *pdev)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ int i;
+
+ wake_lock_destroy(&adc_pmic->adc_wakelock);
+ platform_set_drvdata(pdev, NULL);
+ pmic_adc = NULL;
+ for (i = 0; i < adc_pmic->adc_num_board_channel; i++)
+ device_remove_file(adc_pmic->dev,
+ &adc_pmic->sens_attr[i].dev_attr);
+ pm8xxx_adc_initialized = false;
+
+ return 0;
+}
+
+static int __devinit pm8xxx_adc_probe(struct platform_device *pdev)
+{
+ const struct pm8xxx_adc_platform_data *pdata = pdev->dev.platform_data;
+ struct pm8xxx_adc *adc_pmic;
+ struct pm8xxx_adc_amux_properties *adc_amux_prop;
+ int rc = 0;
+
+ if (!pdata) {
+ dev_err(&pdev->dev, "no platform data?\n");
+ return -EINVAL;
+ }
+
+ adc_pmic = devm_kzalloc(&pdev->dev, sizeof(struct pm8xxx_adc) +
+ sizeof(struct pm8xxx_adc_arb_btm_param) +
+ (sizeof(struct sensor_device_attribute) *
+ pdata->adc_num_board_channel), GFP_KERNEL);
+ if (!adc_pmic) {
+ dev_err(&pdev->dev, "Unable to allocate memory\n");
+ return -ENOMEM;
+ }
+
+ adc_amux_prop = devm_kzalloc(&pdev->dev,
+ sizeof(struct pm8xxx_adc_amux_properties) +
+ sizeof(struct pm8xxx_adc_chan_properties)
+ , GFP_KERNEL);
+ if (!adc_amux_prop) {
+ dev_err(&pdev->dev, "Unable to allocate memory\n");
+ return -ENOMEM;
+ }
+
+ adc_pmic->dev = &pdev->dev;
+ adc_pmic->adc_prop = pdata->adc_prop;
+ adc_pmic->conv = adc_amux_prop;
+ init_completion(&adc_pmic->adc_rslt_completion);
+ adc_pmic->adc_channel = pdata->adc_channel;
+ adc_pmic->adc_num_board_channel = pdata->adc_num_board_channel;
+ adc_pmic->adc_num_channel = ADC_MPP_2_CHANNEL_NONE;
+ adc_pmic->mpp_base = pdata->adc_mpp_base;
+
+ mutex_init(&adc_pmic->adc_lock);
+ mutex_init(&adc_pmic->mpp_adc_lock);
+ spin_lock_init(&adc_pmic->btm_lock);
+
+ adc_pmic->adc_irq = platform_get_irq(pdev, PM8XXX_ADC_IRQ_0);
+ if (adc_pmic->adc_irq < 0)
+ return adc_pmic->adc_irq;
+
+ rc = devm_request_irq(&pdev->dev, adc_pmic->adc_irq,
+ pm8xxx_adc_isr,
+ IRQF_TRIGGER_RISING, "pm8xxx_adc_interrupt", adc_pmic);
+ if (rc) {
+ dev_err(&pdev->dev, "failed to request adc irq "
+ "with error %d\n", rc);
+ }
+
+ disable_irq_nosync(adc_pmic->adc_irq);
+
+ adc_pmic->btm_warm_irq = platform_get_irq(pdev, PM8XXX_ADC_IRQ_1);
+ if (adc_pmic->btm_warm_irq < 0)
+ return adc_pmic->btm_warm_irq;
+
+ rc = devm_request_irq(&pdev->dev, adc_pmic->btm_warm_irq,
+ pm8xxx_btm_warm_isr,
+ IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+ "pm8xxx_btm_warm_interrupt", adc_pmic);
+ if (rc) {
+ pr_err("btm warm irq failed %d with interrupt number %d\n",
+ rc, adc_pmic->btm_warm_irq);
+ dev_err(&pdev->dev, "failed to request btm irq\n");
+ }
+
+ disable_irq_nosync(adc_pmic->btm_warm_irq);
+
+ adc_pmic->btm_cool_irq = platform_get_irq(pdev, PM8XXX_ADC_IRQ_2);
+ if (adc_pmic->btm_cool_irq < 0)
+ return adc_pmic->btm_cool_irq;
+
+ rc = devm_request_irq(&pdev->dev, adc_pmic->btm_cool_irq,
+ pm8xxx_btm_cool_isr,
+ IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+ "pm8xxx_btm_cool_interrupt", adc_pmic);
+ if (rc) {
+ pr_err("btm cool irq failed with return %d and number %d\n",
+ rc, adc_pmic->btm_cool_irq);
+ dev_err(&pdev->dev, "failed to request btm irq\n");
+ }
+
+ disable_irq_nosync(adc_pmic->btm_cool_irq);
+ platform_set_drvdata(pdev, adc_pmic);
+ wake_lock_init(&adc_pmic->adc_wakelock, WAKE_LOCK_SUSPEND,
+ "pm8xxx_adc_wakelock");
+ adc_pmic->msm_suspend_check = 0;
+ pmic_adc = adc_pmic;
+
+ INIT_WORK(&adc_pmic->warm_work, pm8xxx_adc_btm_warm_scheduler_fn);
+ INIT_WORK(&adc_pmic->cool_work, pm8xxx_adc_btm_cool_scheduler_fn);
+ create_debugfs_entries();
+ pm8xxx_adc_calib_first_adc = false;
+ pm8xxx_adc_calib_device_init = false;
+ pm8xxx_adc_initialized = true;
+
+ rc = pm8xxx_adc_init_hwmon(pdev);
+ if (rc) {
+ pr_err("pm8xxx adc init hwmon failed with %d\n", rc);
+ dev_err(&pdev->dev, "failed to initialize pm8xxx hwmon adc\n");
+ }
+ adc_pmic->hwmon = hwmon_device_register(adc_pmic->dev);
+ return 0;
+}
+
+static struct platform_driver pm8xxx_adc_driver = {
+ .probe = pm8xxx_adc_probe,
+ .remove = __devexit_p(pm8xxx_adc_teardown),
+ .driver = {
+ .name = PM8XXX_ADC_DEV_NAME,
+ .owner = THIS_MODULE,
+ .pm = PM8XXX_ADC_DEV_PM_OPS,
+ },
+};
+
+static int __init pm8xxx_adc_init(void)
+{
+ return platform_driver_register(&pm8xxx_adc_driver);
+}
+module_init(pm8xxx_adc_init);
+
+static void __exit pm8xxx_adc_exit(void)
+{
+ platform_driver_unregister(&pm8xxx_adc_driver);
+}
+module_exit(pm8xxx_adc_exit);
+
+MODULE_ALIAS("platform:" PM8XXX_ADC_DEV_NAME);
+MODULE_DESCRIPTION("PMIC8921/8018 ADC driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/input/keyboard/pmic8xxx-keypad.c b/drivers/input/keyboard/pmic8xxx-keypad.c
index f0629ce..0866332 100644
--- a/drivers/input/keyboard/pmic8xxx-keypad.c
+++ b/drivers/input/keyboard/pmic8xxx-keypad.c
@@ -710,9 +710,9 @@
return 0;
err_pmic_reg_read:
- free_irq(kp->key_stuck_irq, NULL);
+ free_irq(kp->key_stuck_irq, kp);
err_req_stuck_irq:
- free_irq(kp->key_sense_irq, NULL);
+ free_irq(kp->key_sense_irq, kp);
err_gpio_config:
err_get_irq:
input_free_device(kp->input);
@@ -727,8 +727,8 @@
struct pmic8xxx_kp *kp = platform_get_drvdata(pdev);
device_init_wakeup(&pdev->dev, 0);
- free_irq(kp->key_stuck_irq, NULL);
- free_irq(kp->key_sense_irq, NULL);
+ free_irq(kp->key_stuck_irq, kp);
+ free_irq(kp->key_sense_irq, kp);
input_unregister_device(kp->input);
kfree(kp);
diff --git a/drivers/input/touchscreen/atmel_mxt_ts.c b/drivers/input/touchscreen/atmel_mxt_ts.c
index fc9d579..4d97331 100644
--- a/drivers/input/touchscreen/atmel_mxt_ts.c
+++ b/drivers/input/touchscreen/atmel_mxt_ts.c
@@ -3,6 +3,7 @@
*
* Copyright (C) 2010 Samsung Electronics Co.Ltd
* Author: Joonyoung Shim <jy0922.shim@samsung.com>
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -17,7 +18,7 @@
#include <linux/firmware.h>
#include <linux/i2c.h>
#include <linux/i2c/atmel_mxt_ts.h>
-#include <linux/input/mt.h>
+#include <linux/input.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <linux/regulator/consumer.h>
@@ -180,10 +181,12 @@
#define MXT_VTG_MIN_UV 2700000
#define MXT_VTG_MAX_UV 3300000
#define MXT_ACTIVE_LOAD_UA 15000
+#define MXT_LPM_LOAD_UA 10
#define MXT_I2C_VTG_MIN_UV 1800000
#define MXT_I2C_VTG_MAX_UV 1800000
#define MXT_I2C_LOAD_UA 10000
+#define MXT_I2C_LPM_LOAD_UA 10
/* Define for MXT_GEN_COMMAND */
#define MXT_BOOT_VALUE 0xa5
@@ -196,6 +199,8 @@
#define MXT_FWRESET_TIME 175 /* msec */
+#define MXT_WAKE_TIME 25
+
/* Command to unlock bootloader */
#define MXT_UNLOCK_CMD_MSB 0xaa
#define MXT_UNLOCK_CMD_LSB 0xdc
@@ -229,7 +234,9 @@
#define MXT_MAX_FINGER 10
#define MXT_BUFF_SIZE 100
-#define T7_DATA_SIZE 3
+#define T7_DATA_SIZE 3
+#define MXT_MAX_RW_TRIES 3
+#define MXT_BLOCK_SIZE 256
struct mxt_info {
u8 family_id;
@@ -274,14 +281,14 @@
struct mxt_info info;
struct mxt_finger finger[MXT_MAX_FINGER];
unsigned int irq;
- unsigned int max_x;
- unsigned int max_y;
struct regulator *vcc;
struct regulator *vcc_i2c;
#if defined(CONFIG_HAS_EARLYSUSPEND)
struct early_suspend early_suspend;
#endif
+
u8 t7_data[T7_DATA_SIZE];
+ u16 t7_start_addr;
u8 t9_ctrl;
};
@@ -416,6 +423,7 @@
{
struct i2c_msg xfer[2];
u8 buf[2];
+ int i = 0;
buf[0] = reg & 0xff;
buf[1] = (reg >> 8) & 0xff;
@@ -432,12 +440,14 @@
xfer[1].len = len;
xfer[1].buf = val;
- if (i2c_transfer(client->adapter, xfer, 2) != 2) {
- dev_err(&client->dev, "%s: i2c transfer failed\n", __func__);
- return -EIO;
- }
+ do {
+ if (i2c_transfer(client->adapter, xfer, 2) == 2)
+ return 0;
+ msleep(MXT_WAKE_TIME);
+ } while (++i < MXT_MAX_RW_TRIES);
- return 0;
+ dev_err(&client->dev, "%s: i2c transfer failed\n", __func__);
+ return -EIO;
}
static int mxt_read_reg(struct i2c_client *client, u16 reg, u8 *val)
@@ -445,20 +455,33 @@
return __mxt_read_reg(client, reg, 1, val);
}
+static int __mxt_write_reg(struct i2c_client *client,
+ u16 addr, u16 length, u8 *value)
+{
+ u8 buf[MXT_BLOCK_SIZE + 2];
+ int i, tries = 0;
+
+ if (length > MXT_BLOCK_SIZE)
+ return -EINVAL;
+
+ buf[0] = addr & 0xff;
+ buf[1] = (addr >> 8) & 0xff;
+ for (i = 0; i < length; i++)
+ buf[i + 2] = *value++;
+
+ do {
+ if (i2c_master_send(client, buf, length + 2) == (length + 2))
+ return 0;
+ msleep(MXT_WAKE_TIME);
+ } while (++tries < MXT_MAX_RW_TRIES);
+
+ dev_err(&client->dev, "%s: i2c send failed\n", __func__);
+ return -EIO;
+}
+
static int mxt_write_reg(struct i2c_client *client, u16 reg, u8 val)
{
- u8 buf[3];
-
- buf[0] = reg & 0xff;
- buf[1] = (reg >> 8) & 0xff;
- buf[2] = val;
-
- if (i2c_master_send(client, buf, 3) != 3) {
- dev_err(&client->dev, "%s: i2c send failed\n", __func__);
- return -EIO;
- }
-
- return 0;
+ return __mxt_write_reg(client, reg, 1, &val);
}
static int mxt_read_object_table(struct i2c_client *client,
@@ -539,21 +562,19 @@
if (!finger[id].status)
continue;
- input_mt_slot(input_dev, id);
- input_mt_report_slot_state(input_dev, MT_TOOL_FINGER,
- finger[id].status != MXT_RELEASE);
+ input_report_abs(input_dev, ABS_MT_TOUCH_MAJOR,
+ finger[id].status != MXT_RELEASE ?
+ finger[id].area : 0);
+ input_report_abs(input_dev, ABS_MT_POSITION_X,
+ finger[id].x);
+ input_report_abs(input_dev, ABS_MT_POSITION_Y,
+ finger[id].y);
+ input_mt_sync(input_dev);
- if (finger[id].status != MXT_RELEASE) {
- finger_num++;
- input_report_abs(input_dev, ABS_MT_TOUCH_MAJOR,
- finger[id].area);
- input_report_abs(input_dev, ABS_MT_POSITION_X,
- finger[id].x);
- input_report_abs(input_dev, ABS_MT_POSITION_Y,
- finger[id].y);
- } else {
+ if (finger[id].status == MXT_RELEASE)
finger[id].status = 0;
- }
+ else
+ finger_num++;
}
input_report_key(input_dev, BTN_TOUCH, finger_num > 0);
@@ -593,9 +614,9 @@
x = (message->message[1] << 4) | ((message->message[3] >> 4) & 0xf);
y = (message->message[2] << 4) | ((message->message[3] & 0xf));
- if (data->max_x < 1024)
+ if (data->pdata->x_size < 1024)
x = x >> 2;
- if (data->max_y < 1024)
+ if (data->pdata->y_size < 1024)
y = y >> 2;
area = message->message[4];
@@ -707,54 +728,6 @@
return 0;
}
-static void mxt_handle_pdata(struct mxt_data *data)
-{
- const struct mxt_platform_data *pdata = data->pdata;
- u8 voltage;
-
- /* Set touchscreen lines */
- mxt_write_object(data, MXT_TOUCH_MULTI, MXT_TOUCH_XSIZE,
- pdata->x_line);
- mxt_write_object(data, MXT_TOUCH_MULTI, MXT_TOUCH_YSIZE,
- pdata->y_line);
-
- /* Set touchscreen orient */
- mxt_write_object(data, MXT_TOUCH_MULTI, MXT_TOUCH_ORIENT,
- pdata->orient);
-
- /* Set touchscreen burst length */
- mxt_write_object(data, MXT_TOUCH_MULTI,
- MXT_TOUCH_BLEN, pdata->blen);
-
- /* Set touchscreen threshold */
- mxt_write_object(data, MXT_TOUCH_MULTI,
- MXT_TOUCH_TCHTHR, pdata->threshold);
-
- /* Set touchscreen resolution */
- mxt_write_object(data, MXT_TOUCH_MULTI,
- MXT_TOUCH_XRANGE_LSB, (pdata->x_size - 1) & 0xff);
- mxt_write_object(data, MXT_TOUCH_MULTI,
- MXT_TOUCH_XRANGE_MSB, (pdata->x_size - 1) >> 8);
- mxt_write_object(data, MXT_TOUCH_MULTI,
- MXT_TOUCH_YRANGE_LSB, (pdata->y_size - 1) & 0xff);
- mxt_write_object(data, MXT_TOUCH_MULTI,
- MXT_TOUCH_YRANGE_MSB, (pdata->y_size - 1) >> 8);
-
- /* Set touchscreen voltage */
- if (pdata->voltage) {
- if (pdata->voltage < MXT_VOLTAGE_DEFAULT) {
- voltage = (MXT_VOLTAGE_DEFAULT - pdata->voltage) /
- MXT_VOLTAGE_STEP;
- voltage = 0xff - voltage + 1;
- } else
- voltage = (pdata->voltage - MXT_VOLTAGE_DEFAULT) /
- MXT_VOLTAGE_STEP;
-
- mxt_write_object(data, MXT_SPT_CTECONFIG,
- MXT_CTE_VOLTAGE, voltage);
- }
-}
-
static int mxt_get_info(struct mxt_data *data)
{
struct i2c_client *client = data->client;
@@ -842,10 +815,11 @@
{
struct i2c_client *client = data->client;
struct mxt_info *info = &data->info;
- int error, i;
+ int error;
int timeout_counter = 0;
u8 val;
u8 command_register;
+ struct mxt_object *t7_object;
error = mxt_get_info(data);
if (error)
@@ -870,14 +844,19 @@
return error;
/* Store T7 and T9 locally, used in suspend/resume operations */
- for (i = 0; i < T7_DATA_SIZE; i++) {
- error = mxt_read_object(data, MXT_GEN_POWER, i,
- &data->t7_data[i]);
- if (error < 0) {
- dev_err(&client->dev,
- "failed to save current power state\n");
- return error;
- }
+ t7_object = mxt_get_object(data, MXT_GEN_POWER);
+ if (!t7_object) {
+ dev_err(&client->dev, "Failed to get T7 object\n");
+ return -EINVAL;
+ }
+
+ data->t7_start_addr = t7_object->start_address;
+ error = __mxt_read_reg(client, data->t7_start_addr,
+ T7_DATA_SIZE, data->t7_data);
+ if (error < 0) {
+ dev_err(&client->dev,
+ "failed to save current power state\n");
+ return error;
}
error = mxt_read_object(data, MXT_TOUCH_MULTI, MXT_TOUCH_CTRL,
&data->t9_ctrl);
@@ -886,8 +865,6 @@
return error;
}
- mxt_handle_pdata(data);
-
/* Backup to memory */
mxt_write_object(data, MXT_GEN_COMMAND,
MXT_COMMAND_BACKUPNV,
@@ -937,20 +914,6 @@
return 0;
}
-static void mxt_calc_resolution(struct mxt_data *data)
-{
- unsigned int max_x = data->pdata->x_size - 1;
- unsigned int max_y = data->pdata->y_size - 1;
-
- if (data->pdata->orient & MXT_XY_SWITCH) {
- data->max_x = max_y;
- data->max_y = max_x;
- } else {
- data->max_x = max_x;
- data->max_y = max_y;
- }
-}
-
static ssize_t mxt_object_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
@@ -1110,17 +1073,17 @@
static int mxt_start(struct mxt_data *data)
{
- int i, error;
+ int error;
+
/* restore the old power state values and reenable touch */
- for (i = 0; i < T7_DATA_SIZE; i++) {
- error = mxt_write_object(data, MXT_GEN_POWER, i,
- data->t7_data[i]);
- if (error < 0) {
- dev_err(&data->client->dev,
- "failed to restore old power state\n");
- return error;
- }
+ error = __mxt_write_reg(data->client, data->t7_start_addr,
+ T7_DATA_SIZE, data->t7_data);
+ if (error < 0) {
+ dev_err(&data->client->dev,
+ "failed to restore old power state\n");
+ return error;
}
+
error = mxt_write_object(data,
MXT_TOUCH_MULTI, MXT_TOUCH_CTRL, data->t9_ctrl);
if (error < 0) {
@@ -1133,22 +1096,21 @@
static int mxt_stop(struct mxt_data *data)
{
- int i, error;
- /* configure deep sleep mode and disable touch */
- for (i = 0; i < T7_DATA_SIZE; i++) {
- error = mxt_write_object(data, MXT_GEN_POWER, i, 0);
- if (error < 0) {
- dev_err(&data->client->dev,
- "failed to configure deep sleep mode\n");
- return error;
- }
+ int error;
+ u8 t7_data[T7_DATA_SIZE] = {0};
+
+ /* disable touch and configure deep sleep mode */
+ error = mxt_write_object(data, MXT_TOUCH_MULTI, MXT_TOUCH_CTRL, 0);
+ if (error < 0) {
+ dev_err(&data->client->dev, "failed to disable touch\n");
+ return error;
}
- error = mxt_write_object(data,
- MXT_TOUCH_MULTI, MXT_TOUCH_CTRL, 0);
+ error = __mxt_write_reg(data->client, data->t7_start_addr,
+ T7_DATA_SIZE, t7_data);
if (error < 0) {
dev_err(&data->client->dev,
- "failed to disable touch\n");
+ "failed to configure deep sleep mode\n");
return error;
}
@@ -1217,7 +1179,7 @@
}
}
- msleep(100);
+ msleep(130);
return 0;
@@ -1310,6 +1272,68 @@
}
#ifdef CONFIG_PM
+static int mxt_regulator_lpm(struct mxt_data *data, bool on)
+{
+
+ int rc;
+
+ if (on == false)
+ goto regulator_hpm;
+
+ rc = regulator_set_optimum_mode(data->vcc, MXT_LPM_LOAD_UA);
+ if (rc < 0) {
+ dev_err(&data->client->dev,
+ "Regulator set_opt failed rc=%d\n", rc);
+ goto fail_regulator_lpm;
+ }
+
+ if (data->pdata->i2c_pull_up) {
+ rc = regulator_set_optimum_mode(data->vcc_i2c,
+ MXT_I2C_LPM_LOAD_UA);
+ if (rc < 0) {
+ dev_err(&data->client->dev,
+ "Regulator set_opt failed rc=%d\n", rc);
+ goto fail_regulator_lpm;
+ }
+ }
+
+ return 0;
+
+regulator_hpm:
+
+ rc = regulator_set_optimum_mode(data->vcc, MXT_ACTIVE_LOAD_UA);
+ if (rc < 0) {
+ dev_err(&data->client->dev,
+ "Regulator set_opt failed rc=%d\n", rc);
+ goto fail_regulator_hpm;
+ }
+
+ if (data->pdata->i2c_pull_up) {
+ rc = regulator_set_optimum_mode(data->vcc_i2c, MXT_I2C_LOAD_UA);
+ if (rc < 0) {
+ dev_err(&data->client->dev,
+ "Regulator set_opt failed rc=%d\n", rc);
+ goto fail_regulator_hpm;
+ }
+ }
+
+ return 0;
+
+fail_regulator_lpm:
+ regulator_set_optimum_mode(data->vcc, MXT_ACTIVE_LOAD_UA);
+ if (data->pdata->i2c_pull_up)
+ regulator_set_optimum_mode(data->vcc_i2c, MXT_I2C_LOAD_UA);
+
+ return rc;
+
+fail_regulator_hpm:
+ regulator_set_optimum_mode(data->vcc, MXT_LPM_LOAD_UA);
+ if (data->pdata->i2c_pull_up)
+ regulator_set_optimum_mode(data->vcc_i2c, MXT_I2C_LPM_LOAD_UA);
+
+ return rc;
+}
+
static int mxt_suspend(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
@@ -1322,7 +1346,7 @@
if (input_dev->users) {
error = mxt_stop(data);
if (error < 0) {
- dev_err(&client->dev, "mxt_stop failed in suspend\n");
+ dev_err(dev, "mxt_stop failed in suspend\n");
mutex_unlock(&input_dev->mutex);
return error;
}
@@ -1331,6 +1355,13 @@
mutex_unlock(&input_dev->mutex);
+ /* put regulators in low power mode */
+ error = mxt_regulator_lpm(data, true);
+ if (error < 0) {
+ dev_err(dev, "failed to enter low power mode\n");
+ return error;
+ }
+
return 0;
}
@@ -1340,18 +1371,20 @@
struct mxt_data *data = i2c_get_clientdata(client);
struct input_dev *input_dev = data->input_dev;
int error;
- /* Soft reset */
- mxt_write_object(data, MXT_GEN_COMMAND,
- MXT_COMMAND_RESET, 1);
- mxt_reset_delay(data);
+ /* put regulators in high power mode */
+ error = mxt_regulator_lpm(data, false);
+ if (error < 0) {
+ dev_err(dev, "failed to enter high power mode\n");
+ return error;
+ }
mutex_lock(&input_dev->mutex);
if (input_dev->users) {
error = mxt_start(data);
if (error < 0) {
- dev_err(&client->dev, "mxt_start failed in resume\n");
+ dev_err(dev, "mxt_start failed in resume\n");
mutex_unlock(&input_dev->mutex);
return error;
}
@@ -1416,26 +1449,23 @@
data->pdata = pdata;
data->irq = client->irq;
- mxt_calc_resolution(data);
-
__set_bit(EV_ABS, input_dev->evbit);
__set_bit(EV_KEY, input_dev->evbit);
__set_bit(BTN_TOUCH, input_dev->keybit);
/* For single touch */
input_set_abs_params(input_dev, ABS_X,
- 0, data->max_x, 0, 0);
+ 0, data->pdata->x_size, 0, 0);
input_set_abs_params(input_dev, ABS_Y,
- 0, data->max_y, 0, 0);
+ 0, data->pdata->y_size, 0, 0);
/* For multi touch */
- input_mt_init_slots(input_dev, MXT_MAX_FINGER);
input_set_abs_params(input_dev, ABS_MT_TOUCH_MAJOR,
0, MXT_MAX_AREA, 0, 0);
input_set_abs_params(input_dev, ABS_MT_POSITION_X,
- 0, data->max_x, 0, 0);
+ 0, data->pdata->x_size, 0, 0);
input_set_abs_params(input_dev, ABS_MT_POSITION_Y,
- 0, data->max_y, 0, 0);
+ 0, data->pdata->y_size, 0, 0);
input_set_drvdata(input_dev, data);
i2c_set_clientdata(client, data);
diff --git a/drivers/media/radio/radio-iris.c b/drivers/media/radio/radio-iris.c
index 2a192db..179f465 100644
--- a/drivers/media/radio/radio-iris.c
+++ b/drivers/media/radio/radio-iris.c
@@ -392,7 +392,16 @@
.minimum = 0,
.maximum = 2,
},
-
+ {
+ .id = V4L2_CID_PRIVATE_IRIS_READ_DEFAULT,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .name = "Read default",
+ },
+ {
+ .id = V4L2_CID_PRIVATE_IRIS_WRITE_DEFAULT,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .name = "Write default",
+ },
};
static void iris_q_event(struct iris_device *radio,
@@ -860,7 +869,7 @@
struct hci_fm_def_data_rd_req *def_data_rd =
(struct hci_fm_def_data_rd_req *) param;
- opcode = hci_opcode_pack(HCI_OGF_FM_RECV_CTRL_CMD_REQ,
+ opcode = hci_opcode_pack(HCI_OGF_FM_COMMON_CTRL_CMD_REQ,
HCI_OCF_FM_DEFAULT_DATA_READ);
return radio_hci_send_cmd(hdev, opcode, sizeof((*def_data_rd)),
def_data_rd);
@@ -873,7 +882,7 @@
struct hci_fm_def_data_wr_req *def_data_wr =
(struct hci_fm_def_data_wr_req *) param;
- opcode = hci_opcode_pack(HCI_OGF_FM_RECV_CTRL_CMD_REQ,
+ opcode = hci_opcode_pack(HCI_OGF_FM_COMMON_CTRL_CMD_REQ,
HCI_OCF_FM_DEFAULT_DATA_WRITE);
return radio_hci_send_cmd(hdev, opcode, sizeof((*def_data_wr)),
def_data_wr);
@@ -1212,7 +1221,6 @@
{
int ret = 0;
struct hci_fm_def_data_rd_req *def_data_rd = arg;
-
ret = radio_hci_request(hdev, hci_def_data_read_req, (unsigned
long)def_data_rd, RADIO_HCI_TIMEOUT);
@@ -1224,7 +1232,6 @@
{
int ret = 0;
struct hci_fm_def_data_wr_req *def_data_wr = arg;
-
ret = radio_hci_request(hdev, hci_def_data_write_req, (unsigned
long)def_data_wr, RADIO_HCI_TIMEOUT);
@@ -1596,6 +1603,32 @@
}
+
+static void hci_cc_riva_read_default_rsp(struct radio_hci_dev *hdev,
+ struct sk_buff *skb)
+{
+ struct iris_device *radio = video_get_drvdata(video_get_dev());
+ __u8 status = *((__u8 *) skb->data);
+ __u8 len;
+ char *data;
+
+ if (status)
+ return;
+ len = skb->data[1];
+ data = kmalloc(len+2, GFP_ATOMIC);
+ if (!data) {
+ FMDERR("Memory allocation failed");
+ return;
+ }
+
+ data[0] = status;
+ data[1] = len;
+ memcpy(&data[2], &skb->data[DEFAULT_DATA_OFFSET], len);
+ iris_q_evt_data(radio, data, len+2, IRIS_BUF_RD_DEFAULT);
+ radio_hci_req_complete(hdev, status);
+ kfree(data);
+}
+
static void hci_cc_ssbi_peek_rsp(struct radio_hci_dev *hdev,
struct sk_buff *skb)
{
@@ -1674,6 +1707,8 @@
case hci_trans_ctrl_cmd_op_pack(HCI_OCF_FM_RDS_RT_REQ):
case hci_trans_ctrl_cmd_op_pack(HCI_OCF_FM_RDS_PS_REQ):
case hci_common_cmd_op_pack(HCI_OCF_FM_DEFAULT_DATA_WRITE):
+ hci_cc_rsp(hdev, skb);
+ break;
case hci_common_cmd_op_pack(HCI_OCF_FM_RESET):
case hci_diagnostic_cmd_op_pack(HCI_OCF_FM_SSBI_POKE_REG):
case hci_diagnostic_cmd_op_pack(HCI_OCF_FM_POKE_DATA):
@@ -1705,6 +1740,9 @@
break;
case hci_common_cmd_op_pack(HCI_OCF_FM_DEFAULT_DATA_READ):
+ hci_cc_riva_read_default_rsp(hdev, skb);
+ break;
+
case hci_diagnostic_cmd_op_pack(HCI_OCF_FM_PEEK_DATA):
hci_cc_riva_peek_rsp(hdev, skb);
break;
@@ -2281,6 +2319,30 @@
return retval;
}
+static int iris_vidioc_g_ext_ctrls(struct file *file, void *priv,
+ struct v4l2_ext_controls *ctrl)
+{
+ int retval = 0;
+ char *data = NULL;
+ struct iris_device *radio = video_get_drvdata(video_devdata(file));
+ struct hci_fm_def_data_rd_req default_data_rd;
+
+ switch ((ctrl->controls[0]).id) {
+ case V4L2_CID_PRIVATE_IRIS_READ_DEFAULT:
+ data = (ctrl->controls[0]).string;
+ memset(&default_data_rd, 0, sizeof(default_data_rd));
+ if (copy_from_user(&default_data_rd.mode, data,
+ sizeof(default_data_rd)))
+ return -EFAULT;
+ retval = hci_def_data_read(&default_data_rd, radio->fm_hdev);
+ break;
+ default:
+ retval = -EINVAL;
+ }
+
+ return retval;
+}
+
static int iris_vidioc_s_ext_ctrls(struct file *file, void *priv,
struct v4l2_ext_controls *ctrl)
{
@@ -2288,6 +2350,7 @@
int bytes_to_copy;
struct hci_fm_tx_ps tx_ps;
struct hci_fm_tx_rt tx_rt;
+ struct hci_fm_def_data_wr_req default_data;
struct iris_device *radio = video_get_drvdata(video_devdata(file));
char *data = NULL;
@@ -2333,6 +2396,13 @@
retval = radio_hci_request(radio->fm_hdev, hci_trans_rt_req,
(unsigned long)&tx_rt, RADIO_HCI_TIMEOUT);
break;
+ case V4L2_CID_PRIVATE_IRIS_WRITE_DEFAULT:
+ data = (ctrl->controls[0]).string;
+ memset(&default_data, 0, sizeof(default_data));
+ if (copy_from_user(&default_data, data, sizeof(default_data)))
+ return -EFAULT;
+ retval = hci_def_data_write(&default_data, radio->fm_hdev);
+ break;
default:
FMDBG("Shouldn't reach here\n");
retval = -1;
@@ -2850,6 +2920,7 @@
.vidioc_dqbuf = iris_vidioc_dqbuf,
.vidioc_g_fmt_type_private = iris_vidioc_g_fmt_type_private,
.vidioc_s_ext_ctrls = iris_vidioc_s_ext_ctrls,
+ .vidioc_g_ext_ctrls = iris_vidioc_g_ext_ctrls,
};
static const struct v4l2_file_operations iris_fops = {
diff --git a/drivers/media/radio/radio-tavarua.c b/drivers/media/radio/radio-tavarua.c
index 36bad1b..49bc46c 100644
--- a/drivers/media/radio/radio-tavarua.c
+++ b/drivers/media/radio/radio-tavarua.c
@@ -2786,20 +2786,14 @@
FMDBG("turning on ..\n");
retval = tavarua_start(radio, ctrl->value);
if (retval >= 0) {
- FMDBG("Setting audio path ...\n");
- retval = tavarua_set_audio_path(
- TAVARUA_AUDIO_OUT_DIGITAL_ON,
- TAVARUA_AUDIO_OUT_ANALOG_OFF);
- if (retval < 0) {
- FMDERR("Error in tavarua_set_audio_path"
- " %d\n", retval);
- }
- /* Enabling 'SoftMute' and 'SignalBlending' features */
- value = (radio->registers[IOCTRL] |
+ /* Enabling 'SoftMute' & 'SignalBlending' */
+ value = (radio->registers[IOCTRL] |
IOC_SFT_MUTE | IOC_SIG_BLND);
- retval = tavarua_write_register(radio, IOCTRL, value);
- if (retval < 0)
- FMDBG("SMute and SBlending not enabled\n");
+ retval = tavarua_write_register(radio,
+ IOCTRL, value);
+ if (retval < 0)
+ FMDBG("SMute and SBlending"
+ "not enabled\n");
}
}
/* check if off */
@@ -2822,6 +2816,28 @@
}
}
break;
+ case V4L2_CID_PRIVATE_TAVARUA_SET_AUDIO_PATH:
+ FMDBG("Setting audio path ...\n");
+ if (ctrl->value == FM_DIGITAL_PATH) {
+ FMDBG("Digital audio path enabled ...\n");
+ retval = tavarua_set_audio_path(
+ TAVARUA_AUDIO_OUT_DIGITAL_ON,
+ TAVARUA_AUDIO_OUT_ANALOG_OFF);
+ if (retval < 0) {
+ FMDERR("Error in tavarua_set_audio_path"
+ " %d\n", retval);
+ }
+ } else if (ctrl->value == FM_ANALOG_PATH) {
+ FMDBG("Analog audio path enabled ...\n");
+ retval = tavarua_set_audio_path(
+ TAVARUA_AUDIO_OUT_ANALOG_ON,
+ TAVARUA_AUDIO_OUT_DIGITAL_OFF);
+ if (retval < 0) {
+ FMDERR("Error in tavarua_set_audio_path"
+ " %d\n", retval);
+ }
+ }
+ break;
case V4L2_CID_PRIVATE_TAVARUA_REGION:
retval = tavarua_set_region(radio, ctrl->value);
break;
diff --git a/drivers/media/video/msm/msm.c b/drivers/media/video/msm/msm.c
index 727b751..74534af 100644
--- a/drivers/media/video/msm/msm.c
+++ b/drivers/media/video/msm/msm.c
@@ -1398,10 +1398,8 @@
}
mutex_lock(&pcam->vid_lock);
for (i = 0; i < MSM_DEV_INST_MAX; i++) {
- if (pcam->dev_inst[i] == NULL) {
- mutex_unlock(&pcam->vid_lock);
+ if (pcam->dev_inst[i] == NULL)
break;
- }
}
/* if no instance is available, return error */
if (i == MSM_DEV_INST_MAX) {
diff --git a/drivers/media/video/msm/msm.h b/drivers/media/video/msm/msm.h
index bf75e8b..083fc57 100644
--- a/drivers/media/video/msm/msm.h
+++ b/drivers/media/video/msm/msm.h
@@ -91,6 +91,11 @@
uint32_t vb;
};
+struct isp_msg_event {
+ uint32_t msg_id;
+ uint32_t sof_count;
+};
+
struct isp_msg_output {
uint8_t output_id;
struct msm_free_buf buf;
diff --git a/drivers/media/video/msm/msm_io_8960.c b/drivers/media/video/msm/msm_io_8960.c
index 45871bc..0e4429e 100644
--- a/drivers/media/video/msm/msm_io_8960.c
+++ b/drivers/media/video/msm/msm_io_8960.c
@@ -27,6 +27,7 @@
#define DBG_CSID 0
#define DBG_CSIPHY 0
+#define BUFF_SIZE_128 128
/* MIPI CSI PHY registers */
#define MIPI_CSIPHY_LNn_CFG1_ADDR 0x0
@@ -194,7 +195,7 @@
void msm_io_dump(void __iomem *addr, int size)
{
- char line_str[128], *p_str;
+ char line_str[BUFF_SIZE_128], *p_str;
int i;
u32 *p = (u32 *) addr;
u32 data;
@@ -203,11 +204,11 @@
p_str = line_str;
for (i = 0; i < size/4; i++) {
if (i % 4 == 0) {
- sprintf(p_str, "%08x: ", (u32) p);
+ snprintf(p_str, 12, "%08x: ", (u32) p);
p_str += 10;
}
data = readl_relaxed(p++);
- sprintf(p_str, "%08x ", data);
+ snprintf(p_str, 12, "%08x ", data);
p_str += 9;
if ((i + 1) % 4 == 0) {
CDBG("%s\n", line_str);
diff --git a/drivers/media/video/msm/msm_io_8x60.c b/drivers/media/video/msm/msm_io_8x60.c
index 5de800f..2262aa4 100644
--- a/drivers/media/video/msm/msm_io_8x60.c
+++ b/drivers/media/video/msm/msm_io_8x60.c
@@ -573,8 +573,6 @@
int rc = 0;
struct msm_camera_sensor_info *sinfo = pdev->dev.platform_data;
struct msm_camera_device_platform_data *camdev = sinfo->pdata;
- uint32_t val;
-
camio_dev = pdev;
camio_ext = camdev->ioext;
camio_clk = camdev->ioclk;
@@ -606,22 +604,6 @@
if (rc < 0)
goto csi_irq_fail;
- msleep(10);
- val = (20 <<
- MIPI_PHY_D0_CONTROL2_SETTLE_COUNT_SHFT) |
- (0x0F << MIPI_PHY_D0_CONTROL2_HS_TERM_IMP_SHFT) |
- (0x0 << MIPI_PHY_D0_CONTROL2_LP_REC_EN_SHFT) |
- (0x1 << MIPI_PHY_D0_CONTROL2_ERR_SOT_HS_EN_SHFT);
- CDBG("%s MIPI_PHY_D0_CONTROL2 val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_D0_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D1_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D2_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D3_CONTROL2);
-
- val = (0x0F << MIPI_PHY_CL_CONTROL_HS_TERM_IMP_SHFT) |
- (0x0 << MIPI_PHY_CL_CONTROL_LP_REC_EN_SHFT);
- CDBG("%s MIPI_PHY_CL_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
return 0;
csi_irq_fail:
@@ -642,30 +624,17 @@
return rc;
}
-void msm_camio_disable(struct platform_device *pdev)
+static void msm_camio_csi_disable(void)
{
uint32_t val;
- val = (0x0 << MIPI_CALIBRATION_CONTROL_SWCAL_CAL_EN_SHFT) |
- (0x0 <<
- MIPI_CALIBRATION_CONTROL_SWCAL_STRENGTH_OVERRIDE_EN_SHFT) |
- (0x0 << MIPI_CALIBRATION_CONTROL_CAL_SW_HW_MODE_SHFT) |
- (0x0 << MIPI_CALIBRATION_CONTROL_MANUAL_OVERRIDE_EN_SHFT);
- CDBG("%s MIPI_CALIBRATION_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_CALIBRATION_CONTROL);
- val = (20 <<
- MIPI_PHY_D0_CONTROL2_SETTLE_COUNT_SHFT) |
- (0x0F << MIPI_PHY_D0_CONTROL2_HS_TERM_IMP_SHFT) |
- (0x0 << MIPI_PHY_D0_CONTROL2_LP_REC_EN_SHFT) |
- (0x1 << MIPI_PHY_D0_CONTROL2_ERR_SOT_HS_EN_SHFT);
+ val = 0x0;
CDBG("%s MIPI_PHY_D0_CONTROL2 val=0x%x\n", __func__, val);
msm_io_w(val, csibase + MIPI_PHY_D0_CONTROL2);
msm_io_w(val, csibase + MIPI_PHY_D1_CONTROL2);
msm_io_w(val, csibase + MIPI_PHY_D2_CONTROL2);
msm_io_w(val, csibase + MIPI_PHY_D3_CONTROL2);
- val = (0x0F << MIPI_PHY_CL_CONTROL_HS_TERM_IMP_SHFT) |
- (0x0 << MIPI_PHY_CL_CONTROL_LP_REC_EN_SHFT);
CDBG("%s MIPI_PHY_CL_CONTROL val=0x%x\n", __func__, val);
msm_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
msleep(10);
@@ -681,8 +650,12 @@
csi_free_irq();
iounmap(csibase);
release_mem_region(camio_ext.csiphy, camio_ext.csisz);
+}
+void msm_camio_disable(struct platform_device *pdev)
+{
+ CDBG("disable mipi\n");
+ msm_camio_csi_disable();
CDBG("disable clocks\n");
-
msm_camio_clk_disable(CAMIO_CSI0_VFE_CLK);
msm_camio_clk_disable(CAMIO_CSI0_CLK);
msm_camio_clk_disable(CAMIO_CSI1_VFE_CLK);
@@ -755,8 +728,9 @@
{
int rc = 0;
uint32_t val = 0;
+ int i;
- CDBG("msm_camio_csi_config \n");
+ CDBG("msm_camio_csi_config\n");
/* SOT_ECC_EN enable error correction for SYNC (data-lane) */
msm_io_w(0x4, csibase + MIPI_PHY_CONTROL);
@@ -776,15 +750,6 @@
CDBG("%s MIPI_PROTOCOL_CONTROL val=0x%x\n", __func__, val);
msm_io_w(val, csibase + MIPI_PROTOCOL_CONTROL);
- /* SW CAL EN */
- val = (0x1 << MIPI_CALIBRATION_CONTROL_SWCAL_CAL_EN_SHFT) |
- (0x1 <<
- MIPI_CALIBRATION_CONTROL_SWCAL_STRENGTH_OVERRIDE_EN_SHFT) |
- (0x1 << MIPI_CALIBRATION_CONTROL_CAL_SW_HW_MODE_SHFT) |
- (0x1 << MIPI_CALIBRATION_CONTROL_MANUAL_OVERRIDE_EN_SHFT);
- CDBG("%s MIPI_CALIBRATION_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_CALIBRATION_CONTROL);
-
/* settle_cnt is very sensitive to speed!
increase this value to run at higher speeds */
val = (csi_params->settle_cnt <<
@@ -793,11 +758,8 @@
(0x1 << MIPI_PHY_D0_CONTROL2_LP_REC_EN_SHFT) |
(0x1 << MIPI_PHY_D0_CONTROL2_ERR_SOT_HS_EN_SHFT);
CDBG("%s MIPI_PHY_D0_CONTROL2 val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_D0_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D1_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D2_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D3_CONTROL2);
-
+ for (i = 0; i < csi_params->lane_cnt; i++)
+ msm_io_w(val, csibase + MIPI_PHY_D0_CONTROL2 + i * 4);
val = (0x0F << MIPI_PHY_CL_CONTROL_HS_TERM_IMP_SHFT) |
(0x1 << MIPI_PHY_CL_CONTROL_LP_REC_EN_SHFT);
diff --git a/drivers/media/video/msm/msm_isp.c b/drivers/media/video/msm/msm_isp.c
index d914404..6983d70 100644
--- a/drivers/media/video/msm/msm_isp.c
+++ b/drivers/media/video/msm/msm_isp.c
@@ -157,7 +157,7 @@
if (notification == NOTIFY_VFE_BUF_EVT)
return msm_isp_notify_VFE_BUF_EVT(sd, arg);
- isp_event = kzalloc(sizeof(struct msm_isp_event_ctrl), GFP_KERNEL);
+ isp_event = kzalloc(sizeof(struct msm_isp_event_ctrl), GFP_ATOMIC);
if (!isp_event) {
pr_err("%s Insufficient memory. return", __func__);
return -ENOMEM;
@@ -172,9 +172,13 @@
isp_event->isp_data.isp_msg.len = 0;
switch (notification) {
- case NOTIFY_ISP_MSG_EVT:
- isp_event->isp_data.isp_msg.msg_id = (uint32_t)arg;
+ case NOTIFY_ISP_MSG_EVT: {
+ struct isp_msg_event *isp_msg = (struct isp_msg_event *)arg;
+
+ isp_event->isp_data.isp_msg.msg_id = isp_msg->msg_id;
+ isp_event->isp_data.isp_msg.frame_id = isp_msg->sof_count;
break;
+ }
case NOTIFY_VFE_MSG_OUT: {
uint8_t msgid;
struct isp_msg_output *isp_output =
@@ -202,6 +206,8 @@
if (!rc) {
isp_event->isp_data.isp_msg.msg_id =
isp_output->output_id;
+ isp_event->isp_data.isp_msg.frame_id =
+ isp_output->frameCounter;
buf = isp_output->buf;
msm_mctl_buf_done(pmctl, msgid,
&buf, isp_output->frameCounter);
@@ -213,6 +219,8 @@
struct isp_msg_stats *isp_stats = (struct isp_msg_stats *)arg;
isp_event->isp_data.isp_msg.msg_id = isp_stats->id;
+ isp_event->isp_data.isp_msg.frame_id =
+ isp_stats->frameCounter;
stats.buffer = msm_pmem_stats_ptov_lookup(&pmctl->sync,
isp_stats->buffer,
&(stats.fd));
diff --git a/drivers/media/video/msm/msm_mctl_pp.c b/drivers/media/video/msm/msm_mctl_pp.c
index 7040c29..4f82d32 100644
--- a/drivers/media/video/msm/msm_mctl_pp.c
+++ b/drivers/media/video/msm/msm_mctl_pp.c
@@ -43,7 +43,7 @@
struct v4l2_event v4l2_evt;
struct msm_isp_event_ctrl *isp_event;
isp_event = kzalloc(sizeof(struct msm_isp_event_ctrl),
- GFP_KERNEL);
+ GFP_ATOMIC);
if (!isp_event) {
pr_err("%s Insufficient memory. return", __func__);
return -ENOMEM;
@@ -581,7 +581,7 @@
struct msm_mctl_pp_event_info *pp_event_info;
struct msm_isp_event_ctrl *isp_event;
isp_event = kzalloc(sizeof(struct msm_isp_event_ctrl),
- GFP_KERNEL);
+ GFP_ATOMIC);
if (!isp_event) {
pr_err("%s Insufficient memory.", __func__);
return -ENOMEM;
diff --git a/drivers/media/video/msm/msm_vfe32.c b/drivers/media/video/msm/msm_vfe32.c
index ea70ce5..219e504 100644
--- a/drivers/media/video/msm/msm_vfe32.c
+++ b/drivers/media/video/msm/msm_vfe32.c
@@ -1121,6 +1121,19 @@
vfe32_program_dmi_cfg(NO_MEM_SELECTED);
}
+static void vfe32_send_isp_msg(
+ struct vfe32_ctrl_type *vctrl,
+ uint32_t isp_msg_id)
+{
+ struct isp_msg_event isp_msg_evt;
+
+ isp_msg_evt.msg_id = isp_msg_id;
+ isp_msg_evt.sof_count = vfe32_ctrl->vfeFrameId;
+ v4l2_subdev_notify(vctrl->subdev,
+ NOTIFY_ISP_MSG_EVT,
+ (void *)&isp_msg_evt);
+}
+
static int vfe32_proc_general(struct msm_isp_cmd *cmd)
{
int i , rc = 0;
@@ -2088,8 +2101,7 @@
CDBG("stop video triggered .\n");
}
if (vfe32_ctrl->start_ack_pending == TRUE) {
- v4l2_subdev_notify(vfe32_ctrl->subdev, NOTIFY_ISP_MSG_EVT,
- (void *)MSG_ID_START_ACK);
+ vfe32_send_isp_msg(vfe32_ctrl, MSG_ID_START_ACK);
vfe32_ctrl->start_ack_pending = FALSE;
} else {
if (vfe32_ctrl->recording_state ==
@@ -2102,9 +2114,7 @@
vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
} else if (vfe32_ctrl->recording_state ==
VFE_REC_STATE_STOPPED) {
- v4l2_subdev_notify(vfe32_ctrl->subdev,
- NOTIFY_ISP_MSG_EVT,
- (void *)MSG_ID_STOP_REC_ACK);
+ vfe32_send_isp_msg(vfe32_ctrl, MSG_ID_STOP_REC_ACK);
vfe32_ctrl->recording_state = VFE_REC_STATE_IDLE;
}
spin_lock_irqsave(&vfe32_ctrl->update_ack_lock, flags);
@@ -2112,9 +2122,7 @@
vfe32_ctrl->update_ack_pending = FALSE;
spin_unlock_irqrestore(
&vfe32_ctrl->update_ack_lock, flags);
- v4l2_subdev_notify(vfe32_ctrl->subdev,
- NOTIFY_ISP_MSG_EVT,
- (void *)MSG_ID_UPDATE_ACK);
+ vfe32_send_isp_msg(vfe32_ctrl, MSG_ID_UPDATE_ACK);
} else {
spin_unlock_irqrestore(
&vfe32_ctrl->update_ack_lock, flags);
@@ -2195,9 +2203,7 @@
if (vfe32_ctrl->stop_ack_pending) {
vfe32_ctrl->stop_ack_pending = FALSE;
spin_unlock_irqrestore(&vfe32_ctrl->stop_flag_lock, flags);
- v4l2_subdev_notify(vfe32_ctrl->subdev,
- NOTIFY_ISP_MSG_EVT,
- (void *)MSG_ID_STOP_ACK);
+ vfe32_send_isp_msg(vfe32_ctrl, MSG_ID_STOP_ACK);
} else {
spin_unlock_irqrestore(&vfe32_ctrl->stop_flag_lock, flags);
/* this is from reset command. */
@@ -2205,9 +2211,7 @@
/* reload all write masters. (frame & line)*/
msm_io_w(0x7FFF, vfe32_ctrl->vfebase + VFE_BUS_CMD);
- v4l2_subdev_notify(vfe32_ctrl->subdev,
- NOTIFY_ISP_MSG_EVT,
- (void *)MSG_ID_RESET_ACK);
+ vfe32_send_isp_msg(vfe32_ctrl, MSG_ID_RESET_ACK);
}
}
@@ -2217,9 +2221,7 @@
if (vfe32_ctrl->operation_mode ==
VFE_MODE_OF_OPERATION_RAW_SNAPSHOT) {
if (vfe32_ctrl->start_ack_pending) {
- v4l2_subdev_notify(vfe32_ctrl->subdev,
- NOTIFY_ISP_MSG_EVT,
- (void *)MSG_ID_START_ACK);
+ vfe32_send_isp_msg(vfe32_ctrl, MSG_ID_START_ACK);
vfe32_ctrl->start_ack_pending = FALSE;
}
vfe32_ctrl->vfe_capture_count--;
@@ -2231,11 +2233,10 @@
vfe32_ctrl->vfebase + VFE_CAMIF_COMMAND);
}
} /* if raw snapshot mode. */
-
- v4l2_subdev_notify(vfe32_ctrl->subdev,
- NOTIFY_ISP_MSG_EVT,
- (void *)MSG_ID_SOF_ACK);
vfe32_ctrl->vfeFrameId++;
+ if (vfe32_ctrl->vfeFrameId == 0)
+ vfe32_ctrl->vfeFrameId = 1; /* wrapped back */
+ vfe32_send_isp_msg(vfe32_ctrl, MSG_ID_SOF_ACK);
CDBG("camif_sof_irq, frameId = %d\n", vfe32_ctrl->vfeFrameId);
if (vfe32_ctrl->sync_timer_state) {
@@ -2256,9 +2257,7 @@
temp = (uint32_t *)(vfe32_ctrl->vfebase + VFE_CAMIF_STATUS);
camifStatus = msm_io_r(temp);
pr_err("camifStatus = 0x%x\n", camifStatus);
- v4l2_subdev_notify(vfe32_ctrl->subdev,
- NOTIFY_ISP_MSG_EVT,
- (void *)MSG_ID_CAMIF_ERROR);
+ vfe32_send_isp_msg(vfe32_ctrl, MSG_ID_CAMIF_ERROR);
}
if (errStatus & VFE32_IMASK_BHIST_OVWR)
@@ -2881,9 +2880,8 @@
CAMIF_COMMAND_STOP_IMMEDIATELY,
vfe32_ctrl->vfebase +
VFE_CAMIF_COMMAND);
- v4l2_subdev_notify(vfe32_ctrl->subdev,
- NOTIFY_ISP_MSG_EVT,
- (void *)MSG_ID_SNAPSHOT_DONE);
+ vfe32_send_isp_msg(vfe32_ctrl,
+ MSG_ID_SNAPSHOT_DONE);
}
}
/* then process stats irq. */
@@ -2930,22 +2928,19 @@
if (qcmd->vfeInterruptStatus0 &
VFE_IRQ_STATUS0_SYNC_TIMER0) {
CDBG("SYNC_TIMER 0 irq occured.\n");
- v4l2_subdev_notify(vfe32_ctrl->subdev,
- NOTIFY_ISP_MSG_EVT, (void *)
+ vfe32_send_isp_msg(vfe32_ctrl,
MSG_ID_SYNC_TIMER0_DONE);
}
if (qcmd->vfeInterruptStatus0 &
VFE_IRQ_STATUS0_SYNC_TIMER1) {
CDBG("SYNC_TIMER 1 irq occured.\n");
- v4l2_subdev_notify(vfe32_ctrl->subdev,
- NOTIFY_ISP_MSG_EVT, (void *)
+ vfe32_send_isp_msg(vfe32_ctrl,
MSG_ID_SYNC_TIMER1_DONE);
}
if (qcmd->vfeInterruptStatus0 &
VFE_IRQ_STATUS0_SYNC_TIMER2) {
CDBG("SYNC_TIMER 2 irq occured.\n");
- v4l2_subdev_notify(vfe32_ctrl->subdev,
- NOTIFY_ISP_MSG_EVT, (void *)
+ vfe32_send_isp_msg(vfe32_ctrl,
MSG_ID_SYNC_TIMER2_DONE);
}
}
diff --git a/drivers/media/video/msm/sensors/imx074_v4l2.c b/drivers/media/video/msm/sensors/imx074_v4l2.c
index 3360ac8..99cc2d4 100644
--- a/drivers/media/video/msm/sensors/imx074_v4l2.c
+++ b/drivers/media/video/msm/sensors/imx074_v4l2.c
@@ -153,14 +153,18 @@
.y_output = 0xC30,
.line_length_pclk = 0x1178,
.frame_length_lines = 0xC90,
- .pixel_clk = 182400000,
+ .vt_pixel_clk = 182400000,
+ .op_pixel_clk = 182400000,
+ .binning_factor = 1,
},
{
.x_output = 0x838,
.y_output = 0x618,
.line_length_pclk = 0x1178,
.frame_length_lines = 0x62D,
- .pixel_clk = 216000000,
+ .vt_pixel_clk = 216000000,
+ .op_pixel_clk = 216000000,
+ .binning_factor = 1,
},
};
diff --git a/drivers/media/video/msm/sensors/msm_sensor.c b/drivers/media/video/msm/sensors/msm_sensor.c
index b9b37e3..19cf8c7 100644
--- a/drivers/media/video/msm/sensors/msm_sensor.c
+++ b/drivers/media/video/msm/sensors/msm_sensor.c
@@ -155,13 +155,15 @@
int32_t rc = 0;
s_ctrl->fps_divider = fps->fps_div;
- total_lines_per_frame = (uint16_t)
- ((s_ctrl->curr_frame_length_lines) *
- s_ctrl->fps_divider/Q10);
+ if (s_ctrl->curr_res != MSM_SENSOR_INVALID_RES) {
+ total_lines_per_frame = (uint16_t)
+ ((s_ctrl->curr_frame_length_lines) *
+ s_ctrl->fps_divider/Q10);
- rc = msm_camera_i2c_write(s_ctrl->sensor_i2c_client,
+ rc = msm_camera_i2c_write(s_ctrl->sensor_i2c_client,
s_ctrl->sensor_output_reg_addr->frame_length_lines,
total_lines_per_frame, MSM_CAMERA_I2C_WORD_DATA);
+ }
return rc;
}
@@ -249,7 +251,7 @@
v4l2_subdev_notify(s_ctrl->sensor_v4l2_subdev,
NOTIFY_PCLK_CHANGE, &s_ctrl->msm_sensor_reg->
- output_settings[res].pixel_clk);
+ output_settings[res].op_pixel_clk);
v4l2_subdev_notify(s_ctrl->sensor_v4l2_subdev,
NOTIFY_ISPIF_STREAM, (void *)ISPIF_STREAM(
PIX0, ISPIF_ON_FRAME_BOUNDARY));
diff --git a/drivers/media/video/msm/sensors/ov2720.c b/drivers/media/video/msm/sensors/ov2720.c
index 4c3370a..bdad57c 100644
--- a/drivers/media/video/msm/sensors/ov2720.c
+++ b/drivers/media/video/msm/sensors/ov2720.c
@@ -310,21 +310,27 @@
.y_output = 0x444,
.line_length_pclk = 0x85c,
.frame_length_lines = 0x460,
- .pixel_clk = 72000000,
+ .vt_pixel_clk = 72000000,
+ .op_pixel_clk = 72000000,
+ .binning_factor = 1,
},
{
.x_output = 0x510,
.y_output = 0x278,
.line_length_pclk = 0x85c,
.frame_length_lines = 0x460,
- .pixel_clk = 72000000,
+ .vt_pixel_clk = 72000000,
+ .op_pixel_clk = 72000000,
+ .binning_factor = 1,
},
{
.x_output = 0x298,
.y_output = 0x1F2,
.line_length_pclk = 0x85c,
.frame_length_lines = 0x460,
- .pixel_clk = 72000000,
+ .vt_pixel_clk = 72000000,
+ .op_pixel_clk = 72000000,
+ .binning_factor = 1,
},
};
diff --git a/drivers/mfd/pm8018-core.c b/drivers/mfd/pm8018-core.c
index 4dfc4cf..528f232 100644
--- a/drivers/mfd/pm8018-core.c
+++ b/drivers/mfd/pm8018-core.c
@@ -21,6 +21,7 @@
#include <linux/mfd/core.h>
#include <linux/mfd/pm8xxx/pm8018.h>
#include <linux/mfd/pm8xxx/core.h>
+#include <linux/leds-pm8xxx.h>
/* PMIC PM8018 SSBI Addresses */
@@ -39,6 +40,9 @@
#define PM8018_VERSION_VALUE 0x08F0
#define PM8018_REVISION_MASK 0x000F
+#define REG_PM8018_PON_CNTRL_3 0x01D
+#define PM8018_RESTART_REASON_MASK 0x07
+
#define SINGLE_IRQ_RESOURCE(_name, _irq) \
{ \
.name = _name, \
@@ -142,6 +146,19 @@
.num_resources = ARRAY_SIZE(gpio_cell_resources),
};
+static const struct resource adc_cell_resources[] __devinitconst = {
+ SINGLE_IRQ_RESOURCE(NULL, PM8018_ADC_EOC_USR_IRQ),
+ SINGLE_IRQ_RESOURCE(NULL, PM8018_ADC_BATT_TEMP_WARM_IRQ),
+ SINGLE_IRQ_RESOURCE(NULL, PM8018_ADC_BATT_TEMP_COLD_IRQ),
+};
+
+static struct mfd_cell adc_cell __devinitdata = {
+ .name = PM8XXX_ADC_DEV_NAME,
+ .id = -1,
+ .resources = adc_cell_resources,
+ .num_resources = ARRAY_SIZE(adc_cell_resources),
+};
+
static const struct resource mpp_cell_resources[] __devinitconst = {
{
.start = PM8018_IRQ_BLOCK_BIT(PM8018_MPP_BLOCK_START, 0),
@@ -199,6 +216,16 @@
.pdata_size = sizeof("pm8018-dbg"),
};
+static struct mfd_cell pwm_cell __devinitdata = {
+ .name = PM8XXX_PWM_DEV_NAME,
+ .id = -1,
+};
+
+static struct mfd_cell leds_cell __devinitdata = {
+ .name = PM8XXX_LEDS_DEV_NAME,
+ .id = -1,
+};
+
static int __devinit
pm8018_add_subdevices(const struct pm8018_platform_data *pdata,
struct pm8018 *pmic)
@@ -280,12 +307,38 @@
}
}
+ if (pdata->adc_pdata) {
+ adc_cell.platform_data = pdata->adc_pdata;
+ adc_cell.pdata_size = sizeof(struct pm8xxx_adc_platform_data);
+ ret = mfd_add_devices(pmic->dev, 0, &adc_cell, 1, NULL,
+ irq_base);
+ if (ret) {
+ pr_err("Failed to add adc subdevice ret=%d\n", ret);
+ }
+ }
+
+ if (pdata->leds_pdata) {
+ leds_cell.platform_data = pdata->leds_pdata;
+ leds_cell.pdata_size = sizeof(struct pm8xxx_led_platform_data);
+ ret = mfd_add_devices(pmic->dev, 0, &leds_cell, 1, NULL, 0);
+ if (ret) {
+ pr_err("Failed to add leds subdevice ret=%d\n", ret);
+ goto bail;
+ }
+ }
+
ret = mfd_add_devices(pmic->dev, 0, &debugfs_cell, 1, NULL, irq_base);
if (ret) {
pr_err("Failed to add debugfs subdevice ret=%d\n", ret);
goto bail;
}
+ ret = mfd_add_devices(pmic->dev, 0, &pwm_cell, 1, NULL, 0);
+ if (ret) {
+ pr_err("Failed to add pwm subdevice ret=%d\n", ret);
+ goto bail;
+ }
+
/* Add one device for each regulator used by the board. */
if (pdata->num_regulators > 0 && pdata->regulator_pdatas) {
mfd_regulators = kzalloc(sizeof(struct mfd_cell)
@@ -325,6 +378,17 @@
return ret;
}
+static const char * const pm8018_restart_reason[] = {
+ [0] = "Unknown",
+ [1] = "Triggered from CBL (external charger)",
+ [2] = "Triggered from KPD (power key press)",
+ [3] = "Triggered from CHG (usb charger insertion)",
+ [4] = "Triggered from SMPL (sudden momentary power loss)",
+ [5] = "Triggered from RTC (real time clock)",
+ [6] = "Triggered by Hard Reset",
+ [7] = "Triggered by General Purpose Trigger",
+};
+
static const char * const pm8018_rev_names[] = {
[PM8XXX_REVISION_8018_TEST] = "test",
[PM8XXX_REVISION_8018_1p0] = "1.0",
@@ -386,6 +450,14 @@
} else {
WARN_ON(version != PM8XXX_VERSION_8018);
}
+ /* Log human readable restart reason */
+ rc = msm_ssbi_read(pdev->dev.parent, REG_PM8018_PON_CNTRL_3, &val, 1);
+ if (rc) {
+ pr_err("Cannot read restart reason rc=%d\n", rc);
+ goto err_read_rev;
+ }
+ val &= PM8018_RESTART_REASON_MASK;
+ pr_info("PMIC Restart Reason: %s\n", pm8018_restart_reason[val]);
rc = pm8018_add_subdevices(pdata, pmic);
if (rc) {
diff --git a/drivers/mfd/pm8821-core.c b/drivers/mfd/pm8821-core.c
index 2da7055..ed29785 100644
--- a/drivers/mfd/pm8821-core.c
+++ b/drivers/mfd/pm8821-core.c
@@ -137,7 +137,7 @@
.name = "pm8xxx-debug",
.id = 1,
.platform_data = "pm8821-dbg",
- .data_size = sizeof("pm8821-dbg"),
+ .pdata_size = sizeof("pm8821-dbg"),
};
@@ -165,7 +165,7 @@
pdata->mpp_pdata->core_data.nmpps = PM8821_NR_MPPS;
pdata->mpp_pdata->core_data.base_addr = REG_MPP_BASE;
mpp_cell.platform_data = pdata->mpp_pdata;
- mpp_cell.data_size = sizeof(struct pm8xxx_mpp_platform_data);
+ mpp_cell.pdata_size = sizeof(struct pm8xxx_mpp_platform_data);
ret = mfd_add_devices(pmic->dev, 0, &mpp_cell, 1, NULL,
irq_base);
if (ret) {
diff --git a/drivers/mfd/pm8xxx-misc.c b/drivers/mfd/pm8xxx-misc.c
index cd5624f..00ac2ab 100644
--- a/drivers/mfd/pm8xxx-misc.c
+++ b/drivers/mfd/pm8xxx-misc.c
@@ -23,6 +23,7 @@
/* PON CTRL 1 register */
#define REG_PM8058_PON_CTRL_1 0x01C
#define REG_PM8921_PON_CTRL_1 0x01C
+#define REG_PM8018_PON_CTRL_1 0x01C
#define PON_CTRL_1_PULL_UP_MASK 0xE0
#define PON_CTRL_1_USB_PWR_EN 0x10
@@ -37,6 +38,7 @@
/* SLEEP CTRL register */
#define REG_PM8058_SLEEP_CTRL 0x02B
#define REG_PM8921_SLEEP_CTRL 0x10A
+#define REG_PM8018_SLEEP_CTRL 0x10A
#define SLEEP_CTRL_SMPL_EN_MASK 0x04
#define SLEEP_CTRL_SMPL_EN_RESET 0x04
@@ -81,6 +83,35 @@
return rc;
}
+static int __pm8018_reset_pwr_off(struct pm8xxx_misc_chip *chip, int reset)
+{
+ int rc;
+
+ /* Enable SMPL if resetting is desired. */
+ rc = pm8xxx_misc_masked_write(chip, REG_PM8018_SLEEP_CTRL,
+ SLEEP_CTRL_SMPL_EN_MASK,
+ (reset ? SLEEP_CTRL_SMPL_EN_RESET : SLEEP_CTRL_SMPL_EN_PWR_OFF));
+ if (rc) {
+ pr_err("pm8xxx_misc_masked_write failed, rc=%d\n", rc);
+ return rc;
+ }
+
+ /*
+ * Select action to perform (reset or shutdown) when PS_HOLD goes low.
+ * Also ensure that KPD, CBL0, and CBL1 pull ups are enabled and that
+ * USB charging is enabled.
+ */
+ rc = pm8xxx_misc_masked_write(chip, REG_PM8018_PON_CTRL_1,
+ PON_CTRL_1_PULL_UP_MASK | PON_CTRL_1_USB_PWR_EN
+ | PON_CTRL_1_WD_EN_MASK,
+ PON_CTRL_1_PULL_UP_MASK | PON_CTRL_1_USB_PWR_EN
+ | (reset ? PON_CTRL_1_WD_EN_RESET : PON_CTRL_1_WD_EN_PWR_OFF));
+ if (rc)
+ pr_err("pm8xxx_misc_masked_write failed, rc=%d\n", rc);
+
+ return rc;
+}
+
static int __pm8058_reset_pwr_off(struct pm8xxx_misc_chip *chip, int reset)
{
int rc;
@@ -201,6 +232,9 @@
/* Loop over all attached PMICs and call specific functions for them. */
list_for_each_entry(chip, &pm8xxx_misc_chips, link) {
switch (chip->version) {
+ case PM8XXX_VERSION_8018:
+ rc = __pm8018_reset_pwr_off(chip, reset);
+ break;
case PM8XXX_VERSION_8058:
rc = __pm8058_reset_pwr_off(chip, reset);
break;
diff --git a/drivers/misc/eeprom/eeprom_93cx6.c b/drivers/misc/eeprom/eeprom_93cx6.c
index 7b33de9..6ffe9e7 100644
--- a/drivers/misc/eeprom/eeprom_93cx6.c
+++ b/drivers/misc/eeprom/eeprom_93cx6.c
@@ -63,6 +63,7 @@
eeprom->reg_data_out = 0;
eeprom->reg_data_clock = 0;
eeprom->reg_chip_select = 1;
+ eeprom->drive_data = 1;
eeprom->register_write(eeprom);
/*
@@ -101,6 +102,7 @@
*/
eeprom->reg_data_in = 0;
eeprom->reg_data_out = 0;
+ eeprom->drive_data = 1;
/*
* Start writing all bits.
@@ -140,6 +142,7 @@
*/
eeprom->reg_data_in = 0;
eeprom->reg_data_out = 0;
+ eeprom->drive_data = 0;
/*
* Start reading all bits.
@@ -231,3 +234,89 @@
}
EXPORT_SYMBOL_GPL(eeprom_93cx6_multiread);
+
+/**
+ * eeprom_93cx6_wren - set the write enable state
+ * @eeprom: Pointer to eeprom structure
+ * @enable: true to enable writes, otherwise disable writes
+ *
+ * Set the EEPROM write enable state to either allow or deny
+ * writes depending on the @enable value.
+ */
+void eeprom_93cx6_wren(struct eeprom_93cx6 *eeprom, bool enable)
+{
+ u16 command;
+
+ /* start the command */
+ eeprom_93cx6_startup(eeprom);
+
+ /* create command to enable/disable */
+
+ command = enable ? PCI_EEPROM_EWEN_OPCODE : PCI_EEPROM_EWDS_OPCODE;
+ command <<= (eeprom->width - 2);
+
+ eeprom_93cx6_write_bits(eeprom, command,
+ PCI_EEPROM_WIDTH_OPCODE + eeprom->width);
+
+ eeprom_93cx6_cleanup(eeprom);
+}
+EXPORT_SYMBOL_GPL(eeprom_93cx6_wren);
+
+/**
+ * eeprom_93cx6_write - write data to the EEPROM
+ * @eeprom: Pointer to eeprom structure
+ * @addr: Address to write data to.
+ * @data: The data to write to address @addr.
+ *
+ * Write the @data to the specified @addr in the EEPROM and
+ * waiting for the device to finish writing.
+ *
+ * Note, since we do not expect large number of write operations
+ * we delay in between parts of the operation to avoid using excessive
+ * amounts of CPU time busy waiting.
+ */
+void eeprom_93cx6_write(struct eeprom_93cx6 *eeprom, u8 addr, u16 data)
+{
+ int timeout = 100;
+ u16 command;
+
+ /* start the command */
+ eeprom_93cx6_startup(eeprom);
+
+ command = PCI_EEPROM_WRITE_OPCODE << eeprom->width;
+ command |= addr;
+
+ /* send write command */
+ eeprom_93cx6_write_bits(eeprom, command,
+ PCI_EEPROM_WIDTH_OPCODE + eeprom->width);
+
+ /* send data */
+ eeprom_93cx6_write_bits(eeprom, data, 16);
+
+ /* get ready to check for busy */
+ eeprom->drive_data = 0;
+ eeprom->reg_chip_select = 1;
+ eeprom->register_write(eeprom);
+
+ /* wait at-least 250ns to get DO to be the busy signal */
+ usleep_range(1000, 2000);
+
+ /* wait for DO to go high to signify finish */
+
+ while (true) {
+ eeprom->register_read(eeprom);
+
+ if (eeprom->reg_data_out)
+ break;
+
+ usleep_range(1000, 2000);
+
+ if (--timeout <= 0) {
+ printk(KERN_ERR "%s: timeout\n", __func__);
+ break;
+ }
+ }
+
+ eeprom_93cx6_cleanup(eeprom);
+}
+EXPORT_SYMBOL_GPL(eeprom_93cx6_write);
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index f6c44c6..8aab269 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -1795,6 +1795,8 @@
depends on SPI
select MII
select CRC32
+ select MISC_DEVICES
+ select EEPROM_93CX6
help
SPI driver for Micrel KS8851 SPI attached network chip.
diff --git a/drivers/net/ks8851.c b/drivers/net/ks8851.c
index 74b6ac2..0bf972a 100644
--- a/drivers/net/ks8851.c
+++ b/drivers/net/ks8851.c
@@ -22,6 +22,8 @@
#include <linux/crc32.h>
#include <linux/mii.h>
#include <linux/regulator/consumer.h>
+#include <linux/eeprom_93cx6.h>
+
#include <linux/spi/spi.h>
#include <linux/ks8851.h>
#include <linux/gpio.h>
@@ -83,6 +85,7 @@
* @rc_ccr: Cached copy of KS_CCR.
* @rc_rxqcr: Cached copy of KS_RXQCR.
* @eeprom_size: Companion eeprom size in Bytes, 0 if no eeprom
+ * @eeprom: 93CX6 EEPROM state for accessing on-board EEPROM.
*
* The @lock ensures that the chip is protected when certain operations are
* in progress. When the read or write packet transfer is in progress, most
@@ -131,6 +134,8 @@
struct spi_transfer spi_xfer2[2];
struct regulator *vdd_io;
struct regulator *vdd_phy;
+
+ struct eeprom_93cx6 eeprom;
};
static int msg_enable;
@@ -346,6 +351,26 @@
}
/**
+ * ks8851_set_powermode - set power mode of the device
+ * @ks: The device state
+ * @pwrmode: The power mode value to write to KS_PMECR.
+ *
+ * Change the power mode of the chip.
+ */
+static void ks8851_set_powermode(struct ks8851_net *ks, unsigned pwrmode)
+{
+ unsigned pmecr;
+
+ netif_dbg(ks, hw, ks->netdev, "setting power mode %d\n", pwrmode);
+
+ pmecr = ks8851_rdreg16(ks, KS_PMECR);
+ pmecr &= ~PMECR_PM_MASK;
+ pmecr |= pwrmode;
+
+ ks8851_wrreg16(ks, KS_PMECR, pmecr);
+}
+
+/**
* ks8851_write_mac_addr - write mac address to device registers
* @dev: The network device
*
@@ -361,8 +386,15 @@
mutex_lock(&ks->lock);
+ /*
+ * Wake up chip in case it was powered off when stopped; otherwise,
+ * the first write to the MAC address does not take effect.
+ */
+ ks8851_set_powermode(ks, PMECR_PM_NORMAL);
for (i = 0; i < ETH_ALEN; i++)
ks8851_wrreg8(ks, KS_MAR(i), dev->dev_addr[i]);
+ if (!netif_running(dev))
+ ks8851_set_powermode(ks, PMECR_PM_SOFTDOWN);
mutex_unlock(&ks->lock);
@@ -370,17 +402,14 @@
}
/**
- * ks8851_init_mac - initialise the mac address
- * @ks: The device structure
+ * ks8851_read_mac_addr - read mac address from device registers
+ * @dev: The network device
*
- * Get or create the initial mac address for the device and then set that
- * into the station address register. The device will try to read a MAC address
- * from the EEPROM and program it into the MARs. We use random_ether_addr()
- * if the EEPROM is not present or if the address in the MARs appears invalid.
- */
-static void ks8851_init_mac(struct ks8851_net *ks)
+ * Update our copy of the KS8851 MAC address from the registers of @dev.
+*/
+static void ks8851_read_mac_addr(struct net_device *dev)
{
- struct net_device *dev = ks->netdev;
+ struct ks8851_net *ks = netdev_priv(dev);
int i;
mutex_lock(&ks->lock);
@@ -389,11 +418,33 @@
dev->dev_addr[i] = ks8851_rdreg8(ks, KS_MAR(i));
mutex_unlock(&ks->lock);
+}
- if (!(ks->rc_ccr & CCR_EEPROM) || !is_valid_ether_addr(dev->dev_addr)) {
- random_ether_addr(dev->dev_addr);
- ks8851_write_mac_addr(dev);
+/**
+ * ks8851_init_mac - initialise the mac address
+ * @ks: The device structure
+ *
+ * Get or create the initial mac address for the device and then set that
+ * into the station address register. If there is an EEPROM present, then
+ * we try that. If no valid mac address is found we use random_ether_addr()
+ * to create a new one.
+ */
+static void ks8851_init_mac(struct ks8851_net *ks)
+{
+ struct net_device *dev = ks->netdev;
+
+ /* first, try reading what we've got already */
+ if (ks->rc_ccr & CCR_EEPROM) {
+ ks8851_read_mac_addr(dev);
+ if (is_valid_ether_addr(dev->dev_addr))
+ return;
+
+ netdev_err(ks->netdev, "invalid mac address read %pM\n",
+ dev->dev_addr);
}
+
+ random_ether_addr(dev->dev_addr);
+ ks8851_write_mac_addr(dev);
}
/**
@@ -749,26 +800,6 @@
}
/**
- * ks8851_set_powermode - set power mode of the device
- * @ks: The device state
- * @pwrmode: The power mode value to write to KS_PMECR.
- *
- * Change the power mode of the chip.
- */
-static void ks8851_set_powermode(struct ks8851_net *ks, unsigned pwrmode)
-{
- unsigned pmecr;
-
- netif_dbg(ks, hw, ks->netdev, "setting power mode %d\n", pwrmode);
-
- pmecr = ks8851_rdreg16(ks, KS_PMECR);
- pmecr &= ~PMECR_PM_MASK;
- pmecr |= pwrmode;
-
- ks8851_wrreg16(ks, KS_PMECR, pmecr);
-}
-
-/**
* ks8851_net_open - open network device
* @dev: The network device being opened.
*
@@ -1048,234 +1079,6 @@
.ndo_validate_addr = eth_validate_addr,
};
-/* Companion eeprom access */
-
-enum { /* EEPROM programming states */
- EEPROM_CONTROL,
- EEPROM_ADDRESS,
- EEPROM_DATA,
- EEPROM_COMPLETE
-};
-
-/**
- * ks8851_eeprom_read - read a 16bits word in ks8851 companion EEPROM
- * @dev: The network device the PHY is on.
- * @addr: EEPROM address to read
- *
- * eeprom_size: used to define the data coding length. Can be changed
- * through debug-fs.
- *
- * Programs a read on the EEPROM using ks8851 EEPROM SW access feature.
- * Warning: The READ feature is not supported on ks8851 revision 0.
- *
- * Rough programming model:
- * - on period start: set clock high and read value on bus
- * - on period / 2: set clock low and program value on bus
- * - start on period / 2
- */
-unsigned int ks8851_eeprom_read(struct net_device *dev, unsigned int addr)
-{
- struct ks8851_net *ks = netdev_priv(dev);
- int eepcr;
- int ctrl = EEPROM_OP_READ;
- int state = EEPROM_CONTROL;
- int bit_count = EEPROM_OP_LEN - 1;
- unsigned int data = 0;
- int dummy;
- unsigned int addr_len;
-
- addr_len = (ks->eeprom_size == 128) ? 6 : 8;
-
- /* start transaction: chip select high, authorize write */
- mutex_lock(&ks->lock);
- eepcr = EEPCR_EESA | EEPCR_EESRWA;
- ks8851_wrreg16(ks, KS_EEPCR, eepcr);
- eepcr |= EEPCR_EECS;
- ks8851_wrreg16(ks, KS_EEPCR, eepcr);
- mutex_unlock(&ks->lock);
-
- while (state != EEPROM_COMPLETE) {
- /* falling clock period starts... */
- /* set EED_IO pin for control and address */
- eepcr &= ~EEPCR_EEDO;
- switch (state) {
- case EEPROM_CONTROL:
- eepcr |= ((ctrl >> bit_count) & 1) << 2;
- if (bit_count-- <= 0) {
- bit_count = addr_len - 1;
- state = EEPROM_ADDRESS;
- }
- break;
- case EEPROM_ADDRESS:
- eepcr |= ((addr >> bit_count) & 1) << 2;
- bit_count--;
- break;
- case EEPROM_DATA:
- /* Change to receive mode */
- eepcr &= ~EEPCR_EESRWA;
- break;
- }
-
- /* lower clock */
- eepcr &= ~EEPCR_EESCK;
-
- mutex_lock(&ks->lock);
- ks8851_wrreg16(ks, KS_EEPCR, eepcr);
- mutex_unlock(&ks->lock);
-
- /* waitread period / 2 */
- udelay(EEPROM_SK_PERIOD / 2);
-
- /* rising clock period starts... */
-
- /* raise clock */
- mutex_lock(&ks->lock);
- eepcr |= EEPCR_EESCK;
- ks8851_wrreg16(ks, KS_EEPCR, eepcr);
- mutex_unlock(&ks->lock);
-
- /* Manage read */
- switch (state) {
- case EEPROM_ADDRESS:
- if (bit_count < 0) {
- bit_count = EEPROM_DATA_LEN - 1;
- state = EEPROM_DATA;
- }
- break;
- case EEPROM_DATA:
- mutex_lock(&ks->lock);
- dummy = ks8851_rdreg16(ks, KS_EEPCR);
- mutex_unlock(&ks->lock);
- data |= ((dummy >> EEPCR_EESB_OFFSET) & 1) << bit_count;
- if (bit_count-- <= 0)
- state = EEPROM_COMPLETE;
- break;
- }
-
- /* wait period / 2 */
- udelay(EEPROM_SK_PERIOD / 2);
- }
-
- /* close transaction */
- mutex_lock(&ks->lock);
- eepcr &= ~EEPCR_EECS;
- ks8851_wrreg16(ks, KS_EEPCR, eepcr);
- eepcr = 0;
- ks8851_wrreg16(ks, KS_EEPCR, eepcr);
- mutex_unlock(&ks->lock);
-
- return data;
-}
-
-/**
- * ks8851_eeprom_write - write a 16bits word in ks8851 companion EEPROM
- * @dev: The network device the PHY is on.
- * @op: operand (can be WRITE, EWEN, EWDS)
- * @addr: EEPROM address to write
- * @data: data to write
- *
- * eeprom_size: used to define the data coding length. Can be changed
- * through debug-fs.
- *
- * Programs a write on the EEPROM using ks8851 EEPROM SW access feature.
- *
- * Note that a write enable is required before writing data.
- *
- * Rough programming model:
- * - on period start: set clock high
- * - on period / 2: set clock low and program value on bus
- * - start on period / 2
- */
-void ks8851_eeprom_write(struct net_device *dev, unsigned int op,
- unsigned int addr, unsigned int data)
-{
- struct ks8851_net *ks = netdev_priv(dev);
- int eepcr;
- int state = EEPROM_CONTROL;
- int bit_count = EEPROM_OP_LEN - 1;
- unsigned int addr_len;
-
- addr_len = (ks->eeprom_size == 128) ? 6 : 8;
-
- switch (op) {
- case EEPROM_OP_EWEN:
- addr = 0x30;
- break;
- case EEPROM_OP_EWDS:
- addr = 0;
- break;
- }
-
- /* start transaction: chip select high, authorize write */
- mutex_lock(&ks->lock);
- eepcr = EEPCR_EESA | EEPCR_EESRWA;
- ks8851_wrreg16(ks, KS_EEPCR, eepcr);
- eepcr |= EEPCR_EECS;
- ks8851_wrreg16(ks, KS_EEPCR, eepcr);
- mutex_unlock(&ks->lock);
-
- while (state != EEPROM_COMPLETE) {
- /* falling clock period starts... */
- /* set EED_IO pin for control and address */
- eepcr &= ~EEPCR_EEDO;
- switch (state) {
- case EEPROM_CONTROL:
- eepcr |= ((op >> bit_count) & 1) << 2;
- if (bit_count-- <= 0) {
- bit_count = addr_len - 1;
- state = EEPROM_ADDRESS;
- }
- break;
- case EEPROM_ADDRESS:
- eepcr |= ((addr >> bit_count) & 1) << 2;
- if (bit_count-- <= 0) {
- if (op == EEPROM_OP_WRITE) {
- bit_count = EEPROM_DATA_LEN - 1;
- state = EEPROM_DATA;
- } else {
- state = EEPROM_COMPLETE;
- }
- }
- break;
- case EEPROM_DATA:
- eepcr |= ((data >> bit_count) & 1) << 2;
- if (bit_count-- <= 0)
- state = EEPROM_COMPLETE;
- break;
- }
-
- /* lower clock */
- eepcr &= ~EEPCR_EESCK;
-
- mutex_lock(&ks->lock);
- ks8851_wrreg16(ks, KS_EEPCR, eepcr);
- mutex_unlock(&ks->lock);
-
- /* wait period / 2 */
- udelay(EEPROM_SK_PERIOD / 2);
-
- /* rising clock period starts... */
-
- /* raise clock */
- eepcr |= EEPCR_EESCK;
- mutex_lock(&ks->lock);
- ks8851_wrreg16(ks, KS_EEPCR, eepcr);
- mutex_unlock(&ks->lock);
-
- /* wait period / 2 */
- udelay(EEPROM_SK_PERIOD / 2);
- }
-
- /* close transaction */
- mutex_lock(&ks->lock);
- eepcr &= ~EEPCR_EECS;
- ks8851_wrreg16(ks, KS_EEPCR, eepcr);
- eepcr = 0;
- ks8851_wrreg16(ks, KS_EEPCR, eepcr);
- mutex_unlock(&ks->lock);
-
-}
-
/* ethtool support */
static void ks8851_get_drvinfo(struct net_device *dev,
@@ -1322,115 +1125,141 @@
return mii_nway_restart(&ks->mii);
}
-static int ks8851_get_eeprom_len(struct net_device *dev)
+/* EEPROM support */
+
+static void ks8851_eeprom_regread(struct eeprom_93cx6 *ee)
+{
+ struct ks8851_net *ks = ee->data;
+ unsigned val;
+
+ val = ks8851_rdreg16(ks, KS_EEPCR);
+
+ ee->reg_data_out = (val & EEPCR_EESB) ? 1 : 0;
+ ee->reg_data_clock = (val & EEPCR_EESCK) ? 1 : 0;
+ ee->reg_chip_select = (val & EEPCR_EECS) ? 1 : 0;
+}
+
+static void ks8851_eeprom_regwrite(struct eeprom_93cx6 *ee)
+{
+ struct ks8851_net *ks = ee->data;
+ unsigned val = EEPCR_EESA; /* default - eeprom access on */
+
+ if (ee->drive_data)
+ val |= EEPCR_EESRWA;
+ if (ee->reg_data_in)
+ val |= EEPCR_EEDO;
+ if (ee->reg_data_clock)
+ val |= EEPCR_EESCK;
+ if (ee->reg_chip_select)
+ val |= EEPCR_EECS;
+
+ ks8851_wrreg16(ks, KS_EEPCR, val);
+}
+
+/**
+ * ks8851_eeprom_claim - claim device EEPROM and activate the interface
+ * @ks: The network deice state.
+ *
+ * Check for the presence of an EEPROM, and then activate software access
+ * to the device.
+ */
+static int ks8851_eeprom_claim(struct ks8851_net *ks)
+{
+ if (!(ks->rc_ccr & CCR_EEPROM))
+ return -ENOENT;
+
+ mutex_lock(&ks->lock);
+
+ /* start with clock low, cs high */
+ ks8851_wrreg16(ks, KS_EEPCR, EEPCR_EESA | EEPCR_EECS);
+ return 0;
+}
+
+/**
+ * ks8851_eeprom_release - release the EEPROM interface
+ * @ks: The device state
+ *
+ * Release the software access to the device EEPROM
+ */
+static void ks8851_eeprom_release(struct ks8851_net *ks)
+{
+ unsigned val = ks8851_rdreg16(ks, KS_EEPCR);
+
+ ks8851_wrreg16(ks, KS_EEPCR, val & ~EEPCR_EESA);
+ mutex_unlock(&ks->lock);
+}
+
+#define KS_EEPROM_MAGIC (0x00008851)
+
+static int ks8851_set_eeprom(struct net_device *dev,
+ struct ethtool_eeprom *ee, u8 *data)
{
struct ks8851_net *ks = netdev_priv(dev);
- return ks->eeprom_size;
+ int offset = ee->offset;
+ int len = ee->len;
+ u16 tmp;
+
+ /* currently only support byte writing */
+ if (len != 1)
+ return -EINVAL;
+
+ if (ee->magic != KS_EEPROM_MAGIC)
+ return -EINVAL;
+
+ if (ks8851_eeprom_claim(ks))
+ return -ENOENT;
+
+ eeprom_93cx6_wren(&ks->eeprom, true);
+
+ /* ethtool currently only supports writing bytes, which means
+ * we have to read/modify/write our 16bit EEPROMs */
+
+ eeprom_93cx6_read(&ks->eeprom, offset/2, &tmp);
+
+ if (offset & 1) {
+ tmp &= 0xff;
+ tmp |= *data << 8;
+ } else {
+ tmp &= 0xff00;
+ tmp |= *data;
+ }
+
+ eeprom_93cx6_write(&ks->eeprom, offset/2, tmp);
+ eeprom_93cx6_wren(&ks->eeprom, false);
+
+ ks8851_eeprom_release(ks);
+
+ return 0;
}
static int ks8851_get_eeprom(struct net_device *dev,
- struct ethtool_eeprom *eeprom, u8 *bytes)
+ struct ethtool_eeprom *ee, u8 *data)
{
struct ks8851_net *ks = netdev_priv(dev);
- u16 *eeprom_buff;
- int first_word;
- int last_word;
- int ret_val = 0;
- u16 i;
+ int offset = ee->offset;
+ int len = ee->len;
- if (eeprom->len == 0)
+ /* must be 2 byte aligned */
+ if (len & 1 || offset & 1)
return -EINVAL;
- if (eeprom->len > ks->eeprom_size)
- return -EINVAL;
+ if (ks8851_eeprom_claim(ks))
+ return -ENOENT;
- eeprom->magic = ks8851_rdreg16(ks, KS_CIDER);
+ ee->magic = KS_EEPROM_MAGIC;
- first_word = eeprom->offset >> 1;
- last_word = (eeprom->offset + eeprom->len - 1) >> 1;
+ eeprom_93cx6_multiread(&ks->eeprom, offset/2, (__le16 *)data, len/2);
+ ks8851_eeprom_release(ks);
- eeprom_buff = kmalloc(sizeof(u16) *
- (last_word - first_word + 1), GFP_KERNEL);
- if (!eeprom_buff)
- return -ENOMEM;
-
- for (i = 0; i < last_word - first_word + 1; i++)
- eeprom_buff[i] = ks8851_eeprom_read(dev, first_word + 1);
-
- /* Device's eeprom is little-endian, word addressable */
- for (i = 0; i < last_word - first_word + 1; i++)
- le16_to_cpus(&eeprom_buff[i]);
-
- memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
- kfree(eeprom_buff);
-
- return ret_val;
+ return 0;
}
-static int ks8851_set_eeprom(struct net_device *dev,
- struct ethtool_eeprom *eeprom, u8 *bytes)
+static int ks8851_get_eeprom_len(struct net_device *dev)
{
struct ks8851_net *ks = netdev_priv(dev);
- u16 *eeprom_buff;
- void *ptr;
- int max_len;
- int first_word;
- int last_word;
- int ret_val = 0;
- u16 i;
- if (eeprom->len == 0)
- return -EOPNOTSUPP;
-
- if (eeprom->len > ks->eeprom_size)
- return -EINVAL;
-
- if (eeprom->magic != ks8851_rdreg16(ks, KS_CIDER))
- return -EFAULT;
-
- first_word = eeprom->offset >> 1;
- last_word = (eeprom->offset + eeprom->len - 1) >> 1;
- max_len = (last_word - first_word + 1) * 2;
- eeprom_buff = kmalloc(max_len, GFP_KERNEL);
- if (!eeprom_buff)
- return -ENOMEM;
-
- ptr = (void *)eeprom_buff;
-
- if (eeprom->offset & 1) {
- /* need read/modify/write of first changed EEPROM word */
- /* only the second byte of the word is being modified */
- eeprom_buff[0] = ks8851_eeprom_read(dev, first_word);
- ptr++;
- }
- if ((eeprom->offset + eeprom->len) & 1)
- /* need read/modify/write of last changed EEPROM word */
- /* only the first byte of the word is being modified */
- eeprom_buff[last_word - first_word] =
- ks8851_eeprom_read(dev, last_word);
-
-
- /* Device's eeprom is little-endian, word addressable */
- le16_to_cpus(&eeprom_buff[0]);
- le16_to_cpus(&eeprom_buff[last_word - first_word]);
-
- memcpy(ptr, bytes, eeprom->len);
-
- for (i = 0; i < last_word - first_word + 1; i++)
- eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
-
- ks8851_eeprom_write(dev, EEPROM_OP_EWEN, 0, 0);
-
- for (i = 0; i < last_word - first_word + 1; i++) {
- ks8851_eeprom_write(dev, EEPROM_OP_WRITE, first_word + i,
- eeprom_buff[i]);
- mdelay(EEPROM_WRITE_TIME);
- }
-
- ks8851_eeprom_write(dev, EEPROM_OP_EWDS, 0, 0);
-
- kfree(eeprom_buff);
- return ret_val;
+ /* currently, we assume it is an 93C46 attached, so return 128 */
+ return ks->rc_ccr & CCR_EEPROM ? 128 : 0;
}
static const struct ethtool_ops ks8851_ethtool_ops = {
@@ -1650,6 +1479,13 @@
spi_message_add_tail(&ks->spi_xfer2[0], &ks->spi_msg2);
spi_message_add_tail(&ks->spi_xfer2[1], &ks->spi_msg2);
+ /* setup EEPROM state */
+
+ ks->eeprom.data = ks;
+ ks->eeprom.width = PCI_EEPROM_WIDTH_93C46;
+ ks->eeprom.register_read = ks8851_eeprom_regread;
+ ks->eeprom.register_write = ks8851_eeprom_regwrite;
+
/* setup mii state */
ks->mii.dev = ndev;
ks->mii.phy_id = 1,
@@ -1711,9 +1547,10 @@
goto err_netdev;
}
- netdev_info(ndev, "revision %d, MAC %pM, IRQ %d\n",
+ netdev_info(ndev, "revision %d, MAC %pM, IRQ %d, %s EEPROM\n",
CIDER_REV_GET(ks8851_rdreg16(ks, KS_CIDER)),
- ndev->dev_addr, ndev->irq);
+ ndev->dev_addr, ndev->irq,
+ ks->rc_ccr & CCR_EEPROM ? "has" : "no");
return 0;
@@ -1723,8 +1560,6 @@
err_id:
err_irq:
- free_netdev(ndev);
-
if (!IS_ERR(ks->vdd_io)) {
regulator_disable(ks->vdd_io);
regulator_put(ks->vdd_io);
@@ -1735,6 +1570,8 @@
regulator_put(ks->vdd_phy);
}
+ free_netdev(ndev);
+
if (pdata && gpio_is_valid(pdata->rst_gpio))
gpio_free(pdata->rst_gpio);
diff --git a/drivers/net/ks8851.h b/drivers/net/ks8851.h
index 537fb06e..b2703a1 100644
--- a/drivers/net/ks8851.h
+++ b/drivers/net/ks8851.h
@@ -16,7 +16,7 @@
#define CCR_32PIN (1 << 0)
/* MAC address registers */
-#define KS_MAR(_m) 0x15 - (_m)
+#define KS_MAR(_m) (0x15 - (_m))
#define KS_MARL 0x10
#define KS_MARM 0x12
#define KS_MARH 0x14
diff --git a/drivers/power/pm8921-bms.c b/drivers/power/pm8921-bms.c
index d0c1392..e666bfc 100644
--- a/drivers/power/pm8921-bms.c
+++ b/drivers/power/pm8921-bms.c
@@ -87,6 +87,7 @@
unsigned int batt_id_channel;
unsigned int pmic_bms_irq[PM_BMS_MAX_INTS];
DECLARE_BITMAP(enabled_irqs, PM_BMS_MAX_INTS);
+ spinlock_t bms_output_lock;
};
static struct pm8921_bms_chip *the_chip;
@@ -156,6 +157,32 @@
return 0;
}
+#define HOLD_OREG_DATA BIT(1)
+static int pm_bms_lock_output_data(struct pm8921_bms_chip *chip)
+{
+ int rc;
+
+ rc = pm_bms_masked_write(chip, BMS_CONTROL, HOLD_OREG_DATA,
+ HOLD_OREG_DATA);
+ if (rc) {
+ pr_err("couldnt lock bms output rc = %d\n", rc);
+ return rc;
+ }
+ return 0;
+}
+
+static int pm_bms_unlock_output_data(struct pm8921_bms_chip *chip)
+{
+ int rc;
+
+ rc = pm_bms_masked_write(chip, BMS_CONTROL, HOLD_OREG_DATA, 0);
+ if (rc) {
+ pr_err("fail to unlock BMS_CONTROL rc = %d\n", rc);
+ return rc;
+ }
+ return 0;
+}
+
#define SELECT_OUTPUT_DATA 0x1C
#define SELECT_OUTPUT_TYPE_SHIFT 2
#define OCV_FOR_RBATT 0x0
@@ -182,6 +209,18 @@
pr_err("invalid type %d asked to read\n", type);
return -EINVAL;
}
+
+ /* make sure the bms registers are locked */
+ rc = pm8xxx_readb(chip->dev->parent, BMS_CONTROL, ®);
+ if (rc) {
+ pr_err("fail to read BMS_OUTPUT0 for type %d rc = %d\n",
+ type, rc);
+ return rc;
+ }
+
+ /* Output register data must be held (locked) while reading output */
+ WARN_ON(!(reg && HOLD_OREG_DATA));
+
rc = pm_bms_masked_write(chip, BMS_CONTROL, SELECT_OUTPUT_DATA,
type << SELECT_OUTPUT_TYPE_SHIFT);
if (rc) {
@@ -779,11 +818,16 @@
int64_t *cc_mah)
{
int coulumb_counter;
+ unsigned long flags;
*fcc = calculate_fcc(chip, batt_temp, chargecycles);
pr_debug("FCC = %umAh batt_temp = %d, cycles = %d",
*fcc, batt_temp, chargecycles);
+ /* fcc doesnt need to be read from hardware, lock the bms now */
+ spin_lock_irqsave(&chip->bms_output_lock, flags);
+ pm_bms_lock_output_data(chip);
+
*unusable_charge = calculate_unusable_charge_mah(chip, *fcc,
batt_temp, chargecycles);
@@ -796,6 +840,9 @@
/* calculate cc milli_volt_hour */
calculate_cc_mah(chip, cc_mah, &coulumb_counter);
+
+ pm_bms_unlock_output_data(chip);
+ spin_unlock_irqrestore(&chip->bms_output_lock, flags);
pr_debug("cc_mah = %lldmAh cc = %d\n", *cc_mah, coulumb_counter);
}
@@ -862,8 +909,7 @@
* shutdown for low battery
*/
soc = BATTERY_POWER_SUPPLY_SOC;
- pr_debug("Adjusting SOC to %d\n",
- BATTERY_POWER_SUPPLY_SOC);
+ pr_debug("Adjusting SOC to %d\n", soc);
}
}
@@ -947,16 +993,26 @@
int pm8921_bms_get_vsense_avg(int *result)
{
- if (the_chip)
- return read_vsense_avg(the_chip, result);
+ int rc = -EINVAL;
+ unsigned long flags;
+
+ if (the_chip) {
+ spin_lock_irqsave(&the_chip->bms_output_lock, flags);
+ pm_bms_lock_output_data(the_chip);
+ rc = read_vsense_avg(the_chip, result);
+ pm_bms_unlock_output_data(the_chip);
+ spin_unlock_irqrestore(&the_chip->bms_output_lock, flags);
+ }
pr_err("called before initialization\n");
- return -EINVAL;
+ return rc;
}
EXPORT_SYMBOL(pm8921_bms_get_vsense_avg);
int pm8921_bms_get_battery_current(int *result)
{
+ unsigned long flags;
+
if (!the_chip) {
pr_err("called before initialization\n");
return -EINVAL;
@@ -966,7 +1022,11 @@
return -EINVAL;
}
+ spin_lock_irqsave(&the_chip->bms_output_lock, flags);
+ pm_bms_lock_output_data(the_chip);
read_vsense_avg(the_chip, result);
+ pm_bms_unlock_output_data(the_chip);
+ spin_unlock_irqrestore(&the_chip->bms_output_lock, flags);
pr_debug("vsense=%d\n", *result);
/* cast for signed division */
*result = *result / (int)the_chip->r_sense;
@@ -1528,7 +1588,7 @@
pr_err("Cannot allocate pm_bms_chip\n");
return -ENOMEM;
}
-
+ spin_lock_init(&chip->bms_output_lock);
chip->dev = &pdev->dev;
chip->r_sense = pdata->r_sense;
chip->i_test = pdata->i_test;
diff --git a/drivers/thermal/msm8960_tsens.c b/drivers/thermal/msm8960_tsens.c
index be434f6..12b3a42e 100644
--- a/drivers/thermal/msm8960_tsens.c
+++ b/drivers/thermal/msm8960_tsens.c
@@ -41,13 +41,7 @@
#define TSENS_MAIN_SENSOR 0
#define TSENS_8960_QFPROM_ADDR0 (MSM_QFPROM_BASE + 0x00000404)
-#define TSENS_8960_QFPROM_RED_TEMP_SENSOR0_SHIFT 8
-#define TSENS_8960_QFPROM_TEMP_SENSOR0_SHIFT 0
-#define TSENS_8960_QFPROM_TEMP_SENSOR0_MASK \
- (255 << TSENS_QFPROM_TEMP_SENSOR0_SHIFT)
-#define TSENS_8960_QFPROM_RED_TEMP_SENSOR0_MASK \
- (255 << TSENS_8960_QFPROM_RED_TEMP_SENSOR0_SHIFT)
-
+#define TSENS_8960_QFPROM_SPARE_ADDR0 (MSM_QFPROM_BASE + 0x00000414)
#define TSENS_8960_CONFIG 0x9b
#define TSENS_8960_CONFIG_SHIFT 0
#define TSENS_8960_CONFIG_MASK (0xf << TSENS_8960_CONFIG_SHIFT)
@@ -679,30 +673,27 @@
static int tsens_calib_sensors8960(void)
{
- uint32_t *main_sensor_addr, sensor_shift, red_sensor_shift;
- uint32_t sensor_mask, red_sensor_mask, i;
+ uint32_t *main_sensor_addr, sensor_shift, *backup_sensor_addr;
+ uint32_t sensor_mask, i;
for (i = 0; i < tmdev->tsens_num_sensor; i++) {
main_sensor_addr = TSENS_8960_QFPROM_ADDR0 +
- (TSENS_8960_QFPROM_SHIFT * (i >> TSENS_MASK1));
- sensor_shift = (i & TSENS_MASK1) * TSENS_SENSOR_SHIFT;
- red_sensor_shift = sensor_shift + TSENS_RED_SHIFT;
+ (TSENS_8960_QFPROM_SHIFT *
+ (i & TSENS_8960_QFPROM_SHIFT >> TSENS_SENSOR0_SHIFT));
+ sensor_shift = (i % TSENS_8960_QFPROM_SHIFT) * TSENS_RED_SHIFT;
sensor_mask = TSENS_THRESHOLD_MAX_CODE << sensor_shift;
- red_sensor_mask = TSENS_THRESHOLD_MAX_CODE <<
- red_sensor_shift;
+ backup_sensor_addr = TSENS_8960_QFPROM_SPARE_ADDR0 +
+ (TSENS_8960_QFPROM_SHIFT *
+ (i & TSENS_8960_QFPROM_SHIFT >> TSENS_SENSOR0_SHIFT));
tmdev->sensor[i].calib_data = (readl_relaxed(main_sensor_addr)
& sensor_mask) >> sensor_shift;
tmdev->sensor[i].calib_data_backup =
- (readl_relaxed(main_sensor_addr) &
- red_sensor_mask) >> red_sensor_shift;
+ (readl_relaxed(backup_sensor_addr) &
+ sensor_mask) >> sensor_shift;
if (tmdev->sensor[i].calib_data_backup)
tmdev->sensor[i].calib_data =
tmdev->sensor[i].calib_data_backup;
- /* Hardcoded calibration data based on pervious
- * chip. Remove once we obtain the data. */
- tmdev->sensor[i].calib_data = 91;
-
if (!tmdev->sensor[i].calib_data) {
pr_err("%s: No temperature sensor:%d data for"
" calibration in QFPROM!\n", __func__, i);
diff --git a/drivers/usb/gadget/android.c b/drivers/usb/gadget/android.c
index 5e38238..8d58833 100644
--- a/drivers/usb/gadget/android.c
+++ b/drivers/usb/gadget/android.c
@@ -320,7 +320,7 @@
struct device *device, struct device_attribute *attr,
const char *buff, size_t size)
{
- strncpy(diag_clients, buff, sizeof(diag_clients));
+ strlcpy(diag_clients, buff, sizeof(diag_clients));
return size;
}
@@ -346,18 +346,16 @@
char *name;
char buf[32], *b;
int once = 0, err = -1;
- int (*notify)(uint32_t, const char *);
+ int (*notify)(uint32_t, const char *) = NULL;
- strncpy(buf, diag_clients, sizeof(buf));
+ strlcpy(buf, diag_clients, sizeof(buf));
b = strim(buf);
while (b) {
name = strsep(&b, ",");
/* Allow only first diag channel to update pid and serial no */
- if (!once++)
+ if (_android_dev->pdata && !once++)
notify = _android_dev->pdata->update_pid_and_serial_num;
- else
- notify = NULL;
if (name) {
err = diag_function_add(c, name, notify);
@@ -383,7 +381,7 @@
struct device *device, struct device_attribute *attr,
const char *buff, size_t size)
{
- strncpy(serial_transports, buff, sizeof(serial_transports));
+ strlcpy(serial_transports, buff, sizeof(serial_transports));
return size;
}
@@ -409,7 +407,7 @@
goto bind_config;
serial_initialized = 1;
- strncpy(buf, serial_transports, sizeof(buf));
+ strlcpy(buf, serial_transports, sizeof(buf));
b = strim(buf);
while (b) {
@@ -675,7 +673,7 @@
{
struct android_usb_function *f = dev_get_drvdata(dev);
struct rndis_function_config *config = f->config;
- return sprintf(buf, "%s\n", config->manufacturer);
+ return snprintf(buf, PAGE_SIZE, "%s\n", config->manufacturer);
}
static ssize_t rndis_manufacturer_store(struct device *dev,
@@ -686,7 +684,7 @@
if (size >= sizeof(config->manufacturer))
return -EINVAL;
- if (sscanf(buf, "%s", config->manufacturer) == 1)
+ if (sscanf(buf, "%255s", config->manufacturer) == 1)
return size;
return -1;
}
@@ -699,7 +697,7 @@
{
struct android_usb_function *f = dev_get_drvdata(dev);
struct rndis_function_config *config = f->config;
- return sprintf(buf, "%d\n", config->wceis);
+ return snprintf(buf, PAGE_SIZE, "%d\n", config->wceis);
}
static ssize_t rndis_wceis_store(struct device *dev,
@@ -724,7 +722,7 @@
{
struct android_usb_function *f = dev_get_drvdata(dev);
struct rndis_function_config *rndis = f->config;
- return sprintf(buf, "%02x:%02x:%02x:%02x:%02x:%02x\n",
+ return snprintf(buf, PAGE_SIZE, "%02x:%02x:%02x:%02x:%02x:%02x\n",
rndis->ethaddr[0], rndis->ethaddr[1], rndis->ethaddr[2],
rndis->ethaddr[3], rndis->ethaddr[4], rndis->ethaddr[5]);
}
@@ -751,7 +749,7 @@
{
struct android_usb_function *f = dev_get_drvdata(dev);
struct rndis_function_config *config = f->config;
- return sprintf(buf, "%04x\n", config->vendorID);
+ return snprintf(buf, PAGE_SIZE, "%04x\n", config->vendorID);
}
static ssize_t rndis_vendorID_store(struct device *dev,
@@ -846,7 +844,7 @@
{
struct android_usb_function *f = dev_get_drvdata(dev);
struct mass_storage_function_config *config = f->config;
- return sprintf(buf, "%s\n", config->common->inquiry_string);
+ return snprintf(buf, PAGE_SIZE, "%s\n", config->common->inquiry_string);
}
static ssize_t mass_storage_inquiry_store(struct device *dev,
@@ -856,7 +854,7 @@
struct mass_storage_function_config *config = f->config;
if (size >= sizeof(config->common->inquiry_string))
return -EINVAL;
- if (sscanf(buf, "%s", config->common->inquiry_string) != 1)
+ if (sscanf(buf, "%28s", config->common->inquiry_string) != 1)
return -EINVAL;
return size;
}
@@ -937,7 +935,7 @@
struct android_usb_function *f;
struct device_attribute **attrs;
struct device_attribute *attr;
- int err;
+ int err = 0;
int index = 0;
for (; (f = *functions++); index++) {
@@ -1050,7 +1048,7 @@
char *buff = buf;
list_for_each_entry(f, &dev->enabled_functions, enabled_list)
- buff += sprintf(buff, "%s,", f->name);
+ buff += snprintf(buff, PAGE_SIZE, "%s,", f->name);
if (buff != buf)
*(buff-1) = '\n';
return buff - buf;
@@ -1067,7 +1065,7 @@
INIT_LIST_HEAD(&dev->enabled_functions);
- strncpy(buf, buff, sizeof(buf));
+ strlcpy(buf, buff, sizeof(buf));
b = strim(buf);
while (b) {
@@ -1086,7 +1084,7 @@
char *buf)
{
struct android_dev *dev = dev_get_drvdata(pdev);
- return sprintf(buf, "%d\n", dev->enabled);
+ return snprintf(buf, PAGE_SIZE, "%d\n", dev->enabled);
}
static ssize_t enable_store(struct device *pdev, struct device_attribute *attr,
@@ -1140,7 +1138,7 @@
state = "CONNECTED";
spin_unlock_irqrestore(&cdev->lock, flags);
out:
- return sprintf(buf, "%s\n", state);
+ return snprintf(buf, PAGE_SIZE, "%s\n", state);
}
#define DESCRIPTOR_ATTR(field, format_string) \
@@ -1148,7 +1146,8 @@
field ## _show(struct device *dev, struct device_attribute *attr, \
char *buf) \
{ \
- return sprintf(buf, format_string, device_desc.field); \
+ return snprintf(buf, PAGE_SIZE, \
+ format_string, device_desc.field); \
} \
static ssize_t \
field ## _store(struct device *dev, struct device_attribute *attr, \
@@ -1168,14 +1167,14 @@
field ## _show(struct device *dev, struct device_attribute *attr, \
char *buf) \
{ \
- return sprintf(buf, "%s", buffer); \
+ return snprintf(buf, PAGE_SIZE, "%s", buffer); \
} \
static ssize_t \
field ## _store(struct device *dev, struct device_attribute *attr, \
const char *buf, size_t size) \
{ \
if (size >= sizeof(buffer)) return -EINVAL; \
- if (sscanf(buf, "%s", buffer) == 1) { \
+ if (sscanf(buf, "%255s", buffer) == 1) { \
return size; \
} \
return -1; \
@@ -1263,9 +1262,10 @@
device_desc.iProduct = id;
/* Default strings - should be updated by userspace */
- strncpy(manufacturer_string, "Android", sizeof(manufacturer_string) - 1);
- strncpy(product_string, "Android", sizeof(product_string) - 1);
- strncpy(serial_string, "0123456789ABCDEF", sizeof(serial_string) - 1);
+ strlcpy(manufacturer_string, "Android",
+ sizeof(manufacturer_string) - 1);
+ strlcpy(product_string, "Android", sizeof(product_string) - 1);
+ strlcpy(serial_string, "0123456789ABCDEF", sizeof(serial_string) - 1);
id = usb_string_id(cdev);
if (id < 0)
diff --git a/drivers/usb/gadget/ci13xxx_udc.c b/drivers/usb/gadget/ci13xxx_udc.c
index 9017706..9d268d1 100644
--- a/drivers/usb/gadget/ci13xxx_udc.c
+++ b/drivers/usb/gadget/ci13xxx_udc.c
@@ -1699,6 +1699,9 @@
if (mReq->req.status != -EALREADY)
return -EINVAL;
+ /* clean speculative fetches on req->ptr->token */
+ mb();
+
if ((TD_STATUS_ACTIVE & mReq->ptr->token) != 0)
return -EBUSY;
@@ -2074,7 +2077,6 @@
continue; /* not configured */
if (hw_test_and_clear_complete(i)) {
- udelay(200);
err = isr_tr_complete_low(mEp);
if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
if (err > 0) /* needs status phase */
diff --git a/drivers/usb/gadget/f_rmnet.c b/drivers/usb/gadget/f_rmnet.c
index ebbd1d8..69f158a 100644
--- a/drivers/usb/gadget/f_rmnet.c
+++ b/drivers/usb/gadget/f_rmnet.c
@@ -701,6 +701,9 @@
f->descriptors = usb_copy_descriptors(rmnet_fs_function);
+ if (!f->descriptors)
+ goto fail;
+
dev->fs.in = usb_find_endpoint(rmnet_fs_function,
f->descriptors,
&rmnet_fs_in_desc);
@@ -722,6 +725,9 @@
/* copy descriptors, and track endpoint copies */
f->hs_descriptors = usb_copy_descriptors(rmnet_hs_function);
+ if (!f->hs_descriptors)
+ goto fail;
+
dev->hs.in = usb_find_endpoint(rmnet_hs_function,
f->hs_descriptors, &rmnet_hs_in_desc);
dev->hs.out = usb_find_endpoint(rmnet_hs_function,
@@ -737,6 +743,9 @@
return 0;
+fail:
+ if (f->descriptors)
+ usb_free_descriptors(f->descriptors);
ep_notify_alloc_fail:
dev->notify->driver_data = NULL;
dev->notify = NULL;
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 4447b0f..ece6785 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -178,6 +178,17 @@
This driver is not supported on boards like trout which
has an external PHY.
+config USB_EHCI_MSM_HSIC
+ bool "Support for HSIC based MSM on-chip EHCI USB controller"
+ depends on USB_EHCI_HCD && ARCH_MSM
+ ---help---
+ Enables support for the HSIC (High Speed Inter-Chip) based
+ USB Host controller present on the Qualcomm chipsets.
+
+ HSIC is a supplement to USB 2.0 specification and is preferred
+ for chip-to-chip interconnect (having maximum circuit length of
+ 10cm) as it removes the analog transceivers.
+
config USB_EHCI_TEGRA
boolean "NVIDIA Tegra HCD support"
depends on USB_EHCI_HCD && ARCH_TEGRA
@@ -258,7 +269,6 @@
Enables support for the full speed USB controller core present
on the Qualcomm chipsets
-
config USB_ISP116X_HCD
tristate "ISP116X HCD support"
depends on USB
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 0744395..dc11eaf 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -1187,31 +1187,6 @@
#define PCI_DRIVER ehci_pci_driver
#endif
-#ifdef CONFIG_USB_EHCI_FSL
-#include "ehci-fsl.c"
-#define PLATFORM_DRIVER ehci_fsl_driver
-#endif
-
-#ifdef CONFIG_USB_EHCI_MXC
-#include "ehci-mxc.c"
-#define PLATFORM_DRIVER ehci_mxc_driver
-#endif
-
-#ifdef CONFIG_USB_EHCI_SH
-#include "ehci-sh.c"
-#define PLATFORM_DRIVER ehci_hcd_sh_driver
-#endif
-
-#ifdef CONFIG_SOC_AU1200
-#include "ehci-au1xxx.c"
-#define PLATFORM_DRIVER ehci_hcd_au1xxx_driver
-#endif
-
-#ifdef CONFIG_USB_EHCI_HCD_OMAP
-#include "ehci-omap.c"
-#define PLATFORM_DRIVER ehci_hcd_omap_driver
-#endif
-
#ifdef CONFIG_PPC_PS3
#include "ehci-ps3.c"
#define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver
@@ -1227,90 +1202,204 @@
#define XILINX_OF_PLATFORM_DRIVER ehci_hcd_xilinx_of_driver
#endif
+#ifdef CONFIG_USB_EHCI_FSL
+#include "ehci-fsl.c"
+#define PLATFORM_DRIVER_PRESENT
+#endif
+
+#ifdef CONFIG_USB_EHCI_MXC
+#include "ehci-mxc.c"
+#define PLATFORM_DRIVER_PRESENT
+#endif
+
+#ifdef CONFIG_USB_EHCI_SH
+#include "ehci-sh.c"
+#define PLATFORM_DRIVER_PRESENT
+#endif
+
+#ifdef CONFIG_SOC_AU1200
+#include "ehci-au1xxx.c"
+#define PLATFORM_DRIVER_PRESENT
+#endif
+
+#ifdef CONFIG_USB_EHCI_HCD_OMAP
+#include "ehci-omap.c"
+#define PLATFORM_DRIVER_PRESENT
+#endif
+
#ifdef CONFIG_PLAT_ORION
#include "ehci-orion.c"
-#define PLATFORM_DRIVER ehci_orion_driver
+#define PLATFORM_DRIVER_PRESENT
#endif
#ifdef CONFIG_ARCH_IXP4XX
#include "ehci-ixp4xx.c"
-#define PLATFORM_DRIVER ixp4xx_ehci_driver
+#define PLATFORM_DRIVER_PRESENT
#endif
#ifdef CONFIG_USB_W90X900_EHCI
#include "ehci-w90x900.c"
-#define PLATFORM_DRIVER ehci_hcd_w90x900_driver
+#define PLATFORM_DRIVER_PRESENT
#endif
#ifdef CONFIG_ARCH_AT91
#include "ehci-atmel.c"
-#define PLATFORM_DRIVER ehci_atmel_driver
+#define PLATFORM_DRIVER_PRESENT
#endif
#ifdef CONFIG_USB_OCTEON_EHCI
#include "ehci-octeon.c"
-#define PLATFORM_DRIVER ehci_octeon_driver
+#define PLATFORM_DRIVER_PRESENT
#endif
#ifdef CONFIG_USB_CNS3XXX_EHCI
#include "ehci-cns3xxx.c"
-#define PLATFORM_DRIVER cns3xxx_ehci_driver
+#define PLATFORM_DRIVER_PRESENT
#endif
#ifdef CONFIG_ARCH_VT8500
#include "ehci-vt8500.c"
-#define PLATFORM_DRIVER vt8500_ehci_driver
+#define PLATFORM_DRIVER_PRESENT
#endif
#ifdef CONFIG_PLAT_SPEAR
#include "ehci-spear.c"
-#define PLATFORM_DRIVER spear_ehci_hcd_driver
+#define PLATFORM_DRIVER_PRESENT
#endif
#ifdef CONFIG_USB_EHCI_MSM_72K
#include "ehci-msm72k.c"
-#define PLATFORM_DRIVER ehci_msm_driver
+#define PLATFORM_DRIVER_PRESENT
#endif
#ifdef CONFIG_USB_EHCI_MSM
#include "ehci-msm.c"
-#define PLATFORM_DRIVER ehci_msm_driver
+#define PLATFORM_DRIVER_PRESENT
#endif
#ifdef CONFIG_USB_EHCI_HCD_PMC_MSP
#include "ehci-pmcmsp.c"
-#define PLATFORM_DRIVER ehci_hcd_msp_driver
+#define PLATFORM_DRIVER_PRESENT
#endif
#ifdef CONFIG_USB_EHCI_TEGRA
#include "ehci-tegra.c"
-#define PLATFORM_DRIVER tegra_ehci_driver
+#define PLATFORM_DRIVER_PRESENT
#endif
#ifdef CONFIG_USB_EHCI_S5P
#include "ehci-s5p.c"
-#define PLATFORM_DRIVER s5p_ehci_driver
+#define PLATFORM_DRIVER_PRESENT
#endif
#ifdef CONFIG_USB_EHCI_ATH79
#include "ehci-ath79.c"
-#define PLATFORM_DRIVER ehci_ath79_driver
+#define PLATFORM_DRIVER_PRESENT
#endif
#ifdef CONFIG_SPARC_LEON
#include "ehci-grlib.c"
-#define PLATFORM_DRIVER ehci_grlib_driver
+#define PLATFORM_DRIVER_PRESENT
#endif
-#if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
+#ifdef CONFIG_USB_EHCI_MSM_HSIC
+#include "ehci-msm-hsic.c"
+#define PLATFORM_DRIVER_PRESENT
+#endif
+
+#if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER_PRESENT) && \
!defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \
!defined(XILINX_OF_PLATFORM_DRIVER)
#error "missing bus glue for ehci-hcd"
#endif
+static struct platform_driver *plat_drivers[] = {
+#ifdef CONFIG_USB_EHCI_FSL
+ &ehci_fsl_driver,
+#endif
+
+#ifdef CONFIG_USB_EHCI_MXC
+ &ehci_mxc_driver,
+#endif
+
+#ifdef CONFIG_CPU_SUBTYPE_SH7786
+ &ehci_hcd_sh_driver,
+#endif
+
+#ifdef CONFIG_SOC_AU1200
+ &ehci_hcd_au1xxx_driver,
+#endif
+
+#ifdef CONFIG_USB_EHCI_HCD_OMAP
+ &ehci_hcd_omap_driver,
+#endif
+
+#ifdef CONFIG_PLAT_ORION
+ &ehci_orion_driver,
+#endif
+
+#ifdef CONFIG_ARCH_IXP4XX
+ &ixp4xx_ehci_driver,
+#endif
+
+#ifdef CONFIG_USB_W90X900_EHCI
+ &ehci_hcd_w90x900_driver,
+#endif
+
+#ifdef CONFIG_ARCH_AT91
+ &ehci_atmel_driver,
+#endif
+
+#ifdef CONFIG_USB_OCTEON_EHCI
+ &ehci_octeon_driver,
+#endif
+
+#ifdef CONFIG_USB_CNS3XXX_EHCI
+ &cns3xxx_ehci_driver,
+#endif
+
+#ifdef CONFIG_ARCH_VT8500
+ &vt8500_ehci_driver,
+#endif
+
+#ifdef CONFIG_PLAT_SPEAR
+ &spear_ehci_hcd_driver,
+#endif
+
+#ifdef CONFIG_USB_EHCI_HCD_PMC_MSP
+ &ehci_hcd_msp_driver
+#endif
+
+#ifdef CONFIG_USB_EHCI_TEGRA
+ &tegra_ehci_driver
+#endif
+
+#ifdef CONFIG_USB_EHCI_S5P
+ &s5p_ehci_driver
+#endif
+
+#ifdef CONFIG_USB_EHCI_ATH79
+ &ehci_ath79_driver
+#endif
+
+#ifdef CONFIG_SPARC_LEON
+ &ehci_grlib_driver
+#endif
+
+#if defined(CONFIG_USB_EHCI_MSM_72K) || defined(CONFIG_USB_EHCI_MSM)
+ &ehci_msm_driver,
+#endif
+
+#ifdef CONFIG_USB_EHCI_MSM_HSIC
+ &ehci_msm_hsic_driver
+#endif
+
+};
+
+
static int __init ehci_hcd_init(void)
{
- int retval = 0;
+ int i, retval = 0;
if (usb_disabled())
return -ENODEV;
@@ -1335,11 +1424,14 @@
}
#endif
-#ifdef PLATFORM_DRIVER
- retval = platform_driver_register(&PLATFORM_DRIVER);
- if (retval < 0)
- goto clean0;
-#endif
+ for (i = 0; i < ARRAY_SIZE(plat_drivers); i++) {
+ retval = platform_driver_register(plat_drivers[i]);
+ if (retval) {
+ while (--i >= 0)
+ platform_driver_unregister(plat_drivers[i]);
+ goto clean0;
+ }
+ }
#ifdef PCI_DRIVER
retval = pci_register_driver(&PCI_DRIVER);
@@ -1382,10 +1474,9 @@
pci_unregister_driver(&PCI_DRIVER);
clean1:
#endif
-#ifdef PLATFORM_DRIVER
- platform_driver_unregister(&PLATFORM_DRIVER);
+ for (i = 0; i < ARRAY_SIZE(plat_drivers); i++)
+ platform_driver_unregister(plat_drivers[i]);
clean0:
-#endif
#ifdef DEBUG
debugfs_remove(ehci_debug_root);
ehci_debug_root = NULL;
@@ -1398,15 +1489,17 @@
static void __exit ehci_hcd_cleanup(void)
{
+ int i;
#ifdef XILINX_OF_PLATFORM_DRIVER
platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER);
#endif
#ifdef OF_PLATFORM_DRIVER
platform_driver_unregister(&OF_PLATFORM_DRIVER);
#endif
-#ifdef PLATFORM_DRIVER
- platform_driver_unregister(&PLATFORM_DRIVER);
-#endif
+
+ for (i = 0; i < ARRAY_SIZE(plat_drivers); i++)
+ platform_driver_unregister(plat_drivers[i]);
+
#ifdef PCI_DRIVER
pci_unregister_driver(&PCI_DRIVER);
#endif
diff --git a/drivers/usb/host/ehci-msm-hsic.c b/drivers/usb/host/ehci-msm-hsic.c
new file mode 100644
index 0000000..1b8b5d6
--- /dev/null
+++ b/drivers/usb/host/ehci-msm-hsic.c
@@ -0,0 +1,795 @@
+/* ehci-msm-hsic.c - HSUSB Host Controller Driver Implementation
+ *
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * Partly derived from ehci-fsl.c and ehci-hcd.c
+ * Copyright (c) 2000-2004 by David Brownell
+ * Copyright (c) 2005 MontaVista Software
+ *
+ * All source code in this file is licensed under the following license except
+ * where indicated.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, you can find it at http://www.fsf.org
+ */
+
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/wakelock.h>
+#include <linux/pm_runtime.h>
+#include <linux/regulator/consumer.h>
+
+#include <linux/usb/msm_hsusb_hw.h>
+#include <linux/usb/msm_hsusb.h>
+#include <linux/gpio.h>
+#include <mach/clk.h>
+#include <mach/msm_iomap.h>
+
+#define MSM_USB_BASE (hcd->regs)
+
+struct msm_hsic_hcd {
+ struct ehci_hcd ehci;
+ struct device *dev;
+ struct clk *ahb_clk;
+ struct clk *sys_clk;
+ struct clk *fs_xcvr_clk;
+ struct clk *hsic_clk;
+ struct clk *cal_clk;
+ struct regulator *hsic_vddcx;
+ bool async_int;
+ atomic_t in_lpm;
+ struct wake_lock wlock;
+};
+
+static inline struct msm_hsic_hcd *hcd_to_hsic(struct usb_hcd *hcd)
+{
+ return (struct msm_hsic_hcd *) (hcd->hcd_priv);
+}
+
+static inline struct usb_hcd *hsic_to_hcd(struct msm_hsic_hcd *mehci)
+{
+ return container_of((void *) mehci, struct usb_hcd, hcd_priv);
+}
+
+#define ULPI_IO_TIMEOUT_USEC (10 * 1000)
+
+#define USB_PHY_VDD_DIG_VOL_MIN 1000000 /* uV */
+#define USB_PHY_VDD_DIG_VOL_MAX 1320000 /* uV */
+#define USB_PHY_VDD_DIG_LOAD 49360 /* uA */
+
+static int msm_hsic_init_vddcx(struct msm_hsic_hcd *mehci, int init)
+{
+ int ret = 0;
+
+ if (!init)
+ goto disable_reg;
+
+ mehci->hsic_vddcx = regulator_get(mehci->dev, "HSIC_VDDCX");
+ if (IS_ERR(mehci->hsic_vddcx)) {
+ dev_err(mehci->dev, "unable to get hsic vddcx\n");
+ return PTR_ERR(mehci->hsic_vddcx);
+ }
+
+ ret = regulator_set_voltage(mehci->hsic_vddcx,
+ USB_PHY_VDD_DIG_VOL_MIN,
+ USB_PHY_VDD_DIG_VOL_MAX);
+ if (ret) {
+ dev_err(mehci->dev, "unable to set the voltage"
+ "for hsic vddcx\n");
+ goto reg_set_voltage_err;
+ }
+
+ ret = regulator_set_optimum_mode(mehci->hsic_vddcx,
+ USB_PHY_VDD_DIG_LOAD);
+ if (ret < 0) {
+ pr_err("%s: Unable to set optimum mode of the regulator:"
+ "VDDCX\n", __func__);
+ goto reg_optimum_mode_err;
+ }
+
+ ret = regulator_enable(mehci->hsic_vddcx);
+ if (ret) {
+ dev_err(mehci->dev, "unable to enable hsic vddcx\n");
+ goto reg_enable_err;
+ }
+
+ return 0;
+
+disable_reg:
+ regulator_disable(mehci->hsic_vddcx);
+reg_enable_err:
+ regulator_set_optimum_mode(mehci->hsic_vddcx, 0);
+reg_optimum_mode_err:
+ regulator_set_voltage(mehci->hsic_vddcx, 0,
+ USB_PHY_VDD_DIG_VOL_MIN);
+reg_set_voltage_err:
+ regulator_put(mehci->hsic_vddcx);
+
+ return ret;
+
+}
+
+static int ulpi_write(struct msm_hsic_hcd *mehci, u32 val, u32 reg)
+{
+ struct usb_hcd *hcd = hsic_to_hcd(mehci);
+ int cnt = 0;
+
+ /* initiate write operation */
+ writel_relaxed(ULPI_RUN | ULPI_WRITE |
+ ULPI_ADDR(reg) | ULPI_DATA(val),
+ USB_ULPI_VIEWPORT);
+
+ /* wait for completion */
+ while (cnt < ULPI_IO_TIMEOUT_USEC) {
+ if (!(readl_relaxed(USB_ULPI_VIEWPORT) & ULPI_RUN))
+ break;
+ udelay(1);
+ cnt++;
+ }
+
+ if (cnt >= ULPI_IO_TIMEOUT_USEC) {
+ dev_err(mehci->dev, "ulpi_write: timeout\n");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+static int msm_hsic_config_gpios(struct msm_hsic_hcd *mehci, int gpio_en)
+{
+ int rc = 0;
+ struct msm_hsic_host_platform_data *pdata;
+
+ pdata = mehci->dev->platform_data;
+ /*
+ * In future versions, dedicated lines might be used for HSIC
+ * strobe and data instead of gpios. Hence returning zero value.
+ */
+ if (!pdata->strobe || !pdata->data)
+ return rc;
+
+ if (!gpio_en)
+ goto free_gpio;
+
+ rc = gpio_request(pdata->strobe, "HSIC_STROBE_GPIO");
+ if (rc < 0) {
+ dev_err(mehci->dev, "gpio request failed for HSIC STROBE\n");
+ return rc;
+ }
+
+ rc = gpio_request(pdata->data, "HSIC_DATA_GPIO");
+ if (rc < 0) {
+ dev_err(mehci->dev, "gpio request failed for HSIC DATA\n");
+ goto free_strobe;
+ }
+
+ return 0;
+
+free_gpio:
+ gpio_free(pdata->data);
+free_strobe:
+ gpio_free(pdata->strobe);
+
+ return rc;
+}
+
+static int msm_hsic_phy_clk_reset(struct msm_hsic_hcd *mehci)
+{
+ int ret;
+
+ clk_enable(mehci->fs_xcvr_clk);
+
+ ret = clk_reset(mehci->sys_clk, CLK_RESET_ASSERT);
+ if (ret) {
+ clk_disable(mehci->fs_xcvr_clk);
+ dev_err(mehci->dev, "usb phy clk assert failed\n");
+ return ret;
+ }
+ usleep_range(10000, 12000);
+ clk_disable(mehci->fs_xcvr_clk);
+
+ ret = clk_reset(mehci->sys_clk, CLK_RESET_DEASSERT);
+ if (ret)
+ dev_err(mehci->dev, "usb phy clk deassert failed\n");
+
+ return ret;
+}
+
+static int msm_hsic_phy_reset(struct msm_hsic_hcd *mehci)
+{
+ struct usb_hcd *hcd = hsic_to_hcd(mehci);
+ u32 val;
+ int ret;
+
+ ret = msm_hsic_phy_clk_reset(mehci);
+ if (ret)
+ return ret;
+
+ val = readl_relaxed(USB_PORTSC) & ~PORTSC_PTS_MASK;
+ writel_relaxed(val | PORTSC_PTS_ULPI, USB_PORTSC);
+
+ /* Ensure that RESET operation is completed before turning off clock */
+ mb();
+ dev_dbg(mehci->dev, "phy_reset: success\n");
+
+ return 0;
+}
+
+#define HSIC_GPIO150_PAD_CTL (MSM_TLMM_BASE+0x20C0)
+#define HSIC_GPIO151_PAD_CTL (MSM_TLMM_BASE+0x20C4)
+#define HSIC_CAL_PAD_CTL (MSM_TLMM_BASE+0x20C8)
+#define HSIC_LV_MODE 0x04
+#define HSIC_PAD_CALIBRATION 0xA8
+#define HSIC_GPIO_PAD_VAL 0x0A0AAA10
+#define LINK_RESET_TIMEOUT_USEC (250 * 1000)
+static int msm_hsic_reset(struct msm_hsic_hcd *mehci)
+{
+ struct usb_hcd *hcd = hsic_to_hcd(mehci);
+ int cnt = 0;
+ int ret;
+
+ ret = msm_hsic_phy_reset(mehci);
+ if (ret) {
+ dev_err(mehci->dev, "phy_reset failed\n");
+ return ret;
+ }
+
+ writel_relaxed(USBCMD_RESET, USB_USBCMD);
+ while (cnt < LINK_RESET_TIMEOUT_USEC) {
+ if (!(readl_relaxed(USB_USBCMD) & USBCMD_RESET))
+ break;
+ udelay(1);
+ cnt++;
+ }
+ if (cnt >= LINK_RESET_TIMEOUT_USEC)
+ return -ETIMEDOUT;
+
+ /* select ULPI phy */
+ writel_relaxed(0x80000000, USB_PORTSC);
+
+ /* TODO: Need to confirm if HSIC PHY also requires delay after RESET */
+ msleep(100);
+
+ /* HSIC PHY Initialization */
+ /* Enable LV_MODE in HSIC_CAL_PAD_CTL register */
+ writel_relaxed(HSIC_LV_MODE, HSIC_CAL_PAD_CTL);
+
+ /*set periodic calibration interval to ~2.048sec in HSIC_IO_CAL_REG */
+ ulpi_write(mehci, 0xFF, 0x33);
+
+ /* Enable periodic IO calibration in HSIC_CFG register */
+ ulpi_write(mehci, HSIC_PAD_CALIBRATION, 0x30);
+
+ /* Configure GPIO 150/151 pins for HSIC functionality mode */
+ ret = msm_hsic_config_gpios(mehci, 1);
+ if (ret) {
+ dev_err(mehci->dev, " gpio configuarion failed\n");
+ return ret;
+ }
+
+ /* Set LV_MODE=0x1 and DCC=0x2 in HSIC_GPIO150/151_PAD_CTL register */
+ writel_relaxed(HSIC_GPIO_PAD_VAL, HSIC_GPIO150_PAD_CTL);
+ writel_relaxed(HSIC_GPIO_PAD_VAL, HSIC_GPIO151_PAD_CTL);
+
+ /* Enable HSIC mode in HSIC_CFG register */
+ ulpi_write(mehci, 0x01, 0x31);
+
+ return 0;
+}
+
+#define PHY_SUSPEND_TIMEOUT_USEC (500 * 1000)
+#define PHY_RESUME_TIMEOUT_USEC (100 * 1000)
+
+#ifdef CONFIG_PM_SLEEP
+static int msm_hsic_suspend(struct msm_hsic_hcd *mehci)
+{
+ struct usb_hcd *hcd = hsic_to_hcd(mehci);
+ int cnt = 0;
+ u32 val;
+
+ if (atomic_read(&mehci->in_lpm)) {
+ dev_dbg(mehci->dev, "%s called in lpm\n", __func__);
+ return 0;
+ }
+
+ disable_irq(hcd->irq);
+ /*
+ * PHY may take some time or even fail to enter into low power
+ * mode (LPM). Hence poll for 500 msec and reset the PHY and link
+ * in failure case.
+ */
+ val = readl_relaxed(USB_PORTSC) | PORTSC_PHCD;
+ writel_relaxed(val, USB_PORTSC);
+ while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
+ if (readl_relaxed(USB_PORTSC) & PORTSC_PHCD)
+ break;
+ udelay(1);
+ cnt++;
+ }
+
+ if (cnt >= PHY_SUSPEND_TIMEOUT_USEC) {
+ dev_err(mehci->dev, "Unable to suspend PHY\n");
+ msm_hsic_config_gpios(mehci, 0);
+ msm_hsic_reset(mehci);
+ enable_irq(hcd->irq);
+ return -ETIMEDOUT;
+ }
+
+ /*
+ * PHY has capability to generate interrupt asynchronously in low
+ * power mode (LPM). This interrupt is level triggered. So USB IRQ
+ * line must be disabled till async interrupt enable bit is cleared
+ * in USBCMD register. Assert STP (ULPI interface STOP signal) to
+ * block data communication from PHY.
+ */
+ writel_relaxed(readl_relaxed(USB_USBCMD) | ASYNC_INTR_CTRL |
+ ULPI_STP_CTRL, USB_USBCMD);
+
+ /*
+ * Ensure that hardware is put in low power mode before
+ * clocks are turned OFF and VDD is allowed to minimize.
+ */
+ mb();
+
+ clk_disable(mehci->sys_clk);
+ clk_disable(mehci->hsic_clk);
+ clk_disable(mehci->cal_clk);
+ clk_disable(mehci->ahb_clk);
+
+ atomic_set(&mehci->in_lpm, 1);
+ enable_irq(hcd->irq);
+ wake_unlock(&mehci->wlock);
+
+ dev_info(mehci->dev, "HSIC-USB in low power mode\n");
+
+ return 0;
+}
+
+static int msm_hsic_resume(struct msm_hsic_hcd *mehci)
+{
+ struct usb_hcd *hcd = hsic_to_hcd(mehci);
+ int cnt = 0;
+ unsigned temp;
+
+ if (!atomic_read(&mehci->in_lpm)) {
+ dev_dbg(mehci->dev, "%s called in !in_lpm\n", __func__);
+ return 0;
+ }
+
+ wake_lock(&mehci->wlock);
+
+ clk_enable(mehci->sys_clk);
+ clk_enable(mehci->hsic_clk);
+ clk_enable(mehci->cal_clk);
+ clk_enable(mehci->ahb_clk);
+
+ temp = readl_relaxed(USB_USBCMD);
+ temp &= ~ASYNC_INTR_CTRL;
+ temp &= ~ULPI_STP_CTRL;
+ writel_relaxed(temp, USB_USBCMD);
+
+ if (!(readl_relaxed(USB_PORTSC) & PORTSC_PHCD))
+ goto skip_phy_resume;
+
+ temp = readl_relaxed(USB_PORTSC) & ~PORTSC_PHCD;
+ writel_relaxed(temp, USB_PORTSC);
+ while (cnt < PHY_RESUME_TIMEOUT_USEC) {
+ if (!(readl_relaxed(USB_PORTSC) & PORTSC_PHCD) &&
+ (readl_relaxed(USB_ULPI_VIEWPORT) & ULPI_SYNC_STATE))
+ break;
+ udelay(1);
+ cnt++;
+ }
+
+ if (cnt >= PHY_RESUME_TIMEOUT_USEC) {
+ /*
+ * This is a fatal error. Reset the link and
+ * PHY to make hsic working.
+ */
+ dev_err(mehci->dev, "Unable to resume USB. Reset the hsic\n");
+ msm_hsic_config_gpios(mehci, 0);
+ msm_hsic_reset(mehci);
+ }
+
+skip_phy_resume:
+
+ atomic_set(&mehci->in_lpm, 0);
+
+ if (mehci->async_int) {
+ mehci->async_int = false;
+ pm_runtime_put_noidle(mehci->dev);
+ enable_irq(hcd->irq);
+ }
+
+ dev_info(mehci->dev, "HSIC-USB exited from low power mode\n");
+
+ return 0;
+}
+#endif
+
+static irqreturn_t msm_hsic_irq(struct usb_hcd *hcd)
+{
+ struct msm_hsic_hcd *mehci = hcd_to_hsic(hcd);
+
+ if (atomic_read(&mehci->in_lpm)) {
+ disable_irq_nosync(hcd->irq);
+ mehci->async_int = true;
+ pm_runtime_get(mehci->dev);
+ return IRQ_HANDLED;
+ }
+
+ return ehci_irq(hcd);
+}
+
+static int ehci_hsic_reset(struct usb_hcd *hcd)
+{
+ struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+ int retval;
+
+ ehci->caps = USB_CAPLENGTH;
+ ehci->regs = USB_CAPLENGTH +
+ HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
+ dbg_hcs_params(ehci, "reset");
+ dbg_hcc_params(ehci, "reset");
+
+ /* cache the data to minimize the chip reads*/
+ ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
+
+ hcd->has_tt = 1;
+ ehci->sbrn = HCD_USB2;
+
+ retval = ehci_halt(ehci);
+ if (retval)
+ return retval;
+
+ /* data structure init */
+ retval = ehci_init(hcd);
+ if (retval)
+ return retval;
+
+ retval = ehci_reset(ehci);
+ if (retval)
+ return retval;
+
+ /* bursts of unspecified length. */
+ writel_relaxed(0, USB_AHBBURST);
+ /* Use the AHB transactor */
+ writel_relaxed(0, USB_AHBMODE);
+ /* Disable streaming mode and select host mode */
+ writel_relaxed(0x13, USB_USBMODE);
+
+ ehci_port_power(ehci, 1);
+ return 0;
+}
+
+static struct hc_driver msm_hsic_driver = {
+ .description = hcd_name,
+ .product_desc = "Qualcomm EHCI Host Controller using HSIC",
+ .hcd_priv_size = sizeof(struct msm_hsic_hcd),
+
+ /*
+ * generic hardware linkage
+ */
+ .irq = msm_hsic_irq,
+ .flags = HCD_USB2 | HCD_MEMORY,
+
+ .reset = ehci_hsic_reset,
+ .start = ehci_run,
+
+ .stop = ehci_stop,
+ .shutdown = ehci_shutdown,
+
+ /*
+ * managing i/o requests and associated device resources
+ */
+ .urb_enqueue = ehci_urb_enqueue,
+ .urb_dequeue = ehci_urb_dequeue,
+ .endpoint_disable = ehci_endpoint_disable,
+ .endpoint_reset = ehci_endpoint_reset,
+ .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
+
+ /*
+ * scheduling support
+ */
+ .get_frame_number = ehci_get_frame,
+
+ /*
+ * root hub support
+ */
+ .hub_status_data = ehci_hub_status_data,
+ .hub_control = ehci_hub_control,
+ .relinquish_port = ehci_relinquish_port,
+ .port_handed_over = ehci_port_handed_over,
+
+ /*
+ * PM support
+ */
+ .bus_suspend = ehci_bus_suspend,
+ .bus_resume = ehci_bus_resume,
+};
+
+static int msm_hsic_init_clocks(struct msm_hsic_hcd *mehci, u32 init)
+{
+ int ret = 0;
+
+ if (!init)
+ goto put_clocks;
+
+ /*sys_clk is required for LINK protocol engine,it should be at 60MHz */
+ mehci->sys_clk = clk_get(mehci->dev, "usb_hsic_system_clk");
+ if (IS_ERR(mehci->sys_clk)) {
+ dev_err(mehci->dev, "failed to get hsic_sys_clk\n");
+ ret = PTR_ERR(mehci->sys_clk);
+ return ret;
+ }
+ clk_set_rate(mehci->sys_clk, 60000000);
+
+ /* 60MHz fs_xcvr_clk is for LINK to be used during PHY RESET */
+ mehci->fs_xcvr_clk = clk_get(mehci->dev, "usb_hsic_xcvr_fs_clk");
+ if (IS_ERR(mehci->fs_xcvr_clk)) {
+ dev_err(mehci->dev, "failed to get fs_xcvr_clk\n");
+ ret = PTR_ERR(mehci->fs_xcvr_clk);
+ goto put_sys_clk;
+ }
+ clk_set_rate(mehci->fs_xcvr_clk, 60000000);
+
+ /* 480MHz hsic_clk is required for HSIC PHY operation */
+ mehci->hsic_clk = clk_get(mehci->dev, "usb_hsic_hsic_clk");
+ if (IS_ERR(mehci->hsic_clk)) {
+ dev_err(mehci->dev, "failed to get hsic_clk\n");
+ ret = PTR_ERR(mehci->hsic_clk);
+ goto put_fs_xcvr_clk;
+ }
+ clk_set_rate(mehci->hsic_clk, 480000000);
+
+ /* 10MHz cal_clk is required for calibration of I/O pads */
+ mehci->cal_clk = clk_get(mehci->dev, "usb_hsic_hsio_cal_clk");
+ if (IS_ERR(mehci->cal_clk)) {
+ dev_err(mehci->dev, "failed to get hsic_cal_clk\n");
+ ret = PTR_ERR(mehci->cal_clk);
+ goto put_hsic_clk;
+ }
+ clk_set_rate(mehci->cal_clk, 10000000);
+
+ /* ahb_clk is required for data transfers */
+ mehci->ahb_clk = clk_get(mehci->dev, "usb_hsic_p_clk");
+ if (IS_ERR(mehci->ahb_clk)) {
+ dev_err(mehci->dev, "failed to get hsic_ahb_clk\n");
+ ret = PTR_ERR(mehci->ahb_clk);
+ goto put_cal_clk;
+ }
+
+ clk_enable(mehci->sys_clk);
+ clk_enable(mehci->hsic_clk);
+ clk_enable(mehci->cal_clk);
+ clk_enable(mehci->ahb_clk);
+
+ return 0;
+
+put_clocks:
+ clk_disable(mehci->sys_clk);
+ clk_disable(mehci->hsic_clk);
+ clk_disable(mehci->cal_clk);
+ clk_disable(mehci->ahb_clk);
+ clk_put(mehci->ahb_clk);
+put_cal_clk:
+ clk_put(mehci->cal_clk);
+put_hsic_clk:
+ clk_put(mehci->hsic_clk);
+put_fs_xcvr_clk:
+ clk_put(mehci->fs_xcvr_clk);
+put_sys_clk:
+ clk_put(mehci->sys_clk);
+
+ return ret;
+}
+static int __devinit ehci_hsic_msm_probe(struct platform_device *pdev)
+{
+ struct usb_hcd *hcd;
+ struct resource *res;
+ struct msm_hsic_hcd *mehci;
+ int ret;
+
+ dev_dbg(&pdev->dev, "ehci_msm-hsic probe\n");
+
+ hcd = usb_create_hcd(&msm_hsic_driver, &pdev->dev,
+ dev_name(&pdev->dev));
+ if (!hcd) {
+ dev_err(&pdev->dev, "Unable to create HCD\n");
+ return -ENOMEM;
+ }
+
+ hcd->irq = platform_get_irq(pdev, 0);
+ if (hcd->irq < 0) {
+ dev_err(&pdev->dev, "Unable to get IRQ resource\n");
+ ret = hcd->irq;
+ goto put_hcd;
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(&pdev->dev, "Unable to get memory resource\n");
+ ret = -ENODEV;
+ goto put_hcd;
+ }
+
+ hcd->rsrc_start = res->start;
+ hcd->rsrc_len = resource_size(res);
+ hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
+ if (!hcd->regs) {
+ dev_err(&pdev->dev, "ioremap failed\n");
+ ret = -ENOMEM;
+ goto put_hcd;
+ }
+
+ mehci = hcd_to_hsic(hcd);
+ mehci->dev = &pdev->dev;
+
+ ret = msm_hsic_init_clocks(mehci, 1);
+ if (ret) {
+ dev_err(&pdev->dev, "unable to initialize clocks\n");
+ ret = -ENODEV;
+ goto unmap;
+ }
+
+ ret = msm_hsic_init_vddcx(mehci, 1);
+ if (ret) {
+ dev_err(&pdev->dev, "unable to initialize VDDCX\n");
+ ret = -ENODEV;
+ goto deinit_clocks;
+ }
+
+ ret = msm_hsic_reset(mehci);
+ if (ret) {
+ dev_err(&pdev->dev, "unable to initialize PHY\n");
+ goto deinit_vddcx;
+ }
+
+ ret = usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
+ if (ret) {
+ dev_err(&pdev->dev, "unable to register HCD\n");
+ goto unconfig_gpio;
+ }
+
+ device_init_wakeup(&pdev->dev, 1);
+ wake_lock_init(&mehci->wlock, WAKE_LOCK_SUSPEND, dev_name(&pdev->dev));
+ wake_lock(&mehci->wlock);
+ /*
+ * This pdev->dev is assigned parent of root-hub by USB core,
+ * hence, runtime framework automatically calls this driver's
+ * runtime APIs based on root-hub's state.
+ */
+ pm_runtime_set_active(&pdev->dev);
+ pm_runtime_enable(&pdev->dev);
+
+ return 0;
+
+unconfig_gpio:
+ msm_hsic_config_gpios(mehci, 0);
+deinit_vddcx:
+ msm_hsic_init_vddcx(mehci, 0);
+deinit_clocks:
+ msm_hsic_init_clocks(mehci, 0);
+unmap:
+ iounmap(hcd->regs);
+put_hcd:
+ usb_put_hcd(hcd);
+
+ return ret;
+}
+
+static int __devexit ehci_hsic_msm_remove(struct platform_device *pdev)
+{
+ struct usb_hcd *hcd = platform_get_drvdata(pdev);
+ struct msm_hsic_hcd *mehci = hcd_to_hsic(hcd);
+
+ device_init_wakeup(&pdev->dev, 0);
+ pm_runtime_disable(&pdev->dev);
+ pm_runtime_set_suspended(&pdev->dev);
+
+ usb_remove_hcd(hcd);
+ msm_hsic_config_gpios(mehci, 0);
+ msm_hsic_init_vddcx(mehci, 0);
+
+ msm_hsic_init_clocks(mehci, 0);
+ wake_lock_destroy(&mehci->wlock);
+ iounmap(hcd->regs);
+ usb_put_hcd(hcd);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int msm_hsic_pm_suspend(struct device *dev)
+{
+ struct usb_hcd *hcd = dev_get_drvdata(dev);
+ struct msm_hsic_hcd *mehci = hcd_to_hsic(hcd);
+
+ dev_dbg(dev, "ehci-msm-hsic PM suspend\n");
+
+ if (device_may_wakeup(dev))
+ enable_irq_wake(hcd->irq);
+
+ return msm_hsic_suspend(mehci);
+
+}
+
+static int msm_hsic_pm_resume(struct device *dev)
+{
+ int ret;
+ struct usb_hcd *hcd = dev_get_drvdata(dev);
+ struct msm_hsic_hcd *mehci = hcd_to_hsic(hcd);
+
+ dev_dbg(dev, "ehci-msm-hsic PM resume\n");
+
+ if (device_may_wakeup(dev))
+ disable_irq_wake(hcd->irq);
+
+ ret = msm_hsic_resume(mehci);
+ if (ret)
+ return ret;
+
+ /* Bring the device to full powered state upon system resume */
+ pm_runtime_disable(dev);
+ pm_runtime_set_active(dev);
+ pm_runtime_enable(dev);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_PM_RUNTIME
+static int msm_hsic_runtime_idle(struct device *dev)
+{
+ dev_dbg(dev, "EHCI runtime idle\n");
+
+ return 0;
+}
+
+static int msm_hsic_runtime_suspend(struct device *dev)
+{
+ struct usb_hcd *hcd = dev_get_drvdata(dev);
+ struct msm_hsic_hcd *mehci = hcd_to_hsic(hcd);
+
+ dev_dbg(dev, "EHCI runtime suspend\n");
+ return msm_hsic_suspend(mehci);
+}
+
+static int msm_hsic_runtime_resume(struct device *dev)
+{
+ struct usb_hcd *hcd = dev_get_drvdata(dev);
+ struct msm_hsic_hcd *mehci = hcd_to_hsic(hcd);
+
+ dev_dbg(dev, "EHCI runtime resume\n");
+ return msm_hsic_resume(mehci);
+}
+#endif
+
+#ifdef CONFIG_PM
+static const struct dev_pm_ops msm_hsic_dev_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(msm_hsic_pm_suspend, msm_hsic_pm_resume)
+ SET_RUNTIME_PM_OPS(msm_hsic_runtime_suspend, msm_hsic_runtime_resume,
+ msm_hsic_runtime_idle)
+};
+#endif
+
+static struct platform_driver ehci_msm_hsic_driver = {
+ .probe = ehci_hsic_msm_probe,
+ .remove = __devexit_p(ehci_hsic_msm_remove),
+ .driver = {
+ .name = "msm_hsic_host",
+#ifdef CONFIG_PM
+ .pm = &msm_hsic_dev_pm_ops,
+#endif
+ },
+};
diff --git a/drivers/usb/misc/Kconfig b/drivers/usb/misc/Kconfig
index 527dc85..1135806 100644
--- a/drivers/usb/misc/Kconfig
+++ b/drivers/usb/misc/Kconfig
@@ -280,3 +280,28 @@
To compile this driver as a module, choose M here: the
module will be called qcaux. If unsure, choose N.
+
+config USB_QCOM_DUN_BRIDGE
+ tristate "USB Qualcomm modem DUN bridge driver"
+ depends on USB && !USB_SERIAL_QUALCOMM
+ help
+ Say Y here if you have a Qualcomm modem device connected via USB that
+ will be bridged in kernel space. This driver will enable bridging
+ with the gadget serial driver for use in dial-up networking. This is
+ not the same as the qcserial driver that exposes a TTY interface to
+ userspace.
+
+ To compile this driver as a module, choose M here: the module
+ will be called dun_bridge.
+
+config USB_QCOM_DUN_BRIDGE_TEST
+ tristate "USB Qualcomm modem DUN bridge driver test"
+ depends on USB && USB_QCOM_DUN_BRIDGE && !USB_SERIAL_QUALCOMM
+ help
+ Say Y here if you want to enable the test hook for the
+ Qualcomm modem bridge driver. When enabled, this will create
+ a debugfs file entry named "dun_bridge_test" which can be used
+ to read and write directly to the modem.
+
+ To compile this driver as a module, choose M here: the module
+ will be called dun_bridge_test.
diff --git a/drivers/usb/misc/Makefile b/drivers/usb/misc/Makefile
index 20ee62a..03568bc 100644
--- a/drivers/usb/misc/Makefile
+++ b/drivers/usb/misc/Makefile
@@ -31,3 +31,5 @@
obj-$(CONFIG_USB_QCOM_DIAG) += diag_usb.o
obj-$(CONFIG_USB_QCOM_DIAG_TEST) += diag_bridge_test.o
+obj-$(CONFIG_USB_QCOM_DUN_BRIDGE) += dun_bridge.o
+obj-$(CONFIG_USB_QCOM_DUN_BRIDGE_TEST) += dun_bridge_test.o
diff --git a/drivers/usb/misc/dun_bridge.c b/drivers/usb/misc/dun_bridge.c
new file mode 100644
index 0000000..aca7714
--- /dev/null
+++ b/drivers/usb/misc/dun_bridge.c
@@ -0,0 +1,520 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/kref.h>
+#include <linux/platform_device.h>
+#include <linux/usb.h>
+#include <linux/usb/cdc.h>
+#include <linux/usb/ch9.h>
+#include <asm/unaligned.h>
+#include <mach/usb_dun_bridge.h>
+
+#define DRIVER_DESC "Qualcomm USB DUN bridge driver"
+#define DRIVER_VERSION "1.0"
+
+struct dun_bridge {
+ struct usb_device *udev;
+ struct usb_interface *intf;
+ struct usb_anchor submitted;
+ u8 int_in_epaddr;
+ unsigned in, out; /* bulk in/out pipes */
+
+ struct urb *inturb;
+ struct usb_ctrlrequest cmd;
+ u8 *ctrl_buf;
+
+ struct kref kref;
+ struct platform_device *pdev;
+
+ struct dun_bridge_ops *ops;
+};
+
+static struct dun_bridge *__dev;
+
+/* This assumes that __dev has already been initialized by probe(). */
+int dun_bridge_open(struct dun_bridge_ops *ops)
+{
+ struct dun_bridge *dev = __dev;
+ int ret = 0;
+
+ if (!dev) {
+ err("%s: dev is null", __func__);
+ return -ENODEV;
+ }
+
+ if (!ops || !ops->read_complete || !ops->write_complete)
+ return -EINVAL;
+
+ dev->ops = ops;
+ if (ops->ctrl_status) {
+ ret = usb_submit_urb(dev->inturb, GFP_KERNEL);
+ if (ret)
+ pr_err("%s: submitting int urb failed: %d\n",
+ __func__, ret);
+ }
+
+ return ret;
+}
+EXPORT_SYMBOL(dun_bridge_open);
+
+int dun_bridge_close(void)
+{
+ struct dun_bridge *dev = __dev;
+ if (!dev)
+ return -ENODEV;
+
+ dev_dbg(&dev->udev->dev, "%s:", __func__);
+ usb_unlink_anchored_urbs(&dev->submitted);
+ usb_unlink_urb(dev->inturb);
+ dev->ops = NULL;
+
+ return 0;
+}
+EXPORT_SYMBOL(dun_bridge_close);
+
+static void read_cb(struct urb *urb)
+{
+ struct dun_bridge *dev = urb->context;
+ struct dun_bridge_ops *ops;
+
+ if (!dev || !dev->intf) {
+ pr_err("%s: device is disconnected\n", __func__);
+ kfree(urb->transfer_buffer);
+ return;
+ }
+
+ dev_dbg(&dev->udev->dev, "%s: status:%d actual:%d\n", __func__,
+ urb->status, urb->actual_length);
+
+ usb_autopm_put_interface(dev->intf);
+ ops = dev->ops;
+ if (ops)
+ ops->read_complete(ops->ctxt,
+ urb->transfer_buffer,
+ urb->transfer_buffer_length,
+ /* callback must check this value for error */
+ urb->status < 0 ?
+ urb->status : urb->actual_length);
+ else {
+ /* can't call back, free buffer on caller's behalf */
+ dev_err(&dev->udev->dev, "cannot complete read callback\n");
+ kfree(urb->transfer_buffer);
+ }
+}
+
+int dun_bridge_read(void *data, int len)
+{
+ struct dun_bridge *dev = __dev;
+ struct urb *urb;
+ int ret;
+
+ if (!dev || !dev->ops)
+ return -ENODEV;
+
+ if (!dev->intf) {
+ pr_err("%s: device is disconnected\n", __func__);
+ return -ENODEV;
+ }
+
+ if (!len) {
+ dev_err(&dev->udev->dev, "%s: invalid len:%d\n", __func__, len);
+ return -EINVAL;
+ }
+
+ urb = usb_alloc_urb(0, GFP_KERNEL);
+ if (!urb) {
+ dev_err(&dev->udev->dev, "%s: Unable to alloc urb\n", __func__);
+ return -ENOMEM;
+ }
+
+ usb_fill_bulk_urb(urb, dev->udev, dev->in,
+ data, len, read_cb, dev);
+ usb_anchor_urb(urb, &dev->submitted);
+
+ usb_autopm_get_interface(dev->intf);
+ ret = usb_submit_urb(urb, GFP_KERNEL);
+ if (ret) {
+ dev_err(&dev->udev->dev, "%s: submit urb err:%d\n",
+ __func__, ret);
+ usb_unanchor_urb(urb);
+ usb_autopm_put_interface(dev->intf);
+ }
+
+ usb_free_urb(urb);
+ return ret;
+}
+EXPORT_SYMBOL(dun_bridge_read);
+
+static void write_cb(struct urb *urb)
+{
+ struct dun_bridge *dev = urb->context;
+ struct dun_bridge_ops *ops;
+
+ if (!dev || !dev->intf) {
+ pr_err("%s: device is disconnected\n", __func__);
+ kfree(urb->transfer_buffer);
+ return;
+ }
+
+ dev_dbg(&dev->udev->dev, "%s: status:%d actual:%d\n", __func__,
+ urb->status, urb->actual_length);
+
+ usb_autopm_put_interface(dev->intf);
+ ops = dev->ops;
+ if (ops)
+ ops->write_complete(ops->ctxt,
+ urb->transfer_buffer,
+ urb->transfer_buffer_length,
+ /* callback must check this value for error */
+ urb->status < 0 ?
+ urb->status : urb->actual_length);
+ else {
+ /* can't call back, free buffer on caller's behalf */
+ dev_err(&dev->udev->dev, "cannot complete write callback\n");
+ kfree(urb->transfer_buffer);
+ }
+}
+
+int dun_bridge_write(void *data, int len)
+{
+ struct dun_bridge *dev = __dev;
+ struct urb *urb;
+ int ret;
+
+ if (!dev || !dev->ops)
+ return -ENODEV;
+
+ if (!dev->intf) {
+ pr_err("%s: device is disconnected\n", __func__);
+ return -ENODEV;
+ }
+
+ if (!len) {
+ dev_err(&dev->udev->dev, "%s: invalid len:%d\n", __func__, len);
+ return -EINVAL;
+ }
+
+ urb = usb_alloc_urb(0, GFP_KERNEL);
+ if (!urb) {
+ dev_err(&dev->udev->dev, "%s: Unable to alloc urb\n", __func__);
+ return -ENOMEM;
+ }
+
+ usb_fill_bulk_urb(urb, dev->udev, dev->out,
+ data, len, write_cb, dev);
+ usb_anchor_urb(urb, &dev->submitted);
+
+ usb_autopm_get_interface(dev->intf);
+ ret = usb_submit_urb(urb, GFP_KERNEL);
+ if (ret) {
+ dev_err(&dev->udev->dev, "%s: submit urb err:%d\n",
+ __func__, ret);
+ usb_unanchor_urb(urb);
+ usb_autopm_put_interface(dev->intf);
+ }
+
+ usb_free_urb(urb);
+ return ret;
+}
+EXPORT_SYMBOL(dun_bridge_write);
+
+static void ctrl_cb(struct urb *urb)
+{
+ struct dun_bridge *dev = urb->context;
+ usb_autopm_put_interface(dev->intf);
+}
+
+int dun_bridge_send_ctrl_bits(unsigned ctrl_bits)
+{
+ struct dun_bridge *dev = __dev;
+ struct urb *urb = NULL;
+ int ret;
+
+ if (!dev || !dev->intf) {
+ pr_err("%s: device is disconnected\n", __func__);
+ return -ENODEV;
+ }
+
+ dev_dbg(&dev->udev->dev, "%s: %#x", __func__, ctrl_bits);
+
+ dev->cmd.bRequestType = USB_TYPE_CLASS | USB_RECIP_INTERFACE;
+ dev->cmd.bRequest = USB_CDC_REQ_SET_CONTROL_LINE_STATE;
+ dev->cmd.wValue = cpu_to_le16(ctrl_bits);
+ dev->cmd.wIndex = cpu_to_le16(dev->int_in_epaddr);
+ dev->cmd.wLength = 0;
+
+ urb = usb_alloc_urb(0, GFP_ATOMIC);
+ if (!urb) {
+ dev_err(&dev->udev->dev, "%s: Unable to alloc urb\n", __func__);
+ return -ENOMEM;
+ }
+
+ usb_fill_control_urb(urb, dev->udev, usb_sndctrlpipe(dev->udev, 0),
+ (unsigned char *)&dev->cmd, NULL, 0,
+ ctrl_cb, dev);
+
+ usb_autopm_get_interface(dev->intf);
+ ret = usb_submit_urb(urb, GFP_ATOMIC);
+ if (ret) {
+ dev_err(&dev->udev->dev, "%s: submit urb err:%d\n",
+ __func__, ret);
+ usb_autopm_put_interface(dev->intf);
+ }
+
+ usb_free_urb(urb);
+ return ret;
+}
+EXPORT_SYMBOL(dun_bridge_send_ctrl_bits);
+
+static void int_cb(struct urb *urb)
+{
+ struct dun_bridge *dev = urb->context;
+ struct usb_cdc_notification *dr = urb->transfer_buffer;
+ unsigned char *data;
+ unsigned int ctrl_bits;
+ int status = urb->status;
+
+ if (!dev || !dev->intf) {
+ pr_err("%s: device is disconnected\n", __func__);
+ return;
+ }
+
+ switch (status) {
+ case 0:
+ /* success */
+ break;
+ case -ECONNRESET:
+ case -ENOENT:
+ case -ESHUTDOWN:
+ /* this urb is terminated, clean up */
+ dev_err(&dev->udev->dev,
+ "%s - urb shutting down with status: %d\n",
+ __func__, status);
+ return;
+ default:
+ dev_err(&dev->udev->dev,
+ "%s - nonzero urb status received: %d\n",
+ __func__, status);
+ goto resubmit_urb;
+ }
+
+ data = (unsigned char *)(dr + 1);
+ switch (dr->bNotificationType) {
+ case USB_CDC_NOTIFY_NETWORK_CONNECTION:
+ dev_dbg(&dev->udev->dev, "%s network\n", dr->wValue ?
+ "connected to" : "disconnected from");
+ break;
+
+ case USB_CDC_NOTIFY_SERIAL_STATE:
+ ctrl_bits = get_unaligned_le16(data);
+ dev_dbg(&dev->udev->dev, "serial state: %d\n", ctrl_bits);
+ if (dev->ops && dev->ops->ctrl_status)
+ dev->ops->ctrl_status(dev->ops->ctxt, ctrl_bits);
+ break;
+
+ default:
+ dev_err(&dev->udev->dev, "unknown notification %d received: "
+ "index %d len %d data0 %d data1 %d\n",
+ dr->bNotificationType, dr->wIndex,
+ dr->wLength, data[0], data[1]);
+ break;
+ }
+resubmit_urb:
+ status = usb_submit_urb(dev->inturb, GFP_ATOMIC);
+ if (status)
+ dev_err(&dev->udev->dev, "%s: submit urb err:%d\n",
+ __func__, status);
+}
+
+static void dun_bridge_delete(struct kref *kref)
+{
+ struct dun_bridge *dev = container_of(kref, struct dun_bridge, kref);
+
+ __dev = NULL;
+ usb_put_dev(dev->udev);
+ usb_free_urb(dev->inturb);
+ kfree(dev->ctrl_buf);
+ kfree(dev);
+}
+
+static int
+dun_bridge_probe(struct usb_interface *intf, const struct usb_device_id *id)
+{
+ struct dun_bridge *dev;
+ struct usb_host_interface *iface_desc;
+ struct usb_endpoint_descriptor *epd;
+ __u8 iface_num;
+ int i;
+ int ctrlsize = 0;
+ int ret = -ENOMEM;
+
+ iface_desc = intf->cur_altsetting;
+ iface_num = iface_desc->desc.bInterfaceNumber;
+
+ /* is this interface supported? */
+ if (iface_num != id->driver_info)
+ return -ENODEV;
+
+ dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+ if (!dev) {
+ pr_err("%s: unable to allocate dev\n", __func__);
+ goto error;
+ }
+
+ dev->pdev = platform_device_alloc("dun_bridge", 0);
+ if (!dev->pdev) {
+ pr_err("%s: unable to allocate platform device\n", __func__);
+ kfree(dev);
+ return -ENOMEM;
+ }
+ __dev = dev;
+
+ kref_init(&dev->kref);
+ dev->udev = usb_get_dev(interface_to_usbdev(intf));
+ dev->intf = intf;
+
+ init_usb_anchor(&dev->submitted);
+ dev->inturb = usb_alloc_urb(0, GFP_KERNEL);
+ if (!dev->inturb) {
+ ret = -ENOMEM;
+ goto error;
+ }
+
+ for (i = 0; i < iface_desc->desc.bNumEndpoints; ++i) {
+ epd = &iface_desc->endpoint[i].desc;
+
+ if (usb_endpoint_is_int_in(epd)) {
+ dev->int_in_epaddr = epd->bEndpointAddress;
+ ctrlsize = le16_to_cpu(epd->wMaxPacketSize);
+
+ dev->ctrl_buf = kzalloc(ctrlsize, GFP_KERNEL);
+ if (!dev->ctrl_buf) {
+ ret = -ENOMEM;
+ goto error;
+ }
+
+ usb_fill_int_urb(dev->inturb, dev->udev,
+ usb_rcvintpipe(dev->udev,
+ dev->int_in_epaddr),
+ dev->ctrl_buf, ctrlsize,
+ int_cb, dev, epd->bInterval);
+
+ } else if (usb_endpoint_is_bulk_in(epd))
+ dev->in = usb_rcvbulkpipe(dev->udev,
+ epd->bEndpointAddress &
+ USB_ENDPOINT_NUMBER_MASK);
+
+ else if (usb_endpoint_is_bulk_out(epd))
+ dev->out = usb_sndbulkpipe(dev->udev,
+ epd->bEndpointAddress &
+ USB_ENDPOINT_NUMBER_MASK);
+ }
+
+ if (!dev->int_in_epaddr && !dev->in && !dev->out) {
+ dev_err(&dev->udev->dev, "%s: could not find all endpoints\n",
+ __func__);
+ ret = -ENODEV;
+ goto error;
+ }
+
+ usb_set_intfdata(intf, dev);
+ platform_device_add(dev->pdev);
+ return 0;
+error:
+ if (dev)
+ kref_put(&dev->kref, dun_bridge_delete);
+ return ret;
+}
+
+static void dun_bridge_disconnect(struct usb_interface *intf)
+{
+ struct dun_bridge *dev = usb_get_intfdata(intf);
+
+ platform_device_del(dev->pdev);
+ usb_set_intfdata(intf, NULL);
+ dev->intf = NULL;
+
+ kref_put(&dev->kref, dun_bridge_delete);
+
+ pr_debug("%s: DUN Bridge now disconnected\n", __func__);
+}
+
+static int dun_bridge_suspend(struct usb_interface *intf, pm_message_t message)
+{
+ struct dun_bridge *dev = usb_get_intfdata(intf);
+
+ dev_dbg(&dev->udev->dev, "%s:", __func__);
+ usb_unlink_anchored_urbs(&dev->submitted);
+ usb_unlink_urb(dev->inturb);
+
+ return 0;
+}
+
+static int dun_bridge_resume(struct usb_interface *intf)
+{
+ struct dun_bridge *dev = usb_get_intfdata(intf);
+ int ret = 0;
+
+ if (dev->ops && dev->ops->ctrl_status) {
+ ret = usb_submit_urb(dev->inturb, GFP_KERNEL);
+ if (ret)
+ dev_err(&dev->udev->dev, "%s: submit int urb err: %d\n",
+ __func__, ret);
+ }
+
+ return ret;
+}
+
+#define VALID_INTERFACE_NUM 2
+static const struct usb_device_id id_table[] = {
+ { USB_DEVICE(0x05c6, 0x9001), /* Generic QC Modem device */
+ .driver_info = VALID_INTERFACE_NUM },
+ { } /* Terminating entry */
+};
+MODULE_DEVICE_TABLE(usb, id_table);
+
+static struct usb_driver dun_bridge_driver = {
+ .name = "dun_usb_bridge",
+ .probe = dun_bridge_probe,
+ .disconnect = dun_bridge_disconnect,
+ .id_table = id_table,
+ .suspend = dun_bridge_suspend,
+ .resume = dun_bridge_resume,
+ .supports_autosuspend = true,
+};
+
+static int __init dun_bridge_init(void)
+{
+ int ret;
+
+ ret = usb_register(&dun_bridge_driver);
+ if (ret)
+ pr_err("%s: unable to register dun_bridge_driver\n", __func__);
+
+ return ret;
+}
+
+static void __exit dun_bridge_exit(void)
+{
+ usb_deregister(&dun_bridge_driver);
+}
+
+module_init(dun_bridge_init);
+module_exit(dun_bridge_exit);
+
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_LICENSE("GPL V2");
diff --git a/drivers/usb/misc/dun_bridge_test.c b/drivers/usb/misc/dun_bridge_test.c
new file mode 100644
index 0000000..d545e13
--- /dev/null
+++ b/drivers/usb/misc/dun_bridge_test.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/slab.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/debugfs.h>
+#include <linux/usb/cdc.h>
+#include <linux/uaccess.h>
+#include <mach/usb_dun_bridge.h>
+
+#define RD_BUF_SIZE 2048
+#define DUN_TEST_CONNECTED 0
+
+
+struct dun_bridge_test_dev {
+ char *read_buf;
+ size_t buflen;
+ struct work_struct read_w;
+ unsigned long flags;
+
+ struct dun_bridge_ops ops;
+};
+static struct dun_bridge_test_dev *__dev;
+
+static struct dentry *dfile;
+
+static void
+dun_bridge_test_read_complete(void *d, char *buf, size_t size, size_t actual)
+{
+ if (actual < 0) {
+ pr_err("%s: read complete err\n", __func__);
+ return;
+ }
+
+ __dev->buflen = actual;
+ buf[actual] = 0;
+
+ pr_info("%s: %s\n", __func__, buf);
+
+ if (test_bit(DUN_TEST_CONNECTED, &__dev->flags))
+ schedule_work(&__dev->read_w);
+}
+
+static void dun_bridge_test_read_work(struct work_struct *w)
+{
+ struct dun_bridge_test_dev *dev =
+ container_of(w, struct dun_bridge_test_dev, read_w);
+
+ dun_bridge_read(dev->read_buf, RD_BUF_SIZE);
+}
+
+static void
+dun_bridge_test_write_complete(void *d, char *buf, size_t size, size_t actual)
+{
+ struct dun_bridge_test_dev *dev = d;
+
+ if (actual > 0)
+ schedule_work(&dev->read_w);
+
+ kfree(buf);
+}
+
+#if defined(CONFIG_DEBUG_FS)
+#define DEBUG_BUF_SIZE 1024
+
+#define ACM_CTRL_DTR 0x01
+#define ACM_CTRL_RTS 0x02
+
+static int debug_open(struct inode *inode, struct file *file)
+{
+ struct dun_bridge_test_dev *dev = __dev;
+ int ret = 0;
+
+ if (!dev)
+ return -ENODEV;
+
+ if (!test_bit(DUN_TEST_CONNECTED, &dev->flags)) {
+ ret = dun_bridge_open(&dev->ops);
+ if (ret)
+ return ret;
+ set_bit(DUN_TEST_CONNECTED, &dev->flags);
+ dun_bridge_send_ctrl_bits(ACM_CTRL_DTR | ACM_CTRL_RTS);
+ }
+
+ return ret;
+}
+
+static ssize_t debug_read(struct file *file, char __user *ubuf,
+ size_t count, loff_t *ppos)
+{
+ struct dun_bridge_test_dev *dev = __dev;
+ return simple_read_from_buffer(ubuf, count, ppos,
+ dev->read_buf, dev->buflen);
+}
+
+static ssize_t debug_write(struct file *file, const char __user *ubuf,
+ size_t count, loff_t *ppos)
+{
+ struct dun_bridge_test_dev *dev = __dev;
+ unsigned char *buf;
+ int ret;
+
+ if (!dev)
+ return -ENODEV;
+
+ buf = kmalloc(count, GFP_KERNEL);
+ if (!buf) {
+ pr_err("%s: unable to allocate mem for writing\n", __func__);
+ return -ENOMEM;
+ }
+
+ if (!copy_from_user(buf, ubuf, count)) {
+ ret = dun_bridge_write(buf, count);
+ if (ret < 0) {
+ pr_err("%s: error writing to dun_bridge\n", __func__);
+ kfree(buf);
+ return ret;
+ }
+ } else {
+ pr_err("%s: error copying for writing\n", __func__);
+ kfree(buf);
+ }
+
+ return count;
+}
+
+const struct file_operations dun_bridge_test_debug_ops = {
+ .open = debug_open,
+ .read = debug_read,
+ .write = debug_write,
+};
+
+static void dun_bridge_test_debug_init(void)
+{
+ dfile = debugfs_create_file("dun_bridge_test", 0555, NULL,
+ NULL, &dun_bridge_test_debug_ops);
+}
+#else
+static void dun_bridge_test_debug_init(void) { }
+#endif
+
+static int __init dun_bridge_test_init(void)
+{
+ struct dun_bridge_test_dev *dev;
+
+ pr_info("%s\n", __func__);
+
+ dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+ if (!dev)
+ return -ENOMEM;
+
+ __dev = dev;
+
+ dev->ops.read_complete = dun_bridge_test_read_complete;
+ dev->ops.write_complete = dun_bridge_test_write_complete;
+ dev->read_buf = kmalloc(RD_BUF_SIZE, GFP_KERNEL);
+ if (!dev->read_buf) {
+ pr_err("%s: unable to allocate read buffer\n", __func__);
+ kfree(dev);
+ return -ENOMEM;
+ }
+
+ dev->ops.ctxt = dev;
+ INIT_WORK(&dev->read_w, dun_bridge_test_read_work);
+
+ dun_bridge_test_debug_init();
+
+ return 0;
+}
+
+static void __exit dun_bridge_test_exit(void)
+{
+ struct dun_bridge_test_dev *dev = __dev;
+
+ pr_info("%s:\n", __func__);
+
+ if (test_bit(DUN_TEST_CONNECTED, &dev->flags))
+ dun_bridge_close();
+
+ debugfs_remove(dfile);
+
+ kfree(dev->read_buf);
+ kfree(dev);
+}
+
+module_init(dun_bridge_test_init);
+module_exit(dun_bridge_test_exit);
+
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_LICENSE("GPL V2");
diff --git a/drivers/video/msm/Kconfig b/drivers/video/msm/Kconfig
index 7fd603d..34b564f 100644
--- a/drivers/video/msm/Kconfig
+++ b/drivers/video/msm/Kconfig
@@ -156,6 +156,10 @@
select FB_MSM_MIPI_DSI
default n
+config FB_MSM_MIPI_DSI_TRULY
+ bool
+ select FB_MSM_MIPI_DSI
+
config FB_MSM_MIPI_DSI_SIMULATOR
bool
select FB_MSM_MIPI_DSI
@@ -282,6 +286,10 @@
The panel is connected to the host
via Toshiba DSI-to-LVDS bridge.
+config FB_MSM_MIPI_TRULY_VIDEO_WVGA_PT
+ bool
+ select FB_MSM_MIPI_DSI_TRULY
+
config FB_MSM_MIPI_SIMULATOR_VIDEO
bool
select FB_MSM_MIPI_DSI_SIMULATOR
@@ -390,6 +398,7 @@
select FB_MSM_MIPI_TOSHIBA_VIDEO_WSVGA_PT
select FB_MSM_MIPI_RENESAS_VIDEO_FWVGA_PT
select FB_MSM_MIPI_RENESAS_CMD_FWVGA_PT
+ select FB_MSM_MIPI_TRULY_VIDEO_WVGA_PT
select FB_MSM_MIPI_NOVATEK_VIDEO_QHD_PT
select FB_MSM_MIPI_NOVATEK_CMD_QHD_PT
select FB_MSM_MIPI_SIMULATOR_VIDEO
@@ -489,6 +498,10 @@
bool "MIPI Chimei WXGA PT Panel"
select FB_MSM_MIPI_CHIMEI_WXGA
+config FB_MSM_MIPI_TRULY_VIDEO_WVGA_PT_PANEL
+ bool "MIPI Truly Video WVGA PT Panel"
+ select FB_MSM_MIPI_TRULY_VIDEO_WVGA_PT
+
config FB_MSM_MIPI_SIMULATOR_VIDEO_PANEL
bool "MIPI Simulator Video Panel"
select FB_MSM_MIPI_SIMULATOR_VIDEO
@@ -602,6 +615,14 @@
Support for HDCP mode for MSM HDMI 1080p Panel
Choose to enable HDCP
+config FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
+ depends on FB_MSM_HDMI_MSM_PANEL
+ bool "Enable CEC"
+ default n
+ ---help---
+ Support for HDMI CEC Feature
+ Choose to enable CEC
+
choice
depends on (FB_MSM_MDP22 || FB_MSM_MDP31 || FB_MSM_MDP40)
prompt "TVOut Region"
diff --git a/drivers/video/msm/Makefile b/drivers/video/msm/Makefile
index 3e89f0b..d6e8ced 100644
--- a/drivers/video/msm/Makefile
+++ b/drivers/video/msm/Makefile
@@ -71,6 +71,7 @@
obj-$(CONFIG_FB_MSM_MIPI_DSI_TOSHIBA) += mipi_toshiba.o
obj-$(CONFIG_FB_MSM_MIPI_DSI_NOVATEK) += mipi_novatek.o
obj-$(CONFIG_FB_MSM_MIPI_DSI_RENESAS) += mipi_renesas.o
+obj-$(CONFIG_FB_MSM_MIPI_DSI_TRULY) += mipi_truly.o
obj-$(CONFIG_FB_MSM_MIPI_DSI_SIMULATOR) += mipi_simulator.o
# MIPI Bridge
@@ -107,14 +108,23 @@
obj-$(CONFIG_FB_MSM_MDDI_QUICKVX) += mddi_quickvx.o
endif
+ifeq ($(CONFIG_FB_MSM_MIPI_PANEL_DETECT),y)
+obj-y += mipi_toshiba_video_wvga_pt.o mipi_toshiba_video_wsvga_pt.o
+obj-y += mipi_novatek_video_qhd_pt.o mipi_novatek_cmd_qhd_pt.o
+obj-y += mipi_renesas_video_fwvga_pt.o mipi_renesas_cmd_fwvga_pt.o
+obj-y += mipi_chimei_wxga_pt.o
+obj-y += mipi_truly_video_wvga_pt.o
+else
obj-$(CONFIG_FB_MSM_MIPI_TOSHIBA_VIDEO_WVGA_PT) += mipi_toshiba_video_wvga_pt.o
obj-$(CONFIG_FB_MSM_MIPI_TOSHIBA_VIDEO_WSVGA_PT) += mipi_toshiba_video_wsvga_pt.o
obj-$(CONFIG_FB_MSM_MIPI_NOVATEK_VIDEO_QHD_PT) += mipi_novatek_video_qhd_pt.o
obj-$(CONFIG_FB_MSM_MIPI_NOVATEK_CMD_QHD_PT) += mipi_novatek_cmd_qhd_pt.o
obj-$(CONFIG_FB_MSM_MIPI_RENESAS_VIDEO_FWVGA_PT) += mipi_renesas_video_fwvga_pt.o
obj-$(CONFIG_FB_MSM_MIPI_RENESAS_CMD_FWVGA_PT) += mipi_renesas_cmd_fwvga_pt.o
+obj-$(CONFIG_FB_MSM_MIPI_TRULY_VIDEO_WVGA_PT) += mipi_truly_video_wvga_pt.o
obj-$(CONFIG_FB_MSM_MIPI_SIMULATOR_VIDEO) += mipi_simulator_video.o
obj-$(CONFIG_FB_MSM_MIPI_CHIMEI_WXGA) += mipi_chimei_wxga_pt.o
+endif
obj-$(CONFIG_FB_MSM_LCDC_PANEL) += lcdc_panel.o
obj-$(CONFIG_FB_MSM_LCDC_PRISM_WVGA) += lcdc_prism.o
diff --git a/drivers/video/msm/external_common.c b/drivers/video/msm/external_common.c
index a499a62..1d87de6 100644
--- a/drivers/video/msm/external_common.c
+++ b/drivers/video/msm/external_common.c
@@ -18,7 +18,9 @@
/* #define DEBUG */
#define DEV_DBG_PREFIX "EXT_COMMON: "
+/* #define CEC_COMPLIANCE_TESTING */
#include "msm_fb.h"
+#include "hdmi_msm.h"
#include "external_common.h"
struct external_common_state_type *external_common_state;
@@ -26,6 +28,7 @@
DEFINE_MUTEX(external_common_state_hpd_mutex);
EXPORT_SYMBOL(external_common_state_hpd_mutex);
+
static int atoi(const char *name)
{
int val = 0;
@@ -307,6 +310,132 @@
return ret;
}
+#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
+/*
+ * This interface for CEC feature is defined to suit
+ * the current requirements. However, the actual functionality is
+ * added to accommodate different interfaces
+ */
+static ssize_t hdmi_msm_rda_cec(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ /* 0x028C CEC_CTRL */
+ ssize_t ret = snprintf(buf, PAGE_SIZE, "%d\n",
+ (HDMI_INP(0x028C) & BIT(0)));
+ return ret;
+}
+
+static ssize_t hdmi_msm_wta_cec(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ ssize_t ret = strnlen(buf, PAGE_SIZE);
+ int cec = atoi(buf);
+
+ if (cec != 0) {
+ mutex_lock(&hdmi_msm_state_mutex);
+ hdmi_msm_state->cec_enabled = true;
+ hdmi_msm_state->cec_logical_addr = 4;
+ mutex_unlock(&hdmi_msm_state_mutex);
+ hdmi_msm_cec_init();
+ hdmi_msm_cec_write_logical_addr(
+ hdmi_msm_state->cec_logical_addr);
+ DEV_DBG("CEC enabled\n");
+ } else {
+ mutex_lock(&hdmi_msm_state_mutex);
+ hdmi_msm_state->cec_enabled = false;
+ hdmi_msm_state->cec_logical_addr = 15;
+ mutex_unlock(&hdmi_msm_state_mutex);
+ hdmi_msm_cec_write_logical_addr(
+ hdmi_msm_state->cec_logical_addr);
+ /* 0x028C CEC_CTRL */
+ HDMI_OUTP(0x028C, 0);
+ DEV_DBG("CEC disabled\n");
+ }
+ return ret;
+}
+
+static ssize_t hdmi_msm_rda_cec_logical_addr(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ ssize_t ret;
+
+ mutex_lock(&hdmi_msm_state_mutex);
+ ret = snprintf(buf, PAGE_SIZE, "%d\n",
+ hdmi_msm_state->cec_logical_addr);
+ mutex_unlock(&hdmi_msm_state_mutex);
+ return ret;
+}
+
+static ssize_t hdmi_msm_wta_cec_logical_addr(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+
+#ifdef CEC_COMPLIANCE_TESTING
+ /*
+ * Only for testing
+ */
+ hdmi_msm_cec_one_touch_play();
+ return 0;
+#else
+ ssize_t ret = strnlen(buf, PAGE_SIZE);
+ int logical_addr = atoi(buf);
+
+ if (logical_addr < 0 || logical_addr > 15)
+ return -EINVAL;
+
+ mutex_lock(&hdmi_msm_state_mutex);
+ hdmi_msm_state->cec_logical_addr = logical_addr;
+ mutex_unlock(&hdmi_msm_state_mutex);
+
+ hdmi_msm_cec_write_logical_addr(logical_addr);
+
+ return ret;
+#endif
+}
+
+static ssize_t hdmi_msm_rda_cec_frame(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ mutex_lock(&hdmi_msm_state_mutex);
+ if (hdmi_msm_state->cec_queue_rd == hdmi_msm_state->cec_queue_wr
+ && !hdmi_msm_state->cec_queue_full) {
+ mutex_unlock(&hdmi_msm_state_mutex);
+ DEV_ERR("CEC message queue is empty\n");
+ return -EBUSY;
+ }
+ memcpy(buf, hdmi_msm_state->cec_queue_rd++,
+ sizeof(struct hdmi_msm_cec_msg));
+ hdmi_msm_state->cec_queue_full = false;
+ if (hdmi_msm_state->cec_queue_rd == CEC_QUEUE_END)
+ hdmi_msm_state->cec_queue_rd = hdmi_msm_state->cec_queue_start;
+ mutex_unlock(&hdmi_msm_state_mutex);
+
+ return sizeof(struct hdmi_msm_cec_msg);
+}
+
+static ssize_t hdmi_msm_wta_cec_frame(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ int retry = ((struct hdmi_msm_cec_msg *) buf)->retransmit;
+
+ if (retry > 15)
+ retry = 15;
+ while (1) {
+ hdmi_msm_cec_msg_send((struct hdmi_msm_cec_msg *) buf);
+ if (hdmi_msm_state->cec_frame_wr_status
+ & CEC_STATUS_WR_ERROR && retry--)
+ msleep(360);
+ else
+ break;
+ }
+
+ if (hdmi_msm_state->cec_frame_wr_status & CEC_STATUS_WR_DONE)
+ return sizeof(struct hdmi_msm_cec_msg);
+ else
+ return -EINVAL;
+}
+#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT */
+
static ssize_t hdmi_common_rda_3d_present(struct device *dev,
struct device_attribute *attr, char *buf)
{
@@ -364,6 +493,23 @@
}
#endif
+#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
+static DEVICE_ATTR(cec, S_IRUGO | S_IWUSR,
+ hdmi_msm_rda_cec,
+ hdmi_msm_wta_cec);
+
+static DEVICE_ATTR(cec_logical_addr, S_IRUGO | S_IWUSR,
+ hdmi_msm_rda_cec_logical_addr,
+ hdmi_msm_wta_cec_logical_addr);
+
+static DEVICE_ATTR(cec_rd_frame, S_IRUGO,
+ hdmi_msm_rda_cec_frame, NULL);
+
+static DEVICE_ATTR(cec_wr_frame, S_IWUSR,
+ NULL, hdmi_msm_wta_cec_frame);
+#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT */
+
+
static ssize_t external_common_rda_video_mode(struct device *dev,
struct device_attribute *attr, char *buf)
{
@@ -456,6 +602,12 @@
#ifdef CONFIG_FB_MSM_HDMI_3D
&dev_attr_format_3d.attr,
#endif
+#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
+ &dev_attr_cec.attr,
+ &dev_attr_cec_logical_addr.attr,
+ &dev_attr_cec_rd_frame.attr,
+ &dev_attr_cec_wr_frame.attr,
+#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT */
NULL,
};
static struct attribute_group external_common_fs_attr_group = {
diff --git a/drivers/video/msm/external_common.h b/drivers/video/msm/external_common.h
index 30a8f48..f629d0f 100644
--- a/drivers/video/msm/external_common.h
+++ b/drivers/video/msm/external_common.h
@@ -225,6 +225,7 @@
/* The external interface driver needs to initialize the common state. */
extern struct external_common_state_type *external_common_state;
extern struct mutex external_common_state_hpd_mutex;
+extern struct mutex hdmi_msm_state_mutex;
#ifdef CONFIG_FB_MSM_HDMI_COMMON
#define VFRMT_NOT_SUPPORTED(VFRMT) \
diff --git a/drivers/video/msm/hdmi_msm.c b/drivers/video/msm/hdmi_msm.c
index 7eca334..63c2147 100644
--- a/drivers/video/msm/hdmi_msm.c
+++ b/drivers/video/msm/hdmi_msm.c
@@ -15,6 +15,9 @@
#define DEV_DBG_PREFIX "HDMI: "
/* #define REG_DUMP */
+#define CEC_MSG_PRINT
+/* #define CEC_COMPLIANCE_TESTING */
+
#include <linux/types.h>
#include <linux/bitops.h>
#include <linux/clk.h>
@@ -49,7 +52,8 @@
struct workqueue_struct *hdmi_work_queue;
struct hdmi_msm_state_type *hdmi_msm_state;
-static DEFINE_MUTEX(hdmi_msm_state_mutex);
+DEFINE_MUTEX(hdmi_msm_state_mutex);
+EXPORT_SYMBOL(hdmi_msm_state_mutex);
static DEFINE_MUTEX(hdcp_auth_state_mutex);
#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_HDCP_SUPPORT
@@ -58,6 +62,478 @@
static inline void hdmi_msm_hdcp_enable(void) {}
#endif
+static void hdmi_msm_turn_on(void);
+static int hdmi_msm_audio_off(void);
+static int hdmi_msm_read_edid(void);
+static void hdmi_msm_hpd_off(void);
+
+#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
+
+#define HDMI_MSM_CEC_REFTIMER_REFTIMER_ENABLE BIT(16)
+#define HDMI_MSM_CEC_REFTIMER_REFTIMER(___t) (((___t)&0xFFFF) << 0)
+
+#define HDMI_MSM_CEC_TIME_SIGNAL_FREE_TIME(___t) (((___t)&0x1FF) << 7)
+#define HDMI_MSM_CEC_TIME_ENABLE BIT(0)
+
+#define HDMI_MSM_CEC_ADDR_LOGICAL_ADDR(___la) (((___la)&0xFF) << 0)
+
+#define HDMI_MSM_CEC_CTRL_LINE_OE BIT(9)
+#define HDMI_MSM_CEC_CTRL_FRAME_SIZE(___sz) (((___sz)&0x1F) << 4)
+#define HDMI_MSM_CEC_CTRL_SOFT_RESET BIT(2)
+#define HDMI_MSM_CEC_CTRL_SEND_TRIG BIT(1)
+#define HDMI_MSM_CEC_CTRL_ENABLE BIT(0)
+
+#define HDMI_MSM_CEC_INT_FRAME_RD_DONE_MASK BIT(7)
+#define HDMI_MSM_CEC_INT_FRAME_RD_DONE_ACK BIT(6)
+#define HDMI_MSM_CEC_INT_FRAME_RD_DONE_INT BIT(6)
+#define HDMI_MSM_CEC_INT_MONITOR_MASK BIT(5)
+#define HDMI_MSM_CEC_INT_MONITOR_ACK BIT(4)
+#define HDMI_MSM_CEC_INT_MONITOR_INT BIT(4)
+#define HDMI_MSM_CEC_INT_FRAME_ERROR_MASK BIT(3)
+#define HDMI_MSM_CEC_INT_FRAME_ERROR_ACK BIT(2)
+#define HDMI_MSM_CEC_INT_FRAME_ERROR_INT BIT(2)
+#define HDMI_MSM_CEC_INT_FRAME_WR_DONE_MASK BIT(1)
+#define HDMI_MSM_CEC_INT_FRAME_WR_DONE_ACK BIT(0)
+#define HDMI_MSM_CEC_INT_FRAME_WR_DONE_INT BIT(0)
+
+#define HDMI_MSM_CEC_FRAME_WR_SUCCESS(___st) (((___st)&0xF) ==\
+ (HDMI_MSM_CEC_INT_FRAME_WR_DONE_INT &&\
+ HDMI_MSM_CEC_INT_FRAME_WR_DONE_MASK &&\
+ (HDMI_MSM_CEC_INT_FRAME_ERROR_MASK &&\
+ !(HDMI_MSM_CEC_INT_FRAME_ERROR_INT))))
+
+#define HDMI_MSM_CEC_RETRANSMIT_NUM(___num) (((___num)&0xF) << 4)
+#define HDMI_MSM_CEC_RETRANSMIT_ENABLE BIT(0)
+
+#define HDMI_MSM_CEC_WR_DATA_DATA(___d) (((___d)&0xFF) << 8)
+
+
+void hdmi_msm_cec_init(void)
+{
+ /* 0x02A8 CEC_REFTIMER */
+ HDMI_OUTP(0x02A8,
+ HDMI_MSM_CEC_REFTIMER_REFTIMER_ENABLE
+ | HDMI_MSM_CEC_REFTIMER_REFTIMER(27 * 50)
+ );
+
+ /* 0x02A4 CEC_TIME */
+ HDMI_OUTP(0x02A4,
+ HDMI_MSM_CEC_TIME_SIGNAL_FREE_TIME(350)
+ | HDMI_MSM_CEC_TIME_ENABLE
+ );
+
+ /*
+ * 0x02A0 CEC_ADDR
+ * Starting with a default address of 4
+ */
+ HDMI_OUTP(0x02A0, HDMI_MSM_CEC_ADDR_LOGICAL_ADDR(4));
+
+ /* 0x028C CEC_CTRL */
+ HDMI_OUTP(0x028C, HDMI_MSM_CEC_CTRL_ENABLE);
+
+ /* 0x029C CEC_INT */
+ /* Enable CEC interrupts */
+ HDMI_OUTP(0x029C, \
+ HDMI_MSM_CEC_INT_FRAME_WR_DONE_MASK \
+ | HDMI_MSM_CEC_INT_FRAME_ERROR_MASK \
+ | HDMI_MSM_CEC_INT_MONITOR_MASK \
+ | HDMI_MSM_CEC_INT_FRAME_RD_DONE_MASK);
+
+ HDMI_OUTP(0x02B0, 0x7FF << 4 | 1);
+
+ /*
+ * Slight adjustment to logic 1 low periods on read,
+ * CEC Test 8.2-3 was failing, 8 for the
+ * BIT_1_ERR_RANGE_HI = 8 => 750us, the test used 775us,
+ * so increased this to 9 which => 800us.
+ */
+ HDMI_OUTP(0x02E0, 0x889788);
+
+ /*
+ * Slight adjustment to logic 0 low period on write
+ */
+ HDMI_OUTP(0x02DC, 0x8888A888);
+
+ /*
+ * Enable Signal Free Time counter and set to 7 bit periods
+ */
+ HDMI_OUTP(0x02A4, 0x1 | (7 * 0x30) << 7);
+
+}
+
+void hdmi_msm_cec_write_logical_addr(int addr)
+{
+ /* 0x02A0 CEC_ADDR
+ * LOGICAL_ADDR 7:0 NUM
+ */
+ HDMI_OUTP(0x02A0, addr & 0xFF);
+}
+
+void hdmi_msm_dump_cec_msg(struct hdmi_msm_cec_msg *msg)
+{
+#ifdef CEC_MSG_PRINT
+ int i;
+ DEV_DBG("sender_id : %d", msg->sender_id);
+ DEV_DBG("recvr_id : %d", msg->recvr_id);
+ if (msg->frame_size < 2) {
+ DEV_DBG("polling message");
+ return;
+ }
+ DEV_DBG("opcode : %02x", msg->opcode);
+ for (i = 0; i < msg->frame_size - 2; i++)
+ DEV_DBG("operand(%2d) : %02x", i + 1, msg->operand[i]);
+#endif /* CEC_MSG_PRINT */
+}
+
+void hdmi_msm_cec_msg_send(struct hdmi_msm_cec_msg *msg)
+{
+ int i;
+ uint32 timeout_count = 1;
+ int retry = 10;
+
+ boolean frameType = (msg->recvr_id == 15 ? BIT(0) : 0);
+
+ INIT_COMPLETION(hdmi_msm_state->cec_frame_wr_done);
+ hdmi_msm_state->cec_frame_wr_status = 0;
+
+ /* 0x0294 HDMI_MSM_CEC_RETRANSMIT */
+ HDMI_OUTP(0x0294,
+ HDMI_MSM_CEC_RETRANSMIT_NUM(msg->retransmit)
+ | (msg->retransmit > 0) ? HDMI_MSM_CEC_RETRANSMIT_ENABLE : 0);
+
+ /* 0x028C CEC_CTRL */
+ HDMI_OUTP(0x028C, 0x1 | msg->frame_size << 4);
+
+ /* 0x0290 CEC_WR_DATA */
+
+ /* header block */
+ HDMI_OUTP(0x0290,
+ HDMI_MSM_CEC_WR_DATA_DATA(msg->sender_id << 4 | msg->recvr_id)
+ | frameType);
+
+ /* data block 0 : opcode */
+ HDMI_OUTP(0x0290,
+ HDMI_MSM_CEC_WR_DATA_DATA(msg->frame_size < 2 ? 0 : msg->opcode)
+ | frameType);
+
+ /* data block 1-14 : operand 0-13 */
+ for (i = 0; i < msg->frame_size - 1; i++)
+ HDMI_OUTP(0x0290,
+ HDMI_MSM_CEC_WR_DATA_DATA(msg->operand[i])
+ | (msg->recvr_id == 15 ? BIT(0) : 0));
+
+ for (; i < 14; i++)
+ HDMI_OUTP(0x0290,
+ HDMI_MSM_CEC_WR_DATA_DATA(0)
+ | (msg->recvr_id == 15 ? BIT(0) : 0));
+
+ while ((HDMI_INP(0x0298) & 1) && retry--) {
+ DEV_DBG("CEC line is busy(%d)\n", retry);
+ schedule();
+ }
+
+ /* 0x028C CEC_CTRL */
+ HDMI_OUTP(0x028C,
+ HDMI_MSM_CEC_CTRL_LINE_OE
+ | HDMI_MSM_CEC_CTRL_FRAME_SIZE(msg->frame_size)
+ | HDMI_MSM_CEC_CTRL_SEND_TRIG
+ | HDMI_MSM_CEC_CTRL_ENABLE);
+
+ timeout_count = wait_for_completion_interruptible_timeout(
+ &hdmi_msm_state->cec_frame_wr_done, HZ);
+
+ if (!timeout_count) {
+ hdmi_msm_state->cec_frame_wr_status |= CEC_STATUS_WR_TMOUT;
+ DEV_ERR("%s: timedout", __func__);
+ hdmi_msm_dump_cec_msg(msg);
+ } else {
+ DEV_DBG("CEC write frame done (frame len=%d)",
+ msg->frame_size);
+ hdmi_msm_dump_cec_msg(msg);
+ }
+}
+
+void hdmi_msm_cec_msg_recv(void)
+{
+ uint32 data;
+ int i;
+#ifdef CEC_COMPLIANCE_TESTING
+ struct hdmi_msm_cec_msg temp_msg;
+#endif
+ mutex_lock(&hdmi_msm_state_mutex);
+ if (hdmi_msm_state->cec_queue_wr == hdmi_msm_state->cec_queue_rd
+ && hdmi_msm_state->cec_queue_full) {
+ mutex_unlock(&hdmi_msm_state_mutex);
+ DEV_ERR("CEC message queue is overflowing\n");
+#ifdef CEC_COMPLIANCE_TESTING
+ /*
+ * Without CEC daemon:
+ * Compliance tests fail once the queue gets filled up.
+ * so reset the pointers to the start of the queue.
+ */
+ hdmi_msm_state->cec_queue_wr = hdmi_msm_state->cec_queue_start;
+ hdmi_msm_state->cec_queue_rd = hdmi_msm_state->cec_queue_start;
+ hdmi_msm_state->cec_queue_full = false;
+#else
+ return;
+#endif
+ }
+ if (hdmi_msm_state->cec_queue_wr == NULL) {
+ DEV_ERR("%s: wp is NULL\n", __func__);
+ return;
+ }
+ mutex_unlock(&hdmi_msm_state_mutex);
+
+ /* 0x02AC CEC_RD_DATA */
+ data = HDMI_INP(0x02AC);
+
+ hdmi_msm_state->cec_queue_wr->sender_id = (data & 0xF0) >> 4;
+ hdmi_msm_state->cec_queue_wr->recvr_id = (data & 0x0F);
+ hdmi_msm_state->cec_queue_wr->frame_size = (data & 0x1F00) >> 8;
+ DEV_DBG("Recvd init=[%u] dest=[%u] size=[%u]\n",
+ hdmi_msm_state->cec_queue_wr->sender_id,
+ hdmi_msm_state->cec_queue_wr->recvr_id,
+ hdmi_msm_state->cec_queue_wr->frame_size);
+
+ if (hdmi_msm_state->cec_queue_wr->frame_size < 1) {
+ DEV_ERR("%s: invalid message (frame length = %d)",
+ __func__, hdmi_msm_state->cec_queue_wr->frame_size);
+ return;
+ } else if (hdmi_msm_state->cec_queue_wr->frame_size == 1) {
+ DEV_DBG("%s: polling message (dest[%x] <- init[%x])",
+ __func__,
+ hdmi_msm_state->cec_queue_wr->recvr_id,
+ hdmi_msm_state->cec_queue_wr->sender_id);
+ return;
+ }
+
+ /* data block 0 : opcode */
+ data = HDMI_INP(0x02AC);
+ hdmi_msm_state->cec_queue_wr->opcode = data & 0xFF;
+
+ /* data block 1-14 : operand 0-13 */
+ for (i = 0; i < hdmi_msm_state->cec_queue_wr->frame_size - 2; i++) {
+ data = HDMI_INP(0x02AC);
+ hdmi_msm_state->cec_queue_wr->operand[i] = data & 0xFF;
+ }
+
+ for (; i < 14; i++)
+ hdmi_msm_state->cec_queue_wr->operand[i] = 0;
+
+ DEV_DBG("CEC read frame done\n");
+ DEV_DBG("=======================================\n");
+ hdmi_msm_dump_cec_msg(hdmi_msm_state->cec_queue_wr);
+ DEV_DBG("=======================================\n");
+
+#ifdef CEC_COMPLIANCE_TESTING
+ switch (hdmi_msm_state->cec_queue_wr->opcode) {
+ case 0x64:
+ /* Set OSD String */
+ DEV_INFO("Recvd OSD Str=[%x]\n",\
+ hdmi_msm_state->cec_queue_wr->operand[3]);
+ break;
+ case 0x83:
+ /* Give Phy Addr */
+ DEV_INFO("Recvd a Give Phy Addr cmd\n");
+ memset(&temp_msg, 0x00, sizeof(struct hdmi_msm_cec_msg));
+ /* Setup a frame for sending out phy addr */
+ temp_msg.sender_id = 0x4;
+
+ /* Broadcast */
+ temp_msg.recvr_id = 0xf;
+ temp_msg.opcode = 0x84;
+ i = 0;
+ temp_msg.operand[i++] = 0x10;
+ temp_msg.operand[i++] = 0x00;
+ temp_msg.operand[i++] = 0x04;
+ temp_msg.frame_size = i + 2;
+ hdmi_msm_cec_msg_send(&temp_msg);
+ break;
+ case 0xFF:
+ /* Abort */
+ DEV_INFO("Recvd an abort cmd 0xFF\n");
+ memset(&temp_msg, 0x00, sizeof(struct hdmi_msm_cec_msg));
+ temp_msg.sender_id = 0x4;
+ temp_msg.recvr_id = hdmi_msm_state->cec_queue_wr->sender_id;
+ i = 0;
+
+ /*feature abort */
+ temp_msg.opcode = 0x00;
+ temp_msg.operand[i++] =
+ hdmi_msm_state->cec_queue_wr->opcode;
+
+ /*reason for abort = "Refused" */
+ temp_msg.operand[i++] = 0x04;
+ temp_msg.frame_size = i + 2;
+ hdmi_msm_dump_cec_msg(&temp_msg);
+ hdmi_msm_cec_msg_send(&temp_msg);
+ break;
+ case 0x046:
+ /* Give OSD name */
+ DEV_INFO("Recvd cmd 0x046\n");
+ memset(&temp_msg, 0x00, sizeof(struct hdmi_msm_cec_msg));
+ temp_msg.sender_id = 0x4;
+ temp_msg.recvr_id = hdmi_msm_state->cec_queue_wr->sender_id;
+ i = 0;
+
+ /* OSD Name */
+ temp_msg.opcode = 0x47;
+
+ /* Display control byte */
+ temp_msg.operand[i++] = 0x00;
+ temp_msg.operand[i++] = 'H';
+ temp_msg.operand[i++] = 'e';
+ temp_msg.operand[i++] = 'l';
+ temp_msg.operand[i++] = 'l';
+ temp_msg.operand[i++] = 'o';
+ temp_msg.operand[i++] = ' ';
+ temp_msg.operand[i++] = 'W';
+ temp_msg.operand[i++] = 'o';
+ temp_msg.operand[i++] = 'r';
+ temp_msg.operand[i++] = 'l';
+ temp_msg.operand[i++] = 'd';
+ temp_msg.frame_size = i + 2;
+ hdmi_msm_cec_msg_send(&temp_msg);
+ break;
+ case 0x08F:
+ /* Give Device Power status */
+ DEV_INFO("Recvd a Power status message\n");
+ memset(&temp_msg, 0x00, sizeof(struct hdmi_msm_cec_msg));
+ temp_msg.sender_id = 0x4;
+ temp_msg.recvr_id = hdmi_msm_state->cec_queue_wr->sender_id;
+ i = 0;
+
+ /* OSD String */
+ temp_msg.opcode = 0x90;
+ temp_msg.operand[i++] = 'H';
+ temp_msg.operand[i++] = 'e';
+ temp_msg.operand[i++] = 'l';
+ temp_msg.operand[i++] = 'l';
+ temp_msg.operand[i++] = 'o';
+ temp_msg.operand[i++] = ' ';
+ temp_msg.operand[i++] = 'W';
+ temp_msg.operand[i++] = 'o';
+ temp_msg.operand[i++] = 'r';
+ temp_msg.operand[i++] = 'l';
+ temp_msg.operand[i++] = 'd';
+ temp_msg.frame_size = i + 2;
+ hdmi_msm_cec_msg_send(&temp_msg);
+ break;
+ case 0x080:
+ /* Routing Change cmd */
+ case 0x086:
+ /* Set Stream Path */
+ DEV_INFO("Recvd Set Stream\n");
+ memset(&temp_msg, 0x00, sizeof(struct hdmi_msm_cec_msg));
+ temp_msg.sender_id = 0x4;
+
+ /*Broadcast this message*/
+ temp_msg.recvr_id = 0xf;
+ i = 0;
+ temp_msg.opcode = 0x82; /* Active Source */
+ temp_msg.operand[i++] = 0x10;
+ temp_msg.operand[i++] = 0x00;
+ temp_msg.frame_size = i + 2;
+ hdmi_msm_cec_msg_send(&temp_msg);
+
+ /*
+ * sending <Image View On> message
+ */
+ memset(&temp_msg, 0x00, sizeof(struct hdmi_msm_cec_msg));
+ temp_msg.sender_id = 0x4;
+ temp_msg.recvr_id = hdmi_msm_state->cec_queue_wr->sender_id;
+ i = 0;
+ /* opcode for Image View On */
+ temp_msg.opcode = 0x04;
+ temp_msg.frame_size = i + 2;
+ hdmi_msm_cec_msg_send(&temp_msg);
+ break;
+ default:
+ DEV_INFO("Recvd an unknown cmd = [%u]\n",
+ hdmi_msm_state->cec_queue_wr->opcode);
+#ifdef __SEND_ABORT__
+ memset(&temp_msg, 0x00, sizeof(struct hdmi_msm_cec_msg));
+ temp_msg.sender_id = 0x4;
+ temp_msg.recvr_id = hdmi_msm_state->cec_queue_wr->sender_id;
+ i = 0;
+ /* opcode for feature abort */
+ temp_msg.opcode = 0x00;
+ temp_msg.operand[i++] =
+ hdmi_msm_state->cec_queue_wr->opcode;
+ /*reason for abort = "Unrecognized opcode" */
+ temp_msg.operand[i++] = 0x00;
+ temp_msg.frame_size = i + 2;
+ hdmi_msm_cec_msg_send(&temp_msg);
+ break;
+#else
+ memset(&temp_msg, 0x00, sizeof(struct hdmi_msm_cec_msg));
+ temp_msg.sender_id = 0x4;
+ temp_msg.recvr_id = hdmi_msm_state->cec_queue_wr->sender_id;
+ i = 0;
+ /* OSD String */
+ temp_msg.opcode = 0x64;
+ temp_msg.operand[i++] = 0x0;
+ temp_msg.operand[i++] = 'H';
+ temp_msg.operand[i++] = 'e';
+ temp_msg.operand[i++] = 'l';
+ temp_msg.operand[i++] = 'l';
+ temp_msg.operand[i++] = 'o';
+ temp_msg.operand[i++] = ' ';
+ temp_msg.operand[i++] = 'W';
+ temp_msg.operand[i++] = 'o';
+ temp_msg.operand[i++] = 'r';
+ temp_msg.operand[i++] = 'l';
+ temp_msg.operand[i++] = 'd';
+ temp_msg.frame_size = i + 2;
+ hdmi_msm_cec_msg_send(&temp_msg);
+ break;
+#endif /* __SEND_ABORT__ */
+ }
+
+#endif /* CEC_COMPLIANCE_TESTING */
+ mutex_lock(&hdmi_msm_state_mutex);
+ hdmi_msm_state->cec_queue_wr++;
+ if (hdmi_msm_state->cec_queue_wr == CEC_QUEUE_END)
+ hdmi_msm_state->cec_queue_wr = hdmi_msm_state->cec_queue_start;
+ if (hdmi_msm_state->cec_queue_wr == hdmi_msm_state->cec_queue_rd)
+ hdmi_msm_state->cec_queue_full = true;
+ mutex_unlock(&hdmi_msm_state_mutex);
+ DEV_DBG("Exiting %s()\n", __func__);
+}
+
+void hdmi_msm_cec_one_touch_play(void)
+{
+ struct hdmi_msm_cec_msg temp_msg;
+ uint32 i = 0;
+ memset(&temp_msg, 0x00, sizeof(struct hdmi_msm_cec_msg));
+ temp_msg.sender_id = 0x4;
+ /*
+ * Broadcast this message
+ */
+ temp_msg.recvr_id = 0xf;
+ i = 0;
+ /* Active Source */
+ temp_msg.opcode = 0x82;
+ temp_msg.operand[i++] = 0x10;
+ temp_msg.operand[i++] = 0x00;
+ /*temp_msg.operand[i++] = 0x04;*/
+ temp_msg.frame_size = i + 2;
+ hdmi_msm_cec_msg_send(&temp_msg);
+ /*
+ * sending <Image View On> message
+ */
+ memset(&temp_msg, 0x00, sizeof(struct hdmi_msm_cec_msg));
+ temp_msg.sender_id = 0x4;
+ temp_msg.recvr_id = hdmi_msm_state->cec_queue_wr->sender_id;
+ i = 0;
+ /* Image View On */
+ temp_msg.opcode = 0x04;
+ temp_msg.frame_size = i + 2;
+ hdmi_msm_cec_msg_send(&temp_msg);
+
+}
+#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT */
+
uint32 hdmi_msm_get_io_base(void)
{
return (uint32)MSM_HDMI_BASE;
@@ -397,6 +873,9 @@
{
uint32 hpd_int_status;
uint32 hpd_int_ctrl;
+#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
+ uint32 cec_intr_status;
+#endif
uint32 ddc_int_ctrl;
uint32 audio_int_val;
#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_HDCP_SUPPORT
@@ -601,8 +1080,55 @@
}
#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL_HDCP_SUPPORT */
+#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
+ /* Process CEC Interrupt */
+ /* HDMI_MSM_CEC_INT[0x029C] */
+ cec_intr_status = HDMI_INP_ND(0x029C);
+
+ DEV_DBG("cec interrupt status is [%u]\n", cec_intr_status);
+
+ if (HDMI_MSM_CEC_FRAME_WR_SUCCESS(cec_intr_status)) {
+ DEV_DBG("CEC_IRQ_FRAME_WR_DONE\n");
+ HDMI_OUTP(0x029C, cec_intr_status |
+ HDMI_MSM_CEC_INT_FRAME_WR_DONE_ACK);
+ mutex_lock(&hdmi_msm_state_mutex);
+ hdmi_msm_state->cec_frame_wr_status |= CEC_STATUS_WR_DONE;
+ mutex_unlock(&hdmi_msm_state_mutex);
+ complete(&hdmi_msm_state->cec_frame_wr_done);
+ return IRQ_HANDLED;
+ }
+ if ((cec_intr_status & (1 << 2)) && (cec_intr_status & (1 << 3))) {
+ DEV_DBG("CEC_IRQ_FRAME_ERROR\n");
+ /* Toggle CEC hardware FSM */
+ HDMI_OUTP(0x028C, 0x0);
+ HDMI_OUTP(0x028C, HDMI_MSM_CEC_CTRL_ENABLE);
+ HDMI_OUTP(0x029C, cec_intr_status);
+ mutex_lock(&hdmi_msm_state_mutex);
+ hdmi_msm_state->cec_frame_wr_status |= CEC_STATUS_WR_ERROR;
+ mutex_unlock(&hdmi_msm_state_mutex);
+ complete(&hdmi_msm_state->cec_frame_wr_done);
+ return IRQ_HANDLED;
+ }
+
+ if ((cec_intr_status & (1 << 4)) && (cec_intr_status & (1 << 5)))
+ DEV_DBG("CEC_IRQ_MONITOR\n");
+
+ if ((cec_intr_status & (1 << 6)) && (cec_intr_status & (1 << 7))) {
+ DEV_DBG("CEC_IRQ_FRAME_RD_DONE\n");
+ HDMI_OUTP(0x029C, cec_intr_status |
+ HDMI_MSM_CEC_INT_FRAME_RD_DONE_ACK);
+ hdmi_msm_cec_msg_recv();
+
+ /* Toggle CEC hardware FSM */
+ HDMI_OUTP(0x028C, 0x0);
+ HDMI_OUTP(0x028C, HDMI_MSM_CEC_CTRL_ENABLE);
+
+ return IRQ_HANDLED;
+ }
+#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT */
+
DEV_DBG("%s: HPD<Ctrl=%04x, State=%04x>, ddc_int_ctrl=%04x, "
- "aud_int=%04x, cec_int=%04x\n", __func__, hpd_int_ctrl,
+ "aud_int=%04x, cec_intr_status=%04x\n", __func__, hpd_int_ctrl,
hpd_int_status, ddc_int_ctrl, audio_int_val,
HDMI_INP_ND(0x029C));
@@ -3130,6 +3656,17 @@
hdmi_msm_state->reauth = FALSE ;
}
#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL_HDCP_SUPPORT */
+
+#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
+ /* re-initialize CEC if enabled */
+ mutex_lock(&hdmi_msm_state_mutex);
+ if (hdmi_msm_state->cec_enabled == true) {
+ hdmi_msm_cec_init();
+ hdmi_msm_cec_write_logical_addr(
+ hdmi_msm_state->cec_logical_addr);
+ }
+ mutex_unlock(&hdmi_msm_state_mutex);
+#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT */
DEV_INFO("HDMI Core: Initialized\n");
}
@@ -3187,6 +3724,7 @@
hdmi_msm_set_mode(FALSE);
HDMI_OUTP_ND(0x0308, 0x7F); /*0b01111111*/
hdmi_msm_state->hpd_initialized = FALSE;
+ hdmi_msm_state->pd->cec_power(0);
hdmi_msm_state->pd->enable_5v(0);
hdmi_msm_state->pd->core_power(0, 1);
hdmi_msm_clk(0);
@@ -3208,6 +3746,7 @@
hdmi_msm_clk(1);
hdmi_msm_state->pd->core_power(1, 1);
hdmi_msm_state->pd->enable_5v(1);
+ hdmi_msm_state->pd->cec_power(1);
hdmi_msm_dump_regs("HDMI-INIT: ");
hdmi_msm_set_mode(FALSE);
@@ -3455,6 +3994,12 @@
goto error;
}
+ if (!hdmi_msm_state->pd->cec_power) {
+ DEV_ERR("Init FAILED: cec_power function missing\n");
+ rc = -ENODEV;
+ goto error;
+ }
+
rc = request_threaded_irq(hdmi_msm_state->irq, NULL, &hdmi_msm_isr,
IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "hdmi_msm_isr", NULL);
if (rc) {
@@ -3686,6 +4231,21 @@
external_common_state->switch_3d = hdmi_msm_switch_3d;
#endif
+#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
+ hdmi_msm_state->cec_queue_start =
+ kzalloc(sizeof(struct hdmi_msm_cec_msg)*CEC_QUEUE_SIZE,
+ GFP_KERNEL);
+ if (!hdmi_msm_state->cec_queue_start) {
+ pr_err("hdmi_msm_init FAILED: CEC queue out of memory\n");
+ rc = -ENOMEM;
+ goto init_exit;
+ }
+
+ hdmi_msm_state->cec_queue_wr = hdmi_msm_state->cec_queue_start;
+ hdmi_msm_state->cec_queue_rd = hdmi_msm_state->cec_queue_start;
+ hdmi_msm_state->cec_queue_full = false;
+#endif
+
/*
* Create your work queue
* allocs and returns ptr
@@ -3710,6 +4270,10 @@
INIT_WORK(&hdmi_msm_state->hdcp_work, hdmi_msm_hdcp_work);
#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL_HDCP_SUPPORT */
+#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
+ init_completion(&hdmi_msm_state->cec_frame_wr_done);
+#endif
+
rc = platform_device_register(&this_device);
if (rc) {
pr_err("hdmi_msm_init FAILED: platform_device_register rc=%d\n",
diff --git a/drivers/video/msm/hdmi_msm.h b/drivers/video/msm/hdmi_msm.h
index 2f44b6d..6d19d157 100644
--- a/drivers/video/msm/hdmi_msm.h
+++ b/drivers/video/msm/hdmi_msm.h
@@ -33,7 +33,22 @@
#define HDMI_INP(offset) inpdw(MSM_HDMI_BASE+(offset))
#endif
+
+/*
+ * Ref. HDMI 1.4a
+ * Supplement-1 CEC Section 6, 7
+ */
+struct hdmi_msm_cec_msg {
+ uint8 sender_id;
+ uint8 recvr_id;
+ uint8 opcode;
+ uint8 operand[15];
+ uint8 frame_size;
+ uint8 retransmit;
+};
+
#define QFPROM_BASE ((uint32)hdmi_msm_state->qfprom_io)
+#define HDMI_BASE ((uint32)hdmi_msm_state->hdmi_io)
struct hdmi_msm_state_type {
boolean panel_power_on;
@@ -58,6 +73,23 @@
struct timer_list hdcp_timer;
#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL_HDCP_SUPPORT */
+#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
+ boolean cec_enabled;
+ int cec_logical_addr;
+ struct completion cec_frame_wr_done;
+#define CEC_STATUS_WR_ERROR 0x0001
+#define CEC_STATUS_WR_DONE 0x0002
+#define CEC_STATUS_WR_TMOUT 0x0004
+ uint32 cec_frame_wr_status;
+
+ struct hdmi_msm_cec_msg *cec_queue_start;
+ struct hdmi_msm_cec_msg *cec_queue_wr;
+ struct hdmi_msm_cec_msg *cec_queue_rd;
+ boolean cec_queue_full;
+#define CEC_QUEUE_SIZE 16
+#define CEC_QUEUE_END (hdmi_msm_state->cec_queue_start + CEC_QUEUE_SIZE)
+#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT */
+
int irq;
struct msm_hdmi_platform_data *pd;
struct clk *hdmi_app_clk;
@@ -84,4 +116,12 @@
void hdmi_msm_phy_status_poll(void);
#endif
+#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
+void hdmi_msm_cec_init(void);
+void hdmi_msm_cec_write_logical_addr(int addr);
+void hdmi_msm_cec_msg_recv(void);
+void hdmi_msm_cec_one_touch_play(void);
+void hdmi_msm_cec_msg_send(struct hdmi_msm_cec_msg *msg);
+#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT */
+
#endif /* __HDMI_MSM_H__ */
diff --git a/drivers/video/msm/mdp4.h b/drivers/video/msm/mdp4.h
index 0740f42..fd2f13e 100644
--- a/drivers/video/msm/mdp4.h
+++ b/drivers/video/msm/mdp4.h
@@ -143,7 +143,7 @@
};
/* 2 VG pipes can be shared by RGB and VIDEO */
-#define MDP4_MAX_PIPE (OVERLAY_PIPE_MAX + 2)
+#define MDP4_MAX_PIPE (OVERLAY_PIPE_MAX + 2)
#define OVERLAY_TYPE_RGB 0x01
#define OVERLAY_TYPE_VIDEO 0x02
@@ -343,6 +343,7 @@
ulong err_format;
};
+struct mdp4_overlay_pipe *mdp4_overlay_ndx2pipe(int ndx);
void mdp4_sw_reset(unsigned long bits);
void mdp4_display_intf_sel(int output, unsigned long intf);
void mdp4_overlay_cfg(int layer, int blt_mode, int refresh, int direct_out);
@@ -367,16 +368,9 @@
void mdp4_clear_lcdc(void);
void mdp4_mixer_blend_init(int mixer_num);
void mdp4_vg_qseed_init(int vg_num);
-void mdp4_vg_csc_mv_setup(int vp_num);
-void mdp4_vg_csc_pre_bv_setup(int vp_num);
-void mdp4_vg_csc_post_bv_setup(int vp_num);
-void mdp4_vg_csc_pre_lv_setup(int vp_num);
-void mdp4_vg_csc_post_lv_setup(int vp_num);
-void mdp4_mixer1_csc_mv_setup(void);
-void mdp4_mixer1_csc_pre_bv_setup(void);
-void mdp4_mixer1_csc_post_bv_setup(void);
-void mdp4_mixer1_csc_pre_lv_setup(void);
-void mdp4_mixer1_csc_post_lv_setup(void);
+void mdp4_vg_csc_setup(int vp_num);
+void mdp4_mixer1_csc_setup(void);
+void mdp4_vg_csc_update(struct mdp_csc *p);
irqreturn_t mdp4_isr(int irq, void *ptr);
void mdp4_overlay_format_to_pipe(uint32 format, struct mdp4_overlay_pipe *pipe);
uint32 mdp4_overlay_format(struct mdp4_overlay_pipe *pipe);
diff --git a/drivers/video/msm/mdp4_overlay.c b/drivers/video/msm/mdp4_overlay.c
index f8cadbb..1b2dec4 100644
--- a/drivers/video/msm/mdp4_overlay.c
+++ b/drivers/video/msm/mdp4_overlay.c
@@ -461,6 +461,7 @@
switch (pipe->src_format) {
case MDP_Y_CR_CB_H2V2:
+ case MDP_Y_CR_CB_GH2V2:
case MDP_Y_CB_CR_H2V2:
*luma_off = pipe->src_x;
*chroma_off = pipe->src_x/2;
@@ -521,6 +522,11 @@
dst_xy = ((pipe->dst_y << 16) | pipe->dst_x);
ptype = mdp4_overlay_format2type(pipe->src_format);
+ if (pipe->src_format == MDP_Y_CR_CB_GH2V2) {
+ frame_size = ((pipe->src_height << 16) |
+ ALIGN(pipe->src_width, 16));
+ src_size = ((pipe->src_h << 16) | ALIGN(pipe->src_w, 16));
+ }
format = mdp4_overlay_format(pipe);
pattern = mdp4_overlay_unpack_pattern(pipe);
@@ -618,6 +624,7 @@
case MDP_Y_CBCR_H2V2_TILE:
case MDP_Y_CRCB_H2V2_TILE:
case MDP_Y_CR_CB_H2V2:
+ case MDP_Y_CR_CB_GH2V2:
case MDP_Y_CB_CR_H2V2:
case MDP_Y_CRCB_H1V1:
case MDP_Y_CBCR_H1V1:
@@ -866,6 +873,7 @@
pipe->bpp = 2; /* 2 bpp */
break;
case MDP_Y_CR_CB_H2V2:
+ case MDP_Y_CR_CB_GH2V2:
case MDP_Y_CB_CR_H2V2:
pipe->frame_format = MDP4_FRAME_FORMAT_LINEAR;
pipe->fetch_plane = OVERLAY_PLANE_PLANAR;
@@ -961,6 +969,7 @@
b_num = 8;
break;
case MDP_Y_CR_CB_H2V2:
+ case MDP_Y_CR_CB_GH2V2:
case MDP_Y_CRCB_H2V2:
case MDP_Y_CRCB_H2V1:
case MDP_Y_CRCB_H1V1:
@@ -2361,18 +2370,35 @@
pipe->srcp2_addr = start + img->offset;
*pp_src_plane2_file = p_src_plane2_file;
} else {
- addr += (pipe->src_width * pipe->src_height);
- pipe->srcp1_addr = addr;
- addr += ((pipe->src_width / 2) *
+ if (pipe->src_format == MDP_Y_CR_CB_GH2V2) {
+ addr += (ALIGN(pipe->src_width, 16) *
+ pipe->src_height);
+ pipe->srcp1_addr = addr;
+ addr += ((ALIGN((pipe->src_width / 2), 16)) *
(pipe->src_height / 2));
- pipe->srcp2_addr = addr;
+ pipe->srcp2_addr = addr;
+ } else {
+ addr += (pipe->src_width * pipe->src_height);
+ pipe->srcp1_addr = addr;
+ addr += ((pipe->src_width / 2) *
+ (pipe->src_height / 2));
+ pipe->srcp2_addr = addr;
+ }
}
/* mdp planar format expects Cb in srcp1 and Cr in p2 */
- if (pipe->src_format == MDP_Y_CR_CB_H2V2)
+ if ((pipe->src_format == MDP_Y_CR_CB_H2V2) ||
+ (pipe->src_format == MDP_Y_CR_CB_GH2V2))
swap(pipe->srcp1_addr, pipe->srcp2_addr);
- pipe->srcp0_ystride = pipe->src_width;
- pipe->srcp1_ystride = pipe->src_width / 2;
- pipe->srcp2_ystride = pipe->src_width / 2;
+
+ if (pipe->src_format == MDP_Y_CR_CB_GH2V2) {
+ pipe->srcp0_ystride = ALIGN(pipe->src_width, 16);
+ pipe->srcp1_ystride = ALIGN(pipe->src_width / 2, 16);
+ pipe->srcp2_ystride = ALIGN(pipe->src_width / 2, 16);
+ } else {
+ pipe->srcp0_ystride = pipe->src_width;
+ pipe->srcp1_ystride = pipe->src_width / 2;
+ pipe->srcp2_ystride = pipe->src_width / 2;
+ }
}
if (pipe->pipe_num >= OVERLAY_PIPE_VG1)
diff --git a/drivers/video/msm/mdp4_util.c b/drivers/video/msm/mdp4_util.c
index 00cffda..99607e7 100644
--- a/drivers/video/msm/mdp4_util.c
+++ b/drivers/video/msm/mdp4_util.c
@@ -265,24 +265,9 @@
mdp4_vg_qseed_init(0);
mdp4_vg_qseed_init(1);
- /* yuv2rgb */
- mdp4_vg_csc_mv_setup(0);
- mdp4_vg_csc_mv_setup(1);
- mdp4_vg_csc_pre_bv_setup(0);
- mdp4_vg_csc_pre_bv_setup(1);
- mdp4_vg_csc_post_bv_setup(0);
- mdp4_vg_csc_post_bv_setup(1);
- mdp4_vg_csc_pre_lv_setup(0);
- mdp4_vg_csc_pre_lv_setup(1);
- mdp4_vg_csc_post_lv_setup(0);
- mdp4_vg_csc_post_lv_setup(1);
-
- /* rgb2yuv */
- mdp4_mixer1_csc_mv_setup();
- mdp4_mixer1_csc_pre_bv_setup();
- mdp4_mixer1_csc_post_bv_setup();
- mdp4_mixer1_csc_pre_lv_setup();
- mdp4_mixer1_csc_post_lv_setup();
+ mdp4_vg_csc_setup(0);
+ mdp4_vg_csc_setup(1);
+ mdp4_mixer1_csc_setup();
if (mdp_rev <= MDP_REV_41) {
mdp4_mixer_gc_lut_setup(0);
@@ -1221,17 +1206,54 @@
}
-static uint32 csc_matrix_tab[9] = {
- 0x0254, 0x0000, 0x0331,
- 0x0254, 0xff37, 0xfe60,
- 0x0254, 0x0409, 0x0000
+struct mdp4_csc_matrix {
+uint32 csc_mv[9];
+uint32 csc_pre_bv[3];
+uint32 csc_post_bv[3];
+uint32 csc_pre_lv[6];
+uint32 csc_post_lv[6];
+} csc_matrix[2] = {
+ {
+ {
+ 0x0254, 0x0000, 0x0331,
+ 0x0254, 0xff37, 0xfe60,
+ 0x0254, 0x0409, 0x0000,
+ },
+ {
+ 0xfff0, 0xff80, 0xff80,
+ },
+ {
+ 0, 0, 0,
+ },
+ {
+ 0, 0xff, 0, 0xff, 0, 0xff,
+ },
+ {
+ 0, 0xff, 0, 0xff, 0, 0xff,
+ },
+ },
+ {
+ {
+ 0x0254, 0x0000, 0x0331,
+ 0x0254, 0xff37, 0xfe60,
+ 0x0254, 0x0409, 0x0000,
+ },
+ {
+ 0xfff0, 0xff80, 0xff80,
+ },
+ {
+ 0, 0, 0,
+ },
+ {
+ 0, 0xff, 0, 0xff, 0, 0xff,
+ },
+ {
+ 0, 0xff, 0, 0xff, 0, 0xff,
+ },
+ },
};
-static uint32 csc_pre_bv_tab[3] = {0xfff0, 0xff80, 0xff80 };
-static uint32 csc_post_bv_tab[3] = {0, 0, 0 };
-static uint32 csc_pre_lv_tab[6] = {0, 0xff, 0, 0xff, 0, 0xff };
-static uint32 csc_post_lv_tab[6] = {0, 0xff, 0, 0xff, 0, 0xff };
#define MDP4_CSC_MV_OFF 0x4400
#define MDP4_CSC_PRE_BV_OFF 0x4500
@@ -1250,7 +1272,7 @@
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
for (i = 0; i < 9; i++) {
- outpdw(off, csc_matrix_tab[i]);
+ outpdw(off, csc_matrix[vp_num].csc_mv[i]);
off++;
}
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
@@ -1267,7 +1289,7 @@
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
for (i = 0; i < 3; i++) {
- outpdw(off, csc_pre_bv_tab[i]);
+ outpdw(off, csc_matrix[vp_num].csc_pre_bv[i]);
off++;
}
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
@@ -1284,7 +1306,7 @@
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
for (i = 0; i < 3; i++) {
- outpdw(off, csc_post_bv_tab[i]);
+ outpdw(off, csc_matrix[vp_num].csc_post_bv[i]);
off++;
}
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
@@ -1301,7 +1323,7 @@
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
for (i = 0; i < 6; i++) {
- outpdw(off, csc_pre_lv_tab[i]);
+ outpdw(off, csc_matrix[vp_num].csc_pre_lv[i]);
off++;
}
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
@@ -1318,12 +1340,47 @@
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
for (i = 0; i < 6; i++) {
- outpdw(off, csc_post_lv_tab[i]);
+ outpdw(off, csc_matrix[vp_num].csc_post_lv[i]);
off++;
}
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
}
+void mdp4_vg_csc_setup(int vp_num)
+{
+ /* yuv2rgb */
+ mdp4_vg_csc_mv_setup(vp_num);
+ mdp4_vg_csc_pre_bv_setup(vp_num);
+ mdp4_vg_csc_post_bv_setup(vp_num);
+ mdp4_vg_csc_pre_lv_setup(vp_num);
+ mdp4_vg_csc_post_lv_setup(vp_num);
+}
+void mdp4_vg_csc_update(struct mdp_csc *p)
+{
+ struct mdp4_overlay_pipe *pipe;
+ int vp_num;
+
+ pipe = mdp4_overlay_ndx2pipe(p->id);
+ if (pipe == NULL) {
+ pr_err("%s: p->id = %d Error\n", __func__, p->id);
+ return;
+ }
+
+ vp_num = pipe->pipe_num - OVERLAY_PIPE_VG1;
+
+ if (vp_num == 0 || vp_num == 1) {
+ memcpy(csc_matrix[vp_num].csc_mv, p->csc_mv, sizeof(p->csc_mv));
+ memcpy(csc_matrix[vp_num].csc_pre_bv, p->csc_pre_bv,
+ sizeof(p->csc_pre_bv));
+ memcpy(csc_matrix[vp_num].csc_post_bv, p->csc_post_bv,
+ sizeof(p->csc_post_bv));
+ memcpy(csc_matrix[vp_num].csc_pre_lv, p->csc_pre_lv,
+ sizeof(p->csc_pre_lv));
+ memcpy(csc_matrix[vp_num].csc_post_lv, p->csc_post_lv,
+ sizeof(p->csc_post_lv));
+ mdp4_vg_csc_setup(vp_num);
+ }
+}
static uint32 csc_rgb2yuv_matrix_tab[9] = {
0x0083, 0x0102, 0x0032,
0x1fb5, 0x1f6c, 0x00e1,
@@ -1419,6 +1476,15 @@
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
}
+void mdp4_mixer1_csc_setup(void)
+{
+ /* rgb2yuv */
+ mdp4_mixer1_csc_mv_setup();
+ mdp4_mixer1_csc_pre_bv_setup();
+ mdp4_mixer1_csc_post_bv_setup();
+ mdp4_mixer1_csc_pre_lv_setup();
+ mdp4_mixer1_csc_post_lv_setup();
+}
char gc_lut[] = {
0x0, 0x1, 0x2, 0x2, 0x3, 0x4, 0x5, 0x6,
diff --git a/drivers/video/msm/mipi_novatek.c b/drivers/video/msm/mipi_novatek.c
index 1ff950d..cb4bd1b 100644
--- a/drivers/video/msm/mipi_novatek.c
+++ b/drivers/video/msm/mipi_novatek.c
@@ -548,7 +548,7 @@
}
static struct device_attribute mipi_dsi_3d_barrier_attributes[] = {
- __ATTR(enable_3d_barrier, 0666, mipi_dsi_3d_barrier_read,
+ __ATTR(enable_3d_barrier, 0664, mipi_dsi_3d_barrier_read,
mipi_dsi_3d_barrier_write),
};
diff --git a/drivers/video/msm/mipi_toshiba_video_wsvga_pt.c b/drivers/video/msm/mipi_toshiba_video_wsvga_pt.c
index ed34aa7..2c02490 100644
--- a/drivers/video/msm/mipi_toshiba_video_wsvga_pt.c
+++ b/drivers/video/msm/mipi_toshiba_video_wsvga_pt.c
@@ -29,7 +29,7 @@
/* strength */
{0xff, 0x00, 0x06, 0x00},
/* pll control */
- {0x0, 0x7f, 0x1, 0x1a, 0x00, 0x50, 0x48, 0x63,
+ {0x0, 0x7f, 0x31, 0xda, 0x00, 0x50, 0x48, 0x63,
0x41, 0x0f, 0x01,
0x00, 0x14, 0x03, 0x00, 0x02, 0x00, 0x20, 0x00, 0x01 },
};
diff --git a/drivers/video/msm/mipi_truly.c b/drivers/video/msm/mipi_truly.c
new file mode 100644
index 0000000..a2060f0
--- /dev/null
+++ b/drivers/video/msm/mipi_truly.c
@@ -0,0 +1,259 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include "msm_fb.h"
+#include "mipi_dsi.h"
+#include "mipi_truly.h"
+
+static struct msm_panel_common_pdata *mipi_truly_pdata;
+static struct dsi_buf truly_tx_buf;
+static struct dsi_buf truly_rx_buf;
+
+#define TRULY_CMD_DELAY 0
+#define TRULY_SLEEP_OFF_DELAY 150
+#define TRULY_DISPLAY_ON_DELAY 150
+#define GPIO_TRULY_LCD_RESET 129
+
+static int prev_bl = 17;
+
+static char extend_cmd_enable[4] = {0xB9, 0xFF, 0x83, 0x69};
+static char display_setting[16] = {
+ 0xB2, 0x00, 0x23, 0x62,
+ 0x62, 0x70, 0x00, 0xFF,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x03, 0x03, 0x00, 0x01,
+};
+static char wave_cycle_setting[6] = {0xB4, 0x00, 0x1D, 0x5F, 0x0E, 0x06};
+static char gip_setting[27] = {
+ 0xD5, 0x00, 0x04, 0x03,
+ 0x00, 0x01, 0x05, 0x1C,
+ 0x70, 0x01, 0x03, 0x00,
+ 0x00, 0x40, 0x06, 0x51,
+ 0x07, 0x00, 0x00, 0x41,
+ 0x06, 0x50, 0x07, 0x07,
+ 0x0F, 0x04, 0x00,
+};
+static char power_setting[20] = {
+ 0xB1, 0x01, 0x00, 0x34,
+ 0x06, 0x00, 0x0F, 0x0F,
+ 0x2A, 0x32, 0x3F, 0x3F,
+ 0x07, 0x3A, 0x01, 0xE6,
+ 0xE6, 0xE6, 0xE6, 0xE6,
+};
+static char vcom_setting[3] = {0xB6, 0x56, 0x56};
+static char pannel_setting[2] = {0xCC, 0x02};
+static char gamma_setting[35] = {
+ 0xE0, 0x00, 0x1D, 0x22,
+ 0x38, 0x3D, 0x3F, 0x2E,
+ 0x4A, 0x06, 0x0D, 0x0F,
+ 0x13, 0x15, 0x13, 0x16,
+ 0x10, 0x19, 0x00, 0x1D,
+ 0x22, 0x38, 0x3D, 0x3F,
+ 0x2E, 0x4A, 0x06, 0x0D,
+ 0x0F, 0x13, 0x15, 0x13,
+ 0x16, 0x10, 0x19,
+};
+static char mipi_setting[14] = {
+ 0xBA, 0x00, 0xA0, 0xC6,
+ 0x00, 0x0A, 0x00, 0x10,
+ 0x30, 0x6F, 0x02, 0x11,
+ 0x18, 0x40,
+};
+static char exit_sleep[2] = {0x11, 0x00};
+static char display_on[2] = {0x29, 0x00};
+static char display_off[2] = {0x28, 0x00};
+static char enter_sleep[2] = {0x10, 0x00};
+
+static struct dsi_cmd_desc truly_display_off_cmds[] = {
+ {DTYPE_DCS_WRITE, 1, 0, 0, 10, sizeof(display_off), display_off},
+ {DTYPE_DCS_WRITE, 1, 0, 0, 120, sizeof(enter_sleep), enter_sleep}
+};
+
+static struct dsi_cmd_desc truly_display_on_cmds[] = {
+ {DTYPE_GEN_LWRITE, 1, 0, 0, TRULY_CMD_DELAY,
+ sizeof(extend_cmd_enable), extend_cmd_enable},
+ {DTYPE_GEN_LWRITE, 1, 0, 0, TRULY_CMD_DELAY,
+ sizeof(display_setting), display_setting},
+ {DTYPE_GEN_LWRITE, 1, 0, 0, TRULY_CMD_DELAY,
+ sizeof(wave_cycle_setting), wave_cycle_setting},
+ {DTYPE_GEN_LWRITE, 1, 0, 0, TRULY_CMD_DELAY,
+ sizeof(gip_setting), gip_setting},
+ {DTYPE_GEN_LWRITE, 1, 0, 0, TRULY_CMD_DELAY,
+ sizeof(power_setting), power_setting},
+ {DTYPE_GEN_LWRITE, 1, 0, 0, TRULY_CMD_DELAY,
+ sizeof(vcom_setting), vcom_setting},
+ {DTYPE_GEN_LWRITE, 1, 0, 0, TRULY_CMD_DELAY,
+ sizeof(pannel_setting), pannel_setting},
+ {DTYPE_GEN_LWRITE, 1, 0, 0, TRULY_CMD_DELAY,
+ sizeof(gamma_setting), gamma_setting},
+ {DTYPE_GEN_LWRITE, 1, 0, 0, TRULY_CMD_DELAY,
+ sizeof(mipi_setting), mipi_setting},
+ {DTYPE_DCS_WRITE, 1, 0, 0, TRULY_SLEEP_OFF_DELAY,
+ sizeof(exit_sleep), exit_sleep},
+ {DTYPE_DCS_WRITE, 1, 0, 0, TRULY_DISPLAY_ON_DELAY,
+ sizeof(display_on), display_on},
+};
+
+static int mipi_truly_lcd_on(struct platform_device *pdev)
+{
+ struct msm_fb_data_type *mfd;
+
+ mfd = platform_get_drvdata(pdev);
+
+ if (!mfd)
+ return -ENODEV;
+ if (mfd->key != MFD_KEY)
+ return -EINVAL;
+
+ msleep(20);
+ mipi_dsi_cmds_tx(mfd, &truly_tx_buf, truly_display_on_cmds,
+ ARRAY_SIZE(truly_display_on_cmds));
+
+ return 0;
+}
+
+static int mipi_truly_lcd_off(struct platform_device *pdev)
+{
+ struct msm_fb_data_type *mfd;
+
+ mfd = platform_get_drvdata(pdev);
+
+ if (!mfd)
+ return -ENODEV;
+ if (mfd->key != MFD_KEY)
+ return -EINVAL;
+
+ mipi_dsi_cmds_tx(mfd, &truly_tx_buf, truly_display_off_cmds,
+ ARRAY_SIZE(truly_display_off_cmds));
+
+ return 0;
+}
+
+#define BL_LEVEL 17
+static void mipi_truly_set_backlight(struct msm_fb_data_type *mfd)
+{
+ int step = 0, i = 0;
+ int bl_level = mfd->bl_level;
+
+ /* real backlight level, 1 - max, 16 - min, 17 - off */
+ bl_level = BL_LEVEL - bl_level;
+
+ if (bl_level > prev_bl) {
+ step = bl_level - prev_bl;
+ if (bl_level == BL_LEVEL)
+ step--;
+ } else if (bl_level < prev_bl) {
+ step = bl_level + 16 - prev_bl;
+ } else {
+ pr_debug("%s: no change\n", __func__);
+ return;
+ }
+
+ if (bl_level == BL_LEVEL) {
+ /* turn off backlight */
+ mipi_truly_pdata->pmic_backlight(0);
+ } else {
+ if (prev_bl == BL_LEVEL) {
+ /* turn on backlight */
+ mipi_truly_pdata->pmic_backlight(1);
+ udelay(30);
+ }
+ /* adjust backlight level */
+ for (i = 0; i < step; i++) {
+ mipi_truly_pdata->pmic_backlight(0);
+ udelay(1);
+ mipi_truly_pdata->pmic_backlight(1);
+ udelay(1);
+ }
+ }
+ msleep(20);
+ prev_bl = bl_level;
+
+ return;
+}
+
+static int __devinit mipi_truly_lcd_probe(struct platform_device *pdev)
+{
+ if (pdev->id == 0) {
+ mipi_truly_pdata = pdev->dev.platform_data;
+ return 0;
+ }
+
+ msm_fb_add_device(pdev);
+
+ return 0;
+}
+
+static struct platform_driver this_driver = {
+ .probe = mipi_truly_lcd_probe,
+ .driver = {
+ .name = "mipi_truly",
+ },
+};
+
+static struct msm_fb_panel_data truly_panel_data = {
+ .on = mipi_truly_lcd_on,
+ .off = mipi_truly_lcd_off,
+ .set_backlight = mipi_truly_set_backlight,
+};
+
+static int ch_used[3];
+
+int mipi_truly_device_register(struct msm_panel_info *pinfo,
+ u32 channel, u32 panel)
+{
+ struct platform_device *pdev = NULL;
+ int ret;
+
+ if ((channel >= 3) || ch_used[channel])
+ return -ENODEV;
+
+ ch_used[channel] = TRUE;
+
+ pdev = platform_device_alloc("mipi_truly", (panel << 8)|channel);
+
+ if (!pdev)
+ return -ENOMEM;
+
+ truly_panel_data.panel_info = *pinfo;
+
+ ret = platform_device_add_data(pdev, &truly_panel_data,
+ sizeof(truly_panel_data));
+ if (ret) {
+ pr_err("%s: platform_device_add_data failed!\n", __func__);
+ goto err_device_put;
+ }
+
+ ret = platform_device_add(pdev);
+
+ if (ret) {
+ pr_err("%s: platform_device_register failed!\n", __func__);
+ goto err_device_put;
+ }
+
+ return 0;
+
+err_device_put:
+ platform_device_put(pdev);
+ return ret;
+}
+
+static int __init mipi_truly_lcd_init(void)
+{
+ mipi_dsi_buf_alloc(&truly_tx_buf, DSI_BUF_SIZE);
+ mipi_dsi_buf_alloc(&truly_rx_buf, DSI_BUF_SIZE);
+
+ return platform_driver_register(&this_driver);
+}
+
+module_init(mipi_truly_lcd_init);
diff --git a/drivers/video/msm/mipi_truly.h b/drivers/video/msm/mipi_truly.h
new file mode 100644
index 0000000..900e6f6
--- /dev/null
+++ b/drivers/video/msm/mipi_truly.h
@@ -0,0 +1,21 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MIPI_TRULY_H
+#define MIPI_TRULY_H
+
+/* #define MIPI_TRULY_FAKE_PANEL */ /* FAKE PANEL for test */
+
+int mipi_truly_device_register(struct msm_panel_info *pinfo,
+ u32 channel, u32 panel);
+
+#endif /* MIPI_TRULY_H */
diff --git a/drivers/video/msm/mipi_truly_video_wvga_pt.c b/drivers/video/msm/mipi_truly_video_wvga_pt.c
new file mode 100644
index 0000000..931c564
--- /dev/null
+++ b/drivers/video/msm/mipi_truly_video_wvga_pt.c
@@ -0,0 +1,110 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include "msm_fb.h"
+#include "mipi_dsi.h"
+#include "mipi_truly.h"
+
+static struct msm_panel_info pinfo;
+
+static struct mipi_dsi_phy_ctrl dsi_video_mode_phy_db = {
+ /* DSI Bit Clock at 500 MHz, 2 lane, RGB888 */
+ /* regulator */
+ {0x03, 0x01, 0x01, 0x00},
+ /* timing */
+ {0xb9, 0x8e, 0x1f, 0x00, 0x98, 0x9c, 0x22, 0x90,
+ 0x18, 0x03, 0x04},
+ /* phy ctrl */
+ {0x7f, 0x00, 0x00, 0x00},
+ /* strength */
+ {0xbb, 0x02, 0x06, 0x00},
+ /* pll control */
+ {0x00, 0xec, 0x31, 0xd2, 0x00, 0x40, 0x37, 0x62,
+ 0x01, 0x0f, 0x07,
+ 0x05, 0x14, 0x03, 0x0, 0x0, 0x0, 0x20, 0x0, 0x02, 0x0},
+};
+
+static int __init mipi_video_truly_wvga_pt_init(void)
+{
+ int ret;
+
+#ifdef CONFIG_FB_MSM_MIPI_PANEL_DETECT
+ if (msm_fb_detect_client("mipi_video_truly_wvga"))
+ return 0;
+#endif
+
+ pinfo.xres = 480;
+ pinfo.yres = 800;
+ pinfo.type = MIPI_VIDEO_PANEL;
+ pinfo.pdest = DISPLAY_1;
+ pinfo.wait_cycle = 0;
+ pinfo.bpp = 24;
+ pinfo.lcdc.h_back_porch = 100;
+ pinfo.lcdc.h_front_porch = 100;
+ pinfo.lcdc.h_pulse_width = 8;
+ pinfo.lcdc.v_back_porch = 20;
+ pinfo.lcdc.v_front_porch = 20;
+ pinfo.lcdc.v_pulse_width = 1;
+ pinfo.lcdc.border_clr = 0; /* blk */
+ pinfo.lcdc.underflow_clr = 0xff; /* blue */
+ /* number of dot_clk cycles HSYNC active edge
+ is delayed from VSYNC active edge */
+ pinfo.lcdc.hsync_skew = 0;
+ pinfo.clk_rate = 499000000;
+ pinfo.bl_max = 15;
+ pinfo.bl_min = 1;
+ pinfo.fb_num = 2;
+
+ pinfo.mipi.mode = DSI_VIDEO_MODE;
+ pinfo.mipi.pulse_mode_hsa_he = TRUE; /* send HSA and HE following
+ VS/VE packet */
+ pinfo.mipi.hfp_power_stop = TRUE; /* LP-11 during the HFP period */
+ pinfo.mipi.hbp_power_stop = TRUE; /* LP-11 during the HBP period */
+ pinfo.mipi.hsa_power_stop = TRUE; /* LP-11 during the HSA period */
+ /* LP-11 or let Command Mode Engine send packets in
+ HS or LP mode for the BLLP of the last line of a frame */
+ pinfo.mipi.eof_bllp_power_stop = TRUE;
+ /* LP-11 or let Command Mode Engine send packets in
+ HS or LP mode for packets sent during BLLP period */
+ pinfo.mipi.bllp_power_stop = TRUE;
+
+ pinfo.mipi.traffic_mode = DSI_BURST_MODE;
+ pinfo.mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB888;
+ pinfo.mipi.vc = 0;
+ pinfo.mipi.rgb_swap = DSI_RGB_SWAP_RGB; /* RGB */
+ pinfo.mipi.data_lane0 = TRUE;
+ pinfo.mipi.data_lane1 = TRUE;
+
+ pinfo.mipi.t_clk_post = 0x20;
+ pinfo.mipi.t_clk_pre = 0x2f;
+
+ pinfo.mipi.stream = 0; /* dma_p */
+ pinfo.mipi.mdp_trigger = DSI_CMD_TRIGGER_NONE;
+ pinfo.mipi.dma_trigger = DSI_CMD_TRIGGER_SW;
+ pinfo.mipi.frame_rate = 60; /* FIXME */
+
+ pinfo.mipi.dsi_phy_db = &dsi_video_mode_phy_db;
+ pinfo.mipi.dlane_swap = 0x01;
+ pinfo.mipi.tx_eot_append = 0x01; /* append EOT at the end
+ of data burst */
+
+ ret = mipi_truly_device_register(&pinfo, MIPI_DSI_PRIM,
+ MIPI_DSI_PANEL_WVGA_PT);
+
+ if (ret)
+ pr_err("%s: failed to register device!\n", __func__);
+
+ return ret;
+}
+
+module_init(mipi_video_truly_wvga_pt_init);
diff --git a/drivers/video/msm/msm_fb.c b/drivers/video/msm/msm_fb.c
index e5ec4cb..94c38ff 100644
--- a/drivers/video/msm/msm_fb.c
+++ b/drivers/video/msm/msm_fb.c
@@ -2690,6 +2690,11 @@
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
}
}
+#else
+static void msmfb_set_color_conv(struct mdp_csc *p)
+{
+ mdp4_vg_csc_update(p);
+}
#endif
static int msmfb_notify_update(struct fb_info *info, unsigned long *argp)
@@ -2726,6 +2731,8 @@
struct mdp_histogram hist;
#ifndef CONFIG_FB_MSM_MDP40
struct mdp_ccs ccs_matrix;
+#else
+ struct mdp_csc csc_matrix;
#endif
struct mdp_page_protection fb_page_protection;
int ret = 0;
@@ -2805,7 +2812,16 @@
msmfb_set_color_conv(&ccs_matrix) ;
up(&msm_fb_ioctl_ppp_sem);
#else
- ret = -EINVAL;
+ ret = copy_from_user(&csc_matrix, argp, sizeof(csc_matrix));
+ if (ret) {
+ pr_err("%s:MSMFB_SET_CSC_MATRIX ioctl failed\n",
+ __func__);
+ return ret;
+ }
+ down(&msm_fb_ioctl_ppp_sem);
+ msmfb_set_color_conv(&csc_matrix);
+ up(&msm_fb_ioctl_ppp_sem);
+
#endif
break;
diff --git a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_interrupt_handler.c b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_interrupt_handler.c
index c2ab8ad..cc35ea3 100644
--- a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_interrupt_handler.c
+++ b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_interrupt_handler.c
@@ -877,25 +877,31 @@
vidc_1080p_clear_returned_channel_inst_id();
ddl = ddl_get_current_ddl_client_for_channel_id(ddl_context,
ddl_context->response_cmd_ch_id);
- if (!ddl || (!DDLCLIENT_STATE_IS(ddl, DDL_CLIENT_WAIT_FOR_EOS_DONE))) {
- DDL_MSG_ERROR("STATE-CRITICAL-EOSFRMDONE");
- ddl_client_fatal_cb(ddl);
+ if (ddl == NULL) {
+ DDL_MSG_ERROR("NO_DDL_CONTEXT");
} else {
- struct ddl_encoder_data *encoder = &(ddl->codec_data.encoder);
- vidc_1080p_get_encode_frame_info(&encoder->enc_frame_info);
- ddl_handle_enc_frame_done(ddl);
- DDL_MSG_LOW("encoder_eos_done");
- ddl->cmd_state = DDL_CMD_INVALID;
- DDL_MSG_LOW("ddl_state_transition: %s ~~>"
+ if (!DDLCLIENT_STATE_IS(ddl, DDL_CLIENT_WAIT_FOR_EOS_DONE)) {
+ DDL_MSG_ERROR("STATE-CRITICAL-EOSFRMDONE");
+ ddl_client_fatal_cb(ddl);
+ } else {
+ struct ddl_encoder_data *encoder =
+ &(ddl->codec_data.encoder);
+ vidc_1080p_get_encode_frame_info(
+ &encoder->enc_frame_info);
+ ddl_handle_enc_frame_done(ddl);
+ DDL_MSG_LOW("encoder_eos_done");
+ ddl->cmd_state = DDL_CMD_INVALID;
+ DDL_MSG_LOW("ddl_state_transition: %s ~~>"
"DDL_CLIENT_WAIT_FOR_FRAME",
ddl_get_state_string(ddl->client_state));
- ddl->client_state = DDL_CLIENT_WAIT_FOR_FRAME;
- DDL_MSG_LOW("eos_done");
- ddl_context->ddl_callback(VCD_EVT_RESP_EOS_DONE,
- VCD_S_SUCCESS, NULL, 0,
- (u32 *)ddl, ddl->client_data);
- ddl_release_command_channel(ddl_context,
- ddl->command_channel);
+ ddl->client_state = DDL_CLIENT_WAIT_FOR_FRAME;
+ DDL_MSG_LOW("eos_done");
+ ddl_context->ddl_callback(VCD_EVT_RESP_EOS_DONE,
+ VCD_S_SUCCESS, NULL, 0,
+ (u32 *)ddl, ddl->client_data);
+ ddl_release_command_channel(ddl_context,
+ ddl->command_channel);
+ }
}
}
diff --git a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_properties.c b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_properties.c
index bb26c51..0405513 100644
--- a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_properties.c
+++ b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_properties.c
@@ -834,38 +834,55 @@
break;
case VCD_I_RECON_BUFFERS:
{
- int index;
+ int index, index_hw_bufs = -1;
struct vcd_property_enc_recon_buffer *recon_buffers =
(struct vcd_property_enc_recon_buffer *)property_value;
for (index = 0; index < 4; index++) {
- if (!encoder->hw_bufs.dpb_y[index].align_physical_addr)
+ if (!encoder->hw_bufs.dpb_y[index].
+ align_physical_addr) {
+ index_hw_bufs = index;
break;
- else
+ } else
continue;
- }
- if (property_hdr->sz == sizeof(struct
- vcd_property_enc_recon_buffer)) {
- encoder->hw_bufs.dpb_y[index].align_physical_addr =
- recon_buffers->physical_addr;
- encoder->hw_bufs.dpb_y[index].align_virtual_addr =
- recon_buffers->kernel_virtual_addr;
- encoder->hw_bufs.dpb_y[index].buffer_size =
- recon_buffers->buffer_size;
- encoder->hw_bufs.dpb_c[index].align_physical_addr =
- recon_buffers->physical_addr + ddl_get_yuv_buf_size(
- encoder->frame_size.width, encoder->frame_size.
- height, DDL_YUV_BUF_TYPE_TILE);
- encoder->hw_bufs.dpb_c[index].align_virtual_addr =
- recon_buffers->kernel_virtual_addr +
- recon_buffers->ysize;
- DDL_MSG_LOW("Y::KVirt: %p,KPhys: %p"
- "UV::KVirt: %p,KPhys: %p\n",
- encoder->hw_bufs.dpb_y[index].align_virtual_addr,
- encoder->hw_bufs.dpb_y[index].align_physical_addr,
- encoder->hw_bufs.dpb_c[index].align_virtual_addr,
- encoder->hw_bufs.dpb_c[index].align_physical_addr);
- vcd_status = VCD_S_SUCCESS;
- }
+ }
+ if (index_hw_bufs == -1) {
+ DDL_MSG_HIGH("ERROR: value of index_hw_bufs");
+ vcd_status = VCD_ERR_ILLEGAL_PARM;
+ } else {
+ if (property_hdr->sz == sizeof(struct
+ vcd_property_enc_recon_buffer)) {
+ encoder->hw_bufs.dpb_y[index_hw_bufs].
+ align_physical_addr =
+ recon_buffers->physical_addr;
+ encoder->hw_bufs.dpb_y[index_hw_bufs].
+ align_virtual_addr =
+ recon_buffers->kernel_virtual_addr;
+ encoder->hw_bufs.dpb_y[index_hw_bufs].
+ buffer_size = recon_buffers->buffer_size;
+ encoder->hw_bufs.dpb_c[index_hw_bufs].
+ align_physical_addr =
+ recon_buffers->physical_addr +
+ ddl_get_yuv_buf_size(
+ encoder->frame_size.width,
+ encoder->frame_size.height,
+ DDL_YUV_BUF_TYPE_TILE);
+ encoder->hw_bufs.dpb_c[index_hw_bufs].
+ align_virtual_addr =
+ recon_buffers->kernel_virtual_addr +
+ recon_buffers->ysize;
+ DDL_MSG_LOW("Y::KVirt: %p,KPhys: %p"
+ "UV::KVirt: %p,KPhys: %p\n",
+ encoder->hw_bufs.dpb_y[index_hw_bufs].
+ align_virtual_addr,
+ encoder->hw_bufs.dpb_y[index_hw_bufs].
+ align_physical_addr,
+ encoder->hw_bufs.dpb_c[index_hw_bufs].
+ align_virtual_addr,
+ encoder->hw_bufs.dpb_c[index_hw_bufs].
+ align_physical_addr);
+ vcd_status = VCD_S_SUCCESS;
+ }
+ }
}
break;
case VCD_I_FREE_RECON_BUFFERS:
diff --git a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_shared_mem.c b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_shared_mem.c
index 8160895..ac05364 100644
--- a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_shared_mem.c
+++ b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_shared_mem.c
@@ -690,7 +690,7 @@
enum vidc_sm_mpeg4_profileinfo profile_info)
{
u32 profile_enforce = 0;
- if (shared_mem) {
+ if (shared_mem != NULL) {
profile_enforce = 1;
switch (profile_info) {
case VIDC_SM_PROFILE_INFO_ASP:
@@ -704,8 +704,8 @@
profile_enforce = 0;
break;
}
+ DDL_MEM_WRITE_32(shared_mem, 0x15c, profile_enforce);
}
- DDL_MEM_WRITE_32(shared_mem, 0x15c, profile_enforce);
}
void vidc_sm_set_decoder_sei_enable(struct ddl_buf_addr *shared_mem,
u32 sei_enable)
diff --git a/drivers/video/msm/vidc/720p/resource_tracker/vcd_res_tracker.c b/drivers/video/msm/vidc/720p/resource_tracker/vcd_res_tracker.c
index 54d48b8..7ac32b7 100644
--- a/drivers/video/msm/vidc/720p/resource_tracker/vcd_res_tracker.c
+++ b/drivers/video/msm/vidc/720p/resource_tracker/vcd_res_tracker.c
@@ -407,7 +407,7 @@
{
VCDRES_MSG_MED("\n res_trk_power_up():: "
"Calling AXI add requirement\n");
- ebi1_clk = clk_get(NULL, "mem_clk");
+ ebi1_clk = clk_get(resource_context.device, "mem_clk");
if (IS_ERR(ebi1_clk)) {
VCDRES_MSG_ERROR("Request AXI bus QOS fails.");
return false;
diff --git a/include/linux/diagchar.h b/include/linux/diagchar.h
index 91d67d5..5c94a3c 100644
--- a/include/linux/diagchar.h
+++ b/include/linux/diagchar.h
@@ -40,8 +40,10 @@
#define APQ8060_MACHINE_ID 86
#define AO8960_MACHINE_ID 87
#define MSM8660_MACHINE_ID 71
+#define APQ8064_MACHINE_ID 109
#define APQ8060_TOOLS_ID 4062
#define AO8960_TOOLS_ID 4064
+#define APQ8064_TOOLS_ID 4072
#define MSG_MASK_0 (0x00000001)
#define MSG_MASK_1 (0x00000002)
diff --git a/include/linux/eeprom_93cx6.h b/include/linux/eeprom_93cx6.h
index c4627cb..e50f98b 100644
--- a/include/linux/eeprom_93cx6.h
+++ b/include/linux/eeprom_93cx6.h
@@ -33,6 +33,7 @@
#define PCI_EEPROM_WIDTH_93C86 8
#define PCI_EEPROM_WIDTH_OPCODE 3
#define PCI_EEPROM_WRITE_OPCODE 0x05
+#define PCI_EEPROM_ERASE_OPCODE 0x07
#define PCI_EEPROM_READ_OPCODE 0x06
#define PCI_EEPROM_EWDS_OPCODE 0x10
#define PCI_EEPROM_EWEN_OPCODE 0x13
@@ -46,6 +47,7 @@
* @register_write(struct eeprom_93cx6 *eeprom): handler to
* write to the eeprom register by using all reg_* fields.
* @width: eeprom width, should be one of the PCI_EEPROM_WIDTH_* defines
+ * @drive_data: Set if we're driving the data line.
* @reg_data_in: register field to indicate data input
* @reg_data_out: register field to indicate data output
* @reg_data_clock: register field to set the data clock
@@ -62,6 +64,7 @@
int width;
+ char drive_data;
char reg_data_in;
char reg_data_out;
char reg_data_clock;
@@ -72,3 +75,8 @@
const u8 word, u16 *data);
extern void eeprom_93cx6_multiread(struct eeprom_93cx6 *eeprom,
const u8 word, __le16 *data, const u16 words);
+
+extern void eeprom_93cx6_wren(struct eeprom_93cx6 *eeprom, bool enable);
+
+extern void eeprom_93cx6_write(struct eeprom_93cx6 *eeprom,
+ u8 addr, u16 data);
diff --git a/include/linux/i2c/atmel_mxt_ts.h b/include/linux/i2c/atmel_mxt_ts.h
index 6a1c918..c425343 100644
--- a/include/linux/i2c/atmel_mxt_ts.h
+++ b/include/linux/i2c/atmel_mxt_ts.h
@@ -3,6 +3,7 @@
*
* Copyright (C) 2010 Samsung Electronics Co.Ltd
* Author: Joonyoung Shim <jy0922.shim@samsung.com>
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -30,18 +31,12 @@
const u8 *config;
size_t config_length;
- unsigned int x_line;
- unsigned int y_line;
unsigned int x_size;
unsigned int y_size;
- unsigned int blen;
- unsigned int threshold;
- unsigned int voltage;
- unsigned char orient;
unsigned long irqflags;
bool i2c_pull_up;
- u8(*read_chg) (void);
+ u8(*read_chg) (void);
int (*init_hw) (bool);
int (*power_on) (bool);
};
diff --git a/include/linux/mfd/pm8xxx/pm8018.h b/include/linux/mfd/pm8xxx/pm8018.h
index ac7231a..1093409 100644
--- a/include/linux/mfd/pm8xxx/pm8018.h
+++ b/include/linux/mfd/pm8xxx/pm8018.h
@@ -26,6 +26,9 @@
#include <linux/input/pmic8xxx-pwrkey.h>
#include <linux/mfd/pm8xxx/misc.h>
#include <linux/regulator/pm8018-regulator.h>
+#include <linux/mfd/pm8xxx/pm8xxx-adc.h>
+#include <linux/mfd/pm8xxx/pwm.h>
+#include <linux/leds-pm8xxx.h>
#define PM8018_CORE_DEV_NAME "pm8018-core"
@@ -50,6 +53,9 @@
#define PM8018_PWRKEY_REL_IRQ PM8018_IRQ_BLOCK_BIT(6, 2)
#define PM8018_PWRKEY_PRESS_IRQ PM8018_IRQ_BLOCK_BIT(6, 3)
+#define PM8018_ADC_EOC_USR_IRQ PM8018_IRQ_BLOCK_BIT(9, 6)
+#define PM8018_ADC_BATT_TEMP_WARM_IRQ PM8018_IRQ_BLOCK_BIT(9, 1)
+#define PM8018_ADC_BATT_TEMP_COLD_IRQ PM8018_IRQ_BLOCK_BIT(9, 0)
struct pm8018_platform_data {
struct pm8xxx_irq_platform_data *irq_pdata;
@@ -59,7 +65,9 @@
struct pm8xxx_pwrkey_platform_data *pwrkey_pdata;
struct pm8xxx_misc_platform_data *misc_pdata;
struct pm8018_regulator_platform_data *regulator_pdatas;
+ struct pm8xxx_adc_platform_data *adc_pdata;
int num_regulators;
+ struct pm8xxx_led_platform_data *leds_pdata;
};
#endif
diff --git a/include/linux/mfd/pm8xxx/pm8xxx-adc.h b/include/linux/mfd/pm8xxx/pm8xxx-adc.h
new file mode 100644
index 0000000..aa642cc
--- /dev/null
+++ b/include/linux/mfd/pm8xxx/pm8xxx-adc.h
@@ -0,0 +1,574 @@
+/*
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+/*
+ * Qualcomm PMIC 8921/8018 ADC driver header file
+ *
+ */
+
+#ifndef __PM8XXX_ADC_H
+#define __PM8XXX_ADC_H
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+
+/**
+ * enum pm8xxx_adc_channels - PM8XXX AMUX arbiter channels
+ * %CHANNEL_VCOIN: Backup voltage for certain register set
+ * %CHANNEL_VBAT: Battery voltage
+ * %CHANNEL_DCIN: Charger input voltage without internal OVP
+ * %CHANNEL_ICHG: Charge-current monitor
+ * %CHANNEL_VPH_PWR: Main system power
+ * %CHANNEL_IBAT: Battery charge current
+ * %CHANNEL_MPP_1: 16:1 pre-mux unity scale MPP input
+ * %CHANNEL_MPP_2: 16:1 pre-mux 1/3 scale MPP input
+ * %CHANNEL_BATT_THERM: Battery temperature
+ * %CHANNEL_BATT_ID: Battery detection
+ * %CHANNEL_USBIN: Charger input voltage with internal OVP
+ * %CHANNEL_DIE_TEMP: Pmic_die temperature
+ * %CHANNEL_625MV: 625mv reference channel
+ * %CHANNEL_125V: 1.25v reference channel
+ * %CHANNEL_CHG_TEMP: Charger temperature
+ * %CHANNEL_MUXOFF: Channel to reduce input load on the mux
+ * %CHANNEL_NONE: Do not use this channel
+ */
+enum pm8xxx_adc_channels {
+ CHANNEL_VCOIN = 0,
+ CHANNEL_VBAT,
+ CHANNEL_DCIN,
+ CHANNEL_ICHG,
+ CHANNEL_VPH_PWR,
+ CHANNEL_IBAT,
+ CHANNEL_MPP_1,
+ CHANNEL_MPP_2,
+ CHANNEL_BATT_THERM,
+ CHANNEL_BATT_ID,
+ CHANNEL_USBIN,
+ CHANNEL_DIE_TEMP,
+ CHANNEL_625MV,
+ CHANNEL_125V,
+ CHANNEL_CHG_TEMP,
+ CHANNEL_MUXOFF,
+ CHANNEL_NONE,
+ ADC_MPP_1_ATEST_8 = 20,
+ ADC_MPP_1_USB_SNS_DIV20,
+ ADC_MPP_1_DCIN_SNS_DIV20,
+ ADC_MPP_1_AMUX3,
+ ADC_MPP_1_AMUX4,
+ ADC_MPP_1_AMUX5,
+ ADC_MPP_1_AMUX6,
+ ADC_MPP_1_AMUX7,
+ ADC_MPP_1_AMUX8,
+ ADC_MPP_1_ATEST_1,
+ ADC_MPP_1_ATEST_2,
+ ADC_MPP_1_ATEST_3,
+ ADC_MPP_1_ATEST_4,
+ ADC_MPP_1_ATEST_5,
+ ADC_MPP_1_ATEST_6,
+ ADC_MPP_1_ATEST_7,
+ ADC_MPP_1_CHANNEL_NONE,
+ ADC_MPP_2_ATEST_8 = 40,
+ ADC_MPP_2_USB_SNS_DIV20,
+ ADC_MPP_2_DCIN_SNS_DIV20,
+ ADC_MPP_2_AMUX3,
+ ADC_MPP_2_AMUX4,
+ ADC_MPP_2_AMUX5,
+ ADC_MPP_2_AMUX6,
+ ADC_MPP_2_AMUX7,
+ ADC_MPP_2_AMUX8,
+ ADC_MPP_2_ATEST_1,
+ ADC_MPP_2_ATEST_2,
+ ADC_MPP_2_ATEST_3,
+ ADC_MPP_2_ATEST_4,
+ ADC_MPP_2_ATEST_5,
+ ADC_MPP_2_ATEST_6,
+ ADC_MPP_2_ATEST_7,
+ ADC_MPP_2_CHANNEL_NONE,
+};
+
+#define PM8XXX_ADC_PMIC_0 0x0
+
+#define PM8XXX_CHANNEL_ADC_625_MV 625
+#define PM8XXX_CHANNEL_MPP_SCALE1_IDX 20
+#define PM8XXX_CHANNEL_MPP_SCALE3_IDX 40
+
+#define PM8XXX_AMUX_MPP_3 0x3
+#define PM8XXX_AMUX_MPP_4 0x4
+#define PM8XXX_AMUX_MPP_5 0x5
+#define PM8XXX_AMUX_MPP_6 0x6
+#define PM8XXX_AMUX_MPP_7 0x7
+#define PM8XXX_AMUX_MPP_8 0x8
+
+#define PM8XXX_ADC_DEV_NAME "pm8xxx-adc"
+
+/**
+ * enum pm8xxx_adc_decimation_type - Sampling rate supported
+ * %ADC_DECIMATION_TYPE1: 512
+ * %ADC_DECIMATION_TYPE2: 1K
+ * %ADC_DECIMATION_TYPE3: 2K
+ * %ADC_DECIMATION_TYPE4: 4k
+ * %ADC_DECIMATION_NONE: Do not use this Sampling type
+ *
+ * The Sampling rate is specific to each channel of the PM8XXX ADC arbiter.
+ */
+enum pm8xxx_adc_decimation_type {
+ ADC_DECIMATION_TYPE1 = 0,
+ ADC_DECIMATION_TYPE2,
+ ADC_DECIMATION_TYPE3,
+ ADC_DECIMATION_TYPE4,
+ ADC_DECIMATION_NONE,
+};
+
+/**
+ * enum pm8xxx_adc_calib_type - PM8XXX ADC Calibration type
+ * %ADC_CALIB_ABSOLUTE: Use 625mV and 1.25V reference channels
+ * %ADC_CALIB_RATIOMETRIC: Use reference Voltage/GND
+ * %ADC_CALIB_CONFIG_NONE: Do not use this calibration type
+ *
+ * Use the input reference voltage depending on the calibration type
+ * to calcluate the offset and gain parameters. The calibration is
+ * specific to each channel of the PM8XXX ADC.
+ */
+enum pm8xxx_adc_calib_type {
+ ADC_CALIB_ABSOLUTE = 0,
+ ADC_CALIB_RATIOMETRIC,
+ ADC_CALIB_NONE,
+};
+
+/**
+ * enum pm8xxx_adc_channel_scaling_param - pre-scaling AMUX ratio
+ * %CHAN_PATH_SCALING1: ratio of {1, 1}
+ * %CHAN_PATH_SCALING2: ratio of {1, 3}
+ * %CHAN_PATH_SCALING3: ratio of {1, 4}
+ * %CHAN_PATH_SCALING4: ratio of {1, 6}
+ * %CHAN_PATH_NONE: Do not use this pre-scaling ratio type
+ *
+ * The pre-scaling is applied for signals to be within the voltage range
+ * of the ADC.
+ */
+enum pm8xxx_adc_channel_scaling_param {
+ CHAN_PATH_SCALING1 = 0,
+ CHAN_PATH_SCALING2,
+ CHAN_PATH_SCALING3,
+ CHAN_PATH_SCALING4,
+ CHAN_PATH_SCALING_NONE,
+};
+
+/**
+ * enum pm8xxx_adc_amux_input_rsv - HK/XOADC reference voltage
+ * %AMUX_RSV0: XO_IN/XOADC_GND
+ * %AMUX_RSV1: PMIC_IN/XOADC_GND
+ * %AMUX_RSV2: PMIC_IN/BMS_CSP
+ * %AMUX_RSV3: not used
+ * %AMUX_RSV4: XOADC_GND/XOADC_GND
+ * %AMUX_RSV5: XOADC_VREF/XOADC_GND
+ * %AMUX_NONE: Do not use this input reference voltage selection
+ */
+enum pm8xxx_adc_amux_input_rsv {
+ AMUX_RSV0 = 0,
+ AMUX_RSV1,
+ AMUX_RSV2,
+ AMUX_RSV3,
+ AMUX_RSV4,
+ AMUX_RSV5,
+ AMUX_NONE,
+};
+
+/**
+ * enum pm8xxx_adc_premux_mpp_scale_type - 16:1 pre-mux scale ratio
+ * %PREMUX_MPP_SCALE_0: No scaling to the input signal
+ * %PREMUX_MPP_SCALE_1: Unity scaling selected by the user for MPP input
+ * %PREMUX_MPP_SCALE_1_DIV3: 1/3 pre-scale to the input MPP signal
+ * %PREMUX_MPP_NONE: Do not use this pre-scale mpp type
+ */
+enum pm8xxx_adc_premux_mpp_scale_type {
+ PREMUX_MPP_SCALE_0 = 0,
+ PREMUX_MPP_SCALE_1,
+ PREMUX_MPP_SCALE_1_DIV3,
+ PREMUX_MPP_NONE,
+};
+
+/**
+ * enum pm8xxx_adc_scale_fn_type - Scaling function for pm8921 pre calibrated
+ * digital data relative to ADC reference
+ * %ADC_SCALE_DEFAULT: Default scaling to convert raw adc code to voltage
+ * %ADC_SCALE_BATT_THERM: Conversion to temperature based on btm parameters
+ * %ADC_SCALE_PMIC_THERM: Returns result in milli degree's Centigrade
+ * %ADC_SCALE_XTERN_CHGR_CUR: Returns current across 0.1 ohm resistor
+ * %ADC_SCALE_XOTHERM: Returns XO thermistor voltage in degree's Centigrade
+ * %ADC_SCALE_NONE: Do not use this scaling type
+ */
+enum pm8xxx_adc_scale_fn_type {
+ ADC_SCALE_DEFAULT = 0,
+ ADC_SCALE_BATT_THERM,
+ ADC_SCALE_PA_THERM,
+ ADC_SCALE_PMIC_THERM,
+ ADC_SCALE_XOTHERM,
+ ADC_SCALE_NONE,
+};
+
+/**
+ * struct pm8xxx_adc_linear_graph - Represent ADC characteristics
+ * @offset: Offset with respect to the actual curve
+ * @dy: Numerator slope to calculate the gain
+ * @dx: Denominator slope to calculate the gain
+ *
+ * Each ADC device has different offset and gain parameters which are computed
+ * to calibrate the device.
+ */
+struct pm8xxx_adc_linear_graph {
+ int32_t offset;
+ int32_t dy;
+ int32_t dx;
+};
+
+/**
+ * struct pm8xxx_adc_map_pt - Map the graph representation for ADC channel
+ * @x: Represent the ADC digitized code
+ * @y: Represent the physical data which can be temperature, voltage,
+ * resistance
+ */
+struct pm8xxx_adc_map_pt {
+ int32_t x;
+ int32_t y;
+};
+
+/**
+ * struct pm8xxx_adc_scaling_ratio - Represent scaling ratio for adc input
+ * @num: Numerator scaling parameter
+ * @den: Denominator scaling parameter
+ */
+struct pm8xxx_adc_scaling_ratio {
+ int32_t num;
+ int32_t den;
+};
+
+/**
+ * struct pm8xxx_adc_properties - Represent the ADC properties
+ * @adc_reference: Reference voltage for PM8XXX ADC
+ * @bitresolution: ADC bit resolution for PM8XXX ADC
+ * @biploar: Polarity for PM8XXX ADC
+ */
+struct pm8xxx_adc_properties {
+ uint32_t adc_vdd_reference;
+ uint32_t bitresolution;
+ bool bipolar;
+};
+
+/**
+ * struct pm8xxx_adc_chan_properties - Represent channel properties of the ADC
+ * @offset_gain_numerator: The inverse numerator of the gain applied to the
+ * input channel
+ * @offset_gain_denominator: The inverse denominator of the gain applied to the
+ * input channel
+ * @adc_graph: ADC graph for the channel of struct type pm8xxx_adc_linear_graph
+ */
+struct pm8xxx_adc_chan_properties {
+ uint32_t offset_gain_numerator;
+ uint32_t offset_gain_denominator;
+ struct pm8xxx_adc_linear_graph adc_graph[2];
+};
+
+/**
+ * struct pm8xxx_adc_chan_result - Represent the result of the PM8XXX ADC
+ * @chan: The channel number of the requested conversion
+ * @adc_code: The pre-calibrated digital output of a given ADC relative to the
+ * the ADC reference
+ * @measurement: In units specific for a given ADC; most ADC uses reference
+ * voltage but some ADC uses reference current. This measurement
+ * here is a number relative to a reference of a given ADC
+ * @physical: The data meaningful for each individual channel whether it is
+ * voltage, current, temperature, etc.
+ */
+struct pm8xxx_adc_chan_result {
+ uint32_t chan;
+ int32_t adc_code;
+ int64_t measurement;
+ int64_t physical;
+};
+
+#if defined(CONFIG_SENSORS_PM8XXX_ADC) \
+ || defined(CONFIG_SENSORS_PM8XXX_ADC_MODULE)
+/**
+ * pm8xxx_adc_scale_default() - Scales the pre-calibrated digital output
+ * of an ADC to the ADC reference and compensates for the
+ * gain and offset.
+ * @adc_code: pre-calibrated digital ouput of the ADC.
+ * @adc_prop: adc properties of the pm8xxx adc such as bit resolution,
+ * reference voltage.
+ * @chan_prop: individual channel properties to compensate the i/p scaling,
+ * slope and offset.
+ * @chan_rslt: Physical result to be stored.
+ */
+int32_t pm8xxx_adc_scale_default(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_prop,
+ const struct pm8xxx_adc_chan_properties *chan_prop,
+ struct pm8xxx_adc_chan_result *chan_rslt);
+/**
+ * pm8xxx_adc_scale_tdkntcg_therm() - Scales the pre-calibrated digital output
+ * of an ADC to the ADC reference and compensates for the
+ * gain and offset. Returns the temperature of the xo therm in mili
+ degC.
+ * @adc_code: pre-calibrated digital ouput of the ADC.
+ * @adc_prop: adc properties of the pm8xxx adc such as bit resolution,
+ * reference voltage.
+ * @chan_prop: individual channel properties to compensate the i/p scaling,
+ * slope and offset.
+ * @chan_rslt: physical result to be stored.
+ */
+int32_t pm8xxx_adc_tdkntcg_therm(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_prop,
+ const struct pm8xxx_adc_chan_properties *chan_prop,
+ struct pm8xxx_adc_chan_result *chan_rslt);
+/**
+ * pm8xxx_adc_scale_batt_therm() - Scales the pre-calibrated digital output
+ * of an ADC to the ADC reference and compensates for the
+ * gain and offset. Returns the temperature in degC.
+ * @adc_code: pre-calibrated digital ouput of the ADC.
+ * @adc_prop: adc properties of the pm8xxx adc such as bit resolution,
+ * reference voltage.
+ * @chan_prop: individual channel properties to compensate the i/p scaling,
+ * slope and offset.
+ * @chan_rslt: physical result to be stored.
+ */
+int32_t pm8xxx_adc_scale_batt_therm(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_prop,
+ const struct pm8xxx_adc_chan_properties *chan_prop,
+ struct pm8xxx_adc_chan_result *chan_rslt);
+/**
+ * pm8xxx_adc_scale_pa_therm() - Scales the pre-calibrated digital output
+ * of an ADC to the ADC reference and compensates for the
+ * gain and offset. Returns the temperature in degC.
+ * @adc_code: pre-calibrated digital ouput of the ADC.
+ * @adc_prop: adc properties of the pm8xxx adc such as bit resolution,
+ * reference voltage.
+ * @chan_prop: individual channel properties to compensate the i/p scaling,
+ * slope and offset.
+ * @chan_rslt: physical result to be stored.
+ */
+int32_t pm8xxx_adc_scale_pa_therm(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_prop,
+ const struct pm8xxx_adc_chan_properties *chan_prop,
+ struct pm8xxx_adc_chan_result *chan_rslt);
+/**
+ * pm8xxx_adc_scale_pmic_therm() - Scales the pre-calibrated digital output
+ * of an ADC to the ADC reference and compensates for the
+ * gain and offset. Performs the AMUX out as 2mv/K and returns
+ * the temperature in mili degC.
+ * @adc_code: pre-calibrated digital ouput of the ADC.
+ * @adc_prop: adc properties of the pm8xxx adc such as bit resolution,
+ * reference voltage.
+ * @chan_prop: individual channel properties to compensate the i/p scaling,
+ * slope and offset.
+ * @chan_rslt: physical result to be stored.
+ */
+int32_t pm8xxx_adc_scale_pmic_therm(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_prop,
+ const struct pm8xxx_adc_chan_properties *chan_prop,
+ struct pm8xxx_adc_chan_result *chan_rslt);
+#else
+static inline int32_t pm8xxx_adc_scale_default(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_prop,
+ const struct pm8xxx_adc_chan_properties *chan_prop,
+ struct pm8xxx_adc_chan_result *chan_rslt)
+{ return -ENXIO; }
+static inline int32_t pm8xxx_adc_tdkntcg_therm(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_prop,
+ const struct pm8xxx_adc_chan_properties *chan_prop,
+ struct pm8xxx_adc_chan_result *chan_rslt)
+{ return -ENXIO; }
+static inline int32_t pm8xxx_adc_scale_batt_therm(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_prop,
+ const struct pm8xxx_adc_chan_properties *chan_prop,
+ struct pm8xxx_adc_chan_result *chan_rslt)
+{ return -ENXIO; }
+static inline int32_t pm8xxx_adc_scale_pa_therm(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_prop,
+ const struct pm8xxx_adc_chan_properties *chan_prop,
+ struct pm8xxx_adc_chan_result *chan_rslt)
+{ return -ENXIO; }
+static inline int32_t pm8xxx_adc_scale_pmic_therm(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_prop,
+ const struct pm8xxx_adc_chan_properties *chan_prop,
+ struct pm8xxx_adc_chan_result *chan_rslt)
+{ return -ENXIO; }
+#endif
+
+/**
+ * struct pm8xxx_adc_scale_fn - Scaling function prototype
+ * @chan: Function pointer to one of the scaling functions
+ * which takes the adc properties, channel properties,
+ * and returns the physical result
+ */
+struct pm8xxx_adc_scale_fn {
+ int32_t (*chan) (int32_t,
+ const struct pm8xxx_adc_properties *,
+ const struct pm8xxx_adc_chan_properties *,
+ struct pm8xxx_adc_chan_result *);
+};
+
+/**
+ * struct pm8xxx_adc_amux - AMUX properties for individual channel
+ * @name: Channel name
+ * @channel_name: Channel in integer used from pm8xxx_adc_channels
+ * @chan_path_prescaling: Channel scaling performed on the input signal
+ * @adc_rsv: Input reference Voltage/GND selection to the ADC
+ * @adc_decimation: Sampling rate desired for the channel
+ * adc_scale_fn: Scaling function to convert to the data meaningful for
+ * each individual channel whether it is voltage, current,
+ * temperature, etc and compensates the channel properties
+ */
+struct pm8xxx_adc_amux {
+ char *name;
+ enum pm8xxx_adc_channels channel_name;
+ enum pm8xxx_adc_channel_scaling_param chan_path_prescaling;
+ enum pm8xxx_adc_amux_input_rsv adc_rsv;
+ enum pm8xxx_adc_decimation_type adc_decimation;
+ enum pm8xxx_adc_scale_fn_type adc_scale_fn;
+};
+
+/**
+ * struct pm8xxx_adc_arb_btm_param - PM8XXX ADC BTM parameters to set threshold
+ * temperature for client notification
+ * @low_thr_temp: low temperature threshold request for notification
+ * @high_thr_temp: high temperature threshold request for notification
+ * @low_thr_voltage: low temperature converted to voltage by arbiter driver
+ * @high_thr_voltage: high temperature converted to voltage by arbiter driver
+ * @interval: Interval period to check for temperature notification
+ * @btm_warm_fn: Remote function call for warm threshold.
+ * @btm_cool_fn: Remote function call for cold threshold.
+ *
+ * BTM client passes the parameters to be set for the
+ * temperature threshold notifications. The client is
+ * responsible for setting the new threshold
+ * levels once the thresholds are reached
+ */
+struct pm8xxx_adc_arb_btm_param {
+ uint32_t low_thr_temp;
+ uint32_t high_thr_temp;
+ uint64_t low_thr_voltage;
+ uint64_t high_thr_voltage;
+ int32_t interval;
+ void (*btm_warm_fn) (bool);
+ void (*btm_cool_fn) (bool);
+};
+
+int32_t pm8xxx_adc_batt_scaler(struct pm8xxx_adc_arb_btm_param *);
+
+/**
+ * struct pm8xxx_adc_platform_data - PM8XXX ADC platform data
+ * @adc_prop: ADC specific parameters, voltage and channel setup
+ * @adc_channel: Channel properties of the ADC arbiter
+ * @adc_num_board_channel: Number of channels added in the board file
+ * @adc_mpp_base: PM8XXX MPP0 base passed from board file. This is used
+ * to offset the PM8XXX MPP passed to configure the
+ * the MPP to AMUX mapping.
+ */
+struct pm8xxx_adc_platform_data {
+ struct pm8xxx_adc_properties *adc_prop;
+ struct pm8xxx_adc_amux *adc_channel;
+ uint32_t adc_num_board_channel;
+ uint32_t adc_mpp_base;
+};
+
+/* Public API */
+#if defined(CONFIG_SENSORS_PM8XXX_ADC) \
+ || defined(CONFIG_SENSORS_PM8XXX_ADC_MODULE)
+/**
+ * pm8xxx_adc_read() - Performs ADC read on the channel.
+ * @channel: Input channel to perform the ADC read.
+ * @result: Structure pointer of type adc_chan_result
+ * in which the ADC read results are stored.
+ */
+uint32_t pm8xxx_adc_read(enum pm8xxx_adc_channels channel,
+ struct pm8xxx_adc_chan_result *result);
+/**
+ * pm8xxx_adc_mpp_config_read() - Configure's the PM8XXX MPP
+ * to AMUX6 and performs an ADC read.
+ *
+ * On PM8921 ADC the MPP needs to first be configured
+ * as an analog input to the AMUX pre-mux channel before
+ * issuing a read request. PM8921 MPP 8 is mapped to AMUX8
+ * and is common between remote processor's.
+ *
+ * On PM8018 ADC the MPP is directly connected to the AMUX
+ * pre-mux. Therefore clients of the PM8018 MPP do not need
+ * to configure the MPP as an analog input to the pre-mux.
+ * Clients can directly issue request on the pre-mux AMUX
+ * channel to read the ADC on the MPP. Clients can directly
+ * call the pm8xxx_adc_read().
+ * @mpp_num PM8XXX MPP number to configure to AMUX6.
+ * @channel: Input channel to perform the ADC read.
+ * a) 'ADC_MPP_1_AMUX6' if the input voltage is less than 1.8V
+ * b) 'ADC_MPP_2_AMUX6' if the input voltage is greater then 1.8V
+ * the input voltage is pre-divided by 3 and passed to the ADC.
+ * The appropriate scaling function needs to be selected to let
+ * the driver know a post scaling is required before returning
+ * the result.
+ * @result: Structure pointer of type adc_chan_result
+ * in which the ADC read results are stored.
+ */
+uint32_t pm8xxx_adc_mpp_config_read(uint32_t mpp_num,
+ enum pm8xxx_adc_channels channel,
+ struct pm8xxx_adc_chan_result *result);
+/**
+ * pm8xxx_adc_btm_start() - Configure the BTM registers and start
+ monitoring the BATT_THERM channel for
+ threshold warm/cold temperature set
+ by the Battery client. The btm_start
+ api is to be used after calling the
+ pm8xxx_btm_configure() api which sets
+ the temperature thresholds, interval
+ and functions to call when warm/cold
+ events are triggered.
+ * @param: none.
+ */
+uint32_t pm8xxx_adc_btm_start(void);
+
+/**
+ * pm8xxx_adc_btm_end() - Configures the BTM registers to stop
+ * monitoring the BATT_THERM channel for
+ * warm/cold events and disables the
+ * interval timer.
+ * @param: none.
+ */
+uint32_t pm8xxx_adc_btm_end(void);
+
+/**
+ * pm8xxx_adc_btm_configure() - Configures the BATT_THERM channel
+ * parameters for warm/cold thresholds.
+ * Sets the interval timer for perfoming
+ * reading the temperature done by the HW.
+ * @btm_param: Structure pointer of type adc_arb_btm_param *
+ * which client provides for threshold warm/cold,
+ * interval and functions to call when warm/cold
+ * events are triggered.
+ */
+uint32_t pm8xxx_adc_btm_configure(struct pm8xxx_adc_arb_btm_param *);
+#else
+static inline uint32_t pm8xxx_adc_read(uint32_t channel,
+ struct pm8xxx_adc_chan_result *result)
+{ return -ENXIO; }
+static inline uint32_t pm8xxx_adc_mpp_config_read(uint32_t mpp_num,
+ enum pm8xxx_adc_channels channel,
+ struct pm8xxx_adc_chan_result *result)
+{ return -ENXIO; }
+static inline uint32_t pm8xxx_adc_btm_start(void)
+{ return -ENXIO; }
+static inline uint32_t pm8xxx_adc_btm_end(void)
+{ return -ENXIO; }
+static inline uint32_t pm8xxx_adc_btm_configure(
+ struct pm8xxx_adc_arb_btm_param *param)
+{ return -ENXIO; }
+#endif
+
+#endif /* PM8XXX_ADC_H */
diff --git a/include/linux/msm_mdp.h b/include/linux/msm_mdp.h
index 144caa0..a739761 100644
--- a/include/linux/msm_mdp.h
+++ b/include/linux/msm_mdp.h
@@ -165,6 +165,15 @@
uint16_t bv[MDP_BV_SIZE]; /* 1x3 bias vector */
};
+struct mdp_csc {
+ int id;
+ uint32_t csc_mv[9];
+ uint32_t csc_pre_bv[3];
+ uint32_t csc_post_bv[3];
+ uint32_t csc_pre_lv[6];
+ uint32_t csc_post_lv[6];
+};
+
/* The version of the mdp_blit_req structure so that
* user applications can selectively decide which functionality
* to include
diff --git a/include/linux/rq_stats.h b/include/linux/rq_stats.h
new file mode 100644
index 0000000..e04063f
--- /dev/null
+++ b/include/linux/rq_stats.h
@@ -0,0 +1,31 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+struct rq_data {
+ unsigned int rq_avg;
+ unsigned long rq_poll_jiffies;
+ unsigned long def_timer_jiffies;
+ unsigned long rq_poll_last_jiffy;
+ unsigned long rq_poll_total_jiffies;
+ unsigned long def_timer_last_jiffy;
+ unsigned int def_interval;
+ int64_t def_start_time;
+ struct attribute_group *attr_group;
+ struct kobject *kobj;
+ struct work_struct def_timer_work;
+ int init;
+};
+
+extern spinlock_t rq_lock;
+extern struct rq_data rq_info;
+extern struct workqueue_struct *rq_wq;
diff --git a/include/linux/usb/msm_hsusb.h b/include/linux/usb/msm_hsusb.h
index 1e158f5..d776718 100644
--- a/include/linux/usb/msm_hsusb.h
+++ b/include/linux/usb/msm_hsusb.h
@@ -237,4 +237,9 @@
#define PHY_OTG_COMP_DISABLED BIT(2)
};
+struct msm_hsic_host_platform_data {
+ unsigned strobe;
+ unsigned data;
+};
+
#endif
diff --git a/include/linux/usb/msm_hsusb_hw.h b/include/linux/usb/msm_hsusb_hw.h
index 55dc134..79b0415 100644
--- a/include/linux/usb/msm_hsusb_hw.h
+++ b/include/linux/usb/msm_hsusb_hw.h
@@ -38,6 +38,7 @@
#define ULPI_RUN (1 << 30)
#define ULPI_WRITE (1 << 29)
#define ULPI_READ (0 << 29)
+#define ULPI_SYNC_STATE (1 << 27)
#define ULPI_ADDR(n) (((n) & 255) << 16)
#define ULPI_DATA(n) ((n) & 255)
#define ULPI_DATA_READ(n) (((n) >> 8) & 255)
diff --git a/include/media/msm_camera.h b/include/media/msm_camera.h
index 4c9b53e..befd768 100644
--- a/include/media/msm_camera.h
+++ b/include/media/msm_camera.h
@@ -810,7 +810,9 @@
uint16_t y_output;
uint16_t line_length_pclk;
uint16_t frame_length_lines;
- uint32_t pixel_clk;
+ uint32_t vt_pixel_clk;
+ uint32_t op_pixel_clk;
+ uint16_t binning_factor;
};
struct sensor_output_info_t {
diff --git a/include/media/radio-iris.h b/include/media/radio-iris.h
index 37ec48a..359668b 100644
--- a/include/media/radio-iris.h
+++ b/include/media/radio-iris.h
@@ -41,6 +41,9 @@
#define RADIO_HCI_EVENT_PKT 0x14
/*HCI reponce packets*/
#define MAX_RIVA_PEEK_RSP_SIZE 251
+/* default data access */
+#define DEFAULT_DATA_OFFSET 2
+#define DEFAULT_DATA_SIZE 249
/* HCI timeouts */
#define RADIO_HCI_TIMEOUT (10000) /* 10 seconds */
@@ -292,11 +295,14 @@
struct hci_fm_def_data_rd_req {
__u8 mode;
__u8 length;
+ __u8 param_len;
+ __u8 param;
} __packed;
struct hci_fm_def_data_wr_req {
- struct hci_fm_def_data_rd_req data_rd;
- __u8 data[256];
+ __u8 mode;
+ __u8 length;
+ __u8 data[DEFAULT_DATA_SIZE];
} __packed;
struct hci_fm_riva_data {
@@ -447,7 +453,7 @@
struct hci_fm_data_rd_rsp {
__u8 status;
__u8 ret_data_len;
- __u8 data[256];
+ __u8 data[DEFAULT_DATA_SIZE];
} __packed;
struct hci_fm_feature_list_rsp {
@@ -540,6 +546,9 @@
V4L2_CID_PRIVATE_IRIS_TX_TONE,
V4L2_CID_PRIVATE_IRIS_RDS_GRP_COUNTERS,
V4L2_CID_PRIVATE_IRIS_SET_NOTCH_FILTER,/*0x8000028*/
+ V4L2_CID_PRIVATE_IRIS_READ_DEFAULT = 0x00980928,/*using private CIDs
+ under userclass*/
+ V4L2_CID_PRIVATE_IRIS_WRITE_DEFAULT,
};
@@ -606,6 +615,7 @@
IRIS_BUF_PEEK,
IRIS_BUF_SSBI_PEEK,
IRIS_BUF_RDS_CNTRS,
+ IRIS_BUF_RD_DEFAULT,
IRIS_BUF_MAX
};
@@ -702,6 +712,7 @@
#define RIVA_PEEK_PARAM 0x6
#define RIVA_PEEK_LEN_OFSET 0x6
#define SSBI_PEEK_LEN 0x01
+
int hci_def_data_read(struct hci_fm_def_data_rd_req *arg,
struct radio_hci_dev *hdev);
int hci_def_data_write(struct hci_fm_def_data_wr_req *arg,
diff --git a/include/media/tavarua.h b/include/media/tavarua.h
index ad9eafb..aafa5d0 100644
--- a/include/media/tavarua.h
+++ b/include/media/tavarua.h
@@ -145,7 +145,9 @@
* Here We have IOCTl's that are specifici to IRIS
* (V4L2_CID_PRIVATE_BASE+0x1D--V4L2_CID_PRIVATE_BASE+0x27)
*/
- V4L2_CID_PRIVATE_TAVARUA_SET_NOTCH_FILTER = V4L2_CID_PRIVATE_BASE + 0x28
+ V4L2_CID_PRIVATE_TAVARUA_SET_NOTCH_FILTER =
+ V4L2_CID_PRIVATE_BASE + 0x28,
+ V4L2_CID_PRIVATE_TAVARUA_SET_AUDIO_PATH
};
enum tavarua_buf_t {
@@ -305,6 +307,10 @@
RDS_AF_JUMP,
};
+enum audio_path {
+ FM_DIGITAL_PATH,
+ FM_ANALOG_PATH
+};
#define SRCH_MODE 0x07
#define SRCH_DIR 0x08 /* 0-up 1-down */
#define SCAN_DWELL 0x70
diff --git a/include/net/bluetooth/hci.h b/include/net/bluetooth/hci.h
index aa6aeb9..b67803a 100644
--- a/include/net/bluetooth/hci.h
+++ b/include/net/bluetooth/hci.h
@@ -708,6 +708,12 @@
__le16 sco_max_pkt;
} __packed;
+#define HCI_OP_WRITE_CURRENT_IAC_LAP 0x0c3a
+struct hci_cp_write_current_iac_lap {
+ __u8 num_current_iac;
+ __u8 lap[6];
+} __packed;
+
#define HCI_OP_WRITE_INQUIRY_MODE 0x0c45
#define HCI_MAX_EIR_LENGTH 240
diff --git a/include/net/bluetooth/l2cap.h b/include/net/bluetooth/l2cap.h
index 04f01b7..b98af28 100644
--- a/include/net/bluetooth/l2cap.h
+++ b/include/net/bluetooth/l2cap.h
@@ -648,6 +648,11 @@
#define L2CAP_AMP_STATE_WAIT_PREPARE 11
#define L2CAP_AMP_STATE_RESEGMENT 12
+#define L2CAP_ATT_ERROR 0x01
+#define L2CAP_ATT_RESPONSE_BIT 0x01
+#define L2CAP_ATT_INDICATE 0x1D
+#define L2CAP_ATT_NOT_SUPPORTED 0x06
+
#define __delta_seq(x, y, pi) ((x) >= (y) ? (x) - (y) : \
(pi)->tx_win_max + 1 - (y) + (x))
#define __next_seq(x, pi) ((x + 1) & ((pi)->tx_win_max))
diff --git a/include/net/bluetooth/mgmt.h b/include/net/bluetooth/mgmt.h
index 5e855dbf..208c157 100644
--- a/include/net/bluetooth/mgmt.h
+++ b/include/net/bluetooth/mgmt.h
@@ -90,6 +90,8 @@
__u8 major;
__u8 minor;
} __packed;
+#define MGMT_MAJOR_CLASS_MASK 0x1F
+#define MGMT_MAJOR_CLASS_LIMITED 0x20
#define MGMT_OP_SET_SERVICE_CACHE 0x000C
struct mgmt_cp_set_service_cache {
@@ -214,6 +216,8 @@
bdaddr_t bdaddr;
} __packed;
+#define MGMT_OP_SET_LIMIT_DISCOVERABLE 0x001F
+
#define MGMT_EV_CMD_COMPLETE 0x0001
struct mgmt_ev_cmd_complete {
__le16 opcode;
diff --git a/include/sound/apr_audio.h b/include/sound/apr_audio.h
index a241d14..0c109ae 100644
--- a/include/sound/apr_audio.h
+++ b/include/sound/apr_audio.h
@@ -847,7 +847,7 @@
#define ADPCM 0x00010BE7
#define YADPCM 0x00010BE8
#define MP3 0x00010BE9
-#define MPEG4_AAC 0x00010BEA
+#define MPEG4_AAC 0x00010D86
#define AMRNB_FS 0x00010BEB
#define V13K_FS 0x00010BED
#define EVRC_FS 0x00010BEE
diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c
index dc154f2..45e149c 100644
--- a/kernel/irq/chip.c
+++ b/kernel/irq/chip.c
@@ -396,7 +396,8 @@
* then mask it and get out of here:
*/
if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
- desc->istate |= IRQS_PENDING;
+ if (!irq_settings_is_level(desc))
+ desc->istate |= IRQS_PENDING;
mask_irq(desc);
goto out;
}
diff --git a/kernel/time/tick-sched.c b/kernel/time/tick-sched.c
index d5097c4..2480d18 100644
--- a/kernel/time/tick-sched.c
+++ b/kernel/time/tick-sched.c
@@ -20,11 +20,17 @@
#include <linux/profile.h>
#include <linux/sched.h>
#include <linux/module.h>
+#include <linux/rq_stats.h>
#include <asm/irq_regs.h>
#include "tick-internal.h"
+
+struct rq_data rq_info;
+struct workqueue_struct *rq_wq;
+spinlock_t rq_lock;
+
/*
* Per cpu nohz control structure
*/
@@ -711,6 +717,50 @@
* High resolution timer specific code
*/
#ifdef CONFIG_HIGH_RES_TIMERS
+static void update_rq_stats(void)
+{
+ unsigned long jiffy_gap = 0;
+ unsigned int rq_avg = 0;
+ unsigned long flags = 0;
+
+ jiffy_gap = jiffies - rq_info.rq_poll_last_jiffy;
+
+ if (jiffy_gap >= rq_info.rq_poll_jiffies) {
+
+ spin_lock_irqsave(&rq_lock, flags);
+
+ if (!rq_info.rq_avg)
+ rq_info.rq_poll_total_jiffies = 0;
+
+ rq_avg = nr_running() * 10;
+
+ if (rq_info.rq_poll_total_jiffies) {
+ rq_avg = (rq_avg * jiffy_gap) +
+ (rq_info.rq_avg *
+ rq_info.rq_poll_total_jiffies);
+ do_div(rq_avg,
+ rq_info.rq_poll_total_jiffies + jiffy_gap);
+ }
+
+ rq_info.rq_avg = rq_avg;
+ rq_info.rq_poll_total_jiffies += jiffy_gap;
+ rq_info.rq_poll_last_jiffy = jiffies;
+
+ spin_unlock_irqrestore(&rq_lock, flags);
+ }
+}
+
+static void wakeup_user(void)
+{
+ unsigned long jiffy_gap;
+
+ jiffy_gap = jiffies - rq_info.def_timer_last_jiffy;
+
+ if (jiffy_gap >= rq_info.def_timer_jiffies) {
+ rq_info.def_timer_last_jiffy = jiffies;
+ queue_work(rq_wq, &rq_info.def_timer_work);
+ }
+}
/*
* We rearm the timer until we get disabled by the idle code.
* Called with interrupts disabled and timer->base->cpu_base->lock held.
@@ -758,6 +808,20 @@
}
update_process_times(user_mode(regs));
profile_tick(CPU_PROFILING);
+
+
+ if ((rq_info.init == 1) && (cpu == 0)) {
+
+ /*
+ * update run queue statistics
+ */
+ update_rq_stats();
+
+ /*
+ * wakeup user if needed
+ */
+ wakeup_user();
+ }
}
hrtimer_forward(timer, now, tick_period);
diff --git a/net/bluetooth/l2cap_core.c b/net/bluetooth/l2cap_core.c
index dea21c1..c21eb88 100644
--- a/net/bluetooth/l2cap_core.c
+++ b/net/bluetooth/l2cap_core.c
@@ -7081,6 +7081,10 @@
static inline int l2cap_att_channel(struct l2cap_conn *conn, __le16 cid, struct sk_buff *skb)
{
struct sock *sk;
+ struct sk_buff *skb_rsp;
+ struct l2cap_hdr *lh;
+ u8 err_rsp[] = {L2CAP_ATT_ERROR, 0x00, 0x00, 0x00,
+ L2CAP_ATT_NOT_SUPPORTED};
sk = l2cap_get_sock_by_fixed_scid(0, cid, conn->src, conn->dst);
if (!sk)
@@ -7100,6 +7104,25 @@
goto done;
drop:
+ if (skb->data[0] & L2CAP_ATT_RESPONSE_BIT &&
+ skb->data[0] != L2CAP_ATT_INDICATE)
+ goto free_skb;
+
+ /* If this is an incoming PDU that requires a response, respond with
+ * a generic error so remote device doesn't hang */
+
+ skb_rsp = bt_skb_alloc(sizeof(err_rsp) + L2CAP_HDR_SIZE, GFP_ATOMIC);
+ if (!skb_rsp)
+ goto free_skb;
+
+ lh = (struct l2cap_hdr *) skb_put(skb_rsp, L2CAP_HDR_SIZE);
+ lh->len = cpu_to_le16(sizeof(err_rsp));
+ lh->cid = cpu_to_le16(L2CAP_CID_LE_DATA);
+ err_rsp[1] = skb->data[0];
+ memcpy(skb_put(skb_rsp, sizeof(err_rsp)), err_rsp, sizeof(err_rsp));
+ hci_send_acl(conn->hcon, NULL, skb_rsp, 0);
+
+free_skb:
kfree_skb(skb);
done:
diff --git a/net/bluetooth/mgmt.c b/net/bluetooth/mgmt.c
index a328db9..ea72708 100644
--- a/net/bluetooth/mgmt.c
+++ b/net/bluetooth/mgmt.c
@@ -409,6 +409,124 @@
return err;
}
+static u8 get_service_classes(struct hci_dev *hdev)
+{
+ struct list_head *p;
+ u8 val = 0;
+
+ list_for_each(p, &hdev->uuids) {
+ struct bt_uuid *uuid = list_entry(p, struct bt_uuid, list);
+
+ val |= uuid->svc_hint;
+ }
+
+ return val;
+}
+
+static int update_class(struct hci_dev *hdev)
+{
+ u8 cod[3];
+
+ BT_DBG("%s", hdev->name);
+
+ if (test_bit(HCI_SERVICE_CACHE, &hdev->flags))
+ return 0;
+
+ cod[0] = hdev->minor_class;
+ cod[1] = hdev->major_class;
+ cod[2] = get_service_classes(hdev);
+
+ if (memcmp(cod, hdev->dev_class, 3) == 0)
+ return 0;
+
+ return hci_send_cmd(hdev, HCI_OP_WRITE_CLASS_OF_DEV, sizeof(cod), cod);
+}
+
+static int set_limited_discoverable(struct sock *sk, u16 index,
+ unsigned char *data, u16 len)
+{
+ struct mgmt_mode *cp;
+ struct hci_dev *hdev;
+ struct pending_cmd *cmd;
+ struct hci_cp_write_current_iac_lap dcp;
+ int update_cod;
+ int err = 0;
+ /* General Inquiry LAP: 0x9E8B33, Limited Inquiry LAP: 0x9E8B00 */
+ u8 lap[] = { 0x33, 0x8b, 0x9e, 0x00, 0x8b, 0x9e };
+
+ cp = (void *) data;
+
+ BT_DBG("hci%u discoverable: %d", index, cp->val);
+
+ if (!cp || len != sizeof(*cp))
+ return cmd_status(sk, index, MGMT_OP_SET_LIMIT_DISCOVERABLE,
+ EINVAL);
+
+ hdev = hci_dev_get(index);
+ if (!hdev)
+ return cmd_status(sk, index, MGMT_OP_SET_LIMIT_DISCOVERABLE,
+ ENODEV);
+
+ hci_dev_lock(hdev);
+
+ if (!test_bit(HCI_UP, &hdev->flags)) {
+ err = cmd_status(sk, index, MGMT_OP_SET_LIMIT_DISCOVERABLE,
+ ENETDOWN);
+ goto failed;
+ }
+
+ if (mgmt_pending_find(MGMT_OP_SET_LIMIT_DISCOVERABLE, index)) {
+ err = cmd_status(sk, index, MGMT_OP_SET_LIMIT_DISCOVERABLE,
+ EBUSY);
+ goto failed;
+ }
+
+ if (cp->val == test_bit(HCI_ISCAN, &hdev->flags) &&
+ test_bit(HCI_PSCAN, &hdev->flags)) {
+ err = cmd_status(sk, index, MGMT_OP_SET_LIMIT_DISCOVERABLE,
+ EALREADY);
+ goto failed;
+ }
+
+ cmd = mgmt_pending_add(sk, MGMT_OP_SET_LIMIT_DISCOVERABLE, index, data,
+ len);
+ if (!cmd) {
+ err = -ENOMEM;
+ goto failed;
+ }
+
+ memset(&dcp, 0, sizeof(dcp));
+ dcp.num_current_iac = cp->val ? 2 : 1;
+ memcpy(&dcp.lap, lap, dcp.num_current_iac * 3);
+ update_cod = 1;
+
+ if (cp->val) {
+ if (hdev->major_class & MGMT_MAJOR_CLASS_LIMITED)
+ update_cod = 0;
+ hdev->major_class |= MGMT_MAJOR_CLASS_LIMITED;
+ } else {
+ if (!(hdev->major_class & MGMT_MAJOR_CLASS_LIMITED))
+ update_cod = 0;
+ hdev->major_class &= ~MGMT_MAJOR_CLASS_LIMITED;
+ }
+
+ if (update_cod)
+ err = update_class(hdev);
+
+ if (err >= 0)
+ err = hci_send_cmd(hdev, HCI_OP_WRITE_CURRENT_IAC_LAP,
+ sizeof(dcp), &dcp);
+
+ if (err < 0)
+ mgmt_pending_remove(cmd);
+
+failed:
+ hci_dev_unlock(hdev);
+ hci_dev_put(hdev);
+
+ return err;
+}
+
static int set_discoverable(struct sock *sk, u16 index, unsigned char *data,
u16 len)
{
@@ -751,39 +869,6 @@
return hci_send_cmd(hdev, HCI_OP_WRITE_EIR, sizeof(cp), &cp);
}
-static u8 get_service_classes(struct hci_dev *hdev)
-{
- struct list_head *p;
- u8 val = 0;
-
- list_for_each(p, &hdev->uuids) {
- struct bt_uuid *uuid = list_entry(p, struct bt_uuid, list);
-
- val |= uuid->svc_hint;
- }
-
- return val;
-}
-
-static int update_class(struct hci_dev *hdev)
-{
- u8 cod[3];
-
- BT_DBG("%s", hdev->name);
-
- if (test_bit(HCI_SERVICE_CACHE, &hdev->flags))
- return 0;
-
- cod[0] = hdev->minor_class;
- cod[1] = hdev->major_class;
- cod[2] = get_service_classes(hdev);
-
- if (memcmp(cod, hdev->dev_class, 3) == 0)
- return 0;
-
- return hci_send_cmd(hdev, HCI_OP_WRITE_CLASS_OF_DEV, sizeof(cod), cod);
-}
-
static int add_uuid(struct sock *sk, u16 index, unsigned char *data, u16 len)
{
struct mgmt_cp_add_uuid *cp;
@@ -912,7 +997,8 @@
hci_dev_lock(hdev);
- hdev->major_class = cp->major;
+ hdev->major_class &= ~MGMT_MAJOR_CLASS_MASK;
+ hdev->major_class |= cp->major & MGMT_MAJOR_CLASS_MASK;
hdev->minor_class = cp->minor;
err = update_class(hdev);
@@ -2111,6 +2197,10 @@
case MGMT_OP_SET_DISCOVERABLE:
err = set_discoverable(sk, index, buf + sizeof(*hdr), len);
break;
+ case MGMT_OP_SET_LIMIT_DISCOVERABLE:
+ err = set_limited_discoverable(sk, index, buf + sizeof(*hdr),
+ len);
+ break;
case MGMT_OP_SET_CONNECTABLE:
err = set_connectable(sk, index, buf + sizeof(*hdr), len);
break;
diff --git a/sound/soc/codecs/wcd9310.c b/sound/soc/codecs/wcd9310.c
index ec31c0f..649f219 100644
--- a/sound/soc/codecs/wcd9310.c
+++ b/sound/soc/codecs/wcd9310.c
@@ -47,6 +47,14 @@
TABLA_BANDGAP_MBHC_MODE,
};
+struct mbhc_micbias_regs {
+ u16 cfilt_val;
+ u16 cfilt_ctl;
+ u16 mbhc_reg;
+ u16 int_rbias;
+ u16 ctl_reg;
+};
+
struct tabla_priv {
struct snd_soc_codec *codec;
u32 adc_count;
@@ -72,6 +80,10 @@
bool no_mic_headset_override;
/* Delayed work to report long button press */
struct delayed_work btn0_dwork;
+
+ struct mbhc_micbias_regs mbhc_bias_regs;
+ u8 cfilt_k_value;
+ bool mbhc_micbias_switched;
};
#ifdef CONFIG_DEBUG_FS
@@ -179,6 +191,62 @@
SOC_ENUM_SINGLE_EXT(2, tabla_ear_pa_gain_text),
};
+/*cut of frequency for high pass filter*/
+static const char *cf_text[] = {
+ "MIN_3DB_4Hz", "MIN_3DB_75Hz", "MIN_3DB_150Hz"
+};
+
+static const struct soc_enum cf_dec1_enum =
+ SOC_ENUM_SINGLE(TABLA_A_CDC_TX1_MUX_CTL, 4, 3, cf_text);
+
+static const struct soc_enum cf_dec2_enum =
+ SOC_ENUM_SINGLE(TABLA_A_CDC_TX2_MUX_CTL, 4, 3, cf_text);
+
+static const struct soc_enum cf_dec3_enum =
+ SOC_ENUM_SINGLE(TABLA_A_CDC_TX3_MUX_CTL, 4, 3, cf_text);
+
+static const struct soc_enum cf_dec4_enum =
+ SOC_ENUM_SINGLE(TABLA_A_CDC_TX4_MUX_CTL, 4, 3, cf_text);
+
+static const struct soc_enum cf_dec5_enum =
+ SOC_ENUM_SINGLE(TABLA_A_CDC_TX5_MUX_CTL, 4, 3, cf_text);
+
+static const struct soc_enum cf_dec6_enum =
+ SOC_ENUM_SINGLE(TABLA_A_CDC_TX6_MUX_CTL, 4, 3, cf_text);
+
+static const struct soc_enum cf_dec7_enum =
+ SOC_ENUM_SINGLE(TABLA_A_CDC_TX7_MUX_CTL, 4, 3, cf_text);
+
+static const struct soc_enum cf_dec8_enum =
+ SOC_ENUM_SINGLE(TABLA_A_CDC_TX8_MUX_CTL, 4, 3, cf_text);
+
+static const struct soc_enum cf_dec9_enum =
+ SOC_ENUM_SINGLE(TABLA_A_CDC_TX9_MUX_CTL, 4, 3, cf_text);
+
+static const struct soc_enum cf_dec10_enum =
+ SOC_ENUM_SINGLE(TABLA_A_CDC_TX10_MUX_CTL, 4, 3, cf_text);
+
+static const struct soc_enum cf_rxmix1_enum =
+ SOC_ENUM_SINGLE(TABLA_A_CDC_RX1_B4_CTL, 1, 3, cf_text);
+
+static const struct soc_enum cf_rxmix2_enum =
+ SOC_ENUM_SINGLE(TABLA_A_CDC_RX2_B4_CTL, 1, 3, cf_text);
+
+static const struct soc_enum cf_rxmix3_enum =
+ SOC_ENUM_SINGLE(TABLA_A_CDC_RX3_B4_CTL, 1, 3, cf_text);
+
+static const struct soc_enum cf_rxmix4_enum =
+ SOC_ENUM_SINGLE(TABLA_A_CDC_RX4_B4_CTL, 1, 3, cf_text);
+
+static const struct soc_enum cf_rxmix5_enum =
+ SOC_ENUM_SINGLE(TABLA_A_CDC_RX5_B4_CTL, 1, 3, cf_text)
+;
+static const struct soc_enum cf_rxmix6_enum =
+ SOC_ENUM_SINGLE(TABLA_A_CDC_RX6_B4_CTL, 1, 3, cf_text);
+
+static const struct soc_enum cf_rxmix7_enum =
+ SOC_ENUM_SINGLE(TABLA_A_CDC_RX7_B4_CTL, 1, 3, cf_text);
+
static const struct snd_kcontrol_new tabla_snd_controls[] = {
SOC_ENUM_EXT("EAR PA Gain", tabla_ear_pa_gain_enum[0],
@@ -261,6 +329,43 @@
SOC_SINGLE_EXT("ANC Slot", SND_SOC_NOPM, 0, 0, 100, tabla_get_anc_slot,
tabla_put_anc_slot),
+ SOC_ENUM("TX1 HPF cut off", cf_dec1_enum),
+ SOC_ENUM("TX2 HPF cut off", cf_dec2_enum),
+ SOC_ENUM("TX3 HPF cut off", cf_dec3_enum),
+ SOC_ENUM("TX4 HPF cut off", cf_dec4_enum),
+ SOC_ENUM("TX5 HPF cut off", cf_dec5_enum),
+ SOC_ENUM("TX6 HPF cut off", cf_dec6_enum),
+ SOC_ENUM("TX7 HPF cut off", cf_dec7_enum),
+ SOC_ENUM("TX8 HPF cut off", cf_dec8_enum),
+ SOC_ENUM("TX9 HPF cut off", cf_dec9_enum),
+ SOC_ENUM("TX10 HPF cut off", cf_dec10_enum),
+
+ SOC_SINGLE("TX1 HPF Switch", TABLA_A_CDC_TX1_MUX_CTL, 3, 1, 0),
+ SOC_SINGLE("TX2 HPF Switch", TABLA_A_CDC_TX2_MUX_CTL, 3, 1, 0),
+ SOC_SINGLE("TX3 HPF Switch", TABLA_A_CDC_TX3_MUX_CTL, 3, 1, 0),
+ SOC_SINGLE("TX4 HPF Switch", TABLA_A_CDC_TX4_MUX_CTL, 3, 1, 0),
+ SOC_SINGLE("TX5 HPF Switch", TABLA_A_CDC_TX5_MUX_CTL, 3, 1, 0),
+ SOC_SINGLE("TX6 HPF Switch", TABLA_A_CDC_TX6_MUX_CTL, 3, 1, 0),
+ SOC_SINGLE("TX7 HPF Switch", TABLA_A_CDC_TX7_MUX_CTL, 3, 1, 0),
+ SOC_SINGLE("TX8 HPF Switch", TABLA_A_CDC_TX8_MUX_CTL, 3, 1, 0),
+ SOC_SINGLE("TX9 HPF Switch", TABLA_A_CDC_TX9_MUX_CTL, 3, 1, 0),
+ SOC_SINGLE("TX10 HPF Switch", TABLA_A_CDC_TX10_MUX_CTL, 3, 1, 0),
+
+ SOC_SINGLE("RX1 HPF Switch", TABLA_A_CDC_RX1_B5_CTL, 2, 1, 0),
+ SOC_SINGLE("RX2 HPF Switch", TABLA_A_CDC_RX2_B5_CTL, 2, 1, 0),
+ SOC_SINGLE("RX3 HPF Switch", TABLA_A_CDC_RX3_B5_CTL, 2, 1, 0),
+ SOC_SINGLE("RX4 HPF Switch", TABLA_A_CDC_RX4_B5_CTL, 2, 1, 0),
+ SOC_SINGLE("RX5 HPF Switch", TABLA_A_CDC_RX5_B5_CTL, 2, 1, 0),
+ SOC_SINGLE("RX6 HPF Switch", TABLA_A_CDC_RX6_B5_CTL, 2, 1, 0),
+ SOC_SINGLE("RX7 HPF Switch", TABLA_A_CDC_RX7_B5_CTL, 2, 1, 0),
+
+ SOC_ENUM("RX1 HPF cut off", cf_rxmix1_enum),
+ SOC_ENUM("RX2 HPF cut off", cf_rxmix2_enum),
+ SOC_ENUM("RX3 HPF cut off", cf_rxmix3_enum),
+ SOC_ENUM("RX4 HPF cut off", cf_rxmix4_enum),
+ SOC_ENUM("RX5 HPF cut off", cf_rxmix5_enum),
+ SOC_ENUM("RX6 HPF cut off", cf_rxmix6_enum),
+ SOC_ENUM("RX7 HPF cut off", cf_rxmix7_enum),
};
static const char *rx_mix1_text[] = {
@@ -907,6 +1012,103 @@
}
}
+static int tabla_find_k_value(unsigned int ldoh_v, unsigned int cfilt_mv)
+{
+ int rc = -EINVAL;
+ unsigned min_mv, max_mv;
+
+ switch (ldoh_v) {
+ case TABLA_LDOH_1P95_V:
+ min_mv = 160;
+ max_mv = 1800;
+ break;
+ case TABLA_LDOH_2P35_V:
+ min_mv = 200;
+ max_mv = 2200;
+ break;
+ case TABLA_LDOH_2P75_V:
+ min_mv = 240;
+ max_mv = 2600;
+ break;
+ case TABLA_LDOH_2P85_V:
+ min_mv = 250;
+ max_mv = 2700;
+ break;
+ default:
+ goto done;
+ }
+
+ if (cfilt_mv < min_mv || cfilt_mv > max_mv)
+ goto done;
+
+ for (rc = 4; rc <= 44; rc++) {
+ min_mv = max_mv * (rc) / 44;
+ if (min_mv >= cfilt_mv) {
+ rc -= 4;
+ break;
+ }
+ }
+done:
+ return rc;
+}
+
+static bool tabla_is_hph_pa_on(struct snd_soc_codec *codec)
+{
+ u8 hph_reg_val = 0;
+ hph_reg_val = snd_soc_read(codec, TABLA_A_RX_HPH_CNP_EN);
+
+ return (hph_reg_val & 0x30) ? true : false;
+}
+
+static void tabla_codec_switch_micbias(struct snd_soc_codec *codec,
+ int vddio_switch)
+{
+ struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
+ int cfilt_k_val;
+
+ switch (vddio_switch) {
+ case 1:
+ if (tabla->mbhc_polling_active) {
+ /* Enable Mic Bias switch to VDDIO */
+ tabla->cfilt_k_value = snd_soc_read(codec,
+ tabla->mbhc_bias_regs.cfilt_val);
+ cfilt_k_val = tabla_find_k_value(
+ tabla->pdata->micbias.ldoh_v, 1800);
+ snd_soc_update_bits(codec,
+ tabla->mbhc_bias_regs.cfilt_val,
+ 0xFC, (cfilt_k_val << 2));
+
+ snd_soc_update_bits(codec,
+ tabla->mbhc_bias_regs.mbhc_reg, 0x80, 0x80);
+ snd_soc_update_bits(codec,
+ tabla->mbhc_bias_regs.mbhc_reg, 0x10, 0x00);
+
+ tabla->mbhc_micbias_switched = true;
+ pr_debug("%s: Enabled MBHC Mic bias to VDDIO Switch\n",
+ __func__);
+ }
+ break;
+
+ case 0:
+ if (tabla->mbhc_micbias_switched) {
+ /* Disable Mic Bias switch to VDDIO */
+ if (tabla->cfilt_k_value != 0)
+ snd_soc_update_bits(codec,
+ tabla->mbhc_bias_regs.cfilt_val, 0XFC,
+ tabla->cfilt_k_value);
+ snd_soc_update_bits(codec,
+ tabla->mbhc_bias_regs.mbhc_reg, 0x80, 0x00);
+ snd_soc_update_bits(codec,
+ tabla->mbhc_bias_regs.mbhc_reg, 0x10, 0x00);
+
+ tabla->mbhc_micbias_switched = false;
+ pr_debug("%s: Disabled MBHC Mic bias to VDDIO Switch\n",
+ __func__);
+ }
+ break;
+ }
+}
+
static int tabla_codec_enable_micbias(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
@@ -948,6 +1150,11 @@
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
+ /* Decide whether to switch the micbias for MBHC */
+ if ((w->reg == tabla->mbhc_bias_regs.ctl_reg)
+ && tabla->mbhc_micbias_switched)
+ tabla_codec_switch_micbias(codec, 0);
+
snd_soc_update_bits(codec, w->reg, 0x0E, 0x0A);
tabla_codec_update_cfilt_usage(codec, cfilt_sel_val, 1);
@@ -966,7 +1173,13 @@
tabla_codec_start_hs_polling(codec);
}
break;
+
case SND_SOC_DAPM_POST_PMD:
+
+ if ((w->reg == tabla->mbhc_bias_regs.ctl_reg)
+ && tabla_is_hph_pa_on(codec))
+ tabla_codec_switch_micbias(codec, 1);
+
if (strnstr(w->name, internal1_text, 30))
snd_soc_update_bits(codec, micb_int_reg, 0x80, 0x00);
else if (strnstr(w->name, internal2_text, 30))
@@ -1072,16 +1285,30 @@
return 0;
}
-
static int tabla_hph_pa_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
-
+ struct snd_soc_codec *codec = w->codec;
+ struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
+ u8 mbhc_micb_ctl_val;
pr_debug("%s: event = %d\n", __func__, event);
switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ mbhc_micb_ctl_val = snd_soc_read(codec,
+ tabla->mbhc_bias_regs.ctl_reg);
+
+ if (!(mbhc_micb_ctl_val & 0x80)
+ && !tabla->mbhc_micbias_switched)
+ tabla_codec_switch_micbias(codec, 1);
+
+ break;
+
case SND_SOC_DAPM_POST_PMD:
+ if (tabla->mbhc_micbias_switched)
+ tabla_codec_switch_micbias(codec, 0);
+
pr_debug("%s: sleep 10 ms after %s PA disable.\n", __func__,
w->name);
usleep_range(10000, 10000);
@@ -1091,6 +1318,59 @@
return 0;
}
+static void tabla_get_mbhc_micbias_regs(struct snd_soc_codec *codec,
+ struct mbhc_micbias_regs *micbias_regs)
+{
+ struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
+ struct tabla_mbhc_calibration *calibration = tabla->calibration;
+ unsigned int cfilt;
+
+ switch (calibration->bias) {
+ case TABLA_MICBIAS1:
+ cfilt = tabla->pdata->micbias.bias1_cfilt_sel;
+ micbias_regs->mbhc_reg = TABLA_A_MICB_1_MBHC;
+ micbias_regs->int_rbias = TABLA_A_MICB_1_INT_RBIAS;
+ micbias_regs->ctl_reg = TABLA_A_MICB_1_CTL;
+ break;
+ case TABLA_MICBIAS2:
+ cfilt = tabla->pdata->micbias.bias2_cfilt_sel;
+ micbias_regs->mbhc_reg = TABLA_A_MICB_2_MBHC;
+ micbias_regs->int_rbias = TABLA_A_MICB_2_INT_RBIAS;
+ micbias_regs->ctl_reg = TABLA_A_MICB_2_CTL;
+ break;
+ case TABLA_MICBIAS3:
+ cfilt = tabla->pdata->micbias.bias3_cfilt_sel;
+ micbias_regs->mbhc_reg = TABLA_A_MICB_3_MBHC;
+ micbias_regs->int_rbias = TABLA_A_MICB_3_INT_RBIAS;
+ micbias_regs->ctl_reg = TABLA_A_MICB_3_CTL;
+ break;
+ case TABLA_MICBIAS4:
+ cfilt = tabla->pdata->micbias.bias4_cfilt_sel;
+ micbias_regs->mbhc_reg = TABLA_A_MICB_4_MBHC;
+ micbias_regs->int_rbias = TABLA_A_MICB_4_INT_RBIAS;
+ micbias_regs->ctl_reg = TABLA_A_MICB_4_CTL;
+ break;
+ default:
+ /* Should never reach here */
+ pr_err("%s: Invalid MIC BIAS for MBHC\n", __func__);
+ }
+
+ switch (cfilt) {
+ case TABLA_CFILT1_SEL:
+ micbias_regs->cfilt_val = TABLA_A_MICB_CFILT_1_VAL;
+ micbias_regs->cfilt_ctl = TABLA_A_MICB_CFILT_1_CTL;
+ break;
+ case TABLA_CFILT2_SEL:
+ micbias_regs->cfilt_val = TABLA_A_MICB_CFILT_2_VAL;
+ micbias_regs->cfilt_ctl = TABLA_A_MICB_CFILT_2_CTL;
+ break;
+ case TABLA_CFILT3_SEL:
+ micbias_regs->cfilt_val = TABLA_A_MICB_CFILT_3_VAL;
+ micbias_regs->cfilt_ctl = TABLA_A_MICB_CFILT_3_CTL;
+ break;
+ }
+}
+
static const struct snd_soc_dapm_widget tabla_dapm_widgets[] = {
/*RX stuff */
SND_SOC_DAPM_OUTPUT("EAR"),
@@ -1106,14 +1386,14 @@
/* Headphone */
SND_SOC_DAPM_OUTPUT("HEADPHONE"),
SND_SOC_DAPM_PGA_E("HPHL", TABLA_A_RX_HPH_CNP_EN, 5, 0, NULL, 0,
- tabla_hph_pa_event, SND_SOC_DAPM_POST_PMD),
-
+ tabla_hph_pa_event, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER("HPHL DAC", TABLA_A_RX_HPH_L_DAC_CTL, 7, 0,
hphl_switch, ARRAY_SIZE(hphl_switch)),
SND_SOC_DAPM_PGA_E("HPHR", TABLA_A_RX_HPH_CNP_EN, 4, 0, NULL, 0,
- tabla_hph_pa_event, SND_SOC_DAPM_POST_PMD),
-
+ tabla_hph_pa_event, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER("HPHR DAC", TABLA_A_RX_HPH_R_DAC_CTL, 7, 0,
hphr_switch, ARRAY_SIZE(hphr_switch)),
@@ -1748,9 +2028,11 @@
static void tabla_codec_calibrate_hs_polling(struct snd_soc_codec *codec)
{
/* TODO store register values in calibration */
+ snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B5_CTL, 0x20);
+ snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B6_CTL, 0xFF);
snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B10_CTL, 0xFF);
- snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B9_CTL, 0x00);
+ snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B9_CTL, 0x20);
snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B4_CTL, 0x08);
snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B3_CTL, 0xEE);
@@ -1823,21 +2105,6 @@
return 0;
}
-static int tabla_digital_mute(struct snd_soc_dai *codec_dai, int mute)
-{
- struct snd_soc_codec *codec = codec_dai->codec;
-
- pr_debug("%s %d\n", __func__, mute);
-
- /* TODO mute TX */
- if (mute)
- snd_soc_update_bits(codec, TABLA_A_CDC_RX1_B6_CTL, 0x01, 0x01);
- else
- snd_soc_update_bits(codec, TABLA_A_CDC_RX1_B6_CTL, 0x01, 0x00);
-
- return 0;
-}
-
static int tabla_set_dai_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
@@ -1948,7 +2215,6 @@
.hw_params = tabla_hw_params,
.set_sysclk = tabla_set_dai_sysclk,
.set_fmt = tabla_set_dai_fmt,
- .digital_mute = tabla_digital_mute,
};
static struct snd_soc_dai_driver tabla_dai[] = {
@@ -2035,10 +2301,7 @@
{
struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
struct tabla_mbhc_calibration *calibration = tabla->calibration;
- int micbias_ctl_reg, micbias_cfilt_ctl_reg,
- micbias_mbhc_reg;
short bias_value;
- unsigned int cfilt_sel;
if (!calibration) {
pr_err("Error, no tabla calibration\n");
@@ -2057,49 +2320,12 @@
snd_soc_update_bits(codec, TABLA_A_TX_COM_BIAS, 0xE0, 0xE0);
- /* select cfilt separately from the micbias line in the platform data */
- switch (calibration->bias) {
- case TABLA_MICBIAS1:
- micbias_ctl_reg = TABLA_A_MICB_1_CTL;
- cfilt_sel = tabla->pdata->micbias.bias1_cfilt_sel;
- micbias_mbhc_reg = TABLA_A_MICB_1_MBHC;
- break;
- case TABLA_MICBIAS2:
- micbias_ctl_reg = TABLA_A_MICB_2_CTL;
- cfilt_sel = tabla->pdata->micbias.bias2_cfilt_sel;
- micbias_mbhc_reg = TABLA_A_MICB_2_MBHC;
- break;
- case TABLA_MICBIAS3:
- micbias_ctl_reg = TABLA_A_MICB_3_CTL;
- cfilt_sel = tabla->pdata->micbias.bias3_cfilt_sel;
- micbias_mbhc_reg = TABLA_A_MICB_3_MBHC;
- break;
- case TABLA_MICBIAS4:
- pr_err("%s: Error, microphone bias 4 not supported\n",
- __func__);
- return -EINVAL;
- default:
- pr_err("Error, invalid mic bias line\n");
- return -EINVAL;
- }
- switch (cfilt_sel) {
- case TABLA_CFILT1_SEL:
- micbias_cfilt_ctl_reg = TABLA_A_MICB_CFILT_1_CTL;
- break;
- case TABLA_CFILT2_SEL:
- micbias_cfilt_ctl_reg = TABLA_A_MICB_CFILT_2_CTL;
- break;
- case TABLA_CFILT3_SEL:
- micbias_cfilt_ctl_reg = TABLA_A_MICB_CFILT_3_CTL;
- break;
- default: /* default should not happen as check should have been done */
- return -EINVAL;
- }
+ snd_soc_update_bits(codec,
+ tabla->mbhc_bias_regs.cfilt_ctl, 0x70, 0x00);
- snd_soc_update_bits(codec, micbias_cfilt_ctl_reg, 0x70, 0x00);
-
- snd_soc_update_bits(codec, micbias_ctl_reg, 0x1F, 0x16);
+ snd_soc_update_bits(codec,
+ tabla->mbhc_bias_regs.ctl_reg, 0x1F, 0x16);
snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_CLK_CTL, 0x2, 0x2);
snd_soc_write(codec, TABLA_A_MBHC_SCALING_MUX_1, 0x84);
@@ -2115,13 +2341,11 @@
snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_B1_CTL, 0x6, 0x6);
snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_CLK_CTL, 0x8, 0x8);
- snd_soc_update_bits(codec, micbias_mbhc_reg, 0x10, 0x10);
- snd_soc_update_bits(codec, TABLA_A_MBHC_HPH, 0x13, 0x01);
-
tabla_codec_calibrate_hs_polling(codec);
bias_value = tabla_codec_measure_micbias_voltage(codec, 0);
- snd_soc_update_bits(codec, micbias_cfilt_ctl_reg, 0x40, 0x40);
+ snd_soc_update_bits(codec,
+ tabla->mbhc_bias_regs.cfilt_ctl, 0x40, 0x40);
snd_soc_update_bits(codec, TABLA_A_MBHC_HPH, 0x13, 0x00);
return bias_value;
@@ -2133,7 +2357,6 @@
struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
struct tabla_mbhc_calibration *calibration = tabla->calibration;
int central_bias_enabled = 0;
- int micbias_int_reg, micbias_ctl_reg, micbias_mbhc_reg;
if (!calibration) {
pr_err("Error, no tabla calibration\n");
@@ -2142,10 +2365,45 @@
snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_INT_CTL, 0x1, 0);
- if (insertion)
+ if (insertion) {
+ /* Make sure mic bias and Mic line schmitt trigger
+ * are turned OFF
+ */
+ snd_soc_update_bits(codec, tabla->mbhc_bias_regs.ctl_reg,
+ 0x81, 0x01);
+ snd_soc_update_bits(codec, tabla->mbhc_bias_regs.mbhc_reg,
+ 0x90, 0x00);
+
+ /* Enable HPH Schmitt Trigger */
+ snd_soc_update_bits(codec, TABLA_A_MBHC_HPH, 0x13, 0x13);
+ snd_soc_update_bits(codec, TABLA_A_MBHC_HPH, 0x0C,
+ calibration->hph_current << 2);
+
+ /* Turn off HPH PAs during insertion detection to avoid false
+ * insertion interrupts
+ */
+ if (tabla->mbhc_micbias_switched)
+ tabla_codec_switch_micbias(codec, 0);
+ snd_soc_update_bits(codec, TABLA_A_RX_HPH_CNP_EN, 0x30, 0x00);
+
+ /* setup for insetion detection */
snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_INT_CTL, 0x2, 0);
- else
+ } else {
+ /* Make sure the HPH schmitt trigger is OFF */
+ snd_soc_update_bits(codec, TABLA_A_MBHC_HPH, 0x12, 0x00);
+
+ /* enable the mic line schmitt trigger */
+ snd_soc_update_bits(codec, tabla->mbhc_bias_regs.mbhc_reg, 0x60,
+ calibration->mic_current << 5);
+ snd_soc_update_bits(codec, tabla->mbhc_bias_regs.mbhc_reg,
+ 0x80, 0x80);
+ usleep_range(calibration->mic_pid, calibration->mic_pid);
+ snd_soc_update_bits(codec, tabla->mbhc_bias_regs.mbhc_reg,
+ 0x10, 0x10);
+
+ /* Setup for low power removal detection */
snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_INT_CTL, 0x2, 0x2);
+ }
if (snd_soc_read(codec, TABLA_A_CDC_MBHC_B1_CTL) & 0x4) {
if (!(tabla->clock_active)) {
@@ -2160,42 +2418,7 @@
0x06, 0);
}
- snd_soc_update_bits(codec, TABLA_A_MBHC_HPH, 0xC,
- calibration->hph_current << 2);
-
- /* Turn off HPH PAs during insertion detection to avoid false
- * insertion interrupts
- */
- snd_soc_update_bits(codec, TABLA_A_RX_HPH_CNP_EN, 0x30, 0x00);
- snd_soc_update_bits(codec, TABLA_A_MBHC_HPH, 0x13, 0x13);
-
- switch (calibration->bias) {
- case TABLA_MICBIAS1:
- micbias_mbhc_reg = TABLA_A_MICB_1_MBHC;
- micbias_int_reg = TABLA_A_MICB_1_INT_RBIAS;
- micbias_ctl_reg = TABLA_A_MICB_1_CTL;
- break;
- case TABLA_MICBIAS2:
- micbias_mbhc_reg = TABLA_A_MICB_2_MBHC;
- micbias_int_reg = TABLA_A_MICB_2_INT_RBIAS;
- micbias_ctl_reg = TABLA_A_MICB_2_CTL;
- break;
- case TABLA_MICBIAS3:
- micbias_mbhc_reg = TABLA_A_MICB_3_MBHC;
- micbias_int_reg = TABLA_A_MICB_3_INT_RBIAS;
- micbias_ctl_reg = TABLA_A_MICB_3_CTL;
- break;
- case TABLA_MICBIAS4:
- micbias_mbhc_reg = TABLA_A_MICB_4_MBHC;
- micbias_int_reg = TABLA_A_MICB_4_INT_RBIAS;
- micbias_ctl_reg = TABLA_A_MICB_4_CTL;
- break;
- default:
- pr_err("Error, invalid mic bias line\n");
- return -EINVAL;
- }
- snd_soc_update_bits(codec, micbias_int_reg, 0x80, 0);
- snd_soc_update_bits(codec, micbias_ctl_reg, 0x1, 0);
+ snd_soc_update_bits(codec, tabla->mbhc_bias_regs.int_rbias, 0x80, 0);
/* If central bandgap disabled */
if (!(snd_soc_read(codec, TABLA_A_PIN_CTL_OE1) & 1)) {
@@ -2215,12 +2438,6 @@
if (central_bias_enabled)
snd_soc_update_bits(codec, TABLA_A_PIN_CTL_OE1, 0x1, 0);
}
- snd_soc_update_bits(codec, micbias_mbhc_reg, 0x60,
- calibration->mic_current << 5);
- snd_soc_update_bits(codec, micbias_mbhc_reg, 0x80, 0x80);
- usleep_range(calibration->mic_pid, calibration->mic_pid);
-
- snd_soc_update_bits(codec, micbias_mbhc_reg, 0x10, 0x10);
snd_soc_update_bits(codec, TABLA_A_MICB_4_MBHC, 0x3, calibration->bias);
@@ -2251,6 +2468,7 @@
}
}
+
int tabla_hs_detect(struct snd_soc_codec *codec,
struct snd_soc_jack *headset_jack, struct snd_soc_jack *button_jack,
struct tabla_mbhc_calibration *calibration)
@@ -2264,6 +2482,7 @@
tabla->headset_jack = headset_jack;
tabla->button_jack = button_jack;
tabla->calibration = calibration;
+ tabla_get_mbhc_micbias_regs(codec, &tabla->mbhc_bias_regs);
INIT_DELAYED_WORK(&tabla->btn0_dwork, btn0_lpress_fn);
return tabla_codec_enable_hs_detect(codec, 1);
@@ -2280,9 +2499,12 @@
tabla_disable_irq(codec->control_data, TABLA_IRQ_MBHC_POTENTIAL);
bias_value = tabla_codec_read_dce_result(codec);
- pr_debug("%s: button press interrupt, bias value is %d\n",
+ pr_debug("%s: button press interrupt, bias value(DCE Read)=%d\n",
__func__, bias_value);
+ bias_value = tabla_codec_read_sta_result(codec);
+ pr_debug("%s: button press interrupt, bias value(STA Read)=%d\n",
+ __func__, bias_value);
/*
* TODO: If button pressed is not button 0,
* report the button press event immediately.
@@ -2306,6 +2528,10 @@
pr_debug("%s\n", __func__);
tabla_disable_irq(codec->control_data, TABLA_IRQ_MBHC_RELEASE);
+ mic_voltage = tabla_codec_read_dce_result(codec);
+ pr_debug("%s: Microphone Voltage on release(DCE Read) = %d\n",
+ __func__, mic_voltage);
+
if (priv->buttons_pressed & SND_JACK_BTN_0) {
ret = cancel_delayed_work(&priv->btn0_dwork);
@@ -2322,7 +2548,7 @@
mic_voltage =
tabla_codec_measure_micbias_voltage(codec, 0);
- pr_debug("%s: Microphone Voltage on release = %d\n",
+ pr_debug("%s: Mic Voltage on release(new STA) = %d\n",
__func__, mic_voltage);
if (mic_voltage < -2000 || mic_voltage > -670) {
@@ -2355,7 +2581,6 @@
{
struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
struct tabla_mbhc_calibration *calibration = tabla->calibration;
- int micbias_mbhc_reg;
if (!tabla->mclk_enabled && !tabla->mbhc_polling_active)
tabla_codec_enable_config_mode(codec, 1);
@@ -2363,24 +2588,8 @@
snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_CLK_CTL, 0x2, 0x2);
snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_B1_CTL, 0x6, 0x0);
- switch (calibration->bias) {
- case TABLA_MICBIAS1:
- micbias_mbhc_reg = TABLA_A_MICB_1_MBHC;
- break;
- case TABLA_MICBIAS2:
- micbias_mbhc_reg = TABLA_A_MICB_2_MBHC;
- break;
- case TABLA_MICBIAS3:
- micbias_mbhc_reg = TABLA_A_MICB_3_MBHC;
- break;
- case TABLA_MICBIAS4:
- micbias_mbhc_reg = TABLA_A_MICB_4_MBHC;
- break;
- default:
- pr_err("Error, invalid mic bias line\n");
- return;
- }
- snd_soc_update_bits(codec, micbias_mbhc_reg, 0x80, 0x00);
+ snd_soc_update_bits(codec,
+ tabla->mbhc_bias_regs.mbhc_reg, 0x80, 0x00);
usleep_range(calibration->shutdown_plug_removal,
calibration->shutdown_plug_removal);
@@ -2411,59 +2620,48 @@
struct tabla_priv *priv = data;
struct snd_soc_codec *codec = priv->codec;
int ldo_h_on, micb_cfilt_on;
- int micbias_cfilt_ctl_reg, cfilt_sel;
short mic_voltage;
short threshold_no_mic = 0xF7F6;
short threshold_fake_insert = 0xFD30;
+ u8 is_removal;
pr_debug("%s\n", __func__);
tabla_disable_irq(codec->control_data, TABLA_IRQ_MBHC_INSERTION);
+ is_removal = snd_soc_read(codec, TABLA_A_CDC_MBHC_INT_CTL) & 0x02;
+ snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_INT_CTL, 0x03, 0x00);
- switch (priv->calibration->bias) {
- case TABLA_MICBIAS1:
- cfilt_sel = priv->pdata->micbias.bias1_cfilt_sel;
- break;
- case TABLA_MICBIAS2:
- cfilt_sel = priv->pdata->micbias.bias2_cfilt_sel;
- break;
- case TABLA_MICBIAS3:
- cfilt_sel = priv->pdata->micbias.bias3_cfilt_sel;
- break;
- default:
- pr_err("%s: Error, invalid mic bias line, bias value = %d\n",
- __func__, priv->calibration->bias);
- return IRQ_HANDLED;
- }
-
- switch (cfilt_sel) {
- case TABLA_CFILT1_SEL:
- micbias_cfilt_ctl_reg = TABLA_A_MICB_CFILT_1_CTL;
- break;
- case TABLA_CFILT2_SEL:
- micbias_cfilt_ctl_reg = TABLA_A_MICB_CFILT_2_CTL;
- break;
- case TABLA_CFILT3_SEL:
- micbias_cfilt_ctl_reg = TABLA_A_MICB_CFILT_3_CTL;
- break;
- default: /* default should not happen as check should have been done */
- pr_err("%s: Invalid cfilt select, cfilt_sel = %d\n",
- __func__, cfilt_sel);
- return IRQ_HANDLED;
- }
+ /* Turn off both HPH and MIC line schmitt triggers */
+ snd_soc_update_bits(codec, priv->mbhc_bias_regs.mbhc_reg,
+ 0x90, 0x00);
+ snd_soc_update_bits(codec, TABLA_A_MBHC_HPH, 0x13, 0x00);
ldo_h_on = snd_soc_read(codec, TABLA_A_LDO_H_MODE_1) & 0x80;
- micb_cfilt_on = snd_soc_read(codec, micbias_cfilt_ctl_reg) & 0x80;
+ micb_cfilt_on = snd_soc_read(codec,
+ priv->mbhc_bias_regs.cfilt_ctl) & 0x80;
if (!ldo_h_on)
snd_soc_update_bits(codec, TABLA_A_LDO_H_MODE_1, 0x80, 0x80);
if (!micb_cfilt_on)
- snd_soc_update_bits(codec, micbias_cfilt_ctl_reg, 0x80, 0x80);
+ snd_soc_update_bits(codec, priv->mbhc_bias_regs.cfilt_ctl,
+ 0x80, 0x80);
usleep_range(priv->calibration->setup_plug_removal_delay,
priv->calibration->setup_plug_removal_delay);
- if (snd_soc_read(codec, TABLA_A_CDC_MBHC_INT_CTL) & 0x02) {
+ if (!ldo_h_on)
+ snd_soc_update_bits(codec, TABLA_A_LDO_H_MODE_1, 0x80, 0x0);
+ if (!micb_cfilt_on)
+ snd_soc_update_bits(codec, priv->mbhc_bias_regs.cfilt_ctl,
+ 0x80, 0x0);
+
+ if (is_removal) {
+ /*
+ * If headphone is removed while playback is in progress,
+ * it is possible that micbias will be switched to VDDIO.
+ */
+ if (priv->mbhc_micbias_switched)
+ tabla_codec_switch_micbias(codec, 0);
if (priv->headset_jack) {
pr_debug("%s: Reporting removal\n", __func__);
snd_soc_jack_report(priv->headset_jack, 0,
@@ -2474,11 +2672,6 @@
return IRQ_HANDLED;
}
- if (!ldo_h_on)
- snd_soc_update_bits(codec, TABLA_A_LDO_H_MODE_1, 0x80, 0x0);
- if (!micb_cfilt_on)
- snd_soc_update_bits(codec, micbias_cfilt_ctl_reg, 0x80, 0x0);
-
mic_voltage = tabla_codec_setup_hs_polling(codec);
if (mic_voltage > threshold_fake_insert) {
@@ -2533,6 +2726,13 @@
pr_debug("False alarm, headset not actually removed\n");
tabla_codec_start_hs_polling(codec);
} else {
+ /*
+ * If this removal is not false, first check the micbias
+ * switch status and switch it to LDOH if it is already
+ * switched to VDDIO.
+ */
+ if (priv->mbhc_micbias_switched)
+ tabla_codec_switch_micbias(codec, 0);
if (priv->headset_jack) {
pr_debug("%s: Reporting removal\n", __func__);
snd_soc_jack_report(priv->headset_jack, 0,
@@ -2574,45 +2774,6 @@
return IRQ_HANDLED;
}
-static int tabla_find_k_value(unsigned int ldoh_v, unsigned int cfilt_mv)
-{
- int rc = -EINVAL;
- unsigned min_mv, max_mv;
-
- switch (ldoh_v) {
- case TABLA_LDOH_1P95_V:
- min_mv = 160;
- max_mv = 1800;
- break;
- case TABLA_LDOH_2P35_V:
- min_mv = 200;
- max_mv = 2200;
- break;
- case TABLA_LDOH_2P75_V:
- min_mv = 240;
- max_mv = 2600;
- break;
- case TABLA_LDOH_2P85_V:
- min_mv = 250;
- max_mv = 2700;
- break;
- default:
- goto done;
- }
-
- if (cfilt_mv < min_mv || cfilt_mv > max_mv)
- goto done;
-
- for (rc = 4; rc <= 44; rc++) {
- min_mv = max_mv * (rc) / 44;
- if (min_mv >= cfilt_mv) {
- rc -= 4;
- break;
- }
- }
-done:
- return rc;
-}
static int tabla_handle_pdata(struct tabla_priv *tabla)
{
@@ -2811,6 +2972,12 @@
return -ENOMEM;
}
+ /* Make sure mbhc micbias register addresses are zeroed out */
+ memset(&tabla->mbhc_bias_regs, 0,
+ sizeof(struct mbhc_micbias_regs));
+ tabla->cfilt_k_value = 0;
+ tabla->mbhc_micbias_switched = false;
+
snd_soc_codec_set_drvdata(codec, tabla);
tabla->mclk_enabled = false;
diff --git a/sound/soc/msm/msm-pcm-lpa.c b/sound/soc/msm/msm-pcm-lpa.c
index eeb163e..8a44a56 100644
--- a/sound/soc/msm/msm-pcm-lpa.c
+++ b/sound/soc/msm/msm-pcm-lpa.c
@@ -78,10 +78,12 @@
struct snd_pcm_substream *substream = prtd->substream;
struct snd_pcm_runtime *runtime = substream->runtime;
struct audio_aio_write_param param;
- struct audio_buffer *buf = prtd->audio_client->port[IN].buf;
+ struct audio_buffer *buf = NULL;
+ unsigned long flag = 0;
int i = 0;
pr_debug("%s\n", __func__);
+ spin_lock_irqsave(&the_locks.event_lock, flag);
switch (opcode) {
case ASM_DATA_EVENT_WRITE_DONE: {
uint32_t *ptrmem = (uint32_t *)¶m;
@@ -100,6 +102,7 @@
pr_debug("%s:writing %d bytes of buffer to dsp 2\n",
__func__, prtd->pcm_count);
+ buf = prtd->audio_client->port[IN].buf;
param.paddr = (unsigned long)buf[0].phys
+ (prtd->out_head * prtd->pcm_count);
param.len = prtd->pcm_count;
@@ -133,6 +136,7 @@
pr_debug("%s:writing %d bytes"
" of buffer to dsp\n",
__func__, prtd->pcm_count);
+ buf = prtd->audio_client->port[IN].buf;
param.paddr = (unsigned long)buf[prtd->out_head].phys;
param.len = prtd->pcm_count;
param.msw_ts = 0;
@@ -163,6 +167,7 @@
pr_debug("Not Supported Event opcode[0x%x]\n", opcode);
break;
}
+ spin_unlock_irqrestore(&the_locks.event_lock, flag);
}
static int msm_pcm_playback_prepare(struct snd_pcm_substream *substream)
@@ -201,6 +206,7 @@
pr_debug("%s\n", __func__);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
+ prtd->pcm_irq_pos = 0;
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
pr_debug("SNDRV_PCM_TRIGGER_START\n");
@@ -337,6 +343,7 @@
dir = IN;
lpa_audio.prtd = NULL;
+ q6asm_cmd(prtd->audio_client, CMD_CLOSE);
q6asm_audio_client_buf_free_contiguous(dir,
prtd->audio_client);
@@ -344,7 +351,6 @@
msm_pcm_routing_dereg_phy_stream(soc_prtd->dai_link->be_id,
SNDRV_PCM_STREAM_PLAYBACK);
pr_debug("%s\n", __func__);
- q6asm_cmd(prtd->audio_client, CMD_CLOSE);
q6asm_audio_client_free(prtd->audio_client);
kfree(prtd);
@@ -511,6 +517,7 @@
static int __init msm_soc_platform_init(void)
{
+ spin_lock_init(&the_locks.event_lock);
init_waitqueue_head(&the_locks.enable_wait);
init_waitqueue_head(&the_locks.eos_wait);
init_waitqueue_head(&the_locks.write_wait);
diff --git a/sound/soc/msm/msm-pcm-q6.c b/sound/soc/msm/msm-pcm-q6.c
index 367a3e7..49324a9 100644
--- a/sound/soc/msm/msm-pcm-q6.c
+++ b/sound/soc/msm/msm-pcm-q6.c
@@ -71,9 +71,9 @@
.rate_max = 48000,
.channels_min = 1,
.channels_max = 2,
- .buffer_bytes_max = 4096 * 8,
- .period_bytes_min = 4096,
- .period_bytes_max = 4096,
+ .buffer_bytes_max = 2048 * 8,
+ .period_bytes_min = 2048,
+ .period_bytes_max = 2048,
.periods_min = 8,
.periods_max = 8,
.fifo_size = 0,
diff --git a/sound/soc/msm/msm-pcm-q6.h b/sound/soc/msm/msm-pcm-q6.h
index 42e54de..214bd9d 100644
--- a/sound/soc/msm/msm-pcm-q6.h
+++ b/sound/soc/msm/msm-pcm-q6.h
@@ -43,6 +43,7 @@
};
struct audio_locks {
+ spinlock_t event_lock;
wait_queue_head_t read_wait;
wait_queue_head_t write_wait;
wait_queue_head_t eos_wait;
diff --git a/sound/soc/msm/msm8960.c b/sound/soc/msm/msm8960.c
index 548b834..5e81e0f 100644
--- a/sound/soc/msm/msm8960.c
+++ b/sound/soc/msm/msm8960.c
@@ -229,10 +229,17 @@
struct snd_soc_dapm_context *dapm = &codec->dapm;
pr_debug("%s: msm8960_spk_control = %d", __func__, msm8960_spk_control);
- if (msm8960_spk_control == MSM8960_SPK_ON)
- snd_soc_dapm_enable_pin(dapm, "Ext Spk");
- else
- snd_soc_dapm_disable_pin(dapm, "Ext Spk");
+ if (msm8960_spk_control == MSM8960_SPK_ON) {
+ snd_soc_dapm_enable_pin(dapm, "Ext Spk Bottom Pos");
+ snd_soc_dapm_enable_pin(dapm, "Ext Spk Bottom Neg");
+ snd_soc_dapm_enable_pin(dapm, "Ext Spk Top Pos");
+ snd_soc_dapm_enable_pin(dapm, "Ext Spk Top Neg");
+ } else {
+ snd_soc_dapm_disable_pin(dapm, "Ext Spk Bottom Pos");
+ snd_soc_dapm_disable_pin(dapm, "Ext Spk Bottom Neg");
+ snd_soc_dapm_disable_pin(dapm, "Ext Spk Top Pos");
+ snd_soc_dapm_disable_pin(dapm, "Ext Spk Top Neg");
+ }
snd_soc_dapm_sync(dapm);
}
@@ -447,11 +454,8 @@
{"DMIC5", NULL, "MIC BIAS4 External"},
{"MIC BIAS4 External", NULL, "Digital Mic5"},
-};
-
-static const struct snd_soc_dapm_route cdp_audio_map[] = {
- /** Digital Mic GM4 on CDP mainboard.
- * Connected to DMIC6 input on Tabla codec.
+ /* Tabla digital Mic6 - back bottom digital Mic on Liquid and
+ * bottom mic on CDP. FLUID/MTP do not have dmic6 installed.
*/
{"DMIC6", NULL, "MIC BIAS4 External"},
{"MIC BIAS4 External", NULL, "Digital Mic6"},
@@ -584,17 +588,10 @@
snd_soc_dapm_add_routes(dapm, common_audio_map,
ARRAY_SIZE(common_audio_map));
- if (machine_is_msm8960_cdp())
- snd_soc_dapm_add_routes(dapm, cdp_audio_map,
- ARRAY_SIZE(cdp_audio_map));
- else if (machine_is_msm8960_mtp())
- snd_soc_dapm_add_routes(dapm, cdp_audio_map,
- ARRAY_SIZE(cdp_audio_map));
- else if (machine_is_msm8960_fluid())
- snd_soc_dapm_add_routes(dapm, cdp_audio_map,
- ARRAY_SIZE(cdp_audio_map));
-
- snd_soc_dapm_enable_pin(dapm, "Ext Spk");
+ snd_soc_dapm_enable_pin(dapm, "Ext Spk Bottom Pos");
+ snd_soc_dapm_enable_pin(dapm, "Ext Spk Bottom Neg");
+ snd_soc_dapm_enable_pin(dapm, "Ext Spk Top Pos");
+ snd_soc_dapm_enable_pin(dapm, "Ext Spk Top Neg");
snd_soc_dapm_sync(dapm);
diff --git a/sound/soc/msm/qdsp6/q6asm.c b/sound/soc/msm/qdsp6/q6asm.c
index 9c54548..052286b 100644
--- a/sound/soc/msm/qdsp6/q6asm.c
+++ b/sound/soc/msm/qdsp6/q6asm.c
@@ -790,7 +790,7 @@
do_gettimeofday(&in_cont_tv);
pr_err("In_CONT:previous read buffer done \
at %ld sec %ld microsec\n",\
- out_cont_tv.tv_sec, out_cont_tv.tv_usec);
+ in_cont_tv.tv_sec, in_cont_tv.tv_usec);
}
}
#endif