Merge "msm: cpufreq: Support reading available frequencies" into msm-3.0
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index e355515..a595612 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -945,7 +945,7 @@
via muxing than BAM could without muxing.
config MSM_N_WAY_SMD
- depends on (MSM_SMD && (ARCH_MSM_SCORPION || ARCH_MSM8960 || ARCH_MSM7X27 || ARCH_MSM7X25 || ARCH_MSM9615))
+ depends on (MSM_SMD && !(ARCH_MSM7X01A))
default y
bool "MSM N-WAY SMD support"
help
@@ -953,7 +953,7 @@
normal APPS-MODEM SMD communication.
config MSM_N_WAY_SMSM
- depends on (MSM_SMD && (ARCH_MSM_SCORPION || ARCH_MSM8960 || ARCH_MSM7X27 || ARCH_MSM7X25 || ARCH_MSM9615))
+ depends on (MSM_SMD && !(ARCH_MSM7X01A))
default y
bool "MSM N-WAY SMSM support"
help
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 0d36b0a..0072100 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -75,6 +75,7 @@
obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o remote_spinlock.o
obj-y += socinfo.o
ifndef CONFIG_ARCH_MSM9615
+ifndef CONFIG_ARCH_APQ8064
ifndef CONFIG_ARCH_MSM8960
ifndef CONFIG_ARCH_MSM8X60
obj-$(CONFIG_MSM_SMD) += pmic.o
@@ -82,6 +83,7 @@
endif
endif
endif
+endif
ifndef CONFIG_ARCH_MSM8960
ifndef CONFIG_ARCH_MSM8X60
ifndef CONFIG_ARCH_APQ8064
diff --git a/arch/arm/mach-msm/acpuclock-8960.c b/arch/arm/mach-msm/acpuclock-8960.c
index 90a7504..d827dd1 100644
--- a/arch/arm/mach-msm/acpuclock-8960.c
+++ b/arch/arm/mach-msm/acpuclock-8960.c
@@ -66,7 +66,7 @@
#define STBY_KHZ 1
#define HFPLL_NOMINAL_VDD 1050000
-#define HFPLL_LOW_VDD 1050000
+#define HFPLL_LOW_VDD 945000
#define HFPLL_LOW_VDD_PLL_L_MAX 0x28
#define SECCLKAGD BIT(4)
@@ -278,20 +278,19 @@
[11] = { { 918000, HFPLL, 1, 0, 0x22 }, 1150000, 1150000, 3 },
};
-/* TODO: Update core voltages when data is available. */
static struct acpu_level acpu_freq_tbl_8960[] = {
- { 0, {STBY_KHZ, QSB, 0, 0, 0x00 }, L2(0), 1050000 },
- { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(1), 1050000 },
- { 1, { 432000, HFPLL, 2, 0, 0x20 }, L2(6), 1050000 },
- { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(6), 1050000 },
- { 1, { 540000, HFPLL, 2, 0, 0x28 }, L2(6), 1050000 },
- { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(6), 1050000 },
- { 1, { 648000, HFPLL, 1, 0, 0x18 }, L2(6), 1050000 },
- { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(6), 1050000 },
- { 1, { 756000, HFPLL, 1, 0, 0x1C }, L2(11), 1150000 },
- { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(11), 1150000 },
- { 1, { 864000, HFPLL, 1, 0, 0x20 }, L2(11), 1150000 },
- { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(11), 1150000 },
+ { 0, {STBY_KHZ, QSB, 0, 0, 0x00 }, L2(0), 950000 },
+ { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(1), 950000 },
+ { 1, { 432000, HFPLL, 2, 0, 0x20 }, L2(6), 950000 },
+ { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(6), 962500 },
+ { 1, { 540000, HFPLL, 2, 0, 0x28 }, L2(6), 962500 },
+ { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(6), 987500 },
+ { 1, { 648000, HFPLL, 1, 0, 0x18 }, L2(6), 1000000 },
+ { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(6), 1025000 },
+ { 1, { 756000, HFPLL, 1, 0, 0x1C }, L2(11), 1050000 },
+ { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(11), 1087500 },
+ { 1, { 864000, HFPLL, 1, 0, 0x20 }, L2(11), 1125000 },
+ { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(11), 1137500 },
{ 0, { 0 } }
};
diff --git a/arch/arm/mach-msm/board-9615.c b/arch/arm/mach-msm/board-9615.c
index c009bdf..87ff559 100644
--- a/arch/arm/mach-msm/board-9615.c
+++ b/arch/arm/mach-msm/board-9615.c
@@ -39,6 +39,16 @@
&msm9615_device_tsens,
&msm_device_nand,
&msm_rpm_device,
+
+#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
+ defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
+ &qcrypto_device,
+#endif
+
+#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
+ defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
+ &qcedev_device,
+#endif
};
static struct pm8xxx_irq_platform_data pm8xxx_irq_pdata __devinitdata = {
@@ -196,6 +206,117 @@
},
};
+#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
+ defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE) || \
+ defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
+ defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
+
+#define QCE_SIZE 0x10000
+#define QCE_0_BASE 0x18500000
+
+#define QCE_HW_KEY_SUPPORT 0
+#define QCE_SHA_HMAC_SUPPORT 1
+#define QCE_SHARE_CE_RESOURCE 1
+#define QCE_CE_SHARED 0
+
+static struct resource qcrypto_resources[] = {
+ [0] = {
+ .start = QCE_0_BASE,
+ .end = QCE_0_BASE + QCE_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .name = "crypto_channels",
+ .start = DMOV_CE_IN_CHAN,
+ .end = DMOV_CE_OUT_CHAN,
+ .flags = IORESOURCE_DMA,
+ },
+ [2] = {
+ .name = "crypto_crci_in",
+ .start = DMOV_CE_IN_CRCI,
+ .end = DMOV_CE_IN_CRCI,
+ .flags = IORESOURCE_DMA,
+ },
+ [3] = {
+ .name = "crypto_crci_out",
+ .start = DMOV_CE_OUT_CRCI,
+ .end = DMOV_CE_OUT_CRCI,
+ .flags = IORESOURCE_DMA,
+ },
+};
+
+static struct resource qcedev_resources[] = {
+ [0] = {
+ .start = QCE_0_BASE,
+ .end = QCE_0_BASE + QCE_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .name = "crypto_channels",
+ .start = DMOV_CE_IN_CHAN,
+ .end = DMOV_CE_OUT_CHAN,
+ .flags = IORESOURCE_DMA,
+ },
+ [2] = {
+ .name = "crypto_crci_in",
+ .start = DMOV_CE_IN_CRCI,
+ .end = DMOV_CE_IN_CRCI,
+ .flags = IORESOURCE_DMA,
+ },
+ [3] = {
+ .name = "crypto_crci_out",
+ .start = DMOV_CE_OUT_CRCI,
+ .end = DMOV_CE_OUT_CRCI,
+ .flags = IORESOURCE_DMA,
+ },
+};
+
+#endif
+
+#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
+ defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
+
+static struct msm_ce_hw_support qcrypto_ce_hw_suppport = {
+ .ce_shared = QCE_CE_SHARED,
+ .shared_ce_resource = QCE_SHARE_CE_RESOURCE,
+ .hw_key_support = QCE_HW_KEY_SUPPORT,
+ .sha_hmac = QCE_SHA_HMAC_SUPPORT,
+};
+
+static struct platform_device qcrypto_device = {
+ .name = "qcrypto",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(qcrypto_resources),
+ .resource = qcrypto_resources,
+ .dev = {
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .platform_data = &qcrypto_ce_hw_suppport,
+ },
+};
+#endif
+
+#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
+ defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
+
+static struct msm_ce_hw_support qcedev_ce_hw_suppport = {
+ .ce_shared = QCE_CE_SHARED,
+ .shared_ce_resource = QCE_SHARE_CE_RESOURCE,
+ .hw_key_support = QCE_HW_KEY_SUPPORT,
+ .sha_hmac = QCE_SHA_HMAC_SUPPORT,
+};
+
+static struct platform_device qcedev_device = {
+ .name = "qce",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(qcedev_resources),
+ .resource = qcedev_resources,
+ .dev = {
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .platform_data = &qcedev_ce_hw_suppport,
+ },
+};
+#endif
+
#if (defined(CONFIG_MMC_MSM_SDC1_SUPPORT)\
|| defined(CONFIG_MMC_MSM_SDC2_SUPPORT))
diff --git a/arch/arm/mach-msm/board-apq8064.c b/arch/arm/mach-msm/board-apq8064.c
index 907fa72..d37fb7b 100644
--- a/arch/arm/mach-msm/board-apq8064.c
+++ b/arch/arm/mach-msm/board-apq8064.c
@@ -271,8 +271,10 @@
apq8064_add_sdcc(3, apq8064_sdc3_pdata);
}
+#define MSM_SHARED_RAM_PHYS 0x80000000
static void __init apq8064_map_io(void)
{
+ msm_shared_ram_phys = MSM_SHARED_RAM_PHYS;
msm_map_apq8064_io();
if (socinfo_init() < 0)
pr_err("socinfo_init() failed!\n");
@@ -307,6 +309,7 @@
&apq8064_slim_ctrl,
&apq8064_device_ssbi_pmic1,
&apq8064_device_ssbi_pmic2,
+ &msm_device_smd_apq8064,
};
static struct platform_device *sim_devices[] __initdata = {
diff --git a/arch/arm/mach-msm/board-msm8960-regulator.c b/arch/arm/mach-msm/board-msm8960-regulator.c
index e85202d..e3f0e31 100644
--- a/arch/arm/mach-msm/board-msm8960-regulator.c
+++ b/arch/arm/mach-msm/board-msm8960-regulator.c
@@ -444,9 +444,9 @@
/* SAW regulator constraints */
struct regulator_init_data msm_saw_regulator_pdata_s5 =
/* ID vreg_name min_uV max_uV */
- SAW_VREG_INIT(S5, "8921_s5", 1050000, 1150000);
+ SAW_VREG_INIT(S5, "8921_s5", 950000, 1150000);
struct regulator_init_data msm_saw_regulator_pdata_s6 =
- SAW_VREG_INIT(S6, "8921_s6", 1050000, 1150000);
+ SAW_VREG_INIT(S6, "8921_s6", 950000, 1150000);
/* PM8921 regulator constraints */
struct pm8921_regulator_platform_data
diff --git a/arch/arm/mach-msm/clock-9615.c b/arch/arm/mach-msm/clock-9615.c
index a5db9b2..9b9ac4a 100644
--- a/arch/arm/mach-msm/clock-9615.c
+++ b/arch/arm/mach-msm/clock-9615.c
@@ -1576,6 +1576,15 @@
CLK_LOOKUP("ebi1_msmbus_clk", ebi1_msmbus_clk.c, NULL),
CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"),
+ CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qce.0"),
+ CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qcrypto.0"),
+ CLK_LOOKUP("core_clk", ce1_core_clk.c, "qce.0"),
+ CLK_LOOKUP("core_clk", ce1_core_clk.c, "qcrypto.0"),
+
+ /* TODO: Make this real when RPM's ready. */
+ CLK_DUMMY("ebi1_msmbus_clk", ebi1_msmbus_clk.c, NULL, OFF),
+ CLK_DUMMY("mem_clk", ebi1_adm_clk.c, "msm_dmov", OFF),
+
};
static void set_fsm_mode(void __iomem *mode_reg)
diff --git a/arch/arm/mach-msm/devices-8064.c b/arch/arm/mach-msm/devices-8064.c
index 02b7569..99e8d23 100644
--- a/arch/arm/mach-msm/devices-8064.c
+++ b/arch/arm/mach-msm/devices-8064.c
@@ -549,6 +549,11 @@
.dev.platform_data = &msm_sps_pdata,
};
+struct platform_device msm_device_smd_apq8064 = {
+ .name = "msm_smd",
+ .id = -1,
+};
+
static struct clk_lookup msm_clocks_8064_dummy[] = {
CLK_DUMMY("pll2", PLL2, NULL, 0),
CLK_DUMMY("pll8", PLL8, NULL, 0),
diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h
index 4d41819..4a82b33 100644
--- a/arch/arm/mach-msm/devices.h
+++ b/arch/arm/mach-msm/devices.h
@@ -112,6 +112,7 @@
extern struct platform_device msm_device_sps_apq8064;
extern struct platform_device msm_device_bam_dmux;
extern struct platform_device msm_device_smd;
+extern struct platform_device msm_device_smd_apq8064;
extern struct platform_device msm_device_dmov;
extern struct platform_device msm8960_device_dmov;
extern struct platform_device apq8064_device_dmov;
diff --git a/arch/arm/mach-msm/include/mach/irqs-8064.h b/arch/arm/mach-msm/include/mach/irqs-8064.h
index 97657ea..25dcd3f 100644
--- a/arch/arm/mach-msm/include/mach/irqs-8064.h
+++ b/arch/arm/mach-msm/include/mach/irqs-8064.h
@@ -299,13 +299,14 @@
#define INT_ADM_AARM ADM_0_SCSS_0_IRQ
/* smd/smsm interrupts */
-#define INT_A9_M2A_0 MSS_TO_APPS_IRQ_0
-#define INT_A9_M2A_5 MSS_TO_APPS_IRQ_1
-#define INT_ADSP_A11 LPASS_SCSS_GP_HIGH_IRQ
-#define INT_ADSP_A11_SMSM LPASS_SCSS_GP_MEDIUM_IRQ
-#define INT_DSPS_A11 SPS_MTI_31
-#define INT_WCNSS_A11 RIVA_APSS_SPARE_IRQ
-#define INT_WCNSS_A11_SMSM RIVA_APPS_WLAN_SMSM_IRQ
+#define INT_A9_M2A_0 (GIC_SPI_START + 37) /*GSS_TO_APPS_IRQ_0*/
+#define INT_A9_M2A_5 (GIC_SPI_START + 38) /*GSS_TO_APPS_IRQ_1*/
+#define INT_ADSP_A11 LPASS_SCSS_GP_HIGH_IRQ
+#define INT_ADSP_A11_SMSM LPASS_SCSS_GP_MEDIUM_IRQ
+#define INT_DSPS_A11 SPS_MTI_31
+#define INT_DSPS_A11_SMSM SPS_MTI_30
+#define INT_WCNSS_A11 RIVA_APSS_SPARE_IRQ
+#define INT_WCNSS_A11_SMSM RIVA_APPS_WLAN_SMSM_IRQ
#endif
diff --git a/arch/arm/mach-msm/include/mach/irqs-8960.h b/arch/arm/mach-msm/include/mach/irqs-8960.h
index 6d121f9..dae0f47 100644
--- a/arch/arm/mach-msm/include/mach/irqs-8960.h
+++ b/arch/arm/mach-msm/include/mach/irqs-8960.h
@@ -273,14 +273,14 @@
#define INT_ADM_AARM ADM_0_SCSS_0_IRQ
/* smd/smsm interrupts */
-#define INT_A9_M2A_0 MSS_TO_APPS_IRQ_0
-#define INT_A9_M2A_5 MSS_TO_APPS_IRQ_1
-#define INT_ADSP_A11 LPASS_SCSS_GP_HIGH_IRQ
-#define INT_ADSP_A11_SMSM LPASS_SCSS_GP_MEDIUM_IRQ
-#define INT_DSPS_A11 SPS_MTI_31
-#define INT_DSPS_A11_SMSM SPS_MTI_30
-#define INT_WCNSS_A11 RIVA_APSS_SPARE_IRQ
-#define INT_WCNSS_A11_SMSM RIVA_APPS_WLAN_SMSM_IRQ
+#define INT_A9_M2A_0 (GIC_SPI_START + 37) /*MSS_TO_APPS_IRQ_0*/
+#define INT_A9_M2A_5 (GIC_SPI_START + 38) /*MSS_TO_APPS_IRQ_1*/
+#define INT_ADSP_A11 LPASS_SCSS_GP_HIGH_IRQ
+#define INT_ADSP_A11_SMSM LPASS_SCSS_GP_MEDIUM_IRQ
+#define INT_DSPS_A11 SPS_MTI_31
+#define INT_DSPS_A11_SMSM SPS_MTI_30
+#define INT_WCNSS_A11 RIVA_APSS_SPARE_IRQ
+#define INT_WCNSS_A11_SMSM RIVA_APPS_WLAN_SMSM_IRQ
#endif
diff --git a/arch/arm/mach-msm/smd.c b/arch/arm/mach-msm/smd.c
index 7dec32a..94dd8b8 100644
--- a/arch/arm/mach-msm/smd.c
+++ b/arch/arm/mach-msm/smd.c
@@ -43,15 +43,17 @@
#if defined(CONFIG_ARCH_QSD8X50) || defined(CONFIG_ARCH_MSM8X60) \
|| defined(CONFIG_ARCH_MSM8960) || defined(CONFIG_ARCH_FSM9XXX) \
- || defined(CONFIG_ARCH_MSM9615)
+ || defined(CONFIG_ARCH_MSM9615) || defined(CONFIG_ARCH_APQ8064)
#define CONFIG_QDSP6 1
#endif
-#if defined(CONFIG_ARCH_MSM8X60) || defined(CONFIG_ARCH_MSM8960)
+#if defined(CONFIG_ARCH_MSM8X60) || defined(CONFIG_ARCH_MSM8960) \
+ || defined(CONFIG_ARCH_APQ8064)
#define CONFIG_DSPS 1
#endif
-#if defined(CONFIG_ARCH_MSM8960)
+#if defined(CONFIG_ARCH_MSM8960) \
+ || defined(CONFIG_ARCH_APQ8064)
#define CONFIG_WCNSS 1
#define CONFIG_DSPS_SMSM 1
#endif
@@ -200,6 +202,23 @@
#define MSM_TRIG_A2DSPS_SMSM_INT
#define MSM_TRIG_A2WCNSS_SMD_INT
#define MSM_TRIG_A2WCNSS_SMSM_INT
+#elif defined(CONFIG_ARCH_APQ8064)
+#define MSM_TRIG_A2M_SMD_INT \
+ (smd_write_intr(1 << 3, MSM_APCS_GCC_BASE + 0x8))
+#define MSM_TRIG_A2Q6_SMD_INT \
+ (smd_write_intr(1 << 15, MSM_APCS_GCC_BASE + 0x8))
+#define MSM_TRIG_A2M_SMSM_INT \
+ (smd_write_intr(1 << 4, MSM_APCS_GCC_BASE + 0x8))
+#define MSM_TRIG_A2Q6_SMSM_INT \
+ (smd_write_intr(1 << 14, MSM_APCS_GCC_BASE + 0x8))
+#define MSM_TRIG_A2DSPS_SMD_INT \
+ (smd_write_intr(1, MSM_SIC_NON_SECURE_BASE + 0x4080))
+#define MSM_TRIG_A2DSPS_SMSM_INT \
+ (smd_write_intr(1, MSM_SIC_NON_SECURE_BASE + 0x4094))
+#define MSM_TRIG_A2WCNSS_SMD_INT \
+ (smd_write_intr(1 << 25, MSM_APCS_GCC_BASE + 0x8))
+#define MSM_TRIG_A2WCNSS_SMSM_INT \
+ (smd_write_intr(1 << 23, MSM_APCS_GCC_BASE + 0x8))
#elif defined(CONFIG_ARCH_FSM9XXX)
#define MSM_TRIG_A2Q6_SMD_INT \
(smd_write_intr(1 << 10, MSM_GCC_BASE + 0x8))
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 8850516..8088e44 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -309,20 +309,21 @@
config CRYPTO_DEV_QCE
tristate "Qualcomm Crypto Engine (QCE) module"
- select CRYPTO_DEV_QCE40 if ARCH_MSM8960
+ select CRYPTO_DEV_QCE40 if ARCH_MSM8960 || ARCH_MSM9615
default n
help
- This driver supports Qualcomm Crypto Engine in MSM7x30 MSM8660
- MSM8x55 and MSM8960
+ This driver supports Qualcomm Crypto Engine in MSM7x30, MSM8660
+ MSM8x55, MSM8960 and MSM9615
To compile this driver as a module, choose M here: the
For MSM7x30 MSM8660 and MSM8x55 the module is called qce
- For MSM8960 the module is called qce40
+ For MSM8960 and MSM9615 the module is called qce40
config CRYPTO_DEV_QCEDEV
tristate "QCEDEV Interface to CE module"
default n
help
- This driver supports Qualcomm QCEDEV Crypto in MSM7x30 MSM8660, MSM8960.
+ This driver supports Qualcomm QCEDEV Crypto in MSM7x30, MSM8660,
+ MSM8960 and MSM9615.
This exposes the interface to the QCE hardware accelerator via IOCTLs
To compile this driver as a module, choose M here: the
module will be called qcedev.
diff --git a/drivers/crypto/msm/qce40.c b/drivers/crypto/msm/qce40.c
index 90a7889..4ef2e08 100644
--- a/drivers/crypto/msm/qce40.c
+++ b/drivers/crypto/msm/qce40.c
@@ -29,6 +29,7 @@
#include <crypto/sha.h>
#include <mach/dma.h>
#include <mach/clk.h>
+#include <mach/socinfo.h>
#include "qce.h"
#include "qce40.h"
@@ -149,6 +150,12 @@
pce_dev->ce_dm.ce_block_size = 16;
}
}
+ /*
+ * This is a temporary change - until Data Mover changes its
+ * configuration from 16 byte crci to 64 byte crci.
+ */
+ if (cpu_is_msm9615())
+ pce_dev->ce_dm.ce_block_size = 16;
dev_info(pce_dev->pdev,
"IO base 0x%x\n, ce_in channel %d , "
@@ -161,6 +168,23 @@
return 0;
};
+#ifdef CONFIG_ARCH_MSM9615
+static void config_ce_engine(struct qce_device *pce_dev)
+{
+ unsigned int val = 0;
+
+ val = (1 << CRYPTO_MASK_DOUT_INTR) | (1 << CRYPTO_MASK_DIN_INTR) |
+ (1 << CRYPTO_MASK_OP_DONE_INTR) |
+ (1 << CRYPTO_MASK_ERR_INTR);
+
+ writel_relaxed(val, pce_dev->iobase + CRYPTO_CONFIG_REG);
+}
+#else
+static void config_ce_engine(struct qce_device *pce_dev)
+{
+
+}
+#endif
static void _check_probe_done_call_back(struct msm_dmov_cmd *cmd_ptr,
unsigned int result, struct msm_dmov_errdata *err)
@@ -185,6 +209,22 @@
clk_reset(pce_dev->ce_core_clk, CLK_RESET_ASSERT);
clk_reset(pce_dev->ce_core_clk, CLK_RESET_DEASSERT);
+ /*
+ * Ensure previous instruction (any writes to CLK registers)
+ * to toggle the CLK reset lines was completed before configuring
+ * ce engine. The ce engine configuration settings should not be lost
+ * becasue of clk reset.
+ */
+ mb();
+
+ /* Configure the CE Engine */
+ config_ce_engine(pce_dev);
+
+ /*
+ * Ensure ce configuration is completed.
+ */
+ mb();
+
pce_dev->ce_dm.chan_ce_in_cmd->complete_func =
_check_probe_done_call_back;
pce_dev->ce_dm.chan_ce_in_cmd->cmdptr =
@@ -2529,4 +2569,4 @@
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Mona Hossain <mhossain@codeaurora.org>");
MODULE_DESCRIPTION("Crypto Engine driver");
-MODULE_VERSION("2.11");
+MODULE_VERSION("2.12");
diff --git a/drivers/crypto/msm/qcedev.c b/drivers/crypto/msm/qcedev.c
index dcc98a0..9d315d2 100644
--- a/drivers/crypto/msm/qcedev.c
+++ b/drivers/crypto/msm/qcedev.c
@@ -1229,6 +1229,7 @@
return qcedev_hmac_final(areq, handle);
}
+#ifdef CONFIG_ANDROID_PMEM
static int qcedev_pmem_ablk_cipher_max_xfer(struct qcedev_async_req *areq,
struct qcedev_handle *handle)
{
@@ -1438,6 +1439,18 @@
return err;
}
+#else
+static int qcedev_pmem_ablk_cipher_max_xfer(struct qcedev_async_req *areq,
+ struct qcedev_handle *handle)
+{
+ return -EPERM;
+}
+static int qcedev_pmem_ablk_cipher(struct qcedev_async_req *qcedev_areq,
+ struct qcedev_handle *handle)
+{
+ return -EPERM;
+}
+#endif/*CONFIG_ANDROID_PMEM*/
static int qcedev_vbuf_ablk_cipher_max_xfer(struct qcedev_async_req *areq,
int *di, struct qcedev_handle *handle,
@@ -1837,7 +1850,7 @@
podev))
return -EINVAL;
- if (qcedev_areq.cipher_op_req.use_pmem == QCEDEV_USE_PMEM)
+ if ((qcedev_areq.cipher_op_req.use_pmem) && (QCEDEV_USE_PMEM))
err = qcedev_pmem_ablk_cipher(&qcedev_areq, handle);
else
err = qcedev_vbuf_ablk_cipher(&qcedev_areq, handle);
@@ -2156,7 +2169,7 @@
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Mona Hossain <mhossain@codeaurora.org>");
MODULE_DESCRIPTION("Qualcomm DEV Crypto driver");
-MODULE_VERSION("1.23");
+MODULE_VERSION("1.24");
module_init(qcedev_init);
module_exit(qcedev_exit);
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index c96213d..de6f8e1 100755
--- a/scripts/checkpatch.pl
+++ b/scripts/checkpatch.pl
@@ -1229,7 +1229,6 @@
my @setup_docs = ();
my $setup_docs = 0;
- my $in_code_block = 0;
my $exec_file = "";
my $shorttext = BEFORE_SHORTTEXT;
@@ -1375,6 +1374,7 @@
if ($line =~ /^diff --git.*?(\S+)$/) {
$realfile = $1;
$realfile =~ s@^([^/]*)/@@;
+ $exec_file = $realfile;
} elsif ($line =~ /^\+\+\+\s+(\S+)/) {
$realfile = $1;
@@ -1389,16 +1389,14 @@
if ($realfile =~ m@^include/asm/@) {
ERROR("do not modify files in include/asm, change architecture specific files in include/asm-<architecture>\n" . "$here$rawline\n");
}
- $in_code_block = 1;
+ $exec_file = "";
next;
}
elsif ($rawline =~ /^diff.+a\/(.+)\sb\/.+$/) {
$exec_file = $1;
- $in_code_block = 0;
}
#Check state to make sure we aren't in code block.
- elsif (!$in_code_block &&
- ($exec_file =~ /^.+\.[chS]$/ or
+ elsif (($exec_file =~ /^.+\.[chS]$/ or
$exec_file =~ /^.+\.txt$/ or
$exec_file =~ /^.+\.ihex$/ or
$exec_file =~ /^.+\.hex$/ or