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Paul Walmsley69d88a02008-03-18 10:02:50 +02001#ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
2#define __ARCH_ARM_MACH_OMAP2_PRM_H
3
4/*
5 * OMAP2/3 Power/Reset Management (PRM) register definitions
6 *
Rajendra Nayakc1294042009-12-08 18:24:51 -07007 * Copyright (C) 2007-2009 Texas Instruments, Inc.
8 * Copyright (C) 2009 Nokia Corporation
Paul Walmsley69d88a02008-03-18 10:02:50 +02009 *
10 * Written by Paul Walmsley
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include "prcm-common.h"
18
Paul Walmsley69d88a02008-03-18 10:02:50 +020019#define OMAP2420_PRM_REGADDR(module, reg) \
Santosh Shilimkar233fd642009-10-19 15:25:31 -070020 OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
Paul Walmsley69d88a02008-03-18 10:02:50 +020021#define OMAP2430_PRM_REGADDR(module, reg) \
Santosh Shilimkar233fd642009-10-19 15:25:31 -070022 OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
Paul Walmsley69d88a02008-03-18 10:02:50 +020023#define OMAP34XX_PRM_REGADDR(module, reg) \
Santosh Shilimkar233fd642009-10-19 15:25:31 -070024 OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
Rajendra Nayakc1294042009-12-08 18:24:51 -070025#define OMAP44XX_PRM_REGADDR(module, reg) \
26 OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg))
Rajendra Nayak0324f592010-01-19 17:30:54 -070027#define OMAP44XX_CHIRONSS_REGADDR(module, reg) \
28 OMAP2_L4_IO_ADDRESS(OMAP4430_CHIRONSS_BASE + (module) + (reg))
Rajendra Nayakc1294042009-12-08 18:24:51 -070029
30#include "prm44xx.h"
Paul Walmsley69d88a02008-03-18 10:02:50 +020031
32/*
33 * Architecture-specific global PRM registers
Kalle Jokiniemidfa3d032008-05-06 10:33:01 +030034 * Use __raw_{read,write}l() with these registers.
Paul Walmsley69d88a02008-03-18 10:02:50 +020035 *
36 * With a few exceptions, these are the register names beginning with
37 * PRCM_* on 24xx, and PRM_* on 34xx. (The exceptions are the
38 * IRQSTATUS and IRQENABLE bits.)
39 *
40 */
41
Tony Lindgren8e3bd352009-05-25 11:26:42 -070042#define OMAP2_PRCM_REVISION_OFFSET 0x0000
43#define OMAP2420_PRCM_REVISION OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000)
44#define OMAP2_PRCM_SYSCONFIG_OFFSET 0x0010
45#define OMAP2420_PRCM_SYSCONFIG OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010)
Tony Lindgrenc2d43e32008-07-03 12:24:38 +030046
Tony Lindgren8e3bd352009-05-25 11:26:42 -070047#define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018
48#define OMAP2420_PRCM_IRQSTATUS_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018)
49#define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c
50#define OMAP2420_PRCM_IRQENABLE_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c)
Tony Lindgrenc2d43e32008-07-03 12:24:38 +030051
Tony Lindgren8e3bd352009-05-25 11:26:42 -070052#define OMAP2_PRCM_VOLTCTRL_OFFSET 0x0050
53#define OMAP2420_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050)
54#define OMAP2_PRCM_VOLTST_OFFSET 0x0054
55#define OMAP2420_PRCM_VOLTST OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054)
56#define OMAP2_PRCM_CLKSRC_CTRL_OFFSET 0x0060
57#define OMAP2420_PRCM_CLKSRC_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060)
58#define OMAP2_PRCM_CLKOUT_CTRL_OFFSET 0x0070
59#define OMAP2420_PRCM_CLKOUT_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070)
60#define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET 0x0078
61#define OMAP2420_PRCM_CLKEMUL_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078)
62#define OMAP2_PRCM_CLKCFG_CTRL_OFFSET 0x0080
63#define OMAP2420_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080)
64#define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084
65#define OMAP2420_PRCM_CLKCFG_STATUS OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084)
66#define OMAP2_PRCM_VOLTSETUP_OFFSET 0x0090
67#define OMAP2420_PRCM_VOLTSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090)
68#define OMAP2_PRCM_CLKSSETUP_OFFSET 0x0094
69#define OMAP2420_PRCM_CLKSSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094)
70#define OMAP2_PRCM_POLCTRL_OFFSET 0x0098
71#define OMAP2420_PRCM_POLCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098)
Tony Lindgrenc2d43e32008-07-03 12:24:38 +030072
Tony Lindgren8e3bd352009-05-25 11:26:42 -070073#define OMAP2430_PRCM_REVISION OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000)
74#define OMAP2430_PRCM_SYSCONFIG OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010)
Paul Walmsley69d88a02008-03-18 10:02:50 +020075
Tony Lindgren8e3bd352009-05-25 11:26:42 -070076#define OMAP2430_PRCM_IRQSTATUS_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018)
77#define OMAP2430_PRCM_IRQENABLE_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c)
Paul Walmsley69d88a02008-03-18 10:02:50 +020078
Tony Lindgren8e3bd352009-05-25 11:26:42 -070079#define OMAP2430_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050)
80#define OMAP2430_PRCM_VOLTST OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054)
81#define OMAP2430_PRCM_CLKSRC_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060)
82#define OMAP2430_PRCM_CLKOUT_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070)
83#define OMAP2430_PRCM_CLKEMUL_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078)
84#define OMAP2430_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080)
85#define OMAP2430_PRCM_CLKCFG_STATUS OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084)
86#define OMAP2430_PRCM_VOLTSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090)
87#define OMAP2430_PRCM_CLKSSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094)
88#define OMAP2430_PRCM_POLCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098)
Paul Walmsley69d88a02008-03-18 10:02:50 +020089
Tony Lindgren8e3bd352009-05-25 11:26:42 -070090#define OMAP3_PRM_REVISION_OFFSET 0x0004
91#define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
92#define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014
93#define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
Paul Walmsley69d88a02008-03-18 10:02:50 +020094
Tony Lindgren8e3bd352009-05-25 11:26:42 -070095#define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018
96#define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
97#define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c
98#define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
Paul Walmsley69d88a02008-03-18 10:02:50 +020099
100
Tony Lindgren8e3bd352009-05-25 11:26:42 -0700101#define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020
102#define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
103#define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024
104#define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
105#define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028
106#define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
107#define OMAP3_PRM_VC_CMD_VAL_0_OFFSET 0x002c
108#define OMAP3430_PRM_VC_CMD_VAL_0 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
109#define OMAP3_PRM_VC_CMD_VAL_1_OFFSET 0x0030
110#define OMAP3430_PRM_VC_CMD_VAL_1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
111#define OMAP3_PRM_VC_CH_CONF_OFFSET 0x0034
112#define OMAP3430_PRM_VC_CH_CONF OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
113#define OMAP3_PRM_VC_I2C_CFG_OFFSET 0x0038
114#define OMAP3430_PRM_VC_I2C_CFG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
115#define OMAP3_PRM_VC_BYPASS_VAL_OFFSET 0x003c
116#define OMAP3430_PRM_VC_BYPASS_VAL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
117#define OMAP3_PRM_RSTCTRL_OFFSET 0x0050
118#define OMAP3430_PRM_RSTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
119#define OMAP3_PRM_RSTTIME_OFFSET 0x0054
120#define OMAP3430_PRM_RSTTIME OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
121#define OMAP3_PRM_RSTST_OFFSET 0x0058
122#define OMAP3430_PRM_RSTST OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
123#define OMAP3_PRM_VOLTCTRL_OFFSET 0x0060
124#define OMAP3430_PRM_VOLTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
125#define OMAP3_PRM_SRAM_PCHARGE_OFFSET 0x0064
126#define OMAP3430_PRM_SRAM_PCHARGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
127#define OMAP3_PRM_CLKSRC_CTRL_OFFSET 0x0070
128#define OMAP3430_PRM_CLKSRC_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
129#define OMAP3_PRM_VOLTSETUP1_OFFSET 0x0090
130#define OMAP3430_PRM_VOLTSETUP1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
131#define OMAP3_PRM_VOLTOFFSET_OFFSET 0x0094
132#define OMAP3430_PRM_VOLTOFFSET OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
133#define OMAP3_PRM_CLKSETUP_OFFSET 0x0098
134#define OMAP3430_PRM_CLKSETUP OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
135#define OMAP3_PRM_POLCTRL_OFFSET 0x009c
136#define OMAP3430_PRM_POLCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
137#define OMAP3_PRM_VOLTSETUP2_OFFSET 0x00a0
138#define OMAP3430_PRM_VOLTSETUP2 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
139#define OMAP3_PRM_VP1_CONFIG_OFFSET 0x00b0
140#define OMAP3430_PRM_VP1_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
141#define OMAP3_PRM_VP1_VSTEPMIN_OFFSET 0x00b4
142#define OMAP3430_PRM_VP1_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
143#define OMAP3_PRM_VP1_VSTEPMAX_OFFSET 0x00b8
144#define OMAP3430_PRM_VP1_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
145#define OMAP3_PRM_VP1_VLIMITTO_OFFSET 0x00bc
146#define OMAP3430_PRM_VP1_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
147#define OMAP3_PRM_VP1_VOLTAGE_OFFSET 0x00c0
148#define OMAP3430_PRM_VP1_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
149#define OMAP3_PRM_VP1_STATUS_OFFSET 0x00c4
150#define OMAP3430_PRM_VP1_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
151#define OMAP3_PRM_VP2_CONFIG_OFFSET 0x00d0
152#define OMAP3430_PRM_VP2_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
153#define OMAP3_PRM_VP2_VSTEPMIN_OFFSET 0x00d4
154#define OMAP3430_PRM_VP2_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
155#define OMAP3_PRM_VP2_VSTEPMAX_OFFSET 0x00d8
156#define OMAP3430_PRM_VP2_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
157#define OMAP3_PRM_VP2_VLIMITTO_OFFSET 0x00dc
158#define OMAP3430_PRM_VP2_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
159#define OMAP3_PRM_VP2_VOLTAGE_OFFSET 0x00e0
160#define OMAP3430_PRM_VP2_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
161#define OMAP3_PRM_VP2_STATUS_OFFSET 0x00e4
162#define OMAP3430_PRM_VP2_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200163
Tony Lindgren8e3bd352009-05-25 11:26:42 -0700164#define OMAP3_PRM_CLKSEL_OFFSET 0x0040
165#define OMAP3430_PRM_CLKSEL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
166#define OMAP3_PRM_CLKOUT_CTRL_OFFSET 0x0070
167#define OMAP3430_PRM_CLKOUT_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200168
169/*
170 * Module specific PRM registers from PRM_BASE + domain offset
171 *
172 * Use prm_{read,write}_mod_reg() with these registers.
173 *
174 * With a few exceptions, these are the register names beginning with
175 * {PM,RM}_* on both architectures. (The exceptions are the IRQSTATUS
176 * and IRQENABLE bits.)
177 *
178 */
179
180/* Registers appearing on both 24xx and 34xx */
181
182#define RM_RSTCTRL 0x0050
183#define RM_RSTTIME 0x0054
184#define RM_RSTST 0x0058
185
186#define PM_WKEN 0x00a0
187#define PM_WKEN1 PM_WKEN
188#define PM_WKST 0x00b0
189#define PM_WKST1 PM_WKST
190#define PM_WKDEP 0x00c8
191#define PM_EVGENCTRL 0x00d4
192#define PM_EVGENONTIM 0x00d8
193#define PM_EVGENOFFTIM 0x00dc
194#define PM_PWSTCTRL 0x00e0
195#define PM_PWSTST 0x00e4
196
Jouni Hogander027d8de2008-05-16 13:58:18 +0300197/* Omap2 specific registers */
198#define OMAP24XX_PM_WKEN2 0x00a4
199#define OMAP24XX_PM_WKST2 0x00b4
200
201#define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */
202#define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */
203#define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8
204#define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc
205
206/* Omap3 specific registers */
207#define OMAP3430ES2_PM_WKEN3 0x00f0
208#define OMAP3430ES2_PM_WKST3 0x00b8
209
Paul Walmsley69d88a02008-03-18 10:02:50 +0200210#define OMAP3430_PM_MPUGRPSEL 0x00a4
211#define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL
Kevin Hilmand3fd3292009-05-05 16:34:25 -0700212#define OMAP3430ES2_PM_MPUGRPSEL3 0x00f8
Paul Walmsley69d88a02008-03-18 10:02:50 +0200213
214#define OMAP3430_PM_IVAGRPSEL 0x00a8
215#define OMAP3430_PM_IVAGRPSEL1 OMAP3430_PM_IVAGRPSEL
Kevin Hilmand3fd3292009-05-05 16:34:25 -0700216#define OMAP3430ES2_PM_IVAGRPSEL3 0x00f4
Paul Walmsley69d88a02008-03-18 10:02:50 +0200217
218#define OMAP3430_PM_PREPWSTST 0x00e8
219
220#define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8
221#define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc
222
223
Paul Walmsley69d88a02008-03-18 10:02:50 +0200224#ifndef __ASSEMBLER__
225
226/* Power/reset management domain register get/set */
Tony Lindgrena58caad2008-07-03 12:24:44 +0300227extern u32 prm_read_mod_reg(s16 module, u16 idx);
228extern void prm_write_mod_reg(u32 val, s16 module, u16 idx);
Tony Lindgrenff00fcc2008-07-03 12:24:44 +0300229extern u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
230
231/* Read-modify-write bits in a PRM register (by domain) */
232static inline u32 prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
233{
234 return prm_rmw_mod_reg_bits(bits, bits, module, idx);
235}
236
237static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
238{
239 return prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
240}
Paul Walmsley69d88a02008-03-18 10:02:50 +0200241
242#endif
243
244/*
245 * Bits common to specific registers
246 *
247 * The 3430 register and bit names are generally used,
248 * since they tend to make more sense
249 */
250
251/* PM_EVGENONTIM_MPU */
252/* Named PM_EVEGENONTIM_MPU on the 24XX */
253#define OMAP_ONTIMEVAL_SHIFT 0
254#define OMAP_ONTIMEVAL_MASK (0xffffffff << 0)
255
256/* PM_EVGENOFFTIM_MPU */
257/* Named PM_EVEGENOFFTIM_MPU on the 24XX */
258#define OMAP_OFFTIMEVAL_SHIFT 0
259#define OMAP_OFFTIMEVAL_MASK (0xffffffff << 0)
260
261/* PRM_CLKSETUP and PRCM_VOLTSETUP */
262/* Named PRCM_CLKSSETUP on the 24XX */
263#define OMAP_SETUP_TIME_SHIFT 0
264#define OMAP_SETUP_TIME_MASK (0xffff << 0)
265
266/* PRM_CLKSRC_CTRL */
267/* Named PRCM_CLKSRC_CTRL on the 24XX */
268#define OMAP_SYSCLKDIV_SHIFT 6
269#define OMAP_SYSCLKDIV_MASK (0x3 << 6)
270#define OMAP_AUTOEXTCLKMODE_SHIFT 3
271#define OMAP_AUTOEXTCLKMODE_MASK (0x3 << 3)
272#define OMAP_SYSCLKSEL_SHIFT 0
273#define OMAP_SYSCLKSEL_MASK (0x3 << 0)
274
275/* PM_EVGENCTRL_MPU */
276#define OMAP_OFFLOADMODE_SHIFT 3
277#define OMAP_OFFLOADMODE_MASK (0x3 << 3)
278#define OMAP_ONLOADMODE_SHIFT 1
279#define OMAP_ONLOADMODE_MASK (0x3 << 1)
280#define OMAP_ENABLE (1 << 0)
281
282/* PRM_RSTTIME */
283/* Named RM_RSTTIME_WKUP on the 24xx */
284#define OMAP_RSTTIME2_SHIFT 8
285#define OMAP_RSTTIME2_MASK (0x1f << 8)
286#define OMAP_RSTTIME1_SHIFT 0
287#define OMAP_RSTTIME1_MASK (0xff << 0)
288
Paul Walmsley69d88a02008-03-18 10:02:50 +0200289/* PRM_RSTCTRL */
290/* Named RM_RSTCTRL_WKUP on the 24xx */
291/* 2420 calls RST_DPLL3 'RST_DPLL' */
292#define OMAP_RST_DPLL3 (1 << 2)
293#define OMAP_RST_GS (1 << 1)
294
295
296/*
297 * Bits common to module-shared registers
298 *
299 * Not all registers of a particular type support all of these bits -
300 * check TRM if you are unsure
301 */
302
303/*
304 * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP
305 *
306 * 2430: PM_PWSTST_MDM
307 *
308 * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
309 * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
310 * PM_PWSTST_NEON
311 */
312#define OMAP_INTRANSITION (1 << 20)
313
314
315/*
316 * 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP
317 *
318 * 2430: PM_PWSTST_MDM
319 *
320 * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
321 * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
322 * PM_PWSTST_NEON
323 */
324#define OMAP_POWERSTATEST_SHIFT 0
325#define OMAP_POWERSTATEST_MASK (0x3 << 0)
326
327/*
328 * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is
329 * called 'COREWKUP_RST'
330 *
331 * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
332 * RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
333 */
334#define OMAP_COREDOMAINWKUP_RST (1 << 3)
335
336/*
337 * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
338 *
339 * 2430: RM_RSTST_MDM
340 *
341 * 3430: RM_RSTST_CORE, RM_RSTST_EMU
342 */
343#define OMAP_DOMAINWKUP_RST (1 << 2)
344
345/*
346 * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
347 * On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'.
348 *
349 * 2430: RM_RSTST_MDM
350 *
351 * 3430: RM_RSTST_CORE, RM_RSTST_EMU
352 */
353#define OMAP_GLOBALWARM_RST (1 << 1)
354#define OMAP_GLOBALCOLD_RST (1 << 0)
355
356/*
357 * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
358 * 2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP"
359 *
360 * 2430: PM_WKDEP_MDM
361 *
362 * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
363 * PM_WKDEP_PER
364 */
Paul Walmsley97171002008-08-19 11:08:40 +0300365#define OMAP_EN_WKUP_SHIFT 4
366#define OMAP_EN_WKUP_MASK (1 << 4)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200367
368/*
369 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
370 * PM_PWSTCTRL_DSP
371 *
372 * 2430: PM_PWSTCTRL_MDM
373 *
374 * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
375 * PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
376 * PM_PWSTCTRL_NEON
377 */
378#define OMAP_LOGICRETSTATE (1 << 2)
379
380/*
381 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
382 * PM_PWSTCTRL_DSP, PM_PWSTST_MPU
383 *
384 * 2430: PM_PWSTCTRL_MDM shared bits
385 *
386 * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE,
387 * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
388 * PM_PWSTCTRL_NEON shared bits
389 */
390#define OMAP_POWERSTATE_SHIFT 0
391#define OMAP_POWERSTATE_MASK (0x3 << 0)
392
393
394#endif