Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file contains work-arounds for many known PCI hardware |
| 3 | * bugs. Devices present only on certain architectures (host |
| 4 | * bridges et cetera) should be handled in arch-specific code. |
| 5 | * |
| 6 | * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. |
| 7 | * |
| 8 | * Copyright (c) 1999 Martin Mares <mj@ucw.cz> |
| 9 | * |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 10 | * Init/reset quirks for USB host controllers should be in the |
| 11 | * USB quirks file, where their drivers can access reuse it. |
| 12 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13 | * The bridge optimization stuff has been removed. If you really |
| 14 | * have a silly BIOS which is unable to set your host bridge right, |
| 15 | * use the PowerTweak utility (see http://powertweak.sourceforge.net). |
| 16 | */ |
| 17 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 18 | #include <linux/types.h> |
| 19 | #include <linux/kernel.h> |
| 20 | #include <linux/pci.h> |
| 21 | #include <linux/init.h> |
| 22 | #include <linux/delay.h> |
Len Brown | 25be5e6 | 2005-05-27 04:21:50 -0400 | [diff] [blame] | 23 | #include <linux/acpi.h> |
Greg KH | bc56b9e | 2005-04-08 14:53:31 +0900 | [diff] [blame] | 24 | #include "pci.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 25 | |
Doug Thompson | bd8481e | 2006-05-08 17:06:09 -0700 | [diff] [blame] | 26 | /* The Mellanox Tavor device gives false positive parity errors |
| 27 | * Mark this device with a broken_parity_status, to allow |
| 28 | * PCI scanning code to "skip" this now blacklisted device. |
| 29 | */ |
| 30 | static void __devinit quirk_mellanox_tavor(struct pci_dev *dev) |
| 31 | { |
| 32 | dev->broken_parity_status = 1; /* This device gives false positives */ |
| 33 | } |
| 34 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor); |
| 35 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor); |
| 36 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 37 | /* Deal with broken BIOS'es that neglect to enable passive release, |
| 38 | which can cause problems in combination with the 82441FX/PPro MTRRs */ |
| 39 | static void __devinit quirk_passive_release(struct pci_dev *dev) |
| 40 | { |
| 41 | struct pci_dev *d = NULL; |
| 42 | unsigned char dlc; |
| 43 | |
| 44 | /* We have to make sure a particular bit is set in the PIIX3 |
| 45 | ISA bridge, so we have to go out and find it. */ |
| 46 | while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { |
| 47 | pci_read_config_byte(d, 0x82, &dlc); |
| 48 | if (!(dlc & 1<<1)) { |
| 49 | printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d)); |
| 50 | dlc |= 1<<1; |
| 51 | pci_write_config_byte(d, 0x82, dlc); |
| 52 | } |
| 53 | } |
| 54 | } |
| 55 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release ); |
| 56 | |
| 57 | /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround |
| 58 | but VIA don't answer queries. If you happen to have good contacts at VIA |
| 59 | ask them for me please -- Alan |
| 60 | |
| 61 | This appears to be BIOS not version dependent. So presumably there is a |
| 62 | chipset level fix */ |
| 63 | int isa_dma_bridge_buggy; /* Exported */ |
| 64 | |
| 65 | static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev) |
| 66 | { |
| 67 | if (!isa_dma_bridge_buggy) { |
| 68 | isa_dma_bridge_buggy=1; |
| 69 | printk(KERN_INFO "Activating ISA DMA hang workarounds.\n"); |
| 70 | } |
| 71 | } |
| 72 | /* |
| 73 | * Its not totally clear which chipsets are the problematic ones |
| 74 | * We know 82C586 and 82C596 variants are affected. |
| 75 | */ |
| 76 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs ); |
| 77 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs ); |
| 78 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs ); |
| 79 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs ); |
| 80 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs ); |
| 81 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs ); |
| 82 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs ); |
| 83 | |
| 84 | int pci_pci_problems; |
| 85 | |
| 86 | /* |
| 87 | * Chipsets where PCI->PCI transfers vanish or hang |
| 88 | */ |
| 89 | static void __devinit quirk_nopcipci(struct pci_dev *dev) |
| 90 | { |
| 91 | if ((pci_pci_problems & PCIPCI_FAIL)==0) { |
| 92 | printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n"); |
| 93 | pci_pci_problems |= PCIPCI_FAIL; |
| 94 | } |
| 95 | } |
Alan Cox | 236561e | 2006-09-30 23:27:03 -0700 | [diff] [blame] | 96 | |
| 97 | static void __devinit quirk_nopciamd(struct pci_dev *dev) |
| 98 | { |
| 99 | u8 rev; |
| 100 | pci_read_config_byte(dev, 0x08, &rev); |
| 101 | if (rev == 0x13) { |
| 102 | /* Erratum 24 */ |
| 103 | printk(KERN_INFO "Chipset erratum: Disabling direct PCI/AGP transfers.\n"); |
| 104 | pci_pci_problems |= PCIAGP_FAIL; |
| 105 | } |
| 106 | } |
| 107 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 108 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci ); |
| 109 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci ); |
Alan Cox | 236561e | 2006-09-30 23:27:03 -0700 | [diff] [blame] | 110 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 111 | |
| 112 | /* |
| 113 | * Triton requires workarounds to be used by the drivers |
| 114 | */ |
| 115 | static void __devinit quirk_triton(struct pci_dev *dev) |
| 116 | { |
| 117 | if ((pci_pci_problems&PCIPCI_TRITON)==0) { |
| 118 | printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); |
| 119 | pci_pci_problems |= PCIPCI_TRITON; |
| 120 | } |
| 121 | } |
| 122 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton ); |
| 123 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton ); |
| 124 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton ); |
| 125 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton ); |
| 126 | |
| 127 | /* |
| 128 | * VIA Apollo KT133 needs PCI latency patch |
| 129 | * Made according to a windows driver based patch by George E. Breese |
| 130 | * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm |
| 131 | * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for |
| 132 | * the info on which Mr Breese based his work. |
| 133 | * |
| 134 | * Updated based on further information from the site and also on |
| 135 | * information provided by VIA |
| 136 | */ |
| 137 | static void __devinit quirk_vialatency(struct pci_dev *dev) |
| 138 | { |
| 139 | struct pci_dev *p; |
| 140 | u8 rev; |
| 141 | u8 busarb; |
| 142 | /* Ok we have a potential problem chipset here. Now see if we have |
| 143 | a buggy southbridge */ |
| 144 | |
| 145 | p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); |
| 146 | if (p!=NULL) { |
| 147 | pci_read_config_byte(p, PCI_CLASS_REVISION, &rev); |
| 148 | /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */ |
| 149 | /* Check for buggy part revisions */ |
| 150 | if (rev < 0x40 || rev > 0x42) |
| 151 | goto exit; |
| 152 | } else { |
| 153 | p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); |
| 154 | if (p==NULL) /* No problem parts */ |
| 155 | goto exit; |
| 156 | pci_read_config_byte(p, PCI_CLASS_REVISION, &rev); |
| 157 | /* Check for buggy part revisions */ |
| 158 | if (rev < 0x10 || rev > 0x12) |
| 159 | goto exit; |
| 160 | } |
| 161 | |
| 162 | /* |
| 163 | * Ok we have the problem. Now set the PCI master grant to |
| 164 | * occur every master grant. The apparent bug is that under high |
| 165 | * PCI load (quite common in Linux of course) you can get data |
| 166 | * loss when the CPU is held off the bus for 3 bus master requests |
| 167 | * This happens to include the IDE controllers.... |
| 168 | * |
| 169 | * VIA only apply this fix when an SB Live! is present but under |
| 170 | * both Linux and Windows this isnt enough, and we have seen |
| 171 | * corruption without SB Live! but with things like 3 UDMA IDE |
| 172 | * controllers. So we ignore that bit of the VIA recommendation.. |
| 173 | */ |
| 174 | |
| 175 | pci_read_config_byte(dev, 0x76, &busarb); |
| 176 | /* Set bit 4 and bi 5 of byte 76 to 0x01 |
| 177 | "Master priority rotation on every PCI master grant */ |
| 178 | busarb &= ~(1<<5); |
| 179 | busarb |= (1<<4); |
| 180 | pci_write_config_byte(dev, 0x76, busarb); |
| 181 | printk(KERN_INFO "Applying VIA southbridge workaround.\n"); |
| 182 | exit: |
| 183 | pci_dev_put(p); |
| 184 | } |
| 185 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency ); |
| 186 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency ); |
| 187 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency ); |
| 188 | |
| 189 | /* |
| 190 | * VIA Apollo VP3 needs ETBF on BT848/878 |
| 191 | */ |
| 192 | static void __devinit quirk_viaetbf(struct pci_dev *dev) |
| 193 | { |
| 194 | if ((pci_pci_problems&PCIPCI_VIAETBF)==0) { |
| 195 | printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); |
| 196 | pci_pci_problems |= PCIPCI_VIAETBF; |
| 197 | } |
| 198 | } |
| 199 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf ); |
| 200 | |
| 201 | static void __devinit quirk_vsfx(struct pci_dev *dev) |
| 202 | { |
| 203 | if ((pci_pci_problems&PCIPCI_VSFX)==0) { |
| 204 | printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); |
| 205 | pci_pci_problems |= PCIPCI_VSFX; |
| 206 | } |
| 207 | } |
| 208 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx ); |
| 209 | |
| 210 | /* |
| 211 | * Ali Magik requires workarounds to be used by the drivers |
| 212 | * that DMA to AGP space. Latency must be set to 0xA and triton |
| 213 | * workaround applied too |
| 214 | * [Info kindly provided by ALi] |
| 215 | */ |
| 216 | static void __init quirk_alimagik(struct pci_dev *dev) |
| 217 | { |
| 218 | if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) { |
| 219 | printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); |
| 220 | pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; |
| 221 | } |
| 222 | } |
| 223 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik ); |
| 224 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik ); |
| 225 | |
| 226 | /* |
| 227 | * Natoma has some interesting boundary conditions with Zoran stuff |
| 228 | * at least |
| 229 | */ |
| 230 | static void __devinit quirk_natoma(struct pci_dev *dev) |
| 231 | { |
| 232 | if ((pci_pci_problems&PCIPCI_NATOMA)==0) { |
| 233 | printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); |
| 234 | pci_pci_problems |= PCIPCI_NATOMA; |
| 235 | } |
| 236 | } |
| 237 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma ); |
| 238 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma ); |
| 239 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma ); |
| 240 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma ); |
| 241 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma ); |
| 242 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma ); |
| 243 | |
| 244 | /* |
| 245 | * This chip can cause PCI parity errors if config register 0xA0 is read |
| 246 | * while DMAs are occurring. |
| 247 | */ |
| 248 | static void __devinit quirk_citrine(struct pci_dev *dev) |
| 249 | { |
| 250 | dev->cfg_size = 0xA0; |
| 251 | } |
| 252 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine ); |
| 253 | |
| 254 | /* |
| 255 | * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. |
| 256 | * If it's needed, re-allocate the region. |
| 257 | */ |
| 258 | static void __devinit quirk_s3_64M(struct pci_dev *dev) |
| 259 | { |
| 260 | struct resource *r = &dev->resource[0]; |
| 261 | |
| 262 | if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { |
| 263 | r->start = 0; |
| 264 | r->end = 0x3ffffff; |
| 265 | } |
| 266 | } |
| 267 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M ); |
| 268 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M ); |
| 269 | |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 270 | static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region, |
| 271 | unsigned size, int nr, const char *name) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 272 | { |
| 273 | region &= ~(size-1); |
| 274 | if (region) { |
David S. Miller | 085ae41 | 2005-08-08 13:19:08 -0700 | [diff] [blame] | 275 | struct pci_bus_region bus_region; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 276 | struct resource *res = dev->resource + nr; |
| 277 | |
| 278 | res->name = pci_name(dev); |
| 279 | res->start = region; |
| 280 | res->end = region + size - 1; |
| 281 | res->flags = IORESOURCE_IO; |
David S. Miller | 085ae41 | 2005-08-08 13:19:08 -0700 | [diff] [blame] | 282 | |
| 283 | /* Convert from PCI bus to resource space. */ |
| 284 | bus_region.start = res->start; |
| 285 | bus_region.end = res->end; |
| 286 | pcibios_bus_to_resource(dev, res, &bus_region); |
| 287 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 288 | pci_claim_resource(dev, nr); |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 289 | printk("PCI quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 290 | } |
| 291 | } |
| 292 | |
| 293 | /* |
| 294 | * ATI Northbridge setups MCE the processor if you even |
| 295 | * read somewhere between 0x3b0->0x3bb or read 0x3d3 |
| 296 | */ |
| 297 | static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev) |
| 298 | { |
| 299 | printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n"); |
| 300 | /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ |
| 301 | request_region(0x3b0, 0x0C, "RadeonIGP"); |
| 302 | request_region(0x3d3, 0x01, "RadeonIGP"); |
| 303 | } |
| 304 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce ); |
| 305 | |
| 306 | /* |
| 307 | * Let's make the southbridge information explicit instead |
| 308 | * of having to worry about people probing the ACPI areas, |
| 309 | * for example.. (Yes, it happens, and if you read the wrong |
| 310 | * ACPI register it will put the machine to sleep with no |
| 311 | * way of waking it up again. Bummer). |
| 312 | * |
| 313 | * ALI M7101: Two IO regions pointed to by words at |
| 314 | * 0xE0 (64 bytes of ACPI registers) |
| 315 | * 0xE2 (32 bytes of SMB registers) |
| 316 | */ |
| 317 | static void __devinit quirk_ali7101_acpi(struct pci_dev *dev) |
| 318 | { |
| 319 | u16 region; |
| 320 | |
| 321 | pci_read_config_word(dev, 0xE0, ®ion); |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 322 | quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 323 | pci_read_config_word(dev, 0xE2, ®ion); |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 324 | quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 325 | } |
| 326 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi ); |
| 327 | |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 328 | static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) |
| 329 | { |
| 330 | u32 devres; |
| 331 | u32 mask, size, base; |
| 332 | |
| 333 | pci_read_config_dword(dev, port, &devres); |
| 334 | if ((devres & enable) != enable) |
| 335 | return; |
| 336 | mask = (devres >> 16) & 15; |
| 337 | base = devres & 0xffff; |
| 338 | size = 16; |
| 339 | for (;;) { |
| 340 | unsigned bit = size >> 1; |
| 341 | if ((bit & mask) == bit) |
| 342 | break; |
| 343 | size = bit; |
| 344 | } |
| 345 | /* |
| 346 | * For now we only print it out. Eventually we'll want to |
| 347 | * reserve it (at least if it's in the 0x1000+ range), but |
| 348 | * let's get enough confirmation reports first. |
| 349 | */ |
| 350 | base &= -size; |
| 351 | printk("%s PIO at %04x-%04x\n", name, base, base + size - 1); |
| 352 | } |
| 353 | |
| 354 | static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) |
| 355 | { |
| 356 | u32 devres; |
| 357 | u32 mask, size, base; |
| 358 | |
| 359 | pci_read_config_dword(dev, port, &devres); |
| 360 | if ((devres & enable) != enable) |
| 361 | return; |
| 362 | base = devres & 0xffff0000; |
| 363 | mask = (devres & 0x3f) << 16; |
| 364 | size = 128 << 16; |
| 365 | for (;;) { |
| 366 | unsigned bit = size >> 1; |
| 367 | if ((bit & mask) == bit) |
| 368 | break; |
| 369 | size = bit; |
| 370 | } |
| 371 | /* |
| 372 | * For now we only print it out. Eventually we'll want to |
| 373 | * reserve it, but let's get enough confirmation reports first. |
| 374 | */ |
| 375 | base &= -size; |
| 376 | printk("%s MMIO at %04x-%04x\n", name, base, base + size - 1); |
| 377 | } |
| 378 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 379 | /* |
| 380 | * PIIX4 ACPI: Two IO regions pointed to by longwords at |
| 381 | * 0x40 (64 bytes of ACPI registers) |
Linus Torvalds | 08db2a7 | 2005-10-30 14:40:07 -0800 | [diff] [blame] | 382 | * 0x90 (16 bytes of SMB registers) |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 383 | * and a few strange programmable PIIX4 device resources. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 384 | */ |
| 385 | static void __devinit quirk_piix4_acpi(struct pci_dev *dev) |
| 386 | { |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 387 | u32 region, res_a; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 388 | |
| 389 | pci_read_config_dword(dev, 0x40, ®ion); |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 390 | quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 391 | pci_read_config_dword(dev, 0x90, ®ion); |
Linus Torvalds | 08db2a7 | 2005-10-30 14:40:07 -0800 | [diff] [blame] | 392 | quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 393 | |
| 394 | /* Device resource A has enables for some of the other ones */ |
| 395 | pci_read_config_dword(dev, 0x5c, &res_a); |
| 396 | |
| 397 | piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); |
| 398 | piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); |
| 399 | |
| 400 | /* Device resource D is just bitfields for static resources */ |
| 401 | |
| 402 | /* Device 12 enabled? */ |
| 403 | if (res_a & (1 << 29)) { |
| 404 | piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); |
| 405 | piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); |
| 406 | } |
| 407 | /* Device 13 enabled? */ |
| 408 | if (res_a & (1 << 30)) { |
| 409 | piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); |
| 410 | piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); |
| 411 | } |
| 412 | piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); |
| 413 | piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 414 | } |
| 415 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi ); |
Linus Torvalds | c676466 | 2006-07-12 08:29:46 -0700 | [diff] [blame] | 416 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 417 | |
| 418 | /* |
| 419 | * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at |
| 420 | * 0x40 (128 bytes of ACPI, GPIO & TCO registers) |
| 421 | * 0x58 (64 bytes of GPIO I/O space) |
| 422 | */ |
| 423 | static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev) |
| 424 | { |
| 425 | u32 region; |
| 426 | |
| 427 | pci_read_config_dword(dev, 0x40, ®ion); |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 428 | quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 429 | |
| 430 | pci_read_config_dword(dev, 0x58, ®ion); |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 431 | quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 432 | } |
| 433 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi ); |
| 434 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi ); |
| 435 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi ); |
| 436 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi ); |
| 437 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi ); |
| 438 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi ); |
| 439 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi ); |
| 440 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi ); |
| 441 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi ); |
R.Marek@sh.cvut.cz | 3aa8c4f | 2005-04-21 10:49:06 +0000 | [diff] [blame] | 442 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 443 | |
R.Marek@sh.cvut.cz | 2cea752 | 2005-09-27 21:54:51 +0000 | [diff] [blame] | 444 | static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev) |
| 445 | { |
| 446 | u32 region; |
| 447 | |
| 448 | pci_read_config_dword(dev, 0x40, ®ion); |
| 449 | quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO"); |
| 450 | |
| 451 | pci_read_config_dword(dev, 0x48, ®ion); |
| 452 | quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO"); |
| 453 | } |
Daniel Ritz | 65ae4dd | 2006-08-22 07:29:10 -0700 | [diff] [blame] | 454 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc_acpi ); |
R.Marek@sh.cvut.cz | 2cea752 | 2005-09-27 21:54:51 +0000 | [diff] [blame] | 455 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi ); |
Daniel Ritz | bacedce | 2006-09-25 16:52:21 -0700 | [diff] [blame] | 456 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich6_lpc_acpi ); |
| 457 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich6_lpc_acpi ); |
| 458 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich6_lpc_acpi ); |
| 459 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich6_lpc_acpi ); |
| 460 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich6_lpc_acpi ); |
| 461 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich6_lpc_acpi ); |
R.Marek@sh.cvut.cz | 2cea752 | 2005-09-27 21:54:51 +0000 | [diff] [blame] | 462 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 463 | /* |
| 464 | * VIA ACPI: One IO region pointed to by longword at |
| 465 | * 0x48 or 0x20 (256 bytes of ACPI registers) |
| 466 | */ |
| 467 | static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev) |
| 468 | { |
| 469 | u8 rev; |
| 470 | u32 region; |
| 471 | |
| 472 | pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev); |
| 473 | if (rev & 0x10) { |
| 474 | pci_read_config_dword(dev, 0x48, ®ion); |
| 475 | region &= PCI_BASE_ADDRESS_IO_MASK; |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 476 | quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 477 | } |
| 478 | } |
| 479 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi ); |
| 480 | |
| 481 | /* |
| 482 | * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at |
| 483 | * 0x48 (256 bytes of ACPI registers) |
| 484 | * 0x70 (128 bytes of hardware monitoring register) |
| 485 | * 0x90 (16 bytes of SMB registers) |
| 486 | */ |
| 487 | static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev) |
| 488 | { |
| 489 | u16 hm; |
| 490 | u32 smb; |
| 491 | |
| 492 | quirk_vt82c586_acpi(dev); |
| 493 | |
| 494 | pci_read_config_word(dev, 0x70, &hm); |
| 495 | hm &= PCI_BASE_ADDRESS_IO_MASK; |
Meelis Roos | 02f313b | 2005-10-29 13:31:49 +0300 | [diff] [blame] | 496 | quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 497 | |
| 498 | pci_read_config_dword(dev, 0x90, &smb); |
| 499 | smb &= PCI_BASE_ADDRESS_IO_MASK; |
Meelis Roos | 02f313b | 2005-10-29 13:31:49 +0300 | [diff] [blame] | 500 | quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 501 | } |
| 502 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi ); |
| 503 | |
Ivan Kokshaysky | 6d85f29 | 2005-08-08 12:55:54 +0400 | [diff] [blame] | 504 | /* |
| 505 | * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at |
| 506 | * 0x88 (128 bytes of power management registers) |
| 507 | * 0xd0 (16 bytes of SMB registers) |
| 508 | */ |
| 509 | static void __devinit quirk_vt8235_acpi(struct pci_dev *dev) |
| 510 | { |
| 511 | u16 pm, smb; |
| 512 | |
| 513 | pci_read_config_word(dev, 0x88, &pm); |
| 514 | pm &= PCI_BASE_ADDRESS_IO_MASK; |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 515 | quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); |
Ivan Kokshaysky | 6d85f29 | 2005-08-08 12:55:54 +0400 | [diff] [blame] | 516 | |
| 517 | pci_read_config_word(dev, 0xd0, &smb); |
| 518 | smb &= PCI_BASE_ADDRESS_IO_MASK; |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 519 | quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB"); |
Ivan Kokshaysky | 6d85f29 | 2005-08-08 12:55:54 +0400 | [diff] [blame] | 520 | } |
| 521 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); |
| 522 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 523 | |
| 524 | #ifdef CONFIG_X86_IO_APIC |
| 525 | |
| 526 | #include <asm/io_apic.h> |
| 527 | |
| 528 | /* |
| 529 | * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip |
| 530 | * devices to the external APIC. |
| 531 | * |
| 532 | * TODO: When we have device-specific interrupt routers, |
| 533 | * this code will go away from quirks. |
| 534 | */ |
| 535 | static void __devinit quirk_via_ioapic(struct pci_dev *dev) |
| 536 | { |
| 537 | u8 tmp; |
| 538 | |
| 539 | if (nr_ioapics < 1) |
| 540 | tmp = 0; /* nothing routed to external APIC */ |
| 541 | else |
| 542 | tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ |
| 543 | |
| 544 | printk(KERN_INFO "PCI: %sbling Via external APIC routing\n", |
| 545 | tmp == 0 ? "Disa" : "Ena"); |
| 546 | |
| 547 | /* Offset 0x58: External APIC IRQ output control */ |
| 548 | pci_write_config_byte (dev, 0x58, tmp); |
| 549 | } |
| 550 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic ); |
| 551 | |
| 552 | /* |
Karsten Wiese | a174091 | 2005-09-03 15:56:33 -0700 | [diff] [blame] | 553 | * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit. |
| 554 | * This leads to doubled level interrupt rates. |
| 555 | * Set this bit to get rid of cycle wastage. |
| 556 | * Otherwise uncritical. |
| 557 | */ |
| 558 | static void __devinit quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) |
| 559 | { |
| 560 | u8 misc_control2; |
| 561 | #define BYPASS_APIC_DEASSERT 8 |
| 562 | |
| 563 | pci_read_config_byte(dev, 0x5B, &misc_control2); |
| 564 | if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { |
| 565 | printk(KERN_INFO "PCI: Bypassing VIA 8237 APIC De-Assert Message\n"); |
| 566 | pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); |
| 567 | } |
| 568 | } |
| 569 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); |
| 570 | |
| 571 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 572 | * The AMD io apic can hang the box when an apic irq is masked. |
| 573 | * We check all revs >= B0 (yet not in the pre production!) as the bug |
| 574 | * is currently marked NoFix |
| 575 | * |
| 576 | * We have multiple reports of hangs with this chipset that went away with |
Alan Cox | 236561e | 2006-09-30 23:27:03 -0700 | [diff] [blame] | 577 | * noapic specified. For the moment we assume it's the erratum. We may be wrong |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 578 | * of course. However the advice is demonstrably good even if so.. |
| 579 | */ |
| 580 | static void __devinit quirk_amd_ioapic(struct pci_dev *dev) |
| 581 | { |
| 582 | u8 rev; |
| 583 | |
| 584 | pci_read_config_byte(dev, PCI_REVISION_ID, &rev); |
| 585 | if (rev >= 0x02) { |
Alan Cox | 236561e | 2006-09-30 23:27:03 -0700 | [diff] [blame] | 586 | printk(KERN_WARNING "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 587 | printk(KERN_WARNING " : booting with the \"noapic\" option.\n"); |
| 588 | } |
| 589 | } |
| 590 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic ); |
| 591 | |
| 592 | static void __init quirk_ioapic_rmw(struct pci_dev *dev) |
| 593 | { |
| 594 | if (dev->devfn == 0 && dev->bus->number == 0) |
| 595 | sis_apic_bug = 1; |
| 596 | } |
| 597 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw ); |
| 598 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 599 | #define AMD8131_revA0 0x01 |
| 600 | #define AMD8131_revB0 0x11 |
| 601 | #define AMD8131_MISC 0x40 |
| 602 | #define AMD8131_NIOAMODE_BIT 0 |
| 603 | static void __init quirk_amd_8131_ioapic(struct pci_dev *dev) |
| 604 | { |
| 605 | unsigned char revid, tmp; |
| 606 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 607 | if (nr_ioapics == 0) |
| 608 | return; |
| 609 | |
| 610 | pci_read_config_byte(dev, PCI_REVISION_ID, &revid); |
| 611 | if (revid == AMD8131_revA0 || revid == AMD8131_revB0) { |
| 612 | printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n"); |
| 613 | pci_read_config_byte( dev, AMD8131_MISC, &tmp); |
| 614 | tmp &= ~(1 << AMD8131_NIOAMODE_BIT); |
| 615 | pci_write_config_byte( dev, AMD8131_MISC, tmp); |
| 616 | } |
| 617 | } |
John W. Linville | 5da594b | 2006-03-20 14:33:56 -0500 | [diff] [blame] | 618 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 619 | #endif /* CONFIG_X86_IO_APIC */ |
| 620 | |
| 621 | |
| 622 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 623 | * FIXME: it is questionable that quirk_via_acpi |
| 624 | * is needed. It shows up as an ISA bridge, and does not |
| 625 | * support the PCI_INTERRUPT_LINE register at all. Therefore |
| 626 | * it seems like setting the pci_dev's 'irq' to the |
| 627 | * value of the ACPI SCI interrupt is only done for convenience. |
| 628 | * -jgarzik |
| 629 | */ |
| 630 | static void __devinit quirk_via_acpi(struct pci_dev *d) |
| 631 | { |
| 632 | /* |
| 633 | * VIA ACPI device: SCI IRQ line in PCI config byte 0x42 |
| 634 | */ |
| 635 | u8 irq; |
| 636 | pci_read_config_byte(d, 0x42, &irq); |
| 637 | irq &= 0xf; |
| 638 | if (irq && (irq != 2)) |
| 639 | d->irq = irq; |
| 640 | } |
| 641 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi ); |
| 642 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi ); |
| 643 | |
Bjorn Helgaas | 93cffff | 2005-06-07 13:22:18 -0700 | [diff] [blame] | 644 | /* |
| 645 | * Via 686A/B: The PCI_INTERRUPT_LINE register for the on-chip |
| 646 | * devices, USB0/1, AC97, MC97, and ACPI, has an unusual feature: |
| 647 | * when written, it makes an internal connection to the PIC. |
| 648 | * For these devices, this register is defined to be 4 bits wide. |
| 649 | * Normally this is fine. However for IO-APIC motherboards, or |
| 650 | * non-x86 architectures (yes Via exists on PPC among other places), |
| 651 | * we must mask the PCI_INTERRUPT_LINE value versus 0xf to get |
| 652 | * interrupts delivered properly. |
Chris Wedgwood | a7b862f | 2006-05-15 09:43:55 -0700 | [diff] [blame] | 653 | * |
| 654 | * Some of the on-chip devices are actually '586 devices' so they are |
| 655 | * listed here. |
Bjorn Helgaas | 93cffff | 2005-06-07 13:22:18 -0700 | [diff] [blame] | 656 | */ |
Daniel Drake | 09d6029 | 2006-09-25 16:52:19 -0700 | [diff] [blame] | 657 | |
| 658 | static int via_irq_fixup_needed = -1; |
| 659 | |
| 660 | /* |
| 661 | * As some VIA hardware is available in PCI-card form, we need to restrict |
| 662 | * this quirk to VIA PCI hardware built onto VIA-based motherboards only. |
| 663 | * We try to locate a VIA southbridge before deciding whether the quirk |
| 664 | * should be applied. |
| 665 | */ |
| 666 | static const struct pci_device_id via_irq_fixup_tbl[] = { |
| 667 | { |
| 668 | .vendor = PCI_VENDOR_ID_VIA, |
| 669 | .device = PCI_ANY_ID, |
| 670 | .subvendor = PCI_ANY_ID, |
| 671 | .subdevice = PCI_ANY_ID, |
| 672 | .class = PCI_CLASS_BRIDGE_ISA << 8, |
| 673 | .class_mask = 0xffff00, |
| 674 | }, |
| 675 | { 0, }, |
| 676 | }; |
| 677 | |
Bjorn Helgaas | 93cffff | 2005-06-07 13:22:18 -0700 | [diff] [blame] | 678 | static void quirk_via_irq(struct pci_dev *dev) |
Len Brown | 25be5e6 | 2005-05-27 04:21:50 -0400 | [diff] [blame] | 679 | { |
| 680 | u8 irq, new_irq; |
| 681 | |
Daniel Drake | 09d6029 | 2006-09-25 16:52:19 -0700 | [diff] [blame] | 682 | if (via_irq_fixup_needed == -1) |
| 683 | via_irq_fixup_needed = pci_dev_present(via_irq_fixup_tbl); |
| 684 | |
| 685 | if (!via_irq_fixup_needed) |
| 686 | return; |
| 687 | |
| 688 | new_irq = dev->irq; |
| 689 | |
| 690 | /* Don't quirk interrupts outside the legacy IRQ range */ |
| 691 | if (!new_irq || new_irq > 15) |
| 692 | return; |
| 693 | |
Len Brown | 25be5e6 | 2005-05-27 04:21:50 -0400 | [diff] [blame] | 694 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); |
| 695 | if (new_irq != irq) { |
Chris Wedgwood | 75cf745 | 2006-04-18 23:57:09 -0700 | [diff] [blame] | 696 | printk(KERN_INFO "PCI: VIA IRQ fixup for %s, from %d to %d\n", |
Len Brown | 25be5e6 | 2005-05-27 04:21:50 -0400 | [diff] [blame] | 697 | pci_name(dev), irq, new_irq); |
| 698 | udelay(15); /* unknown if delay really needed */ |
| 699 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); |
| 700 | } |
| 701 | } |
Daniel Drake | 09d6029 | 2006-09-25 16:52:19 -0700 | [diff] [blame] | 702 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_irq); |
Len Brown | 25be5e6 | 2005-05-27 04:21:50 -0400 | [diff] [blame] | 703 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 704 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 705 | * VIA VT82C598 has its device ID settable and many BIOSes |
| 706 | * set it to the ID of VT82C597 for backward compatibility. |
| 707 | * We need to switch it off to be able to recognize the real |
| 708 | * type of the chip. |
| 709 | */ |
| 710 | static void __devinit quirk_vt82c598_id(struct pci_dev *dev) |
| 711 | { |
| 712 | pci_write_config_byte(dev, 0xfc, 0); |
| 713 | pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); |
| 714 | } |
| 715 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id ); |
| 716 | |
| 717 | /* |
| 718 | * CardBus controllers have a legacy base address that enables them |
| 719 | * to respond as i82365 pcmcia controllers. We don't want them to |
| 720 | * do this even if the Linux CardBus driver is not loaded, because |
| 721 | * the Linux i82365 driver does not (and should not) handle CardBus. |
| 722 | */ |
| 723 | static void __devinit quirk_cardbus_legacy(struct pci_dev *dev) |
| 724 | { |
| 725 | if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class) |
| 726 | return; |
| 727 | pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); |
| 728 | } |
| 729 | DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy); |
| 730 | |
| 731 | /* |
| 732 | * Following the PCI ordering rules is optional on the AMD762. I'm not |
| 733 | * sure what the designers were smoking but let's not inhale... |
| 734 | * |
| 735 | * To be fair to AMD, it follows the spec by default, its BIOS people |
| 736 | * who turn it off! |
| 737 | */ |
| 738 | static void __devinit quirk_amd_ordering(struct pci_dev *dev) |
| 739 | { |
| 740 | u32 pcic; |
| 741 | pci_read_config_dword(dev, 0x4C, &pcic); |
| 742 | if ((pcic&6)!=6) { |
| 743 | pcic |= 6; |
| 744 | printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n"); |
| 745 | pci_write_config_dword(dev, 0x4C, pcic); |
| 746 | pci_read_config_dword(dev, 0x84, &pcic); |
| 747 | pcic |= (1<<23); /* Required in this mode */ |
| 748 | pci_write_config_dword(dev, 0x84, pcic); |
| 749 | } |
| 750 | } |
| 751 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering ); |
| 752 | |
| 753 | /* |
| 754 | * DreamWorks provided workaround for Dunord I-3000 problem |
| 755 | * |
| 756 | * This card decodes and responds to addresses not apparently |
| 757 | * assigned to it. We force a larger allocation to ensure that |
| 758 | * nothing gets put too close to it. |
| 759 | */ |
| 760 | static void __devinit quirk_dunord ( struct pci_dev * dev ) |
| 761 | { |
| 762 | struct resource *r = &dev->resource [1]; |
| 763 | r->start = 0; |
| 764 | r->end = 0xffffff; |
| 765 | } |
| 766 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord ); |
| 767 | |
| 768 | /* |
| 769 | * i82380FB mobile docking controller: its PCI-to-PCI bridge |
| 770 | * is subtractive decoding (transparent), and does indicate this |
| 771 | * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80 |
| 772 | * instead of 0x01. |
| 773 | */ |
| 774 | static void __devinit quirk_transparent_bridge(struct pci_dev *dev) |
| 775 | { |
| 776 | dev->transparent = 1; |
| 777 | } |
| 778 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge ); |
| 779 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge ); |
| 780 | |
| 781 | /* |
| 782 | * Common misconfiguration of the MediaGX/Geode PCI master that will |
| 783 | * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 |
| 784 | * datasheets found at http://www.national.com/ds/GX for info on what |
| 785 | * these bits do. <christer@weinigel.se> |
| 786 | */ |
| 787 | static void __init quirk_mediagx_master(struct pci_dev *dev) |
| 788 | { |
| 789 | u8 reg; |
| 790 | pci_read_config_byte(dev, 0x41, ®); |
| 791 | if (reg & 2) { |
| 792 | reg &= ~2; |
| 793 | printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg); |
| 794 | pci_write_config_byte(dev, 0x41, reg); |
| 795 | } |
| 796 | } |
| 797 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master ); |
| 798 | |
| 799 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 800 | * Ensure C0 rev restreaming is off. This is normally done by |
| 801 | * the BIOS but in the odd case it is not the results are corruption |
| 802 | * hence the presence of a Linux check |
| 803 | */ |
| 804 | static void __init quirk_disable_pxb(struct pci_dev *pdev) |
| 805 | { |
| 806 | u16 config; |
| 807 | u8 rev; |
| 808 | |
| 809 | pci_read_config_byte(pdev, PCI_REVISION_ID, &rev); |
| 810 | if (rev != 0x04) /* Only C0 requires this */ |
| 811 | return; |
| 812 | pci_read_config_word(pdev, 0x40, &config); |
| 813 | if (config & (1<<6)) { |
| 814 | config &= ~(1<<6); |
| 815 | pci_write_config_word(pdev, 0x40, config); |
| 816 | printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n"); |
| 817 | } |
| 818 | } |
| 819 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb ); |
| 820 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 821 | |
| 822 | /* |
| 823 | * Serverworks CSB5 IDE does not fully support native mode |
| 824 | */ |
| 825 | static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev) |
| 826 | { |
| 827 | u8 prog; |
| 828 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); |
| 829 | if (prog & 5) { |
| 830 | prog &= ~5; |
| 831 | pdev->class &= ~5; |
| 832 | pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); |
Alan Cox | 368c73d | 2006-10-04 00:41:26 +0100 | [diff] [blame] | 833 | /* PCI layer will sort out resources */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 834 | } |
| 835 | } |
Alan Cox | 368c73d | 2006-10-04 00:41:26 +0100 | [diff] [blame] | 836 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 837 | |
| 838 | /* |
| 839 | * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same |
| 840 | */ |
| 841 | static void __init quirk_ide_samemode(struct pci_dev *pdev) |
| 842 | { |
| 843 | u8 prog; |
| 844 | |
| 845 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); |
| 846 | |
| 847 | if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { |
| 848 | printk(KERN_INFO "PCI: IDE mode mismatch; forcing legacy mode\n"); |
| 849 | prog &= ~5; |
| 850 | pdev->class &= ~5; |
| 851 | pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 852 | } |
| 853 | } |
Alan Cox | 368c73d | 2006-10-04 00:41:26 +0100 | [diff] [blame] | 854 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 855 | |
| 856 | /* This was originally an Alpha specific thing, but it really fits here. |
| 857 | * The i82375 PCI/EISA bridge appears as non-classified. Fix that. |
| 858 | */ |
| 859 | static void __init quirk_eisa_bridge(struct pci_dev *dev) |
| 860 | { |
| 861 | dev->class = PCI_CLASS_BRIDGE_EISA << 8; |
| 862 | } |
| 863 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge ); |
| 864 | |
| 865 | /* |
Johannes Goecke | 7daa0c4 | 2006-04-20 02:43:17 -0700 | [diff] [blame] | 866 | * On the MSI-K8T-Neo2Fir Board, the internal Soundcard is disabled |
| 867 | * when a PCI-Soundcard is added. The BIOS only gives Options |
| 868 | * "Disabled" and "AUTO". This Quirk Sets the corresponding |
| 869 | * Register-Value to enable the Soundcard. |
Chris Wedgwood | bd91fde | 2006-06-05 00:13:21 -0700 | [diff] [blame] | 870 | * |
| 871 | * FIXME: Presently this quirk will run on anything that has an 8237 |
| 872 | * which isn't correct, we need to check DMI tables or something in |
| 873 | * order to make sure it only runs on the MSI-K8T-Neo2Fir. Because it |
| 874 | * runs everywhere at present we suppress the printk output in most |
| 875 | * irrelevant cases. |
Johannes Goecke | 7daa0c4 | 2006-04-20 02:43:17 -0700 | [diff] [blame] | 876 | */ |
| 877 | static void __init k8t_sound_hostbridge(struct pci_dev *dev) |
| 878 | { |
| 879 | unsigned char val; |
| 880 | |
Johannes Goecke | 7daa0c4 | 2006-04-20 02:43:17 -0700 | [diff] [blame] | 881 | pci_read_config_byte(dev, 0x50, &val); |
| 882 | if (val == 0x88 || val == 0xc8) { |
Chris Wedgwood | bd91fde | 2006-06-05 00:13:21 -0700 | [diff] [blame] | 883 | /* Assume it's probably a MSI-K8T-Neo2Fir */ |
| 884 | printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, attempting to turn soundcard ON\n"); |
Johannes Goecke | 7daa0c4 | 2006-04-20 02:43:17 -0700 | [diff] [blame] | 885 | pci_write_config_byte(dev, 0x50, val & (~0x40)); |
| 886 | |
| 887 | /* Verify the Change for Status output */ |
| 888 | pci_read_config_byte(dev, 0x50, &val); |
| 889 | if (val & 0x40) |
Chris Wedgwood | bd91fde | 2006-06-05 00:13:21 -0700 | [diff] [blame] | 890 | printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, soundcard still off\n"); |
Johannes Goecke | 7daa0c4 | 2006-04-20 02:43:17 -0700 | [diff] [blame] | 891 | else |
Chris Wedgwood | bd91fde | 2006-06-05 00:13:21 -0700 | [diff] [blame] | 892 | printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, soundcard on\n"); |
Johannes Goecke | 7daa0c4 | 2006-04-20 02:43:17 -0700 | [diff] [blame] | 893 | } |
Johannes Goecke | 7daa0c4 | 2006-04-20 02:43:17 -0700 | [diff] [blame] | 894 | } |
| 895 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, k8t_sound_hostbridge); |
| 896 | |
Carl-Daniel Hailfinger | ce007ea | 2006-05-15 09:44:33 -0700 | [diff] [blame] | 897 | #ifndef CONFIG_ACPI_SLEEP |
Johannes Goecke | 7daa0c4 | 2006-04-20 02:43:17 -0700 | [diff] [blame] | 898 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 899 | * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge |
| 900 | * is not activated. The myth is that Asus said that they do not want the |
| 901 | * users to be irritated by just another PCI Device in the Win98 device |
| 902 | * manager. (see the file prog/hotplug/README.p4b in the lm_sensors |
| 903 | * package 2.7.0 for details) |
| 904 | * |
| 905 | * The SMBus PCI Device can be activated by setting a bit in the ICH LPC |
| 906 | * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it |
| 907 | * becomes necessary to do this tweak in two steps -- I've chosen the Host |
| 908 | * bridge as trigger. |
Carl-Daniel Hailfinger | ce007ea | 2006-05-15 09:44:33 -0700 | [diff] [blame] | 909 | * |
| 910 | * Actually, leaving it unhidden and not redoing the quirk over suspend2ram |
| 911 | * will cause thermal management to break down, and causing machine to |
| 912 | * overheat. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 913 | */ |
Carl-Daniel Hailfinger | ce007ea | 2006-05-15 09:44:33 -0700 | [diff] [blame] | 914 | static int __initdata asus_hides_smbus; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 915 | |
| 916 | static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev) |
| 917 | { |
| 918 | if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { |
| 919 | if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) |
| 920 | switch(dev->subsystem_device) { |
Jean Delvare | a00db37 | 2005-06-29 17:04:06 +0200 | [diff] [blame] | 921 | case 0x8025: /* P4B-LX */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 922 | case 0x8070: /* P4B */ |
| 923 | case 0x8088: /* P4B533 */ |
| 924 | case 0x1626: /* L3C notebook */ |
| 925 | asus_hides_smbus = 1; |
| 926 | } |
| 927 | if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) |
| 928 | switch(dev->subsystem_device) { |
| 929 | case 0x80b1: /* P4GE-V */ |
| 930 | case 0x80b2: /* P4PE */ |
| 931 | case 0x8093: /* P4B533-V */ |
| 932 | asus_hides_smbus = 1; |
| 933 | } |
| 934 | if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) |
| 935 | switch(dev->subsystem_device) { |
| 936 | case 0x8030: /* P4T533 */ |
| 937 | asus_hides_smbus = 1; |
| 938 | } |
| 939 | if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) |
| 940 | switch (dev->subsystem_device) { |
| 941 | case 0x8070: /* P4G8X Deluxe */ |
| 942 | asus_hides_smbus = 1; |
| 943 | } |
Jean Delvare | 321311a | 2006-07-31 08:53:15 +0200 | [diff] [blame] | 944 | if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) |
| 945 | switch (dev->subsystem_device) { |
| 946 | case 0x80c9: /* PU-DLS */ |
| 947 | asus_hides_smbus = 1; |
| 948 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 949 | if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) |
| 950 | switch (dev->subsystem_device) { |
| 951 | case 0x1751: /* M2N notebook */ |
| 952 | case 0x1821: /* M5N notebook */ |
| 953 | asus_hides_smbus = 1; |
| 954 | } |
| 955 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) |
| 956 | switch (dev->subsystem_device) { |
| 957 | case 0x184b: /* W1N notebook */ |
| 958 | case 0x186a: /* M6Ne notebook */ |
| 959 | asus_hides_smbus = 1; |
| 960 | } |
R.Marek@sh.cvut.cz | acc0663 | 2005-09-29 08:35:41 +0000 | [diff] [blame] | 961 | if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) { |
| 962 | switch (dev->subsystem_device) { |
| 963 | case 0x1882: /* M6V notebook */ |
Jean Delvare | 2d1e1c7 | 2006-04-01 16:46:35 +0200 | [diff] [blame] | 964 | case 0x1977: /* A6VA notebook */ |
R.Marek@sh.cvut.cz | acc0663 | 2005-09-29 08:35:41 +0000 | [diff] [blame] | 965 | asus_hides_smbus = 1; |
| 966 | } |
| 967 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 968 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { |
| 969 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) |
| 970 | switch(dev->subsystem_device) { |
| 971 | case 0x088C: /* HP Compaq nc8000 */ |
| 972 | case 0x0890: /* HP Compaq nc6000 */ |
| 973 | asus_hides_smbus = 1; |
| 974 | } |
| 975 | if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) |
| 976 | switch (dev->subsystem_device) { |
| 977 | case 0x12bc: /* HP D330L */ |
Jean Delvare | e3b1bd5 | 2005-09-21 22:26:31 +0200 | [diff] [blame] | 978 | case 0x12bd: /* HP D530 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 979 | asus_hides_smbus = 1; |
| 980 | } |
tomek@koprowski.org | 3c0a654 | 2006-02-19 18:03:24 +0100 | [diff] [blame] | 981 | if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) { |
| 982 | switch (dev->subsystem_device) { |
| 983 | case 0x099c: /* HP Compaq nx6110 */ |
| 984 | asus_hides_smbus = 1; |
| 985 | } |
| 986 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 987 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_TOSHIBA)) { |
| 988 | if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) |
| 989 | switch(dev->subsystem_device) { |
| 990 | case 0x0001: /* Toshiba Satellite A40 */ |
| 991 | asus_hides_smbus = 1; |
| 992 | } |
Daniele Gaffuri | e96e2f1 | 2005-07-29 12:15:46 -0700 | [diff] [blame] | 993 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) |
| 994 | switch(dev->subsystem_device) { |
| 995 | case 0x0001: /* Toshiba Tecra M2 */ |
| 996 | asus_hides_smbus = 1; |
| 997 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 998 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { |
| 999 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) |
| 1000 | switch(dev->subsystem_device) { |
| 1001 | case 0xC00C: /* Samsung P35 notebook */ |
| 1002 | asus_hides_smbus = 1; |
| 1003 | } |
Rumen Ivanov Zarev | c87f883 | 2005-09-06 13:39:32 -0700 | [diff] [blame] | 1004 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { |
| 1005 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) |
| 1006 | switch(dev->subsystem_device) { |
| 1007 | case 0x0058: /* Compaq Evo N620c */ |
| 1008 | asus_hides_smbus = 1; |
| 1009 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1010 | } |
| 1011 | } |
| 1012 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge ); |
| 1013 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge ); |
| 1014 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge ); |
| 1015 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge ); |
| 1016 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge ); |
Jean Delvare | 321311a | 2006-07-31 08:53:15 +0200 | [diff] [blame] | 1017 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1018 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge ); |
| 1019 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge ); |
R.Marek@sh.cvut.cz | acc0663 | 2005-09-29 08:35:41 +0000 | [diff] [blame] | 1020 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1021 | |
| 1022 | static void __init asus_hides_smbus_lpc(struct pci_dev *dev) |
| 1023 | { |
| 1024 | u16 val; |
| 1025 | |
| 1026 | if (likely(!asus_hides_smbus)) |
| 1027 | return; |
| 1028 | |
| 1029 | pci_read_config_word(dev, 0xF2, &val); |
| 1030 | if (val & 0x8) { |
| 1031 | pci_write_config_word(dev, 0xF2, val & (~0x8)); |
| 1032 | pci_read_config_word(dev, 0xF2, &val); |
| 1033 | if (val & 0x8) |
| 1034 | printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val); |
| 1035 | else |
| 1036 | printk(KERN_INFO "PCI: Enabled i801 SMBus device\n"); |
| 1037 | } |
| 1038 | } |
| 1039 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc ); |
| 1040 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc ); |
Jean Delvare | 321311a | 2006-07-31 08:53:15 +0200 | [diff] [blame] | 1041 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1042 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc ); |
| 1043 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc ); |
| 1044 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc ); |
| 1045 | |
R.Marek@sh.cvut.cz | acc0663 | 2005-09-29 08:35:41 +0000 | [diff] [blame] | 1046 | static void __init asus_hides_smbus_lpc_ich6(struct pci_dev *dev) |
| 1047 | { |
| 1048 | u32 val, rcba; |
| 1049 | void __iomem *base; |
| 1050 | |
| 1051 | if (likely(!asus_hides_smbus)) |
| 1052 | return; |
| 1053 | pci_read_config_dword(dev, 0xF0, &rcba); |
| 1054 | base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); /* use bits 31:14, 16 kB aligned */ |
| 1055 | if (base == NULL) return; |
| 1056 | val=readl(base + 0x3418); /* read the Function Disable register, dword mode only */ |
| 1057 | writel(val & 0xFFFFFFF7, base + 0x3418); /* enable the SMBus device */ |
| 1058 | iounmap(base); |
| 1059 | printk(KERN_INFO "PCI: Enabled ICH6/i801 SMBus device\n"); |
| 1060 | } |
| 1061 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6 ); |
| 1062 | |
Carl-Daniel Hailfinger | ce007ea | 2006-05-15 09:44:33 -0700 | [diff] [blame] | 1063 | #endif |
| 1064 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1065 | /* |
| 1066 | * SiS 96x south bridge: BIOS typically hides SMBus device... |
| 1067 | */ |
| 1068 | static void __init quirk_sis_96x_smbus(struct pci_dev *dev) |
| 1069 | { |
| 1070 | u8 val = 0; |
| 1071 | printk(KERN_INFO "Enabling SiS 96x SMBus.\n"); |
| 1072 | pci_read_config_byte(dev, 0x77, &val); |
| 1073 | pci_write_config_byte(dev, 0x77, val & ~0x10); |
| 1074 | pci_read_config_byte(dev, 0x77, &val); |
| 1075 | } |
| 1076 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1077 | /* |
| 1078 | * ... This is further complicated by the fact that some SiS96x south |
| 1079 | * bridges pretend to be 85C503/5513 instead. In that case see if we |
| 1080 | * spotted a compatible north bridge to make sure. |
| 1081 | * (pci_find_device doesn't work yet) |
| 1082 | * |
| 1083 | * We can also enable the sis96x bit in the discovery register.. |
| 1084 | */ |
| 1085 | static int __devinitdata sis_96x_compatible = 0; |
| 1086 | |
| 1087 | #define SIS_DETECT_REGISTER 0x40 |
| 1088 | |
| 1089 | static void __init quirk_sis_503(struct pci_dev *dev) |
| 1090 | { |
| 1091 | u8 reg; |
| 1092 | u16 devid; |
| 1093 | |
| 1094 | pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); |
| 1095 | pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); |
| 1096 | pci_read_config_word(dev, PCI_DEVICE_ID, &devid); |
| 1097 | if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { |
| 1098 | pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); |
| 1099 | return; |
| 1100 | } |
| 1101 | |
| 1102 | /* Make people aware that we changed the config.. */ |
| 1103 | printk(KERN_WARNING "Uncovering SIS%x that hid as a SIS503 (compatible=%d)\n", devid, sis_96x_compatible); |
| 1104 | |
| 1105 | /* |
| 1106 | * Ok, it now shows up as a 96x.. The 96x quirks are after |
| 1107 | * the 503 quirk in the quirk table, so they'll automatically |
| 1108 | * run and enable things like the SMBus device |
| 1109 | */ |
| 1110 | dev->device = devid; |
| 1111 | } |
| 1112 | |
| 1113 | static void __init quirk_sis_96x_compatible(struct pci_dev *dev) |
| 1114 | { |
| 1115 | sis_96x_compatible = 1; |
| 1116 | } |
| 1117 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_645, quirk_sis_96x_compatible ); |
| 1118 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_646, quirk_sis_96x_compatible ); |
| 1119 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_648, quirk_sis_96x_compatible ); |
| 1120 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_650, quirk_sis_96x_compatible ); |
| 1121 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_651, quirk_sis_96x_compatible ); |
| 1122 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_735, quirk_sis_96x_compatible ); |
| 1123 | |
| 1124 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 ); |
Bauke Jan Douma | e5548e9 | 2006-02-28 21:44:36 +0100 | [diff] [blame] | 1125 | /* |
| 1126 | * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller |
| 1127 | * and MC97 modem controller are disabled when a second PCI soundcard is |
| 1128 | * present. This patch, tweaking the VT8237 ISA bridge, enables them. |
| 1129 | * -- bjd |
| 1130 | */ |
| 1131 | static void __init asus_hides_ac97_lpc(struct pci_dev *dev) |
| 1132 | { |
| 1133 | u8 val; |
| 1134 | int asus_hides_ac97 = 0; |
| 1135 | |
| 1136 | if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { |
| 1137 | if (dev->device == PCI_DEVICE_ID_VIA_8237) |
| 1138 | asus_hides_ac97 = 1; |
| 1139 | } |
| 1140 | |
| 1141 | if (!asus_hides_ac97) |
| 1142 | return; |
| 1143 | |
| 1144 | pci_read_config_byte(dev, 0x50, &val); |
| 1145 | if (val & 0xc0) { |
| 1146 | pci_write_config_byte(dev, 0x50, val & (~0xc0)); |
| 1147 | pci_read_config_byte(dev, 0x50, &val); |
| 1148 | if (val & 0xc0) |
| 1149 | printk(KERN_INFO "PCI: onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val); |
| 1150 | else |
| 1151 | printk(KERN_INFO "PCI: enabled onboard AC97/MC97 devices\n"); |
| 1152 | } |
| 1153 | } |
| 1154 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc ); |
| 1155 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1156 | |
| 1157 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus ); |
| 1158 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus ); |
| 1159 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus ); |
| 1160 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus ); |
| 1161 | |
Tejun Heo | 7796705 | 2006-08-19 03:54:39 +0900 | [diff] [blame] | 1162 | #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) |
Alan Cox | 15e0c69 | 2006-07-12 15:05:41 +0100 | [diff] [blame] | 1163 | |
| 1164 | /* |
| 1165 | * If we are using libata we can drive this chip properly but must |
| 1166 | * do this early on to make the additional device appear during |
| 1167 | * the PCI scanning. |
| 1168 | */ |
| 1169 | |
| 1170 | static void __devinit quirk_jmicron_dualfn(struct pci_dev *pdev) |
| 1171 | { |
| 1172 | u32 conf; |
| 1173 | u8 hdr; |
| 1174 | |
| 1175 | /* Only poke fn 0 */ |
| 1176 | if (PCI_FUNC(pdev->devfn)) |
| 1177 | return; |
| 1178 | |
| 1179 | switch(pdev->device) { |
| 1180 | case PCI_DEVICE_ID_JMICRON_JMB365: |
| 1181 | case PCI_DEVICE_ID_JMICRON_JMB366: |
| 1182 | /* Redirect IDE second PATA port to the right spot */ |
| 1183 | pci_read_config_dword(pdev, 0x80, &conf); |
| 1184 | conf |= (1 << 24); |
| 1185 | /* Fall through */ |
| 1186 | pci_write_config_dword(pdev, 0x80, conf); |
| 1187 | case PCI_DEVICE_ID_JMICRON_JMB361: |
| 1188 | case PCI_DEVICE_ID_JMICRON_JMB363: |
| 1189 | pci_read_config_dword(pdev, 0x40, &conf); |
| 1190 | /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ |
| 1191 | /* Set the class codes correctly and then direct IDE 0 */ |
| 1192 | conf &= ~0x000F0200; /* Clear bit 9 and 16-19 */ |
| 1193 | conf |= 0x00C20002; /* Set bit 1, 17, 22, 23 */ |
| 1194 | pci_write_config_dword(pdev, 0x40, conf); |
| 1195 | |
| 1196 | /* Reconfigure so that the PCI scanner discovers the |
| 1197 | device is now multifunction */ |
| 1198 | |
| 1199 | pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); |
| 1200 | pdev->hdr_type = hdr & 0x7f; |
| 1201 | pdev->multifunction = !!(hdr & 0x80); |
| 1202 | |
| 1203 | break; |
| 1204 | } |
| 1205 | } |
| 1206 | |
| 1207 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, quirk_jmicron_dualfn); |
| 1208 | |
| 1209 | #endif |
| 1210 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1211 | #ifdef CONFIG_X86_IO_APIC |
| 1212 | static void __init quirk_alder_ioapic(struct pci_dev *pdev) |
| 1213 | { |
| 1214 | int i; |
| 1215 | |
| 1216 | if ((pdev->class >> 8) != 0xff00) |
| 1217 | return; |
| 1218 | |
| 1219 | /* the first BAR is the location of the IO APIC...we must |
| 1220 | * not touch this (and it's already covered by the fixmap), so |
| 1221 | * forcibly insert it into the resource tree */ |
| 1222 | if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) |
| 1223 | insert_resource(&iomem_resource, &pdev->resource[0]); |
| 1224 | |
| 1225 | /* The next five BARs all seem to be rubbish, so just clean |
| 1226 | * them out */ |
| 1227 | for (i=1; i < 6; i++) { |
| 1228 | memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); |
| 1229 | } |
| 1230 | |
| 1231 | } |
| 1232 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic ); |
| 1233 | #endif |
| 1234 | |
Jesse Barnes | 2bd0fa3 | 2005-12-13 03:05:03 -0500 | [diff] [blame] | 1235 | enum ide_combined_type { COMBINED = 0, IDE = 1, LIBATA = 2 }; |
| 1236 | /* Defaults to combined */ |
| 1237 | static enum ide_combined_type combined_mode; |
| 1238 | |
| 1239 | static int __init combined_setup(char *str) |
| 1240 | { |
| 1241 | if (!strncmp(str, "ide", 3)) |
| 1242 | combined_mode = IDE; |
| 1243 | else if (!strncmp(str, "libata", 6)) |
| 1244 | combined_mode = LIBATA; |
| 1245 | else /* "combined" or anything else defaults to old behavior */ |
| 1246 | combined_mode = COMBINED; |
| 1247 | |
| 1248 | return 1; |
| 1249 | } |
| 1250 | __setup("combined_mode=", combined_setup); |
| 1251 | |
Tejun Heo | 7796705 | 2006-08-19 03:54:39 +0900 | [diff] [blame] | 1252 | #ifdef CONFIG_SATA_INTEL_COMBINED |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1253 | static void __devinit quirk_intel_ide_combined(struct pci_dev *pdev) |
| 1254 | { |
| 1255 | u8 prog, comb, tmp; |
| 1256 | int ich = 0; |
| 1257 | |
| 1258 | /* |
| 1259 | * Narrow down to Intel SATA PCI devices. |
| 1260 | */ |
| 1261 | switch (pdev->device) { |
| 1262 | /* PCI ids taken from drivers/scsi/ata_piix.c */ |
| 1263 | case 0x24d1: |
| 1264 | case 0x24df: |
| 1265 | case 0x25a3: |
| 1266 | case 0x25b0: |
| 1267 | ich = 5; |
| 1268 | break; |
| 1269 | case 0x2651: |
| 1270 | case 0x2652: |
| 1271 | case 0x2653: |
Jason Gaston | c368ca4 | 2005-04-16 15:24:44 -0700 | [diff] [blame] | 1272 | case 0x2680: /* ESB2 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1273 | ich = 6; |
| 1274 | break; |
| 1275 | case 0x27c0: |
| 1276 | case 0x27c4: |
| 1277 | ich = 7; |
| 1278 | break; |
Jason Gaston | 012b265 | 2006-01-17 12:28:48 -0800 | [diff] [blame] | 1279 | case 0x2828: /* ICH8M */ |
| 1280 | ich = 8; |
| 1281 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1282 | default: |
| 1283 | /* we do not handle this PCI device */ |
| 1284 | return; |
| 1285 | } |
| 1286 | |
| 1287 | /* |
| 1288 | * Read combined mode register. |
| 1289 | */ |
| 1290 | pci_read_config_byte(pdev, 0x90, &tmp); /* combined mode reg */ |
| 1291 | |
| 1292 | if (ich == 5) { |
| 1293 | tmp &= 0x6; /* interesting bits 2:1, PATA primary/secondary */ |
| 1294 | if (tmp == 0x4) /* bits 10x */ |
| 1295 | comb = (1 << 0); /* SATA port 0, PATA port 1 */ |
| 1296 | else if (tmp == 0x6) /* bits 11x */ |
| 1297 | comb = (1 << 2); /* PATA port 0, SATA port 1 */ |
| 1298 | else |
| 1299 | return; /* not in combined mode */ |
| 1300 | } else { |
Jason Gaston | 012b265 | 2006-01-17 12:28:48 -0800 | [diff] [blame] | 1301 | WARN_ON((ich != 6) && (ich != 7) && (ich != 8)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1302 | tmp &= 0x3; /* interesting bits 1:0 */ |
| 1303 | if (tmp & (1 << 0)) |
| 1304 | comb = (1 << 2); /* PATA port 0, SATA port 1 */ |
| 1305 | else if (tmp & (1 << 1)) |
| 1306 | comb = (1 << 0); /* SATA port 0, PATA port 1 */ |
| 1307 | else |
| 1308 | return; /* not in combined mode */ |
| 1309 | } |
| 1310 | |
| 1311 | /* |
| 1312 | * Read programming interface register. |
| 1313 | * (Tells us if it's legacy or native mode) |
| 1314 | */ |
| 1315 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); |
| 1316 | |
| 1317 | /* if SATA port is in native mode, we're ok. */ |
| 1318 | if (prog & comb) |
| 1319 | return; |
| 1320 | |
Jesse Barnes | 2bd0fa3 | 2005-12-13 03:05:03 -0500 | [diff] [blame] | 1321 | /* Don't reserve any so the IDE driver can get them (but only if |
| 1322 | * combined_mode=ide). |
| 1323 | */ |
| 1324 | if (combined_mode == IDE) |
| 1325 | return; |
| 1326 | |
| 1327 | /* Grab them both for libata if combined_mode=libata. */ |
| 1328 | if (combined_mode == LIBATA) { |
| 1329 | request_region(0x1f0, 8, "libata"); /* port 0 */ |
| 1330 | request_region(0x170, 8, "libata"); /* port 1 */ |
| 1331 | return; |
| 1332 | } |
| 1333 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1334 | /* SATA port is in legacy mode. Reserve port so that |
| 1335 | * IDE driver does not attempt to use it. If request_region |
| 1336 | * fails, it will be obvious at boot time, so we don't bother |
| 1337 | * checking return values. |
| 1338 | */ |
| 1339 | if (comb == (1 << 0)) |
| 1340 | request_region(0x1f0, 8, "libata"); /* port 0 */ |
| 1341 | else |
| 1342 | request_region(0x170, 8, "libata"); /* port 1 */ |
| 1343 | } |
| 1344 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_intel_ide_combined ); |
Tejun Heo | 7796705 | 2006-08-19 03:54:39 +0900 | [diff] [blame] | 1345 | #endif /* CONFIG_SATA_INTEL_COMBINED */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1346 | |
| 1347 | |
| 1348 | int pcie_mch_quirk; |
| 1349 | |
| 1350 | static void __devinit quirk_pcie_mch(struct pci_dev *pdev) |
| 1351 | { |
| 1352 | pcie_mch_quirk = 1; |
| 1353 | } |
| 1354 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch ); |
| 1355 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch ); |
| 1356 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch ); |
| 1357 | |
Kristen Accardi | 4602b88 | 2005-08-16 15:15:58 -0700 | [diff] [blame] | 1358 | |
| 1359 | /* |
| 1360 | * It's possible for the MSI to get corrupted if shpc and acpi |
| 1361 | * are used together on certain PXH-based systems. |
| 1362 | */ |
| 1363 | static void __devinit quirk_pcie_pxh(struct pci_dev *dev) |
| 1364 | { |
| 1365 | disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI), |
| 1366 | PCI_CAP_ID_MSI); |
| 1367 | dev->no_msi = 1; |
| 1368 | |
| 1369 | printk(KERN_WARNING "PCI: PXH quirk detected, " |
| 1370 | "disabling MSI for SHPC device\n"); |
| 1371 | } |
| 1372 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); |
| 1373 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); |
| 1374 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); |
| 1375 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); |
| 1376 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); |
| 1377 | |
Kristen Carlson Accardi | ffadcc2 | 2006-07-12 08:59:00 -0700 | [diff] [blame] | 1378 | /* |
| 1379 | * Some Intel PCI Express chipsets have trouble with downstream |
| 1380 | * device power management. |
| 1381 | */ |
| 1382 | static void quirk_intel_pcie_pm(struct pci_dev * dev) |
| 1383 | { |
| 1384 | pci_pm_d3_delay = 120; |
| 1385 | dev->no_d1d2 = 1; |
| 1386 | } |
| 1387 | |
| 1388 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); |
| 1389 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); |
| 1390 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); |
| 1391 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); |
| 1392 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); |
| 1393 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); |
| 1394 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); |
| 1395 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); |
| 1396 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); |
| 1397 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); |
| 1398 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); |
| 1399 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); |
| 1400 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); |
| 1401 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); |
| 1402 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); |
| 1403 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); |
| 1404 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); |
| 1405 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); |
| 1406 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); |
| 1407 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); |
| 1408 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); |
Kristen Accardi | 4602b88 | 2005-08-16 15:15:58 -0700 | [diff] [blame] | 1409 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1410 | static void __devinit quirk_netmos(struct pci_dev *dev) |
| 1411 | { |
| 1412 | unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; |
| 1413 | unsigned int num_serial = dev->subsystem_device & 0xf; |
| 1414 | |
| 1415 | /* |
| 1416 | * These Netmos parts are multiport serial devices with optional |
| 1417 | * parallel ports. Even when parallel ports are present, they |
| 1418 | * are identified as class SERIAL, which means the serial driver |
| 1419 | * will claim them. To prevent this, mark them as class OTHER. |
| 1420 | * These combo devices should be claimed by parport_serial. |
| 1421 | * |
| 1422 | * The subdevice ID is of the form 0x00PS, where <P> is the number |
| 1423 | * of parallel ports and <S> is the number of serial ports. |
| 1424 | */ |
| 1425 | switch (dev->device) { |
| 1426 | case PCI_DEVICE_ID_NETMOS_9735: |
| 1427 | case PCI_DEVICE_ID_NETMOS_9745: |
| 1428 | case PCI_DEVICE_ID_NETMOS_9835: |
| 1429 | case PCI_DEVICE_ID_NETMOS_9845: |
| 1430 | case PCI_DEVICE_ID_NETMOS_9855: |
| 1431 | if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL && |
| 1432 | num_parallel) { |
| 1433 | printk(KERN_INFO "PCI: Netmos %04x (%u parallel, " |
| 1434 | "%u serial); changing class SERIAL to OTHER " |
| 1435 | "(use parport_serial)\n", |
| 1436 | dev->device, num_parallel, num_serial); |
| 1437 | dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | |
| 1438 | (dev->class & 0xff); |
| 1439 | } |
| 1440 | } |
| 1441 | } |
| 1442 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos); |
| 1443 | |
Bjorn Helgaas | 16a7474 | 2006-04-05 08:47:00 -0400 | [diff] [blame] | 1444 | static void __devinit quirk_e100_interrupt(struct pci_dev *dev) |
| 1445 | { |
| 1446 | u16 command; |
| 1447 | u32 bar; |
| 1448 | u8 __iomem *csr; |
| 1449 | u8 cmd_hi; |
| 1450 | |
| 1451 | switch (dev->device) { |
| 1452 | /* PCI IDs taken from drivers/net/e100.c */ |
| 1453 | case 0x1029: |
| 1454 | case 0x1030 ... 0x1034: |
| 1455 | case 0x1038 ... 0x103E: |
| 1456 | case 0x1050 ... 0x1057: |
| 1457 | case 0x1059: |
| 1458 | case 0x1064 ... 0x106B: |
| 1459 | case 0x1091 ... 0x1095: |
| 1460 | case 0x1209: |
| 1461 | case 0x1229: |
| 1462 | case 0x2449: |
| 1463 | case 0x2459: |
| 1464 | case 0x245D: |
| 1465 | case 0x27DC: |
| 1466 | break; |
| 1467 | default: |
| 1468 | return; |
| 1469 | } |
| 1470 | |
| 1471 | /* |
| 1472 | * Some firmware hands off the e100 with interrupts enabled, |
| 1473 | * which can cause a flood of interrupts if packets are |
| 1474 | * received before the driver attaches to the device. So |
| 1475 | * disable all e100 interrupts here. The driver will |
| 1476 | * re-enable them when it's ready. |
| 1477 | */ |
| 1478 | pci_read_config_word(dev, PCI_COMMAND, &command); |
| 1479 | pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar); |
| 1480 | |
| 1481 | if (!(command & PCI_COMMAND_MEMORY) || !bar) |
| 1482 | return; |
| 1483 | |
| 1484 | csr = ioremap(bar, 8); |
| 1485 | if (!csr) { |
| 1486 | printk(KERN_WARNING "PCI: Can't map %s e100 registers\n", |
| 1487 | pci_name(dev)); |
| 1488 | return; |
| 1489 | } |
| 1490 | |
| 1491 | cmd_hi = readb(csr + 3); |
| 1492 | if (cmd_hi == 0) { |
| 1493 | printk(KERN_WARNING "PCI: Firmware left %s e100 interrupts " |
| 1494 | "enabled, disabling\n", pci_name(dev)); |
| 1495 | writeb(1, csr + 3); |
| 1496 | } |
| 1497 | |
| 1498 | iounmap(csr); |
| 1499 | } |
| 1500 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt); |
Ivan Kokshaysky | a5312e2 | 2005-11-01 01:43:56 +0300 | [diff] [blame] | 1501 | |
| 1502 | static void __devinit fixup_rev1_53c810(struct pci_dev* dev) |
| 1503 | { |
| 1504 | /* rev 1 ncr53c810 chips don't set the class at all which means |
| 1505 | * they don't get their resources remapped. Fix that here. |
| 1506 | */ |
| 1507 | |
| 1508 | if (dev->class == PCI_CLASS_NOT_DEFINED) { |
| 1509 | printk(KERN_INFO "NCR 53c810 rev 1 detected, setting PCI class.\n"); |
| 1510 | dev->class = PCI_CLASS_STORAGE_SCSI; |
| 1511 | } |
| 1512 | } |
| 1513 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); |
| 1514 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1515 | static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end) |
| 1516 | { |
| 1517 | while (f < end) { |
| 1518 | if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) && |
| 1519 | (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) { |
| 1520 | pr_debug("PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev)); |
| 1521 | f->hook(dev); |
| 1522 | } |
| 1523 | f++; |
| 1524 | } |
| 1525 | } |
| 1526 | |
| 1527 | extern struct pci_fixup __start_pci_fixups_early[]; |
| 1528 | extern struct pci_fixup __end_pci_fixups_early[]; |
| 1529 | extern struct pci_fixup __start_pci_fixups_header[]; |
| 1530 | extern struct pci_fixup __end_pci_fixups_header[]; |
| 1531 | extern struct pci_fixup __start_pci_fixups_final[]; |
| 1532 | extern struct pci_fixup __end_pci_fixups_final[]; |
| 1533 | extern struct pci_fixup __start_pci_fixups_enable[]; |
| 1534 | extern struct pci_fixup __end_pci_fixups_enable[]; |
| 1535 | |
| 1536 | |
| 1537 | void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) |
| 1538 | { |
| 1539 | struct pci_fixup *start, *end; |
| 1540 | |
| 1541 | switch(pass) { |
| 1542 | case pci_fixup_early: |
| 1543 | start = __start_pci_fixups_early; |
| 1544 | end = __end_pci_fixups_early; |
| 1545 | break; |
| 1546 | |
| 1547 | case pci_fixup_header: |
| 1548 | start = __start_pci_fixups_header; |
| 1549 | end = __end_pci_fixups_header; |
| 1550 | break; |
| 1551 | |
| 1552 | case pci_fixup_final: |
| 1553 | start = __start_pci_fixups_final; |
| 1554 | end = __end_pci_fixups_final; |
| 1555 | break; |
| 1556 | |
| 1557 | case pci_fixup_enable: |
| 1558 | start = __start_pci_fixups_enable; |
| 1559 | end = __end_pci_fixups_enable; |
| 1560 | break; |
| 1561 | |
| 1562 | default: |
| 1563 | /* stupid compiler warning, you would think with an enum... */ |
| 1564 | return; |
| 1565 | } |
| 1566 | pci_do_fixups(dev, start, end); |
| 1567 | } |
| 1568 | |
Daniel Yeisley | 9d26512 | 2005-12-05 07:06:43 -0500 | [diff] [blame] | 1569 | /* Enable 1k I/O space granularity on the Intel P64H2 */ |
| 1570 | static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev) |
| 1571 | { |
| 1572 | u16 en1k; |
| 1573 | u8 io_base_lo, io_limit_lo; |
| 1574 | unsigned long base, limit; |
| 1575 | struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES; |
| 1576 | |
| 1577 | pci_read_config_word(dev, 0x40, &en1k); |
| 1578 | |
| 1579 | if (en1k & 0x200) { |
| 1580 | printk(KERN_INFO "PCI: Enable I/O Space to 1 KB Granularity\n"); |
| 1581 | |
| 1582 | pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); |
| 1583 | pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); |
| 1584 | base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; |
| 1585 | limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; |
| 1586 | |
| 1587 | if (base <= limit) { |
| 1588 | res->start = base; |
| 1589 | res->end = limit + 0x3ff; |
| 1590 | } |
| 1591 | } |
| 1592 | } |
| 1593 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); |
| 1594 | |
Brice Goglin | cf34a8e | 2006-06-13 14:35:42 -0400 | [diff] [blame] | 1595 | /* Under some circumstances, AER is not linked with extended capabilities. |
| 1596 | * Force it to be linked by setting the corresponding control bit in the |
| 1597 | * config space. |
| 1598 | */ |
| 1599 | static void __devinit quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) |
| 1600 | { |
| 1601 | uint8_t b; |
| 1602 | if (pci_read_config_byte(dev, 0xf41, &b) == 0) { |
| 1603 | if (!(b & 0x20)) { |
| 1604 | pci_write_config_byte(dev, 0xf41, b | 0x20); |
| 1605 | printk(KERN_INFO |
| 1606 | "PCI: Linking AER extended capability on %s\n", |
| 1607 | pci_name(dev)); |
| 1608 | } |
| 1609 | } |
| 1610 | } |
| 1611 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, |
| 1612 | quirk_nvidia_ck804_pcie_aer_ext_cap); |
| 1613 | |
Brice Goglin | 3f79e10 | 2006-08-31 01:54:56 -0400 | [diff] [blame] | 1614 | #ifdef CONFIG_PCI_MSI |
| 1615 | /* To disable MSI globally */ |
| 1616 | int pci_msi_quirk; |
| 1617 | |
| 1618 | /* The Serverworks PCI-X chipset does not support MSI. We cannot easily rely |
| 1619 | * on setting PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually |
| 1620 | * some other busses controlled by the chipset even if Linux is not aware of it. |
| 1621 | * Instead of setting the flag on all busses in the machine, simply disable MSI |
| 1622 | * globally. |
| 1623 | */ |
| 1624 | static void __init quirk_svw_msi(struct pci_dev *dev) |
| 1625 | { |
| 1626 | pci_msi_quirk = 1; |
| 1627 | printk(KERN_WARNING "PCI: MSI quirk detected. pci_msi_quirk set.\n"); |
| 1628 | } |
| 1629 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_svw_msi); |
| 1630 | |
| 1631 | /* Disable MSI on chipsets that are known to not support it */ |
| 1632 | static void __devinit quirk_disable_msi(struct pci_dev *dev) |
| 1633 | { |
| 1634 | if (dev->subordinate) { |
| 1635 | printk(KERN_WARNING "PCI: MSI quirk detected. " |
| 1636 | "PCI_BUS_FLAGS_NO_MSI set for %s subordinate bus.\n", |
| 1637 | pci_name(dev)); |
| 1638 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; |
| 1639 | } |
| 1640 | } |
| 1641 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); |
Brice Goglin | 6397c75 | 2006-08-31 01:55:32 -0400 | [diff] [blame] | 1642 | |
| 1643 | /* Go through the list of Hypertransport capabilities and |
| 1644 | * return 1 if a HT MSI capability is found and enabled */ |
| 1645 | static int __devinit msi_ht_cap_enabled(struct pci_dev *dev) |
| 1646 | { |
| 1647 | u8 pos; |
| 1648 | int ttl; |
| 1649 | for (pos = pci_find_capability(dev, PCI_CAP_ID_HT), ttl = 48; |
| 1650 | pos && ttl; |
| 1651 | pos = pci_find_next_capability(dev, pos, PCI_CAP_ID_HT), ttl--) { |
| 1652 | u32 cap_hdr; |
| 1653 | /* MSI mapping section according to Hypertransport spec */ |
| 1654 | if (pci_read_config_dword(dev, pos, &cap_hdr) == 0 |
| 1655 | && (cap_hdr & 0xf8000000) == 0xa8000000 /* MSI mapping */) { |
| 1656 | printk(KERN_INFO "PCI: Found HT MSI mapping on %s with capability %s\n", |
| 1657 | pci_name(dev), cap_hdr & 0x10000 ? "enabled" : "disabled"); |
| 1658 | return (cap_hdr & 0x10000) != 0; /* MSI mapping cap enabled */ |
| 1659 | } |
| 1660 | } |
| 1661 | return 0; |
| 1662 | } |
| 1663 | |
| 1664 | /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */ |
| 1665 | static void __devinit quirk_msi_ht_cap(struct pci_dev *dev) |
| 1666 | { |
| 1667 | if (dev->subordinate && !msi_ht_cap_enabled(dev)) { |
| 1668 | printk(KERN_WARNING "PCI: MSI quirk detected. " |
| 1669 | "MSI disabled on chipset %s.\n", |
| 1670 | pci_name(dev)); |
| 1671 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; |
| 1672 | } |
| 1673 | } |
| 1674 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, |
| 1675 | quirk_msi_ht_cap); |
| 1676 | |
| 1677 | /* The nVidia CK804 chipset may have 2 HT MSI mappings. |
| 1678 | * MSI are supported if the MSI capability set in any of these mappings. |
| 1679 | */ |
| 1680 | static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) |
| 1681 | { |
| 1682 | struct pci_dev *pdev; |
| 1683 | |
| 1684 | if (!dev->subordinate) |
| 1685 | return; |
| 1686 | |
| 1687 | /* check HT MSI cap on this chipset and the root one. |
| 1688 | * a single one having MSI is enough to be sure that MSI are supported. |
| 1689 | */ |
Alan Cox | 11f242f | 2006-10-10 14:39:00 -0700 | [diff] [blame] | 1690 | pdev = pci_get_slot(dev->bus, 0); |
David Rientjes | 0c875c2 | 2006-12-03 11:55:34 -0800 | [diff] [blame^] | 1691 | if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) { |
Brice Goglin | 6397c75 | 2006-08-31 01:55:32 -0400 | [diff] [blame] | 1692 | printk(KERN_WARNING "PCI: MSI quirk detected. " |
| 1693 | "MSI disabled on chipset %s.\n", |
| 1694 | pci_name(dev)); |
| 1695 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; |
| 1696 | } |
Alan Cox | 11f242f | 2006-10-10 14:39:00 -0700 | [diff] [blame] | 1697 | pci_dev_put(pdev); |
Brice Goglin | 6397c75 | 2006-08-31 01:55:32 -0400 | [diff] [blame] | 1698 | } |
| 1699 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, |
| 1700 | quirk_nvidia_ck804_msi_ht_cap); |
Brice Goglin | 3f79e10 | 2006-08-31 01:54:56 -0400 | [diff] [blame] | 1701 | #endif /* CONFIG_PCI_MSI */ |
| 1702 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1703 | EXPORT_SYMBOL(pcie_mch_quirk); |
| 1704 | #ifdef CONFIG_HOTPLUG |
| 1705 | EXPORT_SYMBOL(pci_fixup_device); |
| 1706 | #endif |