blob: 125e7b7f34ffd13462e551b31c79cd03ab0d3572 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * drivers/pci/setup-bus.c
3 *
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
8 *
9 * Support routines for initializing a PCI subsystem.
10 */
11
12/*
13 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
14 * PCI-PCI bridges cleanup, sorted resource allocation.
15 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16 * Converted to allocation in 3 passes, which gives
17 * tighter packing. Prefetchable range support.
18 */
19
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/pci.h>
24#include <linux/errno.h>
25#include <linux/ioport.h>
26#include <linux/cache.h>
27#include <linux/slab.h>
28
29
30#define DEBUG_CONFIG 1
31#if DEBUG_CONFIG
32#define DBG(x...) printk(x)
33#else
34#define DBG(x...)
35#endif
36
Sam Ravnborg96bde062007-03-26 21:53:30 -080037static void pbus_assign_resources_sorted(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -070038{
39 struct pci_dev *dev;
40 struct resource *res;
41 struct resource_list head, *list, *tmp;
42 int idx;
43
Linus Torvalds1da177e2005-04-16 15:20:36 -070044 head.next = NULL;
45 list_for_each_entry(dev, &bus->devices, bus_list) {
46 u16 class = dev->class >> 8;
47
Kenji Kaneshige9bded002006-10-04 02:15:34 -070048 /* Don't touch classless devices or host bridges or ioapics. */
Linus Torvalds1da177e2005-04-16 15:20:36 -070049 if (class == PCI_CLASS_NOT_DEFINED ||
Satoru Takeuchi23186272006-09-12 10:21:44 -070050 class == PCI_CLASS_BRIDGE_HOST)
Linus Torvalds1da177e2005-04-16 15:20:36 -070051 continue;
52
Kenji Kaneshige9bded002006-10-04 02:15:34 -070053 /* Don't touch ioapic devices already enabled by firmware */
Satoru Takeuchi23186272006-09-12 10:21:44 -070054 if (class == PCI_CLASS_SYSTEM_PIC) {
Kenji Kaneshige9bded002006-10-04 02:15:34 -070055 u16 command;
56 pci_read_config_word(dev, PCI_COMMAND, &command);
57 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
Satoru Takeuchi23186272006-09-12 10:21:44 -070058 continue;
59 }
60
Linus Torvalds1da177e2005-04-16 15:20:36 -070061 pdev_sort_resources(dev, &head);
62 }
63
64 for (list = head.next; list;) {
65 res = list->res;
66 idx = res - &list->dev->resource[0];
Rajesh Shah542df5d2005-04-28 00:25:50 -070067 if (pci_assign_resource(list->dev, idx)) {
68 res->start = 0;
Ivan Kokshaysky960b8462005-07-07 03:07:56 +040069 res->end = 0;
Rajesh Shah542df5d2005-04-28 00:25:50 -070070 res->flags = 0;
71 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070072 tmp = list;
73 list = list->next;
74 kfree(tmp);
75 }
76}
77
Dominik Brodowskib3743fa2005-09-09 13:03:23 -070078void pci_setup_cardbus(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -070079{
80 struct pci_dev *bridge = bus->self;
81 struct pci_bus_region region;
82
83 printk("PCI: Bus %d, cardbus bridge: %s\n",
84 bus->number, pci_name(bridge));
85
86 pcibios_resource_to_bus(bridge, &region, bus->resource[0]);
87 if (bus->resource[0]->flags & IORESOURCE_IO) {
88 /*
89 * The IO resource is allocated a range twice as large as it
90 * would normally need. This allows us to set both IO regs.
91 */
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +110092 printk(KERN_INFO " IO window: 0x%08lx-0x%08lx\n",
93 (unsigned long)region.start,
94 (unsigned long)region.end);
Linus Torvalds1da177e2005-04-16 15:20:36 -070095 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
96 region.start);
97 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
98 region.end);
99 }
100
101 pcibios_resource_to_bus(bridge, &region, bus->resource[1]);
102 if (bus->resource[1]->flags & IORESOURCE_IO) {
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100103 printk(KERN_INFO " IO window: 0x%08lx-0x%08lx\n",
104 (unsigned long)region.start,
105 (unsigned long)region.end);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700106 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
107 region.start);
108 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
109 region.end);
110 }
111
112 pcibios_resource_to_bus(bridge, &region, bus->resource[2]);
113 if (bus->resource[2]->flags & IORESOURCE_MEM) {
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100114 printk(KERN_INFO " PREFETCH window: 0x%08lx-0x%08lx\n",
115 (unsigned long)region.start,
116 (unsigned long)region.end);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700117 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
118 region.start);
119 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
120 region.end);
121 }
122
123 pcibios_resource_to_bus(bridge, &region, bus->resource[3]);
124 if (bus->resource[3]->flags & IORESOURCE_MEM) {
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100125 printk(KERN_INFO " MEM window: 0x%08lx-0x%08lx\n",
126 (unsigned long)region.start,
127 (unsigned long)region.end);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700128 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
129 region.start);
130 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
131 region.end);
132 }
133}
Dominik Brodowskib3743fa2005-09-09 13:03:23 -0700134EXPORT_SYMBOL(pci_setup_cardbus);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700135
136/* Initialize bridges with base/limit values we have collected.
137 PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
138 requires that if there is no I/O ports or memory behind the
139 bridge, corresponding range must be turned off by writing base
140 value greater than limit to the bridge's base/limit registers.
141
142 Note: care must be taken when updating I/O base/limit registers
143 of bridges which support 32-bit I/O. This update requires two
144 config space writes, so it's quite possible that an I/O window of
145 the bridge will have some undesirable address (e.g. 0) after the
146 first write. Ditto 64-bit prefetchable MMIO. */
147static void __devinit
148pci_setup_bridge(struct pci_bus *bus)
149{
150 struct pci_dev *bridge = bus->self;
151 struct pci_bus_region region;
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100152 u32 l, bu, lu, io_upper16;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700153
154 DBG(KERN_INFO "PCI: Bridge: %s\n", pci_name(bridge));
155
156 /* Set up the top and bottom of the PCI I/O segment for this bus. */
157 pcibios_resource_to_bus(bridge, &region, bus->resource[0]);
158 if (bus->resource[0]->flags & IORESOURCE_IO) {
159 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
160 l &= 0xffff0000;
161 l |= (region.start >> 8) & 0x00f0;
162 l |= region.end & 0xf000;
163 /* Set up upper 16 bits of I/O base/limit. */
164 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
165 DBG(KERN_INFO " IO window: %04lx-%04lx\n",
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100166 (unsigned long)region.start,
167 (unsigned long)region.end);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700168 }
169 else {
170 /* Clear upper 16 bits of I/O base/limit. */
171 io_upper16 = 0;
172 l = 0x00f0;
173 DBG(KERN_INFO " IO window: disabled.\n");
174 }
175 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
176 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
177 /* Update lower 16 bits of I/O base/limit. */
178 pci_write_config_dword(bridge, PCI_IO_BASE, l);
179 /* Update upper 16 bits of I/O base/limit. */
180 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
181
182 /* Set up the top and bottom of the PCI Memory segment
183 for this bus. */
184 pcibios_resource_to_bus(bridge, &region, bus->resource[1]);
185 if (bus->resource[1]->flags & IORESOURCE_MEM) {
186 l = (region.start >> 16) & 0xfff0;
187 l |= region.end & 0xfff00000;
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100188 DBG(KERN_INFO " MEM window: 0x%08lx-0x%08lx\n",
189 (unsigned long)region.start,
190 (unsigned long)region.end);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700191 }
192 else {
193 l = 0x0000fff0;
194 DBG(KERN_INFO " MEM window: disabled.\n");
195 }
196 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
197
198 /* Clear out the upper 32 bits of PREF limit.
199 If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
200 disables PREF range, which is ok. */
201 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
202
203 /* Set up PREF base/limit. */
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100204 bu = lu = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700205 pcibios_resource_to_bus(bridge, &region, bus->resource[2]);
206 if (bus->resource[2]->flags & IORESOURCE_PREFETCH) {
207 l = (region.start >> 16) & 0xfff0;
208 l |= region.end & 0xfff00000;
Andrew Morton13d36c22008-02-04 23:50:12 -0800209 bu = upper_32_bits(region.start);
210 lu = upper_32_bits(region.end);
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100211 DBG(KERN_INFO " PREFETCH window: 0x%016llx-0x%016llx\n",
212 (unsigned long long)region.start,
213 (unsigned long long)region.end);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700214 }
215 else {
216 l = 0x0000fff0;
217 DBG(KERN_INFO " PREFETCH window: disabled.\n");
218 }
219 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
220
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100221 /* Set the upper 32 bits of PREF base & limit. */
222 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
223 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700224
225 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
226}
227
228/* Check whether the bridge supports optional I/O and
229 prefetchable memory ranges. If not, the respective
230 base/limit registers must be read-only and read as 0. */
Sam Ravnborg96bde062007-03-26 21:53:30 -0800231static void pci_bridge_check_ranges(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700232{
233 u16 io;
234 u32 pmem;
235 struct pci_dev *bridge = bus->self;
236 struct resource *b_res;
237
238 b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
239 b_res[1].flags |= IORESOURCE_MEM;
240
241 pci_read_config_word(bridge, PCI_IO_BASE, &io);
242 if (!io) {
243 pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
244 pci_read_config_word(bridge, PCI_IO_BASE, &io);
245 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
246 }
247 if (io)
248 b_res[0].flags |= IORESOURCE_IO;
249 /* DECchip 21050 pass 2 errata: the bridge may miss an address
250 disconnect boundary by one PCI data phase.
251 Workaround: do not use prefetching on this device. */
252 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
253 return;
254 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
255 if (!pmem) {
256 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
257 0xfff0fff0);
258 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
259 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
260 }
261 if (pmem)
262 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
263}
264
265/* Helper function for sizing routines: find first available
266 bus resource of a given type. Note: we intentionally skip
267 the bus resources which have already been assigned (that is,
268 have non-NULL parent resource). */
Sam Ravnborg96bde062007-03-26 21:53:30 -0800269static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700270{
271 int i;
272 struct resource *r;
273 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
274 IORESOURCE_PREFETCH;
275
276 for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
277 r = bus->resource[i];
Ivan Kokshaysky299de032005-06-15 18:59:27 +0400278 if (r == &ioport_resource || r == &iomem_resource)
279 continue;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700280 if (r && (r->flags & type_mask) == type && !r->parent)
281 return r;
282 }
283 return NULL;
284}
285
286/* Sizing the IO windows of the PCI-PCI bridge is trivial,
287 since these windows have 4K granularity and the IO ranges
288 of non-bridge PCI devices are limited to 256 bytes.
289 We must be careful with the ISA aliasing though. */
Sam Ravnborg96bde062007-03-26 21:53:30 -0800290static void pbus_size_io(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700291{
292 struct pci_dev *dev;
293 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
294 unsigned long size = 0, size1 = 0;
295
296 if (!b_res)
297 return;
298
299 list_for_each_entry(dev, &bus->devices, bus_list) {
300 int i;
301
302 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
303 struct resource *r = &dev->resource[i];
304 unsigned long r_size;
305
306 if (r->parent || !(r->flags & IORESOURCE_IO))
307 continue;
308 r_size = r->end - r->start + 1;
309
310 if (r_size < 0x400)
311 /* Might be re-aligned for ISA */
312 size += r_size;
313 else
314 size1 += r_size;
315 }
316 }
317/* To be fixed in 2.5: we should have sort of HAVE_ISA
318 flag in the struct pci_bus. */
319#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
320 size = (size & 0xff) + ((size & ~0xffUL) << 2);
321#endif
Milind Arun Choudhary6f6f8c22007-07-09 11:55:51 -0700322 size = ALIGN(size + size1, 4096);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700323 if (!size) {
324 b_res->flags = 0;
325 return;
326 }
327 /* Alignment of the IO window is always 4K */
328 b_res->start = 4096;
329 b_res->end = b_res->start + size - 1;
330}
331
332/* Calculate the size of the bus and minimal alignment which
333 guarantees that all child resources fit in this size. */
Sam Ravnborg96bde062007-03-26 21:53:30 -0800334static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long type)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700335{
336 struct pci_dev *dev;
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100337 resource_size_t min_align, align, size;
338 resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700339 int order, max_order;
340 struct resource *b_res = find_free_bus_resource(bus, type);
341
342 if (!b_res)
343 return 0;
344
345 memset(aligns, 0, sizeof(aligns));
346 max_order = 0;
347 size = 0;
348
349 list_for_each_entry(dev, &bus->devices, bus_list) {
350 int i;
351
352 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
353 struct resource *r = &dev->resource[i];
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100354 resource_size_t r_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700355
356 if (r->parent || (r->flags & mask) != type)
357 continue;
358 r_size = r->end - r->start + 1;
359 /* For bridges size != alignment */
360 align = (i < PCI_BRIDGE_RESOURCES) ? r_size : r->start;
361 order = __ffs(align) - 20;
362 if (order > 11) {
363 printk(KERN_WARNING "PCI: region %s/%d "
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100364 "too large: 0x%016llx-0x%016llx\n",
Greg Kroah-Hartman1396a8c2006-06-12 15:14:29 -0700365 pci_name(dev), i,
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100366 (unsigned long long)r->start,
367 (unsigned long long)r->end);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700368 r->flags = 0;
369 continue;
370 }
371 size += r_size;
372 if (order < 0)
373 order = 0;
374 /* Exclude ranges with size > align from
375 calculation of the alignment. */
376 if (r_size == align)
377 aligns[order] += align;
378 if (order > max_order)
379 max_order = order;
380 }
381 }
382
383 align = 0;
384 min_align = 0;
385 for (order = 0; order <= max_order; order++) {
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100386#ifdef CONFIG_RESOURCES_64BIT
387 resource_size_t align1 = 1ULL << (order + 20);
388#else
389 resource_size_t align1 = 1U << (order + 20);
390#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700391 if (!align)
392 min_align = align1;
Milind Arun Choudhary6f6f8c22007-07-09 11:55:51 -0700393 else if (ALIGN(align + min_align, min_align) < align1)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700394 min_align = align1 >> 1;
395 align += aligns[order];
396 }
Milind Arun Choudhary6f6f8c22007-07-09 11:55:51 -0700397 size = ALIGN(size, min_align);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700398 if (!size) {
399 b_res->flags = 0;
400 return 1;
401 }
402 b_res->start = min_align;
403 b_res->end = size + min_align - 1;
404 return 1;
405}
406
407static void __devinit
408pci_bus_size_cardbus(struct pci_bus *bus)
409{
410 struct pci_dev *bridge = bus->self;
411 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
412 u16 ctrl;
413
414 /*
415 * Reserve some resources for CardBus. We reserve
416 * a fixed amount of bus space for CardBus bridges.
417 */
Atsushi Nemoto4516a612007-02-05 16:36:06 -0800418 b_res[0].start = pci_cardbus_io_size;
419 b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700420 b_res[0].flags |= IORESOURCE_IO;
421
Atsushi Nemoto4516a612007-02-05 16:36:06 -0800422 b_res[1].start = pci_cardbus_io_size;
423 b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700424 b_res[1].flags |= IORESOURCE_IO;
425
426 /*
427 * Check whether prefetchable memory is supported
428 * by this bridge.
429 */
430 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
431 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
432 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
433 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
434 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
435 }
436
437 /*
438 * If we have prefetchable memory support, allocate
439 * two regions. Otherwise, allocate one region of
440 * twice the size.
441 */
442 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
Atsushi Nemoto4516a612007-02-05 16:36:06 -0800443 b_res[2].start = pci_cardbus_mem_size;
444 b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700445 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
446
Atsushi Nemoto4516a612007-02-05 16:36:06 -0800447 b_res[3].start = pci_cardbus_mem_size;
448 b_res[3].end = b_res[3].start + pci_cardbus_mem_size - 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700449 b_res[3].flags |= IORESOURCE_MEM;
450 } else {
Atsushi Nemoto4516a612007-02-05 16:36:06 -0800451 b_res[3].start = pci_cardbus_mem_size * 2;
452 b_res[3].end = b_res[3].start + pci_cardbus_mem_size * 2 - 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700453 b_res[3].flags |= IORESOURCE_MEM;
454 }
455}
456
Sam Ravnborg451124a2008-02-02 22:33:43 +0100457void __ref pci_bus_size_bridges(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700458{
459 struct pci_dev *dev;
460 unsigned long mask, prefmask;
461
462 list_for_each_entry(dev, &bus->devices, bus_list) {
463 struct pci_bus *b = dev->subordinate;
464 if (!b)
465 continue;
466
467 switch (dev->class >> 8) {
468 case PCI_CLASS_BRIDGE_CARDBUS:
469 pci_bus_size_cardbus(b);
470 break;
471
472 case PCI_CLASS_BRIDGE_PCI:
473 default:
474 pci_bus_size_bridges(b);
475 break;
476 }
477 }
478
479 /* The root bus? */
480 if (!bus->self)
481 return;
482
483 switch (bus->self->class >> 8) {
484 case PCI_CLASS_BRIDGE_CARDBUS:
485 /* don't size cardbuses yet. */
486 break;
487
488 case PCI_CLASS_BRIDGE_PCI:
Gary Hade8fa59132007-10-03 15:55:51 -0700489 /* don't size subtractive decoding (transparent)
490 * PCI-to-PCI bridges */
491 if (bus->self->transparent)
492 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700493 pci_bridge_check_ranges(bus);
Gary Hade8fa59132007-10-03 15:55:51 -0700494 /* fall through */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700495 default:
496 pbus_size_io(bus);
497 /* If the bridge supports prefetchable range, size it
498 separately. If it doesn't, or its prefetchable window
499 has already been allocated by arch code, try
500 non-prefetchable range for both types of PCI memory
501 resources. */
502 mask = IORESOURCE_MEM;
503 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
504 if (pbus_size_mem(bus, prefmask, prefmask))
505 mask = prefmask; /* Success, size non-prefetch only. */
506 pbus_size_mem(bus, mask, IORESOURCE_MEM);
507 break;
508 }
509}
510EXPORT_SYMBOL(pci_bus_size_bridges);
511
Sam Ravnborg451124a2008-02-02 22:33:43 +0100512void __ref pci_bus_assign_resources(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700513{
514 struct pci_bus *b;
515 struct pci_dev *dev;
516
517 pbus_assign_resources_sorted(bus);
518
Linus Torvalds1da177e2005-04-16 15:20:36 -0700519 list_for_each_entry(dev, &bus->devices, bus_list) {
520 b = dev->subordinate;
521 if (!b)
522 continue;
523
524 pci_bus_assign_resources(b);
525
526 switch (dev->class >> 8) {
527 case PCI_CLASS_BRIDGE_PCI:
528 pci_setup_bridge(b);
529 break;
530
531 case PCI_CLASS_BRIDGE_CARDBUS:
532 pci_setup_cardbus(b);
533 break;
534
535 default:
536 printk(KERN_INFO "PCI: not setting up bridge %s "
537 "for bus %d\n", pci_name(dev), b->number);
538 break;
539 }
540 }
541}
542EXPORT_SYMBOL(pci_bus_assign_resources);
543
544void __init
545pci_assign_unassigned_resources(void)
546{
547 struct pci_bus *bus;
548
549 /* Depth first, calculate sizes and alignments of all
550 subordinate buses. */
551 list_for_each_entry(bus, &pci_root_buses, node) {
552 pci_bus_size_bridges(bus);
553 }
554 /* Depth last, allocate resources and update the hardware. */
555 list_for_each_entry(bus, &pci_root_buses, node) {
556 pci_bus_assign_resources(bus);
557 pci_enable_bridges(bus);
558 }
559}