blob: 7b19db598ff45bc4e8a80968cbc5ebc0f04c470a [file] [log] [blame]
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Stephen Hemminger793b8832005-09-14 16:06:14 -070018 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070019 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
Stephen Hemminger793b8832005-09-14 16:06:14 -070026#include <linux/crc32.h>
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070027#include <linux/kernel.h>
28#include <linux/version.h>
29#include <linux/module.h>
30#include <linux/netdevice.h>
Andrew Mortond0bbccf2005-11-10 15:29:27 -080031#include <linux/dma-mapping.h>
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070032#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/pci.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
Stephen Hemminger91c86df2005-12-09 11:34:57 -080039#include <linux/workqueue.h>
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -070040#include <linux/if_vlan.h>
Stephen Hemmingerd70cd512005-12-09 11:35:09 -080041#include <linux/prefetch.h>
shemminger@osdl.orgef743d32005-11-30 11:45:12 -080042#include <linux/mii.h>
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070043
44#include <asm/irq.h>
45
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -070046#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070050#include "sky2.h"
51
52#define DRV_NAME "sky2"
shemminger@osdl.orge981d472006-08-28 10:00:53 -070053#define DRV_VERSION "1.7"
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070054#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
Stephen Hemminger14d02632006-09-26 11:57:43 -070059 * similar to Tigon3.
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070060 */
61
Stephen Hemminger14d02632006-09-26 11:57:43 -070062#define RX_LE_SIZE 1024
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070063#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
Stephen Hemminger14d02632006-09-26 11:57:43 -070064#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
shemminger@osdl.org13210ce2005-11-30 11:45:14 -080065#define RX_DEF_PENDING RX_MAX_PENDING
Stephen Hemminger82788c72006-01-17 13:43:10 -080066#define RX_SKB_ALIGN 8
Stephen Hemminger22e11702006-07-12 15:23:48 -070067#define RX_BUF_WRITE 16
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070068
Stephen Hemminger793b8832005-09-14 16:06:14 -070069#define TX_RING_SIZE 512
70#define TX_DEF_PENDING (TX_RING_SIZE - 1)
71#define TX_MIN_PENDING 64
Stephen Hemmingerb19666d2006-03-07 11:06:36 -080072#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
Stephen Hemminger793b8832005-09-14 16:06:14 -070073
74#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070075#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070076#define TX_WATCHDOG (5 * HZ)
77#define NAPI_WEIGHT 64
78#define PHY_RETRIES 1000
79
Stephen Hemmingercb5d9542006-05-08 15:11:29 -070080#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
81
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070082static const u32 default_msg =
Stephen Hemminger793b8832005-09-14 16:06:14 -070083 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
84 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
Stephen Hemminger3be92a72006-01-17 13:43:17 -080085 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070086
Stephen Hemminger793b8832005-09-14 16:06:14 -070087static int debug = -1; /* defaults above */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070088module_param(debug, int, 0);
89MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
90
Stephen Hemminger14d02632006-09-26 11:57:43 -070091static int copybreak __read_mostly = 128;
Stephen Hemmingerbdb5c582005-12-09 11:34:55 -080092module_param(copybreak, int, 0);
93MODULE_PARM_DESC(copybreak, "Receive copy threshold");
94
Stephen Hemmingerfb2690a2006-03-20 15:48:19 -080095static int disable_msi = 0;
96module_param(disable_msi, int, 0);
97MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
98
Stephen Hemminger01bd7562006-05-08 15:11:30 -070099static int idle_timeout = 100;
100module_param(idle_timeout, int, 0);
101MODULE_PARM_DESC(idle_timeout, "Idle timeout workaround for lost interrupts (ms)");
102
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700103static const struct pci_device_id sky2_id_table[] = {
Stephen Hemminger793b8832005-09-14 16:06:14 -0700104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
Stephen Hemminger2d2a3872006-05-17 14:37:04 -0700106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
Stephen Hemminger2f4a66a2006-09-01 14:52:04 -0700107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
shemminger@osdl.org5a5b1ea2005-11-30 11:45:15 -0800118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
Stephen Hemminger2f4a66a2006-09-01 14:52:04 -0700119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) },
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
shemminger@osdl.org5a5b1ea2005-11-30 11:45:15 -0800123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
Stephen Hemminger5f5d83f2006-07-17 15:38:32 -0400124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) },
Stephen Hemminger57fa4422006-07-29 17:21:55 -0700125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) },
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) },
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) },
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) },
Stephen Hemminger2f4a66a2006-09-01 14:52:04 -0700129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) },
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700130 { 0 }
131};
Stephen Hemminger793b8832005-09-14 16:06:14 -0700132
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700133MODULE_DEVICE_TABLE(pci, sky2_id_table);
134
135/* Avoid conditionals by using array */
136static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
137static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
Stephen Hemmingerf4ea4312006-05-09 14:46:54 -0700138static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700139
Stephen Hemminger92f965e2005-12-09 11:34:53 -0800140/* This driver supports yukon2 chipset only */
141static const char *yukon2_name[] = {
142 "XL", /* 0xb3 */
143 "EC Ultra", /* 0xb4 */
144 "UNKNOWN", /* 0xb5 */
145 "EC", /* 0xb6 */
146 "FE", /* 0xb7 */
Stephen Hemminger793b8832005-09-14 16:06:14 -0700147};
148
Stephen Hemminger793b8832005-09-14 16:06:14 -0700149/* Access to external PHY */
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800150static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700151{
152 int i;
153
154 gma_write16(hw, port, GM_SMI_DATA, val);
155 gma_write16(hw, port, GM_SMI_CTRL,
156 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
157
158 for (i = 0; i < PHY_RETRIES; i++) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700159 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800160 return 0;
Stephen Hemminger793b8832005-09-14 16:06:14 -0700161 udelay(1);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700162 }
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800163
Stephen Hemminger793b8832005-09-14 16:06:14 -0700164 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800165 return -ETIMEDOUT;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700166}
167
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800168static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700169{
170 int i;
171
Stephen Hemminger793b8832005-09-14 16:06:14 -0700172 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700173 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
174
175 for (i = 0; i < PHY_RETRIES; i++) {
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800176 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
177 *val = gma_read16(hw, port, GM_SMI_DATA);
178 return 0;
179 }
180
Stephen Hemminger793b8832005-09-14 16:06:14 -0700181 udelay(1);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700182 }
183
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800184 return -ETIMEDOUT;
185}
186
187static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
188{
189 u16 v;
190
191 if (__gm_phy_read(hw, port, reg, &v) != 0)
192 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
193 return v;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700194}
195
Stephen Hemminger2ccc99b2006-06-13 17:17:27 +0900196static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -0700197{
198 u16 power_control;
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -0700199 int vaux;
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -0700200
201 pr_debug("sky2_set_power_state %d\n", state);
202 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
203
Stephen Hemminger56a645c2006-02-22 11:45:02 -0800204 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
Stephen Hemminger08c06d82006-01-30 11:37:54 -0800205 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -0700206 (power_control & PCI_PM_CAP_PME_D3cold);
207
Stephen Hemminger56a645c2006-02-22 11:45:02 -0800208 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -0700209
210 power_control |= PCI_PM_CTRL_PME_STATUS;
211 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
212
213 switch (state) {
214 case PCI_D0:
215 /* switch power to VCC (WA for VAUX problem) */
216 sky2_write8(hw, B0_POWER_CTRL,
217 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
218
219 /* disable Core Clock Division, */
220 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
221
222 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
223 /* enable bits are inverted */
224 sky2_write8(hw, B2_Y2_CLK_GATE,
225 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
226 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
227 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
228 else
229 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
230
Stephen Hemminger977bdf02006-02-22 11:44:58 -0800231 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
shemminger@osdl.orgd3bcfbe2006-08-28 10:00:51 -0700232 u32 reg1;
233
Stephen Hemminger56a645c2006-02-22 11:45:02 -0800234 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
235 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
Stephen Hemminger977bdf02006-02-22 11:44:58 -0800236 reg1 &= P_ASPM_CONTROL_MSK;
Stephen Hemminger56a645c2006-02-22 11:45:02 -0800237 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
238 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
Stephen Hemminger977bdf02006-02-22 11:44:58 -0800239 }
240
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -0700241 break;
242
243 case PCI_D3hot:
244 case PCI_D3cold:
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -0700245 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
246 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
247 else
248 /* enable bits are inverted */
249 sky2_write8(hw, B2_Y2_CLK_GATE,
250 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
251 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
252 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
253
254 /* switch power to VAUX */
255 if (vaux && state != PCI_D3cold)
256 sky2_write8(hw, B0_POWER_CTRL,
257 (PC_VAUX_ENA | PC_VCC_ENA |
258 PC_VAUX_ON | PC_VCC_OFF));
259 break;
260 default:
261 printk(KERN_ERR PFX "Unknown power state %d\n", state);
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -0700262 }
263
Stephen Hemminger56a645c2006-02-22 11:45:02 -0800264 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -0700265 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -0700266}
267
shemminger@osdl.orgd3bcfbe2006-08-28 10:00:51 -0700268static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700269{
270 u16 reg;
271
272 /* disable all GMAC IRQ's */
273 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
274 /* disable PHY IRQs */
275 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
Stephen Hemminger793b8832005-09-14 16:06:14 -0700276
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700277 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
278 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
279 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
280 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
281
282 reg = gma_read16(hw, port, GM_RX_CTRL);
283 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
284 gma_write16(hw, port, GM_RX_CTRL, reg);
285}
286
287static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
288{
289 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
Stephen Hemminger2eaba1a2006-09-06 12:44:47 -0700290 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700291
Stephen Hemmingered6d32c2006-05-08 15:11:33 -0700292 if (sky2->autoneg == AUTONEG_ENABLE &&
Stephen Hemminger86a31a72006-05-17 14:37:05 -0700293 !(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700294 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
295
296 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
Stephen Hemminger793b8832005-09-14 16:06:14 -0700297 PHY_M_EC_MAC_S_MSK);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700298 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
299
300 if (hw->chip_id == CHIP_ID_YUKON_EC)
301 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
302 else
303 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
304
305 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
306 }
307
308 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
Stephen Hemmingerb89165f2006-09-06 12:44:53 -0700309 if (sky2_is_copper(hw)) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700310 if (hw->chip_id == CHIP_ID_YUKON_FE) {
311 /* enable automatic crossover */
312 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
313 } else {
314 /* disable energy detect */
315 ctrl &= ~PHY_M_PC_EN_DET_MSK;
316
317 /* enable automatic crossover */
318 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
319
320 if (sky2->autoneg == AUTONEG_ENABLE &&
Stephen Hemmingered6d32c2006-05-08 15:11:33 -0700321 (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700322 ctrl &= ~PHY_M_PC_DSC_MSK;
323 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
324 }
325 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700326 } else {
327 /* workaround for deviation #4.88 (CRC errors) */
328 /* disable Automatic Crossover */
329
330 ctrl &= ~PHY_M_PC_MDIX_MSK;
Stephen Hemmingerb89165f2006-09-06 12:44:53 -0700331 }
332
333 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
334
335 /* special setup for PHY 88E1112 Fiber */
336 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
337 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
338
339 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
340 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
341 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
342 ctrl &= ~PHY_M_MAC_MD_MSK;
343 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700344 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
345
Stephen Hemmingerb89165f2006-09-06 12:44:53 -0700346 if (hw->pmd_type == 'P') {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700347 /* select page 1 to access Fiber registers */
348 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
Stephen Hemmingerb89165f2006-09-06 12:44:53 -0700349
350 /* for SFP-module set SIGDET polarity to low */
351 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
352 ctrl |= PHY_M_FIB_SIGD_POL;
353 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700354 }
Stephen Hemmingerb89165f2006-09-06 12:44:53 -0700355
356 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700357 }
358
359 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
360 if (sky2->autoneg == AUTONEG_DISABLE)
361 ctrl &= ~PHY_CT_ANE;
362 else
363 ctrl |= PHY_CT_ANE;
364
365 ctrl |= PHY_CT_RESET;
366 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
367
368 ctrl = 0;
369 ct1000 = 0;
370 adv = PHY_AN_CSMA;
Stephen Hemminger2eaba1a2006-09-06 12:44:47 -0700371 reg = 0;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700372
373 if (sky2->autoneg == AUTONEG_ENABLE) {
Stephen Hemmingerb89165f2006-09-06 12:44:53 -0700374 if (sky2_is_copper(hw)) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700375 if (sky2->advertising & ADVERTISED_1000baseT_Full)
376 ct1000 |= PHY_M_1000C_AFD;
377 if (sky2->advertising & ADVERTISED_1000baseT_Half)
378 ct1000 |= PHY_M_1000C_AHD;
379 if (sky2->advertising & ADVERTISED_100baseT_Full)
380 adv |= PHY_M_AN_100_FD;
381 if (sky2->advertising & ADVERTISED_100baseT_Half)
382 adv |= PHY_M_AN_100_HD;
383 if (sky2->advertising & ADVERTISED_10baseT_Full)
384 adv |= PHY_M_AN_10_FD;
385 if (sky2->advertising & ADVERTISED_10baseT_Half)
386 adv |= PHY_M_AN_10_HD;
Stephen Hemmingerb89165f2006-09-06 12:44:53 -0700387 } else { /* special defines for FIBER (88E1040S only) */
388 if (sky2->advertising & ADVERTISED_1000baseT_Full)
389 adv |= PHY_M_AN_1000X_AFD;
390 if (sky2->advertising & ADVERTISED_1000baseT_Half)
391 adv |= PHY_M_AN_1000X_AHD;
392 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700393
394 /* Set Flow-control capabilities */
395 if (sky2->tx_pause && sky2->rx_pause)
Stephen Hemminger793b8832005-09-14 16:06:14 -0700396 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700397 else if (sky2->rx_pause && !sky2->tx_pause)
Stephen Hemminger793b8832005-09-14 16:06:14 -0700398 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700399 else if (!sky2->rx_pause && sky2->tx_pause)
400 adv |= PHY_AN_PAUSE_ASYM; /* local */
401
402 /* Restart Auto-negotiation */
403 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
404 } else {
405 /* forced speed/duplex settings */
406 ct1000 = PHY_M_1000C_MSE;
407
Stephen Hemminger2eaba1a2006-09-06 12:44:47 -0700408 /* Disable auto update for duplex flow control and speed */
409 reg |= GM_GPCR_AU_ALL_DIS;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700410
411 switch (sky2->speed) {
412 case SPEED_1000:
413 ctrl |= PHY_CT_SP1000;
Stephen Hemminger2eaba1a2006-09-06 12:44:47 -0700414 reg |= GM_GPCR_SPEED_1000;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700415 break;
416 case SPEED_100:
417 ctrl |= PHY_CT_SP100;
Stephen Hemminger2eaba1a2006-09-06 12:44:47 -0700418 reg |= GM_GPCR_SPEED_100;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700419 break;
420 }
421
Stephen Hemminger2eaba1a2006-09-06 12:44:47 -0700422 if (sky2->duplex == DUPLEX_FULL) {
423 reg |= GM_GPCR_DUP_FULL;
424 ctrl |= PHY_CT_DUP_MD;
425 } else if (sky2->speed != SPEED_1000 && hw->chip_id != CHIP_ID_YUKON_EC_U) {
426 /* Turn off flow control for 10/100mbps */
427 sky2->rx_pause = 0;
428 sky2->tx_pause = 0;
429 }
430
431 if (!sky2->rx_pause)
432 reg |= GM_GPCR_FC_RX_DIS;
433
434 if (!sky2->tx_pause)
435 reg |= GM_GPCR_FC_TX_DIS;
436
437 /* Forward pause packets to GMAC? */
438 if (sky2->tx_pause || sky2->rx_pause)
439 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
440 else
441 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
442
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700443 ctrl |= PHY_CT_RESET;
444 }
445
Stephen Hemminger2eaba1a2006-09-06 12:44:47 -0700446 gma_write16(hw, port, GM_GP_CTRL, reg);
447
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700448 if (hw->chip_id != CHIP_ID_YUKON_FE)
449 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
450
451 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
452 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
453
454 /* Setup Phy LED's */
455 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
456 ledover = 0;
457
458 switch (hw->chip_id) {
459 case CHIP_ID_YUKON_FE:
460 /* on 88E3082 these bits are at 11..9 (shifted left) */
461 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
462
463 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
464
465 /* delete ACT LED control bits */
466 ctrl &= ~PHY_M_FELP_LED1_MSK;
467 /* change ACT LED control to blink mode */
468 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
469 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
470 break;
471
472 case CHIP_ID_YUKON_XL:
Stephen Hemminger793b8832005-09-14 16:06:14 -0700473 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700474
475 /* select page 3 to access LED control register */
476 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
477
478 /* set LED Function Control register */
Stephen Hemmingered6d32c2006-05-08 15:11:33 -0700479 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
480 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
481 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
482 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
483 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700484
485 /* set Polarity Control register */
486 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
Stephen Hemminger793b8832005-09-14 16:06:14 -0700487 (PHY_M_POLC_LS1_P_MIX(4) |
488 PHY_M_POLC_IS0_P_MIX(4) |
489 PHY_M_POLC_LOS_CTRL(2) |
490 PHY_M_POLC_INIT_CTRL(2) |
491 PHY_M_POLC_STA1_CTRL(2) |
492 PHY_M_POLC_STA0_CTRL(2)));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700493
494 /* restore page register */
Stephen Hemminger793b8832005-09-14 16:06:14 -0700495 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700496 break;
Stephen Hemmingered6d32c2006-05-08 15:11:33 -0700497 case CHIP_ID_YUKON_EC_U:
498 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
499
500 /* select page 3 to access LED control register */
501 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
502
503 /* set LED Function Control register */
504 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
505 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
506 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
507 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
508 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
509
510 /* set Blink Rate in LED Timer Control Register */
511 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
512 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
513 /* restore page register */
514 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
515 break;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700516
517 default:
518 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
519 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
520 /* turn off the Rx LED (LED_RX) */
521 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
522 }
523
Stephen Hemmingered6d32c2006-05-08 15:11:33 -0700524 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
Stephen Hemminger977bdf02006-02-22 11:44:58 -0800525 /* apply fixes in PHY AFE */
Stephen Hemmingered6d32c2006-05-08 15:11:33 -0700526 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
527 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
528
Stephen Hemminger977bdf02006-02-22 11:44:58 -0800529 /* increase differential signal amplitude in 10BASE-T */
Stephen Hemmingered6d32c2006-05-08 15:11:33 -0700530 gm_phy_write(hw, port, 0x18, 0xaa99);
531 gm_phy_write(hw, port, 0x17, 0x2011);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700532
Stephen Hemminger977bdf02006-02-22 11:44:58 -0800533 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
Stephen Hemmingered6d32c2006-05-08 15:11:33 -0700534 gm_phy_write(hw, port, 0x18, 0xa204);
535 gm_phy_write(hw, port, 0x17, 0x2002);
Stephen Hemminger977bdf02006-02-22 11:44:58 -0800536
537 /* set page register to 0 */
Stephen Hemmingered6d32c2006-05-08 15:11:33 -0700538 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
Stephen Hemminger977bdf02006-02-22 11:44:58 -0800539 } else {
540 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
541
542 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
543 /* turn on 100 Mbps LED (LED_LINK100) */
544 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
545 }
546
547 if (ledover)
548 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
549
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700550 }
Stephen Hemminger2eaba1a2006-09-06 12:44:47 -0700551
shemminger@osdl.orgd571b692005-10-26 12:16:09 -0700552 /* Enable phy interrupt on auto-negotiation complete (or link up) */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700553 if (sky2->autoneg == AUTONEG_ENABLE)
554 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
555 else
556 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
557}
558
shemminger@osdl.orgd3bcfbe2006-08-28 10:00:51 -0700559static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
560{
561 u32 reg1;
562 static const u32 phy_power[]
563 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
564
565 /* looks like this XL is back asswards .. */
566 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
567 onoff = !onoff;
568
569 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
570
571 if (onoff)
572 /* Turn off phy power saving */
573 reg1 &= ~phy_power[port];
574 else
575 reg1 |= phy_power[port];
576
577 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
shemminger@osdl.org98232f82006-08-28 10:00:52 -0700578 sky2_pci_read32(hw, PCI_DEV_REG1);
shemminger@osdl.orgd3bcfbe2006-08-28 10:00:51 -0700579 udelay(100);
580}
581
Stephen Hemminger1b537562005-12-20 15:08:07 -0800582/* Force a renegotiation */
583static void sky2_phy_reinit(struct sky2_port *sky2)
584{
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -0800585 spin_lock_bh(&sky2->phy_lock);
Stephen Hemminger1b537562005-12-20 15:08:07 -0800586 sky2_phy_init(sky2->hw, sky2->port);
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -0800587 spin_unlock_bh(&sky2->phy_lock);
Stephen Hemminger1b537562005-12-20 15:08:07 -0800588}
589
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700590static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
591{
592 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
593 u16 reg;
594 int i;
595 const u8 *addr = hw->dev[port]->dev_addr;
596
shemminger@osdl.org42eeea02005-11-30 11:45:13 -0800597 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
598 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700599
600 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
601
Stephen Hemminger793b8832005-09-14 16:06:14 -0700602 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700603 /* WA DEV_472 -- looks like crossed wires on port 2 */
604 /* clear GMAC 1 Control reset */
605 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
606 do {
607 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
608 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
609 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
610 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
611 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
612 }
613
Stephen Hemminger793b8832005-09-14 16:06:14 -0700614 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700615
Stephen Hemminger2eaba1a2006-09-06 12:44:47 -0700616 /* Enable Transmit FIFO Underrun */
617 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
618
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -0800619 spin_lock_bh(&sky2->phy_lock);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700620 sky2_phy_init(hw, port);
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -0800621 spin_unlock_bh(&sky2->phy_lock);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700622
623 /* MIB clear */
624 reg = gma_read16(hw, port, GM_PHY_ADDR);
625 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
626
Stephen Hemminger43f2f102006-04-05 17:47:15 -0700627 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
628 gma_read16(hw, port, i);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700629 gma_write16(hw, port, GM_PHY_ADDR, reg);
630
631 /* transmit control */
632 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
633
634 /* receive control reg: unicast + multicast + no FCS */
635 gma_write16(hw, port, GM_RX_CTRL,
Stephen Hemminger793b8832005-09-14 16:06:14 -0700636 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700637
638 /* transmit flow control */
639 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
640
641 /* transmit parameter */
642 gma_write16(hw, port, GM_TX_PARAM,
643 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
644 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
645 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
646 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
647
648 /* serial mode register */
649 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -0700650 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700651
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -0700652 if (hw->dev[port]->mtu > ETH_DATA_LEN)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700653 reg |= GM_SMOD_JUMBO_ENA;
654
655 gma_write16(hw, port, GM_SERIAL_MODE, reg);
656
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700657 /* virtual address for data */
658 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
659
Stephen Hemminger793b8832005-09-14 16:06:14 -0700660 /* physical address: used for pause frames */
661 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
662
663 /* ignore counter overflows */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700664 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
665 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
666 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
667
668 /* Configure Rx MAC FIFO */
669 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
Stephen Hemminger70f1be42006-03-07 11:06:37 -0800670 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
671 GMF_OPER_ON | GMF_RX_F_FL_ON);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700672
shemminger@osdl.orgd571b692005-10-26 12:16:09 -0700673 /* Flush Rx MAC FIFO on any flow control or error */
shemminger@osdl.org42eeea02005-11-30 11:45:13 -0800674 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700675
Stephen Hemminger793b8832005-09-14 16:06:14 -0700676 /* Set threshold to 0xa (64 bytes)
677 * ASF disabled so no need to do WA dev #4.30
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700678 */
679 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
680
681 /* Configure Tx MAC FIFO */
682 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
683 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
shemminger@osdl.org5a5b1ea2005-11-30 11:45:15 -0800684
685 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
686 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
687 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
688 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
689 /* set Tx GMAC FIFO Almost Empty Threshold */
690 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
691 /* Disable Store & Forward mode for TX */
692 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
693 }
694 }
695
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700696}
697
Stephen Hemminger1c28f6b2006-01-17 13:43:13 -0800698/* Assign Ram Buffer allocation.
699 * start and end are in units of 4k bytes
700 * ram registers are in units of 64bit words
701 */
702static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700703{
Stephen Hemminger1c28f6b2006-01-17 13:43:13 -0800704 u32 start, end;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700705
Stephen Hemminger1c28f6b2006-01-17 13:43:13 -0800706 start = startk * 4096/8;
707 end = (endk * 4096/8) - 1;
Stephen Hemminger793b8832005-09-14 16:06:14 -0700708
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700709 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
710 sky2_write32(hw, RB_ADDR(q, RB_START), start);
711 sky2_write32(hw, RB_ADDR(q, RB_END), end);
712 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
713 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
714
715 if (q == Q_R1 || q == Q_R2) {
Stephen Hemminger1c28f6b2006-01-17 13:43:13 -0800716 u32 space = (endk - startk) * 4096/8;
717 u32 tp = space - space/4;
Stephen Hemminger793b8832005-09-14 16:06:14 -0700718
Stephen Hemminger1c28f6b2006-01-17 13:43:13 -0800719 /* On receive queue's set the thresholds
720 * give receiver priority when > 3/4 full
721 * send pause when down to 2K
722 */
723 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
724 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
Stephen Hemminger793b8832005-09-14 16:06:14 -0700725
Stephen Hemminger1c28f6b2006-01-17 13:43:13 -0800726 tp = space - 2048/8;
727 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
728 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700729 } else {
730 /* Enable store & forward on Tx queue's because
731 * Tx FIFO is only 1K on Yukon
732 */
733 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
734 }
735
736 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
Stephen Hemminger793b8832005-09-14 16:06:14 -0700737 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700738}
739
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700740/* Setup Bus Memory Interface */
shemminger@osdl.orgaf4ed7e2005-11-30 11:45:21 -0800741static void sky2_qset(struct sky2_hw *hw, u16 q)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700742{
743 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
744 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
745 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
shemminger@osdl.orgaf4ed7e2005-11-30 11:45:21 -0800746 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700747}
748
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700749/* Setup prefetch unit registers. This is the interface between
750 * hardware and driver list elements
751 */
Stephen Hemminger8cc048e2005-12-09 11:35:07 -0800752static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700753 u64 addr, u32 last)
754{
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700755 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
756 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
757 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
758 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
759 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
760 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
Stephen Hemminger793b8832005-09-14 16:06:14 -0700761
762 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700763}
764
Stephen Hemminger793b8832005-09-14 16:06:14 -0700765static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
766{
767 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
768
Stephen Hemmingercb5d9542006-05-08 15:11:29 -0700769 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
Stephen Hemminger291ea612006-09-26 11:57:41 -0700770 le->ctrl = 0;
Stephen Hemminger793b8832005-09-14 16:06:14 -0700771 return le;
772}
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700773
Stephen Hemminger291ea612006-09-26 11:57:41 -0700774static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
775 struct sky2_tx_le *le)
776{
777 return sky2->tx_ring + (le - sky2->tx_le);
778}
779
Stephen Hemminger290d4de2006-03-20 15:48:15 -0800780/* Update chip's next pointer */
781static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700782{
shemminger@osdl.org98232f82006-08-28 10:00:52 -0700783 q = Y2_QADDR(q, PREF_UNIT_PUT_IDX);
Stephen Hemminger762c2de2006-01-17 13:43:14 -0800784 wmb();
shemminger@osdl.org98232f82006-08-28 10:00:52 -0700785 sky2_write16(hw, q, idx);
786 sky2_read16(hw, q);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700787}
788
Stephen Hemminger793b8832005-09-14 16:06:14 -0700789
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700790static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
791{
792 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
Stephen Hemmingercb5d9542006-05-08 15:11:29 -0700793 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
Stephen Hemminger291ea612006-09-26 11:57:41 -0700794 le->ctrl = 0;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700795 return le;
796}
797
shemminger@osdl.orga018e332005-11-30 11:45:16 -0800798/* Return high part of DMA address (could be 32 or 64 bit) */
799static inline u32 high32(dma_addr_t a)
800{
Stephen Hemmingera0361192006-01-17 13:43:16 -0800801 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
shemminger@osdl.orga018e332005-11-30 11:45:16 -0800802}
803
Stephen Hemminger14d02632006-09-26 11:57:43 -0700804/* Build description to hardware for one receive segment */
805static void sky2_rx_add(struct sky2_port *sky2, u8 op,
806 dma_addr_t map, unsigned len)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700807{
808 struct sky2_rx_le *le;
Stephen Hemminger734d1862005-12-09 11:35:00 -0800809 u32 hi = high32(map);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700810
Stephen Hemminger793b8832005-09-14 16:06:14 -0700811 if (sky2->rx_addr64 != hi) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700812 le = sky2_next_rx(sky2);
Stephen Hemminger793b8832005-09-14 16:06:14 -0700813 le->addr = cpu_to_le32(hi);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700814 le->opcode = OP_ADDR64 | HW_OWNER;
Stephen Hemminger734d1862005-12-09 11:35:00 -0800815 sky2->rx_addr64 = high32(map + len);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700816 }
Stephen Hemminger793b8832005-09-14 16:06:14 -0700817
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700818 le = sky2_next_rx(sky2);
Stephen Hemminger734d1862005-12-09 11:35:00 -0800819 le->addr = cpu_to_le32((u32) map);
820 le->length = cpu_to_le16(len);
Stephen Hemminger14d02632006-09-26 11:57:43 -0700821 le->opcode = op | HW_OWNER;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700822}
823
Stephen Hemminger14d02632006-09-26 11:57:43 -0700824/* Build description to hardware for one possibly fragmented skb */
825static void sky2_rx_submit(struct sky2_port *sky2,
826 const struct rx_ring_info *re)
827{
828 int i;
829
830 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
831
832 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
833 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
834}
835
836
837static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
838 unsigned size)
839{
840 struct sk_buff *skb = re->skb;
841 int i;
842
843 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
844 pci_unmap_len_set(re, data_size, size);
845
846 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
847 re->frag_addr[i] = pci_map_page(pdev,
848 skb_shinfo(skb)->frags[i].page,
849 skb_shinfo(skb)->frags[i].page_offset,
850 skb_shinfo(skb)->frags[i].size,
851 PCI_DMA_FROMDEVICE);
852}
853
854static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
855{
856 struct sk_buff *skb = re->skb;
857 int i;
858
859 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
860 PCI_DMA_FROMDEVICE);
861
862 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
863 pci_unmap_page(pdev, re->frag_addr[i],
864 skb_shinfo(skb)->frags[i].size,
865 PCI_DMA_FROMDEVICE);
866}
Stephen Hemminger793b8832005-09-14 16:06:14 -0700867
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700868/* Tell chip where to start receive checksum.
869 * Actually has two checksums, but set both same to avoid possible byte
870 * order problems.
871 */
Stephen Hemminger793b8832005-09-14 16:06:14 -0700872static void rx_set_checksum(struct sky2_port *sky2)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700873{
874 struct sky2_rx_le *le;
875
Stephen Hemminger793b8832005-09-14 16:06:14 -0700876 le = sky2_next_rx(sky2);
Stephen Hemmingerf65b1382006-09-06 12:45:02 -0700877 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
Stephen Hemminger793b8832005-09-14 16:06:14 -0700878 le->ctrl = 0;
879 le->opcode = OP_TCPSTART | HW_OWNER;
880
Stephen Hemminger793b8832005-09-14 16:06:14 -0700881 sky2_write32(sky2->hw,
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700882 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
883 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
884
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700885}
886
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -0700887/*
888 * The RX Stop command will not work for Yukon-2 if the BMU does not
889 * reach the end of packet and since we can't make sure that we have
890 * incoming data, we must reset the BMU while it is not doing a DMA
891 * transfer. Since it is possible that the RX path is still active,
892 * the RX RAM buffer will be stopped first, so any possible incoming
893 * data will not trigger a DMA. After the RAM buffer is stopped, the
894 * BMU is polled until any DMA in progress is ended and only then it
895 * will be reset.
896 */
897static void sky2_rx_stop(struct sky2_port *sky2)
898{
899 struct sky2_hw *hw = sky2->hw;
900 unsigned rxq = rxqaddr[sky2->port];
901 int i;
902
903 /* disable the RAM Buffer receive queue */
904 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
905
906 for (i = 0; i < 0xffff; i++)
907 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
908 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
909 goto stopped;
910
911 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
912 sky2->netdev->name);
913stopped:
914 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
915
916 /* reset the Rx prefetch unit */
917 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
918}
Stephen Hemminger793b8832005-09-14 16:06:14 -0700919
shemminger@osdl.orgd571b692005-10-26 12:16:09 -0700920/* Clean out receive buffer area, assumes receiver hardware stopped */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700921static void sky2_rx_clean(struct sky2_port *sky2)
922{
923 unsigned i;
924
925 memset(sky2->rx_le, 0, RX_LE_BYTES);
Stephen Hemminger793b8832005-09-14 16:06:14 -0700926 for (i = 0; i < sky2->rx_pending; i++) {
Stephen Hemminger291ea612006-09-26 11:57:41 -0700927 struct rx_ring_info *re = sky2->rx_ring + i;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700928
929 if (re->skb) {
Stephen Hemminger14d02632006-09-26 11:57:43 -0700930 sky2_rx_unmap_skb(sky2->hw->pdev, re);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700931 kfree_skb(re->skb);
932 re->skb = NULL;
933 }
934 }
935}
936
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800937/* Basic MII support */
938static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
939{
940 struct mii_ioctl_data *data = if_mii(ifr);
941 struct sky2_port *sky2 = netdev_priv(dev);
942 struct sky2_hw *hw = sky2->hw;
943 int err = -EOPNOTSUPP;
944
945 if (!netif_running(dev))
946 return -ENODEV; /* Phy still in reset */
947
Stephen Hemmingerd89e1342006-03-20 15:48:20 -0800948 switch (cmd) {
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800949 case SIOCGMIIPHY:
950 data->phy_id = PHY_ADDR_MARV;
951
952 /* fallthru */
953 case SIOCGMIIREG: {
954 u16 val = 0;
Stephen Hemminger91c86df2005-12-09 11:34:57 -0800955
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -0800956 spin_lock_bh(&sky2->phy_lock);
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800957 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -0800958 spin_unlock_bh(&sky2->phy_lock);
Stephen Hemminger91c86df2005-12-09 11:34:57 -0800959
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800960 data->val_out = val;
961 break;
962 }
963
964 case SIOCSMIIREG:
965 if (!capable(CAP_NET_ADMIN))
966 return -EPERM;
967
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -0800968 spin_lock_bh(&sky2->phy_lock);
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800969 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
970 data->val_in);
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -0800971 spin_unlock_bh(&sky2->phy_lock);
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800972 break;
973 }
974 return err;
975}
976
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -0700977#ifdef SKY2_VLAN_TAG_USED
978static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
979{
980 struct sky2_port *sky2 = netdev_priv(dev);
981 struct sky2_hw *hw = sky2->hw;
982 u16 port = sky2->port;
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -0700983
Stephen Hemminger2bb8c262006-09-26 11:57:42 -0700984 netif_tx_lock_bh(dev);
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -0700985
986 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
987 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
988 sky2->vlgrp = grp;
989
Stephen Hemminger2bb8c262006-09-26 11:57:42 -0700990 netif_tx_unlock_bh(dev);
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -0700991}
992
993static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
994{
995 struct sky2_port *sky2 = netdev_priv(dev);
996 struct sky2_hw *hw = sky2->hw;
997 u16 port = sky2->port;
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -0700998
Stephen Hemminger2bb8c262006-09-26 11:57:42 -0700999 netif_tx_lock_bh(dev);
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -07001000
1001 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
1002 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
1003 if (sky2->vlgrp)
1004 sky2->vlgrp->vlan_devices[vid] = NULL;
1005
Stephen Hemminger2bb8c262006-09-26 11:57:42 -07001006 netif_tx_unlock_bh(dev);
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -07001007}
1008#endif
1009
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001010/*
Stephen Hemminger14d02632006-09-26 11:57:43 -07001011 * Allocate an skb for receiving. If the MTU is large enough
1012 * make the skb non-linear with a fragment list of pages.
1013 *
Stephen Hemminger82788c72006-01-17 13:43:10 -08001014 * It appears the hardware has a bug in the FIFO logic that
1015 * cause it to hang if the FIFO gets overrun and the receive buffer
shemminger@osdl.org497d7c82006-08-28 10:00:46 -07001016 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1017 * aligned except if slab debugging is enabled.
Stephen Hemminger82788c72006-01-17 13:43:10 -08001018 */
Stephen Hemminger14d02632006-09-26 11:57:43 -07001019static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
Stephen Hemminger82788c72006-01-17 13:43:10 -08001020{
1021 struct sk_buff *skb;
Stephen Hemminger14d02632006-09-26 11:57:43 -07001022 unsigned long p;
1023 int i;
Stephen Hemminger82788c72006-01-17 13:43:10 -08001024
Stephen Hemminger14d02632006-09-26 11:57:43 -07001025 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1026 if (!skb)
1027 goto nomem;
1028
1029 p = (unsigned long) skb->data;
1030 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1031
1032 for (i = 0; i < sky2->rx_nfrags; i++) {
1033 struct page *page = alloc_page(GFP_ATOMIC);
1034
1035 if (!page)
1036 goto free_partial;
1037 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
Stephen Hemminger82788c72006-01-17 13:43:10 -08001038 }
1039
1040 return skb;
Stephen Hemminger14d02632006-09-26 11:57:43 -07001041free_partial:
1042 kfree_skb(skb);
1043nomem:
1044 return NULL;
Stephen Hemminger82788c72006-01-17 13:43:10 -08001045}
1046
1047/*
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001048 * Allocate and setup receiver buffer pool.
Stephen Hemminger14d02632006-09-26 11:57:43 -07001049 * Normal case this ends up creating one list element for skb
1050 * in the receive ring. Worst case if using large MTU and each
1051 * allocation falls on a different 64 bit region, that results
1052 * in 6 list elements per ring entry.
1053 * One element is used for checksum enable/disable, and one
1054 * extra to avoid wrap.
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001055 */
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001056static int sky2_rx_start(struct sky2_port *sky2)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001057{
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001058 struct sky2_hw *hw = sky2->hw;
Stephen Hemminger14d02632006-09-26 11:57:43 -07001059 struct rx_ring_info *re;
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001060 unsigned rxq = rxqaddr[sky2->port];
Stephen Hemminger14d02632006-09-26 11:57:43 -07001061 unsigned i, size, space, thresh;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001062
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001063 sky2->rx_put = sky2->rx_next = 0;
shemminger@osdl.orgaf4ed7e2005-11-30 11:45:21 -08001064 sky2_qset(hw, rxq);
Stephen Hemminger977bdf02006-02-22 11:44:58 -08001065
1066 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
1067 /* MAC Rx RAM Read is controlled by hardware */
1068 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
1069 }
1070
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001071 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1072
1073 rx_set_checksum(sky2);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001074
Stephen Hemminger14d02632006-09-26 11:57:43 -07001075 /* Space needed for frame data + headers rounded up */
1076 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
1077 + 8;
1078
1079 /* Stopping point for hardware truncation */
1080 thresh = (size - 8) / sizeof(u32);
1081
1082 /* Account for overhead of skb - to avoid order > 0 allocation */
1083 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1084 + sizeof(struct skb_shared_info);
1085
1086 sky2->rx_nfrags = space >> PAGE_SHIFT;
1087 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1088
1089 if (sky2->rx_nfrags != 0) {
1090 /* Compute residue after pages */
1091 space = sky2->rx_nfrags << PAGE_SHIFT;
1092
1093 if (space < size)
1094 size -= space;
1095 else
1096 size = 0;
1097
1098 /* Optimize to handle small packets and headers */
1099 if (size < copybreak)
1100 size = copybreak;
1101 if (size < ETH_HLEN)
1102 size = ETH_HLEN;
1103 }
1104 sky2->rx_data_size = size;
1105
1106 /* Fill Rx ring */
1107 for (i = 0; i < sky2->rx_pending; i++) {
1108 re = sky2->rx_ring + i;
1109
1110 re->skb = sky2_rx_alloc(sky2);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001111 if (!re->skb)
1112 goto nomem;
1113
Stephen Hemminger14d02632006-09-26 11:57:43 -07001114 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1115 sky2_rx_submit(sky2, re);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001116 }
1117
Stephen Hemmingera1433ac2006-05-22 12:03:42 -07001118 /*
1119 * The receiver hangs if it receives frames larger than the
1120 * packet buffer. As a workaround, truncate oversize frames, but
1121 * the register is limited to 9 bits, so if you do frames > 2052
1122 * you better get the MTU right!
1123 */
Stephen Hemmingera1433ac2006-05-22 12:03:42 -07001124 if (thresh > 0x1ff)
1125 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1126 else {
1127 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1128 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1129 }
1130
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001131 /* Tell chip about available buffers */
1132 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001133 return 0;
1134nomem:
1135 sky2_rx_clean(sky2);
1136 return -ENOMEM;
1137}
1138
1139/* Bring up network interface. */
1140static int sky2_up(struct net_device *dev)
1141{
1142 struct sky2_port *sky2 = netdev_priv(dev);
1143 struct sky2_hw *hw = sky2->hw;
1144 unsigned port = sky2->port;
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001145 u32 ramsize, rxspace, imask;
Stephen Hemmingeree7abb02006-05-18 11:16:21 -07001146 int cap, err = -ENOMEM;
Stephen Hemminger843a46f2006-05-11 15:07:28 -07001147 struct net_device *otherdev = hw->dev[sky2->port^1];
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001148
Stephen Hemmingeree7abb02006-05-18 11:16:21 -07001149 /*
1150 * On dual port PCI-X card, there is an problem where status
1151 * can be received out of order due to split transactions
Stephen Hemminger843a46f2006-05-11 15:07:28 -07001152 */
Stephen Hemmingeree7abb02006-05-18 11:16:21 -07001153 if (otherdev && netif_running(otherdev) &&
1154 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1155 struct sky2_port *osky2 = netdev_priv(otherdev);
1156 u16 cmd;
Stephen Hemminger843a46f2006-05-11 15:07:28 -07001157
Stephen Hemmingeree7abb02006-05-18 11:16:21 -07001158 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1159 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1160 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1161
1162 sky2->rx_csum = 0;
1163 osky2->rx_csum = 0;
1164 }
1165
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001166 if (netif_msg_ifup(sky2))
1167 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1168
1169 /* must be power of 2 */
1170 sky2->tx_le = pci_alloc_consistent(hw->pdev,
Stephen Hemminger793b8832005-09-14 16:06:14 -07001171 TX_RING_SIZE *
1172 sizeof(struct sky2_tx_le),
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001173 &sky2->tx_le_map);
1174 if (!sky2->tx_le)
1175 goto err_out;
1176
Stephen Hemminger6cdbbdf2005-12-09 11:35:01 -08001177 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001178 GFP_KERNEL);
1179 if (!sky2->tx_ring)
1180 goto err_out;
1181 sky2->tx_prod = sky2->tx_cons = 0;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001182
1183 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1184 &sky2->rx_le_map);
1185 if (!sky2->rx_le)
1186 goto err_out;
1187 memset(sky2->rx_le, 0, RX_LE_BYTES);
1188
Stephen Hemminger291ea612006-09-26 11:57:41 -07001189 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001190 GFP_KERNEL);
1191 if (!sky2->rx_ring)
1192 goto err_out;
1193
shemminger@osdl.orgd3bcfbe2006-08-28 10:00:51 -07001194 sky2_phy_power(hw, port, 1);
1195
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001196 sky2_mac_init(hw, port);
1197
Stephen Hemminger1c28f6b2006-01-17 13:43:13 -08001198 /* Determine available ram buffer space (in 4K blocks).
1199 * Note: not sure about the FE setting below yet
1200 */
1201 if (hw->chip_id == CHIP_ID_YUKON_FE)
1202 ramsize = 4;
1203 else
1204 ramsize = sky2_read8(hw, B2_E_0);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001205
Stephen Hemminger1c28f6b2006-01-17 13:43:13 -08001206 /* Give transmitter one third (rounded up) */
1207 rxspace = ramsize - (ramsize + 2) / 3;
1208
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001209 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
Stephen Hemminger1c28f6b2006-01-17 13:43:13 -08001210 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001211
Stephen Hemminger793b8832005-09-14 16:06:14 -07001212 /* Make sure SyncQ is disabled */
1213 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1214 RB_RST_SET);
1215
shemminger@osdl.orgaf4ed7e2005-11-30 11:45:21 -08001216 sky2_qset(hw, txqaddr[port]);
shemminger@osdl.org5a5b1ea2005-11-30 11:45:15 -08001217
Stephen Hemminger977bdf02006-02-22 11:44:58 -08001218 /* Set almost empty threshold */
Stephen Hemmingerc2716fb2006-09-26 11:57:39 -07001219 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1220 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
Stephen Hemminger977bdf02006-02-22 11:44:58 -08001221 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
shemminger@osdl.org5a5b1ea2005-11-30 11:45:15 -08001222
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001223 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1224 TX_RING_SIZE - 1);
1225
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001226 err = sky2_rx_start(sky2);
1227 if (err)
1228 goto err_out;
1229
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001230 /* Enable interrupts from phy/mac for port */
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001231 imask = sky2_read32(hw, B0_IMSK);
Stephen Hemmingerf4ea4312006-05-09 14:46:54 -07001232 imask |= portirq_msk[port];
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001233 sky2_write32(hw, B0_IMSK, imask);
1234
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001235 return 0;
1236
1237err_out:
Stephen Hemminger1b537562005-12-20 15:08:07 -08001238 if (sky2->rx_le) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001239 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1240 sky2->rx_le, sky2->rx_le_map);
Stephen Hemminger1b537562005-12-20 15:08:07 -08001241 sky2->rx_le = NULL;
1242 }
1243 if (sky2->tx_le) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001244 pci_free_consistent(hw->pdev,
1245 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1246 sky2->tx_le, sky2->tx_le_map);
Stephen Hemminger1b537562005-12-20 15:08:07 -08001247 sky2->tx_le = NULL;
1248 }
1249 kfree(sky2->tx_ring);
1250 kfree(sky2->rx_ring);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001251
Stephen Hemminger1b537562005-12-20 15:08:07 -08001252 sky2->tx_ring = NULL;
1253 sky2->rx_ring = NULL;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001254 return err;
1255}
1256
Stephen Hemminger793b8832005-09-14 16:06:14 -07001257/* Modular subtraction in ring */
1258static inline int tx_dist(unsigned tail, unsigned head)
1259{
Stephen Hemmingercb5d9542006-05-08 15:11:29 -07001260 return (head - tail) & (TX_RING_SIZE - 1);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001261}
1262
1263/* Number of list elements available for next tx */
1264static inline int tx_avail(const struct sky2_port *sky2)
1265{
1266 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1267}
1268
1269/* Estimate of number of transmit list elements required */
Stephen Hemminger28bd1812006-01-17 13:43:19 -08001270static unsigned tx_le_req(const struct sk_buff *skb)
Stephen Hemminger793b8832005-09-14 16:06:14 -07001271{
1272 unsigned count;
1273
1274 count = sizeof(dma_addr_t) / sizeof(u32);
1275 count += skb_shinfo(skb)->nr_frags * count;
1276
Herbert Xu89114af2006-07-08 13:34:32 -07001277 if (skb_is_gso(skb))
Stephen Hemminger793b8832005-09-14 16:06:14 -07001278 ++count;
1279
Patrick McHardy84fa7932006-08-29 16:44:56 -07001280 if (skb->ip_summed == CHECKSUM_PARTIAL)
Stephen Hemminger793b8832005-09-14 16:06:14 -07001281 ++count;
1282
1283 return count;
1284}
1285
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001286/*
Stephen Hemminger793b8832005-09-14 16:06:14 -07001287 * Put one packet in ring for transmit.
1288 * A single packet can generate multiple list elements, and
1289 * the number of ring elements will probably be less than the number
1290 * of list elements used.
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001291 */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001292static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1293{
1294 struct sky2_port *sky2 = netdev_priv(dev);
1295 struct sky2_hw *hw = sky2->hw;
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -07001296 struct sky2_tx_le *le = NULL;
Stephen Hemminger6cdbbdf2005-12-09 11:35:01 -08001297 struct tx_ring_info *re;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001298 unsigned i, len;
1299 dma_addr_t mapping;
1300 u32 addr64;
1301 u16 mss;
1302 u8 ctrl;
1303
Stephen Hemminger2bb8c262006-09-26 11:57:42 -07001304 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1305 return NETDEV_TX_BUSY;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001306
Stephen Hemminger793b8832005-09-14 16:06:14 -07001307 if (unlikely(netif_msg_tx_queued(sky2)))
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001308 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1309 dev->name, sky2->tx_prod, skb->len);
1310
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001311 len = skb_headlen(skb);
1312 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
shemminger@osdl.orga018e332005-11-30 11:45:16 -08001313 addr64 = high32(mapping);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001314
shemminger@osdl.orga018e332005-11-30 11:45:16 -08001315 /* Send high bits if changed or crosses boundary */
1316 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
Stephen Hemminger793b8832005-09-14 16:06:14 -07001317 le = get_tx_le(sky2);
Stephen Hemmingerf65b1382006-09-06 12:45:02 -07001318 le->addr = cpu_to_le32(addr64);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001319 le->opcode = OP_ADDR64 | HW_OWNER;
shemminger@osdl.orga018e332005-11-30 11:45:16 -08001320 sky2->tx_addr64 = high32(mapping + len);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001321 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001322
1323 /* Check for TCP Segmentation Offload */
Herbert Xu79671682006-06-22 02:40:14 -07001324 mss = skb_shinfo(skb)->gso_size;
Stephen Hemminger793b8832005-09-14 16:06:14 -07001325 if (mss != 0) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001326 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1327 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1328 mss += ETH_HLEN;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001329
shemminger@osdl.orge07560c2006-08-28 10:00:49 -07001330 if (mss != sky2->tx_last_mss) {
1331 le = get_tx_le(sky2);
Stephen Hemmingerf65b1382006-09-06 12:45:02 -07001332 le->addr = cpu_to_le32(mss);
shemminger@osdl.orge07560c2006-08-28 10:00:49 -07001333 le->opcode = OP_LRGLEN | HW_OWNER;
shemminger@osdl.orge07560c2006-08-28 10:00:49 -07001334 sky2->tx_last_mss = mss;
1335 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001336 }
1337
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001338 ctrl = 0;
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -07001339#ifdef SKY2_VLAN_TAG_USED
1340 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1341 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1342 if (!le) {
1343 le = get_tx_le(sky2);
Stephen Hemmingerf65b1382006-09-06 12:45:02 -07001344 le->addr = 0;
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -07001345 le->opcode = OP_VLAN|HW_OWNER;
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -07001346 } else
1347 le->opcode |= OP_VLAN;
1348 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1349 ctrl |= INS_VLAN;
1350 }
1351#endif
1352
1353 /* Handle TCP checksum offload */
Patrick McHardy84fa7932006-08-29 16:44:56 -07001354 if (skb->ip_summed == CHECKSUM_PARTIAL) {
Stephen Hemmingerf65b1382006-09-06 12:45:02 -07001355 unsigned offset = skb->h.raw - skb->data;
1356 u32 tcpsum;
1357
1358 tcpsum = offset << 16; /* sum start */
1359 tcpsum |= offset + skb->csum; /* sum write */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001360
1361 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1362 if (skb->nh.iph->protocol == IPPROTO_UDP)
1363 ctrl |= UDPTCP;
1364
Stephen Hemmingerf65b1382006-09-06 12:45:02 -07001365 if (tcpsum != sky2->tx_tcpsum) {
1366 sky2->tx_tcpsum = tcpsum;
shemminger@osdl.org1d179332006-08-28 10:00:50 -07001367
1368 le = get_tx_le(sky2);
Stephen Hemmingerf65b1382006-09-06 12:45:02 -07001369 le->addr = cpu_to_le32(tcpsum);
shemminger@osdl.org1d179332006-08-28 10:00:50 -07001370 le->length = 0; /* initial checksum value */
1371 le->ctrl = 1; /* one packet */
1372 le->opcode = OP_TCPLISW | HW_OWNER;
1373 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001374 }
1375
1376 le = get_tx_le(sky2);
Stephen Hemmingerf65b1382006-09-06 12:45:02 -07001377 le->addr = cpu_to_le32((u32) mapping);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001378 le->length = cpu_to_le16(len);
1379 le->ctrl = ctrl;
Stephen Hemminger793b8832005-09-14 16:06:14 -07001380 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001381
Stephen Hemminger291ea612006-09-26 11:57:41 -07001382 re = tx_le_re(sky2, le);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001383 re->skb = skb;
Stephen Hemminger6cdbbdf2005-12-09 11:35:01 -08001384 pci_unmap_addr_set(re, mapaddr, mapping);
Stephen Hemminger291ea612006-09-26 11:57:41 -07001385 pci_unmap_len_set(re, maplen, len);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001386
1387 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
Stephen Hemminger291ea612006-09-26 11:57:41 -07001388 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001389
1390 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1391 frag->size, PCI_DMA_TODEVICE);
Stephen Hemmingera0361192006-01-17 13:43:16 -08001392 addr64 = high32(mapping);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001393 if (addr64 != sky2->tx_addr64) {
1394 le = get_tx_le(sky2);
Stephen Hemmingerf65b1382006-09-06 12:45:02 -07001395 le->addr = cpu_to_le32(addr64);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001396 le->ctrl = 0;
1397 le->opcode = OP_ADDR64 | HW_OWNER;
1398 sky2->tx_addr64 = addr64;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001399 }
1400
1401 le = get_tx_le(sky2);
Stephen Hemmingerf65b1382006-09-06 12:45:02 -07001402 le->addr = cpu_to_le32((u32) mapping);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001403 le->length = cpu_to_le16(frag->size);
1404 le->ctrl = ctrl;
Stephen Hemminger793b8832005-09-14 16:06:14 -07001405 le->opcode = OP_BUFFER | HW_OWNER;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001406
Stephen Hemminger291ea612006-09-26 11:57:41 -07001407 re = tx_le_re(sky2, le);
1408 re->skb = skb;
1409 pci_unmap_addr_set(re, mapaddr, mapping);
1410 pci_unmap_len_set(re, maplen, frag->size);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001411 }
Stephen Hemminger6cdbbdf2005-12-09 11:35:01 -08001412
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001413 le->ctrl |= EOP;
1414
shemminger@osdl.org97bda702006-08-28 10:00:47 -07001415 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1416 netif_stop_queue(dev);
Stephen Hemmingerb19666d2006-03-07 11:06:36 -08001417
Stephen Hemminger290d4de2006-03-20 15:48:15 -08001418 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001419
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001420 dev->trans_start = jiffies;
1421 return NETDEV_TX_OK;
1422}
1423
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001424/*
Stephen Hemminger793b8832005-09-14 16:06:14 -07001425 * Free ring elements from starting at tx_cons until "done"
1426 *
1427 * NB: the hardware will tell us about partial completion of multi-part
Stephen Hemminger291ea612006-09-26 11:57:41 -07001428 * buffers so make sure not to free skb to early.
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001429 */
shemminger@osdl.orgd11c13e2005-09-27 15:02:56 -07001430static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001431{
shemminger@osdl.orgd11c13e2005-09-27 15:02:56 -07001432 struct net_device *dev = sky2->netdev;
Stephen Hemmingeraf2a58a2005-12-09 11:35:04 -08001433 struct pci_dev *pdev = sky2->hw->pdev;
Stephen Hemminger291ea612006-09-26 11:57:41 -07001434 unsigned idx;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001435
Stephen Hemminger0e3ff6a2005-12-09 11:35:02 -08001436 BUG_ON(done >= TX_RING_SIZE);
shemminger@osdl.org22247952005-11-30 11:45:19 -08001437
Stephen Hemminger291ea612006-09-26 11:57:41 -07001438 for (idx = sky2->tx_cons; idx != done;
1439 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1440 struct sky2_tx_le *le = sky2->tx_le + idx;
1441 struct tx_ring_info *re = sky2->tx_ring + idx;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001442
Stephen Hemminger291ea612006-09-26 11:57:41 -07001443 switch(le->opcode & ~HW_OWNER) {
1444 case OP_LARGESEND:
1445 case OP_PACKET:
1446 pci_unmap_single(pdev,
1447 pci_unmap_addr(re, mapaddr),
1448 pci_unmap_len(re, maplen),
1449 PCI_DMA_TODEVICE);
Stephen Hemmingeraf2a58a2005-12-09 11:35:04 -08001450 break;
Stephen Hemminger291ea612006-09-26 11:57:41 -07001451 case OP_BUFFER:
1452 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1453 pci_unmap_len(re, maplen),
Stephen Hemminger734d1862005-12-09 11:35:00 -08001454 PCI_DMA_TODEVICE);
Stephen Hemminger291ea612006-09-26 11:57:41 -07001455 break;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001456 }
1457
Stephen Hemminger291ea612006-09-26 11:57:41 -07001458 if (le->ctrl & EOP) {
1459 if (unlikely(netif_msg_tx_done(sky2)))
1460 printk(KERN_DEBUG "%s: tx done %u\n",
1461 dev->name, idx);
1462 dev_kfree_skb(re->skb);
1463 }
1464
1465 le->opcode = 0; /* paranoia */
Stephen Hemminger793b8832005-09-14 16:06:14 -07001466 }
Stephen Hemminger793b8832005-09-14 16:06:14 -07001467
Stephen Hemminger291ea612006-09-26 11:57:41 -07001468 sky2->tx_cons = idx;
Stephen Hemminger22e11702006-07-12 15:23:48 -07001469 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001470 netif_wake_queue(dev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001471}
1472
1473/* Cleanup all untransmitted buffers, assume transmitter not running */
Stephen Hemminger2bb8c262006-09-26 11:57:42 -07001474static void sky2_tx_clean(struct net_device *dev)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001475{
Stephen Hemminger2bb8c262006-09-26 11:57:42 -07001476 struct sky2_port *sky2 = netdev_priv(dev);
1477
1478 netif_tx_lock_bh(dev);
shemminger@osdl.orgd11c13e2005-09-27 15:02:56 -07001479 sky2_tx_complete(sky2, sky2->tx_prod);
Stephen Hemminger2bb8c262006-09-26 11:57:42 -07001480 netif_tx_unlock_bh(dev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001481}
1482
1483/* Network shutdown */
1484static int sky2_down(struct net_device *dev)
1485{
1486 struct sky2_port *sky2 = netdev_priv(dev);
1487 struct sky2_hw *hw = sky2->hw;
1488 unsigned port = sky2->port;
1489 u16 ctrl;
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001490 u32 imask;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001491
Stephen Hemminger1b537562005-12-20 15:08:07 -08001492 /* Never really got started! */
1493 if (!sky2->tx_le)
1494 return 0;
1495
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001496 if (netif_msg_ifdown(sky2))
1497 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1498
shemminger@osdl.org018d1c62005-11-30 11:45:18 -08001499 /* Stop more packets from being queued */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001500 netif_stop_queue(dev);
1501
shemminger@osdl.orgd3bcfbe2006-08-28 10:00:51 -07001502 sky2_gmac_reset(hw, port);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001503
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001504 /* Stop transmitter */
1505 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1506 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1507
1508 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
Stephen Hemminger793b8832005-09-14 16:06:14 -07001509 RB_RST_SET | RB_DIS_OP_MD);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001510
Stephen Hemmingerc2716fb2006-09-26 11:57:39 -07001511 /* WA for dev. #4.209 */
1512 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1513 && hw->chip_rev == CHIP_REV_YU_EC_U_A1)
1514 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1515 sky2->speed != SPEED_1000 ?
1516 TX_STFW_ENA : TX_STFW_DIS);
1517
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001518 ctrl = gma_read16(hw, port, GM_GP_CTRL);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001519 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001520 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1521
1522 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1523
1524 /* Workaround shared GMAC reset */
Stephen Hemminger793b8832005-09-14 16:06:14 -07001525 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1526 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001527 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1528
1529 /* Disable Force Sync bit and Enable Alloc bit */
1530 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1531 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1532
1533 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1534 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1535 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1536
1537 /* Reset the PCI FIFO of the async Tx queue */
Stephen Hemminger793b8832005-09-14 16:06:14 -07001538 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1539 BMU_RST_SET | BMU_FIFO_RST);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001540
1541 /* Reset the Tx prefetch units */
1542 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1543 PREF_UNIT_RST_SET);
1544
1545 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1546
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001547 sky2_rx_stop(sky2);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001548
1549 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1550 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1551
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001552 /* Disable port IRQ */
1553 imask = sky2_read32(hw, B0_IMSK);
Stephen Hemmingerf4ea4312006-05-09 14:46:54 -07001554 imask &= ~portirq_msk[port];
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001555 sky2_write32(hw, B0_IMSK, imask);
1556
shemminger@osdl.orgd3bcfbe2006-08-28 10:00:51 -07001557 sky2_phy_power(hw, port, 0);
1558
shemminger@osdl.orgd571b692005-10-26 12:16:09 -07001559 /* turn off LED's */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001560 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1561
shemminger@osdl.org018d1c62005-11-30 11:45:18 -08001562 synchronize_irq(hw->pdev->irq);
1563
Stephen Hemminger2bb8c262006-09-26 11:57:42 -07001564 sky2_tx_clean(dev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001565 sky2_rx_clean(sky2);
1566
1567 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1568 sky2->rx_le, sky2->rx_le_map);
1569 kfree(sky2->rx_ring);
1570
1571 pci_free_consistent(hw->pdev,
1572 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1573 sky2->tx_le, sky2->tx_le_map);
1574 kfree(sky2->tx_ring);
1575
Stephen Hemminger1b537562005-12-20 15:08:07 -08001576 sky2->tx_le = NULL;
1577 sky2->rx_le = NULL;
1578
1579 sky2->rx_ring = NULL;
1580 sky2->tx_ring = NULL;
1581
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001582 return 0;
1583}
1584
1585static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1586{
Stephen Hemmingerb89165f2006-09-06 12:44:53 -07001587 if (!sky2_is_copper(hw))
Stephen Hemminger793b8832005-09-14 16:06:14 -07001588 return SPEED_1000;
1589
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001590 if (hw->chip_id == CHIP_ID_YUKON_FE)
1591 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1592
1593 switch (aux & PHY_M_PS_SPEED_MSK) {
1594 case PHY_M_PS_SPEED_1000:
1595 return SPEED_1000;
1596 case PHY_M_PS_SPEED_100:
1597 return SPEED_100;
1598 default:
1599 return SPEED_10;
1600 }
1601}
1602
1603static void sky2_link_up(struct sky2_port *sky2)
1604{
1605 struct sky2_hw *hw = sky2->hw;
1606 unsigned port = sky2->port;
1607 u16 reg;
1608
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001609 /* enable Rx/Tx */
Stephen Hemminger2eaba1a2006-09-06 12:44:47 -07001610 reg = gma_read16(hw, port, GM_GP_CTRL);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001611 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1612 gma_write16(hw, port, GM_GP_CTRL, reg);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001613
1614 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1615
1616 netif_carrier_on(sky2->netdev);
1617 netif_wake_queue(sky2->netdev);
1618
1619 /* Turn on link LED */
Stephen Hemminger793b8832005-09-14 16:06:14 -07001620 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001621 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1622
Stephen Hemmingered6d32c2006-05-08 15:11:33 -07001623 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
Stephen Hemminger793b8832005-09-14 16:06:14 -07001624 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
Stephen Hemmingered6d32c2006-05-08 15:11:33 -07001625 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1626
1627 switch(sky2->speed) {
1628 case SPEED_10:
1629 led |= PHY_M_LEDC_INIT_CTRL(7);
1630 break;
1631
1632 case SPEED_100:
1633 led |= PHY_M_LEDC_STA1_CTRL(7);
1634 break;
1635
1636 case SPEED_1000:
1637 led |= PHY_M_LEDC_STA0_CTRL(7);
1638 break;
1639 }
Stephen Hemminger793b8832005-09-14 16:06:14 -07001640
1641 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
Stephen Hemmingered6d32c2006-05-08 15:11:33 -07001642 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001643 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1644 }
1645
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001646 if (netif_msg_link(sky2))
1647 printk(KERN_INFO PFX
shemminger@osdl.orgd571b692005-10-26 12:16:09 -07001648 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001649 sky2->netdev->name, sky2->speed,
1650 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1651 (sky2->tx_pause && sky2->rx_pause) ? "both" :
Stephen Hemminger793b8832005-09-14 16:06:14 -07001652 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001653}
1654
1655static void sky2_link_down(struct sky2_port *sky2)
1656{
1657 struct sky2_hw *hw = sky2->hw;
1658 unsigned port = sky2->port;
1659 u16 reg;
1660
1661 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1662
1663 reg = gma_read16(hw, port, GM_GP_CTRL);
1664 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1665 gma_write16(hw, port, GM_GP_CTRL, reg);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001666
1667 if (sky2->rx_pause && !sky2->tx_pause) {
1668 /* restore Asymmetric Pause bit */
1669 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
Stephen Hemminger793b8832005-09-14 16:06:14 -07001670 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1671 | PHY_M_AN_ASP);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001672 }
1673
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001674 netif_carrier_off(sky2->netdev);
1675 netif_stop_queue(sky2->netdev);
1676
1677 /* Turn on link LED */
1678 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1679
1680 if (netif_msg_link(sky2))
1681 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
Stephen Hemminger2eaba1a2006-09-06 12:44:47 -07001682
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001683 sky2_phy_init(hw, port);
1684}
1685
Stephen Hemminger793b8832005-09-14 16:06:14 -07001686static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1687{
1688 struct sky2_hw *hw = sky2->hw;
1689 unsigned port = sky2->port;
1690 u16 lpa;
1691
1692 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1693
1694 if (lpa & PHY_M_AN_RF) {
1695 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1696 return -1;
1697 }
1698
Stephen Hemminger793b8832005-09-14 16:06:14 -07001699 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1700 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1701 sky2->netdev->name);
1702 return -1;
1703 }
1704
Stephen Hemminger793b8832005-09-14 16:06:14 -07001705 sky2->speed = sky2_phy_speed(hw, aux);
Stephen Hemmingere0ed5452006-09-26 11:57:37 -07001706 if (sky2->speed == SPEED_1000) {
1707 u16 ctl2 = gm_phy_read(hw, port, PHY_MARV_1000T_CTRL);
1708 u16 lpa2 = gm_phy_read(hw, port, PHY_MARV_1000T_STAT);
1709 if (lpa2 & PHY_B_1000S_MSF) {
1710 printk(KERN_ERR PFX "%s: master/slave fault",
1711 sky2->netdev->name);
1712 return -1;
1713 }
1714
1715 if ((ctl2 & PHY_M_1000C_AFD) && (lpa2 & PHY_B_1000S_LP_FD))
1716 sky2->duplex = DUPLEX_FULL;
1717 else
1718 sky2->duplex = DUPLEX_HALF;
1719 } else {
1720 u16 adv = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1721 if ((aux & adv) & PHY_AN_FULL)
1722 sky2->duplex = DUPLEX_FULL;
1723 else
1724 sky2->duplex = DUPLEX_HALF;
1725 }
Stephen Hemminger793b8832005-09-14 16:06:14 -07001726
1727 /* Pause bits are offset (9..8) */
Stephen Hemmingered6d32c2006-05-08 15:11:33 -07001728 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
Stephen Hemminger793b8832005-09-14 16:06:14 -07001729 aux >>= 6;
1730
1731 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1732 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1733
Stephen Hemminger2eaba1a2006-09-06 12:44:47 -07001734 if (sky2->duplex == DUPLEX_HALF && sky2->speed != SPEED_1000
1735 && hw->chip_id != CHIP_ID_YUKON_EC_U)
1736 sky2->rx_pause = sky2->tx_pause = 0;
1737
1738 if (sky2->rx_pause || sky2->tx_pause)
Stephen Hemminger793b8832005-09-14 16:06:14 -07001739 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1740 else
1741 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1742
1743 return 0;
1744}
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001745
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001746/* Interrupt from PHY */
1747static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001748{
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001749 struct net_device *dev = hw->dev[port];
1750 struct sky2_port *sky2 = netdev_priv(dev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001751 u16 istatus, phystat;
1752
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001753 spin_lock(&sky2->phy_lock);
1754 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1755 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1756
1757 if (!netif_running(dev))
1758 goto out;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001759
1760 if (netif_msg_intr(sky2))
1761 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1762 sky2->netdev->name, istatus, phystat);
1763
Stephen Hemminger2eaba1a2006-09-06 12:44:47 -07001764 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
Stephen Hemminger793b8832005-09-14 16:06:14 -07001765 if (sky2_autoneg_done(sky2, phystat) == 0)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001766 sky2_link_up(sky2);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001767 goto out;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001768 }
1769
Stephen Hemminger793b8832005-09-14 16:06:14 -07001770 if (istatus & PHY_M_IS_LSP_CHANGE)
1771 sky2->speed = sky2_phy_speed(hw, phystat);
1772
1773 if (istatus & PHY_M_IS_DUP_CHANGE)
1774 sky2->duplex =
1775 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1776
1777 if (istatus & PHY_M_IS_LST_CHANGE) {
1778 if (phystat & PHY_M_PS_LINK_UP)
1779 sky2_link_up(sky2);
1780 else
1781 sky2_link_down(sky2);
1782 }
1783out:
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001784 spin_unlock(&sky2->phy_lock);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001785}
1786
Stephen Hemminger302d1252006-01-17 13:43:20 -08001787
1788/* Transmit timeout is only called if we are running, carries is up
1789 * and tx queue is full (stopped).
1790 */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001791static void sky2_tx_timeout(struct net_device *dev)
1792{
1793 struct sky2_port *sky2 = netdev_priv(dev);
Stephen Hemminger8cc048e2005-12-09 11:35:07 -08001794 struct sky2_hw *hw = sky2->hw;
1795 unsigned txq = txqaddr[sky2->port];
Stephen Hemminger8f246642006-03-20 15:48:21 -08001796 u16 report, done;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001797
1798 if (netif_msg_timer(sky2))
1799 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1800
Stephen Hemminger8f246642006-03-20 15:48:21 -08001801 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1802 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001803
Stephen Hemminger8f246642006-03-20 15:48:21 -08001804 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1805 dev->name,
1806 sky2->tx_cons, sky2->tx_prod, report, done);
Stephen Hemminger8cc048e2005-12-09 11:35:07 -08001807
Stephen Hemminger8f246642006-03-20 15:48:21 -08001808 if (report != done) {
1809 printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
1810
1811 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1812 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1813 } else if (report != sky2->tx_cons) {
1814 printk(KERN_INFO PFX "status report lost?\n");
1815
Stephen Hemminger2bb8c262006-09-26 11:57:42 -07001816 netif_tx_lock_bh(dev);
Stephen Hemminger8f246642006-03-20 15:48:21 -08001817 sky2_tx_complete(sky2, report);
Stephen Hemminger2bb8c262006-09-26 11:57:42 -07001818 netif_tx_unlock_bh(dev);
Stephen Hemminger8f246642006-03-20 15:48:21 -08001819 } else {
1820 printk(KERN_INFO PFX "hardware hung? flushing\n");
1821
1822 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1823 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1824
Stephen Hemminger2bb8c262006-09-26 11:57:42 -07001825 sky2_tx_clean(dev);
Stephen Hemminger8f246642006-03-20 15:48:21 -08001826
1827 sky2_qset(hw, txq);
1828 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1829 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001830}
1831
1832static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1833{
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001834 struct sky2_port *sky2 = netdev_priv(dev);
1835 struct sky2_hw *hw = sky2->hw;
1836 int err;
1837 u16 ctl, mode;
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001838 u32 imask;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001839
1840 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1841 return -EINVAL;
1842
shemminger@osdl.org5a5b1ea2005-11-30 11:45:15 -08001843 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1844 return -EINVAL;
1845
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001846 if (!netif_running(dev)) {
1847 dev->mtu = new_mtu;
1848 return 0;
1849 }
1850
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001851 imask = sky2_read32(hw, B0_IMSK);
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001852 sky2_write32(hw, B0_IMSK, 0);
1853
shemminger@osdl.org018d1c62005-11-30 11:45:18 -08001854 dev->trans_start = jiffies; /* prevent tx timeout */
1855 netif_stop_queue(dev);
1856 netif_poll_disable(hw->dev[0]);
1857
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001858 synchronize_irq(hw->pdev->irq);
1859
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001860 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1861 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1862 sky2_rx_stop(sky2);
1863 sky2_rx_clean(sky2);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001864
1865 dev->mtu = new_mtu;
Stephen Hemminger14d02632006-09-26 11:57:43 -07001866
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001867 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1868 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001869
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001870 if (dev->mtu > ETH_DATA_LEN)
1871 mode |= GM_SMOD_JUMBO_ENA;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001872
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001873 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1874
1875 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1876
1877 err = sky2_rx_start(sky2);
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001878 sky2_write32(hw, B0_IMSK, imask);
shemminger@osdl.org018d1c62005-11-30 11:45:18 -08001879
Stephen Hemminger1b537562005-12-20 15:08:07 -08001880 if (err)
1881 dev_close(dev);
1882 else {
1883 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1884
1885 netif_poll_enable(hw->dev[0]);
1886 netif_wake_queue(dev);
1887 }
1888
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001889 return err;
1890}
1891
Stephen Hemminger14d02632006-09-26 11:57:43 -07001892/* For small just reuse existing skb for next receive */
1893static struct sk_buff *receive_copy(struct sky2_port *sky2,
1894 const struct rx_ring_info *re,
1895 unsigned length)
1896{
1897 struct sk_buff *skb;
1898
1899 skb = netdev_alloc_skb(sky2->netdev, length + 2);
1900 if (likely(skb)) {
1901 skb_reserve(skb, 2);
1902 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
1903 length, PCI_DMA_FROMDEVICE);
1904 memcpy(skb->data, re->skb->data, length);
1905 skb->ip_summed = re->skb->ip_summed;
1906 skb->csum = re->skb->csum;
1907 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
1908 length, PCI_DMA_FROMDEVICE);
1909 re->skb->ip_summed = CHECKSUM_NONE;
1910 __skb_put(skb, length);
1911 }
1912 return skb;
1913}
1914
1915/* Adjust length of skb with fragments to match received data */
1916static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
1917 unsigned int length)
1918{
1919 int i, num_frags;
1920 unsigned int size;
1921
1922 /* put header into skb */
1923 size = min(length, hdr_space);
1924 skb->tail += size;
1925 skb->len += size;
1926 length -= size;
1927
1928 num_frags = skb_shinfo(skb)->nr_frags;
1929 for (i = 0; i < num_frags; i++) {
1930 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1931
1932 if (length == 0) {
1933 /* don't need this page */
1934 __free_page(frag->page);
1935 --skb_shinfo(skb)->nr_frags;
1936 } else {
1937 size = min(length, (unsigned) PAGE_SIZE);
1938
1939 frag->size = size;
1940 skb->data_len += size;
1941 skb->truesize += size;
1942 skb->len += size;
1943 length -= size;
1944 }
1945 }
1946}
1947
1948/* Normal packet - take skb from ring element and put in a new one */
1949static struct sk_buff *receive_new(struct sky2_port *sky2,
1950 struct rx_ring_info *re,
1951 unsigned int length)
1952{
1953 struct sk_buff *skb, *nskb;
1954 unsigned hdr_space = sky2->rx_data_size;
1955
1956 pr_debug(PFX "receive new length=%d\n", length);
1957
1958 /* Don't be tricky about reusing pages (yet) */
1959 nskb = sky2_rx_alloc(sky2);
1960 if (unlikely(!nskb))
1961 return NULL;
1962
1963 skb = re->skb;
1964 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1965
1966 prefetch(skb->data);
1967 re->skb = nskb;
1968 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
1969
1970 if (skb_shinfo(skb)->nr_frags)
1971 skb_put_frags(skb, hdr_space, length);
1972 else
1973 skb_put(skb, hdr_space);
1974 return skb;
1975}
1976
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001977/*
1978 * Receive one packet.
shemminger@osdl.orgd571b692005-10-26 12:16:09 -07001979 * For larger packets, get new buffer.
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001980 */
shemminger@osdl.org497d7c82006-08-28 10:00:46 -07001981static struct sk_buff *sky2_receive(struct net_device *dev,
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001982 u16 length, u32 status)
1983{
shemminger@osdl.org497d7c82006-08-28 10:00:46 -07001984 struct sky2_port *sky2 = netdev_priv(dev);
Stephen Hemminger291ea612006-09-26 11:57:41 -07001985 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
Stephen Hemminger79e57d32005-09-19 15:42:33 -07001986 struct sk_buff *skb = NULL;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001987
1988 if (unlikely(netif_msg_rx_status(sky2)))
1989 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
shemminger@osdl.org497d7c82006-08-28 10:00:46 -07001990 dev->name, sky2->rx_next, status, length);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001991
Stephen Hemminger793b8832005-09-14 16:06:14 -07001992 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
Stephen Hemmingerd70cd512005-12-09 11:35:09 -08001993 prefetch(sky2->rx_ring + sky2->rx_next);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001994
shemminger@osdl.org42eeea02005-11-30 11:45:13 -08001995 if (status & GMR_FS_ANY_ERR)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001996 goto error;
1997
shemminger@osdl.org42eeea02005-11-30 11:45:13 -08001998 if (!(status & GMR_FS_RX_OK))
1999 goto resubmit;
2000
shemminger@osdl.org497d7c82006-08-28 10:00:46 -07002001 if (length > dev->mtu + ETH_HLEN)
Stephen Hemminger6e15b712005-12-20 15:08:09 -08002002 goto oversize;
2003
Stephen Hemminger14d02632006-09-26 11:57:43 -07002004 if (length < copybreak)
2005 skb = receive_copy(sky2, re, length);
2006 else
2007 skb = receive_new(sky2, re, length);
Stephen Hemminger793b8832005-09-14 16:06:14 -07002008resubmit:
Stephen Hemminger14d02632006-09-26 11:57:43 -07002009 sky2_rx_submit(sky2, re);
Stephen Hemminger79e57d32005-09-19 15:42:33 -07002010
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002011 return skb;
2012
Stephen Hemminger6e15b712005-12-20 15:08:09 -08002013oversize:
2014 ++sky2->net_stats.rx_over_errors;
2015 goto resubmit;
2016
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002017error:
Stephen Hemminger6e15b712005-12-20 15:08:09 -08002018 ++sky2->net_stats.rx_errors;
2019
Stephen Hemminger3be92a72006-01-17 13:43:17 -08002020 if (netif_msg_rx_err(sky2) && net_ratelimit())
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002021 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
shemminger@osdl.org497d7c82006-08-28 10:00:46 -07002022 dev->name, status, length);
Stephen Hemminger793b8832005-09-14 16:06:14 -07002023
2024 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002025 sky2->net_stats.rx_length_errors++;
2026 if (status & GMR_FS_FRAGMENT)
2027 sky2->net_stats.rx_frame_errors++;
2028 if (status & GMR_FS_CRC_ERR)
2029 sky2->net_stats.rx_crc_errors++;
Stephen Hemminger793b8832005-09-14 16:06:14 -07002030 if (status & GMR_FS_RX_FF_OV)
2031 sky2->net_stats.rx_fifo_errors++;
Stephen Hemminger79e57d32005-09-19 15:42:33 -07002032
Stephen Hemminger793b8832005-09-14 16:06:14 -07002033 goto resubmit;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002034}
2035
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002036/* Transmit complete */
2037static inline void sky2_tx_done(struct net_device *dev, u16 last)
Stephen Hemminger13b97b72005-12-09 11:35:03 -08002038{
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002039 struct sky2_port *sky2 = netdev_priv(dev);
Stephen Hemminger302d1252006-01-17 13:43:20 -08002040
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002041 if (netif_running(dev)) {
Stephen Hemminger2bb8c262006-09-26 11:57:42 -07002042 netif_tx_lock(dev);
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002043 sky2_tx_complete(sky2, last);
Stephen Hemminger2bb8c262006-09-26 11:57:42 -07002044 netif_tx_unlock(dev);
shemminger@osdl.org22247952005-11-30 11:45:19 -08002045 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002046}
2047
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002048/* Process status response ring */
2049static int sky2_status_intr(struct sky2_hw *hw, int to_do)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002050{
Stephen Hemminger22e11702006-07-12 15:23:48 -07002051 struct sky2_port *sky2;
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002052 int work_done = 0;
Stephen Hemminger22e11702006-07-12 15:23:48 -07002053 unsigned buf_write[2] = { 0, 0 };
Stephen Hemmingere71ebd72006-05-08 15:11:31 -07002054 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002055
Stephen Hemmingeraf2a58a2005-12-09 11:35:04 -08002056 rmb();
shemminger@osdl.orgbea86102005-10-26 12:16:10 -07002057
Stephen Hemmingere71ebd72006-05-08 15:11:31 -07002058 while (hw->st_idx != hwidx) {
shemminger@osdl.org13210ce2005-11-30 11:45:14 -08002059 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2060 struct net_device *dev;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002061 struct sk_buff *skb;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002062 u32 status;
2063 u16 length;
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002064
Stephen Hemmingercb5d9542006-05-08 15:11:29 -07002065 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
shemminger@osdl.orgbea86102005-10-26 12:16:10 -07002066
Stephen Hemmingere71ebd72006-05-08 15:11:31 -07002067 BUG_ON(le->link >= 2);
2068 dev = hw->dev[le->link];
shemminger@osdl.org13210ce2005-11-30 11:45:14 -08002069
2070 sky2 = netdev_priv(dev);
Stephen Hemmingerf65b1382006-09-06 12:45:02 -07002071 length = le16_to_cpu(le->length);
2072 status = le32_to_cpu(le->status);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002073
Stephen Hemmingere71ebd72006-05-08 15:11:31 -07002074 switch (le->opcode & ~HW_OWNER) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002075 case OP_RXSTAT:
shemminger@osdl.org497d7c82006-08-28 10:00:46 -07002076 skb = sky2_receive(dev, length, status);
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -07002077 if (!skb)
2078 break;
shemminger@osdl.org13210ce2005-11-30 11:45:14 -08002079
shemminger@osdl.org13210ce2005-11-30 11:45:14 -08002080 skb->protocol = eth_type_trans(skb, dev);
2081 dev->last_rx = jiffies;
2082
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -07002083#ifdef SKY2_VLAN_TAG_USED
2084 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2085 vlan_hwaccel_receive_skb(skb,
2086 sky2->vlgrp,
2087 be16_to_cpu(sky2->rx_tag));
2088 } else
2089#endif
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002090 netif_receive_skb(skb);
shemminger@osdl.org13210ce2005-11-30 11:45:14 -08002091
Stephen Hemminger22e11702006-07-12 15:23:48 -07002092 /* Update receiver after 16 frames */
2093 if (++buf_write[le->link] == RX_BUF_WRITE) {
2094 sky2_put_idx(hw, rxqaddr[le->link],
2095 sky2->rx_put);
2096 buf_write[le->link] = 0;
2097 }
2098
2099 /* Stop after net poll weight */
shemminger@osdl.org13210ce2005-11-30 11:45:14 -08002100 if (++work_done >= to_do)
2101 goto exit_loop;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002102 break;
2103
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -07002104#ifdef SKY2_VLAN_TAG_USED
2105 case OP_RXVLAN:
2106 sky2->rx_tag = length;
2107 break;
2108
2109 case OP_RXCHKSVLAN:
2110 sky2->rx_tag = length;
2111 /* fall through */
2112#endif
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002113 case OP_RXCHKS:
shemminger@osdl.orgd11c13e2005-09-27 15:02:56 -07002114 skb = sky2->rx_ring[sky2->rx_next].skb;
Patrick McHardy84fa7932006-08-29 16:44:56 -07002115 skb->ip_summed = CHECKSUM_COMPLETE;
Stephen Hemmingerf65b1382006-09-06 12:45:02 -07002116 skb->csum = status & 0xffff;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002117 break;
2118
2119 case OP_TXINDEXLE:
Stephen Hemminger13b97b72005-12-09 11:35:03 -08002120 /* TX index reports status for both ports */
Stephen Hemmingerf55925d2006-05-08 15:11:28 -07002121 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2122 sky2_tx_done(hw->dev[0], status & 0xfff);
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002123 if (hw->dev[1])
2124 sky2_tx_done(hw->dev[1],
2125 ((status >> 24) & 0xff)
2126 | (u16)(length & 0xf) << 8);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002127 break;
2128
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002129 default:
2130 if (net_ratelimit())
Stephen Hemminger793b8832005-09-14 16:06:14 -07002131 printk(KERN_WARNING PFX
Stephen Hemmingere71ebd72006-05-08 15:11:31 -07002132 "unknown status opcode 0x%x\n", le->opcode);
2133 goto exit_loop;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002134 }
shemminger@osdl.org13210ce2005-11-30 11:45:14 -08002135 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002136
Stephen Hemmingerfe2a24d2006-08-01 11:55:23 -07002137 /* Fully processed status ring so clear irq */
2138 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2139
shemminger@osdl.org13210ce2005-11-30 11:45:14 -08002140exit_loop:
Stephen Hemminger22e11702006-07-12 15:23:48 -07002141 if (buf_write[0]) {
2142 sky2 = netdev_priv(hw->dev[0]);
2143 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2144 }
2145
2146 if (buf_write[1]) {
2147 sky2 = netdev_priv(hw->dev[1]);
2148 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2149 }
2150
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002151 return work_done;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002152}
2153
2154static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2155{
2156 struct net_device *dev = hw->dev[port];
2157
Stephen Hemminger3be92a72006-01-17 13:43:17 -08002158 if (net_ratelimit())
2159 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2160 dev->name, status);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002161
2162 if (status & Y2_IS_PAR_RD1) {
Stephen Hemminger3be92a72006-01-17 13:43:17 -08002163 if (net_ratelimit())
2164 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2165 dev->name);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002166 /* Clear IRQ */
2167 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2168 }
2169
2170 if (status & Y2_IS_PAR_WR1) {
Stephen Hemminger3be92a72006-01-17 13:43:17 -08002171 if (net_ratelimit())
2172 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2173 dev->name);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002174
2175 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2176 }
2177
2178 if (status & Y2_IS_PAR_MAC1) {
Stephen Hemminger3be92a72006-01-17 13:43:17 -08002179 if (net_ratelimit())
2180 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002181 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2182 }
2183
2184 if (status & Y2_IS_PAR_RX1) {
Stephen Hemminger3be92a72006-01-17 13:43:17 -08002185 if (net_ratelimit())
2186 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002187 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2188 }
2189
2190 if (status & Y2_IS_TCP_TXA1) {
Stephen Hemminger3be92a72006-01-17 13:43:17 -08002191 if (net_ratelimit())
2192 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2193 dev->name);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002194 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2195 }
2196}
2197
2198static void sky2_hw_intr(struct sky2_hw *hw)
2199{
2200 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2201
Stephen Hemminger793b8832005-09-14 16:06:14 -07002202 if (status & Y2_IS_TIST_OV)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002203 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002204
2205 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
Stephen Hemminger793b8832005-09-14 16:06:14 -07002206 u16 pci_err;
2207
Stephen Hemminger56a645c2006-02-22 11:45:02 -08002208 pci_err = sky2_pci_read16(hw, PCI_STATUS);
Stephen Hemminger3be92a72006-01-17 13:43:17 -08002209 if (net_ratelimit())
2210 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2211 pci_name(hw->pdev), pci_err);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002212
2213 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
Stephen Hemminger56a645c2006-02-22 11:45:02 -08002214 sky2_pci_write16(hw, PCI_STATUS,
Stephen Hemminger91aeb3e2006-09-26 11:57:38 -07002215 pci_err | PCI_STATUS_ERROR_BITS);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002216 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2217 }
2218
2219 if (status & Y2_IS_PCI_EXP) {
shemminger@osdl.orgd571b692005-10-26 12:16:09 -07002220 /* PCI-Express uncorrectable Error occurred */
Stephen Hemminger793b8832005-09-14 16:06:14 -07002221 u32 pex_err;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002222
Stephen Hemminger91aeb3e2006-09-26 11:57:38 -07002223 pex_err = sky2_pci_read32(hw,
2224 hw->err_cap + PCI_ERR_UNCOR_STATUS);
Stephen Hemminger793b8832005-09-14 16:06:14 -07002225
Stephen Hemminger3be92a72006-01-17 13:43:17 -08002226 if (net_ratelimit())
2227 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2228 pci_name(hw->pdev), pex_err);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002229
2230 /* clear the interrupt */
2231 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
Stephen Hemminger91aeb3e2006-09-26 11:57:38 -07002232 sky2_pci_write32(hw,
2233 hw->err_cap + PCI_ERR_UNCOR_STATUS,
2234 0xffffffffUL);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002235 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2236
Stephen Hemminger91aeb3e2006-09-26 11:57:38 -07002237
2238 /* In case of fatal error mask off to keep from getting stuck */
2239 if (pex_err & (PCI_ERR_UNC_POISON_TLP | PCI_ERR_UNC_FCP
2240 | PCI_ERR_UNC_DLP)) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002241 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2242 hwmsk &= ~Y2_IS_PCI_EXP;
2243 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2244 }
Stephen Hemminger91aeb3e2006-09-26 11:57:38 -07002245
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002246 }
2247
2248 if (status & Y2_HWE_L1_MASK)
2249 sky2_hw_error(hw, 0, status);
2250 status >>= 8;
2251 if (status & Y2_HWE_L1_MASK)
2252 sky2_hw_error(hw, 1, status);
2253}
2254
2255static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2256{
2257 struct net_device *dev = hw->dev[port];
2258 struct sky2_port *sky2 = netdev_priv(dev);
2259 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2260
2261 if (netif_msg_intr(sky2))
2262 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2263 dev->name, status);
2264
2265 if (status & GM_IS_RX_FF_OR) {
2266 ++sky2->net_stats.rx_fifo_errors;
2267 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2268 }
2269
2270 if (status & GM_IS_TX_FF_UR) {
2271 ++sky2->net_stats.tx_fifo_errors;
2272 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2273 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002274}
2275
Stephen Hemmingerd2579242006-03-20 15:48:22 -08002276/* This should never happen it is a fatal situation */
2277static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2278 const char *rxtx, u32 mask)
2279{
2280 struct net_device *dev = hw->dev[port];
2281 struct sky2_port *sky2 = netdev_priv(dev);
2282 u32 imask;
2283
2284 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2285 dev ? dev->name : "<not registered>", rxtx);
2286
2287 imask = sky2_read32(hw, B0_IMSK);
2288 imask &= ~mask;
2289 sky2_write32(hw, B0_IMSK, imask);
2290
2291 if (dev) {
2292 spin_lock(&sky2->phy_lock);
2293 sky2_link_down(sky2);
2294 spin_unlock(&sky2->phy_lock);
2295 }
2296}
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002297
Stephen Hemmingerd27ed382006-04-25 10:58:51 -07002298/* If idle then force a fake soft NAPI poll once a second
2299 * to work around cases where sharing an edge triggered interrupt.
2300 */
Stephen Hemmingereb35cf62006-06-13 17:17:31 +09002301static inline void sky2_idle_start(struct sky2_hw *hw)
2302{
2303 if (idle_timeout > 0)
2304 mod_timer(&hw->idle_timer,
2305 jiffies + msecs_to_jiffies(idle_timeout));
2306}
2307
Stephen Hemmingerd27ed382006-04-25 10:58:51 -07002308static void sky2_idle(unsigned long arg)
2309{
Stephen Hemminger01bd7562006-05-08 15:11:30 -07002310 struct sky2_hw *hw = (struct sky2_hw *) arg;
2311 struct net_device *dev = hw->dev[0];
Stephen Hemmingerd27ed382006-04-25 10:58:51 -07002312
Stephen Hemmingerd27ed382006-04-25 10:58:51 -07002313 if (__netif_rx_schedule_prep(dev))
2314 __netif_rx_schedule(dev);
Stephen Hemminger01bd7562006-05-08 15:11:30 -07002315
2316 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
Stephen Hemmingerd27ed382006-04-25 10:58:51 -07002317}
2318
2319
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002320static int sky2_poll(struct net_device *dev0, int *budget)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002321{
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002322 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2323 int work_limit = min(dev0->quota, *budget);
2324 int work_done = 0;
Stephen Hemmingerfb2690a2006-03-20 15:48:19 -08002325 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002326
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002327 if (status & Y2_IS_HW_ERR)
2328 sky2_hw_intr(hw);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002329
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002330 if (status & Y2_IS_IRQ_PHY1)
2331 sky2_phy_intr(hw, 0);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002332
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002333 if (status & Y2_IS_IRQ_PHY2)
2334 sky2_phy_intr(hw, 1);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002335
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002336 if (status & Y2_IS_IRQ_MAC1)
2337 sky2_mac_intr(hw, 0);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002338
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002339 if (status & Y2_IS_IRQ_MAC2)
2340 sky2_mac_intr(hw, 1);
Stephen Hemmingerd2579242006-03-20 15:48:22 -08002341
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002342 if (status & Y2_IS_CHK_RX1)
2343 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
Stephen Hemmingerd2579242006-03-20 15:48:22 -08002344
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002345 if (status & Y2_IS_CHK_RX2)
2346 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
Stephen Hemmingerd2579242006-03-20 15:48:22 -08002347
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002348 if (status & Y2_IS_CHK_TXA1)
2349 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
Stephen Hemmingerd2579242006-03-20 15:48:22 -08002350
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002351 if (status & Y2_IS_CHK_TXA2)
2352 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002353
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002354 work_done = sky2_status_intr(hw, work_limit);
Stephen Hemmingerfe2a24d2006-08-01 11:55:23 -07002355 if (work_done < work_limit) {
2356 netif_rx_complete(dev0);
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002357
Stephen Hemmingerfe2a24d2006-08-01 11:55:23 -07002358 sky2_read32(hw, B0_Y2_SP_LISR);
2359 return 0;
2360 } else {
2361 *budget -= work_done;
2362 dev0->quota -= work_done;
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002363 return 1;
Stephen Hemmingerfe2a24d2006-08-01 11:55:23 -07002364 }
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002365}
2366
2367static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2368{
2369 struct sky2_hw *hw = dev_id;
2370 struct net_device *dev0 = hw->dev[0];
2371 u32 status;
2372
2373 /* Reading this mask interrupts as side effect */
2374 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2375 if (status == 0 || status == ~0)
2376 return IRQ_NONE;
2377
2378 prefetch(&hw->st_le[hw->st_idx]);
2379 if (likely(__netif_rx_schedule_prep(dev0)))
2380 __netif_rx_schedule(dev0);
Stephen Hemminger793b8832005-09-14 16:06:14 -07002381
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002382 return IRQ_HANDLED;
2383}
2384
2385#ifdef CONFIG_NET_POLL_CONTROLLER
2386static void sky2_netpoll(struct net_device *dev)
2387{
2388 struct sky2_port *sky2 = netdev_priv(dev);
Stephen Hemminger88d11362006-06-16 12:10:46 -07002389 struct net_device *dev0 = sky2->hw->dev[0];
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002390
Stephen Hemminger88d11362006-06-16 12:10:46 -07002391 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2392 __netif_rx_schedule(dev0);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002393}
2394#endif
2395
2396/* Chip internal frequency for clock calculations */
Stephen Hemmingerfb173582005-12-09 11:34:56 -08002397static inline u32 sky2_mhz(const struct sky2_hw *hw)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002398{
Stephen Hemminger793b8832005-09-14 16:06:14 -07002399 switch (hw->chip_id) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002400 case CHIP_ID_YUKON_EC:
shemminger@osdl.org5a5b1ea2005-11-30 11:45:15 -08002401 case CHIP_ID_YUKON_EC_U:
Stephen Hemmingerfb173582005-12-09 11:34:56 -08002402 return 125; /* 125 Mhz */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002403 case CHIP_ID_YUKON_FE:
Stephen Hemmingerfb173582005-12-09 11:34:56 -08002404 return 100; /* 100 Mhz */
Stephen Hemminger793b8832005-09-14 16:06:14 -07002405 default: /* YUKON_XL */
Stephen Hemmingerfb173582005-12-09 11:34:56 -08002406 return 156; /* 156 Mhz */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002407 }
2408}
2409
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002410static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2411{
Stephen Hemmingerfb173582005-12-09 11:34:56 -08002412 return sky2_mhz(hw) * us;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002413}
2414
Stephen Hemmingerfb173582005-12-09 11:34:56 -08002415static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2416{
2417 return clk / sky2_mhz(hw);
2418}
2419
2420
Stephen Hemminger59139522006-07-12 15:23:45 -07002421static int sky2_reset(struct sky2_hw *hw)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002422{
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002423 u16 status;
Stephen Hemmingerb89165f2006-09-06 12:44:53 -07002424 u8 t8;
Stephen Hemminger56a645c2006-02-22 11:45:02 -08002425 int i;
Stephen Hemminger91aeb3e2006-09-26 11:57:38 -07002426 u32 msk;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002427
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002428 sky2_write8(hw, B0_CTST, CS_RST_CLR);
Stephen Hemminger08c06d82006-01-30 11:37:54 -08002429
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002430 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2431 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2432 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2433 pci_name(hw->pdev), hw->chip_id);
2434 return -EOPNOTSUPP;
2435 }
2436
Stephen Hemminger290d4de2006-03-20 15:48:15 -08002437 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2438
2439 /* This rev is really old, and requires untested workarounds */
2440 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2441 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2442 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2443 hw->chip_id, hw->chip_rev);
2444 return -EOPNOTSUPP;
2445 }
2446
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002447 /* disable ASF */
2448 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2449 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2450 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2451 }
2452
2453 /* do a SW reset */
2454 sky2_write8(hw, B0_CTST, CS_RST_SET);
2455 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2456
2457 /* clear PCI errors, if any */
Stephen Hemminger56a645c2006-02-22 11:45:02 -08002458 status = sky2_pci_read16(hw, PCI_STATUS);
Stephen Hemminger2d42d212006-01-30 11:37:55 -08002459
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002460 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
Stephen Hemminger56a645c2006-02-22 11:45:02 -08002461 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2462
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002463
2464 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2465
2466 /* clear any PEX errors */
Stephen Hemminger91aeb3e2006-09-26 11:57:38 -07002467 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP)) {
2468 hw->err_cap = pci_find_ext_capability(hw->pdev, PCI_EXT_CAP_ID_ERR);
2469 if (hw->err_cap)
2470 sky2_pci_write32(hw,
2471 hw->err_cap + PCI_ERR_UNCOR_STATUS,
2472 0xffffffffUL);
2473 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002474
Stephen Hemmingerb89165f2006-09-06 12:44:53 -07002475 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002476 hw->ports = 1;
2477 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2478 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2479 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2480 ++hw->ports;
2481 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002482
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -07002483 sky2_set_power_state(hw, PCI_D0);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002484
2485 for (i = 0; i < hw->ports; i++) {
2486 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2487 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2488 }
2489
2490 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2491
Stephen Hemminger793b8832005-09-14 16:06:14 -07002492 /* Clear I2C IRQ noise */
2493 sky2_write32(hw, B2_I2C_IRQ, 1);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002494
2495 /* turn off hardware timer (unused) */
2496 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2497 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
Stephen Hemminger793b8832005-09-14 16:06:14 -07002498
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002499 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2500
Stephen Hemminger69634ee2005-12-09 11:35:06 -08002501 /* Turn off descriptor polling */
2502 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002503
2504 /* Turn off receive timestamp */
2505 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
Stephen Hemminger793b8832005-09-14 16:06:14 -07002506 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002507
2508 /* enable the Tx Arbiters */
2509 for (i = 0; i < hw->ports; i++)
2510 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2511
2512 /* Initialize ram interface */
2513 for (i = 0; i < hw->ports; i++) {
Stephen Hemminger793b8832005-09-14 16:06:14 -07002514 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002515
2516 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2517 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2518 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2519 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2520 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2521 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2522 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2523 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2524 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2525 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2526 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2527 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2528 }
2529
Stephen Hemminger91aeb3e2006-09-26 11:57:38 -07002530 msk = Y2_HWE_ALL_MASK;
2531 if (!hw->err_cap)
2532 msk &= ~Y2_IS_PCI_EXP;
2533 sky2_write32(hw, B0_HWE_IMSK, msk);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002534
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002535 for (i = 0; i < hw->ports; i++)
shemminger@osdl.orgd3bcfbe2006-08-28 10:00:51 -07002536 sky2_gmac_reset(hw, i);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002537
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002538 memset(hw->st_le, 0, STATUS_LE_BYTES);
2539 hw->st_idx = 0;
2540
2541 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2542 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2543
2544 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
Stephen Hemminger793b8832005-09-14 16:06:14 -07002545 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002546
2547 /* Set the list last index */
Stephen Hemminger793b8832005-09-14 16:06:14 -07002548 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002549
Stephen Hemminger290d4de2006-03-20 15:48:15 -08002550 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2551 sky2_write8(hw, STAT_FIFO_WM, 16);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002552
Stephen Hemminger290d4de2006-03-20 15:48:15 -08002553 /* set Status-FIFO ISR watermark */
2554 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2555 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2556 else
2557 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002558
Stephen Hemminger290d4de2006-03-20 15:48:15 -08002559 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
Stephen Hemminger77b3d6a2006-03-20 15:48:18 -08002560 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2561 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002562
Stephen Hemminger793b8832005-09-14 16:06:14 -07002563 /* enable status unit */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002564 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2565
2566 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2567 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2568 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2569
2570 return 0;
2571}
2572
Stephen Hemminger28bd1812006-01-17 13:43:19 -08002573static u32 sky2_supported_modes(const struct sky2_hw *hw)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002574{
Stephen Hemmingerb89165f2006-09-06 12:44:53 -07002575 if (sky2_is_copper(hw)) {
2576 u32 modes = SUPPORTED_10baseT_Half
2577 | SUPPORTED_10baseT_Full
2578 | SUPPORTED_100baseT_Half
2579 | SUPPORTED_100baseT_Full
2580 | SUPPORTED_Autoneg | SUPPORTED_TP;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002581
2582 if (hw->chip_id != CHIP_ID_YUKON_FE)
2583 modes |= SUPPORTED_1000baseT_Half
Stephen Hemmingerb89165f2006-09-06 12:44:53 -07002584 | SUPPORTED_1000baseT_Full;
2585 return modes;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002586 } else
Stephen Hemmingerb89165f2006-09-06 12:44:53 -07002587 return SUPPORTED_1000baseT_Half
2588 | SUPPORTED_1000baseT_Full
2589 | SUPPORTED_Autoneg
2590 | SUPPORTED_FIBRE;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002591}
2592
Stephen Hemminger793b8832005-09-14 16:06:14 -07002593static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002594{
2595 struct sky2_port *sky2 = netdev_priv(dev);
2596 struct sky2_hw *hw = sky2->hw;
2597
2598 ecmd->transceiver = XCVR_INTERNAL;
2599 ecmd->supported = sky2_supported_modes(hw);
2600 ecmd->phy_address = PHY_ADDR_MARV;
Stephen Hemmingerb89165f2006-09-06 12:44:53 -07002601 if (sky2_is_copper(hw)) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002602 ecmd->supported = SUPPORTED_10baseT_Half
Stephen Hemminger793b8832005-09-14 16:06:14 -07002603 | SUPPORTED_10baseT_Full
2604 | SUPPORTED_100baseT_Half
2605 | SUPPORTED_100baseT_Full
2606 | SUPPORTED_1000baseT_Half
2607 | SUPPORTED_1000baseT_Full
2608 | SUPPORTED_Autoneg | SUPPORTED_TP;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002609 ecmd->port = PORT_TP;
Stephen Hemmingerb89165f2006-09-06 12:44:53 -07002610 ecmd->speed = sky2->speed;
2611 } else {
2612 ecmd->speed = SPEED_1000;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002613 ecmd->port = PORT_FIBRE;
Stephen Hemmingerb89165f2006-09-06 12:44:53 -07002614 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002615
2616 ecmd->advertising = sky2->advertising;
2617 ecmd->autoneg = sky2->autoneg;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002618 ecmd->duplex = sky2->duplex;
2619 return 0;
2620}
2621
2622static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2623{
2624 struct sky2_port *sky2 = netdev_priv(dev);
2625 const struct sky2_hw *hw = sky2->hw;
2626 u32 supported = sky2_supported_modes(hw);
2627
2628 if (ecmd->autoneg == AUTONEG_ENABLE) {
2629 ecmd->advertising = supported;
2630 sky2->duplex = -1;
2631 sky2->speed = -1;
2632 } else {
2633 u32 setting;
2634
Stephen Hemminger793b8832005-09-14 16:06:14 -07002635 switch (ecmd->speed) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002636 case SPEED_1000:
2637 if (ecmd->duplex == DUPLEX_FULL)
2638 setting = SUPPORTED_1000baseT_Full;
2639 else if (ecmd->duplex == DUPLEX_HALF)
2640 setting = SUPPORTED_1000baseT_Half;
2641 else
2642 return -EINVAL;
2643 break;
2644 case SPEED_100:
2645 if (ecmd->duplex == DUPLEX_FULL)
2646 setting = SUPPORTED_100baseT_Full;
2647 else if (ecmd->duplex == DUPLEX_HALF)
2648 setting = SUPPORTED_100baseT_Half;
2649 else
2650 return -EINVAL;
2651 break;
2652
2653 case SPEED_10:
2654 if (ecmd->duplex == DUPLEX_FULL)
2655 setting = SUPPORTED_10baseT_Full;
2656 else if (ecmd->duplex == DUPLEX_HALF)
2657 setting = SUPPORTED_10baseT_Half;
2658 else
2659 return -EINVAL;
2660 break;
2661 default:
2662 return -EINVAL;
2663 }
2664
2665 if ((setting & supported) == 0)
2666 return -EINVAL;
2667
2668 sky2->speed = ecmd->speed;
2669 sky2->duplex = ecmd->duplex;
2670 }
2671
2672 sky2->autoneg = ecmd->autoneg;
2673 sky2->advertising = ecmd->advertising;
2674
Stephen Hemminger1b537562005-12-20 15:08:07 -08002675 if (netif_running(dev))
2676 sky2_phy_reinit(sky2);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002677
2678 return 0;
2679}
2680
2681static void sky2_get_drvinfo(struct net_device *dev,
2682 struct ethtool_drvinfo *info)
2683{
2684 struct sky2_port *sky2 = netdev_priv(dev);
2685
2686 strcpy(info->driver, DRV_NAME);
2687 strcpy(info->version, DRV_VERSION);
2688 strcpy(info->fw_version, "N/A");
2689 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2690}
2691
2692static const struct sky2_stat {
Stephen Hemminger793b8832005-09-14 16:06:14 -07002693 char name[ETH_GSTRING_LEN];
2694 u16 offset;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002695} sky2_stats[] = {
2696 { "tx_bytes", GM_TXO_OK_HI },
2697 { "rx_bytes", GM_RXO_OK_HI },
2698 { "tx_broadcast", GM_TXF_BC_OK },
2699 { "rx_broadcast", GM_RXF_BC_OK },
2700 { "tx_multicast", GM_TXF_MC_OK },
2701 { "rx_multicast", GM_RXF_MC_OK },
2702 { "tx_unicast", GM_TXF_UC_OK },
2703 { "rx_unicast", GM_RXF_UC_OK },
2704 { "tx_mac_pause", GM_TXF_MPAUSE },
2705 { "rx_mac_pause", GM_RXF_MPAUSE },
Stephen Hemmingereadfa7dd2006-03-22 10:38:45 -08002706 { "collisions", GM_TXF_COL },
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002707 { "late_collision",GM_TXF_LAT_COL },
2708 { "aborted", GM_TXF_ABO_COL },
Stephen Hemmingereadfa7dd2006-03-22 10:38:45 -08002709 { "single_collisions", GM_TXF_SNG_COL },
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002710 { "multi_collisions", GM_TXF_MUL_COL },
Stephen Hemmingereadfa7dd2006-03-22 10:38:45 -08002711
Stephen Hemmingerd2604542006-03-23 08:51:36 -08002712 { "rx_short", GM_RXF_SHT },
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002713 { "rx_runt", GM_RXE_FRAG },
Stephen Hemmingereadfa7dd2006-03-22 10:38:45 -08002714 { "rx_64_byte_packets", GM_RXF_64B },
2715 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2716 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2717 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2718 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2719 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2720 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002721 { "rx_too_long", GM_RXF_LNG_ERR },
Stephen Hemmingereadfa7dd2006-03-22 10:38:45 -08002722 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2723 { "rx_jabber", GM_RXF_JAB_PKT },
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002724 { "rx_fcs_error", GM_RXF_FCS_ERR },
Stephen Hemmingereadfa7dd2006-03-22 10:38:45 -08002725
2726 { "tx_64_byte_packets", GM_TXF_64B },
2727 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2728 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2729 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2730 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2731 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2732 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2733 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002734};
2735
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002736static u32 sky2_get_rx_csum(struct net_device *dev)
2737{
2738 struct sky2_port *sky2 = netdev_priv(dev);
2739
2740 return sky2->rx_csum;
2741}
2742
2743static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2744{
2745 struct sky2_port *sky2 = netdev_priv(dev);
2746
2747 sky2->rx_csum = data;
Stephen Hemminger793b8832005-09-14 16:06:14 -07002748
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002749 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2750 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2751
2752 return 0;
2753}
2754
2755static u32 sky2_get_msglevel(struct net_device *netdev)
2756{
2757 struct sky2_port *sky2 = netdev_priv(netdev);
2758 return sky2->msg_enable;
2759}
2760
Stephen Hemminger9a7ae0a2005-09-27 15:28:42 -07002761static int sky2_nway_reset(struct net_device *dev)
2762{
2763 struct sky2_port *sky2 = netdev_priv(dev);
Stephen Hemminger9a7ae0a2005-09-27 15:28:42 -07002764
2765 if (sky2->autoneg != AUTONEG_ENABLE)
2766 return -EINVAL;
2767
Stephen Hemminger1b537562005-12-20 15:08:07 -08002768 sky2_phy_reinit(sky2);
Stephen Hemminger9a7ae0a2005-09-27 15:28:42 -07002769
2770 return 0;
2771}
2772
Stephen Hemminger793b8832005-09-14 16:06:14 -07002773static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002774{
2775 struct sky2_hw *hw = sky2->hw;
2776 unsigned port = sky2->port;
2777 int i;
2778
2779 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
Stephen Hemminger793b8832005-09-14 16:06:14 -07002780 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002781 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
Stephen Hemminger793b8832005-09-14 16:06:14 -07002782 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002783
Stephen Hemminger793b8832005-09-14 16:06:14 -07002784 for (i = 2; i < count; i++)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002785 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2786}
2787
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002788static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2789{
2790 struct sky2_port *sky2 = netdev_priv(netdev);
2791 sky2->msg_enable = value;
2792}
2793
2794static int sky2_get_stats_count(struct net_device *dev)
2795{
2796 return ARRAY_SIZE(sky2_stats);
2797}
2798
2799static void sky2_get_ethtool_stats(struct net_device *dev,
Stephen Hemminger793b8832005-09-14 16:06:14 -07002800 struct ethtool_stats *stats, u64 * data)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002801{
2802 struct sky2_port *sky2 = netdev_priv(dev);
2803
Stephen Hemminger793b8832005-09-14 16:06:14 -07002804 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002805}
2806
Stephen Hemminger793b8832005-09-14 16:06:14 -07002807static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002808{
2809 int i;
2810
2811 switch (stringset) {
2812 case ETH_SS_STATS:
2813 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2814 memcpy(data + i * ETH_GSTRING_LEN,
2815 sky2_stats[i].name, ETH_GSTRING_LEN);
2816 break;
2817 }
2818}
2819
2820/* Use hardware MIB variables for critical path statistics and
2821 * transmit feedback not reported at interrupt.
2822 * Other errors are accounted for in interrupt handler.
2823 */
2824static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2825{
2826 struct sky2_port *sky2 = netdev_priv(dev);
Stephen Hemminger793b8832005-09-14 16:06:14 -07002827 u64 data[13];
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002828
Stephen Hemminger793b8832005-09-14 16:06:14 -07002829 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002830
2831 sky2->net_stats.tx_bytes = data[0];
2832 sky2->net_stats.rx_bytes = data[1];
2833 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2834 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
Stephen Hemminger050ff182006-03-23 08:51:37 -08002835 sky2->net_stats.multicast = data[3] + data[5];
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002836 sky2->net_stats.collisions = data[10];
2837 sky2->net_stats.tx_aborted_errors = data[12];
2838
2839 return &sky2->net_stats;
2840}
2841
2842static int sky2_set_mac_address(struct net_device *dev, void *p)
2843{
2844 struct sky2_port *sky2 = netdev_priv(dev);
Stephen Hemmingera8ab1ec2006-01-30 11:37:57 -08002845 struct sky2_hw *hw = sky2->hw;
2846 unsigned port = sky2->port;
2847 const struct sockaddr *addr = p;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002848
2849 if (!is_valid_ether_addr(addr->sa_data))
2850 return -EADDRNOTAVAIL;
2851
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002852 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
Stephen Hemmingera8ab1ec2006-01-30 11:37:57 -08002853 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002854 dev->dev_addr, ETH_ALEN);
Stephen Hemmingera8ab1ec2006-01-30 11:37:57 -08002855 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002856 dev->dev_addr, ETH_ALEN);
Stephen Hemminger1b537562005-12-20 15:08:07 -08002857
Stephen Hemmingera8ab1ec2006-01-30 11:37:57 -08002858 /* virtual address for data */
2859 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2860
2861 /* physical address: used for pause frames */
2862 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
Stephen Hemminger1b537562005-12-20 15:08:07 -08002863
2864 return 0;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002865}
2866
2867static void sky2_set_multicast(struct net_device *dev)
2868{
2869 struct sky2_port *sky2 = netdev_priv(dev);
2870 struct sky2_hw *hw = sky2->hw;
2871 unsigned port = sky2->port;
2872 struct dev_mc_list *list = dev->mc_list;
2873 u16 reg;
2874 u8 filter[8];
2875
2876 memset(filter, 0, sizeof(filter));
2877
2878 reg = gma_read16(hw, port, GM_RX_CTRL);
2879 reg |= GM_RXCR_UCF_ENA;
2880
shemminger@osdl.orgd571b692005-10-26 12:16:09 -07002881 if (dev->flags & IFF_PROMISC) /* promiscuous */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002882 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
Stephen Hemminger793b8832005-09-14 16:06:14 -07002883 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002884 memset(filter, 0xff, sizeof(filter));
Stephen Hemminger793b8832005-09-14 16:06:14 -07002885 else if (dev->mc_count == 0) /* no multicast */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002886 reg &= ~GM_RXCR_MCF_ENA;
2887 else {
2888 int i;
2889 reg |= GM_RXCR_MCF_ENA;
2890
2891 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2892 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
Stephen Hemminger793b8832005-09-14 16:06:14 -07002893 filter[bit / 8] |= 1 << (bit % 8);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002894 }
2895 }
2896
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002897 gma_write16(hw, port, GM_MC_ADDR_H1,
Stephen Hemminger793b8832005-09-14 16:06:14 -07002898 (u16) filter[0] | ((u16) filter[1] << 8));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002899 gma_write16(hw, port, GM_MC_ADDR_H2,
Stephen Hemminger793b8832005-09-14 16:06:14 -07002900 (u16) filter[2] | ((u16) filter[3] << 8));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002901 gma_write16(hw, port, GM_MC_ADDR_H3,
Stephen Hemminger793b8832005-09-14 16:06:14 -07002902 (u16) filter[4] | ((u16) filter[5] << 8));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002903 gma_write16(hw, port, GM_MC_ADDR_H4,
Stephen Hemminger793b8832005-09-14 16:06:14 -07002904 (u16) filter[6] | ((u16) filter[7] << 8));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002905
2906 gma_write16(hw, port, GM_RX_CTRL, reg);
2907}
2908
2909/* Can have one global because blinking is controlled by
2910 * ethtool and that is always under RTNL mutex
2911 */
Stephen Hemminger91c86df2005-12-09 11:34:57 -08002912static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002913{
Stephen Hemminger793b8832005-09-14 16:06:14 -07002914 u16 pg;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002915
Stephen Hemminger793b8832005-09-14 16:06:14 -07002916 switch (hw->chip_id) {
2917 case CHIP_ID_YUKON_XL:
2918 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2919 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2920 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2921 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2922 PHY_M_LEDC_INIT_CTRL(7) |
2923 PHY_M_LEDC_STA1_CTRL(7) |
2924 PHY_M_LEDC_STA0_CTRL(7))
2925 : 0);
2926
2927 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2928 break;
2929
2930 default:
2931 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2932 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2933 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2934 PHY_M_LED_MO_10(MO_LED_ON) |
2935 PHY_M_LED_MO_100(MO_LED_ON) |
2936 PHY_M_LED_MO_1000(MO_LED_ON) |
2937 PHY_M_LED_MO_RX(MO_LED_ON)
2938 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2939 PHY_M_LED_MO_10(MO_LED_OFF) |
2940 PHY_M_LED_MO_100(MO_LED_OFF) |
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002941 PHY_M_LED_MO_1000(MO_LED_OFF) |
2942 PHY_M_LED_MO_RX(MO_LED_OFF));
2943
Stephen Hemminger793b8832005-09-14 16:06:14 -07002944 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002945}
2946
2947/* blink LED's for finding board */
2948static int sky2_phys_id(struct net_device *dev, u32 data)
2949{
2950 struct sky2_port *sky2 = netdev_priv(dev);
2951 struct sky2_hw *hw = sky2->hw;
2952 unsigned port = sky2->port;
Stephen Hemminger793b8832005-09-14 16:06:14 -07002953 u16 ledctrl, ledover = 0;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002954 long ms;
Stephen Hemminger91c86df2005-12-09 11:34:57 -08002955 int interrupted;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002956 int onoff = 1;
2957
Stephen Hemminger793b8832005-09-14 16:06:14 -07002958 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002959 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2960 else
2961 ms = data * 1000;
2962
2963 /* save initial values */
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002964 spin_lock_bh(&sky2->phy_lock);
Stephen Hemminger793b8832005-09-14 16:06:14 -07002965 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2966 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2967 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2968 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2969 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2970 } else {
2971 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2972 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2973 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002974
Stephen Hemminger91c86df2005-12-09 11:34:57 -08002975 interrupted = 0;
2976 while (!interrupted && ms > 0) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002977 sky2_led(hw, port, onoff);
2978 onoff = !onoff;
2979
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002980 spin_unlock_bh(&sky2->phy_lock);
Stephen Hemminger91c86df2005-12-09 11:34:57 -08002981 interrupted = msleep_interruptible(250);
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002982 spin_lock_bh(&sky2->phy_lock);
Stephen Hemminger91c86df2005-12-09 11:34:57 -08002983
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002984 ms -= 250;
2985 }
2986
2987 /* resume regularly scheduled programming */
Stephen Hemminger793b8832005-09-14 16:06:14 -07002988 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2989 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2990 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2991 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2992 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2993 } else {
2994 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2995 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2996 }
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002997 spin_unlock_bh(&sky2->phy_lock);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002998
2999 return 0;
3000}
3001
3002static void sky2_get_pauseparam(struct net_device *dev,
3003 struct ethtool_pauseparam *ecmd)
3004{
3005 struct sky2_port *sky2 = netdev_priv(dev);
3006
3007 ecmd->tx_pause = sky2->tx_pause;
3008 ecmd->rx_pause = sky2->rx_pause;
3009 ecmd->autoneg = sky2->autoneg;
3010}
3011
3012static int sky2_set_pauseparam(struct net_device *dev,
3013 struct ethtool_pauseparam *ecmd)
3014{
3015 struct sky2_port *sky2 = netdev_priv(dev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003016
3017 sky2->autoneg = ecmd->autoneg;
3018 sky2->tx_pause = ecmd->tx_pause != 0;
3019 sky2->rx_pause = ecmd->rx_pause != 0;
3020
Stephen Hemminger1b537562005-12-20 15:08:07 -08003021 sky2_phy_reinit(sky2);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003022
Stephen Hemminger2eaba1a2006-09-06 12:44:47 -07003023 return 0;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003024}
3025
Stephen Hemmingerfb173582005-12-09 11:34:56 -08003026static int sky2_get_coalesce(struct net_device *dev,
3027 struct ethtool_coalesce *ecmd)
3028{
3029 struct sky2_port *sky2 = netdev_priv(dev);
3030 struct sky2_hw *hw = sky2->hw;
3031
3032 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3033 ecmd->tx_coalesce_usecs = 0;
3034 else {
3035 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3036 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3037 }
3038 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3039
3040 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3041 ecmd->rx_coalesce_usecs = 0;
3042 else {
3043 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3044 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3045 }
3046 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3047
3048 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3049 ecmd->rx_coalesce_usecs_irq = 0;
3050 else {
3051 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3052 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3053 }
3054
3055 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3056
3057 return 0;
3058}
3059
3060/* Note: this affect both ports */
3061static int sky2_set_coalesce(struct net_device *dev,
3062 struct ethtool_coalesce *ecmd)
3063{
3064 struct sky2_port *sky2 = netdev_priv(dev);
3065 struct sky2_hw *hw = sky2->hw;
Stephen Hemminger77b3d6a2006-03-20 15:48:18 -08003066 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
Stephen Hemmingerfb173582005-12-09 11:34:56 -08003067
Stephen Hemminger77b3d6a2006-03-20 15:48:18 -08003068 if (ecmd->tx_coalesce_usecs > tmax ||
3069 ecmd->rx_coalesce_usecs > tmax ||
3070 ecmd->rx_coalesce_usecs_irq > tmax)
Stephen Hemmingerfb173582005-12-09 11:34:56 -08003071 return -EINVAL;
3072
Stephen Hemmingerff81fbb2006-02-22 11:44:59 -08003073 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
Stephen Hemmingerfb173582005-12-09 11:34:56 -08003074 return -EINVAL;
Stephen Hemmingerff81fbb2006-02-22 11:44:59 -08003075 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
Stephen Hemmingerfb173582005-12-09 11:34:56 -08003076 return -EINVAL;
Stephen Hemmingerff81fbb2006-02-22 11:44:59 -08003077 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
Stephen Hemmingerfb173582005-12-09 11:34:56 -08003078 return -EINVAL;
3079
3080 if (ecmd->tx_coalesce_usecs == 0)
3081 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3082 else {
3083 sky2_write32(hw, STAT_TX_TIMER_INI,
3084 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3085 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3086 }
3087 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3088
3089 if (ecmd->rx_coalesce_usecs == 0)
3090 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3091 else {
3092 sky2_write32(hw, STAT_LEV_TIMER_INI,
3093 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3094 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3095 }
3096 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3097
3098 if (ecmd->rx_coalesce_usecs_irq == 0)
3099 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3100 else {
Stephen Hemmingerd28d4872006-01-30 11:37:56 -08003101 sky2_write32(hw, STAT_ISR_TIMER_INI,
Stephen Hemmingerfb173582005-12-09 11:34:56 -08003102 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3103 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3104 }
3105 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3106 return 0;
3107}
3108
Stephen Hemminger793b8832005-09-14 16:06:14 -07003109static void sky2_get_ringparam(struct net_device *dev,
3110 struct ethtool_ringparam *ering)
3111{
3112 struct sky2_port *sky2 = netdev_priv(dev);
3113
3114 ering->rx_max_pending = RX_MAX_PENDING;
3115 ering->rx_mini_max_pending = 0;
3116 ering->rx_jumbo_max_pending = 0;
3117 ering->tx_max_pending = TX_RING_SIZE - 1;
3118
3119 ering->rx_pending = sky2->rx_pending;
3120 ering->rx_mini_pending = 0;
3121 ering->rx_jumbo_pending = 0;
3122 ering->tx_pending = sky2->tx_pending;
3123}
3124
3125static int sky2_set_ringparam(struct net_device *dev,
3126 struct ethtool_ringparam *ering)
3127{
3128 struct sky2_port *sky2 = netdev_priv(dev);
3129 int err = 0;
3130
3131 if (ering->rx_pending > RX_MAX_PENDING ||
3132 ering->rx_pending < 8 ||
3133 ering->tx_pending < MAX_SKB_TX_LE ||
3134 ering->tx_pending > TX_RING_SIZE - 1)
3135 return -EINVAL;
3136
3137 if (netif_running(dev))
3138 sky2_down(dev);
3139
3140 sky2->rx_pending = ering->rx_pending;
3141 sky2->tx_pending = ering->tx_pending;
3142
Stephen Hemminger1b537562005-12-20 15:08:07 -08003143 if (netif_running(dev)) {
Stephen Hemminger793b8832005-09-14 16:06:14 -07003144 err = sky2_up(dev);
Stephen Hemminger1b537562005-12-20 15:08:07 -08003145 if (err)
3146 dev_close(dev);
Stephen Hemminger6ed995b2005-12-20 15:08:08 -08003147 else
3148 sky2_set_multicast(dev);
Stephen Hemminger1b537562005-12-20 15:08:07 -08003149 }
Stephen Hemminger793b8832005-09-14 16:06:14 -07003150
3151 return err;
3152}
3153
Stephen Hemminger793b8832005-09-14 16:06:14 -07003154static int sky2_get_regs_len(struct net_device *dev)
3155{
Stephen Hemminger6e4cbb32005-09-19 15:47:57 -07003156 return 0x4000;
Stephen Hemminger793b8832005-09-14 16:06:14 -07003157}
3158
3159/*
3160 * Returns copy of control register region
Stephen Hemminger6e4cbb32005-09-19 15:47:57 -07003161 * Note: access to the RAM address register set will cause timeouts.
Stephen Hemminger793b8832005-09-14 16:06:14 -07003162 */
3163static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3164 void *p)
3165{
3166 const struct sky2_port *sky2 = netdev_priv(dev);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003167 const void __iomem *io = sky2->hw->regs;
Stephen Hemminger793b8832005-09-14 16:06:14 -07003168
Stephen Hemminger6e4cbb32005-09-19 15:47:57 -07003169 BUG_ON(regs->len < B3_RI_WTO_R1);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003170 regs->version = 1;
Stephen Hemminger6e4cbb32005-09-19 15:47:57 -07003171 memset(p, 0, regs->len);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003172
Stephen Hemminger6e4cbb32005-09-19 15:47:57 -07003173 memcpy_fromio(p, io, B3_RAM_ADDR);
3174
3175 memcpy_fromio(p + B3_RI_WTO_R1,
3176 io + B3_RI_WTO_R1,
3177 regs->len - B3_RI_WTO_R1);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003178}
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003179
Jeff Garzik7282d492006-09-13 14:30:00 -04003180static const struct ethtool_ops sky2_ethtool_ops = {
Stephen Hemminger793b8832005-09-14 16:06:14 -07003181 .get_settings = sky2_get_settings,
3182 .set_settings = sky2_set_settings,
3183 .get_drvinfo = sky2_get_drvinfo,
3184 .get_msglevel = sky2_get_msglevel,
3185 .set_msglevel = sky2_set_msglevel,
Stephen Hemminger9a7ae0a2005-09-27 15:28:42 -07003186 .nway_reset = sky2_nway_reset,
Stephen Hemminger793b8832005-09-14 16:06:14 -07003187 .get_regs_len = sky2_get_regs_len,
3188 .get_regs = sky2_get_regs,
3189 .get_link = ethtool_op_get_link,
3190 .get_sg = ethtool_op_get_sg,
3191 .set_sg = ethtool_op_set_sg,
3192 .get_tx_csum = ethtool_op_get_tx_csum,
3193 .set_tx_csum = ethtool_op_set_tx_csum,
3194 .get_tso = ethtool_op_get_tso,
3195 .set_tso = ethtool_op_set_tso,
3196 .get_rx_csum = sky2_get_rx_csum,
3197 .set_rx_csum = sky2_set_rx_csum,
3198 .get_strings = sky2_get_strings,
Stephen Hemmingerfb173582005-12-09 11:34:56 -08003199 .get_coalesce = sky2_get_coalesce,
3200 .set_coalesce = sky2_set_coalesce,
Stephen Hemminger793b8832005-09-14 16:06:14 -07003201 .get_ringparam = sky2_get_ringparam,
3202 .set_ringparam = sky2_set_ringparam,
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003203 .get_pauseparam = sky2_get_pauseparam,
3204 .set_pauseparam = sky2_set_pauseparam,
Stephen Hemminger793b8832005-09-14 16:06:14 -07003205 .phys_id = sky2_phys_id,
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003206 .get_stats_count = sky2_get_stats_count,
3207 .get_ethtool_stats = sky2_get_ethtool_stats,
Stephen Hemminger2995bfb2005-09-28 10:01:03 -07003208 .get_perm_addr = ethtool_op_get_perm_addr,
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003209};
3210
3211/* Initialize network device */
3212static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3213 unsigned port, int highmem)
3214{
3215 struct sky2_port *sky2;
3216 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3217
3218 if (!dev) {
3219 printk(KERN_ERR "sky2 etherdev alloc failed");
3220 return NULL;
3221 }
3222
3223 SET_MODULE_OWNER(dev);
3224 SET_NETDEV_DEV(dev, &hw->pdev->dev);
shemminger@osdl.orgef743d32005-11-30 11:45:12 -08003225 dev->irq = hw->pdev->irq;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003226 dev->open = sky2_up;
3227 dev->stop = sky2_down;
shemminger@osdl.orgef743d32005-11-30 11:45:12 -08003228 dev->do_ioctl = sky2_ioctl;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003229 dev->hard_start_xmit = sky2_xmit_frame;
3230 dev->get_stats = sky2_get_stats;
3231 dev->set_multicast_list = sky2_set_multicast;
3232 dev->set_mac_address = sky2_set_mac_address;
3233 dev->change_mtu = sky2_change_mtu;
3234 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3235 dev->tx_timeout = sky2_tx_timeout;
3236 dev->watchdog_timeo = TX_WATCHDOG;
3237 if (port == 0)
3238 dev->poll = sky2_poll;
3239 dev->weight = NAPI_WEIGHT;
3240#ifdef CONFIG_NET_POLL_CONTROLLER
3241 dev->poll_controller = sky2_netpoll;
3242#endif
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003243
3244 sky2 = netdev_priv(dev);
3245 sky2->netdev = dev;
3246 sky2->hw = hw;
3247 sky2->msg_enable = netif_msg_init(debug, default_msg);
3248
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003249 /* Auto speed and flow control */
3250 sky2->autoneg = AUTONEG_ENABLE;
Stephen Hemminger585b56012005-12-09 11:35:10 -08003251 sky2->tx_pause = 1;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003252 sky2->rx_pause = 1;
3253 sky2->duplex = -1;
3254 sky2->speed = -1;
3255 sky2->advertising = sky2_supported_modes(hw);
Stephen Hemmingeree7abb02006-05-18 11:16:21 -07003256 sky2->rx_csum = 1;
Stephen Hemminger75d070c2005-12-09 11:35:11 -08003257
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08003258 spin_lock_init(&sky2->phy_lock);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003259 sky2->tx_pending = TX_DEF_PENDING;
Stephen Hemminger290d4de2006-03-20 15:48:15 -08003260 sky2->rx_pending = RX_DEF_PENDING;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003261
3262 hw->dev[port] = dev;
3263
3264 sky2->port = port;
3265
shemminger@osdl.org5a5b1ea2005-11-30 11:45:15 -08003266 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3267 dev->features |= NETIF_F_TSO;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003268 if (highmem)
3269 dev->features |= NETIF_F_HIGHDMA;
Stephen Hemminger793b8832005-09-14 16:06:14 -07003270 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003271
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -07003272#ifdef SKY2_VLAN_TAG_USED
3273 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3274 dev->vlan_rx_register = sky2_vlan_rx_register;
3275 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3276#endif
3277
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003278 /* read the mac address */
Stephen Hemminger793b8832005-09-14 16:06:14 -07003279 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
Stephen Hemminger2995bfb2005-09-28 10:01:03 -07003280 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003281
3282 /* device is off until link detection */
3283 netif_carrier_off(dev);
3284 netif_stop_queue(dev);
3285
3286 return dev;
3287}
3288
Stephen Hemminger28bd1812006-01-17 13:43:19 -08003289static void __devinit sky2_show_addr(struct net_device *dev)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003290{
3291 const struct sky2_port *sky2 = netdev_priv(dev);
3292
3293 if (netif_msg_probe(sky2))
3294 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3295 dev->name,
3296 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3297 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3298}
3299
Stephen Hemmingerfb2690a2006-03-20 15:48:19 -08003300/* Handle software interrupt used during MSI test */
3301static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id,
3302 struct pt_regs *regs)
3303{
3304 struct sky2_hw *hw = dev_id;
3305 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3306
3307 if (status == 0)
3308 return IRQ_NONE;
3309
3310 if (status & Y2_IS_IRQ_SW) {
3311 hw->msi_detected = 1;
3312 wake_up(&hw->msi_wait);
3313 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3314 }
3315 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3316
3317 return IRQ_HANDLED;
3318}
3319
3320/* Test interrupt path by forcing a a software IRQ */
3321static int __devinit sky2_test_msi(struct sky2_hw *hw)
3322{
3323 struct pci_dev *pdev = hw->pdev;
3324 int err;
3325
shemminger@osdl.orgbb507fe2006-08-28 10:00:48 -07003326 init_waitqueue_head (&hw->msi_wait);
3327
Stephen Hemmingerfb2690a2006-03-20 15:48:19 -08003328 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3329
Thomas Gleixner1fb9df52006-07-01 19:29:39 -07003330 err = request_irq(pdev->irq, sky2_test_intr, IRQF_SHARED, DRV_NAME, hw);
Stephen Hemmingerfb2690a2006-03-20 15:48:19 -08003331 if (err) {
3332 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3333 pci_name(pdev), pdev->irq);
3334 return err;
3335 }
3336
Stephen Hemmingerfb2690a2006-03-20 15:48:19 -08003337 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
shemminger@osdl.orgbb507fe2006-08-28 10:00:48 -07003338 sky2_read8(hw, B0_CTST);
Stephen Hemmingerfb2690a2006-03-20 15:48:19 -08003339
3340 wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10);
3341
3342 if (!hw->msi_detected) {
3343 /* MSI test failed, go back to INTx mode */
3344 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
3345 "switching to INTx mode. Please report this failure to "
3346 "the PCI maintainer and include system chipset information.\n",
3347 pci_name(pdev));
3348
3349 err = -EOPNOTSUPP;
3350 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3351 }
3352
3353 sky2_write32(hw, B0_IMSK, 0);
3354
3355 free_irq(pdev->irq, hw);
3356
3357 return err;
3358}
3359
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003360static int __devinit sky2_probe(struct pci_dev *pdev,
3361 const struct pci_device_id *ent)
3362{
Stephen Hemminger793b8832005-09-14 16:06:14 -07003363 struct net_device *dev, *dev1 = NULL;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003364 struct sky2_hw *hw;
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -07003365 int err, pm_cap, using_dac = 0;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003366
Stephen Hemminger793b8832005-09-14 16:06:14 -07003367 err = pci_enable_device(pdev);
3368 if (err) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003369 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3370 pci_name(pdev));
3371 goto err_out;
3372 }
3373
Stephen Hemminger793b8832005-09-14 16:06:14 -07003374 err = pci_request_regions(pdev, DRV_NAME);
3375 if (err) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003376 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3377 pci_name(pdev));
Stephen Hemminger793b8832005-09-14 16:06:14 -07003378 goto err_out;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003379 }
3380
3381 pci_set_master(pdev);
3382
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -07003383 /* Find power-management capability. */
3384 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3385 if (pm_cap == 0) {
3386 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3387 "aborting.\n");
3388 err = -EIO;
3389 goto err_out_free_regions;
3390 }
3391
Stephen Hemmingerd1f3d4d2006-01-17 13:43:11 -08003392 if (sizeof(dma_addr_t) > sizeof(u32) &&
3393 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3394 using_dac = 1;
3395 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3396 if (err < 0) {
3397 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3398 "for consistent allocations\n", pci_name(pdev));
3399 goto err_out_free_regions;
3400 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003401
Stephen Hemmingerd1f3d4d2006-01-17 13:43:11 -08003402 } else {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003403 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3404 if (err) {
3405 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3406 pci_name(pdev));
3407 goto err_out_free_regions;
3408 }
3409 }
Stephen Hemmingerd1f3d4d2006-01-17 13:43:11 -08003410
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003411 err = -ENOMEM;
Stephen Hemminger6aad85d2006-01-17 13:43:18 -08003412 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003413 if (!hw) {
3414 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3415 pci_name(pdev));
3416 goto err_out_free_regions;
3417 }
3418
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003419 hw->pdev = pdev;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003420
3421 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3422 if (!hw->regs) {
3423 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3424 pci_name(pdev));
3425 goto err_out_free_hw;
3426 }
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -07003427 hw->pm_cap = pm_cap;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003428
Stephen Hemminger56a645c2006-02-22 11:45:02 -08003429#ifdef __BIG_ENDIAN
Stephen Hemmingerf65b1382006-09-06 12:45:02 -07003430 /* The sk98lin vendor driver uses hardware byte swapping but
3431 * this driver uses software swapping.
3432 */
Stephen Hemminger56a645c2006-02-22 11:45:02 -08003433 {
3434 u32 reg;
Stephen Hemminger56a645c2006-02-22 11:45:02 -08003435 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
Stephen Hemmingerf65b1382006-09-06 12:45:02 -07003436 reg &= ~PCI_REV_DESC;
Stephen Hemminger56a645c2006-02-22 11:45:02 -08003437 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3438 }
3439#endif
3440
Stephen Hemminger08c06d82006-01-30 11:37:54 -08003441 /* ring for status responses */
3442 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3443 &hw->st_dma);
3444 if (!hw->st_le)
3445 goto err_out_iounmap;
3446
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003447 err = sky2_reset(hw);
3448 if (err)
Stephen Hemminger793b8832005-09-14 16:06:14 -07003449 goto err_out_iounmap;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003450
Greg Kroah-Hartman7c7459d2006-06-12 15:13:08 -07003451 printk(KERN_INFO PFX "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3452 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3453 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
Stephen Hemminger793b8832005-09-14 16:06:14 -07003454 hw->chip_id, hw->chip_rev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003455
Stephen Hemminger793b8832005-09-14 16:06:14 -07003456 dev = sky2_init_netdev(hw, 0, using_dac);
3457 if (!dev)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003458 goto err_out_free_pci;
3459
Stephen Hemminger9fa1b1f2006-09-26 11:57:40 -07003460 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3461 err = sky2_test_msi(hw);
3462 if (err == -EOPNOTSUPP)
3463 pci_disable_msi(pdev);
3464 else if (err)
3465 goto err_out_free_netdev;
3466 }
3467
Stephen Hemminger793b8832005-09-14 16:06:14 -07003468 err = register_netdev(dev);
3469 if (err) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003470 printk(KERN_ERR PFX "%s: cannot register net device\n",
3471 pci_name(pdev));
3472 goto err_out_free_netdev;
3473 }
3474
Stephen Hemminger9fa1b1f2006-09-26 11:57:40 -07003475 err = request_irq(pdev->irq, sky2_intr, IRQF_SHARED, dev->name, hw);
3476 if (err) {
3477 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3478 pci_name(pdev), pdev->irq);
3479 goto err_out_unregister;
3480 }
3481 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3482
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003483 sky2_show_addr(dev);
3484
3485 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3486 if (register_netdev(dev1) == 0)
3487 sky2_show_addr(dev1);
3488 else {
3489 /* Failure to register second port need not be fatal */
Stephen Hemminger793b8832005-09-14 16:06:14 -07003490 printk(KERN_WARNING PFX
3491 "register of second port failed\n");
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003492 hw->dev[1] = NULL;
3493 free_netdev(dev1);
3494 }
3495 }
3496
Stephen Hemminger01bd7562006-05-08 15:11:30 -07003497 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
Stephen Hemmingereb35cf62006-06-13 17:17:31 +09003498 sky2_idle_start(hw);
Stephen Hemmingerd27ed382006-04-25 10:58:51 -07003499
Stephen Hemminger793b8832005-09-14 16:06:14 -07003500 pci_set_drvdata(pdev, hw);
3501
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003502 return 0;
3503
Stephen Hemminger793b8832005-09-14 16:06:14 -07003504err_out_unregister:
Stephen Hemmingerfb2690a2006-03-20 15:48:19 -08003505 pci_disable_msi(pdev);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003506 unregister_netdev(dev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003507err_out_free_netdev:
3508 free_netdev(dev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003509err_out_free_pci:
Stephen Hemminger793b8832005-09-14 16:06:14 -07003510 sky2_write8(hw, B0_CTST, CS_RST_SET);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003511 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3512err_out_iounmap:
3513 iounmap(hw->regs);
3514err_out_free_hw:
3515 kfree(hw);
3516err_out_free_regions:
3517 pci_release_regions(pdev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003518 pci_disable_device(pdev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003519err_out:
3520 return err;
3521}
3522
3523static void __devexit sky2_remove(struct pci_dev *pdev)
3524{
Stephen Hemminger793b8832005-09-14 16:06:14 -07003525 struct sky2_hw *hw = pci_get_drvdata(pdev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003526 struct net_device *dev0, *dev1;
3527
Stephen Hemminger793b8832005-09-14 16:06:14 -07003528 if (!hw)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003529 return;
3530
Stephen Hemmingerd27ed382006-04-25 10:58:51 -07003531 del_timer_sync(&hw->idle_timer);
3532
3533 sky2_write32(hw, B0_IMSK, 0);
Stephen Hemminger72cb8522006-05-08 15:11:32 -07003534 synchronize_irq(hw->pdev->irq);
3535
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003536 dev0 = hw->dev[0];
Stephen Hemminger793b8832005-09-14 16:06:14 -07003537 dev1 = hw->dev[1];
3538 if (dev1)
3539 unregister_netdev(dev1);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003540 unregister_netdev(dev0);
3541
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -07003542 sky2_set_power_state(hw, PCI_D3hot);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003543 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003544 sky2_write8(hw, B0_CTST, CS_RST_SET);
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -07003545 sky2_read8(hw, B0_CTST);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003546
3547 free_irq(pdev->irq, hw);
Stephen Hemmingerfb2690a2006-03-20 15:48:19 -08003548 pci_disable_msi(pdev);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003549 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003550 pci_release_regions(pdev);
3551 pci_disable_device(pdev);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003552
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003553 if (dev1)
3554 free_netdev(dev1);
3555 free_netdev(dev0);
3556 iounmap(hw->regs);
3557 kfree(hw);
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -07003558
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003559 pci_set_drvdata(pdev, NULL);
3560}
3561
3562#ifdef CONFIG_PM
3563static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3564{
Stephen Hemminger793b8832005-09-14 16:06:14 -07003565 struct sky2_hw *hw = pci_get_drvdata(pdev);
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -07003566 int i;
Stephen Hemminger2ccc99b2006-06-13 17:17:27 +09003567 pci_power_t pstate = pci_choose_state(pdev, state);
3568
3569 if (!(pstate == PCI_D3hot || pstate == PCI_D3cold))
3570 return -EINVAL;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003571
Stephen Hemmingereb35cf62006-06-13 17:17:31 +09003572 del_timer_sync(&hw->idle_timer);
Stephen Hemminger6a5706b2006-07-12 15:23:46 -07003573 netif_poll_disable(hw->dev[0]);
Stephen Hemmingereb35cf62006-06-13 17:17:31 +09003574
Stephen Hemmingerf05267e2006-06-13 17:17:28 +09003575 for (i = 0; i < hw->ports; i++) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003576 struct net_device *dev = hw->dev[i];
3577
Stephen Hemminger6a5706b2006-07-12 15:23:46 -07003578 if (netif_running(dev)) {
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -07003579 sky2_down(dev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003580 netif_device_detach(dev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003581 }
3582 }
3583
Stephen Hemminger8ab8fca2006-06-13 17:17:30 +09003584 sky2_write32(hw, B0_IMSK, 0);
Linus Torvaldsd374c1c2006-06-12 12:53:27 -07003585 pci_save_state(pdev);
Stephen Hemminger2ccc99b2006-06-13 17:17:27 +09003586 sky2_set_power_state(hw, pstate);
3587 return 0;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003588}
3589
3590static int sky2_resume(struct pci_dev *pdev)
3591{
Stephen Hemminger793b8832005-09-14 16:06:14 -07003592 struct sky2_hw *hw = pci_get_drvdata(pdev);
Stephen Hemminger08c06d82006-01-30 11:37:54 -08003593 int i, err;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003594
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003595 pci_restore_state(pdev);
3596 pci_enable_wake(pdev, PCI_D0, 0);
Stephen Hemminger2ccc99b2006-06-13 17:17:27 +09003597 sky2_set_power_state(hw, PCI_D0);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003598
Stephen Hemminger08c06d82006-01-30 11:37:54 -08003599 err = sky2_reset(hw);
3600 if (err)
3601 goto out;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003602
Stephen Hemminger8ab8fca2006-06-13 17:17:30 +09003603 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3604
Stephen Hemmingerf05267e2006-06-13 17:17:28 +09003605 for (i = 0; i < hw->ports; i++) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003606 struct net_device *dev = hw->dev[i];
Stephen Hemminger6a5706b2006-07-12 15:23:46 -07003607 if (netif_running(dev)) {
Stephen Hemminger08c06d82006-01-30 11:37:54 -08003608 netif_device_attach(dev);
Stephen Hemminger88d11362006-06-16 12:10:46 -07003609
Stephen Hemminger08c06d82006-01-30 11:37:54 -08003610 err = sky2_up(dev);
3611 if (err) {
3612 printk(KERN_ERR PFX "%s: could not up: %d\n",
3613 dev->name, err);
3614 dev_close(dev);
Stephen Hemmingereb35cf62006-06-13 17:17:31 +09003615 goto out;
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -07003616 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003617 }
3618 }
Stephen Hemmingereb35cf62006-06-13 17:17:31 +09003619
Stephen Hemminger6a5706b2006-07-12 15:23:46 -07003620 netif_poll_enable(hw->dev[0]);
Stephen Hemmingereb35cf62006-06-13 17:17:31 +09003621 sky2_idle_start(hw);
Stephen Hemminger08c06d82006-01-30 11:37:54 -08003622out:
3623 return err;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003624}
3625#endif
3626
3627static struct pci_driver sky2_driver = {
Stephen Hemminger793b8832005-09-14 16:06:14 -07003628 .name = DRV_NAME,
3629 .id_table = sky2_id_table,
3630 .probe = sky2_probe,
3631 .remove = __devexit_p(sky2_remove),
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003632#ifdef CONFIG_PM
Stephen Hemminger793b8832005-09-14 16:06:14 -07003633 .suspend = sky2_suspend,
3634 .resume = sky2_resume,
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003635#endif
3636};
3637
3638static int __init sky2_init_module(void)
3639{
shemminger@osdl.org50241c42005-11-30 11:45:22 -08003640 return pci_register_driver(&sky2_driver);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003641}
3642
3643static void __exit sky2_cleanup_module(void)
3644{
3645 pci_unregister_driver(&sky2_driver);
3646}
3647
3648module_init(sky2_init_module);
3649module_exit(sky2_cleanup_module);
3650
3651MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3652MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3653MODULE_LICENSE("GPL");
shemminger@osdl.org5f4f9dc2005-11-30 11:45:23 -08003654MODULE_VERSION(DRV_VERSION);