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gerrit-public.fairphone.software / fp2-dev / kernel / msm / 75051f2dac34c71be2094141492113340cb9e86a / . / arch / arm / mach-msm / clock-8226.c
blob: 18c922d50890b820daeb4e3b1887e5e22fd0b596 [file] [log] [blame]
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/err.h>
16#include <linux/ctype.h>
17#include <linux/io.h>
18#include <linux/spinlock.h>
19#include <linux/delay.h>
20#include <linux/clk.h>
21#include <linux/iopoll.h>
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]22#include <linux/regulator/consumer.h>
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]23
24#include <mach/rpm-regulator-smd.h>
25#include <mach/socinfo.h>
26#include <mach/rpm-smd.h>
27
28#include "clock-local2.h"
29#include "clock-pll.h"
30#include "clock-rpm.h"
31#include "clock-voter.h"
32#include "clock-mdss-8974.h"
33#include "clock.h"
34
35enum {
36 GCC_BASE,
37 MMSS_BASE,
38 LPASS_BASE,
39 APCS_BASE,
40 APCS_PLL_BASE,
41 N_BASES,
42};
43
44static void __iomem *virt_bases[N_BASES];
45
46#define GCC_REG_BASE(x) (void __iomem *)(virt_bases[GCC_BASE] + (x))
47#define MMSS_REG_BASE(x) (void __iomem *)(virt_bases[MMSS_BASE] + (x))
48#define LPASS_REG_BASE(x) (void __iomem *)(virt_bases[LPASS_BASE] + (x))
49#define APCS_REG_BASE(x) (void __iomem *)(virt_bases[APCS_BASE] + (x))
50
51/* Mux source select values */
52#define xo_source_val 0
53#define gpll0_source_val 1
54#define gpll1_source_val 2
55
56#define xo_mm_source_val 0
57#define mmpll0_pll_mm_source_val 1
58#define mmpll1_pll_mm_source_val 2
59#define mmpll2_pll_mm_source_val 3
60#define gpll0_mm_source_val 5
61#define dsipll_750_mm_source_val 1
62#define dsipll_667_mm_source_val 1
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]63#define dsipll0_byte_mm_source_val 1
64#define dsipll0_pixel_mm_source_val 1
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]65
66#define gpll1_hsic_source_val 4
67
68#define xo_lpass_source_val 0
69#define lpaaudio_pll_lpass_source_val 1
70#define gpll0_lpass_source_val 5
71
72/* Prevent a divider of -1 */
73#define FIXDIV(div) (div ? (2 * (div) - 1) : (0))
74
75#define F_GCC(f, s, div, m, n) \
76 { \
77 .freq_hz = (f), \
78 .src_clk = &s.c, \
79 .m_val = (m), \
80 .n_val = ~((n)-(m)) * !!(n), \
81 .d_val = ~(n),\
82 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
83 | BVAL(10, 8, s##_source_val), \
84 }
85
86#define F_MMSS(f, s, div, m, n) \
87 { \
88 .freq_hz = (f), \
89 .src_clk = &s.c, \
90 .m_val = (m), \
91 .n_val = ~((n)-(m)) * !!(n), \
92 .d_val = ~(n),\
93 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
94 | BVAL(10, 8, s##_mm_source_val), \
95 }
96
97#define F_MDSS(f, s, div, m, n) \
98 { \
99 .freq_hz = (f), \
100 .m_val = (m), \
101 .n_val = ~((n)-(m)) * !!(n), \
102 .d_val = ~(n),\
103 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
104 | BVAL(10, 8, s##_mm_source_val), \
105 }
106
107#define F_HSIC(f, s, div, m, n) \
108 { \
109 .freq_hz = (f), \
110 .src_clk = &s.c, \
111 .m_val = (m), \
112 .n_val = ~((n)-(m)) * !!(n), \
113 .d_val = ~(n),\
114 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
115 | BVAL(10, 8, s##_hsic_source_val), \
116 }
117
118#define F_LPASS(f, s, div, m, n) \
119 { \
120 .freq_hz = (f), \
121 .src_clk = &s.c, \
122 .m_val = (m), \
123 .n_val = ~((n)-(m)) * !!(n), \
124 .d_val = ~(n),\
125 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
126 | BVAL(10, 8, s##_lpass_source_val), \
127 }
128
129#define F_APCS_PLL(f, l, m, n, pre_div, post_div, vco) \
130 { \
131 .freq_hz = (f), \
132 .l_val = (l), \
133 .m_val = (m), \
134 .n_val = (n), \
135 .pre_div_val = BVAL(12, 12, (pre_div)), \
136 .post_div_val = BVAL(9, 8, (post_div)), \
137 .vco_val = BVAL(29, 28, (vco)), \
138 }
139
140#define VDD_DIG_FMAX_MAP1(l1, f1) \
141 .vdd_class = &vdd_dig, \
142 .fmax = (unsigned long[VDD_DIG_NUM]) { \
143 [VDD_DIG_##l1] = (f1), \
144 }, \
145 .num_fmax = VDD_DIG_NUM
146
147#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \
148 .vdd_class = &vdd_dig, \
149 .fmax = (unsigned long[VDD_DIG_NUM]) { \
150 [VDD_DIG_##l1] = (f1), \
151 [VDD_DIG_##l2] = (f2), \
152 }, \
153 .num_fmax = VDD_DIG_NUM
154
155#define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \
156 .vdd_class = &vdd_dig, \
157 .fmax = (unsigned long[VDD_DIG_NUM]) { \
158 [VDD_DIG_##l1] = (f1), \
159 [VDD_DIG_##l2] = (f2), \
160 [VDD_DIG_##l3] = (f3), \
161 }, \
162 .num_fmax = VDD_DIG_NUM
163
164enum vdd_dig_levels {
165 VDD_DIG_NONE,
166 VDD_DIG_LOW,
167 VDD_DIG_NOMINAL,
168 VDD_DIG_HIGH,
169 VDD_DIG_NUM
170};
171
Patrick Dalyebc26bc2013-02-05 11:49:07 -0800[diff] [blame]172static const int *vdd_corner[] = {
173 [VDD_DIG_NONE] = VDD_UV(RPM_REGULATOR_CORNER_NONE),
174 [VDD_DIG_LOW] = VDD_UV(RPM_REGULATOR_CORNER_SVS_SOC),
175 [VDD_DIG_NOMINAL] = VDD_UV(RPM_REGULATOR_CORNER_NORMAL),
176 [VDD_DIG_HIGH] = VDD_UV(RPM_REGULATOR_CORNER_SUPER_TURBO),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]177};
178
Patrick Dalyebc26bc2013-02-05 11:49:07 -0800[diff] [blame]179static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner);
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]180
181#define RPM_MISC_CLK_TYPE 0x306b6c63
182#define RPM_BUS_CLK_TYPE 0x316b6c63
183#define RPM_MEM_CLK_TYPE 0x326b6c63
184
185#define RPM_SMD_KEY_ENABLE 0x62616E45
186
187#define CXO_ID 0x0
188#define QDSS_ID 0x1
189
190#define PNOC_ID 0x0
191#define SNOC_ID 0x1
192#define CNOC_ID 0x2
193#define MMSSNOC_AHB_ID 0x3
194
195#define BIMC_ID 0x0
196#define OXILI_ID 0x1
197#define OCMEM_ID 0x2
198
199#define D0_ID 1
200#define D1_ID 2
201#define A0_ID 4
202#define A1_ID 5
203#define A2_ID 6
204#define DIFF_CLK_ID 7
205#define DIV_CLK1_ID 11
206#define DIV_CLK2_ID 12
207
208DEFINE_CLK_RPM_SMD(pnoc_clk, pnoc_a_clk, RPM_BUS_CLK_TYPE, PNOC_ID, NULL);
209DEFINE_CLK_RPM_SMD(snoc_clk, snoc_a_clk, RPM_BUS_CLK_TYPE, SNOC_ID, NULL);
210DEFINE_CLK_RPM_SMD(cnoc_clk, cnoc_a_clk, RPM_BUS_CLK_TYPE, CNOC_ID, NULL);
211DEFINE_CLK_RPM_SMD(mmssnoc_ahb_clk, mmssnoc_ahb_a_clk, RPM_BUS_CLK_TYPE,
212 MMSSNOC_AHB_ID, NULL);
213
214DEFINE_CLK_RPM_SMD(bimc_clk, bimc_a_clk, RPM_MEM_CLK_TYPE, BIMC_ID, NULL);
215DEFINE_CLK_RPM_SMD(ocmemgx_clk, ocmemgx_a_clk, RPM_MEM_CLK_TYPE, OCMEM_ID,
216 NULL);
217DEFINE_CLK_RPM_SMD(gfx3d_clk_src, gfx3d_a_clk_src, RPM_MEM_CLK_TYPE, OXILI_ID,
218 NULL);
219
220DEFINE_CLK_RPM_SMD_BRANCH(xo, xo_a_clk,
221 RPM_MISC_CLK_TYPE, CXO_ID, 19200000);
222DEFINE_CLK_RPM_SMD_QDSS(qdss_clk, qdss_a_clk, RPM_MISC_CLK_TYPE, QDSS_ID);
223
224DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_d0, cxo_d0_a, D0_ID);
225DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_d1, cxo_d1_a, D1_ID);
226DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_a0, cxo_a0_a, A0_ID);
227DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_a1, cxo_a1_a, A1_ID);
228DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_a2, cxo_a2_a, A2_ID);
229DEFINE_CLK_RPM_SMD_XO_BUFFER(div_clk1, div_a_clk1, DIV_CLK1_ID);
230DEFINE_CLK_RPM_SMD_XO_BUFFER(div_clk2, div_a_clk2, DIV_CLK2_ID);
231DEFINE_CLK_RPM_SMD_XO_BUFFER(diff_clk, diff_a_clk, DIFF_CLK_ID);
232
233DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_d0_pin, cxo_d0_a_pin, D0_ID);
234DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_d1_pin, cxo_d1_a_pin, D1_ID);
235DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_a0_pin, cxo_a0_a_pin, A0_ID);
236DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_a1_pin, cxo_a1_a_pin, A1_ID);
237DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_a2_pin, cxo_a2_a_pin, A2_ID);
238
239struct measure_mux_entry {
240 struct clk *c;
241 int base;
242 u32 debug_mux;
243};
244
245static struct branch_clk oxilicx_axi_clk;
246
247#define MSS_DEBUG_CLOCK_CTL 0x0078
248#define LPASS_DEBUG_CLK_CTL 0x29000
249#define GLB_CLK_DIAG 0x01C
250#define GLB_TEST_BUS_SEL 0x020
251
252#define MMPLL0_PLL_MODE (0x0000)
253#define MMPLL0_PLL_L_VAL (0x0004)
254#define MMPLL0_PLL_M_VAL (0x0008)
255#define MMPLL0_PLL_N_VAL (0x000C)
256#define MMPLL0_PLL_USER_CTL (0x0010)
257#define MMPLL0_PLL_STATUS (0x001C)
258#define MMPLL1_PLL_MODE (0x0040)
259#define MMPLL1_PLL_L_VAL (0x0044)
260#define MMPLL1_PLL_M_VAL (0x0048)
261#define MMPLL1_PLL_N_VAL (0x004C)
262#define MMPLL1_PLL_USER_CTL (0x0050)
263#define MMPLL1_PLL_STATUS (0x005C)
264#define MMSS_PLL_VOTE_APCS (0x0100)
265#define VCODEC0_CMD_RCGR (0x1000)
266#define VENUS0_VCODEC0_CBCR (0x1028)
267#define VENUS0_AHB_CBCR (0x1030)
268#define VENUS0_AXI_CBCR (0x1034)
269#define PCLK0_CMD_RCGR (0x2000)
270#define MDP_CMD_RCGR (0x2040)
271#define VSYNC_CMD_RCGR (0x2080)
272#define BYTE0_CMD_RCGR (0x2120)
273#define ESC0_CMD_RCGR (0x2160)
274#define MDSS_AHB_CBCR (0x2308)
275#define MDSS_AXI_CBCR (0x2310)
276#define MDSS_PCLK0_CBCR (0x2314)
277#define MDSS_MDP_CBCR (0x231C)
278#define MDSS_MDP_LUT_CBCR (0x2320)
279#define MDSS_VSYNC_CBCR (0x2328)
280#define MDSS_BYTE0_CBCR (0x233C)
281#define MDSS_ESC0_CBCR (0x2344)
282#define CSI0PHYTIMER_CMD_RCGR (0x3000)
283#define CAMSS_PHY0_CSI0PHYTIMER_CBCR (0x3024)
284#define CSI1PHYTIMER_CMD_RCGR (0x3030)
285#define CAMSS_PHY1_CSI1PHYTIMER_CBCR (0x3054)
286#define CSI0_CMD_RCGR (0x3090)
287#define CAMSS_CSI0_CBCR (0x30B4)
288#define CAMSS_CSI0_AHB_CBCR (0x30BC)
289#define CAMSS_CSI0PHY_CBCR (0x30C4)
290#define CAMSS_CSI0RDI_CBCR (0x30D4)
291#define CAMSS_CSI0PIX_CBCR (0x30E4)
292#define CSI1_CMD_RCGR (0x3100)
293#define CAMSS_CSI1_CBCR (0x3124)
294#define CAMSS_CSI1_AHB_CBCR (0x3128)
295#define CAMSS_CSI1PHY_CBCR (0x3134)
296#define CAMSS_CSI1RDI_CBCR (0x3144)
297#define CAMSS_CSI1PIX_CBCR (0x3154)
298#define CAMSS_ISPIF_AHB_CBCR (0x3224)
299#define CCI_CMD_RCGR (0x3300)
300#define CAMSS_CCI_CCI_CBCR (0x3344)
301#define CAMSS_CCI_CCI_AHB_CBCR (0x3348)
302#define MCLK0_CMD_RCGR (0x3360)
303#define CAMSS_MCLK0_CBCR (0x3384)
304#define MCLK1_CMD_RCGR (0x3390)
305#define CAMSS_MCLK1_CBCR (0x33B4)
306#define MMSS_GP0_CMD_RCGR (0x3420)
307#define CAMSS_GP0_CBCR (0x3444)
308#define MMSS_GP1_CMD_RCGR (0x3450)
309#define CAMSS_GP1_CBCR (0x3474)
310#define CAMSS_TOP_AHB_CBCR (0x3484)
311#define CAMSS_MICRO_AHB_CBCR (0x3494)
312#define JPEG0_CMD_RCGR (0x3500)
313#define CAMSS_JPEG_JPEG0_CBCR (0x35A8)
314#define CAMSS_JPEG_JPEG_AHB_CBCR (0x35B4)
315#define CAMSS_JPEG_JPEG_AXI_CBCR (0x35B8)
316#define VFE0_CMD_RCGR (0x3600)
317#define CPP_CMD_RCGR (0x3640)
318#define CAMSS_VFE_VFE0_CBCR (0x36A8)
319#define CAMSS_VFE_CPP_CBCR (0x36B0)
320#define CAMSS_VFE_CPP_AHB_CBCR (0x36B4)
321#define CAMSS_VFE_VFE_AHB_CBCR (0x36B8)
322#define CAMSS_VFE_VFE_AXI_CBCR (0x36BC)
323#define CAMSS_CSI_VFE0_CBCR (0x3704)
324#define OXILI_GFX3D_CBCR (0x4028)
325#define OXILICX_AXI_CBCR (0x4038)
326#define OXILICX_AHB_CBCR (0x403C)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]327#define MMPLL2_PLL_MODE (0x4100)
328#define MMPLL2_PLL_STATUS (0x411C)
329#define MMSS_MMSSNOC_AHB_CBCR (0x5024)
330#define MMSS_MMSSNOC_BTO_AHB_CBCR (0x5028)
331#define MMSS_MISC_AHB_CBCR (0x502C)
332#define AXI_CMD_RCGR (0x5040)
333#define MMSS_S0_AXI_CBCR (0x5064)
334#define MMSS_MMSSNOC_AXI_CBCR (0x506C)
335#define MMSS_DEBUG_CLK_CTL (0x0900)
336#define GPLL0_MODE (0x0000)
337#define GPLL0_L_VAL (0x0004)
338#define GPLL0_M_VAL (0x0008)
339#define GPLL0_N_VAL (0x000C)
340#define GPLL0_USER_CTL (0x0010)
341#define GPLL0_STATUS (0x001C)
342#define GPLL1_MODE (0x0040)
343#define GPLL1_L_VAL (0x0044)
344#define GPLL1_M_VAL (0x0048)
345#define GPLL1_N_VAL (0x004C)
346#define GPLL1_USER_CTL (0x0050)
347#define GPLL1_STATUS (0x005C)
348#define PERIPH_NOC_AHB_CBCR (0x0184)
349#define NOC_CONF_XPU_AHB_CBCR (0x01C0)
350#define MMSS_NOC_CFG_AHB_CBCR (0x024C)
351#define MSS_CFG_AHB_CBCR (0x0280)
352#define MSS_Q6_BIMC_AXI_CBCR (0x0284)
353#define USB_HS_HSIC_BCR (0x0400)
354#define USB_HSIC_AHB_CBCR (0x0408)
355#define USB_HSIC_SYSTEM_CMD_RCGR (0x041C)
356#define USB_HSIC_SYSTEM_CBCR (0x040C)
357#define USB_HSIC_CMD_RCGR (0x0440)
358#define USB_HSIC_CBCR (0x0410)
359#define USB_HSIC_IO_CAL_CMD_RCGR (0x0458)
360#define USB_HSIC_IO_CAL_CBCR (0x0414)
361#define USB_HS_BCR (0x0480)
362#define USB_HS_SYSTEM_CBCR (0x0484)
363#define USB_HS_AHB_CBCR (0x0488)
364#define USB_HS_SYSTEM_CMD_RCGR (0x0490)
365#define USB2A_PHY_SLEEP_CBCR (0x04AC)
366#define SDCC1_APPS_CMD_RCGR (0x04D0)
367#define SDCC1_APPS_CBCR (0x04C4)
368#define SDCC1_AHB_CBCR (0x04C8)
369#define SDCC2_APPS_CMD_RCGR (0x0510)
370#define SDCC2_APPS_CBCR (0x0504)
371#define SDCC2_AHB_CBCR (0x0508)
372#define SDCC3_APPS_CMD_RCGR (0x0550)
373#define SDCC3_APPS_CBCR (0x0544)
374#define SDCC3_AHB_CBCR (0x0548)
375#define BLSP1_AHB_CBCR (0x05C4)
376#define BLSP1_QUP1_SPI_APPS_CBCR (0x0644)
377#define BLSP1_QUP1_I2C_APPS_CBCR (0x0648)
378#define BLSP1_QUP1_I2C_APPS_CMD_RCGR (0x0660)
379#define BLSP1_QUP2_I2C_APPS_CMD_RCGR (0x06E0)
380#define BLSP1_QUP3_I2C_APPS_CMD_RCGR (0x0760)
381#define BLSP1_QUP4_I2C_APPS_CMD_RCGR (0x07E0)
382#define BLSP1_QUP5_I2C_APPS_CMD_RCGR (0x0860)
383#define BLSP1_QUP6_I2C_APPS_CMD_RCGR (0x08E0)
384#define BLSP1_QUP1_SPI_APPS_CMD_RCGR (0x064C)
385#define BLSP1_UART1_APPS_CBCR (0x0684)
386#define BLSP1_UART1_APPS_CMD_RCGR (0x068C)
387#define BLSP1_QUP2_SPI_APPS_CBCR (0x06C4)
388#define BLSP1_QUP2_I2C_APPS_CBCR (0x06C8)
389#define BLSP1_QUP2_SPI_APPS_CMD_RCGR (0x06CC)
390#define BLSP1_UART2_APPS_CBCR (0x0704)
391#define BLSP1_UART2_APPS_CMD_RCGR (0x070C)
392#define BLSP1_QUP3_SPI_APPS_CBCR (0x0744)
393#define BLSP1_QUP3_I2C_APPS_CBCR (0x0748)
394#define BLSP1_QUP3_SPI_APPS_CMD_RCGR (0x074C)
395#define BLSP1_UART3_APPS_CBCR (0x0784)
396#define BLSP1_UART3_APPS_CMD_RCGR (0x078C)
397#define BLSP1_QUP4_SPI_APPS_CBCR (0x07C4)
398#define BLSP1_QUP4_I2C_APPS_CBCR (0x07C8)
399#define BLSP1_QUP4_SPI_APPS_CMD_RCGR (0x07CC)
400#define BLSP1_UART4_APPS_CBCR (0x0804)
401#define BLSP1_UART4_APPS_CMD_RCGR (0x080C)
402#define BLSP1_QUP5_SPI_APPS_CBCR (0x0844)
403#define BLSP1_QUP5_I2C_APPS_CBCR (0x0848)
404#define BLSP1_QUP5_SPI_APPS_CMD_RCGR (0x084C)
405#define BLSP1_UART5_APPS_CBCR (0x0884)
406#define BLSP1_UART5_APPS_CMD_RCGR (0x088C)
407#define BLSP1_QUP6_SPI_APPS_CBCR (0x08C4)
408#define BLSP1_QUP6_I2C_APPS_CBCR (0x08C8)
409#define BLSP1_QUP6_SPI_APPS_CMD_RCGR (0x08CC)
410#define BLSP1_UART6_APPS_CBCR (0x0904)
411#define BLSP1_UART6_APPS_CMD_RCGR (0x090C)
412#define PDM_AHB_CBCR (0x0CC4)
413#define PDM_XO4_CBCR (0x0CC8)
414#define PDM2_CBCR (0x0CCC)
415#define PDM2_CMD_RCGR (0x0CD0)
416#define PRNG_AHB_CBCR (0x0D04)
417#define BAM_DMA_AHB_CBCR (0x0D44)
418#define BOOT_ROM_AHB_CBCR (0x0E04)
419#define CE1_CMD_RCGR (0x1050)
420#define CE1_CBCR (0x1044)
421#define CE1_AXI_CBCR (0x1048)
422#define CE1_AHB_CBCR (0x104C)
423#define GCC_XO_DIV4_CBCR (0x10C8)
424#define LPASS_Q6_AXI_CBCR (0x11C0)
425#define APCS_GPLL_ENA_VOTE (0x1480)
426#define APCS_CLOCK_BRANCH_ENA_VOTE (0x1484)
427#define APCS_CLOCK_SLEEP_ENA_VOTE (0x1488)
428#define GCC_DEBUG_CLK_CTL (0x1880)
429#define CLOCK_FRQ_MEASURE_CTL (0x1884)
430#define CLOCK_FRQ_MEASURE_STATUS (0x1888)
431#define PLLTEST_PAD_CFG (0x188C)
432#define GP1_CBCR (0x1900)
433#define GP1_CMD_RCGR (0x1904)
434#define GP2_CBCR (0x1940)
435#define GP2_CMD_RCGR (0x1944)
436#define GP3_CBCR (0x1980)
437#define GP3_CMD_RCGR (0x1984)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]438#define Q6SS_BCR (0x6000)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]439#define Q6SS_AHB_LFABIF_CBCR (0x22000)
440#define Q6SS_AHBM_CBCR (0x22004)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]441#define Q6SS_XO_CBCR (0x26000)
442
443static unsigned int soft_vote_gpll0;
444
445static struct pll_vote_clk gpll0 = {
446 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
447 .en_mask = BIT(0),
448 .status_reg = (void __iomem *)GPLL0_STATUS,
449 .status_mask = BIT(17),
450 .soft_vote = &soft_vote_gpll0,
451 .soft_vote_mask = PLL_SOFT_VOTE_PRIMARY,
452 .base = &virt_bases[GCC_BASE],
453 .c = {
454 .rate = 600000000,
455 .parent = &xo.c,
456 .dbg_name = "gpll0",
457 .ops = &clk_ops_pll_acpu_vote,
458 CLK_INIT(gpll0.c),
459 },
460};
461
462/*Don't vote for xo if using this clock to allow xo shutdown*/
463static struct pll_vote_clk gpll0_ao = {
464 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
465 .en_mask = BIT(0),
466 .status_reg = (void __iomem *)GPLL0_STATUS,
467 .status_mask = BIT(17),
468 .soft_vote = &soft_vote_gpll0,
469 .soft_vote_mask = PLL_SOFT_VOTE_ACPU,
470 .base = &virt_bases[GCC_BASE],
471 .c = {
472 .rate = 600000000,
473 .dbg_name = "gpll0_ao",
474 .ops = &clk_ops_pll_acpu_vote,
475 CLK_INIT(gpll0_ao.c),
476 },
477};
478
479static struct pll_vote_clk gpll1 = {
480 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
481 .en_mask = BIT(1),
482 .status_reg = (void __iomem *)GPLL1_STATUS,
483 .status_mask = BIT(17),
484 .base = &virt_bases[GCC_BASE],
485 .c = {
486 .rate = 480000000,
487 .parent = &xo.c,
488 .dbg_name = "gpll1",
489 .ops = &clk_ops_pll_vote,
490 CLK_INIT(gpll1.c),
491 },
492};
493
494static struct clk_freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = {
Patrick Daly4f832432013-02-26 12:40:49 -0800[diff] [blame]495 F_GCC( 19200000, xo, 1, 0, 0),
496 F_GCC( 50000000, gpll0, 12, 0, 0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]497 F_END
498};
499
500static struct rcg_clk blsp1_qup1_i2c_apps_clk_src = {
501 .cmd_rcgr_reg = BLSP1_QUP1_I2C_APPS_CMD_RCGR,
502 .set_rate = set_rate_hid,
503 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
504 .current_freq = &rcg_dummy_freq,
505 .base = &virt_bases[GCC_BASE],
506 .c = {
507 .dbg_name = "blsp1_qup1_i2c_apps_clk_src",
508 .ops = &clk_ops_rcg,
509 VDD_DIG_FMAX_MAP1(LOW, 50000000),
510 CLK_INIT(blsp1_qup1_i2c_apps_clk_src.c),
511 },
512};
513
514static struct clk_freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = {
515 F_GCC( 960000, xo, 10, 1, 2),
516 F_GCC( 4800000, xo, 4, 0, 0),
517 F_GCC( 9600000, xo, 2, 0, 0),
518 F_GCC( 15000000, gpll0, 10, 1, 4),
519 F_GCC( 19200000, xo, 1, 0, 0),
520 F_GCC( 25000000, gpll0, 12, 1, 2),
521 F_GCC( 50000000, gpll0, 12, 0, 0),
522 F_END
523};
524
525static struct rcg_clk blsp1_qup1_spi_apps_clk_src = {
526 .cmd_rcgr_reg = BLSP1_QUP1_SPI_APPS_CMD_RCGR,
527 .set_rate = set_rate_mnd,
528 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
529 .current_freq = &rcg_dummy_freq,
530 .base = &virt_bases[GCC_BASE],
531 .c = {
532 .dbg_name = "blsp1_qup1_spi_apps_clk_src",
533 .ops = &clk_ops_rcg_mnd,
534 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
535 CLK_INIT(blsp1_qup1_spi_apps_clk_src.c),
536 },
537};
538
539static struct rcg_clk blsp1_qup2_i2c_apps_clk_src = {
540 .cmd_rcgr_reg = BLSP1_QUP2_I2C_APPS_CMD_RCGR,
541 .set_rate = set_rate_hid,
542 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
543 .current_freq = &rcg_dummy_freq,
544 .base = &virt_bases[GCC_BASE],
545 .c = {
546 .dbg_name = "blsp1_qup2_i2c_apps_clk_src",
547 .ops = &clk_ops_rcg,
548 VDD_DIG_FMAX_MAP1(LOW, 50000000),
549 CLK_INIT(blsp1_qup2_i2c_apps_clk_src.c),
550 },
551};
552
553static struct rcg_clk blsp1_qup2_spi_apps_clk_src = {
554 .cmd_rcgr_reg = BLSP1_QUP2_SPI_APPS_CMD_RCGR,
555 .set_rate = set_rate_mnd,
556 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
557 .current_freq = &rcg_dummy_freq,
558 .base = &virt_bases[GCC_BASE],
559 .c = {
560 .dbg_name = "blsp1_qup2_spi_apps_clk_src",
561 .ops = &clk_ops_rcg_mnd,
562 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
563 CLK_INIT(blsp1_qup2_spi_apps_clk_src.c),
564 },
565};
566
567static struct rcg_clk blsp1_qup3_i2c_apps_clk_src = {
568 .cmd_rcgr_reg = BLSP1_QUP3_I2C_APPS_CMD_RCGR,
569 .set_rate = set_rate_hid,
570 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
571 .current_freq = &rcg_dummy_freq,
572 .base = &virt_bases[GCC_BASE],
573 .c = {
574 .dbg_name = "blsp1_qup3_i2c_apps_clk_src",
575 .ops = &clk_ops_rcg,
576 VDD_DIG_FMAX_MAP1(LOW, 50000000),
577 CLK_INIT(blsp1_qup3_i2c_apps_clk_src.c),
578 },
579};
580
581static struct rcg_clk blsp1_qup3_spi_apps_clk_src = {
582 .cmd_rcgr_reg = BLSP1_QUP3_SPI_APPS_CMD_RCGR,
583 .set_rate = set_rate_mnd,
584 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
585 .current_freq = &rcg_dummy_freq,
586 .base = &virt_bases[GCC_BASE],
587 .c = {
588 .dbg_name = "blsp1_qup3_spi_apps_clk_src",
589 .ops = &clk_ops_rcg_mnd,
590 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
591 CLK_INIT(blsp1_qup3_spi_apps_clk_src.c),
592 },
593};
594
595static struct rcg_clk blsp1_qup4_i2c_apps_clk_src = {
596 .cmd_rcgr_reg = BLSP1_QUP4_I2C_APPS_CMD_RCGR,
597 .set_rate = set_rate_hid,
598 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
599 .current_freq = &rcg_dummy_freq,
600 .base = &virt_bases[GCC_BASE],
601 .c = {
602 .dbg_name = "blsp1_qup4_i2c_apps_clk_src",
603 .ops = &clk_ops_rcg,
604 VDD_DIG_FMAX_MAP1(LOW, 50000000),
605 CLK_INIT(blsp1_qup4_i2c_apps_clk_src.c),
606 },
607};
608
609static struct rcg_clk blsp1_qup4_spi_apps_clk_src = {
610 .cmd_rcgr_reg = BLSP1_QUP4_SPI_APPS_CMD_RCGR,
611 .set_rate = set_rate_mnd,
612 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
613 .current_freq = &rcg_dummy_freq,
614 .base = &virt_bases[GCC_BASE],
615 .c = {
616 .dbg_name = "blsp1_qup4_spi_apps_clk_src",
617 .ops = &clk_ops_rcg_mnd,
618 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
619 CLK_INIT(blsp1_qup4_spi_apps_clk_src.c),
620 },
621};
622
623static struct rcg_clk blsp1_qup5_i2c_apps_clk_src = {
624 .cmd_rcgr_reg = BLSP1_QUP5_I2C_APPS_CMD_RCGR,
625 .set_rate = set_rate_hid,
626 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
627 .current_freq = &rcg_dummy_freq,
628 .base = &virt_bases[GCC_BASE],
629 .c = {
630 .dbg_name = "blsp1_qup5_i2c_apps_clk_src",
631 .ops = &clk_ops_rcg,
632 VDD_DIG_FMAX_MAP1(LOW, 50000000),
633 CLK_INIT(blsp1_qup5_i2c_apps_clk_src.c),
634 },
635};
636
637static struct rcg_clk blsp1_qup5_spi_apps_clk_src = {
638 .cmd_rcgr_reg = BLSP1_QUP5_SPI_APPS_CMD_RCGR,
639 .set_rate = set_rate_mnd,
640 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
641 .current_freq = &rcg_dummy_freq,
642 .base = &virt_bases[GCC_BASE],
643 .c = {
644 .dbg_name = "blsp1_qup5_spi_apps_clk_src",
645 .ops = &clk_ops_rcg_mnd,
646 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
647 CLK_INIT(blsp1_qup5_spi_apps_clk_src.c),
648 },
649};
650
651static struct rcg_clk blsp1_qup6_i2c_apps_clk_src = {
652 .cmd_rcgr_reg = BLSP1_QUP6_I2C_APPS_CMD_RCGR,
653 .set_rate = set_rate_hid,
654 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
655 .current_freq = &rcg_dummy_freq,
656 .base = &virt_bases[GCC_BASE],
657 .c = {
658 .dbg_name = "blsp1_qup6_i2c_apps_clk_src",
659 .ops = &clk_ops_rcg,
660 VDD_DIG_FMAX_MAP1(LOW, 50000000),
661 CLK_INIT(blsp1_qup6_i2c_apps_clk_src.c),
662 },
663};
664
665static struct rcg_clk blsp1_qup6_spi_apps_clk_src = {
666 .cmd_rcgr_reg = BLSP1_QUP6_SPI_APPS_CMD_RCGR,
667 .set_rate = set_rate_mnd,
668 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
669 .current_freq = &rcg_dummy_freq,
670 .base = &virt_bases[GCC_BASE],
671 .c = {
672 .dbg_name = "blsp1_qup6_spi_apps_clk_src",
673 .ops = &clk_ops_rcg_mnd,
674 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
675 CLK_INIT(blsp1_qup6_spi_apps_clk_src.c),
676 },
677};
678
679static struct clk_freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = {
680 F_GCC( 3686400, gpll0, 1, 96, 15625),
681 F_GCC( 7372800, gpll0, 1, 192, 15625),
682 F_GCC( 14745600, gpll0, 1, 384, 15625),
683 F_GCC( 16000000, gpll0, 5, 2, 15),
684 F_GCC( 19200000, xo, 1, 0, 0),
685 F_GCC( 24000000, gpll0, 5, 1, 5),
686 F_GCC( 32000000, gpll0, 1, 4, 75),
687 F_GCC( 40000000, gpll0, 15, 0, 0),
688 F_GCC( 46400000, gpll0, 1, 29, 375),
689 F_GCC( 48000000, gpll0, 12.5, 0, 0),
690 F_GCC( 51200000, gpll0, 1, 32, 375),
691 F_GCC( 56000000, gpll0, 1, 7, 75),
692 F_GCC( 58982400, gpll0, 1, 1536, 15625),
693 F_GCC( 60000000, gpll0, 10, 0, 0),
694 F_END
695};
696
697static struct rcg_clk blsp1_uart1_apps_clk_src = {
698 .cmd_rcgr_reg = BLSP1_UART1_APPS_CMD_RCGR,
699 .set_rate = set_rate_mnd,
700 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
701 .current_freq = &rcg_dummy_freq,
702 .base = &virt_bases[GCC_BASE],
703 .c = {
704 .dbg_name = "blsp1_uart1_apps_clk_src",
705 .ops = &clk_ops_rcg_mnd,
706 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
707 CLK_INIT(blsp1_uart1_apps_clk_src.c),
708 },
709};
710
711static struct rcg_clk blsp1_uart2_apps_clk_src = {
712 .cmd_rcgr_reg = BLSP1_UART2_APPS_CMD_RCGR,
713 .set_rate = set_rate_mnd,
714 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
715 .current_freq = &rcg_dummy_freq,
716 .base = &virt_bases[GCC_BASE],
717 .c = {
718 .dbg_name = "blsp1_uart2_apps_clk_src",
719 .ops = &clk_ops_rcg_mnd,
720 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
721 CLK_INIT(blsp1_uart2_apps_clk_src.c),
722 },
723};
724
725static struct rcg_clk blsp1_uart3_apps_clk_src = {
726 .cmd_rcgr_reg = BLSP1_UART3_APPS_CMD_RCGR,
727 .set_rate = set_rate_mnd,
728 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
729 .current_freq = &rcg_dummy_freq,
730 .base = &virt_bases[GCC_BASE],
731 .c = {
732 .dbg_name = "blsp1_uart3_apps_clk_src",
733 .ops = &clk_ops_rcg_mnd,
734 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
735 CLK_INIT(blsp1_uart3_apps_clk_src.c),
736 },
737};
738
739static struct rcg_clk blsp1_uart4_apps_clk_src = {
740 .cmd_rcgr_reg = BLSP1_UART4_APPS_CMD_RCGR,
741 .set_rate = set_rate_mnd,
742 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
743 .current_freq = &rcg_dummy_freq,
744 .base = &virt_bases[GCC_BASE],
745 .c = {
746 .dbg_name = "blsp1_uart4_apps_clk_src",
747 .ops = &clk_ops_rcg_mnd,
748 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
749 CLK_INIT(blsp1_uart4_apps_clk_src.c),
750 },
751};
752
753static struct rcg_clk blsp1_uart5_apps_clk_src = {
754 .cmd_rcgr_reg = BLSP1_UART5_APPS_CMD_RCGR,
755 .set_rate = set_rate_mnd,
756 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
757 .current_freq = &rcg_dummy_freq,
758 .base = &virt_bases[GCC_BASE],
759 .c = {
760 .dbg_name = "blsp1_uart5_apps_clk_src",
761 .ops = &clk_ops_rcg_mnd,
762 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
763 CLK_INIT(blsp1_uart5_apps_clk_src.c),
764 },
765};
766
767static struct rcg_clk blsp1_uart6_apps_clk_src = {
768 .cmd_rcgr_reg = BLSP1_UART6_APPS_CMD_RCGR,
769 .set_rate = set_rate_mnd,
770 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
771 .current_freq = &rcg_dummy_freq,
772 .base = &virt_bases[GCC_BASE],
773 .c = {
774 .dbg_name = "blsp1_uart6_apps_clk_src",
775 .ops = &clk_ops_rcg_mnd,
776 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
777 CLK_INIT(blsp1_uart6_apps_clk_src.c),
778 },
779};
780
781static struct clk_freq_tbl ftbl_gcc_ce1_clk[] = {
782 F_GCC( 50000000, gpll0, 12, 0, 0),
783 F_GCC( 100000000, gpll0, 6, 0, 0),
784 F_END
785};
786
787static struct rcg_clk ce1_clk_src = {
788 .cmd_rcgr_reg = CE1_CMD_RCGR,
789 .set_rate = set_rate_hid,
790 .freq_tbl = ftbl_gcc_ce1_clk,
791 .current_freq = &rcg_dummy_freq,
792 .base = &virt_bases[GCC_BASE],
793 .c = {
794 .dbg_name = "ce1_clk_src",
795 .ops = &clk_ops_rcg,
796 VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000),
797 CLK_INIT(ce1_clk_src.c),
798 },
799};
800
801static struct clk_freq_tbl ftbl_gcc_gp1_3_clk[] = {
802 F_GCC( 19200000, xo, 1, 0, 0),
803 F_END
804};
805
806static struct rcg_clk gp1_clk_src = {
807 .cmd_rcgr_reg = GP1_CMD_RCGR,
808 .set_rate = set_rate_mnd,
809 .freq_tbl = ftbl_gcc_gp1_3_clk,
810 .current_freq = &rcg_dummy_freq,
811 .base = &virt_bases[GCC_BASE],
812 .c = {
813 .dbg_name = "gp1_clk_src",
814 .ops = &clk_ops_rcg_mnd,
815 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
816 CLK_INIT(gp1_clk_src.c),
817 },
818};
819
820static struct rcg_clk gp2_clk_src = {
821 .cmd_rcgr_reg = GP2_CMD_RCGR,
822 .set_rate = set_rate_mnd,
823 .freq_tbl = ftbl_gcc_gp1_3_clk,
824 .current_freq = &rcg_dummy_freq,
825 .base = &virt_bases[GCC_BASE],
826 .c = {
827 .dbg_name = "gp2_clk_src",
828 .ops = &clk_ops_rcg_mnd,
829 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
830 CLK_INIT(gp2_clk_src.c),
831 },
832};
833
834static struct rcg_clk gp3_clk_src = {
835 .cmd_rcgr_reg = GP3_CMD_RCGR,
836 .set_rate = set_rate_mnd,
837 .freq_tbl = ftbl_gcc_gp1_3_clk,
838 .current_freq = &rcg_dummy_freq,
839 .base = &virt_bases[GCC_BASE],
840 .c = {
841 .dbg_name = "gp3_clk_src",
842 .ops = &clk_ops_rcg_mnd,
843 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
844 CLK_INIT(gp3_clk_src.c),
845 },
846};
847
848static struct clk_freq_tbl ftbl_gcc_pdm2_clk[] = {
849 F_GCC( 60000000, gpll0, 10, 0, 0),
850 F_END
851};
852
853static struct rcg_clk pdm2_clk_src = {
854 .cmd_rcgr_reg = PDM2_CMD_RCGR,
855 .set_rate = set_rate_hid,
856 .freq_tbl = ftbl_gcc_pdm2_clk,
857 .current_freq = &rcg_dummy_freq,
858 .base = &virt_bases[GCC_BASE],
859 .c = {
860 .dbg_name = "pdm2_clk_src",
861 .ops = &clk_ops_rcg,
862 VDD_DIG_FMAX_MAP1(LOW, 60000000),
863 CLK_INIT(pdm2_clk_src.c),
864 },
865};
866
867static struct clk_freq_tbl ftbl_gcc_sdcc1_3_apps_clk[] = {
868 F_GCC( 144000, xo, 16, 3, 25),
869 F_GCC( 400000, xo, 12, 1, 4),
870 F_GCC( 20000000, gpll0, 15, 1, 2),
871 F_GCC( 25000000, gpll0, 12, 1, 2),
872 F_GCC( 50000000, gpll0, 12, 0, 0),
873 F_GCC( 100000000, gpll0, 6, 0, 0),
874 F_GCC( 200000000, gpll0, 3, 0, 0),
875 F_END
876};
877
878static struct rcg_clk sdcc1_apps_clk_src = {
879 .cmd_rcgr_reg = SDCC1_APPS_CMD_RCGR,
880 .set_rate = set_rate_mnd,
881 .freq_tbl = ftbl_gcc_sdcc1_3_apps_clk,
882 .current_freq = &rcg_dummy_freq,
883 .base = &virt_bases[GCC_BASE],
884 .c = {
885 .dbg_name = "sdcc1_apps_clk_src",
886 .ops = &clk_ops_rcg_mnd,
887 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
888 CLK_INIT(sdcc1_apps_clk_src.c),
889 },
890};
891
892static struct rcg_clk sdcc2_apps_clk_src = {
893 .cmd_rcgr_reg = SDCC2_APPS_CMD_RCGR,
894 .set_rate = set_rate_mnd,
895 .freq_tbl = ftbl_gcc_sdcc1_3_apps_clk,
896 .current_freq = &rcg_dummy_freq,
897 .base = &virt_bases[GCC_BASE],
898 .c = {
899 .dbg_name = "sdcc2_apps_clk_src",
900 .ops = &clk_ops_rcg_mnd,
901 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
902 CLK_INIT(sdcc2_apps_clk_src.c),
903 },
904};
905
906static struct rcg_clk sdcc3_apps_clk_src = {
907 .cmd_rcgr_reg = SDCC3_APPS_CMD_RCGR,
908 .set_rate = set_rate_mnd,
909 .freq_tbl = ftbl_gcc_sdcc1_3_apps_clk,
910 .current_freq = &rcg_dummy_freq,
911 .base = &virt_bases[GCC_BASE],
912 .c = {
913 .dbg_name = "sdcc3_apps_clk_src",
914 .ops = &clk_ops_rcg_mnd,
915 VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000),
916 CLK_INIT(sdcc3_apps_clk_src.c),
917 },
918};
919
920static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
921 F_GCC( 75000000, gpll0, 8, 0, 0),
922 F_END
923};
924
925static struct rcg_clk usb_hs_system_clk_src = {
926 .cmd_rcgr_reg = USB_HS_SYSTEM_CMD_RCGR,
927 .set_rate = set_rate_hid,
928 .freq_tbl = ftbl_gcc_usb_hs_system_clk,
929 .current_freq = &rcg_dummy_freq,
930 .base = &virt_bases[GCC_BASE],
931 .c = {
932 .dbg_name = "usb_hs_system_clk_src",
933 .ops = &clk_ops_rcg,
934 VDD_DIG_FMAX_MAP2(LOW, 37500000, NOMINAL, 75000000),
935 CLK_INIT(usb_hs_system_clk_src.c),
936 },
937};
938
939static struct clk_freq_tbl ftbl_gcc_usb_hsic_clk[] = {
940 F_HSIC( 480000000, gpll1, 0, 0, 0),
941 F_END
942};
943
944static struct rcg_clk usb_hsic_clk_src = {
945 .cmd_rcgr_reg = USB_HSIC_CMD_RCGR,
946 .set_rate = set_rate_hid,
947 .freq_tbl = ftbl_gcc_usb_hsic_clk,
948 .current_freq = &rcg_dummy_freq,
949 .base = &virt_bases[GCC_BASE],
950 .c = {
951 .dbg_name = "usb_hsic_clk_src",
952 .ops = &clk_ops_rcg,
953 VDD_DIG_FMAX_MAP1(LOW, 480000000),
954 CLK_INIT(usb_hsic_clk_src.c),
955 },
956};
957
958static struct clk_freq_tbl ftbl_gcc_usb_hsic_io_cal_clk[] = {
959 F_GCC( 9600000, xo, 2, 0, 0),
960 F_END
961};
962
963static struct rcg_clk usb_hsic_io_cal_clk_src = {
964 .cmd_rcgr_reg = USB_HSIC_IO_CAL_CMD_RCGR,
965 .set_rate = set_rate_hid,
966 .freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk,
967 .current_freq = &rcg_dummy_freq,
968 .base = &virt_bases[GCC_BASE],
969 .c = {
970 .dbg_name = "usb_hsic_io_cal_clk_src",
971 .ops = &clk_ops_rcg,
972 VDD_DIG_FMAX_MAP1(LOW, 9600000),
973 CLK_INIT(usb_hsic_io_cal_clk_src.c),
974 },
975};
976
977static struct clk_freq_tbl ftbl_gcc_usb_hsic_system_clk[] = {
978 F_GCC( 75000000, gpll0, 8, 0, 0),
979 F_END
980};
981
982static struct rcg_clk usb_hsic_system_clk_src = {
983 .cmd_rcgr_reg = USB_HSIC_SYSTEM_CMD_RCGR,
984 .set_rate = set_rate_hid,
985 .freq_tbl = ftbl_gcc_usb_hsic_system_clk,
986 .current_freq = &rcg_dummy_freq,
987 .base = &virt_bases[GCC_BASE],
988 .c = {
989 .dbg_name = "usb_hsic_system_clk_src",
990 .ops = &clk_ops_rcg,
991 VDD_DIG_FMAX_MAP2(LOW, 37500000, NOMINAL, 75000000),
992 CLK_INIT(usb_hsic_system_clk_src.c),
993 },
994};
995
996static struct local_vote_clk gcc_bam_dma_ahb_clk = {
997 .cbcr_reg = BAM_DMA_AHB_CBCR,
998 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
999 .en_mask = BIT(12),
1000 .base = &virt_bases[GCC_BASE],
1001 .c = {
1002 .dbg_name = "gcc_bam_dma_ahb_clk",
1003 .ops = &clk_ops_vote,
1004 CLK_INIT(gcc_bam_dma_ahb_clk.c),
1005 },
1006};
1007
1008static struct local_vote_clk gcc_blsp1_ahb_clk = {
1009 .cbcr_reg = BLSP1_AHB_CBCR,
1010 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1011 .en_mask = BIT(17),
1012 .base = &virt_bases[GCC_BASE],
1013 .c = {
1014 .dbg_name = "gcc_blsp1_ahb_clk",
1015 .ops = &clk_ops_vote,
1016 CLK_INIT(gcc_blsp1_ahb_clk.c),
1017 },
1018};
1019
1020static struct branch_clk gcc_blsp1_qup1_i2c_apps_clk = {
1021 .cbcr_reg = BLSP1_QUP1_I2C_APPS_CBCR,
1022 .has_sibling = 0,
1023 .base = &virt_bases[GCC_BASE],
1024 .c = {
1025 .dbg_name = "gcc_blsp1_qup1_i2c_apps_clk",
1026 .parent = &blsp1_qup1_i2c_apps_clk_src.c,
1027 .ops = &clk_ops_branch,
1028 CLK_INIT(gcc_blsp1_qup1_i2c_apps_clk.c),
1029 },
1030};
1031
1032static struct branch_clk gcc_blsp1_qup1_spi_apps_clk = {
1033 .cbcr_reg = BLSP1_QUP1_SPI_APPS_CBCR,
1034 .has_sibling = 0,
1035 .base = &virt_bases[GCC_BASE],
1036 .c = {
1037 .dbg_name = "gcc_blsp1_qup1_spi_apps_clk",
1038 .parent = &blsp1_qup1_spi_apps_clk_src.c,
1039 .ops = &clk_ops_branch,
1040 CLK_INIT(gcc_blsp1_qup1_spi_apps_clk.c),
1041 },
1042};
1043
1044static struct branch_clk gcc_blsp1_qup2_i2c_apps_clk = {
1045 .cbcr_reg = BLSP1_QUP2_I2C_APPS_CBCR,
1046 .has_sibling = 0,
1047 .base = &virt_bases[GCC_BASE],
1048 .c = {
1049 .dbg_name = "gcc_blsp1_qup2_i2c_apps_clk",
1050 .parent = &blsp1_qup2_i2c_apps_clk_src.c,
1051 .ops = &clk_ops_branch,
1052 CLK_INIT(gcc_blsp1_qup2_i2c_apps_clk.c),
1053 },
1054};
1055
1056static struct branch_clk gcc_blsp1_qup2_spi_apps_clk = {
1057 .cbcr_reg = BLSP1_QUP2_SPI_APPS_CBCR,
1058 .has_sibling = 0,
1059 .base = &virt_bases[GCC_BASE],
1060 .c = {
1061 .dbg_name = "gcc_blsp1_qup2_spi_apps_clk",
1062 .parent = &blsp1_qup2_spi_apps_clk_src.c,
1063 .ops = &clk_ops_branch,
1064 CLK_INIT(gcc_blsp1_qup2_spi_apps_clk.c),
1065 },
1066};
1067
1068static struct branch_clk gcc_blsp1_qup3_i2c_apps_clk = {
1069 .cbcr_reg = BLSP1_QUP3_I2C_APPS_CBCR,
1070 .has_sibling = 0,
1071 .base = &virt_bases[GCC_BASE],
1072 .c = {
1073 .dbg_name = "gcc_blsp1_qup3_i2c_apps_clk",
1074 .parent = &blsp1_qup3_i2c_apps_clk_src.c,
1075 .ops = &clk_ops_branch,
1076 CLK_INIT(gcc_blsp1_qup3_i2c_apps_clk.c),
1077 },
1078};
1079
1080static struct branch_clk gcc_blsp1_qup3_spi_apps_clk = {
1081 .cbcr_reg = BLSP1_QUP3_SPI_APPS_CBCR,
1082 .has_sibling = 0,
1083 .base = &virt_bases[GCC_BASE],
1084 .c = {
1085 .dbg_name = "gcc_blsp1_qup3_spi_apps_clk",
1086 .parent = &blsp1_qup3_spi_apps_clk_src.c,
1087 .ops = &clk_ops_branch,
1088 CLK_INIT(gcc_blsp1_qup3_spi_apps_clk.c),
1089 },
1090};
1091
1092static struct branch_clk gcc_blsp1_qup4_i2c_apps_clk = {
1093 .cbcr_reg = BLSP1_QUP4_I2C_APPS_CBCR,
1094 .has_sibling = 0,
1095 .base = &virt_bases[GCC_BASE],
1096 .c = {
1097 .dbg_name = "gcc_blsp1_qup4_i2c_apps_clk",
1098 .parent = &blsp1_qup4_i2c_apps_clk_src.c,
1099 .ops = &clk_ops_branch,
1100 CLK_INIT(gcc_blsp1_qup4_i2c_apps_clk.c),
1101 },
1102};
1103
1104static struct branch_clk gcc_blsp1_qup4_spi_apps_clk = {
1105 .cbcr_reg = BLSP1_QUP4_SPI_APPS_CBCR,
1106 .has_sibling = 0,
1107 .base = &virt_bases[GCC_BASE],
1108 .c = {
1109 .dbg_name = "gcc_blsp1_qup4_spi_apps_clk",
1110 .parent = &blsp1_qup4_spi_apps_clk_src.c,
1111 .ops = &clk_ops_branch,
1112 CLK_INIT(gcc_blsp1_qup4_spi_apps_clk.c),
1113 },
1114};
1115
1116static struct branch_clk gcc_blsp1_qup5_i2c_apps_clk = {
1117 .cbcr_reg = BLSP1_QUP5_I2C_APPS_CBCR,
1118 .has_sibling = 0,
1119 .base = &virt_bases[GCC_BASE],
1120 .c = {
1121 .dbg_name = "gcc_blsp1_qup5_i2c_apps_clk",
1122 .parent = &blsp1_qup5_i2c_apps_clk_src.c,
1123 .ops = &clk_ops_branch,
1124 CLK_INIT(gcc_blsp1_qup5_i2c_apps_clk.c),
1125 },
1126};
1127
1128static struct branch_clk gcc_blsp1_qup5_spi_apps_clk = {
1129 .cbcr_reg = BLSP1_QUP5_SPI_APPS_CBCR,
1130 .has_sibling = 0,
1131 .base = &virt_bases[GCC_BASE],
1132 .c = {
1133 .dbg_name = "gcc_blsp1_qup5_spi_apps_clk",
1134 .parent = &blsp1_qup5_spi_apps_clk_src.c,
1135 .ops = &clk_ops_branch,
1136 CLK_INIT(gcc_blsp1_qup5_spi_apps_clk.c),
1137 },
1138};
1139
1140static struct branch_clk gcc_blsp1_qup6_i2c_apps_clk = {
1141 .cbcr_reg = BLSP1_QUP6_I2C_APPS_CBCR,
1142 .has_sibling = 0,
1143 .base = &virt_bases[GCC_BASE],
1144 .c = {
1145 .dbg_name = "gcc_blsp1_qup6_i2c_apps_clk",
1146 .parent = &blsp1_qup6_i2c_apps_clk_src.c,
1147 .ops = &clk_ops_branch,
1148 CLK_INIT(gcc_blsp1_qup6_i2c_apps_clk.c),
1149 },
1150};
1151
1152static struct branch_clk gcc_blsp1_qup6_spi_apps_clk = {
1153 .cbcr_reg = BLSP1_QUP6_SPI_APPS_CBCR,
1154 .has_sibling = 0,
1155 .base = &virt_bases[GCC_BASE],
1156 .c = {
1157 .dbg_name = "gcc_blsp1_qup6_spi_apps_clk",
1158 .parent = &blsp1_qup6_spi_apps_clk_src.c,
1159 .ops = &clk_ops_branch,
1160 CLK_INIT(gcc_blsp1_qup6_spi_apps_clk.c),
1161 },
1162};
1163
1164static struct branch_clk gcc_blsp1_uart1_apps_clk = {
1165 .cbcr_reg = BLSP1_UART1_APPS_CBCR,
1166 .has_sibling = 0,
1167 .base = &virt_bases[GCC_BASE],
1168 .c = {
1169 .dbg_name = "gcc_blsp1_uart1_apps_clk",
1170 .parent = &blsp1_uart1_apps_clk_src.c,
1171 .ops = &clk_ops_branch,
1172 CLK_INIT(gcc_blsp1_uart1_apps_clk.c),
1173 },
1174};
1175
1176static struct branch_clk gcc_blsp1_uart2_apps_clk = {
1177 .cbcr_reg = BLSP1_UART2_APPS_CBCR,
1178 .has_sibling = 0,
1179 .base = &virt_bases[GCC_BASE],
1180 .c = {
1181 .dbg_name = "gcc_blsp1_uart2_apps_clk",
1182 .parent = &blsp1_uart2_apps_clk_src.c,
1183 .ops = &clk_ops_branch,
1184 CLK_INIT(gcc_blsp1_uart2_apps_clk.c),
1185 },
1186};
1187
1188static struct branch_clk gcc_blsp1_uart3_apps_clk = {
1189 .cbcr_reg = BLSP1_UART3_APPS_CBCR,
1190 .has_sibling = 0,
1191 .base = &virt_bases[GCC_BASE],
1192 .c = {
1193 .dbg_name = "gcc_blsp1_uart3_apps_clk",
1194 .parent = &blsp1_uart3_apps_clk_src.c,
1195 .ops = &clk_ops_branch,
1196 CLK_INIT(gcc_blsp1_uart3_apps_clk.c),
1197 },
1198};
1199
1200static struct branch_clk gcc_blsp1_uart4_apps_clk = {
1201 .cbcr_reg = BLSP1_UART4_APPS_CBCR,
1202 .has_sibling = 0,
1203 .base = &virt_bases[GCC_BASE],
1204 .c = {
1205 .dbg_name = "gcc_blsp1_uart4_apps_clk",
1206 .parent = &blsp1_uart4_apps_clk_src.c,
1207 .ops = &clk_ops_branch,
1208 CLK_INIT(gcc_blsp1_uart4_apps_clk.c),
1209 },
1210};
1211
1212static struct branch_clk gcc_blsp1_uart5_apps_clk = {
1213 .cbcr_reg = BLSP1_UART5_APPS_CBCR,
1214 .has_sibling = 0,
1215 .base = &virt_bases[GCC_BASE],
1216 .c = {
1217 .dbg_name = "gcc_blsp1_uart5_apps_clk",
1218 .parent = &blsp1_uart5_apps_clk_src.c,
1219 .ops = &clk_ops_branch,
1220 CLK_INIT(gcc_blsp1_uart5_apps_clk.c),
1221 },
1222};
1223
1224static struct branch_clk gcc_blsp1_uart6_apps_clk = {
1225 .cbcr_reg = BLSP1_UART6_APPS_CBCR,
1226 .has_sibling = 0,
1227 .base = &virt_bases[GCC_BASE],
1228 .c = {
1229 .dbg_name = "gcc_blsp1_uart6_apps_clk",
1230 .parent = &blsp1_uart6_apps_clk_src.c,
1231 .ops = &clk_ops_branch,
1232 CLK_INIT(gcc_blsp1_uart6_apps_clk.c),
1233 },
1234};
1235
1236static struct local_vote_clk gcc_boot_rom_ahb_clk = {
1237 .cbcr_reg = BOOT_ROM_AHB_CBCR,
1238 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1239 .en_mask = BIT(10),
1240 .base = &virt_bases[GCC_BASE],
1241 .c = {
1242 .dbg_name = "gcc_boot_rom_ahb_clk",
1243 .ops = &clk_ops_vote,
1244 CLK_INIT(gcc_boot_rom_ahb_clk.c),
1245 },
1246};
1247
1248static struct local_vote_clk gcc_ce1_ahb_clk = {
1249 .cbcr_reg = CE1_AHB_CBCR,
1250 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1251 .en_mask = BIT(3),
1252 .base = &virt_bases[GCC_BASE],
1253 .c = {
1254 .dbg_name = "gcc_ce1_ahb_clk",
1255 .ops = &clk_ops_vote,
1256 CLK_INIT(gcc_ce1_ahb_clk.c),
1257 },
1258};
1259
1260static struct local_vote_clk gcc_ce1_axi_clk = {
1261 .cbcr_reg = CE1_AXI_CBCR,
1262 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1263 .en_mask = BIT(4),
1264 .base = &virt_bases[GCC_BASE],
1265 .c = {
1266 .dbg_name = "gcc_ce1_axi_clk",
1267 .ops = &clk_ops_vote,
1268 CLK_INIT(gcc_ce1_axi_clk.c),
1269 },
1270};
1271
1272static struct local_vote_clk gcc_ce1_clk = {
1273 .cbcr_reg = CE1_CBCR,
1274 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1275 .en_mask = BIT(5),
1276 .base = &virt_bases[GCC_BASE],
1277 .c = {
1278 .dbg_name = "gcc_ce1_clk",
1279 .ops = &clk_ops_vote,
1280 CLK_INIT(gcc_ce1_clk.c),
1281 },
1282};
1283
1284static struct branch_clk gcc_gp1_clk = {
1285 .cbcr_reg = GP1_CBCR,
1286 .has_sibling = 0,
1287 .base = &virt_bases[GCC_BASE],
1288 .c = {
1289 .dbg_name = "gcc_gp1_clk",
1290 .parent = &gp1_clk_src.c,
1291 .ops = &clk_ops_branch,
1292 CLK_INIT(gcc_gp1_clk.c),
1293 },
1294};
1295
1296static struct branch_clk gcc_gp2_clk = {
1297 .cbcr_reg = GP2_CBCR,
1298 .has_sibling = 0,
1299 .base = &virt_bases[GCC_BASE],
1300 .c = {
1301 .dbg_name = "gcc_gp2_clk",
1302 .parent = &gp2_clk_src.c,
1303 .ops = &clk_ops_branch,
1304 CLK_INIT(gcc_gp2_clk.c),
1305 },
1306};
1307
1308static struct branch_clk gcc_gp3_clk = {
1309 .cbcr_reg = GP3_CBCR,
1310 .has_sibling = 0,
1311 .base = &virt_bases[GCC_BASE],
1312 .c = {
1313 .dbg_name = "gcc_gp3_clk",
1314 .parent = &gp3_clk_src.c,
1315 .ops = &clk_ops_branch,
1316 CLK_INIT(gcc_gp3_clk.c),
1317 },
1318};
1319
1320static struct branch_clk gcc_lpass_q6_axi_clk = {
1321 .cbcr_reg = LPASS_Q6_AXI_CBCR,
1322 .has_sibling = 1,
1323 .base = &virt_bases[GCC_BASE],
1324 .c = {
1325 .dbg_name = "gcc_lpass_q6_axi_clk",
1326 .ops = &clk_ops_branch,
1327 CLK_INIT(gcc_lpass_q6_axi_clk.c),
1328 },
1329};
1330
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1331static struct branch_clk gcc_mss_cfg_ahb_clk = {
1332 .cbcr_reg = MSS_CFG_AHB_CBCR,
1333 .has_sibling = 1,
1334 .base = &virt_bases[GCC_BASE],
1335 .c = {
1336 .dbg_name = "gcc_mss_cfg_ahb_clk",
1337 .ops = &clk_ops_branch,
1338 CLK_INIT(gcc_mss_cfg_ahb_clk.c),
1339 },
1340};
1341
1342static struct branch_clk gcc_mss_q6_bimc_axi_clk = {
1343 .cbcr_reg = MSS_Q6_BIMC_AXI_CBCR,
1344 .has_sibling = 1,
1345 .base = &virt_bases[GCC_BASE],
1346 .c = {
1347 .dbg_name = "gcc_mss_q6_bimc_axi_clk",
1348 .ops = &clk_ops_branch,
1349 CLK_INIT(gcc_mss_q6_bimc_axi_clk.c),
1350 },
1351};
1352
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1353static struct branch_clk gcc_pdm2_clk = {
1354 .cbcr_reg = PDM2_CBCR,
1355 .has_sibling = 0,
1356 .base = &virt_bases[GCC_BASE],
1357 .c = {
1358 .dbg_name = "gcc_pdm2_clk",
1359 .parent = &pdm2_clk_src.c,
1360 .ops = &clk_ops_branch,
1361 CLK_INIT(gcc_pdm2_clk.c),
1362 },
1363};
1364
1365static struct branch_clk gcc_pdm_ahb_clk = {
1366 .cbcr_reg = PDM_AHB_CBCR,
1367 .has_sibling = 1,
1368 .base = &virt_bases[GCC_BASE],
1369 .c = {
1370 .dbg_name = "gcc_pdm_ahb_clk",
1371 .ops = &clk_ops_branch,
1372 CLK_INIT(gcc_pdm_ahb_clk.c),
1373 },
1374};
1375
1376static struct branch_clk gcc_pdm_xo4_clk = {
1377 .cbcr_reg = PDM_XO4_CBCR,
1378 .has_sibling = 1,
1379 .base = &virt_bases[GCC_BASE],
1380 .c = {
1381 .dbg_name = "gcc_pdm_xo4_clk",
1382 .parent = &xo.c,
1383 .ops = &clk_ops_branch,
1384 CLK_INIT(gcc_pdm_xo4_clk.c),
1385 },
1386};
1387
1388static struct branch_clk gcc_periph_noc_ahb_clk = {
1389 .cbcr_reg = PERIPH_NOC_AHB_CBCR,
1390 .has_sibling = 1,
1391 .base = &virt_bases[GCC_BASE],
1392 .c = {
1393 .dbg_name = "gcc_periph_noc_ahb_clk",
1394 .ops = &clk_ops_branch,
1395 CLK_INIT(gcc_periph_noc_ahb_clk.c),
1396 },
1397};
1398
1399static struct local_vote_clk gcc_prng_ahb_clk = {
1400 .cbcr_reg = PRNG_AHB_CBCR,
1401 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1402 .en_mask = BIT(13),
1403 .base = &virt_bases[GCC_BASE],
1404 .c = {
1405 .dbg_name = "gcc_prng_ahb_clk",
1406 .ops = &clk_ops_vote,
1407 CLK_INIT(gcc_prng_ahb_clk.c),
1408 },
1409};
1410
1411static struct branch_clk gcc_sdcc1_ahb_clk = {
1412 .cbcr_reg = SDCC1_AHB_CBCR,
1413 .has_sibling = 1,
1414 .base = &virt_bases[GCC_BASE],
1415 .c = {
1416 .dbg_name = "gcc_sdcc1_ahb_clk",
1417 .ops = &clk_ops_branch,
1418 CLK_INIT(gcc_sdcc1_ahb_clk.c),
1419 },
1420};
1421
1422static struct branch_clk gcc_sdcc1_apps_clk = {
1423 .cbcr_reg = SDCC1_APPS_CBCR,
1424 .has_sibling = 0,
1425 .base = &virt_bases[GCC_BASE],
1426 .c = {
1427 .dbg_name = "gcc_sdcc1_apps_clk",
1428 .parent = &sdcc1_apps_clk_src.c,
1429 .ops = &clk_ops_branch,
1430 CLK_INIT(gcc_sdcc1_apps_clk.c),
1431 },
1432};
1433
1434static struct branch_clk gcc_sdcc2_ahb_clk = {
1435 .cbcr_reg = SDCC2_AHB_CBCR,
1436 .has_sibling = 1,
1437 .base = &virt_bases[GCC_BASE],
1438 .c = {
1439 .dbg_name = "gcc_sdcc2_ahb_clk",
1440 .ops = &clk_ops_branch,
1441 CLK_INIT(gcc_sdcc2_ahb_clk.c),
1442 },
1443};
1444
1445static struct branch_clk gcc_sdcc2_apps_clk = {
1446 .cbcr_reg = SDCC2_APPS_CBCR,
1447 .has_sibling = 0,
1448 .base = &virt_bases[GCC_BASE],
1449 .c = {
1450 .dbg_name = "gcc_sdcc2_apps_clk",
1451 .parent = &sdcc2_apps_clk_src.c,
1452 .ops = &clk_ops_branch,
1453 CLK_INIT(gcc_sdcc2_apps_clk.c),
1454 },
1455};
1456
1457static struct branch_clk gcc_sdcc3_ahb_clk = {
1458 .cbcr_reg = SDCC3_AHB_CBCR,
1459 .has_sibling = 1,
1460 .base = &virt_bases[GCC_BASE],
1461 .c = {
1462 .dbg_name = "gcc_sdcc3_ahb_clk",
1463 .ops = &clk_ops_branch,
1464 CLK_INIT(gcc_sdcc3_ahb_clk.c),
1465 },
1466};
1467
1468static struct branch_clk gcc_sdcc3_apps_clk = {
1469 .cbcr_reg = SDCC3_APPS_CBCR,
1470 .has_sibling = 0,
1471 .base = &virt_bases[GCC_BASE],
1472 .c = {
1473 .dbg_name = "gcc_sdcc3_apps_clk",
1474 .parent = &sdcc3_apps_clk_src.c,
1475 .ops = &clk_ops_branch,
1476 CLK_INIT(gcc_sdcc3_apps_clk.c),
1477 },
1478};
1479
1480static struct branch_clk gcc_usb2a_phy_sleep_clk = {
1481 .cbcr_reg = USB2A_PHY_SLEEP_CBCR,
1482 .has_sibling = 1,
1483 .base = &virt_bases[GCC_BASE],
1484 .c = {
1485 .dbg_name = "gcc_usb2a_phy_sleep_clk",
1486 .ops = &clk_ops_branch,
1487 CLK_INIT(gcc_usb2a_phy_sleep_clk.c),
1488 },
1489};
1490
1491static struct branch_clk gcc_usb_hs_ahb_clk = {
1492 .cbcr_reg = USB_HS_AHB_CBCR,
1493 .has_sibling = 1,
1494 .base = &virt_bases[GCC_BASE],
1495 .c = {
1496 .dbg_name = "gcc_usb_hs_ahb_clk",
1497 .ops = &clk_ops_branch,
1498 CLK_INIT(gcc_usb_hs_ahb_clk.c),
1499 },
1500};
1501
1502static struct branch_clk gcc_usb_hs_system_clk = {
1503 .cbcr_reg = USB_HS_SYSTEM_CBCR,
1504 .has_sibling = 0,
1505 .bcr_reg = USB_HS_BCR,
1506 .base = &virt_bases[GCC_BASE],
1507 .c = {
1508 .dbg_name = "gcc_usb_hs_system_clk",
1509 .parent = &usb_hs_system_clk_src.c,
1510 .ops = &clk_ops_branch,
1511 CLK_INIT(gcc_usb_hs_system_clk.c),
1512 },
1513};
1514
1515static struct branch_clk gcc_usb_hsic_ahb_clk = {
1516 .cbcr_reg = USB_HSIC_AHB_CBCR,
1517 .has_sibling = 1,
1518 .base = &virt_bases[GCC_BASE],
1519 .c = {
1520 .dbg_name = "gcc_usb_hsic_ahb_clk",
1521 .ops = &clk_ops_branch,
1522 CLK_INIT(gcc_usb_hsic_ahb_clk.c),
1523 },
1524};
1525
1526static struct branch_clk gcc_usb_hsic_clk = {
1527 .cbcr_reg = USB_HSIC_CBCR,
1528 .has_sibling = 0,
1529 .bcr_reg = USB_HS_HSIC_BCR,
1530 .base = &virt_bases[GCC_BASE],
1531 .c = {
1532 .dbg_name = "gcc_usb_hsic_clk",
1533 .parent = &usb_hsic_clk_src.c,
1534 .ops = &clk_ops_branch,
1535 CLK_INIT(gcc_usb_hsic_clk.c),
1536 },
1537};
1538
1539static struct branch_clk gcc_usb_hsic_io_cal_clk = {
1540 .cbcr_reg = USB_HSIC_IO_CAL_CBCR,
1541 .has_sibling = 0,
1542 .base = &virt_bases[GCC_BASE],
1543 .c = {
1544 .dbg_name = "gcc_usb_hsic_io_cal_clk",
1545 .parent = &usb_hsic_io_cal_clk_src.c,
1546 .ops = &clk_ops_branch,
1547 CLK_INIT(gcc_usb_hsic_io_cal_clk.c),
1548 },
1549};
1550
1551static struct branch_clk gcc_usb_hsic_system_clk = {
1552 .cbcr_reg = USB_HSIC_SYSTEM_CBCR,
1553 .has_sibling = 0,
1554 .bcr_reg = USB_HS_HSIC_BCR,
1555 .base = &virt_bases[GCC_BASE],
1556 .c = {
1557 .dbg_name = "gcc_usb_hsic_system_clk",
1558 .parent = &usb_hsic_system_clk_src.c,
1559 .ops = &clk_ops_branch,
1560 CLK_INIT(gcc_usb_hsic_system_clk.c),
1561 },
1562};
1563
1564static struct measure_mux_entry measure_mux_GCC[] = {
1565 { &gcc_periph_noc_ahb_clk.c, GCC_BASE, 0x0010 },
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1566 { &gcc_mss_cfg_ahb_clk.c, GCC_BASE, 0x0030 },
1567 { &gcc_mss_q6_bimc_axi_clk.c, GCC_BASE, 0x0031 },
1568 { &gcc_usb_hsic_ahb_clk.c, GCC_BASE, 0x0058 },
1569 { &gcc_usb_hsic_system_clk.c, GCC_BASE, 0x0059 },
1570 { &gcc_usb_hsic_clk.c, GCC_BASE, 0x005a },
1571 { &gcc_usb_hsic_io_cal_clk.c, GCC_BASE, 0x005b },
1572 { &gcc_usb_hs_system_clk.c, GCC_BASE, 0x0060 },
1573 { &gcc_usb_hs_ahb_clk.c, GCC_BASE, 0x0061 },
1574 { &gcc_usb2a_phy_sleep_clk.c, GCC_BASE, 0x0063 },
1575 { &gcc_sdcc1_apps_clk.c, GCC_BASE, 0x0068 },
1576 { &gcc_sdcc1_ahb_clk.c, GCC_BASE, 0x0069 },
1577 { &gcc_sdcc2_apps_clk.c, GCC_BASE, 0x0070 },
1578 { &gcc_sdcc2_ahb_clk.c, GCC_BASE, 0x0071 },
1579 { &gcc_sdcc3_apps_clk.c, GCC_BASE, 0x0078 },
1580 { &gcc_sdcc3_ahb_clk.c, GCC_BASE, 0x0079 },
1581 { &gcc_blsp1_ahb_clk.c, GCC_BASE, 0x0088 },
1582 { &gcc_blsp1_qup1_spi_apps_clk.c, GCC_BASE, 0x008a },
1583 { &gcc_blsp1_qup1_i2c_apps_clk.c, GCC_BASE, 0x008b },
1584 { &gcc_blsp1_uart1_apps_clk.c, GCC_BASE, 0x008c },
1585 { &gcc_blsp1_qup2_spi_apps_clk.c, GCC_BASE, 0x008e },
1586 { &gcc_blsp1_qup2_i2c_apps_clk.c, GCC_BASE, 0x0090 },
1587 { &gcc_blsp1_uart2_apps_clk.c, GCC_BASE, 0x0091 },
1588 { &gcc_blsp1_qup3_spi_apps_clk.c, GCC_BASE, 0x0093 },
1589 { &gcc_blsp1_qup3_i2c_apps_clk.c, GCC_BASE, 0x0094 },
1590 { &gcc_blsp1_uart3_apps_clk.c, GCC_BASE, 0x0095 },
1591 { &gcc_blsp1_qup4_spi_apps_clk.c, GCC_BASE, 0x0098 },
1592 { &gcc_blsp1_qup4_i2c_apps_clk.c, GCC_BASE, 0x0099 },
1593 { &gcc_blsp1_uart4_apps_clk.c, GCC_BASE, 0x009a },
1594 { &gcc_blsp1_qup5_spi_apps_clk.c, GCC_BASE, 0x009c },
1595 { &gcc_blsp1_qup5_i2c_apps_clk.c, GCC_BASE, 0x009d },
1596 { &gcc_blsp1_uart5_apps_clk.c, GCC_BASE, 0x009e },
1597 { &gcc_blsp1_qup6_spi_apps_clk.c, GCC_BASE, 0x00a1 },
1598 { &gcc_blsp1_qup6_i2c_apps_clk.c, GCC_BASE, 0x00a2 },
1599 { &gcc_blsp1_uart6_apps_clk.c, GCC_BASE, 0x00a3 },
1600 { &gcc_pdm_ahb_clk.c, GCC_BASE, 0x00d0 },
1601 { &gcc_pdm_xo4_clk.c, GCC_BASE, 0x00d1 },
1602 { &gcc_pdm2_clk.c, GCC_BASE, 0x00d2 },
1603 { &gcc_prng_ahb_clk.c, GCC_BASE, 0x00d8 },
1604 { &gcc_bam_dma_ahb_clk.c, GCC_BASE, 0x00e0 },
1605 { &gcc_boot_rom_ahb_clk.c, GCC_BASE, 0x00f8 },
1606 { &gcc_ce1_clk.c, GCC_BASE, 0x0138 },
1607 { &gcc_ce1_axi_clk.c, GCC_BASE, 0x0139 },
1608 { &gcc_ce1_ahb_clk.c, GCC_BASE, 0x013a },
1609 { &gcc_lpass_q6_axi_clk.c, GCC_BASE, 0x0160 },
1610 {&dummy_clk, N_BASES, 0x0000},
1611};
1612
1613static struct pll_vote_clk mmpll0_pll = {
1614 .en_reg = (void __iomem *)MMSS_PLL_VOTE_APCS,
1615 .en_mask = BIT(0),
1616 .status_reg = (void __iomem *)MMPLL0_PLL_STATUS,
1617 .status_mask = BIT(17),
1618 .base = &virt_bases[MMSS_BASE],
1619 .c = {
1620 .rate = 800000000,
1621 .parent = &xo.c,
1622 .dbg_name = "mmpll0_pll",
1623 .ops = &clk_ops_pll_vote,
1624 CLK_INIT(mmpll0_pll.c),
1625 },
1626};
1627
1628static struct pll_vote_clk mmpll1_pll = {
1629 .en_reg = (void __iomem *)MMSS_PLL_VOTE_APCS,
1630 .en_mask = BIT(1),
1631 .status_reg = (void __iomem *)MMPLL1_PLL_STATUS,
1632 .status_mask = BIT(17),
1633 .base = &virt_bases[MMSS_BASE],
1634 .c = {
1635 .rate = 1000000000,
1636 .parent = &xo.c,
1637 .dbg_name = "mmpll1_pll",
1638 .ops = &clk_ops_pll_vote,
1639 CLK_INIT(mmpll1_pll.c),
1640 },
1641};
1642
1643static struct clk_freq_tbl ftbl_mmss_mmssnoc_axi_clk[] = {
1644 F_MMSS( 19200000, xo, 1, 0, 0),
1645 F_MMSS( 37500000, gpll0, 16, 0, 0),
1646 F_MMSS( 50000000, gpll0, 12, 0, 0),
1647 F_MMSS( 75000000, gpll0, 8, 0, 0),
1648 F_MMSS( 100000000, gpll0, 6, 0, 0),
1649 F_MMSS( 150000000, gpll0, 4, 0, 0),
1650 F_MMSS( 200000000, mmpll0_pll, 4, 0, 0),
pfang948c93e2013-03-20 17:04:18 -0700[diff] [blame]1651 F_MMSS( 266666666, mmpll0_pll, 3, 0, 0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1652 F_END
1653};
1654
1655static struct rcg_clk axi_clk_src = {
1656 .cmd_rcgr_reg = AXI_CMD_RCGR,
1657 .set_rate = set_rate_hid,
1658 .freq_tbl = ftbl_mmss_mmssnoc_axi_clk,
1659 .current_freq = &rcg_dummy_freq,
1660 .base = &virt_bases[MMSS_BASE],
1661 .c = {
1662 .dbg_name = "axi_clk_src",
1663 .ops = &clk_ops_rcg,
1664 VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1665 266670000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1666 CLK_INIT(axi_clk_src.c),
1667 },
1668};
1669
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1670static struct clk_freq_tbl ftbl_camss_csi0_1_clk[] = {
1671 F_MMSS( 100000000, gpll0, 6, 0, 0),
1672 F_MMSS( 200000000, mmpll0_pll, 4, 0, 0),
1673 F_END
1674};
1675
1676static struct rcg_clk csi0_clk_src = {
1677 .cmd_rcgr_reg = CSI0_CMD_RCGR,
1678 .set_rate = set_rate_hid,
1679 .freq_tbl = ftbl_camss_csi0_1_clk,
1680 .current_freq = &rcg_dummy_freq,
1681 .base = &virt_bases[MMSS_BASE],
1682 .c = {
1683 .dbg_name = "csi0_clk_src",
1684 .ops = &clk_ops_rcg,
1685 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1686 CLK_INIT(csi0_clk_src.c),
1687 },
1688};
1689
1690static struct rcg_clk csi1_clk_src = {
1691 .cmd_rcgr_reg = CSI1_CMD_RCGR,
1692 .set_rate = set_rate_hid,
1693 .freq_tbl = ftbl_camss_csi0_1_clk,
1694 .current_freq = &rcg_dummy_freq,
1695 .base = &virt_bases[MMSS_BASE],
1696 .c = {
1697 .dbg_name = "csi1_clk_src",
1698 .ops = &clk_ops_rcg,
1699 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1700 CLK_INIT(csi1_clk_src.c),
1701 },
1702};
1703
1704static struct clk_freq_tbl ftbl_camss_vfe_vfe0_clk[] = {
1705 F_MMSS( 37500000, gpll0, 16, 0, 0),
1706 F_MMSS( 50000000, gpll0, 12, 0, 0),
1707 F_MMSS( 60000000, gpll0, 10, 0, 0),
1708 F_MMSS( 80000000, gpll0, 7.5, 0, 0),
1709 F_MMSS( 100000000, gpll0, 6, 0, 0),
1710 F_MMSS( 109090000, gpll0, 5.5, 0, 0),
1711 F_MMSS( 133330000, gpll0, 4.5, 0, 0),
1712 F_MMSS( 200000000, gpll0, 3, 0, 0),
1713 F_MMSS( 228570000, mmpll0_pll, 3.5, 0, 0),
1714 F_MMSS( 266670000, mmpll0_pll, 3, 0, 0),
1715 F_MMSS( 320000000, mmpll0_pll, 2.5, 0, 0),
1716 F_END
1717};
1718
1719static struct rcg_clk vfe0_clk_src = {
1720 .cmd_rcgr_reg = VFE0_CMD_RCGR,
1721 .set_rate = set_rate_hid,
1722 .freq_tbl = ftbl_camss_vfe_vfe0_clk,
1723 .current_freq = &rcg_dummy_freq,
1724 .base = &virt_bases[MMSS_BASE],
1725 .c = {
1726 .dbg_name = "vfe0_clk_src",
1727 .ops = &clk_ops_rcg,
1728 VDD_DIG_FMAX_MAP3(LOW, 133330000, NOMINAL, 266670000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1729 320000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1730 CLK_INIT(vfe0_clk_src.c),
1731 },
1732};
1733
1734static struct clk_freq_tbl ftbl_mdss_mdp_clk[] = {
1735 F_MMSS( 37500000, gpll0, 16, 0, 0),
1736 F_MMSS( 60000000, gpll0, 10, 0, 0),
1737 F_MMSS( 75000000, gpll0, 8, 0, 0),
1738 F_MMSS( 92310000, gpll0, 6.5, 0, 0),
1739 F_MMSS( 100000000, gpll0, 6, 0, 0),
1740 F_MMSS( 133330000, mmpll0_pll, 6, 0, 0),
1741 F_MMSS( 177780000, mmpll0_pll, 4.5, 0, 0),
1742 F_MMSS( 200000000, mmpll0_pll, 4, 0, 0),
1743 F_END
1744};
1745
1746static struct rcg_clk mdp_clk_src = {
1747 .cmd_rcgr_reg = MDP_CMD_RCGR,
1748 .set_rate = set_rate_hid,
1749 .freq_tbl = ftbl_mdss_mdp_clk,
1750 .current_freq = &rcg_dummy_freq,
1751 .base = &virt_bases[MMSS_BASE],
1752 .c = {
1753 .dbg_name = "mdp_clk_src",
1754 .ops = &clk_ops_rcg,
1755 VDD_DIG_FMAX_MAP3(LOW, 92310000, NOMINAL, 177780000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1756 200000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1757 CLK_INIT(mdp_clk_src.c),
1758 },
1759};
1760
1761static struct clk_freq_tbl ftbl_camss_jpeg_jpeg0_clk[] = {
1762 F_MMSS( 75000000, gpll0, 8, 0, 0),
1763 F_MMSS( 133330000, gpll0, 4.5, 0, 0),
1764 F_MMSS( 200000000, gpll0, 3, 0, 0),
1765 F_MMSS( 228570000, mmpll0_pll, 3.5, 0, 0),
1766 F_MMSS( 266670000, mmpll0_pll, 3, 0, 0),
1767 F_MMSS( 320000000, mmpll0_pll, 2.5, 0, 0),
1768 F_END
1769};
1770
1771static struct rcg_clk jpeg0_clk_src = {
1772 .cmd_rcgr_reg = JPEG0_CMD_RCGR,
1773 .set_rate = set_rate_hid,
1774 .freq_tbl = ftbl_camss_jpeg_jpeg0_clk,
1775 .current_freq = &rcg_dummy_freq,
1776 .base = &virt_bases[MMSS_BASE],
1777 .c = {
1778 .dbg_name = "jpeg0_clk_src",
1779 .ops = &clk_ops_rcg,
1780 VDD_DIG_FMAX_MAP3(LOW, 133330000, NOMINAL, 266670000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1781 320000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1782 CLK_INIT(jpeg0_clk_src.c),
1783 },
1784};
1785
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]1786static struct branch_clk mdss_ahb_clk;
1787static struct clk dsipll0_byte_clk_src = {
1788 .depends = &mdss_ahb_clk.c,
1789 .parent = &xo.c,
1790 .dbg_name = "dsipll0_byte_clk_src",
1791 .ops = &clk_ops_dsi_byte_pll,
1792 CLK_INIT(dsipll0_byte_clk_src),
1793};
1794
1795static struct clk dsipll0_pixel_clk_src = {
1796 .depends = &mdss_ahb_clk.c,
1797 .parent = &xo.c,
1798 .dbg_name = "dsipll0_pixel_clk_src",
1799 .ops = &clk_ops_dsi_pixel_pll,
1800 CLK_INIT(dsipll0_pixel_clk_src),
1801};
1802
Vikram Mulukutlaae13f3c2013-03-20 18:03:29 -0700[diff] [blame]1803static struct clk_freq_tbl pixel_freq_tbl[] = {
1804 {
1805 .src_clk = &dsipll0_pixel_clk_src,
1806 .div_src_val = BVAL(10, 8, dsipll0_pixel_mm_source_val),
1807 },
1808 F_END
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1809};
1810
1811static struct rcg_clk pclk0_clk_src = {
1812 .cmd_rcgr_reg = PCLK0_CMD_RCGR,
Vikram Mulukutlaae13f3c2013-03-20 18:03:29 -0700[diff] [blame]1813 .current_freq = pixel_freq_tbl,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1814 .base = &virt_bases[MMSS_BASE],
1815 .c = {
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]1816 .parent = &dsipll0_pixel_clk_src,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1817 .dbg_name = "pclk0_clk_src",
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]1818 .ops = &clk_ops_pixel,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1819 VDD_DIG_FMAX_MAP2(LOW, 83330000, NOMINAL, 166670000),
1820 CLK_INIT(pclk0_clk_src.c),
1821 },
1822};
1823
1824static struct clk_freq_tbl ftbl_venus0_vcodec0_clk[] = {
1825 F_MMSS( 66700000, gpll0, 9, 0, 0),
1826 F_MMSS( 100000000, gpll0, 6, 0, 0),
1827 F_MMSS( 133330000, mmpll0_pll, 6, 0, 0),
Patrick Daly4f832432013-02-26 12:40:49 -0800[diff] [blame]1828 F_MMSS( 160000000, mmpll0_pll, 5, 0, 0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1829 F_END
1830};
1831
1832static struct rcg_clk vcodec0_clk_src = {
1833 .cmd_rcgr_reg = VCODEC0_CMD_RCGR,
1834 .set_rate = set_rate_mnd,
1835 .freq_tbl = ftbl_venus0_vcodec0_clk,
1836 .current_freq = &rcg_dummy_freq,
1837 .base = &virt_bases[MMSS_BASE],
1838 .c = {
1839 .dbg_name = "vcodec0_clk_src",
1840 .ops = &clk_ops_rcg_mnd,
1841 VDD_DIG_FMAX_MAP3(LOW, 66670000, NOMINAL, 133330000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1842 160000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1843 CLK_INIT(vcodec0_clk_src.c),
1844 },
1845};
1846
1847static struct clk_freq_tbl ftbl_camss_cci_cci_clk[] = {
1848 F_MMSS( 19200000, xo, 1, 0, 0),
1849 F_END
1850};
1851
1852static struct rcg_clk cci_clk_src = {
1853 .cmd_rcgr_reg = CCI_CMD_RCGR,
1854 .set_rate = set_rate_mnd,
1855 .freq_tbl = ftbl_camss_cci_cci_clk,
1856 .current_freq = &rcg_dummy_freq,
1857 .base = &virt_bases[MMSS_BASE],
1858 .c = {
1859 .dbg_name = "cci_clk_src",
1860 .ops = &clk_ops_rcg_mnd,
1861 VDD_DIG_FMAX_MAP2(LOW, 20000000, NOMINAL, 40000000),
1862 CLK_INIT(cci_clk_src.c),
1863 },
1864};
1865
1866static struct clk_freq_tbl ftbl_camss_gp0_1_clk[] = {
1867 F_MMSS( 10000, xo, 16, 1, 120),
1868 F_MMSS( 24000, xo, 16, 1, 50),
1869 F_MMSS( 6000000, gpll0, 10, 1, 10),
1870 F_MMSS( 12000000, gpll0, 10, 1, 5),
1871 F_MMSS( 13000000, gpll0, 4, 13, 150),
1872 F_MMSS( 24000000, gpll0, 5, 1, 5),
1873 F_END
1874};
1875
1876static struct rcg_clk mmss_gp0_clk_src = {
1877 .cmd_rcgr_reg = MMSS_GP0_CMD_RCGR,
1878 .set_rate = set_rate_mnd,
1879 .freq_tbl = ftbl_camss_gp0_1_clk,
1880 .current_freq = &rcg_dummy_freq,
1881 .base = &virt_bases[MMSS_BASE],
1882 .c = {
1883 .dbg_name = "mmss_gp0_clk_src",
1884 .ops = &clk_ops_rcg_mnd,
1885 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1886 CLK_INIT(mmss_gp0_clk_src.c),
1887 },
1888};
1889
1890static struct rcg_clk mmss_gp1_clk_src = {
1891 .cmd_rcgr_reg = MMSS_GP1_CMD_RCGR,
1892 .set_rate = set_rate_mnd,
1893 .freq_tbl = ftbl_camss_gp0_1_clk,
1894 .current_freq = &rcg_dummy_freq,
1895 .base = &virt_bases[MMSS_BASE],
1896 .c = {
1897 .dbg_name = "mmss_gp1_clk_src",
1898 .ops = &clk_ops_rcg_mnd,
1899 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1900 CLK_INIT(mmss_gp1_clk_src.c),
1901 },
1902};
1903
1904static struct clk_freq_tbl ftbl_camss_mclk0_1_clk[] = {
Patrick Daly42d2b7a2013-03-07 17:12:33 -0800[diff] [blame]1905 F_MMSS( 19200000, xo, 1, 0, 0),
1906 F_MMSS( 24000000, gpll0, 5, 1, 5),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1907 F_MMSS( 66670000, gpll0, 9, 0, 0),
1908 F_END
1909};
1910
1911static struct rcg_clk mclk0_clk_src = {
1912 .cmd_rcgr_reg = MCLK0_CMD_RCGR,
1913 .set_rate = set_rate_mnd,
1914 .freq_tbl = ftbl_camss_mclk0_1_clk,
1915 .current_freq = &rcg_dummy_freq,
1916 .base = &virt_bases[MMSS_BASE],
1917 .c = {
1918 .dbg_name = "mclk0_clk_src",
1919 .ops = &clk_ops_rcg_mnd,
1920 VDD_DIG_FMAX_MAP1(LOW, 66670000),
1921 CLK_INIT(mclk0_clk_src.c),
1922 },
1923};
1924
1925static struct rcg_clk mclk1_clk_src = {
1926 .cmd_rcgr_reg = MCLK1_CMD_RCGR,
1927 .set_rate = set_rate_mnd,
1928 .freq_tbl = ftbl_camss_mclk0_1_clk,
1929 .current_freq = &rcg_dummy_freq,
1930 .base = &virt_bases[MMSS_BASE],
1931 .c = {
1932 .dbg_name = "mclk1_clk_src",
1933 .ops = &clk_ops_rcg_mnd,
1934 VDD_DIG_FMAX_MAP1(LOW, 66670000),
1935 CLK_INIT(mclk1_clk_src.c),
1936 },
1937};
1938
1939static struct clk_freq_tbl ftbl_camss_phy0_1_csi0_1phytimer_clk[] = {
1940 F_MMSS( 100000000, gpll0, 6, 0, 0),
1941 F_MMSS( 200000000, mmpll0_pll, 4, 0, 0),
1942 F_END
1943};
1944
1945static struct rcg_clk csi0phytimer_clk_src = {
1946 .cmd_rcgr_reg = CSI0PHYTIMER_CMD_RCGR,
1947 .set_rate = set_rate_hid,
1948 .freq_tbl = ftbl_camss_phy0_1_csi0_1phytimer_clk,
1949 .current_freq = &rcg_dummy_freq,
1950 .base = &virt_bases[MMSS_BASE],
1951 .c = {
1952 .dbg_name = "csi0phytimer_clk_src",
1953 .ops = &clk_ops_rcg,
1954 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1955 CLK_INIT(csi0phytimer_clk_src.c),
1956 },
1957};
1958
1959static struct rcg_clk csi1phytimer_clk_src = {
1960 .cmd_rcgr_reg = CSI1PHYTIMER_CMD_RCGR,
1961 .set_rate = set_rate_hid,
1962 .freq_tbl = ftbl_camss_phy0_1_csi0_1phytimer_clk,
1963 .current_freq = &rcg_dummy_freq,
1964 .base = &virt_bases[MMSS_BASE],
1965 .c = {
1966 .dbg_name = "csi1phytimer_clk_src",
1967 .ops = &clk_ops_rcg,
1968 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1969 CLK_INIT(csi1phytimer_clk_src.c),
1970 },
1971};
1972
1973static struct clk_freq_tbl ftbl_camss_vfe_cpp_clk[] = {
1974 F_MMSS( 133330000, gpll0, 4.5, 0, 0),
1975 F_MMSS( 266670000, mmpll0_pll, 3, 0, 0),
1976 F_MMSS( 320000000, mmpll0_pll, 2.5, 0, 0),
1977 F_END
1978};
1979
1980static struct rcg_clk cpp_clk_src = {
1981 .cmd_rcgr_reg = CPP_CMD_RCGR,
1982 .set_rate = set_rate_hid,
1983 .freq_tbl = ftbl_camss_vfe_cpp_clk,
1984 .current_freq = &rcg_dummy_freq,
1985 .base = &virt_bases[MMSS_BASE],
1986 .c = {
1987 .dbg_name = "cpp_clk_src",
1988 .ops = &clk_ops_rcg,
1989 VDD_DIG_FMAX_MAP3(LOW, 133330000, NOMINAL, 266670000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1990 320000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1991 CLK_INIT(cpp_clk_src.c),
1992 },
1993};
1994
Vikram Mulukutlaae13f3c2013-03-20 18:03:29 -0700[diff] [blame]1995static struct clk_freq_tbl byte_freq_tbl[] = {
1996 {
1997 .src_clk = &dsipll0_byte_clk_src,
1998 .div_src_val = BVAL(10, 8, dsipll0_byte_mm_source_val),
1999 },
2000 F_END
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2001};
2002
2003static struct rcg_clk byte0_clk_src = {
2004 .cmd_rcgr_reg = BYTE0_CMD_RCGR,
Vikram Mulukutlaae13f3c2013-03-20 18:03:29 -0700[diff] [blame]2005 .current_freq = byte_freq_tbl,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2006 .base = &virt_bases[MMSS_BASE],
2007 .c = {
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]2008 .parent = &dsipll0_byte_clk_src,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2009 .dbg_name = "byte0_clk_src",
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]2010 .ops = &clk_ops_byte,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2011 VDD_DIG_FMAX_MAP2(LOW, 62500000, NOMINAL, 125000000),
2012 CLK_INIT(byte0_clk_src.c),
2013 },
2014};
2015
2016static struct clk_freq_tbl ftbl_mdss_esc0_clk[] = {
2017 F_MDSS( 19200000, xo, 1, 0, 0),
2018 F_END
2019};
2020
2021static struct rcg_clk esc0_clk_src = {
2022 .cmd_rcgr_reg = ESC0_CMD_RCGR,
2023 .set_rate = set_rate_hid,
2024 .freq_tbl = ftbl_mdss_esc0_clk,
2025 .current_freq = &rcg_dummy_freq,
2026 .base = &virt_bases[MMSS_BASE],
2027 .c = {
2028 .dbg_name = "esc0_clk_src",
2029 .ops = &clk_ops_rcg,
2030 VDD_DIG_FMAX_MAP2(LOW, 20000000, NOMINAL, 40000000),
2031 CLK_INIT(esc0_clk_src.c),
2032 },
2033};
2034
2035static struct clk_freq_tbl ftbl_mdss_vsync_clk[] = {
2036 F_MDSS( 19200000, xo, 1, 0, 0),
2037 F_END
2038};
2039
2040static struct rcg_clk vsync_clk_src = {
2041 .cmd_rcgr_reg = VSYNC_CMD_RCGR,
2042 .set_rate = set_rate_hid,
2043 .freq_tbl = ftbl_mdss_vsync_clk,
2044 .current_freq = &rcg_dummy_freq,
2045 .base = &virt_bases[MMSS_BASE],
2046 .c = {
2047 .dbg_name = "vsync_clk_src",
2048 .ops = &clk_ops_rcg,
2049 VDD_DIG_FMAX_MAP2(LOW, 20000000, NOMINAL, 40000000),
2050 CLK_INIT(vsync_clk_src.c),
2051 },
2052};
2053
2054static struct branch_clk camss_cci_cci_ahb_clk = {
2055 .cbcr_reg = CAMSS_CCI_CCI_AHB_CBCR,
2056 .has_sibling = 1,
2057 .base = &virt_bases[MMSS_BASE],
2058 .c = {
2059 .dbg_name = "camss_cci_cci_ahb_clk",
2060 .ops = &clk_ops_branch,
2061 CLK_INIT(camss_cci_cci_ahb_clk.c),
2062 },
2063};
2064
2065static struct branch_clk camss_cci_cci_clk = {
2066 .cbcr_reg = CAMSS_CCI_CCI_CBCR,
2067 .has_sibling = 0,
2068 .base = &virt_bases[MMSS_BASE],
2069 .c = {
2070 .dbg_name = "camss_cci_cci_clk",
2071 .parent = &cci_clk_src.c,
2072 .ops = &clk_ops_branch,
2073 CLK_INIT(camss_cci_cci_clk.c),
2074 },
2075};
2076
2077static struct branch_clk camss_csi0_ahb_clk = {
2078 .cbcr_reg = CAMSS_CSI0_AHB_CBCR,
2079 .has_sibling = 1,
2080 .base = &virt_bases[MMSS_BASE],
2081 .c = {
2082 .dbg_name = "camss_csi0_ahb_clk",
2083 .ops = &clk_ops_branch,
2084 CLK_INIT(camss_csi0_ahb_clk.c),
2085 },
2086};
2087
2088static struct branch_clk camss_csi0_clk = {
2089 .cbcr_reg = CAMSS_CSI0_CBCR,
2090 .has_sibling = 1,
2091 .base = &virt_bases[MMSS_BASE],
2092 .c = {
2093 .dbg_name = "camss_csi0_clk",
2094 .parent = &csi0_clk_src.c,
2095 .ops = &clk_ops_branch,
2096 CLK_INIT(camss_csi0_clk.c),
2097 },
2098};
2099
2100static struct branch_clk camss_csi0phy_clk = {
2101 .cbcr_reg = CAMSS_CSI0PHY_CBCR,
2102 .has_sibling = 1,
2103 .base = &virt_bases[MMSS_BASE],
2104 .c = {
2105 .dbg_name = "camss_csi0phy_clk",
2106 .parent = &csi0_clk_src.c,
2107 .ops = &clk_ops_branch,
2108 CLK_INIT(camss_csi0phy_clk.c),
2109 },
2110};
2111
2112static struct branch_clk camss_csi0pix_clk = {
2113 .cbcr_reg = CAMSS_CSI0PIX_CBCR,
2114 .has_sibling = 1,
2115 .base = &virt_bases[MMSS_BASE],
2116 .c = {
2117 .dbg_name = "camss_csi0pix_clk",
2118 .parent = &csi0_clk_src.c,
2119 .ops = &clk_ops_branch,
2120 CLK_INIT(camss_csi0pix_clk.c),
2121 },
2122};
2123
2124static struct branch_clk camss_csi0rdi_clk = {
2125 .cbcr_reg = CAMSS_CSI0RDI_CBCR,
2126 .has_sibling = 1,
2127 .base = &virt_bases[MMSS_BASE],
2128 .c = {
2129 .dbg_name = "camss_csi0rdi_clk",
2130 .parent = &csi0_clk_src.c,
2131 .ops = &clk_ops_branch,
2132 CLK_INIT(camss_csi0rdi_clk.c),
2133 },
2134};
2135
2136static struct branch_clk camss_csi1_ahb_clk = {
2137 .cbcr_reg = CAMSS_CSI1_AHB_CBCR,
2138 .has_sibling = 1,
2139 .base = &virt_bases[MMSS_BASE],
2140 .c = {
2141 .dbg_name = "camss_csi1_ahb_clk",
2142 .ops = &clk_ops_branch,
2143 CLK_INIT(camss_csi1_ahb_clk.c),
2144 },
2145};
2146
2147static struct branch_clk camss_csi1_clk = {
2148 .cbcr_reg = CAMSS_CSI1_CBCR,
2149 .has_sibling = 1,
2150 .base = &virt_bases[MMSS_BASE],
2151 .c = {
2152 .dbg_name = "camss_csi1_clk",
2153 .parent = &csi1_clk_src.c,
2154 .ops = &clk_ops_branch,
2155 CLK_INIT(camss_csi1_clk.c),
2156 },
2157};
2158
2159static struct branch_clk camss_csi1phy_clk = {
2160 .cbcr_reg = CAMSS_CSI1PHY_CBCR,
2161 .has_sibling = 1,
2162 .base = &virt_bases[MMSS_BASE],
2163 .c = {
2164 .dbg_name = "camss_csi1phy_clk",
2165 .parent = &csi1_clk_src.c,
2166 .ops = &clk_ops_branch,
2167 CLK_INIT(camss_csi1phy_clk.c),
2168 },
2169};
2170
2171static struct branch_clk camss_csi1pix_clk = {
2172 .cbcr_reg = CAMSS_CSI1PIX_CBCR,
2173 .has_sibling = 1,
2174 .base = &virt_bases[MMSS_BASE],
2175 .c = {
2176 .dbg_name = "camss_csi1pix_clk",
2177 .parent = &csi1_clk_src.c,
2178 .ops = &clk_ops_branch,
2179 CLK_INIT(camss_csi1pix_clk.c),
2180 },
2181};
2182
2183static struct branch_clk camss_csi1rdi_clk = {
2184 .cbcr_reg = CAMSS_CSI1RDI_CBCR,
2185 .has_sibling = 1,
2186 .base = &virt_bases[MMSS_BASE],
2187 .c = {
2188 .dbg_name = "camss_csi1rdi_clk",
2189 .parent = &csi1_clk_src.c,
2190 .ops = &clk_ops_branch,
2191 CLK_INIT(camss_csi1rdi_clk.c),
2192 },
2193};
2194
2195static struct branch_clk camss_csi_vfe0_clk = {
2196 .cbcr_reg = CAMSS_CSI_VFE0_CBCR,
2197 .has_sibling = 1,
2198 .base = &virt_bases[MMSS_BASE],
2199 .c = {
2200 .dbg_name = "camss_csi_vfe0_clk",
2201 .parent = &vfe0_clk_src.c,
2202 .ops = &clk_ops_branch,
2203 CLK_INIT(camss_csi_vfe0_clk.c),
2204 },
2205};
2206
2207static struct branch_clk camss_gp0_clk = {
2208 .cbcr_reg = CAMSS_GP0_CBCR,
2209 .has_sibling = 0,
2210 .base = &virt_bases[MMSS_BASE],
2211 .c = {
2212 .dbg_name = "camss_gp0_clk",
2213 .parent = &mmss_gp0_clk_src.c,
2214 .ops = &clk_ops_branch,
2215 CLK_INIT(camss_gp0_clk.c),
2216 },
2217};
2218
2219static struct branch_clk camss_gp1_clk = {
2220 .cbcr_reg = CAMSS_GP1_CBCR,
2221 .has_sibling = 0,
2222 .base = &virt_bases[MMSS_BASE],
2223 .c = {
2224 .dbg_name = "camss_gp1_clk",
2225 .parent = &mmss_gp1_clk_src.c,
2226 .ops = &clk_ops_branch,
2227 CLK_INIT(camss_gp1_clk.c),
2228 },
2229};
2230
2231static struct branch_clk camss_ispif_ahb_clk = {
2232 .cbcr_reg = CAMSS_ISPIF_AHB_CBCR,
2233 .has_sibling = 1,
2234 .base = &virt_bases[MMSS_BASE],
2235 .c = {
2236 .dbg_name = "camss_ispif_ahb_clk",
2237 .ops = &clk_ops_branch,
2238 CLK_INIT(camss_ispif_ahb_clk.c),
2239 },
2240};
2241
2242static struct branch_clk camss_jpeg_jpeg0_clk = {
2243 .cbcr_reg = CAMSS_JPEG_JPEG0_CBCR,
2244 .has_sibling = 0,
2245 .base = &virt_bases[MMSS_BASE],
2246 .c = {
2247 .dbg_name = "camss_jpeg_jpeg0_clk",
2248 .parent = &jpeg0_clk_src.c,
2249 .ops = &clk_ops_branch,
2250 CLK_INIT(camss_jpeg_jpeg0_clk.c),
2251 },
2252};
2253
2254static struct branch_clk camss_jpeg_jpeg_ahb_clk = {
2255 .cbcr_reg = CAMSS_JPEG_JPEG_AHB_CBCR,
2256 .has_sibling = 1,
2257 .base = &virt_bases[MMSS_BASE],
2258 .c = {
2259 .dbg_name = "camss_jpeg_jpeg_ahb_clk",
2260 .ops = &clk_ops_branch,
2261 CLK_INIT(camss_jpeg_jpeg_ahb_clk.c),
2262 },
2263};
2264
2265static struct branch_clk camss_jpeg_jpeg_axi_clk = {
2266 .cbcr_reg = CAMSS_JPEG_JPEG_AXI_CBCR,
2267 .has_sibling = 1,
2268 .base = &virt_bases[MMSS_BASE],
2269 .c = {
2270 .dbg_name = "camss_jpeg_jpeg_axi_clk",
2271 .parent = &axi_clk_src.c,
2272 .ops = &clk_ops_branch,
2273 CLK_INIT(camss_jpeg_jpeg_axi_clk.c),
2274 },
2275};
2276
2277static struct branch_clk camss_mclk0_clk = {
2278 .cbcr_reg = CAMSS_MCLK0_CBCR,
2279 .has_sibling = 0,
2280 .base = &virt_bases[MMSS_BASE],
2281 .c = {
2282 .dbg_name = "camss_mclk0_clk",
2283 .parent = &mclk0_clk_src.c,
2284 .ops = &clk_ops_branch,
2285 CLK_INIT(camss_mclk0_clk.c),
2286 },
2287};
2288
2289static struct branch_clk camss_mclk1_clk = {
2290 .cbcr_reg = CAMSS_MCLK1_CBCR,
2291 .has_sibling = 0,
2292 .base = &virt_bases[MMSS_BASE],
2293 .c = {
2294 .dbg_name = "camss_mclk1_clk",
2295 .parent = &mclk1_clk_src.c,
2296 .ops = &clk_ops_branch,
2297 CLK_INIT(camss_mclk1_clk.c),
2298 },
2299};
2300
2301static struct branch_clk camss_micro_ahb_clk = {
2302 .cbcr_reg = CAMSS_MICRO_AHB_CBCR,
2303 .has_sibling = 1,
2304 .base = &virt_bases[MMSS_BASE],
2305 .c = {
2306 .dbg_name = "camss_micro_ahb_clk",
2307 .ops = &clk_ops_branch,
2308 CLK_INIT(camss_micro_ahb_clk.c),
2309 },
2310};
2311
2312static struct branch_clk camss_phy0_csi0phytimer_clk = {
2313 .cbcr_reg = CAMSS_PHY0_CSI0PHYTIMER_CBCR,
2314 .has_sibling = 0,
2315 .base = &virt_bases[MMSS_BASE],
2316 .c = {
2317 .dbg_name = "camss_phy0_csi0phytimer_clk",
2318 .parent = &csi0phytimer_clk_src.c,
2319 .ops = &clk_ops_branch,
2320 CLK_INIT(camss_phy0_csi0phytimer_clk.c),
2321 },
2322};
2323
2324static struct branch_clk camss_phy1_csi1phytimer_clk = {
2325 .cbcr_reg = CAMSS_PHY1_CSI1PHYTIMER_CBCR,
2326 .has_sibling = 0,
2327 .base = &virt_bases[MMSS_BASE],
2328 .c = {
2329 .dbg_name = "camss_phy1_csi1phytimer_clk",
2330 .parent = &csi1phytimer_clk_src.c,
2331 .ops = &clk_ops_branch,
2332 CLK_INIT(camss_phy1_csi1phytimer_clk.c),
2333 },
2334};
2335
2336static struct branch_clk camss_top_ahb_clk = {
2337 .cbcr_reg = CAMSS_TOP_AHB_CBCR,
2338 .has_sibling = 1,
2339 .base = &virt_bases[MMSS_BASE],
2340 .c = {
2341 .dbg_name = "camss_top_ahb_clk",
2342 .ops = &clk_ops_branch,
2343 CLK_INIT(camss_top_ahb_clk.c),
2344 },
2345};
2346
2347static struct branch_clk camss_vfe_cpp_ahb_clk = {
2348 .cbcr_reg = CAMSS_VFE_CPP_AHB_CBCR,
2349 .has_sibling = 1,
2350 .base = &virt_bases[MMSS_BASE],
2351 .c = {
2352 .dbg_name = "camss_vfe_cpp_ahb_clk",
2353 .ops = &clk_ops_branch,
2354 CLK_INIT(camss_vfe_cpp_ahb_clk.c),
2355 },
2356};
2357
2358static struct branch_clk camss_vfe_cpp_clk = {
2359 .cbcr_reg = CAMSS_VFE_CPP_CBCR,
2360 .has_sibling = 0,
2361 .base = &virt_bases[MMSS_BASE],
2362 .c = {
2363 .dbg_name = "camss_vfe_cpp_clk",
2364 .parent = &cpp_clk_src.c,
2365 .ops = &clk_ops_branch,
2366 CLK_INIT(camss_vfe_cpp_clk.c),
2367 },
2368};
2369
2370static struct branch_clk camss_vfe_vfe0_clk = {
2371 .cbcr_reg = CAMSS_VFE_VFE0_CBCR,
2372 .has_sibling = 1,
2373 .base = &virt_bases[MMSS_BASE],
2374 .c = {
2375 .dbg_name = "camss_vfe_vfe0_clk",
2376 .parent = &vfe0_clk_src.c,
2377 .ops = &clk_ops_branch,
2378 CLK_INIT(camss_vfe_vfe0_clk.c),
2379 },
2380};
2381
2382static struct branch_clk camss_vfe_vfe_ahb_clk = {
2383 .cbcr_reg = CAMSS_VFE_VFE_AHB_CBCR,
2384 .has_sibling = 1,
2385 .base = &virt_bases[MMSS_BASE],
2386 .c = {
2387 .dbg_name = "camss_vfe_vfe_ahb_clk",
2388 .ops = &clk_ops_branch,
2389 CLK_INIT(camss_vfe_vfe_ahb_clk.c),
2390 },
2391};
2392
2393static struct branch_clk camss_vfe_vfe_axi_clk = {
2394 .cbcr_reg = CAMSS_VFE_VFE_AXI_CBCR,
2395 .has_sibling = 1,
2396 .base = &virt_bases[MMSS_BASE],
2397 .c = {
2398 .dbg_name = "camss_vfe_vfe_axi_clk",
2399 .parent = &axi_clk_src.c,
2400 .ops = &clk_ops_branch,
2401 CLK_INIT(camss_vfe_vfe_axi_clk.c),
2402 },
2403};
2404
2405static struct branch_clk mdss_ahb_clk = {
2406 .cbcr_reg = MDSS_AHB_CBCR,
2407 .has_sibling = 1,
2408 .base = &virt_bases[MMSS_BASE],
2409 .c = {
2410 .dbg_name = "mdss_ahb_clk",
2411 .ops = &clk_ops_branch,
2412 CLK_INIT(mdss_ahb_clk.c),
2413 },
2414};
2415
2416static struct branch_clk mdss_axi_clk = {
2417 .cbcr_reg = MDSS_AXI_CBCR,
2418 .has_sibling = 1,
2419 .base = &virt_bases[MMSS_BASE],
2420 .c = {
2421 .dbg_name = "mdss_axi_clk",
2422 .parent = &axi_clk_src.c,
2423 .ops = &clk_ops_branch,
2424 CLK_INIT(mdss_axi_clk.c),
2425 },
2426};
2427
2428static struct branch_clk mdss_byte0_clk = {
2429 .cbcr_reg = MDSS_BYTE0_CBCR,
2430 .has_sibling = 0,
2431 .base = &virt_bases[MMSS_BASE],
2432 .c = {
2433 .dbg_name = "mdss_byte0_clk",
2434 .parent = &byte0_clk_src.c,
2435 .ops = &clk_ops_branch,
2436 CLK_INIT(mdss_byte0_clk.c),
2437 },
2438};
2439
2440static struct branch_clk mdss_esc0_clk = {
2441 .cbcr_reg = MDSS_ESC0_CBCR,
2442 .has_sibling = 0,
2443 .base = &virt_bases[MMSS_BASE],
2444 .c = {
2445 .dbg_name = "mdss_esc0_clk",
2446 .parent = &esc0_clk_src.c,
2447 .ops = &clk_ops_branch,
2448 CLK_INIT(mdss_esc0_clk.c),
2449 },
2450};
2451
2452static struct branch_clk mdss_mdp_clk = {
2453 .cbcr_reg = MDSS_MDP_CBCR,
2454 .has_sibling = 1,
2455 .base = &virt_bases[MMSS_BASE],
2456 .c = {
2457 .dbg_name = "mdss_mdp_clk",
2458 .parent = &mdp_clk_src.c,
2459 .ops = &clk_ops_branch,
2460 CLK_INIT(mdss_mdp_clk.c),
2461 },
2462};
2463
2464static struct branch_clk mdss_mdp_lut_clk = {
2465 .cbcr_reg = MDSS_MDP_LUT_CBCR,
2466 .has_sibling = 1,
2467 .base = &virt_bases[MMSS_BASE],
2468 .c = {
2469 .dbg_name = "mdss_mdp_lut_clk",
2470 .parent = &mdp_clk_src.c,
2471 .ops = &clk_ops_branch,
2472 CLK_INIT(mdss_mdp_lut_clk.c),
2473 },
2474};
2475
2476static struct branch_clk mdss_pclk0_clk = {
2477 .cbcr_reg = MDSS_PCLK0_CBCR,
2478 .has_sibling = 0,
2479 .base = &virt_bases[MMSS_BASE],
2480 .c = {
2481 .dbg_name = "mdss_pclk0_clk",
2482 .parent = &pclk0_clk_src.c,
2483 .ops = &clk_ops_branch,
2484 CLK_INIT(mdss_pclk0_clk.c),
2485 },
2486};
2487
2488static struct branch_clk mdss_vsync_clk = {
2489 .cbcr_reg = MDSS_VSYNC_CBCR,
2490 .has_sibling = 0,
2491 .base = &virt_bases[MMSS_BASE],
2492 .c = {
2493 .dbg_name = "mdss_vsync_clk",
2494 .parent = &vsync_clk_src.c,
2495 .ops = &clk_ops_branch,
2496 CLK_INIT(mdss_vsync_clk.c),
2497 },
2498};
2499
2500static struct branch_clk mmss_misc_ahb_clk = {
2501 .cbcr_reg = MMSS_MISC_AHB_CBCR,
2502 .has_sibling = 1,
2503 .base = &virt_bases[MMSS_BASE],
2504 .c = {
2505 .dbg_name = "mmss_misc_ahb_clk",
2506 .ops = &clk_ops_branch,
2507 CLK_INIT(mmss_misc_ahb_clk.c),
2508 },
2509};
2510
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2511static struct branch_clk mmss_mmssnoc_bto_ahb_clk = {
2512 .cbcr_reg = MMSS_MMSSNOC_BTO_AHB_CBCR,
2513 .has_sibling = 1,
2514 .base = &virt_bases[MMSS_BASE],
2515 .c = {
2516 .dbg_name = "mmss_mmssnoc_bto_ahb_clk",
2517 .ops = &clk_ops_branch,
2518 CLK_INIT(mmss_mmssnoc_bto_ahb_clk.c),
2519 },
2520};
2521
2522static struct branch_clk mmss_mmssnoc_axi_clk = {
2523 .cbcr_reg = MMSS_MMSSNOC_AXI_CBCR,
2524 .has_sibling = 1,
2525 .base = &virt_bases[MMSS_BASE],
2526 .c = {
2527 .dbg_name = "mmss_mmssnoc_axi_clk",
2528 .parent = &axi_clk_src.c,
2529 .ops = &clk_ops_branch,
2530 CLK_INIT(mmss_mmssnoc_axi_clk.c),
2531 },
2532};
2533
2534static struct branch_clk mmss_s0_axi_clk = {
2535 .cbcr_reg = MMSS_S0_AXI_CBCR,
2536 .has_sibling = 0,
2537 .max_div = 0,
2538 .base = &virt_bases[MMSS_BASE],
2539 .c = {
2540 .dbg_name = "mmss_s0_axi_clk",
2541 .parent = &axi_clk_src.c,
2542 .ops = &clk_ops_branch,
2543 CLK_INIT(mmss_s0_axi_clk.c),
2544 .depends = &mmss_mmssnoc_axi_clk.c,
2545 },
2546};
2547
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2548static struct branch_clk oxili_gfx3d_clk = {
2549 .cbcr_reg = OXILI_GFX3D_CBCR,
Patrick Daly295173b2013-03-11 13:35:40 -0700[diff] [blame]2550 .has_sibling = 0,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2551 .max_div = 0,
2552 .base = &virt_bases[MMSS_BASE],
2553 .c = {
2554 .dbg_name = "oxili_gfx3d_clk",
2555 .parent = &gfx3d_clk_src.c,
2556 .ops = &clk_ops_branch,
2557 CLK_INIT(oxili_gfx3d_clk.c),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2558 },
2559};
2560
2561static struct branch_clk oxilicx_ahb_clk = {
2562 .cbcr_reg = OXILICX_AHB_CBCR,
2563 .has_sibling = 1,
2564 .base = &virt_bases[MMSS_BASE],
2565 .c = {
2566 .dbg_name = "oxilicx_ahb_clk",
2567 .ops = &clk_ops_branch,
2568 CLK_INIT(oxilicx_ahb_clk.c),
2569 },
2570};
2571
2572static struct branch_clk oxilicx_axi_clk = {
2573 .cbcr_reg = OXILICX_AXI_CBCR,
2574 .has_sibling = 1,
2575 .base = &virt_bases[MMSS_BASE],
2576 .c = {
2577 .dbg_name = "oxilicx_axi_clk",
2578 .parent = &axi_clk_src.c,
2579 .ops = &clk_ops_branch,
2580 CLK_INIT(oxilicx_axi_clk.c),
2581 },
2582};
2583
2584static struct branch_clk venus0_ahb_clk = {
2585 .cbcr_reg = VENUS0_AHB_CBCR,
2586 .has_sibling = 1,
2587 .base = &virt_bases[MMSS_BASE],
2588 .c = {
2589 .dbg_name = "venus0_ahb_clk",
2590 .ops = &clk_ops_branch,
2591 CLK_INIT(venus0_ahb_clk.c),
2592 },
2593};
2594
2595static struct branch_clk venus0_axi_clk = {
2596 .cbcr_reg = VENUS0_AXI_CBCR,
2597 .has_sibling = 1,
2598 .base = &virt_bases[MMSS_BASE],
2599 .c = {
2600 .dbg_name = "venus0_axi_clk",
2601 .parent = &axi_clk_src.c,
2602 .ops = &clk_ops_branch,
2603 CLK_INIT(venus0_axi_clk.c),
2604 },
2605};
2606
2607static struct branch_clk venus0_vcodec0_clk = {
2608 .cbcr_reg = VENUS0_VCODEC0_CBCR,
2609 .has_sibling = 0,
2610 .base = &virt_bases[MMSS_BASE],
2611 .c = {
2612 .dbg_name = "venus0_vcodec0_clk",
2613 .parent = &vcodec0_clk_src.c,
2614 .ops = &clk_ops_branch,
2615 CLK_INIT(venus0_vcodec0_clk.c),
2616 },
2617};
2618
2619static struct measure_mux_entry measure_mux_MMSS[] = {
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2620 { &mmss_mmssnoc_bto_ahb_clk.c, MMSS_BASE, 0x0002 },
2621 { &mmss_misc_ahb_clk.c, MMSS_BASE, 0x0003 },
2622 { &mmss_mmssnoc_axi_clk.c, MMSS_BASE, 0x0004 },
2623 { &mmss_s0_axi_clk.c, MMSS_BASE, 0x0005 },
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2624 { &oxilicx_axi_clk.c, MMSS_BASE, 0x000b },
2625 { &oxilicx_ahb_clk.c, MMSS_BASE, 0x000c },
2626 { &oxili_gfx3d_clk.c, MMSS_BASE, 0x000d },
2627 { &venus0_vcodec0_clk.c, MMSS_BASE, 0x000e },
2628 { &venus0_axi_clk.c, MMSS_BASE, 0x000f },
2629 { &venus0_ahb_clk.c, MMSS_BASE, 0x0011 },
2630 { &mdss_mdp_clk.c, MMSS_BASE, 0x0014 },
2631 { &mdss_mdp_lut_clk.c, MMSS_BASE, 0x0015 },
2632 { &mdss_pclk0_clk.c, MMSS_BASE, 0x0016 },
2633 { &mdss_vsync_clk.c, MMSS_BASE, 0x001c },
2634 { &mdss_byte0_clk.c, MMSS_BASE, 0x001e },
2635 { &mdss_esc0_clk.c, MMSS_BASE, 0x0020 },
2636 { &mdss_ahb_clk.c, MMSS_BASE, 0x0022 },
2637 { &mdss_axi_clk.c, MMSS_BASE, 0x0024 },
2638 { &camss_top_ahb_clk.c, MMSS_BASE, 0x0025 },
2639 { &camss_micro_ahb_clk.c, MMSS_BASE, 0x0026 },
2640 { &camss_gp0_clk.c, MMSS_BASE, 0x0027 },
2641 { &camss_gp1_clk.c, MMSS_BASE, 0x0028 },
2642 { &camss_mclk0_clk.c, MMSS_BASE, 0x0029 },
2643 { &camss_mclk1_clk.c, MMSS_BASE, 0x002a },
2644 { &camss_cci_cci_clk.c, MMSS_BASE, 0x002d },
2645 { &camss_cci_cci_ahb_clk.c, MMSS_BASE, 0x002e },
2646 { &camss_phy0_csi0phytimer_clk.c, MMSS_BASE, 0x002f },
2647 { &camss_phy1_csi1phytimer_clk.c, MMSS_BASE, 0x0030 },
2648 { &camss_jpeg_jpeg0_clk.c, MMSS_BASE, 0x0032 },
2649 { &camss_jpeg_jpeg_ahb_clk.c, MMSS_BASE, 0x0035 },
2650 { &camss_jpeg_jpeg_axi_clk.c, MMSS_BASE, 0x0036 },
2651 { &camss_vfe_vfe0_clk.c, MMSS_BASE, 0x0038 },
2652 { &camss_vfe_cpp_clk.c, MMSS_BASE, 0x003a },
2653 { &camss_vfe_cpp_ahb_clk.c, MMSS_BASE, 0x003b },
2654 { &camss_vfe_vfe_ahb_clk.c, MMSS_BASE, 0x003c },
2655 { &camss_vfe_vfe_axi_clk.c, MMSS_BASE, 0x003d },
2656 { &camss_csi_vfe0_clk.c, MMSS_BASE, 0x003f },
2657 { &camss_csi0_clk.c, MMSS_BASE, 0x0041 },
2658 { &camss_csi0_ahb_clk.c, MMSS_BASE, 0x0042 },
2659 { &camss_csi0phy_clk.c, MMSS_BASE, 0x0043 },
2660 { &camss_csi0rdi_clk.c, MMSS_BASE, 0x0044 },
2661 { &camss_csi0pix_clk.c, MMSS_BASE, 0x0045 },
2662 { &camss_csi1_clk.c, MMSS_BASE, 0x0046 },
2663 { &camss_csi1_ahb_clk.c, MMSS_BASE, 0x0047 },
2664 { &camss_csi1phy_clk.c, MMSS_BASE, 0x0048 },
2665 { &camss_csi1rdi_clk.c, MMSS_BASE, 0x0049 },
2666 { &camss_csi1pix_clk.c, MMSS_BASE, 0x004a },
2667 { &camss_ispif_ahb_clk.c, MMSS_BASE, 0x0055 },
2668 {&dummy_clk, N_BASES, 0x0000},
2669};
2670
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2671static struct branch_clk q6ss_ahb_lfabif_clk = {
2672 .cbcr_reg = Q6SS_AHB_LFABIF_CBCR,
2673 .has_sibling = 1,
2674 .base = &virt_bases[LPASS_BASE],
2675 .c = {
2676 .dbg_name = "q6ss_ahb_lfabif_clk",
2677 .ops = &clk_ops_branch,
2678 CLK_INIT(q6ss_ahb_lfabif_clk.c),
2679 },
2680};
2681
2682static struct branch_clk q6ss_ahbm_clk = {
2683 .cbcr_reg = Q6SS_AHBM_CBCR,
2684 .has_sibling = 1,
2685 .base = &virt_bases[LPASS_BASE],
2686 .c = {
2687 .dbg_name = "q6ss_ahbm_clk",
2688 .ops = &clk_ops_branch,
2689 CLK_INIT(q6ss_ahbm_clk.c),
2690 },
2691};
2692
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2693static struct branch_clk q6ss_xo_clk = {
2694 .cbcr_reg = Q6SS_XO_CBCR,
2695 .has_sibling = 1,
2696 .bcr_reg = Q6SS_BCR,
2697 .base = &virt_bases[LPASS_BASE],
2698 .c = {
2699 .dbg_name = "q6ss_xo_clk",
2700 .parent = &xo.c,
2701 .ops = &clk_ops_branch,
2702 CLK_INIT(q6ss_xo_clk.c),
2703 },
2704};
2705
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2706static struct measure_mux_entry measure_mux_LPASS[] = {
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2707 { &q6ss_ahbm_clk.c, LPASS_BASE, 0x001d },
2708 { &q6ss_ahb_lfabif_clk.c, LPASS_BASE, 0x001e },
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2709 { &q6ss_xo_clk.c, LPASS_BASE, 0x002b },
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2710 {&dummy_clk, N_BASES, 0x0000},
2711};
2712
2713
2714static DEFINE_CLK_MEASURE(apc0_m_clk);
2715static DEFINE_CLK_MEASURE(apc1_m_clk);
2716static DEFINE_CLK_MEASURE(apc2_m_clk);
2717static DEFINE_CLK_MEASURE(apc3_m_clk);
2718static DEFINE_CLK_MEASURE(l2_m_clk);
2719
2720static struct measure_mux_entry measure_mux_APSS[] = {
2721 {&apc0_m_clk, APCS_BASE, 0x00010},
2722 {&apc1_m_clk, APCS_BASE, 0x00114},
2723 {&apc2_m_clk, APCS_BASE, 0x00220},
2724 {&apc3_m_clk, APCS_BASE, 0x00324},
2725 {&l2_m_clk, APCS_BASE, 0x01000},
2726 {&dummy_clk, N_BASES, 0x0000}
2727};
2728
2729#define APCS_SH_PLL_MODE (0x000)
2730#define APCS_SH_PLL_L_VAL (0x004)
2731#define APCS_SH_PLL_M_VAL (0x008)
2732#define APCS_SH_PLL_N_VAL (0x00C)
2733#define APCS_SH_PLL_USER_CTL (0x010)
2734#define APCS_SH_PLL_CONFIG_CTL (0x014)
2735#define APCS_SH_PLL_STATUS (0x01C)
2736
2737enum vdd_sr2_pll_levels {
2738 VDD_SR2_PLL_OFF,
Patrick Daly6fb589a2013-03-29 17:55:55 -0700[diff] [blame]2739 VDD_SR2_PLL_SVS,
2740 VDD_SR2_PLL_NOM,
2741 VDD_SR2_PLL_TUR,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2742 VDD_SR2_PLL_NUM
2743};
2744
Patrick Dalyebc26bc2013-02-05 11:49:07 -0800[diff] [blame]2745static const int *vdd_sr2_levels[] = {
Patrick Daly6fb589a2013-03-29 17:55:55 -0700[diff] [blame]2746 [VDD_SR2_PLL_OFF] = VDD_UV(0, RPM_REGULATOR_CORNER_NONE),
2747 [VDD_SR2_PLL_SVS] = VDD_UV(1800000, RPM_REGULATOR_CORNER_SVS_SOC),
2748 [VDD_SR2_PLL_NOM] = VDD_UV(1800000, RPM_REGULATOR_CORNER_NORMAL),
2749 [VDD_SR2_PLL_TUR] = VDD_UV(1800000, RPM_REGULATOR_CORNER_SUPER_TURBO),
Patrick Dalyebc26bc2013-02-05 11:49:07 -0800[diff] [blame]2750};
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2751
Patrick Daly6fb589a2013-03-29 17:55:55 -0700[diff] [blame]2752static DEFINE_VDD_REGULATORS(vdd_sr2_pll, VDD_SR2_PLL_NUM, 2, vdd_sr2_levels);
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2753
2754static struct pll_freq_tbl apcs_pll_freq[] = {
2755 F_APCS_PLL( 384000000, 20, 0x0, 0x1, 0x0, 0x0, 0x0),
2756 F_APCS_PLL( 787200000, 41, 0x0, 0x1, 0x0, 0x0, 0x0),
2757 F_APCS_PLL( 998400000, 52, 0x0, 0x1, 0x0, 0x0, 0x0),
2758 F_APCS_PLL(1190400000, 62, 0x0, 0x1, 0x0, 0x0, 0x0),
2759 PLL_F_END
2760};
2761
2762static struct pll_clk a7sspll = {
2763 .mode_reg = (void __iomem *)APCS_SH_PLL_MODE,
2764 .l_reg = (void __iomem *)APCS_SH_PLL_L_VAL,
2765 .m_reg = (void __iomem *)APCS_SH_PLL_M_VAL,
2766 .n_reg = (void __iomem *)APCS_SH_PLL_N_VAL,
2767 .config_reg = (void __iomem *)APCS_SH_PLL_USER_CTL,
2768 .status_reg = (void __iomem *)APCS_SH_PLL_STATUS,
2769 .freq_tbl = apcs_pll_freq,
2770 .masks = {
2771 .vco_mask = BM(29, 28),
2772 .pre_div_mask = BIT(12),
2773 .post_div_mask = BM(9, 8),
2774 .mn_en_mask = BIT(24),
2775 .main_output_mask = BIT(0),
2776 },
2777 .base = &virt_bases[APCS_PLL_BASE],
2778 .c = {
Patrick Daly9bdc8a52013-03-21 19:12:40 -0700[diff] [blame]2779 .parent = &xo_a_clk.c,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2780 .dbg_name = "a7sspll",
2781 .ops = &clk_ops_sr2_pll,
2782 .vdd_class = &vdd_sr2_pll,
2783 .fmax = (unsigned long [VDD_SR2_PLL_NUM]) {
Patrick Daly6fb589a2013-03-29 17:55:55 -0700[diff] [blame]2784 [VDD_SR2_PLL_SVS] = 1000000000,
2785 [VDD_SR2_PLL_NOM] = 1900000000,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2786 },
2787 .num_fmax = VDD_SR2_PLL_NUM,
2788 CLK_INIT(a7sspll.c),
2789 /*
2790 * Need to skip handoff of the acpu pll to avoid
2791 * turning off the pll when the cpu is using it
2792 */
2793 .flags = CLKFLAG_SKIP_HANDOFF,
2794 },
2795};
2796
2797static DEFINE_CLK_VOTER(pnoc_msmbus_clk, &pnoc_clk.c, LONG_MAX);
2798static DEFINE_CLK_VOTER(snoc_msmbus_clk, &snoc_clk.c, LONG_MAX);
2799static DEFINE_CLK_VOTER(cnoc_msmbus_clk, &cnoc_clk.c, LONG_MAX);
2800static DEFINE_CLK_VOTER(pnoc_msmbus_a_clk, &pnoc_a_clk.c, LONG_MAX);
2801static DEFINE_CLK_VOTER(snoc_msmbus_a_clk, &snoc_a_clk.c, LONG_MAX);
2802static DEFINE_CLK_VOTER(cnoc_msmbus_a_clk, &cnoc_a_clk.c, LONG_MAX);
2803
2804static DEFINE_CLK_VOTER(bimc_msmbus_clk, &bimc_clk.c, LONG_MAX);
2805static DEFINE_CLK_VOTER(bimc_msmbus_a_clk, &bimc_a_clk.c, LONG_MAX);
2806static DEFINE_CLK_VOTER(bimc_acpu_a_clk, &bimc_a_clk.c, LONG_MAX);
2807static DEFINE_CLK_VOTER(oxili_gfx3d_clk_src, &gfx3d_clk_src.c, LONG_MAX);
2808static DEFINE_CLK_VOTER(ocmemgx_msmbus_clk, &ocmemgx_clk.c, LONG_MAX);
2809static DEFINE_CLK_VOTER(ocmemgx_msmbus_a_clk, &ocmemgx_a_clk.c, LONG_MAX);
2810static DEFINE_CLK_VOTER(ocmemgx_core_clk, &ocmemgx_clk.c, LONG_MAX);
2811
2812static DEFINE_CLK_VOTER(pnoc_sps_clk, &pnoc_clk.c, LONG_MAX);
2813
Patrick Dalye07324c2013-03-27 18:02:49 -0700[diff] [blame]2814static DEFINE_CLK_VOTER(qseecom_ce1_clk_src, &ce1_clk_src.c, LONG_MAX);
2815static DEFINE_CLK_VOTER(scm_ce1_clk_src, &ce1_clk_src.c, LONG_MAX);
2816
Patrick Dalya5296072013-03-19 12:18:04 -0700[diff] [blame]2817static DEFINE_CLK_BRANCH_VOTER(cxo_otg_clk, &xo.c);
2818static DEFINE_CLK_BRANCH_VOTER(cxo_pil_lpass_clk, &xo.c);
2819static DEFINE_CLK_BRANCH_VOTER(cxo_pil_mss_clk, &xo.c);
2820static DEFINE_CLK_BRANCH_VOTER(cxo_wlan_clk, &xo.c);
2821static DEFINE_CLK_BRANCH_VOTER(cxo_pil_pronto_clk, &xo.c);
2822
2823
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2824#ifdef CONFIG_DEBUG_FS
2825static int measure_clk_set_parent(struct clk *c, struct clk *parent)
2826{
2827 struct measure_clk *clk = to_measure_clk(c);
2828 unsigned long flags;
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2829 u32 regval, clk_sel, found = 0;
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2830 int i;
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2831 static const struct measure_mux_entry *array[] = {
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2832 measure_mux_GCC,
2833 measure_mux_MMSS,
2834 measure_mux_LPASS,
2835 measure_mux_APSS,
2836 NULL
2837 };
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2838 const struct measure_mux_entry *mux = array[0];
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2839
2840 if (!parent)
2841 return -EINVAL;
2842
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2843 for (i = 0; array[i] && !found; i++) {
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2844 for (mux = array[i]; mux->c != &dummy_clk; mux++)
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2845 if (mux->c == parent) {
2846 found = 1;
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2847 break;
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2848 }
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2849 }
2850
2851 if (mux->c == &dummy_clk)
2852 return -EINVAL;
2853
2854 spin_lock_irqsave(&local_clock_reg_lock, flags);
2855 /*
2856 * Program the test vector, measurement period (sample_ticks)
2857 * and scaling multiplier.
2858 */
2859 clk->sample_ticks = 0x10000;
2860 clk->multiplier = 1;
2861
2862 switch (mux->base) {
2863
2864 case GCC_BASE:
2865 writel_relaxed(0, GCC_REG_BASE(GCC_DEBUG_CLK_CTL));
2866 clk_sel = mux->debug_mux;
2867 break;
2868
2869 case MMSS_BASE:
2870 writel_relaxed(0, MMSS_REG_BASE(MMSS_DEBUG_CLK_CTL));
2871 clk_sel = 0x02C;
2872 regval = BVAL(11, 0, mux->debug_mux);
2873 writel_relaxed(regval, MMSS_REG_BASE(MMSS_DEBUG_CLK_CTL));
2874
2875 /* Activate debug clock output */
2876 regval |= BIT(16);
2877 writel_relaxed(regval, MMSS_REG_BASE(MMSS_DEBUG_CLK_CTL));
2878 break;
2879
2880 case LPASS_BASE:
2881 writel_relaxed(0, LPASS_REG_BASE(LPASS_DEBUG_CLK_CTL));
2882 clk_sel = 0x161;
2883 regval = BVAL(11, 0, mux->debug_mux);
2884 writel_relaxed(regval, LPASS_REG_BASE(LPASS_DEBUG_CLK_CTL));
2885
2886 /* Activate debug clock output */
2887 regval |= BIT(20);
2888 writel_relaxed(regval, LPASS_REG_BASE(LPASS_DEBUG_CLK_CTL));
2889 break;
2890
2891 case APCS_BASE:
2892 clk->multiplier = 4;
2893 clk_sel = 362;
2894 regval = readl_relaxed(APCS_REG_BASE(GLB_CLK_DIAG));
2895 regval &= ~0xC0037335;
2896 /* configure a divider of 4 */
2897 regval = BVAL(31, 30, 0x3) | mux->debug_mux;
2898 writel_relaxed(regval, APCS_REG_BASE(GLB_CLK_DIAG));
2899 break;
2900
2901 default:
2902 return -EINVAL;
2903 }
2904
2905 /* Set debug mux clock index */
2906 regval = BVAL(8, 0, clk_sel);
2907 writel_relaxed(regval, GCC_REG_BASE(GCC_DEBUG_CLK_CTL));
2908
2909 /* Activate debug clock output */
2910 regval |= BIT(16);
2911 writel_relaxed(regval, GCC_REG_BASE(GCC_DEBUG_CLK_CTL));
2912
2913 /* Make sure test vector is set before starting measurements. */
2914 mb();
2915 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
2916
2917 return 0;
2918}
2919
2920/* Sample clock for 'ticks' reference clock ticks. */
2921static u32 run_measurement(unsigned ticks)
2922{
2923 /* Stop counters and set the XO4 counter start value. */
2924 writel_relaxed(ticks, GCC_REG_BASE(CLOCK_FRQ_MEASURE_CTL));
2925
2926 /* Wait for timer to become ready. */
2927 while ((readl_relaxed(GCC_REG_BASE(CLOCK_FRQ_MEASURE_STATUS)) &
2928 BIT(25)) != 0)
2929 cpu_relax();
2930
2931 /* Run measurement and wait for completion. */
2932 writel_relaxed(BIT(20)|ticks, GCC_REG_BASE(CLOCK_FRQ_MEASURE_CTL));
2933 while ((readl_relaxed(GCC_REG_BASE(CLOCK_FRQ_MEASURE_STATUS)) &
2934 BIT(25)) == 0)
2935 cpu_relax();
2936
2937 /* Return measured ticks. */
2938 return readl_relaxed(GCC_REG_BASE(CLOCK_FRQ_MEASURE_STATUS)) &
2939 BM(24, 0);
2940}
2941
2942/*
2943 * Perform a hardware rate measurement for a given clock.
2944 * FOR DEBUG USE ONLY: Measurements take ~15 ms!
2945 */
2946static unsigned long measure_clk_get_rate(struct clk *c)
2947{
2948 unsigned long flags;
2949 u32 gcc_xo4_reg_backup;
2950 u64 raw_count_short, raw_count_full;
2951 struct measure_clk *clk = to_measure_clk(c);
2952 unsigned ret;
2953
2954 ret = clk_prepare_enable(&xo.c);
2955 if (ret) {
2956 pr_warn("CXO clock failed to enable. Can't measure\n");
2957 return 0;
2958 }
2959
2960 spin_lock_irqsave(&local_clock_reg_lock, flags);
2961
2962 /* Enable CXO/4 and RINGOSC branch. */
2963 gcc_xo4_reg_backup = readl_relaxed(GCC_REG_BASE(GCC_XO_DIV4_CBCR));
2964 writel_relaxed(0x1, GCC_REG_BASE(GCC_XO_DIV4_CBCR));
2965
2966 /*
2967 * The ring oscillator counter will not reset if the measured clock
2968 * is not running. To detect this, run a short measurement before
2969 * the full measurement. If the raw results of the two are the same
2970 * then the clock must be off.
2971 */
2972
2973 /* Run a short measurement. (~1 ms) */
2974 raw_count_short = run_measurement(0x1000);
2975 /* Run a full measurement. (~14 ms) */
2976 raw_count_full = run_measurement(clk->sample_ticks);
2977
2978 writel_relaxed(gcc_xo4_reg_backup, GCC_REG_BASE(GCC_XO_DIV4_CBCR));
2979
2980 /* Return 0 if the clock is off. */
2981 if (raw_count_full == raw_count_short) {
2982 ret = 0;
2983 } else {
2984 /* Compute rate in Hz. */
2985 raw_count_full = ((raw_count_full * 10) + 15) * 4800000;
2986 do_div(raw_count_full, ((clk->sample_ticks * 10) + 35));
2987 ret = (raw_count_full * clk->multiplier);
2988 }
2989
2990 writel_relaxed(0x51A00, GCC_REG_BASE(PLLTEST_PAD_CFG));
2991 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
2992
2993 clk_disable_unprepare(&xo.c);
2994
2995 return ret;
2996}
2997
2998#else /* !CONFIG_DEBUG_FS */
2999static int measure_clk_set_parent(struct clk *clk, struct clk *parent)
3000{
3001 return -EINVAL;
3002}
3003
3004static unsigned long measure_clk_get_rate(struct clk *clk)
3005{
3006 return 0;
3007}
3008#endif /* CONFIG_DEBUG_FS */
3009
3010static struct clk_ops clk_ops_measure = {
3011 .set_parent = measure_clk_set_parent,
3012 .get_rate = measure_clk_get_rate,
3013};
3014
3015static struct measure_clk measure_clk = {
3016 .c = {
3017 .dbg_name = "measure_clk",
3018 .ops = &clk_ops_measure,
3019 CLK_INIT(measure_clk.c),
3020 },
3021 .multiplier = 1,
3022};
3023
3024static struct clk_lookup msm_clocks_8226[] = {
3025 /* Debug Clocks */
3026 CLK_LOOKUP("measure", measure_clk.c, "debug"),
3027 CLK_LOOKUP("apc0_m_clk", apc0_m_clk, ""),
3028 CLK_LOOKUP("apc1_m_clk", apc1_m_clk, ""),
3029 CLK_LOOKUP("apc2_m_clk", apc2_m_clk, ""),
3030 CLK_LOOKUP("apc3_m_clk", apc3_m_clk, ""),
3031 CLK_LOOKUP("l2_m_clk", l2_m_clk, ""),
3032
3033 /* PIL-LPASS */
Patrick Dalya5296072013-03-19 12:18:04 -0700[diff] [blame]3034 CLK_LOOKUP("xo", cxo_pil_lpass_clk.c, "fe200000.qcom,lpass"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3035 CLK_LOOKUP("core_clk", q6ss_xo_clk.c, "fe200000.qcom,lpass"),
3036 CLK_LOOKUP("bus_clk", gcc_lpass_q6_axi_clk.c, "fe200000.qcom,lpass"),
3037 CLK_LOOKUP("iface_clk", q6ss_ahb_lfabif_clk.c, "fe200000.qcom,lpass"),
3038 CLK_LOOKUP("reg_clk", q6ss_ahbm_clk.c, "fe200000.qcom,lpass"),
3039
3040 /* PIL-MODEM */
Patrick Dalya5296072013-03-19 12:18:04 -0700[diff] [blame]3041 CLK_LOOKUP("xo", cxo_pil_mss_clk.c, "fc880000.qcom,mss"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3042 CLK_LOOKUP("bus_clk", gcc_mss_q6_bimc_axi_clk.c, "fc880000.qcom,mss"),
3043 CLK_LOOKUP("iface_clk", gcc_mss_cfg_ahb_clk.c, "fc880000.qcom,mss"),
3044 CLK_LOOKUP("mem_clk", gcc_boot_rom_ahb_clk.c, "fc880000.qcom,mss"),
3045
3046 /* PIL-PRONTO */
Patrick Dalya5296072013-03-19 12:18:04 -0700[diff] [blame]3047 CLK_LOOKUP("xo", cxo_pil_pronto_clk.c, "fb21b000.qcom,pronto"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3048
3049 /* PIL-VENUS */
3050 CLK_LOOKUP("src_clk", vcodec0_clk_src.c, "fdce0000.qcom,venus"),
3051 CLK_LOOKUP("core_clk", venus0_vcodec0_clk.c, "fdce0000.qcom,venus"),
3052 CLK_LOOKUP("iface_clk", venus0_ahb_clk.c, "fdce0000.qcom,venus"),
3053 CLK_LOOKUP("bus_clk", venus0_axi_clk.c, "fdce0000.qcom,venus"),
3054 CLK_LOOKUP("mem_clk", venus0_ahb_clk.c, "fdce0000.qcom,venus"),
3055
3056 /* ACPUCLOCK */
3057 CLK_LOOKUP("xo", xo_a_clk.c, "f9011050.qcom,acpuclk"),
3058 CLK_LOOKUP("gpll0", gpll0_ao.c, "f9011050.qcom,acpuclk"),
3059 CLK_LOOKUP("a7sspll", a7sspll.c, "f9011050.qcom,acpuclk"),
3060
3061 /* WCNSS CLOCKS */
Patrick Dalya5296072013-03-19 12:18:04 -0700[diff] [blame]3062 CLK_LOOKUP("xo", cxo_wlan_clk.c, "fb000000.qcom,wcnss-wlan"),
Vikram Mulukutla7e5b3112013-04-15 16:32:40 -0700[diff] [blame]3063 CLK_LOOKUP("rf_clk", cxo_a1.c, "fb000000.qcom,wcnss-wlan"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3064
3065 /* BUS DRIVER */
3066 CLK_LOOKUP("bus_clk", cnoc_msmbus_clk.c, "msm_config_noc"),
3067 CLK_LOOKUP("bus_a_clk", cnoc_msmbus_a_clk.c, "msm_config_noc"),
3068 CLK_LOOKUP("bus_clk", snoc_msmbus_clk.c, "msm_sys_noc"),
3069 CLK_LOOKUP("bus_a_clk", snoc_msmbus_a_clk.c, "msm_sys_noc"),
3070 CLK_LOOKUP("bus_clk", pnoc_msmbus_clk.c, "msm_periph_noc"),
3071 CLK_LOOKUP("bus_a_clk", pnoc_msmbus_a_clk.c, "msm_periph_noc"),
3072 CLK_LOOKUP("mem_clk", bimc_msmbus_clk.c, "msm_bimc"),
3073 CLK_LOOKUP("mem_a_clk", bimc_msmbus_a_clk.c, "msm_bimc"),
3074 CLK_LOOKUP("mem_clk", bimc_acpu_a_clk.c, ""),
3075 CLK_LOOKUP("ocmem_clk", ocmemgx_msmbus_clk.c, "msm_bus"),
3076 CLK_LOOKUP("ocmem_a_clk", ocmemgx_msmbus_a_clk.c, "msm_bus"),
3077 CLK_LOOKUP("bus_clk", mmss_s0_axi_clk.c, "msm_mmss_noc"),
3078 CLK_LOOKUP("bus_a_clk", mmss_s0_axi_clk.c, "msm_mmss_noc"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3079
Aparna Das8c8e9752013-02-28 21:23:24 -0800[diff] [blame]3080 /* CoreSight clocks */
3081 CLK_LOOKUP("core_clk", qdss_clk.c, "fc322000.tmc"),
3082 CLK_LOOKUP("core_clk", qdss_clk.c, "fc318000.tpiu"),
3083 CLK_LOOKUP("core_clk", qdss_clk.c, "fc31c000.replicator"),
3084 CLK_LOOKUP("core_clk", qdss_clk.c, "fc307000.tmc"),
3085 CLK_LOOKUP("core_clk", qdss_clk.c, "fc31b000.funnel"),
3086 CLK_LOOKUP("core_clk", qdss_clk.c, "fc319000.funnel"),
3087 CLK_LOOKUP("core_clk", qdss_clk.c, "fc31a000.funnel"),
3088 CLK_LOOKUP("core_clk", qdss_clk.c, "fc345000.funnel"),
3089 CLK_LOOKUP("core_clk", qdss_clk.c, "fc364000.funnel"),
3090 CLK_LOOKUP("core_clk", qdss_clk.c, "fc321000.stm"),
3091 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33c000.etm"),
3092 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33d000.etm"),
3093 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33e000.etm"),
3094 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33f000.etm"),
Pushkar Joshi14676cc2013-03-11 14:53:53 -0700[diff] [blame]3095 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33c000.jtagmm"),
3096 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33d000.jtagmm"),
3097 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33e000.jtagmm"),
3098 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33f000.jtagmm"),
Aparna Dasbb65be42013-03-07 12:39:45 -0800[diff] [blame]3099 CLK_LOOKUP("core_clk", qdss_clk.c, "fc308000.cti"),
3100 CLK_LOOKUP("core_clk", qdss_clk.c, "fc309000.cti"),
3101 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30a000.cti"),
3102 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30b000.cti"),
3103 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30c000.cti"),
3104 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30d000.cti"),
3105 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30e000.cti"),
3106 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30f000.cti"),
3107 CLK_LOOKUP("core_clk", qdss_clk.c, "fc310000.cti"),
3108 CLK_LOOKUP("core_clk", qdss_clk.c, "fc340000.cti"),
3109 CLK_LOOKUP("core_clk", qdss_clk.c, "fc341000.cti"),
3110 CLK_LOOKUP("core_clk", qdss_clk.c, "fc342000.cti"),
3111 CLK_LOOKUP("core_clk", qdss_clk.c, "fc343000.cti"),
3112 CLK_LOOKUP("core_clk", qdss_clk.c, "fc344000.cti"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3113
Aparna Das8c8e9752013-02-28 21:23:24 -0800[diff] [blame]3114 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc322000.tmc"),
3115 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc318000.tpiu"),
3116 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc31c000.replicator"),
3117 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc307000.tmc"),
3118 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc31b000.funnel"),
3119 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc319000.funnel"),
3120 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc31a000.funnel"),
3121 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc345000.funnel"),
3122 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc364000.funnel"),
3123 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc321000.stm"),
3124 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33c000.etm"),
3125 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33d000.etm"),
3126 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33e000.etm"),
3127 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33f000.etm"),
Pushkar Joshi14676cc2013-03-11 14:53:53 -0700[diff] [blame]3128 CLK_LOOKUP("core_a_clk", qdss_clk.c, "fc33c000.jtagmm"),
3129 CLK_LOOKUP("core_a_clk", qdss_clk.c, "fc33d000.jtagmm"),
3130 CLK_LOOKUP("core_a_clk", qdss_clk.c, "fc33e000.jtagmm"),
3131 CLK_LOOKUP("core_a_clk", qdss_clk.c, "fc33f000.jtagmm"),
Aparna Dasbb65be42013-03-07 12:39:45 -0800[diff] [blame]3132 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc308000.cti"),
3133 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc309000.cti"),
3134 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30a000.cti"),
3135 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30b000.cti"),
3136 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30c000.cti"),
3137 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30d000.cti"),
3138 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30e000.cti"),
3139 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30f000.cti"),
3140 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc310000.cti"),
3141 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc340000.cti"),
3142 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc341000.cti"),
3143 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc342000.cti"),
3144 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc343000.cti"),
3145 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc344000.cti"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3146
3147 /* HSUSB-OTG Clocks */
Patrick Dalya5296072013-03-19 12:18:04 -0700[diff] [blame]3148 CLK_LOOKUP("xo", cxo_otg_clk.c, "f9a55000.usb"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3149 CLK_LOOKUP("iface_clk", gcc_usb_hs_ahb_clk.c, "f9a55000.usb"),
3150 CLK_LOOKUP("core_clk", gcc_usb_hs_system_clk.c, "f9a55000.usb"),
3151
3152 /* SPS CLOCKS */
3153 CLK_LOOKUP("dfab_clk", pnoc_sps_clk.c, "f9984000.qcom,sps"),
3154 CLK_LOOKUP("dma_bam_pclk", gcc_bam_dma_ahb_clk.c, "f9884000.qcom,sps"),
3155 CLK_LOOKUP("dfab_clk", pnoc_sps_clk.c, "msm_sps"),
3156 CLK_LOOKUP("dma_bam_pclk", gcc_bam_dma_ahb_clk.c, "msm_sps"),
3157
3158 /* I2C Clocks */
3159 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9926000.i2c"),
3160 CLK_LOOKUP("core_clk", gcc_blsp1_qup4_i2c_apps_clk.c, "f9926000.i2c"),
3161
Amy Maloche41708ba2013-03-03 15:19:27 -0800[diff] [blame]3162 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9927000.i2c"),
3163 CLK_LOOKUP("core_clk", gcc_blsp1_qup5_i2c_apps_clk.c, "f9927000.i2c"),
3164
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3165 /* lsuart-v14 Clocks */
3166 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f991f000.serial"),
3167 CLK_LOOKUP("core_clk", gcc_blsp1_uart3_apps_clk.c, "f991f000.serial"),
3168
3169 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f995e000.serial"),
3170 CLK_LOOKUP("core_clk", gcc_blsp1_uart2_apps_clk.c, "f995e000.serial"),
3171
Gilad Avidovd59217c2013-02-01 13:45:59 -0700[diff] [blame]3172 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9923000.spi"),
3173 CLK_LOOKUP("core_clk", gcc_blsp1_qup1_spi_apps_clk.c, "f9923000.spi"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3174
3175 CLK_LOOKUP("core_clk", gcc_ce1_clk.c, "qseecom"),
3176 CLK_LOOKUP("iface_clk", gcc_ce1_ahb_clk.c, "qseecom"),
3177 CLK_LOOKUP("bus_clk", gcc_ce1_axi_clk.c, "qseecom"),
Patrick Dalye07324c2013-03-27 18:02:49 -0700[diff] [blame]3178 CLK_LOOKUP("core_clk_src", qseecom_ce1_clk_src.c, "qseecom"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3179
Patrick Dalyd5234252013-03-07 16:35:08 -0800[diff] [blame]3180 CLK_LOOKUP("core_clk", gcc_ce1_clk.c, "scm"),
3181 CLK_LOOKUP("iface_clk", gcc_ce1_ahb_clk.c, "scm"),
3182 CLK_LOOKUP("bus_clk", gcc_ce1_axi_clk.c, "scm"),
Patrick Dalye07324c2013-03-27 18:02:49 -0700[diff] [blame]3183 CLK_LOOKUP("core_clk_src", scm_ce1_clk_src.c, "scm"),
3184
3185 CLK_LOOKUP("core_clk_src", ce1_clk_src.c, ""),
Patrick Dalyd5234252013-03-07 16:35:08 -0800[diff] [blame]3186
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3187 /* SDCC */
3188 CLK_LOOKUP("iface_clk", gcc_sdcc1_ahb_clk.c, "f9824000.qcom,sdcc"),
3189 CLK_LOOKUP("core_clk", gcc_sdcc1_apps_clk.c, "f9824000.qcom,sdcc"),
3190 CLK_LOOKUP("iface_clk", gcc_sdcc1_ahb_clk.c, "msm_sdcc.1"),
3191 CLK_LOOKUP("core_clk", gcc_sdcc1_apps_clk.c, "msm_sdcc.1"),
3192
3193 CLK_LOOKUP("iface_clk", gcc_sdcc2_ahb_clk.c, "f98a4000.qcom,sdcc"),
3194 CLK_LOOKUP("core_clk", gcc_sdcc2_apps_clk.c, "f98a4000.qcom,sdcc"),
3195 CLK_LOOKUP("iface_clk", gcc_sdcc2_ahb_clk.c, "msm_sdcc.2"),
3196 CLK_LOOKUP("core_clk", gcc_sdcc2_apps_clk.c, "msm_sdcc.2"),
3197
3198 CLK_LOOKUP("iface_clk", gcc_sdcc3_ahb_clk.c, "msm_sdcc.3"),
3199 CLK_LOOKUP("core_clk", gcc_sdcc3_apps_clk.c, "msm_sdcc.3"),
3200
3201 CLK_LOOKUP("sleep_a_clk", gcc_usb2a_phy_sleep_clk.c, "msm_dwc3"),
3202 CLK_LOOKUP("ref_clk", diff_clk.c, "msm_dwc3"),
3203
3204
3205 CLK_LOOKUP("bus_clk", pnoc_clk.c, ""),
3206 CLK_LOOKUP("bus_clk", pnoc_a_clk.c, ""),
3207 CLK_LOOKUP("bus_clk", snoc_clk.c, ""),
3208 CLK_LOOKUP("bus_clk", snoc_a_clk.c, ""),
3209 CLK_LOOKUP("bus_clk", cnoc_clk.c, ""),
3210 CLK_LOOKUP("bus_clk", cnoc_a_clk.c, ""),
3211 CLK_LOOKUP("bus_clk", mmssnoc_ahb_clk.c, ""),
3212 CLK_LOOKUP("bus_clk", mmssnoc_ahb_a_clk.c, ""),
3213 CLK_LOOKUP("bus_clk", bimc_clk.c, ""),
3214 CLK_LOOKUP("bus_clk", bimc_a_clk.c, ""),
3215 CLK_LOOKUP("bus_clk_src", axi_clk_src.c, ""),
3216
3217 CLK_LOOKUP("gpll0", gpll0.c, ""),
3218 CLK_LOOKUP("gpll1", gpll1.c, ""),
3219 CLK_LOOKUP("mmpll0", mmpll0_pll.c, ""),
3220 CLK_LOOKUP("mmpll1", mmpll1_pll.c, ""),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3221
3222 CLK_LOOKUP("core_clk", gcc_blsp1_qup1_i2c_apps_clk.c, ""),
3223 CLK_LOOKUP("core_clk", gcc_blsp1_qup2_i2c_apps_clk.c, ""),
3224 CLK_LOOKUP("core_clk", gcc_blsp1_qup2_spi_apps_clk.c, ""),
3225 CLK_LOOKUP("core_clk", gcc_blsp1_qup3_i2c_apps_clk.c, ""),
3226 CLK_LOOKUP("core_clk", gcc_blsp1_qup3_spi_apps_clk.c, ""),
3227 CLK_LOOKUP("core_clk", gcc_blsp1_qup4_i2c_apps_clk.c, ""),
3228 CLK_LOOKUP("core_clk", gcc_blsp1_qup4_spi_apps_clk.c, ""),
3229 CLK_LOOKUP("core_clk", gcc_blsp1_qup5_i2c_apps_clk.c, ""),
3230 CLK_LOOKUP("core_clk", gcc_blsp1_qup5_spi_apps_clk.c, ""),
3231 CLK_LOOKUP("core_clk", gcc_blsp1_qup6_i2c_apps_clk.c, ""),
3232 CLK_LOOKUP("core_clk", gcc_blsp1_qup6_spi_apps_clk.c, ""),
3233 CLK_LOOKUP("core_clk", gcc_blsp1_uart1_apps_clk.c, ""),
3234 CLK_LOOKUP("core_clk", gcc_blsp1_uart4_apps_clk.c, ""),
3235 CLK_LOOKUP("core_clk", gcc_blsp1_uart5_apps_clk.c, ""),
3236 CLK_LOOKUP("core_clk", gcc_blsp1_uart6_apps_clk.c, ""),
3237 CLK_LOOKUP("core_clk", gcc_pdm2_clk.c, ""),
3238 CLK_LOOKUP("iface_clk", gcc_pdm_ahb_clk.c, ""),
3239 CLK_LOOKUP("iface_clk", gcc_prng_ahb_clk.c, ""),
3240 CLK_LOOKUP("core_clk", gcc_gp1_clk.c, ""),
3241 CLK_LOOKUP("core_clk", gcc_gp2_clk.c, ""),
3242 CLK_LOOKUP("core_clk", gcc_gp3_clk.c, ""),
3243
3244 CLK_LOOKUP("iface_clk", gcc_usb_hsic_ahb_clk.c, "msm_hsic_host"),
3245 CLK_LOOKUP("phy_clk", gcc_usb_hsic_clk.c, "msm_hsic_host"),
3246 CLK_LOOKUP("cal_clk", gcc_usb_hsic_io_cal_clk.c, "msm_hsic_host"),
3247 CLK_LOOKUP("core_clk", gcc_usb_hsic_system_clk.c, "msm_hsic_host"),
3248 CLK_LOOKUP("ref_clk", div_clk2.c, "msm_smsc_hub"),
3249 CLK_LOOKUP("iface_clk", gcc_usb_hs_ahb_clk.c, "msm_ehci_host"),
3250 CLK_LOOKUP("core_clk", gcc_usb_hs_system_clk.c, "msm_ehci_host"),
3251 CLK_LOOKUP("pwm_clk", div_clk2.c, "0-0048"),
3252
3253 /* Multimedia clocks */
3254 CLK_LOOKUP("byte_clk", mdss_byte0_clk.c, "fd922800.qcom,mdss_dsi"),
3255 CLK_LOOKUP("core_clk", mdss_esc0_clk.c, "fd922800.qcom,mdss_dsi"),
3256 CLK_LOOKUP("pixel_clk", mdss_pclk0_clk.c, "fd922800.qcom,mdss_dsi"),
3257 CLK_LOOKUP("iface_clk", mdss_ahb_clk.c, "mdss_dsi_clk_ctrl"),
3258
Adrian Salido-Morenof840a032013-03-01 23:10:03 -0800[diff] [blame]3259 CLK_LOOKUP("core_clk", mdss_mdp_clk.c, "fd900000.qcom,mdss_mdp"),
3260 CLK_LOOKUP("lut_clk", mdss_mdp_lut_clk.c, "fd900000.qcom,mdss_mdp"),
3261 CLK_LOOKUP("core_clk_src", mdp_clk_src.c, "fd900000.qcom,mdss_mdp"),
3262 CLK_LOOKUP("vsync_clk", mdss_vsync_clk.c, "fd900000.qcom,mdss_mdp"),
3263 CLK_LOOKUP("iface_clk", mdss_ahb_clk.c, "fd900000.qcom,mdss_mdp"),
3264 CLK_LOOKUP("bus_clk", mdss_axi_clk.c, "fd900000.qcom,mdss_mdp"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3265
3266 CLK_LOOKUP("iface_clk", mdss_ahb_clk.c, "fd928000.qcom,iommu"),
3267 CLK_LOOKUP("core_clk", mdss_axi_clk.c, "fd928000.qcom,iommu"),
3268
3269 /* MM sensor clocks */
Su Liud1c66ee2013-03-22 15:29:48 -0700[diff] [blame]3270 CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "6f.qcom,camera"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3271 CLK_LOOKUP("cam_src_clk", mclk1_clk_src.c, "90.qcom,camera"),
Su Liud1c66ee2013-03-22 15:29:48 -0700[diff] [blame]3272 CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "6d.qcom,camera"),
3273 CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "6f.qcom,camera"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3274 CLK_LOOKUP("cam_clk", camss_mclk1_clk.c, "90.qcom,camera"),
Su Liud1c66ee2013-03-22 15:29:48 -0700[diff] [blame]3275 CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "6d.qcom,camera"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3276
3277 /* CCI clocks */
3278 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3279 "fda0c000.qcom,cci"),
3280 CLK_LOOKUP("cci_ahb_clk", camss_cci_cci_ahb_clk.c,
3281 "fda0c000.qcom,cci"),
3282 CLK_LOOKUP("cci_src_clk", cci_clk_src.c, "fda0c000.qcom,cci"),
3283 CLK_LOOKUP("cci_clk", camss_cci_cci_clk.c, "fda0c000.qcom,cci"),
3284
3285 /* CSIPHY clocks */
3286 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3287 "fda0ac00.qcom,csiphy"),
3288 CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,
3289 "fda0ac00.qcom,csiphy"),
3290 CLK_LOOKUP("csiphy_timer_src_clk", csi0phytimer_clk_src.c,
3291 "fda0ac00.qcom,csiphy"),
3292 CLK_LOOKUP("csiphy_timer_clk", camss_phy0_csi0phytimer_clk.c,
3293 "fda0ac00.qcom,csiphy"),
3294 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3295 "fda0b000.qcom,csiphy"),
3296 CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,
3297 "fda0b000.qcom,csiphy"),
3298 CLK_LOOKUP("csiphy_timer_src_clk", csi1phytimer_clk_src.c,
3299 "fda0b000.qcom,csiphy"),
3300 CLK_LOOKUP("csiphy_timer_clk", camss_phy1_csi1phytimer_clk.c,
3301 "fda0b000.qcom,csiphy"),
3302
3303 /* CSID clocks */
3304 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3305 "fda08000.qcom,csid"),
3306 CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,
3307 "fda08000.qcom,csid"),
3308 CLK_LOOKUP("csi0_ahb_clk", camss_csi0_ahb_clk.c, "fda08000.qcom,csid"),
3309 CLK_LOOKUP("csi0_src_clk", csi0_clk_src.c, "fda08000.qcom,csid"),
3310 CLK_LOOKUP("csi0_phy_clk", camss_csi0phy_clk.c, "fda08000.qcom,csid"),
3311 CLK_LOOKUP("csi0_clk", camss_csi0_clk.c, "fda08000.qcom,csid"),
3312 CLK_LOOKUP("csi0_pix_clk", camss_csi0pix_clk.c, "fda08000.qcom,csid"),
3313 CLK_LOOKUP("csi0_rdi_clk", camss_csi0rdi_clk.c, "fda08000.qcom,csid"),
3314
3315 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3316 "fda08400.qcom,csid"),
3317 CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,
3318 "fda08400.qcom,csid"),
3319 CLK_LOOKUP("csi0_ahb_clk", camss_csi0_ahb_clk.c, "fda08400.qcom,csid"),
3320 CLK_LOOKUP("csi1_ahb_clk", camss_csi1_ahb_clk.c, "fda08400.qcom,csid"),
3321 CLK_LOOKUP("csi0_src_clk", csi0_clk_src.c, "fda08400.qcom,csid"),
3322 CLK_LOOKUP("csi1_src_clk", csi1_clk_src.c, "fda08400.qcom,csid"),
3323 CLK_LOOKUP("csi0_phy_clk", camss_csi0phy_clk.c, "fda08400.qcom,csid"),
3324 CLK_LOOKUP("csi1_phy_clk", camss_csi1phy_clk.c, "fda08400.qcom,csid"),
3325 CLK_LOOKUP("csi0_pix_clk", camss_csi0pix_clk.c, "fda08400.qcom,csid"),
3326 CLK_LOOKUP("csi1_pix_clk", camss_csi1pix_clk.c, "fda08400.qcom,csid"),
3327 CLK_LOOKUP("csi0_rdi_clk", camss_csi0rdi_clk.c, "fda08400.qcom,csid"),
3328 CLK_LOOKUP("csi1_rdi_clk", camss_csi1rdi_clk.c, "fda08400.qcom,csid"),
3329
3330 /* ISPIF clocks */
Sreesudhan Ramakrish Ramkumarecdcfce2013-04-17 12:58:26 -0700[diff] [blame]3331 CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,
3332 "fda0a000.qcom,ispif"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3333 CLK_LOOKUP("camss_vfe_vfe_clk", camss_vfe_vfe0_clk.c,
3334 "fda0a000.qcom,ispif"),
3335 CLK_LOOKUP("camss_csi_vfe_clk", camss_csi_vfe0_clk.c,
3336 "fda0a000.qcom,ispif"),
3337
3338 /* VFE clocks */
3339 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3340 "fda10000.qcom,vfe"),
3341 CLK_LOOKUP("vfe_clk_src", vfe0_clk_src.c, "fda10000.qcom,vfe"),
3342 CLK_LOOKUP("camss_vfe_vfe_clk", camss_vfe_vfe0_clk.c,
3343 "fda10000.qcom,vfe"),
3344 CLK_LOOKUP("camss_csi_vfe_clk", camss_csi_vfe0_clk.c,
3345 "fda10000.qcom,vfe"),
3346 CLK_LOOKUP("iface_clk", camss_vfe_vfe_ahb_clk.c, "fda10000.qcom,vfe"),
3347 CLK_LOOKUP("bus_clk", camss_vfe_vfe_axi_clk.c, "fda10000.qcom,vfe"),
3348
3349 CLK_LOOKUP("iface_clk", camss_vfe_vfe_ahb_clk.c,
3350 "fda44000.qcom,iommu"),
3351 CLK_LOOKUP("core_clk", camss_vfe_vfe_axi_clk.c, "fda44000.qcom,iommu"),
3352 CLK_LOOKUP("alt_core_clk", camss_top_ahb_clk.c, "fda44000.qcom,iommu"),
3353
3354 /* Jpeg Clocks */
3355 CLK_LOOKUP("core_clk", camss_jpeg_jpeg0_clk.c, "fda1c000.qcom,jpeg"),
3356 CLK_LOOKUP("iface_clk", camss_jpeg_jpeg_ahb_clk.c,
3357 "fda1c000.qcom,jpeg"),
3358 CLK_LOOKUP("bus_clk0", camss_jpeg_jpeg_axi_clk.c,
3359 "fda1c000.qcom,jpeg"),
3360 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3361 "fda1c000.qcom,jpeg"),
3362
3363 CLK_LOOKUP("alt_core_clk", camss_top_ahb_clk.c, "fda64000.qcom,iommu"),
3364 CLK_LOOKUP("iface_clk", camss_jpeg_jpeg_ahb_clk.c,
3365 "fda64000.qcom,iommu"),
3366 CLK_LOOKUP("core_clk", camss_jpeg_jpeg_axi_clk.c,
3367 "fda64000.qcom,iommu"),
3368
Su Liudb7b2062013-03-14 20:57:15 -0700[diff] [blame]3369 CLK_LOOKUP("micro_iface_clk", camss_micro_ahb_clk.c,
3370 "fda04000.qcom,cpp"),
3371 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3372 "fda04000.qcom,cpp"),
3373 CLK_LOOKUP("cpp_iface_clk", camss_vfe_cpp_ahb_clk.c,
3374 "fda04000.qcom,cpp"),
3375 CLK_LOOKUP("cpp_core_clk", camss_vfe_cpp_clk.c, "fda04000.qcom,cpp"),
3376 CLK_LOOKUP("cpp_bus_clk", camss_vfe_vfe_axi_clk.c, "fda04000.qcom,cpp"),
3377 CLK_LOOKUP("vfe_clk_src", vfe0_clk_src.c, "fda04000.qcom,cpp"),
3378 CLK_LOOKUP("camss_vfe_vfe_clk", camss_vfe_vfe0_clk.c,
3379 "fda04000.qcom,cpp"),
3380 CLK_LOOKUP("iface_clk", camss_vfe_vfe_ahb_clk.c, "fda04000.qcom,cpp"),
3381
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3382 /* KGSL Clocks */
3383 CLK_LOOKUP("core_clk", oxili_gfx3d_clk.c, "fdb00000.qcom,kgsl-3d0"),
3384 CLK_LOOKUP("iface_clk", oxilicx_ahb_clk.c, "fdb00000.qcom,kgsl-3d0"),
liu zhongc45eb8b2013-02-21 11:50:24 -0800[diff] [blame]3385 CLK_LOOKUP("mem_iface_clk", oxilicx_axi_clk.c,
3386 "fdb00000.qcom,kgsl-3d0"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3387
3388 CLK_LOOKUP("alt_core_clk", oxili_gfx3d_clk.c, "fdb10000.qcom,iommu"),
3389 CLK_LOOKUP("iface_clk", oxilicx_ahb_clk.c, "fdb10000.qcom,iommu"),
3390 CLK_LOOKUP("core_clk", oxilicx_axi_clk.c, "fdb10000.qcom,iommu"),
3391
3392 CLK_LOOKUP("core_clk", ocmemgx_core_clk.c, "fdd00000.qcom,ocmem"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3393
3394 /* Venus Clocks */
3395 CLK_LOOKUP("core_clk", venus0_vcodec0_clk.c, "fdc00000.qcom,vidc"),
3396 CLK_LOOKUP("iface_clk", venus0_ahb_clk.c, "fdc00000.qcom,vidc"),
3397 CLK_LOOKUP("bus_clk", venus0_axi_clk.c, "fdc00000.qcom,vidc"),
3398
3399 CLK_LOOKUP("alt_core_clk", venus0_vcodec0_clk.c,
3400 "fdc84000.qcom,iommu"),
3401 CLK_LOOKUP("iface_clk", venus0_ahb_clk.c, "fdc84000.qcom,iommu"),
3402 CLK_LOOKUP("core_clk", venus0_axi_clk.c, "fdc84000.qcom,iommu"),
Hariprasad Dhalinarasimha92a13222013-03-12 11:59:28 -0700[diff] [blame]3403 CLK_LOOKUP("iface_clk", gcc_prng_ahb_clk.c, "f9bff000.qcom,msm-rng"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3404 CLK_LOOKUP("cam_gp0_clk", camss_gp0_clk.c, ""),
3405 CLK_LOOKUP("cam_gp1_clk", camss_gp1_clk.c, ""),
3406 CLK_LOOKUP("iface_clk", camss_micro_ahb_clk.c, ""),
3407
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3408 CLK_LOOKUP("", mmss_mmssnoc_bto_ahb_clk.c, ""),
3409 CLK_LOOKUP("", mmss_mmssnoc_axi_clk.c, ""),
3410 CLK_LOOKUP("", mmss_s0_axi_clk.c, ""),
Bhalchandra Gajared5a4ba72013-03-11 16:15:13 -0700[diff] [blame]3411
3412 /* Audio clocks */
3413 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.224"),
3414 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.4106"),
3415 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.16384"),
3416 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.16386"),
3417 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.16390"),
3418 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.16391"),
3419
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3420};
3421
3422static struct clk_lookup msm_clocks_8226_rumi[] = {
3423 CLK_DUMMY("core_clk", BLSP1_UART_CLK, "f991f000.serial", OFF),
3424 CLK_DUMMY("iface_clk", BLSP1_UART_CLK, "f991f000.serial", OFF),
3425 CLK_DUMMY("iface_clk", HSUSB_IFACE_CLK, "f9a55000.usb", OFF),
3426 CLK_DUMMY("core_clk", HSUSB_CORE_CLK, "f9a55000.usb", OFF),
3427 CLK_DUMMY("iface_clk", NULL, "msm_sdcc.1", OFF),
3428 CLK_DUMMY("core_clk", NULL, "msm_sdcc.1", OFF),
3429 CLK_DUMMY("bus_clk", NULL, "msm_sdcc.1", OFF),
3430 CLK_DUMMY("iface_clk", NULL, "msm_sdcc.2", OFF),
3431 CLK_DUMMY("core_clk", NULL, "msm_sdcc.2", OFF),
3432 CLK_DUMMY("bus_clk", NULL, "msm_sdcc.2", OFF),
3433};
3434
3435struct clock_init_data msm8226_rumi_clock_init_data __initdata = {
3436 .table = msm_clocks_8226_rumi,
3437 .size = ARRAY_SIZE(msm_clocks_8226_rumi),
3438};
3439
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3440static void __init reg_init(void)
3441{
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]3442 u32 regval;
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3443
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3444 /* Vote for GPLL0 to turn on. Needed by acpuclock. */
3445 regval = readl_relaxed(GCC_REG_BASE(APCS_GPLL_ENA_VOTE));
3446 regval |= BIT(0);
3447 writel_relaxed(regval, GCC_REG_BASE(APCS_GPLL_ENA_VOTE));
3448
3449 /*
Patrick Daly3668dd62013-03-04 20:27:55 -0800[diff] [blame]3450 * No clocks need to be enabled during sleep.
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3451 */
3452 writel_relaxed(0x0, GCC_REG_BASE(APCS_CLOCK_SLEEP_ENA_VOTE));
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3453}
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]3454
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3455static void __init msm8226_clock_post_init(void)
3456{
Vikram Mulukutla441db7a2013-03-15 13:56:33 -0700[diff] [blame]3457 /*
3458 * Hold an active set vote for CXO; this is because CXO is expected
3459 * to remain on whenever CPUs aren't power collapsed.
3460 */
3461 clk_prepare_enable(&xo_a_clk.c);
3462
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3463 /* Set rates for single-rate clocks. */
3464 clk_set_rate(&usb_hs_system_clk_src.c,
3465 usb_hs_system_clk_src.freq_tbl[0].freq_hz);
3466 clk_set_rate(&usb_hsic_clk_src.c,
3467 usb_hsic_clk_src.freq_tbl[0].freq_hz);
3468 clk_set_rate(&usb_hsic_io_cal_clk_src.c,
3469 usb_hsic_io_cal_clk_src.freq_tbl[0].freq_hz);
3470 clk_set_rate(&usb_hsic_system_clk_src.c,
3471 usb_hsic_system_clk_src.freq_tbl[0].freq_hz);
3472 clk_set_rate(&pdm2_clk_src.c, pdm2_clk_src.freq_tbl[0].freq_hz);
3473 clk_set_rate(&cci_clk_src.c, cci_clk_src.freq_tbl[0].freq_hz);
3474 clk_set_rate(&mclk0_clk_src.c, mclk0_clk_src.freq_tbl[0].freq_hz);
3475 clk_set_rate(&mclk1_clk_src.c, mclk1_clk_src.freq_tbl[0].freq_hz);
3476 clk_set_rate(&esc0_clk_src.c, esc0_clk_src.freq_tbl[0].freq_hz);
3477 clk_set_rate(&vsync_clk_src.c, vsync_clk_src.freq_tbl[0].freq_hz);
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3478}
3479
3480#define GCC_CC_PHYS 0xFC400000
3481#define GCC_CC_SIZE SZ_16K
3482
3483#define MMSS_CC_PHYS 0xFD8C0000
3484#define MMSS_CC_SIZE SZ_256K
3485
3486#define LPASS_CC_PHYS 0xFE000000
3487#define LPASS_CC_SIZE SZ_256K
3488
3489#define APCS_KPSS_SH_PLL_PHYS 0xF9016000
3490#define APCS_KPSS_SH_PLL_SIZE SZ_64
3491
3492#define APCS_KPSS_GLB_PHYS 0xF9011000
3493#define APCS_KPSS_GLB_SIZE SZ_4K
3494
3495
3496static void __init msm8226_clock_pre_init(void)
3497{
3498 virt_bases[GCC_BASE] = ioremap(GCC_CC_PHYS, GCC_CC_SIZE);
3499 if (!virt_bases[GCC_BASE])
3500 panic("clock-8226: Unable to ioremap GCC memory!");
3501
3502 virt_bases[MMSS_BASE] = ioremap(MMSS_CC_PHYS, MMSS_CC_SIZE);
3503 if (!virt_bases[MMSS_BASE])
3504 panic("clock-8226: Unable to ioremap MMSS_CC memory!");
3505
3506 virt_bases[LPASS_BASE] = ioremap(LPASS_CC_PHYS, LPASS_CC_SIZE);
3507 if (!virt_bases[LPASS_BASE])
3508 panic("clock-8226: Unable to ioremap LPASS_CC memory!");
3509
3510 virt_bases[APCS_BASE] = ioremap(APCS_KPSS_GLB_PHYS,
3511 APCS_KPSS_GLB_SIZE);
3512 if (!virt_bases[APCS_BASE])
3513 panic("clock-8226: Unable to ioremap APCS_GCC_CC memory!");
3514
3515 virt_bases[APCS_PLL_BASE] = ioremap(APCS_KPSS_SH_PLL_PHYS,
3516 APCS_KPSS_SH_PLL_SIZE);
3517 if (!virt_bases[APCS_PLL_BASE])
3518 panic("clock-8226: Unable to ioremap APCS_GCC_CC memory!");
3519
3520 clk_ops_local_pll.enable = sr_hpm_lp_pll_clk_enable;
3521
Patrick Dalyebc26bc2013-02-05 11:49:07 -0800[diff] [blame]3522 vdd_dig.regulator[0] = regulator_get(NULL, "vdd_dig");
3523 if (IS_ERR(vdd_dig.regulator[0]))
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3524 panic("clock-8226: Unable to get the vdd_dig regulator!");
3525
Patrick Dalyebc26bc2013-02-05 11:49:07 -0800[diff] [blame]3526 vdd_sr2_pll.regulator[0] = regulator_get(NULL, "vdd_sr2_pll");
3527 if (IS_ERR(vdd_sr2_pll.regulator[0]))
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]3528 panic("clock-8226: Unable to get the sr2_pll regulator!");
3529
Patrick Daly6fb589a2013-03-29 17:55:55 -0700[diff] [blame]3530 vdd_sr2_pll.regulator[1] = regulator_get(NULL, "vdd_sr2_dig");
3531 if (IS_ERR(vdd_sr2_pll.regulator[1]))
3532 panic("clock-8226: Unable to get the vdd_sr2_dig regulator!");
3533
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]3534 /*
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3535 * Hold an active set vote at a rate of 40MHz for the MMSS NOC AHB
3536 * source. Sleep set vote is 0.
3537 * RPM will also turn on gcc_mmss_noc_cfg_ahb_clk, which is needed to
3538 * access mmss clock controller registers.
3539 */
3540 clk_set_rate(&mmssnoc_ahb_a_clk.c, 40000000);
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3541
Vikram Mulukutla29a06a32013-03-14 10:54:02 -0700[diff] [blame]3542 /* Set an initial rate (fmax at nominal) on the MMSSNOC AXI clock */
3543 clk_set_rate(&axi_clk_src.c, 200000000);
3544
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3545 enable_rpm_scaling();
3546
3547 reg_init();
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]3548
3549 /*
3550 * MDSS needs the ahb clock and needs to init before we register the
3551 * lookup table.
3552 */
3553 mdss_clk_ctrl_pre_init(&mdss_ahb_clk.c);
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3554}
3555
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3556struct clock_init_data msm8226_clock_init_data __initdata = {
3557 .table = msm_clocks_8226,
3558 .size = ARRAY_SIZE(msm_clocks_8226),
3559 .pre_init = msm8226_clock_pre_init,
3560 .post_init = msm8226_clock_post_init,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3561};