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gerrit-public.fairphone.software / fp2-dev / kernel / msm / 44ea66879d5638cfed5b5ecf628badfd8ec26f36 / . / drivers / infiniband / hw / mthca / mthca_dev.h
blob: f437979e8967c8ed425de62012e0cce36d63a5fb [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 * $Id: mthca_dev.h 1349 2004-12-16 21:09:43Z roland $
33 */
34
35#ifndef MTHCA_DEV_H
36#define MTHCA_DEV_H
37
38#include <linux/spinlock.h>
39#include <linux/kernel.h>
40#include <linux/pci.h>
41#include <linux/dma-mapping.h>
42#include <asm/semaphore.h>
43
44#include "mthca_provider.h"
45#include "mthca_doorbell.h"
46
47#define DRV_NAME "ib_mthca"
48#define PFX DRV_NAME ": "
49#define DRV_VERSION "0.06-pre"
50#define DRV_RELDATE "November 8, 2004"
51
52/* Types of supported HCA */
53enum {
54 TAVOR, /* MT23108 */
55 ARBEL_COMPAT, /* MT25208 in Tavor compat mode */
56 ARBEL_NATIVE /* MT25208 with extended features */
57};
58
59enum {
60 MTHCA_FLAG_DDR_HIDDEN = 1 << 1,
61 MTHCA_FLAG_SRQ = 1 << 2,
62 MTHCA_FLAG_MSI = 1 << 3,
63 MTHCA_FLAG_MSI_X = 1 << 4,
64 MTHCA_FLAG_NO_LAM = 1 << 5
65};
66
67enum {
68 MTHCA_MAX_PORTS = 2
69};
70
71enum {
72 MTHCA_EQ_CONTEXT_SIZE = 0x40,
73 MTHCA_CQ_CONTEXT_SIZE = 0x40,
74 MTHCA_QP_CONTEXT_SIZE = 0x200,
75 MTHCA_RDB_ENTRY_SIZE = 0x20,
76 MTHCA_AV_SIZE = 0x20,
77 MTHCA_MGM_ENTRY_SIZE = 0x40,
78
79 /* Arbel FW gives us these, but we need them for Tavor */
80 MTHCA_MPT_ENTRY_SIZE = 0x40,
81 MTHCA_MTT_SEG_SIZE = 0x40,
82};
83
84enum {
85 MTHCA_EQ_CMD,
86 MTHCA_EQ_ASYNC,
87 MTHCA_EQ_COMP,
88 MTHCA_NUM_EQ
89};
90
91struct mthca_cmd {
92 int use_events;
93 struct semaphore hcr_sem;
94 struct semaphore poll_sem;
95 struct semaphore event_sem;
96 int max_cmds;
97 spinlock_t context_lock;
98 int free_head;
99 struct mthca_cmd_context *context;
100 u16 token_mask;
101};
102
103struct mthca_limits {
104 int num_ports;
105 int vl_cap;
106 int mtu_cap;
107 int gid_table_len;
108 int pkey_table_len;
109 int local_ca_ack_delay;
110 int num_uars;
111 int max_sg;
112 int num_qps;
113 int reserved_qps;
114 int num_srqs;
115 int reserved_srqs;
116 int num_eecs;
117 int reserved_eecs;
118 int num_cqs;
119 int reserved_cqs;
120 int num_eqs;
121 int reserved_eqs;
122 int num_mpts;
123 int num_mtt_segs;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]124 int reserved_mtts;
125 int reserved_mrws;
126 int reserved_uars;
127 int num_mgms;
128 int num_amgms;
129 int reserved_mcgs;
130 int num_pds;
131 int reserved_pds;
132};
133
134struct mthca_alloc {
135 u32 last;
136 u32 top;
137 u32 max;
138 u32 mask;
139 spinlock_t lock;
140 unsigned long *table;
141};
142
143struct mthca_array {
144 struct {
145 void **page;
146 int used;
147 } *page_list;
148};
149
150struct mthca_uar_table {
151 struct mthca_alloc alloc;
152 u64 uarc_base;
153 int uarc_size;
154};
155
156struct mthca_pd_table {
157 struct mthca_alloc alloc;
158};
159
160struct mthca_mr_table {
161 struct mthca_alloc mpt_alloc;
162 int max_mtt_order;
163 unsigned long **mtt_buddy;
164 u64 mtt_base;
165 struct mthca_icm_table *mtt_table;
166 struct mthca_icm_table *mpt_table;
167};
168
169struct mthca_eq_table {
170 struct mthca_alloc alloc;
171 void __iomem *clr_int;
172 u32 clr_mask;
173 u32 arm_mask;
174 struct mthca_eq eq[MTHCA_NUM_EQ];
175 u64 icm_virt;
176 struct page *icm_page;
177 dma_addr_t icm_dma;
178 int have_irq;
179 u8 inta_pin;
180};
181
182struct mthca_cq_table {
183 struct mthca_alloc alloc;
184 spinlock_t lock;
185 struct mthca_array cq;
186 struct mthca_icm_table *table;
187};
188
189struct mthca_qp_table {
190 struct mthca_alloc alloc;
191 u32 rdb_base;
192 int rdb_shift;
193 int sqp_start;
194 spinlock_t lock;
195 struct mthca_array qp;
196 struct mthca_icm_table *qp_table;
197 struct mthca_icm_table *eqp_table;
198};
199
200struct mthca_av_table {
201 struct pci_pool *pool;
202 int num_ddr_avs;
203 u64 ddr_av_base;
204 void __iomem *av_map;
205 struct mthca_alloc alloc;
206};
207
208struct mthca_mcg_table {
209 struct semaphore sem;
210 struct mthca_alloc alloc;
211 struct mthca_icm_table *table;
212};
213
214struct mthca_dev {
215 struct ib_device ib_dev;
216 struct pci_dev *pdev;
217
218 int hca_type;
219 unsigned long mthca_flags;
220 unsigned long device_cap_flags;
221
222 u32 rev_id;
223
224 /* firmware info */
225 u64 fw_ver;
226 union {
227 struct {
228 u64 fw_start;
229 u64 fw_end;
230 } tavor;
231 struct {
232 u64 clr_int_base;
233 u64 eq_arm_base;
234 u64 eq_set_ci_base;
235 struct mthca_icm *fw_icm;
236 struct mthca_icm *aux_icm;
237 u16 fw_pages;
238 } arbel;
239 } fw;
240
241 u64 ddr_start;
242 u64 ddr_end;
243
244 MTHCA_DECLARE_DOORBELL_LOCK(doorbell_lock)
245 struct semaphore cap_mask_mutex;
246
247 void __iomem *hcr;
248 void __iomem *kar;
249 void __iomem *clr_base;
250 union {
251 struct {
252 void __iomem *ecr_base;
253 } tavor;
254 struct {
255 void __iomem *eq_arm;
256 void __iomem *eq_set_ci_base;
257 } arbel;
258 } eq_regs;
259
260 struct mthca_cmd cmd;
261 struct mthca_limits limits;
262
263 struct mthca_uar_table uar_table;
264 struct mthca_pd_table pd_table;
265 struct mthca_mr_table mr_table;
266 struct mthca_eq_table eq_table;
267 struct mthca_cq_table cq_table;
268 struct mthca_qp_table qp_table;
269 struct mthca_av_table av_table;
270 struct mthca_mcg_table mcg_table;
271
272 struct mthca_uar driver_uar;
273 struct mthca_db_table *db_tab;
274 struct mthca_pd driver_pd;
275 struct mthca_mr driver_mr;
276
277 struct ib_mad_agent *send_agent[MTHCA_MAX_PORTS][2];
278 struct ib_ah *sm_ah[MTHCA_MAX_PORTS];
279 spinlock_t sm_lock;
280};
281
282#define mthca_dbg(mdev, format, arg...) \
283 dev_dbg(&mdev->pdev->dev, format, ## arg)
284#define mthca_err(mdev, format, arg...) \
285 dev_err(&mdev->pdev->dev, format, ## arg)
286#define mthca_info(mdev, format, arg...) \
287 dev_info(&mdev->pdev->dev, format, ## arg)
288#define mthca_warn(mdev, format, arg...) \
289 dev_warn(&mdev->pdev->dev, format, ## arg)
290
291extern void __buggy_use_of_MTHCA_GET(void);
292extern void __buggy_use_of_MTHCA_PUT(void);
293
294#define MTHCA_GET(dest, source, offset) \
295 do { \
296 void *__p = (char *) (source) + (offset); \
297 switch (sizeof (dest)) { \
298 case 1: (dest) = *(u8 *) __p; break; \
299 case 2: (dest) = be16_to_cpup(__p); break; \
300 case 4: (dest) = be32_to_cpup(__p); break; \
301 case 8: (dest) = be64_to_cpup(__p); break; \
302 default: __buggy_use_of_MTHCA_GET(); \
303 } \
304 } while (0)
305
306#define MTHCA_PUT(dest, source, offset) \
307 do { \
308 __typeof__(source) *__p = \
309 (__typeof__(source) *) ((char *) (dest) + (offset)); \
310 switch (sizeof(source)) { \
311 case 1: *__p = (source); break; \
312 case 2: *__p = cpu_to_be16(source); break; \
313 case 4: *__p = cpu_to_be32(source); break; \
314 case 8: *__p = cpu_to_be64(source); break; \
315 default: __buggy_use_of_MTHCA_PUT(); \
316 } \
317 } while (0)
318
319int mthca_reset(struct mthca_dev *mdev);
320
321u32 mthca_alloc(struct mthca_alloc *alloc);
322void mthca_free(struct mthca_alloc *alloc, u32 obj);
323int mthca_alloc_init(struct mthca_alloc *alloc, u32 num, u32 mask,
324 u32 reserved);
325void mthca_alloc_cleanup(struct mthca_alloc *alloc);
326void *mthca_array_get(struct mthca_array *array, int index);
327int mthca_array_set(struct mthca_array *array, int index, void *value);
328void mthca_array_clear(struct mthca_array *array, int index);
329int mthca_array_init(struct mthca_array *array, int nent);
330void mthca_array_cleanup(struct mthca_array *array, int nent);
331
332int mthca_init_uar_table(struct mthca_dev *dev);
333int mthca_init_pd_table(struct mthca_dev *dev);
334int mthca_init_mr_table(struct mthca_dev *dev);
335int mthca_init_eq_table(struct mthca_dev *dev);
336int mthca_init_cq_table(struct mthca_dev *dev);
337int mthca_init_qp_table(struct mthca_dev *dev);
338int mthca_init_av_table(struct mthca_dev *dev);
339int mthca_init_mcg_table(struct mthca_dev *dev);
340
341void mthca_cleanup_uar_table(struct mthca_dev *dev);
342void mthca_cleanup_pd_table(struct mthca_dev *dev);
343void mthca_cleanup_mr_table(struct mthca_dev *dev);
344void mthca_cleanup_eq_table(struct mthca_dev *dev);
345void mthca_cleanup_cq_table(struct mthca_dev *dev);
346void mthca_cleanup_qp_table(struct mthca_dev *dev);
347void mthca_cleanup_av_table(struct mthca_dev *dev);
348void mthca_cleanup_mcg_table(struct mthca_dev *dev);
349
350int mthca_register_device(struct mthca_dev *dev);
351void mthca_unregister_device(struct mthca_dev *dev);
352
353int mthca_uar_alloc(struct mthca_dev *dev, struct mthca_uar *uar);
354void mthca_uar_free(struct mthca_dev *dev, struct mthca_uar *uar);
355
356int mthca_pd_alloc(struct mthca_dev *dev, struct mthca_pd *pd);
357void mthca_pd_free(struct mthca_dev *dev, struct mthca_pd *pd);
358
359int mthca_mr_alloc_notrans(struct mthca_dev *dev, u32 pd,
360 u32 access, struct mthca_mr *mr);
361int mthca_mr_alloc_phys(struct mthca_dev *dev, u32 pd,
362 u64 *buffer_list, int buffer_size_shift,
363 int list_len, u64 iova, u64 total_size,
364 u32 access, struct mthca_mr *mr);
365void mthca_free_mr(struct mthca_dev *dev, struct mthca_mr *mr);
366
367int mthca_map_eq_icm(struct mthca_dev *dev, u64 icm_virt);
368void mthca_unmap_eq_icm(struct mthca_dev *dev);
369
370int mthca_poll_cq(struct ib_cq *ibcq, int num_entries,
371 struct ib_wc *entry);
372int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify);
373int mthca_arbel_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify);
374int mthca_init_cq(struct mthca_dev *dev, int nent,
375 struct mthca_cq *cq);
376void mthca_free_cq(struct mthca_dev *dev,
377 struct mthca_cq *cq);
378void mthca_cq_event(struct mthca_dev *dev, u32 cqn);
379void mthca_cq_clean(struct mthca_dev *dev, u32 cqn, u32 qpn);
380
381void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
382 enum ib_event_type event_type);
383int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask);
384int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
385 struct ib_send_wr **bad_wr);
386int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
387 struct ib_recv_wr **bad_wr);
388int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
389 struct ib_send_wr **bad_wr);
390int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
391 struct ib_recv_wr **bad_wr);
392int mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
393 int index, int *dbd, u32 *new_wqe);
394int mthca_alloc_qp(struct mthca_dev *dev,
395 struct mthca_pd *pd,
396 struct mthca_cq *send_cq,
397 struct mthca_cq *recv_cq,
398 enum ib_qp_type type,
399 enum ib_sig_type send_policy,
400 struct mthca_qp *qp);
401int mthca_alloc_sqp(struct mthca_dev *dev,
402 struct mthca_pd *pd,
403 struct mthca_cq *send_cq,
404 struct mthca_cq *recv_cq,
405 enum ib_sig_type send_policy,
406 int qpn,
407 int port,
408 struct mthca_sqp *sqp);
409void mthca_free_qp(struct mthca_dev *dev, struct mthca_qp *qp);
410int mthca_create_ah(struct mthca_dev *dev,
411 struct mthca_pd *pd,
412 struct ib_ah_attr *ah_attr,
413 struct mthca_ah *ah);
414int mthca_destroy_ah(struct mthca_dev *dev, struct mthca_ah *ah);
415int mthca_read_ah(struct mthca_dev *dev, struct mthca_ah *ah,
416 struct ib_ud_header *header);
417
418int mthca_multicast_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid);
419int mthca_multicast_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid);
420
421int mthca_process_mad(struct ib_device *ibdev,
422 int mad_flags,
423 u8 port_num,
424 struct ib_wc *in_wc,
425 struct ib_grh *in_grh,
426 struct ib_mad *in_mad,
427 struct ib_mad *out_mad);
428int mthca_create_agents(struct mthca_dev *dev);
429void mthca_free_agents(struct mthca_dev *dev);
430
431static inline struct mthca_dev *to_mdev(struct ib_device *ibdev)
432{
433 return container_of(ibdev, struct mthca_dev, ib_dev);
434}
435
436#endif /* MTHCA_DEV_H */