blob: 1e7be9eee9c3c4cf112293b59d51670b6887dfb9 [file] [log] [blame]
Jeff Garzik669a5db2006-08-29 18:12:40 -04001/*
2 * pata_via.c - VIA PATA for new ATA layer
3 * (C) 2005-2006 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * Documentation
7 * Most chipset documentation available under NDA only
8 *
9 * VIA version guide
10 * VIA VT82C561 - early design, uses ata_generic currently
11 * VIA VT82C576 - MWDMA, 33Mhz
12 * VIA VT82C586 - MWDMA, 33Mhz
13 * VIA VT82C586a - Added UDMA to 33Mhz
14 * VIA VT82C586b - UDMA33
15 * VIA VT82C596a - Nonfunctional UDMA66
16 * VIA VT82C596b - Working UDMA66
17 * VIA VT82C686 - Nonfunctional UDMA66
18 * VIA VT82C686a - Working UDMA66
19 * VIA VT82C686b - Updated to UDMA100
20 * VIA VT8231 - UDMA100
21 * VIA VT8233 - UDMA100
22 * VIA VT8233a - UDMA133
23 * VIA VT8233c - UDMA100
24 * VIA VT8235 - UDMA133
25 * VIA VT8237 - UDMA133
26 *
27 * Most registers remain compatible across chips. Others start reserved
28 * and acquire sensible semantics if set to 1 (eg cable detect). A few
29 * exceptions exist, notably around the FIFO settings.
30 *
31 * One additional quirk of the VIA design is that like ALi they use few
32 * PCI IDs for a lot of chips.
33 *
34 * Based heavily on:
35 *
36 * Version 3.38
37 *
38 * VIA IDE driver for Linux. Supported southbridges:
39 *
40 * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
41 * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
42 * vt8235, vt8237
43 *
44 * Copyright (c) 2000-2002 Vojtech Pavlik
45 *
46 * Based on the work of:
47 * Michel Aubry
48 * Jeff Garzik
49 * Andre Hedrick
50
51 */
52
53#include <linux/kernel.h>
54#include <linux/module.h>
55#include <linux/pci.h>
56#include <linux/init.h>
57#include <linux/blkdev.h>
58#include <linux/delay.h>
59#include <scsi/scsi_host.h>
60#include <linux/libata.h>
61
62#define DRV_NAME "pata_via"
Alan Coxc9619222006-09-26 17:53:38 +010063#define DRV_VERSION "0.1.14"
Jeff Garzik669a5db2006-08-29 18:12:40 -040064
65/*
66 * The following comes directly from Vojtech Pavlik's ide/pci/via82cxxx
67 * driver.
68 */
69
70enum {
71 VIA_UDMA = 0x007,
72 VIA_UDMA_NONE = 0x000,
73 VIA_UDMA_33 = 0x001,
74 VIA_UDMA_66 = 0x002,
75 VIA_UDMA_100 = 0x003,
76 VIA_UDMA_133 = 0x004,
77 VIA_BAD_PREQ = 0x010, /* Crashes if PREQ# till DDACK# set */
78 VIA_BAD_CLK66 = 0x020, /* 66 MHz clock doesn't work correctly */
79 VIA_SET_FIFO = 0x040, /* Needs to have FIFO split set */
80 VIA_NO_UNMASK = 0x080, /* Doesn't work with IRQ unmasking on */
81 VIA_BAD_ID = 0x100, /* Has wrong vendor ID (0x1107) */
82 VIA_BAD_AST = 0x200, /* Don't touch Address Setup Timing */
83 VIA_NO_ENABLES = 0x400, /* Has no enablebits */
84};
85
86/*
87 * VIA SouthBridge chips.
88 */
89
90static const struct via_isa_bridge {
91 const char *name;
92 u16 id;
93 u8 rev_min;
94 u8 rev_max;
95 u16 flags;
96} via_isa_bridges[] = {
97 { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
98 { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST | VIA_NO_ENABLES},
99 { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
100 { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
101 { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
102 { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
103 { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, VIA_UDMA_100 },
104 { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, VIA_UDMA_100 },
105 { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, VIA_UDMA_100 },
106 { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, VIA_UDMA_100 },
107 { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, VIA_UDMA_66 },
108 { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 },
109 { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, VIA_UDMA_66 },
110 { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 },
111 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, VIA_UDMA_33 | VIA_SET_FIFO },
112 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, VIA_UDMA_33 | VIA_SET_FIFO | VIA_BAD_PREQ },
113 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, VIA_UDMA_33 | VIA_SET_FIFO },
114 { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, VIA_UDMA_33 | VIA_SET_FIFO },
115 { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, VIA_UDMA_NONE | VIA_SET_FIFO },
116 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK },
117 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
118 { NULL }
119};
120
121/**
122 * via_cable_detect - cable detection
123 * @ap: ATA port
124 *
125 * Perform cable detection. Actually for the VIA case the BIOS
126 * already did this for us. We read the values provided by the
127 * BIOS. If you are using an 8235 in a non-PC configuration you
128 * may need to update this code.
129 *
130 * Hotplug also impacts on this.
131 */
132
133static int via_cable_detect(struct ata_port *ap) {
134 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
135 u32 ata66;
136
137 pci_read_config_dword(pdev, 0x50, &ata66);
138 /* Check both the drive cable reporting bits, we might not have
139 two drives */
140 if (ata66 & (0x10100000 >> (16 * ap->port_no)))
141 return ATA_CBL_PATA80;
142 else
143 return ATA_CBL_PATA40;
144}
145
146static int via_pre_reset(struct ata_port *ap)
147{
148 const struct via_isa_bridge *config = ap->host->private_data;
149
150 if (!(config->flags & VIA_NO_ENABLES)) {
151 static const struct pci_bits via_enable_bits[] = {
152 { 0x40, 1, 0x02, 0x02 },
153 { 0x40, 1, 0x01, 0x01 }
154 };
155
156 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400157
Alan Coxc9619222006-09-26 17:53:38 +0100158 if (!pci_test_config_bits(pdev, &via_enable_bits[ap->port_no]))
159 return -ENOENT;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400160 }
161
162 if ((config->flags & VIA_UDMA) >= VIA_UDMA_66)
163 ap->cbl = via_cable_detect(ap);
164 else
165 ap->cbl = ATA_CBL_PATA40;
166 return ata_std_prereset(ap);
167}
168
169
170/**
171 * via_error_handler - reset for VIA chips
172 * @ap: ATA port
173 *
174 * Handle the reset callback for the later chips with cable detect
175 */
176
177static void via_error_handler(struct ata_port *ap)
178{
179 ata_bmdma_drive_eh(ap, via_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
180}
181
182/**
183 * via_do_set_mode - set initial PIO mode data
184 * @ap: ATA interface
185 * @adev: ATA device
186 * @mode: ATA mode being programmed
187 * @tdiv: Clocks per PCI clock
188 * @set_ast: Set to program address setup
189 * @udma_type: UDMA mode/format of registers
190 *
191 * Program the VIA registers for DMA and PIO modes. Uses the ata timing
192 * support in order to compute modes.
193 *
194 * FIXME: Hotplug will require we serialize multiple mode changes
195 * on the two channels.
196 */
197
198static void via_do_set_mode(struct ata_port *ap, struct ata_device *adev, int mode, int tdiv, int set_ast, int udma_type)
199{
200 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
201 struct ata_device *peer = ata_dev_pair(adev);
202 struct ata_timing t, p;
203 static int via_clock = 33333; /* Bus clock in kHZ - ought to be tunable one day */
204 unsigned long T = 1000000000 / via_clock;
205 unsigned long UT = T/tdiv;
206 int ut;
207 int offset = 3 - (2*ap->port_no) - adev->devno;
208
209
210 /* Calculate the timing values we require */
211 ata_timing_compute(adev, mode, &t, T, UT);
212
213 /* We share 8bit timing so we must merge the constraints */
214 if (peer) {
215 if (peer->pio_mode) {
216 ata_timing_compute(peer, peer->pio_mode, &p, T, UT);
217 ata_timing_merge(&p, &t, &t, ATA_TIMING_8BIT);
218 }
219 }
220
221 /* Address setup is programmable but breaks on UDMA133 setups */
222 if (set_ast) {
223 u8 setup; /* 2 bits per drive */
224 int shift = 2 * offset;
225
226 pci_read_config_byte(pdev, 0x4C, &setup);
227 setup &= ~(3 << shift);
228 setup |= FIT(t.setup, 1, 4) << shift; /* 1,4 or 1,4 - 1 FIXME */
229 pci_write_config_byte(pdev, 0x4C, setup);
230 }
231
232 /* Load the PIO mode bits */
233 pci_write_config_byte(pdev, 0x4F - ap->port_no,
234 ((FIT(t.act8b, 1, 16) - 1) << 4) | (FIT(t.rec8b, 1, 16) - 1));
235 pci_write_config_byte(pdev, 0x48 + offset,
236 ((FIT(t.active, 1, 16) - 1) << 4) | (FIT(t.recover, 1, 16) - 1));
237
238 /* Load the UDMA bits according to type */
239 switch(udma_type) {
240 default:
241 /* BUG() ? */
242 /* fall through */
243 case 33:
244 ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 5) - 2)) : 0x03;
245 break;
246 case 66:
247 ut = t.udma ? (0xe8 | (FIT(t.udma, 2, 9) - 2)) : 0x0f;
248 break;
249 case 100:
250 ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 9) - 2)) : 0x07;
251 break;
252 case 133:
253 ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 9) - 2)) : 0x07;
254 break;
255 }
256 /* Set UDMA unless device is not UDMA capable */
257 if (udma_type)
258 pci_write_config_byte(pdev, 0x50 + offset, ut);
259}
260
261static void via_set_piomode(struct ata_port *ap, struct ata_device *adev)
262{
263 const struct via_isa_bridge *config = ap->host->private_data;
264 int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
265 int mode = config->flags & VIA_UDMA;
266 static u8 tclock[5] = { 1, 1, 2, 3, 4 };
267 static u8 udma[5] = { 0, 33, 66, 100, 133 };
268
269 via_do_set_mode(ap, adev, adev->pio_mode, tclock[mode], set_ast, udma[mode]);
270}
271
272static void via_set_dmamode(struct ata_port *ap, struct ata_device *adev)
273{
274 const struct via_isa_bridge *config = ap->host->private_data;
275 int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
276 int mode = config->flags & VIA_UDMA;
277 static u8 tclock[5] = { 1, 1, 2, 3, 4 };
278 static u8 udma[5] = { 0, 33, 66, 100, 133 };
279
280 via_do_set_mode(ap, adev, adev->dma_mode, tclock[mode], set_ast, udma[mode]);
281}
282
283static struct scsi_host_template via_sht = {
284 .module = THIS_MODULE,
285 .name = DRV_NAME,
286 .ioctl = ata_scsi_ioctl,
287 .queuecommand = ata_scsi_queuecmd,
288 .can_queue = ATA_DEF_QUEUE,
289 .this_id = ATA_SHT_THIS_ID,
290 .sg_tablesize = LIBATA_MAX_PRD,
291 .max_sectors = ATA_MAX_SECTORS,
292 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
293 .emulated = ATA_SHT_EMULATED,
294 .use_clustering = ATA_SHT_USE_CLUSTERING,
295 .proc_name = DRV_NAME,
296 .dma_boundary = ATA_DMA_BOUNDARY,
297 .slave_configure = ata_scsi_slave_config,
298 .bios_param = ata_std_bios_param,
299};
300
301static struct ata_port_operations via_port_ops = {
302 .port_disable = ata_port_disable,
303 .set_piomode = via_set_piomode,
304 .set_dmamode = via_set_dmamode,
305 .mode_filter = ata_pci_default_filter,
306
307 .tf_load = ata_tf_load,
308 .tf_read = ata_tf_read,
309 .check_status = ata_check_status,
310 .exec_command = ata_exec_command,
311 .dev_select = ata_std_dev_select,
312
313 .freeze = ata_bmdma_freeze,
314 .thaw = ata_bmdma_thaw,
315 .error_handler = via_error_handler,
316 .post_internal_cmd = ata_bmdma_post_internal_cmd,
317
318 .bmdma_setup = ata_bmdma_setup,
319 .bmdma_start = ata_bmdma_start,
320 .bmdma_stop = ata_bmdma_stop,
321 .bmdma_status = ata_bmdma_status,
322
323 .qc_prep = ata_qc_prep,
324 .qc_issue = ata_qc_issue_prot,
Jeff Garzikbda30282006-09-27 05:41:13 -0400325
Jeff Garzik669a5db2006-08-29 18:12:40 -0400326 .data_xfer = ata_pio_data_xfer,
327
328 .irq_handler = ata_interrupt,
329 .irq_clear = ata_bmdma_irq_clear,
330
331 .port_start = ata_port_start,
332 .port_stop = ata_port_stop,
333 .host_stop = ata_host_stop
334};
335
336static struct ata_port_operations via_port_ops_noirq = {
337 .port_disable = ata_port_disable,
338 .set_piomode = via_set_piomode,
339 .set_dmamode = via_set_dmamode,
340 .mode_filter = ata_pci_default_filter,
341
342 .tf_load = ata_tf_load,
343 .tf_read = ata_tf_read,
344 .check_status = ata_check_status,
345 .exec_command = ata_exec_command,
346 .dev_select = ata_std_dev_select,
347
348 .freeze = ata_bmdma_freeze,
349 .thaw = ata_bmdma_thaw,
350 .error_handler = via_error_handler,
351 .post_internal_cmd = ata_bmdma_post_internal_cmd,
352
353 .bmdma_setup = ata_bmdma_setup,
354 .bmdma_start = ata_bmdma_start,
355 .bmdma_stop = ata_bmdma_stop,
356 .bmdma_status = ata_bmdma_status,
357
358 .qc_prep = ata_qc_prep,
359 .qc_issue = ata_qc_issue_prot,
Jeff Garzikbda30282006-09-27 05:41:13 -0400360
Jeff Garzik669a5db2006-08-29 18:12:40 -0400361 .data_xfer = ata_pio_data_xfer_noirq,
362
363 .irq_handler = ata_interrupt,
364 .irq_clear = ata_bmdma_irq_clear,
365
366 .port_start = ata_port_start,
367 .port_stop = ata_port_stop,
368 .host_stop = ata_host_stop
369};
370
371/**
372 * via_init_one - discovery callback
373 * @pdev: PCI device ID
374 * @id: PCI table info
375 *
376 * A VIA IDE interface has been discovered. Figure out what revision
377 * and perform configuration work before handing it to the ATA layer
378 */
379
380static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
381{
382 /* Early VIA without UDMA support */
383 static struct ata_port_info via_mwdma_info = {
384 .sht = &via_sht,
385 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
386 .pio_mask = 0x1f,
387 .mwdma_mask = 0x07,
388 .port_ops = &via_port_ops
389 };
390 /* Ditto with IRQ masking required */
391 static struct ata_port_info via_mwdma_info_borked = {
392 .sht = &via_sht,
393 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
394 .pio_mask = 0x1f,
395 .mwdma_mask = 0x07,
396 .port_ops = &via_port_ops_noirq,
397 };
398 /* VIA UDMA 33 devices (and borked 66) */
399 static struct ata_port_info via_udma33_info = {
400 .sht = &via_sht,
401 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
402 .pio_mask = 0x1f,
403 .mwdma_mask = 0x07,
404 .udma_mask = 0x7,
405 .port_ops = &via_port_ops
406 };
407 /* VIA UDMA 66 devices */
408 static struct ata_port_info via_udma66_info = {
409 .sht = &via_sht,
410 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
411 .pio_mask = 0x1f,
412 .mwdma_mask = 0x07,
413 .udma_mask = 0x1f,
414 .port_ops = &via_port_ops
415 };
416 /* VIA UDMA 100 devices */
417 static struct ata_port_info via_udma100_info = {
418 .sht = &via_sht,
419 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
420 .pio_mask = 0x1f,
421 .mwdma_mask = 0x07,
422 .udma_mask = 0x3f,
423 .port_ops = &via_port_ops
424 };
425 /* UDMA133 with bad AST (All current 133) */
426 static struct ata_port_info via_udma133_info = {
427 .sht = &via_sht,
428 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
429 .pio_mask = 0x1f,
430 .mwdma_mask = 0x07,
431 .udma_mask = 0x7f, /* FIXME: should check north bridge */
432 .port_ops = &via_port_ops
433 };
434 struct ata_port_info *port_info[2], *type;
435 struct pci_dev *isa = NULL;
436 const struct via_isa_bridge *config;
437 static int printed_version;
438 u8 t;
439 u8 enable;
440 u32 timing;
441
442 if (!printed_version++)
443 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
444
445 /* To find out how the IDE will behave and what features we
446 actually have to look at the bridge not the IDE controller */
447 for (config = via_isa_bridges; config->id; config++)
448 if ((isa = pci_get_device(PCI_VENDOR_ID_VIA +
449 !!(config->flags & VIA_BAD_ID),
450 config->id, NULL))) {
451
452 pci_read_config_byte(isa, PCI_REVISION_ID, &t);
453 if (t >= config->rev_min &&
454 t <= config->rev_max)
455 break;
456 pci_dev_put(isa);
457 }
458
459 if (!config->id) {
460 printk(KERN_WARNING "via: Unknown VIA SouthBridge, disabling.\n");
461 return -ENODEV;
462 }
463 pci_dev_put(isa);
464
465 /* 0x40 low bits indicate enabled channels */
466 pci_read_config_byte(pdev, 0x40 , &enable);
467 enable &= 3;
468 if (enable == 0) {
469 return -ENODEV;
470 }
471
472 /* Initialise the FIFO for the enabled channels. */
473 if (config->flags & VIA_SET_FIFO) {
474 u8 fifo_setting[4] = {0x00, 0x60, 0x00, 0x20};
475 u8 fifo;
476
477 pci_read_config_byte(pdev, 0x43, &fifo);
478
479 /* Clear PREQ# until DDACK# for errata */
480 if (config->flags & VIA_BAD_PREQ)
481 fifo &= 0x7F;
482 else
483 fifo &= 0x9f;
484 /* Turn on FIFO for enabled channels */
485 fifo |= fifo_setting[enable];
486 pci_write_config_byte(pdev, 0x43, fifo);
487 }
488 /* Clock set up */
489 switch(config->flags & VIA_UDMA) {
490 case VIA_UDMA_NONE:
491 if (config->flags & VIA_NO_UNMASK)
492 type = &via_mwdma_info_borked;
493 else
494 type = &via_mwdma_info;
495 break;
496 case VIA_UDMA_33:
497 type = &via_udma33_info;
498 break;
499 case VIA_UDMA_66:
500 type = &via_udma66_info;
501 /* The 66 MHz devices require we enable the clock */
502 pci_read_config_dword(pdev, 0x50, &timing);
503 timing |= 0x80008;
504 pci_write_config_dword(pdev, 0x50, timing);
505 break;
506 case VIA_UDMA_100:
507 type = &via_udma100_info;
508 break;
509 case VIA_UDMA_133:
510 type = &via_udma133_info;
511 break;
512 default:
513 WARN_ON(1);
514 return -ENODEV;
515 }
516
517 if (config->flags & VIA_BAD_CLK66) {
518 /* Disable the 66MHz clock on problem devices */
519 pci_read_config_dword(pdev, 0x50, &timing);
520 timing &= ~0x80008;
521 pci_write_config_dword(pdev, 0x50, timing);
522 }
523
524 /* We have established the device type, now fire it up */
525 type->private_data = (void *)config;
526
527 port_info[0] = port_info[1] = type;
528 return ata_pci_init_one(pdev, port_info, 2);
529}
530
531static const struct pci_device_id via[] = {
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400532 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C576_1), },
533 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C586_1), },
534 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6410), },
535 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_SATA_EIDE), },
536
537 { },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400538};
539
540static struct pci_driver via_pci_driver = {
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400541 .name = DRV_NAME,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400542 .id_table = via,
543 .probe = via_init_one,
544 .remove = ata_pci_remove_one
545};
546
547static int __init via_init(void)
548{
549 return pci_register_driver(&via_pci_driver);
550}
551
Jeff Garzik669a5db2006-08-29 18:12:40 -0400552static void __exit via_exit(void)
553{
554 pci_unregister_driver(&via_pci_driver);
555}
556
Jeff Garzik669a5db2006-08-29 18:12:40 -0400557MODULE_AUTHOR("Alan Cox");
558MODULE_DESCRIPTION("low-level driver for VIA PATA");
559MODULE_LICENSE("GPL");
560MODULE_DEVICE_TABLE(pci, via);
561MODULE_VERSION(DRV_VERSION);
562
563module_init(via_init);
564module_exit(via_exit);