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Arnd Bergmannc902be72006-01-04 19:55:53 +00001/*
2 * CBE Pervasive Monitor and Debug
3 *
4 * (C) Copyright IBM Corporation 2005
5 *
6 * Authors: Maximino Aguilar (maguilar@us.ibm.com)
7 * Michael N. Day (mnday@us.ibm.com)
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24#undef DEBUG
25
Arnd Bergmannc902be72006-01-04 19:55:53 +000026#include <linux/interrupt.h>
27#include <linux/irq.h>
28#include <linux/percpu.h>
29#include <linux/types.h>
30#include <linux/kallsyms.h>
31
32#include <asm/io.h>
33#include <asm/machdep.h>
34#include <asm/prom.h>
35#include <asm/pgtable.h>
36#include <asm/reg.h>
37
38#include "pervasive.h"
Benjamin Herrenschmidtacf7d762006-06-19 20:33:16 +020039#include "cbe_regs.h"
Arnd Bergmannc902be72006-01-04 19:55:53 +000040
arnd@arndb.de302eca12006-10-24 18:31:26 +020041static void cbe_power_save(void)
Arnd Bergmannc902be72006-01-04 19:55:53 +000042{
arnd@arndb.de302eca12006-10-24 18:31:26 +020043 unsigned long ctrl, thread_switch_control;
44 ctrl = mfspr(SPRN_CTRLF);
Arnd Bergmannc902be72006-01-04 19:55:53 +000045
46 /* Enable DEC and EE interrupt request */
47 thread_switch_control = mfspr(SPRN_TSC_CELL);
48 thread_switch_control |= TSC_CELL_EE_ENABLE | TSC_CELL_EE_BOOST;
49
arnd@arndb.de302eca12006-10-24 18:31:26 +020050 switch (ctrl & CTRL_CT) {
Arnd Bergmannc902be72006-01-04 19:55:53 +000051 case CTRL_CT0:
52 thread_switch_control |= TSC_CELL_DEC_ENABLE_0;
Arnd Bergmannc902be72006-01-04 19:55:53 +000053 break;
54 case CTRL_CT1:
55 thread_switch_control |= TSC_CELL_DEC_ENABLE_1;
Arnd Bergmannc902be72006-01-04 19:55:53 +000056 break;
57 default:
58 printk(KERN_WARNING "%s: unknown configuration\n",
59 __FUNCTION__);
Arnd Bergmannc902be72006-01-04 19:55:53 +000060 break;
61 }
Arnd Bergmannc902be72006-01-04 19:55:53 +000062 mtspr(SPRN_TSC_CELL, thread_switch_control);
63
arnd@arndb.de302eca12006-10-24 18:31:26 +020064 /*
65 * go into low thread priority, medium priority will be
66 * restored for us after wake-up.
Benjamin Herrenschmidtacf7d762006-06-19 20:33:16 +020067 */
arnd@arndb.de302eca12006-10-24 18:31:26 +020068 HMT_low();
Arnd Bergmannc902be72006-01-04 19:55:53 +000069
arnd@arndb.de302eca12006-10-24 18:31:26 +020070 /*
71 * atomically disable thread execution and runlatch.
72 * External and Decrementer exceptions are still handled when the
73 * thread is disabled but now enter in cbe_system_reset_exception()
74 */
75 ctrl &= ~(CTRL_RUNLATCH | CTRL_TE);
76 mtspr(SPRN_CTRLT, ctrl);
Arnd Bergmannc902be72006-01-04 19:55:53 +000077}
78
Arnd Bergmann8fce10a2006-01-11 23:07:11 +000079static int cbe_system_reset_exception(struct pt_regs *regs)
Arnd Bergmannc902be72006-01-04 19:55:53 +000080{
81 switch (regs->msr & SRR1_WAKEMASK) {
82 case SRR1_WAKEEE:
83 do_IRQ(regs);
84 break;
85 case SRR1_WAKEDEC:
86 timer_interrupt(regs);
87 break;
88 case SRR1_WAKEMT:
Arnd Bergmannc902be72006-01-04 19:55:53 +000089 break;
Benjamin Herrenschmidtacf7d762006-06-19 20:33:16 +020090#ifdef CONFIG_CBE_RAS
91 case SRR1_WAKESYSERR:
92 cbe_system_error_exception(regs);
93 break;
94 case SRR1_WAKETHERM:
95 cbe_thermal_exception(regs);
96 break;
97#endif /* CONFIG_CBE_RAS */
Arnd Bergmannc902be72006-01-04 19:55:53 +000098 default:
99 /* do system reset */
100 return 0;
101 }
102 /* everything handled */
103 return 1;
104}
105
Benjamin Herrenschmidtacf7d762006-06-19 20:33:16 +0200106void __init cbe_pervasive_init(void)
Arnd Bergmannc902be72006-01-04 19:55:53 +0000107{
arnd@arndb.de302eca12006-10-24 18:31:26 +0200108 int cpu;
Arnd Bergmannc902be72006-01-04 19:55:53 +0000109 if (!cpu_has_feature(CPU_FTR_PAUSE_ZERO))
110 return;
111
arnd@arndb.de302eca12006-10-24 18:31:26 +0200112 for_each_possible_cpu(cpu) {
113 struct cbe_pmd_regs __iomem *regs = cbe_get_cpu_pmd_regs(cpu);
114 if (!regs)
115 continue;
116
117 /* Enable Pause(0) control bit */
118 out_be64(&regs->pmcr, in_be64(&regs->pmcr) |
119 CBE_PMD_PAUSE_ZERO_CONTROL);
120 }
121
122 ppc_md.power_save = cbe_power_save;
Arnd Bergmannc902be72006-01-04 19:55:53 +0000123 ppc_md.system_reset_exception = cbe_system_reset_exception;
124}