blob: 2d1533f116c0c020f57a4de59c952b6167f3545c [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Copyright 2002 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc.
4 * ppopov@mvista.com or source@mvista.com
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070026#include <linux/init.h>
27#include <linux/sched.h>
28#include <linux/ioport.h>
29#include <linux/mm.h>
30#include <linux/console.h>
31#include <linux/delay.h>
32
33#include <asm/cpu.h>
34#include <asm/bootinfo.h>
35#include <asm/irq.h>
36#include <asm/mipsregs.h>
37#include <asm/reboot.h>
38#include <asm/pgtable.h>
39#include <asm/mach-au1x00/au1000.h>
40#include <asm/mach-pb1x00/pb1100.h>
41
42void board_reset (void)
43{
44 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
45 au_writel(0x00000000, 0xAE00001C);
46}
47
48void __init board_setup(void)
49{
50 u32 pin_func;
51 u32 sys_freqctrl, sys_clksrc;
52
53 // set AUX clock to 12MHz * 8 = 96 MHz
54 au_writel(8, SYS_AUXPLL);
55 au_writel(0, SYS_PININPUTEN);
56 udelay(100);
57
Ralf Baechle5536b232006-10-09 16:34:41 +010058#ifdef CONFIG_USB_OHCI
Linus Torvalds1da177e2005-04-16 15:20:36 -070059 // configure pins GPIO[14:9] as GPIO
60 pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x80);
61
62 /* zero and disable FREQ2 */
63 sys_freqctrl = au_readl(SYS_FREQCTRL0);
64 sys_freqctrl &= ~0xFFF00000;
65 au_writel(sys_freqctrl, SYS_FREQCTRL0);
66
67 /* zero and disable USBH/USBD/IrDA clock */
68 sys_clksrc = au_readl(SYS_CLKSRC);
69 sys_clksrc &= ~0x0000001F;
70 au_writel(sys_clksrc, SYS_CLKSRC);
71
72 sys_freqctrl = au_readl(SYS_FREQCTRL0);
73 sys_freqctrl &= ~0xFFF00000;
74
75 sys_clksrc = au_readl(SYS_CLKSRC);
76 sys_clksrc &= ~0x0000001F;
77
78 // FREQ2 = aux/2 = 48 MHz
79 sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20));
80 au_writel(sys_freqctrl, SYS_FREQCTRL0);
81
82 /*
83 * Route 48MHz FREQ2 into USBH/USBD/IrDA
84 */
85 sys_clksrc |= ((4<<2) | (0<<1) | 0 );
86 au_writel(sys_clksrc, SYS_CLKSRC);
87
88 /* setup the static bus controller */
89 au_writel(0x00000002, MEM_STCFG3); /* type = PCMCIA */
90 au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */
91 au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */
92
93 // get USB Functionality pin state (device vs host drive pins)
94 pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8000);
Linus Torvalds1da177e2005-04-16 15:20:36 -070095 // 2nd USB port is USB host
96 pin_func |= 0x8000;
Linus Torvalds1da177e2005-04-16 15:20:36 -070097 au_writel(pin_func, SYS_PINFUNC);
Ralf Baechle5536b232006-10-09 16:34:41 +010098#endif // defined (CONFIG_USB_OHCI)
Linus Torvalds1da177e2005-04-16 15:20:36 -070099
100 /* Enable sys bus clock divider when IDLE state or no bus activity. */
101 au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
102
103 // Enable the RTC if not already enabled
104 if (!(readb(0xac000028) & 0x20)) {
105 writeb(readb(0xac000028) | 0x20, 0xac000028);
106 au_sync();
107 }
108 // Put the clock in BCD mode
109 if (readb(0xac00002C) & 0x4) { /* reg B */
110 writeb(readb(0xac00002c) & ~0x4, 0xac00002c);
111 au_sync();
112 }
113}