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Graf Yang5be36d22008-04-25 03:09:15 +08001/*
2 * file: include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * blackfin serial driver head file
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
Bryan Wu1394f032007-05-06 14:50:22 -070032#include <linux/serial.h>
33#include <asm/dma.h>
Michael Hennerichc58c2142007-10-04 00:35:05 +080034#include <asm/portmux.h>
Bryan Wu1394f032007-05-06 14:50:22 -070035
Bryan Wu1394f032007-05-06 14:50:22 -070036#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
37#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
38#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
39#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
40#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
41#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
Bryan Wu1394f032007-05-06 14:50:22 -070042#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
43
44#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
45#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
46#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
Mike Frysinger89bf6dc2008-05-07 11:41:26 +080047#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
48#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
Bryan Wu1394f032007-05-06 14:50:22 -070049#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
50#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
51#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
52
53#ifdef CONFIG_BFIN_UART0_CTSRTS
54# define CONFIG_SERIAL_BFIN_CTSRTS
55# ifndef CONFIG_UART0_CTS_PIN
56# define CONFIG_UART0_CTS_PIN -1
57# endif
58# ifndef CONFIG_UART0_RTS_PIN
59# define CONFIG_UART0_RTS_PIN -1
60# endif
61#endif
62
63struct bfin_serial_port {
64 struct uart_port port;
65 unsigned int old_status;
Mike Frysinger0bcfd702007-12-24 19:40:05 +080066 unsigned int lsr;
Bryan Wu1394f032007-05-06 14:50:22 -070067#ifdef CONFIG_SERIAL_BFIN_DMA
68 int tx_done;
69 int tx_count;
70 struct circ_buf rx_dma_buf;
71 struct timer_list rx_dma_timer;
72 int rx_dma_nrows;
73 unsigned int tx_dma_channel;
74 unsigned int rx_dma_channel;
75 struct work_struct tx_dma_workqueue;
76#else
Mike Frysinger8851c712007-12-24 19:48:04 +080077# if ANOMALY_05000230
78 unsigned int anomaly_threshold;
79# endif
Bryan Wu1394f032007-05-06 14:50:22 -070080#endif
81#ifdef CONFIG_SERIAL_BFIN_CTSRTS
Sonic Zhang4cb4f222008-02-02 14:29:25 +080082 struct work_struct cts_workqueue;
Bryan Wu1394f032007-05-06 14:50:22 -070083 int cts_pin;
84 int rts_pin;
85#endif
86};
87
Mike Frysinger0bcfd702007-12-24 19:40:05 +080088/* The hardware clears the LSR bits upon read, so we need to cache
89 * some of the more fun bits in software so they don't get lost
90 * when checking the LSR in other code paths (TX).
91 */
92static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
93{
94 unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
95 uart->lsr |= (lsr & (BI|FE|PE|OE));
96 return lsr | uart->lsr;
97}
98
99static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
100{
101 uart->lsr = 0;
102 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
103}
104
Graf Yang5be36d22008-04-25 03:09:15 +0800105struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
Bryan Wu1394f032007-05-06 14:50:22 -0700106struct bfin_serial_res {
107 unsigned long uart_base_addr;
108 int uart_irq;
109#ifdef CONFIG_SERIAL_BFIN_DMA
110 unsigned int uart_tx_dma_channel;
111 unsigned int uart_rx_dma_channel;
112#endif
113#ifdef CONFIG_SERIAL_BFIN_CTSRTS
114 int uart_cts_pin;
115 int uart_rts_pin;
116#endif
117};
118
119struct bfin_serial_res bfin_serial_resource[] = {
Mike Frysinger9c8f1722007-06-21 11:34:16 +0800120 {
Bryan Wu1394f032007-05-06 14:50:22 -0700121 0xFFC00400,
122 IRQ_UART_RX,
123#ifdef CONFIG_SERIAL_BFIN_DMA
124 CH_UART_TX,
125 CH_UART_RX,
126#endif
127#ifdef CONFIG_BFIN_UART0_CTSRTS
128 CONFIG_UART0_CTS_PIN,
129 CONFIG_UART0_RTS_PIN,
130#endif
Mike Frysinger9c8f1722007-06-21 11:34:16 +0800131 }
Bryan Wu1394f032007-05-06 14:50:22 -0700132};
133
Michael Hennerichc58c2142007-10-04 00:35:05 +0800134#define DRIVER_NAME "bfin-uart"
Bryan Wu1394f032007-05-06 14:50:22 -0700135
Graf Yang5be36d22008-04-25 03:09:15 +0800136int nr_ports = BFIN_UART_NR_PORTS;
Bryan Wu1394f032007-05-06 14:50:22 -0700137static void bfin_serial_hw_init(struct bfin_serial_port *uart)
138{
139
Michael Hennerichc58c2142007-10-04 00:35:05 +0800140#ifdef CONFIG_SERIAL_BFIN_UART0
141 peripheral_request(P_UART0_TX, DRIVER_NAME);
142 peripheral_request(P_UART0_RX, DRIVER_NAME);
143#endif
144
Bryan Wu1394f032007-05-06 14:50:22 -0700145#ifdef CONFIG_SERIAL_BFIN_CTSRTS
146 if (uart->cts_pin >= 0) {
Michael Hennerichc58c2142007-10-04 00:35:05 +0800147 gpio_request(uart->cts_pin, DRIVER_NAME);
Bryan Wu1394f032007-05-06 14:50:22 -0700148 gpio_direction_input(uart->cts_pin);
149 }
150 if (uart->rts_pin >= 0) {
Michael Hennerichc58c2142007-10-04 00:35:05 +0800151 gpio_request(uart->rts_pin, DRIVER_NAME);
Michael Hennerichacbcd262008-01-22 18:36:20 +0800152 gpio_direction_input(uart->rts_pin, 0);
Bryan Wu1394f032007-05-06 14:50:22 -0700153 }
154#endif
155}