Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify it |
| 5 | * under the terms of the GNU General Public License as published by the Free |
| 6 | * Software Foundation; either version 2 of the License, or (at your option) |
| 7 | * any later version. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 12 | * more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License along with |
| 15 | * this program; if not, write to the Free Software Foundation, Inc., 59 |
| 16 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 17 | * |
| 18 | * The full GNU General Public License is included in this distribution in the |
| 19 | * file called COPYING. |
| 20 | */ |
Russell King - ARM Linux | d2ebfb3 | 2012-03-06 22:34:26 +0000 | [diff] [blame] | 21 | #ifndef LINUX_DMAENGINE_H |
| 22 | #define LINUX_DMAENGINE_H |
David Woodhouse | 1c0f16e | 2006-06-27 02:53:56 -0700 | [diff] [blame] | 23 | |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 24 | #include <linux/device.h> |
| 25 | #include <linux/uio.h> |
Paul Gortmaker | 187f188 | 2011-11-23 20:12:59 -0500 | [diff] [blame] | 26 | #include <linux/bug.h> |
Vinod Koul | 90b44f8 | 2011-07-25 19:57:52 +0530 | [diff] [blame] | 27 | #include <linux/scatterlist.h> |
Paul Gortmaker | a8efa9d | 2011-07-29 16:55:11 +1000 | [diff] [blame] | 28 | #include <linux/bitmap.h> |
Viresh Kumar | dcc043d | 2012-02-01 16:12:18 +0530 | [diff] [blame] | 29 | #include <linux/types.h> |
Paul Gortmaker | a8efa9d | 2011-07-29 16:55:11 +1000 | [diff] [blame] | 30 | #include <asm/page.h> |
Alexey Dobriyan | b7f080c | 2011-06-16 11:01:34 +0000 | [diff] [blame] | 31 | |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 32 | /** |
Randy Dunlap | fe4ada2 | 2006-07-03 19:44:51 -0700 | [diff] [blame] | 33 | * typedef dma_cookie_t - an opaque DMA cookie |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 34 | * |
| 35 | * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code |
| 36 | */ |
| 37 | typedef s32 dma_cookie_t; |
Steven J. Magnani | 76bd061 | 2010-02-28 22:18:16 -0700 | [diff] [blame] | 38 | #define DMA_MIN_COOKIE 1 |
| 39 | #define DMA_MAX_COOKIE INT_MAX |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 40 | |
| 41 | #define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0) |
| 42 | |
| 43 | /** |
| 44 | * enum dma_status - DMA transaction status |
| 45 | * @DMA_SUCCESS: transaction completed successfully |
| 46 | * @DMA_IN_PROGRESS: transaction not yet processed |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 47 | * @DMA_PAUSED: transaction is paused |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 48 | * @DMA_ERROR: transaction failed |
| 49 | */ |
| 50 | enum dma_status { |
| 51 | DMA_SUCCESS, |
| 52 | DMA_IN_PROGRESS, |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 53 | DMA_PAUSED, |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 54 | DMA_ERROR, |
| 55 | }; |
| 56 | |
| 57 | /** |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 58 | * enum dma_transaction_type - DMA transaction types/indexes |
Dan Williams | 138f4c3 | 2009-09-08 17:42:51 -0700 | [diff] [blame] | 59 | * |
| 60 | * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is |
| 61 | * automatically set as dma devices are registered. |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 62 | */ |
| 63 | enum dma_transaction_type { |
| 64 | DMA_MEMCPY, |
| 65 | DMA_XOR, |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 66 | DMA_PQ, |
Dan Williams | 099f53c | 2009-04-08 14:28:37 -0700 | [diff] [blame] | 67 | DMA_XOR_VAL, |
| 68 | DMA_PQ_VAL, |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 69 | DMA_MEMSET, |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 70 | DMA_INTERRUPT, |
Ira Snyder | a86ee03 | 2010-09-30 11:46:44 +0000 | [diff] [blame] | 71 | DMA_SG, |
Dan Williams | 59b5ec2 | 2009-01-06 11:38:15 -0700 | [diff] [blame] | 72 | DMA_PRIVATE, |
Dan Williams | 138f4c3 | 2009-09-08 17:42:51 -0700 | [diff] [blame] | 73 | DMA_ASYNC_TX, |
Haavard Skinnemoen | dc0ee64 | 2008-07-08 11:59:35 -0700 | [diff] [blame] | 74 | DMA_SLAVE, |
Sascha Hauer | 782bc95 | 2010-09-30 13:56:32 +0000 | [diff] [blame] | 75 | DMA_CYCLIC, |
Jassi Brar | b14dab7 | 2011-10-13 12:33:30 +0530 | [diff] [blame] | 76 | DMA_INTERLEAVE, |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 77 | /* last transaction type for creation of the capabilities mask */ |
Jassi Brar | b14dab7 | 2011-10-13 12:33:30 +0530 | [diff] [blame] | 78 | DMA_TX_TYPE_END, |
| 79 | }; |
Haavard Skinnemoen | dc0ee64 | 2008-07-08 11:59:35 -0700 | [diff] [blame] | 80 | |
Vinod Koul | 49920bc | 2011-10-13 15:15:27 +0530 | [diff] [blame] | 81 | /** |
| 82 | * enum dma_transfer_direction - dma transfer mode and direction indicator |
| 83 | * @DMA_MEM_TO_MEM: Async/Memcpy mode |
| 84 | * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device |
| 85 | * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory |
| 86 | * @DMA_DEV_TO_DEV: Slave mode & From Device to Device |
| 87 | */ |
| 88 | enum dma_transfer_direction { |
| 89 | DMA_MEM_TO_MEM, |
| 90 | DMA_MEM_TO_DEV, |
| 91 | DMA_DEV_TO_MEM, |
| 92 | DMA_DEV_TO_DEV, |
Shawn Guo | 62268ce | 2011-12-13 23:48:03 +0800 | [diff] [blame] | 93 | DMA_TRANS_NONE, |
Vinod Koul | 49920bc | 2011-10-13 15:15:27 +0530 | [diff] [blame] | 94 | }; |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 95 | |
| 96 | /** |
Jassi Brar | b14dab7 | 2011-10-13 12:33:30 +0530 | [diff] [blame] | 97 | * Interleaved Transfer Request |
| 98 | * ---------------------------- |
| 99 | * A chunk is collection of contiguous bytes to be transfered. |
| 100 | * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG). |
| 101 | * ICGs may or maynot change between chunks. |
| 102 | * A FRAME is the smallest series of contiguous {chunk,icg} pairs, |
| 103 | * that when repeated an integral number of times, specifies the transfer. |
| 104 | * A transfer template is specification of a Frame, the number of times |
| 105 | * it is to be repeated and other per-transfer attributes. |
| 106 | * |
| 107 | * Practically, a client driver would have ready a template for each |
| 108 | * type of transfer it is going to need during its lifetime and |
| 109 | * set only 'src_start' and 'dst_start' before submitting the requests. |
| 110 | * |
| 111 | * |
| 112 | * | Frame-1 | Frame-2 | ~ | Frame-'numf' | |
| 113 | * |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...| |
| 114 | * |
| 115 | * == Chunk size |
| 116 | * ... ICG |
| 117 | */ |
| 118 | |
| 119 | /** |
| 120 | * struct data_chunk - Element of scatter-gather list that makes a frame. |
| 121 | * @size: Number of bytes to read from source. |
| 122 | * size_dst := fn(op, size_src), so doesn't mean much for destination. |
| 123 | * @icg: Number of bytes to jump after last src/dst address of this |
| 124 | * chunk and before first src/dst address for next chunk. |
| 125 | * Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false. |
| 126 | * Ignored for src(assumed 0), if src_inc is true and src_sgl is false. |
| 127 | */ |
| 128 | struct data_chunk { |
| 129 | size_t size; |
| 130 | size_t icg; |
| 131 | }; |
| 132 | |
| 133 | /** |
| 134 | * struct dma_interleaved_template - Template to convey DMAC the transfer pattern |
| 135 | * and attributes. |
| 136 | * @src_start: Bus address of source for the first chunk. |
| 137 | * @dst_start: Bus address of destination for the first chunk. |
| 138 | * @dir: Specifies the type of Source and Destination. |
| 139 | * @src_inc: If the source address increments after reading from it. |
| 140 | * @dst_inc: If the destination address increments after writing to it. |
| 141 | * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read). |
| 142 | * Otherwise, source is read contiguously (icg ignored). |
| 143 | * Ignored if src_inc is false. |
| 144 | * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write). |
| 145 | * Otherwise, destination is filled contiguously (icg ignored). |
| 146 | * Ignored if dst_inc is false. |
| 147 | * @numf: Number of frames in this template. |
| 148 | * @frame_size: Number of chunks in a frame i.e, size of sgl[]. |
| 149 | * @sgl: Array of {chunk,icg} pairs that make up a frame. |
| 150 | */ |
| 151 | struct dma_interleaved_template { |
| 152 | dma_addr_t src_start; |
| 153 | dma_addr_t dst_start; |
| 154 | enum dma_transfer_direction dir; |
| 155 | bool src_inc; |
| 156 | bool dst_inc; |
| 157 | bool src_sgl; |
| 158 | bool dst_sgl; |
| 159 | size_t numf; |
| 160 | size_t frame_size; |
| 161 | struct data_chunk sgl[0]; |
| 162 | }; |
| 163 | |
| 164 | /** |
Dan Williams | 636bdea | 2008-04-17 20:17:26 -0700 | [diff] [blame] | 165 | * enum dma_ctrl_flags - DMA flags to augment operation preparation, |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 166 | * control completion, and communicate status. |
Dan Williams | d4c56f9 | 2008-02-02 19:49:58 -0700 | [diff] [blame] | 167 | * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 168 | * this transaction |
Guennadi Liakhovetski | a88f666 | 2009-12-10 18:35:15 +0100 | [diff] [blame] | 169 | * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 170 | * acknowledges receipt, i.e. has has a chance to establish any dependency |
| 171 | * chains |
Dan Williams | e1d181e | 2008-07-04 00:13:40 -0700 | [diff] [blame] | 172 | * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s) |
| 173 | * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s) |
Maciej Sosnowski | 4f005db | 2009-04-23 12:31:51 +0200 | [diff] [blame] | 174 | * @DMA_COMPL_SRC_UNMAP_SINGLE - set to do the source dma-unmapping as single |
| 175 | * (if not set, do the source dma-unmapping as page) |
| 176 | * @DMA_COMPL_DEST_UNMAP_SINGLE - set to do the destination dma-unmapping as single |
| 177 | * (if not set, do the destination dma-unmapping as page) |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 178 | * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q |
| 179 | * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P |
| 180 | * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as |
| 181 | * sources that were the result of a previous operation, in the case of a PQ |
| 182 | * operation it continues the calculation with new sources |
Dan Williams | 0403e38 | 2009-09-08 17:42:50 -0700 | [diff] [blame] | 183 | * @DMA_PREP_FENCE - tell the driver that subsequent operations depend |
| 184 | * on the result of this operation |
Dan Williams | d4c56f9 | 2008-02-02 19:49:58 -0700 | [diff] [blame] | 185 | */ |
Dan Williams | 636bdea | 2008-04-17 20:17:26 -0700 | [diff] [blame] | 186 | enum dma_ctrl_flags { |
Dan Williams | d4c56f9 | 2008-02-02 19:49:58 -0700 | [diff] [blame] | 187 | DMA_PREP_INTERRUPT = (1 << 0), |
Dan Williams | 636bdea | 2008-04-17 20:17:26 -0700 | [diff] [blame] | 188 | DMA_CTRL_ACK = (1 << 1), |
Dan Williams | e1d181e | 2008-07-04 00:13:40 -0700 | [diff] [blame] | 189 | DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2), |
| 190 | DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3), |
Maciej Sosnowski | 4f005db | 2009-04-23 12:31:51 +0200 | [diff] [blame] | 191 | DMA_COMPL_SRC_UNMAP_SINGLE = (1 << 4), |
| 192 | DMA_COMPL_DEST_UNMAP_SINGLE = (1 << 5), |
Dan Williams | f9dd213 | 2009-09-08 17:42:29 -0700 | [diff] [blame] | 193 | DMA_PREP_PQ_DISABLE_P = (1 << 6), |
| 194 | DMA_PREP_PQ_DISABLE_Q = (1 << 7), |
| 195 | DMA_PREP_CONTINUE = (1 << 8), |
Dan Williams | 0403e38 | 2009-09-08 17:42:50 -0700 | [diff] [blame] | 196 | DMA_PREP_FENCE = (1 << 9), |
Dan Williams | d4c56f9 | 2008-02-02 19:49:58 -0700 | [diff] [blame] | 197 | }; |
| 198 | |
| 199 | /** |
Linus Walleij | c3635c7 | 2010-03-26 16:44:01 -0700 | [diff] [blame] | 200 | * enum dma_ctrl_cmd - DMA operations that can optionally be exercised |
| 201 | * on a running channel. |
| 202 | * @DMA_TERMINATE_ALL: terminate all ongoing transfers |
| 203 | * @DMA_PAUSE: pause ongoing transfers |
| 204 | * @DMA_RESUME: resume paused transfer |
Linus Walleij | c156d0a | 2010-08-04 13:37:33 +0200 | [diff] [blame] | 205 | * @DMA_SLAVE_CONFIG: this command is only implemented by DMA controllers |
| 206 | * that need to runtime reconfigure the slave channels (as opposed to passing |
| 207 | * configuration data in statically from the platform). An additional |
| 208 | * argument of struct dma_slave_config must be passed in with this |
| 209 | * command. |
Ira Snyder | 968f19a | 2010-09-30 11:46:46 +0000 | [diff] [blame] | 210 | * @FSLDMA_EXTERNAL_START: this command will put the Freescale DMA controller |
| 211 | * into external start mode. |
Linus Walleij | c3635c7 | 2010-03-26 16:44:01 -0700 | [diff] [blame] | 212 | */ |
| 213 | enum dma_ctrl_cmd { |
| 214 | DMA_TERMINATE_ALL, |
| 215 | DMA_PAUSE, |
| 216 | DMA_RESUME, |
Linus Walleij | c156d0a | 2010-08-04 13:37:33 +0200 | [diff] [blame] | 217 | DMA_SLAVE_CONFIG, |
Ira Snyder | 968f19a | 2010-09-30 11:46:46 +0000 | [diff] [blame] | 218 | FSLDMA_EXTERNAL_START, |
Linus Walleij | c3635c7 | 2010-03-26 16:44:01 -0700 | [diff] [blame] | 219 | }; |
| 220 | |
| 221 | /** |
Dan Williams | ad283ea | 2009-08-29 19:09:26 -0700 | [diff] [blame] | 222 | * enum sum_check_bits - bit position of pq_check_flags |
| 223 | */ |
| 224 | enum sum_check_bits { |
| 225 | SUM_CHECK_P = 0, |
| 226 | SUM_CHECK_Q = 1, |
| 227 | }; |
| 228 | |
| 229 | /** |
| 230 | * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations |
| 231 | * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise |
| 232 | * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise |
| 233 | */ |
| 234 | enum sum_check_flags { |
| 235 | SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P), |
| 236 | SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q), |
| 237 | }; |
| 238 | |
| 239 | |
| 240 | /** |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 241 | * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t. |
| 242 | * See linux/cpumask.h |
| 243 | */ |
| 244 | typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t; |
| 245 | |
| 246 | /** |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 247 | * struct dma_chan_percpu - the per-CPU part of struct dma_chan |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 248 | * @memcpy_count: transaction counter |
| 249 | * @bytes_transferred: byte counter |
| 250 | */ |
| 251 | |
| 252 | struct dma_chan_percpu { |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 253 | /* stats */ |
| 254 | unsigned long memcpy_count; |
| 255 | unsigned long bytes_transferred; |
| 256 | }; |
| 257 | |
| 258 | /** |
| 259 | * struct dma_chan - devices supply DMA channels, clients use them |
Randy Dunlap | fe4ada2 | 2006-07-03 19:44:51 -0700 | [diff] [blame] | 260 | * @device: ptr to the dma device who supplies this channel, always !%NULL |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 261 | * @cookie: last cookie value returned to client |
Russell King - ARM Linux | 4d4e58d | 2012-03-06 22:34:06 +0000 | [diff] [blame] | 262 | * @completed_cookie: last completed cookie for this channel |
Randy Dunlap | fe4ada2 | 2006-07-03 19:44:51 -0700 | [diff] [blame] | 263 | * @chan_id: channel ID for sysfs |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 264 | * @dev: class device for sysfs |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 265 | * @device_node: used to add this to the device chan list |
| 266 | * @local: per-cpu pointer to a struct dma_chan_percpu |
Dan Williams | 7cc5bf9 | 2008-07-08 11:58:21 -0700 | [diff] [blame] | 267 | * @client-count: how many clients are using this channel |
Dan Williams | bec0851 | 2009-01-06 11:38:14 -0700 | [diff] [blame] | 268 | * @table_count: number of appearances in the mem-to-mem allocation table |
Dan Williams | 287d859 | 2009-02-18 14:48:26 -0800 | [diff] [blame] | 269 | * @private: private data for certain client-channel associations |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 270 | */ |
| 271 | struct dma_chan { |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 272 | struct dma_device *device; |
| 273 | dma_cookie_t cookie; |
Russell King - ARM Linux | 4d4e58d | 2012-03-06 22:34:06 +0000 | [diff] [blame] | 274 | dma_cookie_t completed_cookie; |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 275 | |
| 276 | /* sysfs */ |
| 277 | int chan_id; |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 278 | struct dma_chan_dev *dev; |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 279 | |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 280 | struct list_head device_node; |
Tejun Heo | a29d8b8 | 2010-02-02 14:39:15 +0900 | [diff] [blame] | 281 | struct dma_chan_percpu __percpu *local; |
Dan Williams | 7cc5bf9 | 2008-07-08 11:58:21 -0700 | [diff] [blame] | 282 | int client_count; |
Dan Williams | bec0851 | 2009-01-06 11:38:14 -0700 | [diff] [blame] | 283 | int table_count; |
Dan Williams | 287d859 | 2009-02-18 14:48:26 -0800 | [diff] [blame] | 284 | void *private; |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 285 | }; |
| 286 | |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 287 | /** |
| 288 | * struct dma_chan_dev - relate sysfs device node to backing channel device |
| 289 | * @chan - driver channel device |
| 290 | * @device - sysfs device |
Dan Williams | 864498a | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 291 | * @dev_id - parent dma_device dev_id |
| 292 | * @idr_ref - reference count to gate release of dma_device dev_id |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 293 | */ |
| 294 | struct dma_chan_dev { |
| 295 | struct dma_chan *chan; |
| 296 | struct device device; |
Dan Williams | 864498a | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 297 | int dev_id; |
| 298 | atomic_t *idr_ref; |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 299 | }; |
| 300 | |
Linus Walleij | c156d0a | 2010-08-04 13:37:33 +0200 | [diff] [blame] | 301 | /** |
| 302 | * enum dma_slave_buswidth - defines bus with of the DMA slave |
| 303 | * device, source or target buses |
| 304 | */ |
| 305 | enum dma_slave_buswidth { |
| 306 | DMA_SLAVE_BUSWIDTH_UNDEFINED = 0, |
| 307 | DMA_SLAVE_BUSWIDTH_1_BYTE = 1, |
| 308 | DMA_SLAVE_BUSWIDTH_2_BYTES = 2, |
| 309 | DMA_SLAVE_BUSWIDTH_4_BYTES = 4, |
| 310 | DMA_SLAVE_BUSWIDTH_8_BYTES = 8, |
| 311 | }; |
| 312 | |
| 313 | /** |
| 314 | * struct dma_slave_config - dma slave channel runtime config |
| 315 | * @direction: whether the data shall go in or out on this slave |
| 316 | * channel, right now. DMA_TO_DEVICE and DMA_FROM_DEVICE are |
| 317 | * legal values, DMA_BIDIRECTIONAL is not acceptable since we |
| 318 | * need to differentiate source and target addresses. |
| 319 | * @src_addr: this is the physical address where DMA slave data |
| 320 | * should be read (RX), if the source is memory this argument is |
| 321 | * ignored. |
| 322 | * @dst_addr: this is the physical address where DMA slave data |
| 323 | * should be written (TX), if the source is memory this argument |
| 324 | * is ignored. |
| 325 | * @src_addr_width: this is the width in bytes of the source (RX) |
| 326 | * register where DMA data shall be read. If the source |
| 327 | * is memory this may be ignored depending on architecture. |
| 328 | * Legal values: 1, 2, 4, 8. |
| 329 | * @dst_addr_width: same as src_addr_width but for destination |
| 330 | * target (TX) mutatis mutandis. |
| 331 | * @src_maxburst: the maximum number of words (note: words, as in |
| 332 | * units of the src_addr_width member, not bytes) that can be sent |
| 333 | * in one burst to the device. Typically something like half the |
| 334 | * FIFO depth on I/O peripherals so you don't overflow it. This |
| 335 | * may or may not be applicable on memory sources. |
| 336 | * @dst_maxburst: same as src_maxburst but for destination target |
| 337 | * mutatis mutandis. |
Viresh Kumar | dcc043d | 2012-02-01 16:12:18 +0530 | [diff] [blame] | 338 | * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill |
| 339 | * with 'true' if peripheral should be flow controller. Direction will be |
| 340 | * selected at Runtime. |
Linus Walleij | c156d0a | 2010-08-04 13:37:33 +0200 | [diff] [blame] | 341 | * |
| 342 | * This struct is passed in as configuration data to a DMA engine |
| 343 | * in order to set up a certain channel for DMA transport at runtime. |
| 344 | * The DMA device/engine has to provide support for an additional |
| 345 | * command in the channel config interface, DMA_SLAVE_CONFIG |
| 346 | * and this struct will then be passed in as an argument to the |
| 347 | * DMA engine device_control() function. |
| 348 | * |
| 349 | * The rationale for adding configuration information to this struct |
| 350 | * is as follows: if it is likely that most DMA slave controllers in |
| 351 | * the world will support the configuration option, then make it |
| 352 | * generic. If not: if it is fixed so that it be sent in static from |
| 353 | * the platform data, then prefer to do that. Else, if it is neither |
| 354 | * fixed at runtime, nor generic enough (such as bus mastership on |
| 355 | * some CPU family and whatnot) then create a custom slave config |
| 356 | * struct and pass that, then make this config a member of that |
| 357 | * struct, if applicable. |
| 358 | */ |
| 359 | struct dma_slave_config { |
Vinod Koul | 49920bc | 2011-10-13 15:15:27 +0530 | [diff] [blame] | 360 | enum dma_transfer_direction direction; |
Linus Walleij | c156d0a | 2010-08-04 13:37:33 +0200 | [diff] [blame] | 361 | dma_addr_t src_addr; |
| 362 | dma_addr_t dst_addr; |
| 363 | enum dma_slave_buswidth src_addr_width; |
| 364 | enum dma_slave_buswidth dst_addr_width; |
| 365 | u32 src_maxburst; |
| 366 | u32 dst_maxburst; |
Viresh Kumar | dcc043d | 2012-02-01 16:12:18 +0530 | [diff] [blame] | 367 | bool device_fc; |
Linus Walleij | c156d0a | 2010-08-04 13:37:33 +0200 | [diff] [blame] | 368 | }; |
| 369 | |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 370 | static inline const char *dma_chan_name(struct dma_chan *chan) |
| 371 | { |
| 372 | return dev_name(&chan->dev->device); |
| 373 | } |
Dan Williams | d379b01 | 2007-07-09 11:56:42 -0700 | [diff] [blame] | 374 | |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 375 | void dma_chan_cleanup(struct kref *kref); |
| 376 | |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 377 | /** |
Dan Williams | 59b5ec2 | 2009-01-06 11:38:15 -0700 | [diff] [blame] | 378 | * typedef dma_filter_fn - callback filter for dma_request_channel |
| 379 | * @chan: channel to be reviewed |
| 380 | * @filter_param: opaque parameter passed through dma_request_channel |
| 381 | * |
| 382 | * When this optional parameter is specified in a call to dma_request_channel a |
| 383 | * suitable channel is passed to this routine for further dispositioning before |
| 384 | * being returned. Where 'suitable' indicates a non-busy channel that |
Dan Williams | 7dd6025 | 2009-01-06 11:38:19 -0700 | [diff] [blame] | 385 | * satisfies the given capability mask. It returns 'true' to indicate that the |
| 386 | * channel is suitable. |
Dan Williams | 59b5ec2 | 2009-01-06 11:38:15 -0700 | [diff] [blame] | 387 | */ |
Dan Williams | 7dd6025 | 2009-01-06 11:38:19 -0700 | [diff] [blame] | 388 | typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param); |
Dan Williams | 59b5ec2 | 2009-01-06 11:38:15 -0700 | [diff] [blame] | 389 | |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 390 | typedef void (*dma_async_tx_callback)(void *dma_async_param); |
| 391 | /** |
| 392 | * struct dma_async_tx_descriptor - async transaction descriptor |
| 393 | * ---dma generic offload fields--- |
| 394 | * @cookie: tracking cookie for this transaction, set to -EBUSY if |
| 395 | * this tx is sitting on a dependency list |
Dan Williams | 636bdea | 2008-04-17 20:17:26 -0700 | [diff] [blame] | 396 | * @flags: flags to augment operation preparation, control completion, and |
| 397 | * communicate status |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 398 | * @phys: physical address of the descriptor |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 399 | * @chan: target channel for this operation |
| 400 | * @tx_submit: set the prepared descriptor(s) to be executed by the engine |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 401 | * @callback: routine to call after this operation is complete |
| 402 | * @callback_param: general parameter to pass to the callback routine |
| 403 | * ---async_tx api specific fields--- |
Dan Williams | 19242d7 | 2008-04-17 20:17:25 -0700 | [diff] [blame] | 404 | * @next: at completion submit this descriptor |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 405 | * @parent: pointer to the next level up in the dependency chain |
Dan Williams | 19242d7 | 2008-04-17 20:17:25 -0700 | [diff] [blame] | 406 | * @lock: protect the parent and next pointers |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 407 | */ |
| 408 | struct dma_async_tx_descriptor { |
| 409 | dma_cookie_t cookie; |
Dan Williams | 636bdea | 2008-04-17 20:17:26 -0700 | [diff] [blame] | 410 | enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */ |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 411 | dma_addr_t phys; |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 412 | struct dma_chan *chan; |
| 413 | dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx); |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 414 | dma_async_tx_callback callback; |
| 415 | void *callback_param; |
Dan Williams | 5fc6d89 | 2010-10-07 16:44:50 -0700 | [diff] [blame] | 416 | #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH |
Dan Williams | 19242d7 | 2008-04-17 20:17:25 -0700 | [diff] [blame] | 417 | struct dma_async_tx_descriptor *next; |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 418 | struct dma_async_tx_descriptor *parent; |
| 419 | spinlock_t lock; |
Dan Williams | caa20d97 | 2010-05-17 16:24:16 -0700 | [diff] [blame] | 420 | #endif |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 421 | }; |
| 422 | |
Dan Williams | 5fc6d89 | 2010-10-07 16:44:50 -0700 | [diff] [blame] | 423 | #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH |
Dan Williams | caa20d97 | 2010-05-17 16:24:16 -0700 | [diff] [blame] | 424 | static inline void txd_lock(struct dma_async_tx_descriptor *txd) |
| 425 | { |
| 426 | } |
| 427 | static inline void txd_unlock(struct dma_async_tx_descriptor *txd) |
| 428 | { |
| 429 | } |
| 430 | static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next) |
| 431 | { |
| 432 | BUG(); |
| 433 | } |
| 434 | static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd) |
| 435 | { |
| 436 | } |
| 437 | static inline void txd_clear_next(struct dma_async_tx_descriptor *txd) |
| 438 | { |
| 439 | } |
| 440 | static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd) |
| 441 | { |
| 442 | return NULL; |
| 443 | } |
| 444 | static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd) |
| 445 | { |
| 446 | return NULL; |
| 447 | } |
| 448 | |
| 449 | #else |
| 450 | static inline void txd_lock(struct dma_async_tx_descriptor *txd) |
| 451 | { |
| 452 | spin_lock_bh(&txd->lock); |
| 453 | } |
| 454 | static inline void txd_unlock(struct dma_async_tx_descriptor *txd) |
| 455 | { |
| 456 | spin_unlock_bh(&txd->lock); |
| 457 | } |
| 458 | static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next) |
| 459 | { |
| 460 | txd->next = next; |
| 461 | next->parent = txd; |
| 462 | } |
| 463 | static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd) |
| 464 | { |
| 465 | txd->parent = NULL; |
| 466 | } |
| 467 | static inline void txd_clear_next(struct dma_async_tx_descriptor *txd) |
| 468 | { |
| 469 | txd->next = NULL; |
| 470 | } |
| 471 | static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd) |
| 472 | { |
| 473 | return txd->parent; |
| 474 | } |
| 475 | static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd) |
| 476 | { |
| 477 | return txd->next; |
| 478 | } |
| 479 | #endif |
| 480 | |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 481 | /** |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 482 | * struct dma_tx_state - filled in to report the status of |
| 483 | * a transfer. |
| 484 | * @last: last completed DMA cookie |
| 485 | * @used: last issued DMA cookie (i.e. the one in progress) |
| 486 | * @residue: the remaining number of bytes left to transmit |
| 487 | * on the selected transfer for states DMA_IN_PROGRESS and |
| 488 | * DMA_PAUSED if this is implemented in the driver, else 0 |
| 489 | */ |
| 490 | struct dma_tx_state { |
| 491 | dma_cookie_t last; |
| 492 | dma_cookie_t used; |
| 493 | u32 residue; |
| 494 | }; |
| 495 | |
| 496 | /** |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 497 | * struct dma_device - info on the entity supplying DMA services |
| 498 | * @chancnt: how many DMA channels are supported |
Atsushi Nemoto | 0f57151 | 2009-03-06 20:07:14 +0900 | [diff] [blame] | 499 | * @privatecnt: how many DMA channels are requested by dma_request_channel |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 500 | * @channels: the list of struct dma_chan |
| 501 | * @global_node: list_head for global dma_device_list |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 502 | * @cap_mask: one or more dma_capability flags |
| 503 | * @max_xor: maximum number of xor sources, 0 if no capability |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 504 | * @max_pq: maximum number of PQ sources and PQ-continue capability |
Dan Williams | 83544ae | 2009-09-08 17:42:53 -0700 | [diff] [blame] | 505 | * @copy_align: alignment shift for memcpy operations |
| 506 | * @xor_align: alignment shift for xor operations |
| 507 | * @pq_align: alignment shift for pq operations |
| 508 | * @fill_align: alignment shift for memset operations |
Randy Dunlap | fe4ada2 | 2006-07-03 19:44:51 -0700 | [diff] [blame] | 509 | * @dev_id: unique device ID |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 510 | * @dev: struct device reference for dma mapping api |
Randy Dunlap | fe4ada2 | 2006-07-03 19:44:51 -0700 | [diff] [blame] | 511 | * @device_alloc_chan_resources: allocate resources and return the |
| 512 | * number of allocated descriptors |
| 513 | * @device_free_chan_resources: release DMA channel's resources |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 514 | * @device_prep_dma_memcpy: prepares a memcpy operation |
| 515 | * @device_prep_dma_xor: prepares a xor operation |
Dan Williams | 099f53c | 2009-04-08 14:28:37 -0700 | [diff] [blame] | 516 | * @device_prep_dma_xor_val: prepares a xor validation operation |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 517 | * @device_prep_dma_pq: prepares a pq operation |
| 518 | * @device_prep_dma_pq_val: prepares a pqzero_sum operation |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 519 | * @device_prep_dma_memset: prepares a memset operation |
| 520 | * @device_prep_dma_interrupt: prepares an end of chain interrupt operation |
Haavard Skinnemoen | dc0ee64 | 2008-07-08 11:59:35 -0700 | [diff] [blame] | 521 | * @device_prep_slave_sg: prepares a slave dma operation |
Sascha Hauer | 782bc95 | 2010-09-30 13:56:32 +0000 | [diff] [blame] | 522 | * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio. |
| 523 | * The function takes a buffer of size buf_len. The callback function will |
| 524 | * be called after period_len bytes have been transferred. |
Jassi Brar | b14dab7 | 2011-10-13 12:33:30 +0530 | [diff] [blame] | 525 | * @device_prep_interleaved_dma: Transfer expression in a generic way. |
Linus Walleij | c3635c7 | 2010-03-26 16:44:01 -0700 | [diff] [blame] | 526 | * @device_control: manipulate all pending operations on a channel, returns |
| 527 | * zero or error code |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 528 | * @device_tx_status: poll for transaction completion, the optional |
| 529 | * txstate parameter can be supplied with a pointer to get a |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 530 | * struct with auxiliary transfer status information, otherwise the call |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 531 | * will just return a simple status code |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 532 | * @device_issue_pending: push pending transactions to hardware |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 533 | */ |
| 534 | struct dma_device { |
| 535 | |
| 536 | unsigned int chancnt; |
Atsushi Nemoto | 0f57151 | 2009-03-06 20:07:14 +0900 | [diff] [blame] | 537 | unsigned int privatecnt; |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 538 | struct list_head channels; |
| 539 | struct list_head global_node; |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 540 | dma_cap_mask_t cap_mask; |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 541 | unsigned short max_xor; |
| 542 | unsigned short max_pq; |
Dan Williams | 83544ae | 2009-09-08 17:42:53 -0700 | [diff] [blame] | 543 | u8 copy_align; |
| 544 | u8 xor_align; |
| 545 | u8 pq_align; |
| 546 | u8 fill_align; |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 547 | #define DMA_HAS_PQ_CONTINUE (1 << 15) |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 548 | |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 549 | int dev_id; |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 550 | struct device *dev; |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 551 | |
Dan Williams | aa1e6f1 | 2009-01-06 11:38:17 -0700 | [diff] [blame] | 552 | int (*device_alloc_chan_resources)(struct dma_chan *chan); |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 553 | void (*device_free_chan_resources)(struct dma_chan *chan); |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 554 | |
| 555 | struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)( |
Dan Williams | 0036731 | 2008-02-02 19:49:57 -0700 | [diff] [blame] | 556 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, |
Dan Williams | d4c56f9 | 2008-02-02 19:49:58 -0700 | [diff] [blame] | 557 | size_t len, unsigned long flags); |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 558 | struct dma_async_tx_descriptor *(*device_prep_dma_xor)( |
Dan Williams | 0036731 | 2008-02-02 19:49:57 -0700 | [diff] [blame] | 559 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, |
Dan Williams | d4c56f9 | 2008-02-02 19:49:58 -0700 | [diff] [blame] | 560 | unsigned int src_cnt, size_t len, unsigned long flags); |
Dan Williams | 099f53c | 2009-04-08 14:28:37 -0700 | [diff] [blame] | 561 | struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)( |
Dan Williams | 0036731 | 2008-02-02 19:49:57 -0700 | [diff] [blame] | 562 | struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt, |
Dan Williams | ad283ea | 2009-08-29 19:09:26 -0700 | [diff] [blame] | 563 | size_t len, enum sum_check_flags *result, unsigned long flags); |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 564 | struct dma_async_tx_descriptor *(*device_prep_dma_pq)( |
| 565 | struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, |
| 566 | unsigned int src_cnt, const unsigned char *scf, |
| 567 | size_t len, unsigned long flags); |
| 568 | struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)( |
| 569 | struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, |
| 570 | unsigned int src_cnt, const unsigned char *scf, size_t len, |
| 571 | enum sum_check_flags *pqres, unsigned long flags); |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 572 | struct dma_async_tx_descriptor *(*device_prep_dma_memset)( |
Dan Williams | 0036731 | 2008-02-02 19:49:57 -0700 | [diff] [blame] | 573 | struct dma_chan *chan, dma_addr_t dest, int value, size_t len, |
Dan Williams | d4c56f9 | 2008-02-02 19:49:58 -0700 | [diff] [blame] | 574 | unsigned long flags); |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 575 | struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)( |
Dan Williams | 636bdea | 2008-04-17 20:17:26 -0700 | [diff] [blame] | 576 | struct dma_chan *chan, unsigned long flags); |
Ira Snyder | a86ee03 | 2010-09-30 11:46:44 +0000 | [diff] [blame] | 577 | struct dma_async_tx_descriptor *(*device_prep_dma_sg)( |
| 578 | struct dma_chan *chan, |
| 579 | struct scatterlist *dst_sg, unsigned int dst_nents, |
| 580 | struct scatterlist *src_sg, unsigned int src_nents, |
| 581 | unsigned long flags); |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 582 | |
Haavard Skinnemoen | dc0ee64 | 2008-07-08 11:59:35 -0700 | [diff] [blame] | 583 | struct dma_async_tx_descriptor *(*device_prep_slave_sg)( |
| 584 | struct dma_chan *chan, struct scatterlist *sgl, |
Vinod Koul | 49920bc | 2011-10-13 15:15:27 +0530 | [diff] [blame] | 585 | unsigned int sg_len, enum dma_transfer_direction direction, |
Alexandre Bounine | 185ecb5 | 2012-03-08 15:35:13 -0500 | [diff] [blame] | 586 | unsigned long flags, void *context); |
Sascha Hauer | 782bc95 | 2010-09-30 13:56:32 +0000 | [diff] [blame] | 587 | struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)( |
| 588 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, |
Alexandre Bounine | 185ecb5 | 2012-03-08 15:35:13 -0500 | [diff] [blame] | 589 | size_t period_len, enum dma_transfer_direction direction, |
| 590 | void *context); |
Jassi Brar | b14dab7 | 2011-10-13 12:33:30 +0530 | [diff] [blame] | 591 | struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)( |
| 592 | struct dma_chan *chan, struct dma_interleaved_template *xt, |
| 593 | unsigned long flags); |
Linus Walleij | 0582763 | 2010-05-17 16:30:42 -0700 | [diff] [blame] | 594 | int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
| 595 | unsigned long arg); |
Haavard Skinnemoen | dc0ee64 | 2008-07-08 11:59:35 -0700 | [diff] [blame] | 596 | |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 597 | enum dma_status (*device_tx_status)(struct dma_chan *chan, |
| 598 | dma_cookie_t cookie, |
| 599 | struct dma_tx_state *txstate); |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 600 | void (*device_issue_pending)(struct dma_chan *chan); |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 601 | }; |
| 602 | |
Sascha Hauer | 6e3ecaf | 2010-09-30 13:56:33 +0000 | [diff] [blame] | 603 | static inline int dmaengine_device_control(struct dma_chan *chan, |
| 604 | enum dma_ctrl_cmd cmd, |
| 605 | unsigned long arg) |
| 606 | { |
| 607 | return chan->device->device_control(chan, cmd, arg); |
| 608 | } |
| 609 | |
| 610 | static inline int dmaengine_slave_config(struct dma_chan *chan, |
| 611 | struct dma_slave_config *config) |
| 612 | { |
| 613 | return dmaengine_device_control(chan, DMA_SLAVE_CONFIG, |
| 614 | (unsigned long)config); |
| 615 | } |
| 616 | |
Vinod Koul | 90b44f8 | 2011-07-25 19:57:52 +0530 | [diff] [blame] | 617 | static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single( |
| 618 | struct dma_chan *chan, void *buf, size_t len, |
Vinod Koul | 49920bc | 2011-10-13 15:15:27 +0530 | [diff] [blame] | 619 | enum dma_transfer_direction dir, unsigned long flags) |
Vinod Koul | 90b44f8 | 2011-07-25 19:57:52 +0530 | [diff] [blame] | 620 | { |
| 621 | struct scatterlist sg; |
| 622 | sg_init_one(&sg, buf, len); |
| 623 | |
Alexandre Bounine | 185ecb5 | 2012-03-08 15:35:13 -0500 | [diff] [blame] | 624 | return chan->device->device_prep_slave_sg(chan, &sg, 1, |
| 625 | dir, flags, NULL); |
Vinod Koul | 90b44f8 | 2011-07-25 19:57:52 +0530 | [diff] [blame] | 626 | } |
| 627 | |
Alexandre Bounine | 1605282 | 2012-03-08 16:11:18 -0500 | [diff] [blame] | 628 | static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg( |
| 629 | struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, |
| 630 | enum dma_transfer_direction dir, unsigned long flags) |
| 631 | { |
| 632 | return chan->device->device_prep_slave_sg(chan, sgl, sg_len, |
Alexandre Bounine | 185ecb5 | 2012-03-08 15:35:13 -0500 | [diff] [blame] | 633 | dir, flags, NULL); |
Alexandre Bounine | 1605282 | 2012-03-08 16:11:18 -0500 | [diff] [blame] | 634 | } |
| 635 | |
| 636 | static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic( |
| 637 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, |
| 638 | size_t period_len, enum dma_transfer_direction dir) |
| 639 | { |
| 640 | return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len, |
Alexandre Bounine | 185ecb5 | 2012-03-08 15:35:13 -0500 | [diff] [blame] | 641 | period_len, dir, NULL); |
Sascha Hauer | 6e3ecaf | 2010-09-30 13:56:33 +0000 | [diff] [blame] | 642 | } |
| 643 | |
| 644 | static inline int dmaengine_terminate_all(struct dma_chan *chan) |
| 645 | { |
| 646 | return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0); |
| 647 | } |
Russell King - ARM Linux | 98d530f | 2011-01-01 23:00:23 +0000 | [diff] [blame] | 648 | |
Sascha Hauer | 6e3ecaf | 2010-09-30 13:56:33 +0000 | [diff] [blame] | 649 | static inline int dmaengine_pause(struct dma_chan *chan) |
| 650 | { |
| 651 | return dmaengine_device_control(chan, DMA_PAUSE, 0); |
| 652 | } |
Dan Williams | 83544ae | 2009-09-08 17:42:53 -0700 | [diff] [blame] | 653 | |
| 654 | static inline int dmaengine_resume(struct dma_chan *chan) |
| 655 | { |
| 656 | return dmaengine_device_control(chan, DMA_RESUME, 0); |
| 657 | } |
| 658 | |
| 659 | static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc) |
| 660 | { |
| 661 | return desc->tx_submit(desc); |
| 662 | } |
| 663 | |
| 664 | static inline bool dmaengine_check_align(u8 align, size_t off1, size_t off2, size_t len) |
| 665 | { |
| 666 | size_t mask; |
| 667 | |
| 668 | if (!align) |
| 669 | return true; |
| 670 | mask = (1 << align) - 1; |
| 671 | if (mask & (off1 | off2 | len)) |
| 672 | return false; |
| 673 | return true; |
| 674 | } |
| 675 | |
| 676 | static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1, |
| 677 | size_t off2, size_t len) |
| 678 | { |
| 679 | return dmaengine_check_align(dev->copy_align, off1, off2, len); |
| 680 | } |
| 681 | |
| 682 | static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1, |
| 683 | size_t off2, size_t len) |
| 684 | { |
| 685 | return dmaengine_check_align(dev->xor_align, off1, off2, len); |
| 686 | } |
| 687 | |
| 688 | static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1, |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 689 | size_t off2, size_t len) |
| 690 | { |
| 691 | return dmaengine_check_align(dev->pq_align, off1, off2, len); |
| 692 | } |
| 693 | |
| 694 | static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1, |
| 695 | size_t off2, size_t len) |
| 696 | { |
| 697 | return dmaengine_check_align(dev->fill_align, off1, off2, len); |
| 698 | } |
| 699 | |
| 700 | static inline void |
| 701 | dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue) |
| 702 | { |
| 703 | dma->max_pq = maxpq; |
| 704 | if (has_pq_continue) |
| 705 | dma->max_pq |= DMA_HAS_PQ_CONTINUE; |
| 706 | } |
| 707 | |
| 708 | static inline bool dmaf_continue(enum dma_ctrl_flags flags) |
| 709 | { |
| 710 | return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE; |
| 711 | } |
| 712 | |
| 713 | static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags) |
Mathieu Lacage | d3f3cf8 | 2010-08-14 15:02:44 +0200 | [diff] [blame] | 714 | { |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 715 | enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P; |
| 716 | |
| 717 | return (flags & mask) == mask; |
| 718 | } |
| 719 | |
| 720 | static inline bool dma_dev_has_pq_continue(struct dma_device *dma) |
| 721 | { |
| 722 | return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE; |
| 723 | } |
| 724 | |
| 725 | static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma) |
| 726 | { |
| 727 | return dma->max_pq & ~DMA_HAS_PQ_CONTINUE; |
| 728 | } |
| 729 | |
| 730 | /* dma_maxpq - reduce maxpq in the face of continued operations |
| 731 | * @dma - dma device with PQ capability |
| 732 | * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set |
| 733 | * |
| 734 | * When an engine does not support native continuation we need 3 extra |
| 735 | * source slots to reuse P and Q with the following coefficients: |
| 736 | * 1/ {00} * P : remove P from Q', but use it as a source for P' |
| 737 | * 2/ {01} * Q : use Q to continue Q' calculation |
| 738 | * 3/ {00} * Q : subtract Q from P' to cancel (2) |
| 739 | * |
| 740 | * In the case where P is disabled we only need 1 extra source: |
| 741 | * 1/ {01} * Q : use Q to continue Q' calculation |
| 742 | */ |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 743 | static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags) |
| 744 | { |
Dan Williams | 649274d | 2009-01-11 00:20:39 -0800 | [diff] [blame] | 745 | if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags)) |
Dan Williams | 209b84a | 2009-01-06 11:38:17 -0700 | [diff] [blame] | 746 | return dma_dev_to_maxpq(dma); |
| 747 | else if (dmaf_p_disabled_continue(flags)) |
Dan Williams | 649274d | 2009-01-11 00:20:39 -0800 | [diff] [blame] | 748 | return dma_dev_to_maxpq(dma) - 1; |
| 749 | else if (dmaf_continue(flags)) |
| 750 | return dma_dev_to_maxpq(dma) - 3; |
| 751 | BUG(); |
| 752 | } |
| 753 | |
| 754 | /* --- public DMA engine API --- */ |
| 755 | |
| 756 | #ifdef CONFIG_DMA_ENGINE |
David S. Miller | b4bd07c | 2009-02-06 22:06:43 -0800 | [diff] [blame] | 757 | void dmaengine_get(void); |
| 758 | void dmaengine_put(void); |
| 759 | #else |
| 760 | static inline void dmaengine_get(void) |
| 761 | { |
| 762 | } |
| 763 | static inline void dmaengine_put(void) |
| 764 | { |
| 765 | } |
| 766 | #endif |
| 767 | |
| 768 | #ifdef CONFIG_NET_DMA |
Dan Williams | 729b5d1 | 2009-03-25 09:13:25 -0700 | [diff] [blame] | 769 | #define net_dmaengine_get() dmaengine_get() |
| 770 | #define net_dmaengine_put() dmaengine_put() |
| 771 | #else |
Dan Williams | 5fc6d89 | 2010-10-07 16:44:50 -0700 | [diff] [blame] | 772 | static inline void net_dmaengine_get(void) |
Dan Williams | 138f4c3 | 2009-09-08 17:42:51 -0700 | [diff] [blame] | 773 | { |
| 774 | } |
Dan Williams | 729b5d1 | 2009-03-25 09:13:25 -0700 | [diff] [blame] | 775 | static inline void net_dmaengine_put(void) |
Dan Williams | 5fc6d89 | 2010-10-07 16:44:50 -0700 | [diff] [blame] | 776 | { |
Dan Williams | 729b5d1 | 2009-03-25 09:13:25 -0700 | [diff] [blame] | 777 | } |
| 778 | #endif |
| 779 | |
| 780 | #ifdef CONFIG_ASYNC_TX_DMA |
| 781 | #define async_dmaengine_get() dmaengine_get() |
| 782 | #define async_dmaengine_put() dmaengine_put() |
| 783 | #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH |
| 784 | #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX) |
| 785 | #else |
| 786 | #define async_dma_find_channel(type) dma_find_channel(type) |
| 787 | #endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */ |
| 788 | #else |
Dan Williams | 138f4c3 | 2009-09-08 17:42:51 -0700 | [diff] [blame] | 789 | static inline void async_dmaengine_get(void) |
Dan Williams | 729b5d1 | 2009-03-25 09:13:25 -0700 | [diff] [blame] | 790 | { |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 791 | } |
| 792 | static inline void async_dmaengine_put(void) |
| 793 | { |
| 794 | } |
| 795 | static inline struct dma_chan * |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 796 | async_dma_find_channel(enum dma_transaction_type type) |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 797 | { |
| 798 | return NULL; |
| 799 | } |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 800 | #endif /* CONFIG_ASYNC_TX_DMA */ |
Dan Williams | 0839875 | 2008-07-17 17:59:56 -0700 | [diff] [blame] | 801 | |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 802 | dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan, |
Dan Williams | 636bdea | 2008-04-17 20:17:26 -0700 | [diff] [blame] | 803 | void *dest, void *src, size_t len); |
| 804 | dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan, |
| 805 | struct page *page, unsigned int offset, void *kdata, size_t len); |
Guennadi Liakhovetski | ef56068 | 2009-01-19 15:36:21 -0700 | [diff] [blame] | 806 | dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan, |
| 807 | struct page *dest_pg, unsigned int dest_off, struct page *src_pg, |
| 808 | unsigned int src_off, size_t len); |
| 809 | void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx, |
| 810 | struct dma_chan *chan); |
Dan Williams | 0839875 | 2008-07-17 17:59:56 -0700 | [diff] [blame] | 811 | |
Dan Williams | 636bdea | 2008-04-17 20:17:26 -0700 | [diff] [blame] | 812 | static inline void async_tx_ack(struct dma_async_tx_descriptor *tx) |
Dan Williams | 0839875 | 2008-07-17 17:59:56 -0700 | [diff] [blame] | 813 | { |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 814 | tx->flags |= DMA_CTRL_ACK; |
| 815 | } |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 816 | |
| 817 | static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx) |
| 818 | { |
| 819 | tx->flags &= ~DMA_CTRL_ACK; |
| 820 | } |
| 821 | |
| 822 | static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx) |
| 823 | { |
| 824 | return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK; |
| 825 | } |
| 826 | |
| 827 | #define first_dma_cap(mask) __first_dma_cap(&(mask)) |
| 828 | static inline int __first_dma_cap(const dma_cap_mask_t *srcp) |
| 829 | { |
| 830 | return min_t(int, DMA_TX_TYPE_END, |
| 831 | find_first_bit(srcp->bits, DMA_TX_TYPE_END)); |
| 832 | } |
| 833 | |
| 834 | #define next_dma_cap(n, mask) __next_dma_cap((n), &(mask)) |
| 835 | static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp) |
| 836 | { |
Atsushi Nemoto | 0f57151 | 2009-03-06 20:07:14 +0900 | [diff] [blame] | 837 | return min_t(int, DMA_TX_TYPE_END, |
| 838 | find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1)); |
| 839 | } |
| 840 | |
| 841 | #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask)) |
| 842 | static inline void |
| 843 | __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) |
Dan Williams | 33df8ca | 2009-01-06 11:38:15 -0700 | [diff] [blame] | 844 | { |
| 845 | set_bit(tx_type, dstp->bits); |
| 846 | } |
| 847 | |
| 848 | #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask)) |
| 849 | static inline void |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 850 | __dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) |
| 851 | { |
| 852 | clear_bit(tx_type, dstp->bits); |
| 853 | } |
| 854 | |
| 855 | #define dma_cap_zero(mask) __dma_cap_zero(&(mask)) |
| 856 | static inline void __dma_cap_zero(dma_cap_mask_t *dstp) |
| 857 | { |
| 858 | bitmap_zero(dstp->bits, DMA_TX_TYPE_END); |
| 859 | } |
| 860 | |
| 861 | #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask)) |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 862 | static inline int |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 863 | __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp) |
Randy Dunlap | fe4ada2 | 2006-07-03 19:44:51 -0700 | [diff] [blame] | 864 | { |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 865 | return test_bit(tx_type, srcp->bits); |
| 866 | } |
| 867 | |
| 868 | #define for_each_dma_cap_mask(cap, mask) \ |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 869 | for ((cap) = first_dma_cap(mask); \ |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 870 | (cap) < DMA_TX_TYPE_END; \ |
Dan Williams | ec8670f | 2008-03-01 07:51:29 -0700 | [diff] [blame] | 871 | (cap) = next_dma_cap((cap), (mask))) |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 872 | |
| 873 | /** |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 874 | * dma_async_issue_pending - flush pending transactions to HW |
| 875 | * @chan: target DMA channel |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 876 | * |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 877 | * This allows drivers to push copies to HW in batches, |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 878 | * reducing MMIO writes where possible. |
| 879 | */ |
| 880 | static inline void dma_async_issue_pending(struct dma_chan *chan) |
| 881 | { |
| 882 | chan->device->device_issue_pending(chan); |
| 883 | } |
| 884 | |
| 885 | #define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan) |
| 886 | |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 887 | /** |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 888 | * dma_async_is_tx_complete - poll for transaction completion |
| 889 | * @chan: DMA channel |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 890 | * @cookie: transaction identifier to check status of |
| 891 | * @last: returns last completed cookie, can be NULL |
| 892 | * @used: returns last issued cookie, can be NULL |
| 893 | * |
| 894 | * If @last and @used are passed in, upon return they reflect the driver |
| 895 | * internal state and can be used with dma_async_is_complete() to check |
| 896 | * the status of multiple cookies without re-checking hardware state. |
| 897 | */ |
| 898 | static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan, |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 899 | dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used) |
| 900 | { |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 901 | struct dma_tx_state state; |
| 902 | enum dma_status status; |
| 903 | |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 904 | status = chan->device->device_tx_status(chan, cookie, &state); |
| 905 | if (last) |
| 906 | *last = state.last; |
| 907 | if (used) |
| 908 | *used = state.used; |
| 909 | return status; |
| 910 | } |
Sebastian Siewior | 8a5703f | 2008-04-21 22:38:45 +0000 | [diff] [blame] | 911 | |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 912 | #define dma_async_memcpy_complete(chan, cookie, last, used)\ |
| 913 | dma_async_is_tx_complete(chan, cookie, last, used) |
| 914 | |
| 915 | /** |
| 916 | * dma_async_is_complete - test a cookie against chan state |
| 917 | * @cookie: transaction identifier to test status of |
| 918 | * @last_complete: last know completed transaction |
| 919 | * @last_used: last cookie value handed out |
| 920 | * |
| 921 | * dma_async_is_complete() is used in dma_async_memcpy_complete() |
| 922 | * the test logic is separated for lightweight testing of multiple cookies |
| 923 | */ |
| 924 | static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie, |
| 925 | dma_cookie_t last_complete, dma_cookie_t last_used) |
Dan Williams | bca3469 | 2010-03-26 16:52:10 -0700 | [diff] [blame] | 926 | { |
| 927 | if (last_complete <= last_used) { |
| 928 | if ((cookie <= last_complete) || (cookie > last_used)) |
| 929 | return DMA_SUCCESS; |
| 930 | } else { |
| 931 | if ((cookie <= last_complete) && (cookie > last_used)) |
| 932 | return DMA_SUCCESS; |
| 933 | } |
| 934 | return DMA_IN_PROGRESS; |
| 935 | } |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 936 | |
Dan Williams | 07f2211 | 2009-01-05 17:14:31 -0700 | [diff] [blame] | 937 | static inline void |
| 938 | dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue) |
Dan Williams | c50331e | 2009-01-19 15:33:14 -0700 | [diff] [blame] | 939 | { |
Guennadi Liakhovetski | 8f33d52 | 2010-12-22 14:46:46 +0100 | [diff] [blame] | 940 | if (st) { |
| 941 | st->last = last; |
Dan Williams | 07f2211 | 2009-01-05 17:14:31 -0700 | [diff] [blame] | 942 | st->used = used; |
| 943 | st->residue = residue; |
| 944 | } |
| 945 | } |
| 946 | |
Dan Williams | c50331e | 2009-01-19 15:33:14 -0700 | [diff] [blame] | 947 | enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie); |
| 948 | #ifdef CONFIG_DMA_ENGINE |
Guennadi Liakhovetski | 8f33d52 | 2010-12-22 14:46:46 +0100 | [diff] [blame] | 949 | enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx); |
| 950 | void dma_issue_pending_all(void); |
| 951 | struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param); |
| 952 | void dma_release_channel(struct dma_chan *chan); |
| 953 | #else |
| 954 | static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx) |
| 955 | { |
| 956 | return DMA_SUCCESS; |
Dan Williams | c50331e | 2009-01-19 15:33:14 -0700 | [diff] [blame] | 957 | } |
Dan Williams | 07f2211 | 2009-01-05 17:14:31 -0700 | [diff] [blame] | 958 | static inline void dma_issue_pending_all(void) |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 959 | { |
| 960 | } |
| 961 | static inline struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, |
| 962 | dma_filter_fn fn, void *fn_param) |
| 963 | { |
Dan Williams | 07f2211 | 2009-01-05 17:14:31 -0700 | [diff] [blame] | 964 | return NULL; |
Dan Williams | bec0851 | 2009-01-06 11:38:14 -0700 | [diff] [blame] | 965 | } |
Dan Williams | 59b5ec2 | 2009-01-06 11:38:15 -0700 | [diff] [blame] | 966 | static inline void dma_release_channel(struct dma_chan *chan) |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 967 | { |
Chris Leech | de5506e | 2006-05-23 17:50:37 -0700 | [diff] [blame] | 968 | } |
| 969 | #endif |
| 970 | |
Al Viro | b2ddb90 | 2008-03-29 03:09:38 +0000 | [diff] [blame] | 971 | /* --- DMA device --- */ |
Chris Leech | de5506e | 2006-05-23 17:50:37 -0700 | [diff] [blame] | 972 | |
| 973 | int dma_async_device_register(struct dma_device *device); |
| 974 | void dma_async_device_unregister(struct dma_device *device); |
| 975 | void dma_run_dependencies(struct dma_async_tx_descriptor *tx); |
| 976 | struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type); |
| 977 | #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y) |
| 978 | |
| 979 | /* --- Helper iov-locking functions --- */ |
| 980 | |
| 981 | struct dma_page_list { |
| 982 | char __user *base_address; |
| 983 | int nr_pages; |
| 984 | struct page **pages; |
| 985 | }; |
| 986 | |
| 987 | struct dma_pinned_list { |
| 988 | int nr_iovecs; |
| 989 | struct dma_page_list page_list[0]; |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 990 | }; |
| 991 | |
| 992 | struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len); |
| 993 | void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list); |
| 994 | |
| 995 | dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov, |
| 996 | struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len); |
| 997 | dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov, |
| 998 | struct dma_pinned_list *pinned_list, struct page *page, |
| 999 | unsigned int offset, size_t len); |
| 1000 | |
| 1001 | #endif /* DMAENGINE_H */ |