blob: c19f49bce7af41678b4ef58a16e4e8344a26b313 [file] [log] [blame]
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001/*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
Stephen Hemminger747802a2005-06-27 11:33:16 -070010 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040011 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
Arnaldo Carvalho de Melo14c85022005-12-27 02:43:12 -020027#include <linux/in.h>
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040028#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/moduleparam.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/pci.h>
35#include <linux/if_vlan.h>
36#include <linux/ip.h>
37#include <linux/delay.h>
38#include <linux/crc32.h>
Al Viro40754002005-04-03 09:15:52 +010039#include <linux/dma-mapping.h>
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -080040#include <linux/mii.h>
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040041#include <asm/irq.h>
42
43#include "skge.h"
44
45#define DRV_NAME "skge"
Stephen Hemmingerf6aa1692006-09-01 15:53:50 -070046#define DRV_VERSION "1.8"
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040047#define PFX DRV_NAME " "
48
49#define DEFAULT_TX_RING_SIZE 128
50#define DEFAULT_RX_RING_SIZE 512
51#define MAX_TX_RING_SIZE 1024
Stephen Hemminger9db96472006-06-06 10:11:12 -070052#define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040053#define MAX_RX_RING_SIZE 4096
Stephen Hemminger19a33d42005-06-27 11:33:15 -070054#define RX_COPY_THRESHOLD 128
55#define RX_BUF_SIZE 1536
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040056#define PHY_RETRIES 1000
57#define ETH_JUMBO_MTU 9000
58#define TX_WATCHDOG (5 * HZ)
59#define NAPI_WEIGHT 64
Stephen Hemminger6abebb52005-07-22 16:26:10 -070060#define BLINK_MS 250
Stephen Hemminger64f6b642006-09-23 21:25:28 -070061#define LINK_HZ (HZ/2)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040062
63MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
64MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
65MODULE_LICENSE("GPL");
66MODULE_VERSION(DRV_VERSION);
67
68static const u32 default_msg
69 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
70 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
71
72static int debug = -1; /* defaults above */
73module_param(debug, int, 0);
74MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
75
76static const struct pci_device_id skge_id_table[] = {
Stephen Hemminger275834d2005-06-27 11:33:03 -070077 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
78 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
79 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
80 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
Stephen Hemminger275834d2005-06-27 11:33:03 -070081 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
Stephen Hemminger2d2a3872006-05-17 14:37:04 -070082 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */
Stephen Hemminger275834d2005-06-27 11:33:03 -070083 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
84 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
85 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
Stephen Hemminger275834d2005-06-27 11:33:03 -070086 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
Francois Romieu86f0cd52005-08-24 01:14:23 +020087 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040088 { 0 }
89};
90MODULE_DEVICE_TABLE(pci, skge_id_table);
91
92static int skge_up(struct net_device *dev);
93static int skge_down(struct net_device *dev);
Stephen Hemmingeree294dc2005-12-14 15:47:44 -080094static void skge_phy_reset(struct skge_port *skge);
Stephen Hemminger513f5332006-09-01 15:53:49 -070095static void skge_tx_clean(struct net_device *dev);
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -080096static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
97static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040098static void genesis_get_stats(struct skge_port *skge, u64 *data);
99static void yukon_get_stats(struct skge_port *skge, u64 *data);
100static void yukon_init(struct skge_hw *hw, int port);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400101static void genesis_mac_init(struct skge_hw *hw, int port);
Stephen Hemminger45bada62005-06-27 11:33:12 -0700102static void genesis_link_up(struct skge_port *skge);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400103
Stephen Hemminger7e676d92005-06-27 11:33:13 -0700104/* Avoid conditionals by using array */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400105static const int txqaddr[] = { Q_XA1, Q_XA2 };
106static const int rxqaddr[] = { Q_R1, Q_R2 };
107static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
108static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
Stephen Hemminger513f5332006-09-01 15:53:49 -0700109static const u32 irqmask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400110
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400111static int skge_get_regs_len(struct net_device *dev)
112{
Stephen Hemmingerc3f8be92005-09-19 15:37:34 -0700113 return 0x4000;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400114}
115
116/*
Stephen Hemmingerc3f8be92005-09-19 15:37:34 -0700117 * Returns copy of whole control register region
118 * Note: skip RAM address register because accessing it will
119 * cause bus hangs!
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400120 */
121static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
122 void *p)
123{
124 const struct skge_port *skge = netdev_priv(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400125 const void __iomem *io = skge->hw->regs;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400126
127 regs->version = 1;
Stephen Hemmingerc3f8be92005-09-19 15:37:34 -0700128 memset(p, 0, regs->len);
129 memcpy_fromio(p, io, B3_RAM_ADDR);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400130
Stephen Hemmingerc3f8be92005-09-19 15:37:34 -0700131 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
132 regs->len - B3_RI_WTO_R1);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400133}
134
Stephen Hemminger8f3f8192005-11-08 10:33:45 -0800135/* Wake on Lan only supported on Yukon chips with rev 1 or above */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400136static int wol_supported(const struct skge_hw *hw)
137{
138 return !((hw->chip_id == CHIP_ID_GENESIS ||
Stephen Hemminger981d0372005-06-27 11:33:06 -0700139 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400140}
141
142static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
143{
144 struct skge_port *skge = netdev_priv(dev);
145
146 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
147 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
148}
149
150static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
151{
152 struct skge_port *skge = netdev_priv(dev);
153 struct skge_hw *hw = skge->hw;
154
Stephen Hemminger95566062005-06-27 11:33:02 -0700155 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400156 return -EOPNOTSUPP;
157
158 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
159 return -EOPNOTSUPP;
160
161 skge->wol = wol->wolopts == WAKE_MAGIC;
162
163 if (skge->wol) {
164 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
165
166 skge_write16(hw, WOL_CTRL_STAT,
167 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
168 WOL_CTL_ENA_MAGIC_PKT_UNIT);
169 } else
170 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
171
172 return 0;
173}
174
Stephen Hemminger8f3f8192005-11-08 10:33:45 -0800175/* Determine supported/advertised modes based on hardware.
176 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700177 */
178static u32 skge_supported_modes(const struct skge_hw *hw)
179{
180 u32 supported;
181
Stephen Hemminger5e1705d2005-08-16 14:00:58 -0700182 if (hw->copper) {
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700183 supported = SUPPORTED_10baseT_Half
184 | SUPPORTED_10baseT_Full
185 | SUPPORTED_100baseT_Half
186 | SUPPORTED_100baseT_Full
187 | SUPPORTED_1000baseT_Half
188 | SUPPORTED_1000baseT_Full
189 | SUPPORTED_Autoneg| SUPPORTED_TP;
190
191 if (hw->chip_id == CHIP_ID_GENESIS)
192 supported &= ~(SUPPORTED_10baseT_Half
193 | SUPPORTED_10baseT_Full
194 | SUPPORTED_100baseT_Half
195 | SUPPORTED_100baseT_Full);
196
197 else if (hw->chip_id == CHIP_ID_YUKON)
198 supported &= ~SUPPORTED_1000baseT_Half;
199 } else
Stephen Hemminger4b67be92006-10-05 15:49:51 -0700200 supported = SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half
201 | SUPPORTED_FIBRE | SUPPORTED_Autoneg;
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700202
203 return supported;
204}
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400205
206static int skge_get_settings(struct net_device *dev,
207 struct ethtool_cmd *ecmd)
208{
209 struct skge_port *skge = netdev_priv(dev);
210 struct skge_hw *hw = skge->hw;
211
212 ecmd->transceiver = XCVR_INTERNAL;
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700213 ecmd->supported = skge_supported_modes(hw);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400214
Stephen Hemminger5e1705d2005-08-16 14:00:58 -0700215 if (hw->copper) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400216 ecmd->port = PORT_TP;
217 ecmd->phy_address = hw->phy_addr;
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700218 } else
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400219 ecmd->port = PORT_FIBRE;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400220
221 ecmd->advertising = skge->advertising;
222 ecmd->autoneg = skge->autoneg;
223 ecmd->speed = skge->speed;
224 ecmd->duplex = skge->duplex;
225 return 0;
226}
227
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400228static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
229{
230 struct skge_port *skge = netdev_priv(dev);
231 const struct skge_hw *hw = skge->hw;
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700232 u32 supported = skge_supported_modes(hw);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400233
234 if (ecmd->autoneg == AUTONEG_ENABLE) {
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700235 ecmd->advertising = supported;
236 skge->duplex = -1;
237 skge->speed = -1;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400238 } else {
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700239 u32 setting;
240
Stephen Hemminger2c668512005-07-22 16:26:07 -0700241 switch (ecmd->speed) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400242 case SPEED_1000:
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700243 if (ecmd->duplex == DUPLEX_FULL)
244 setting = SUPPORTED_1000baseT_Full;
245 else if (ecmd->duplex == DUPLEX_HALF)
246 setting = SUPPORTED_1000baseT_Half;
247 else
248 return -EINVAL;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400249 break;
250 case SPEED_100:
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700251 if (ecmd->duplex == DUPLEX_FULL)
252 setting = SUPPORTED_100baseT_Full;
253 else if (ecmd->duplex == DUPLEX_HALF)
254 setting = SUPPORTED_100baseT_Half;
255 else
256 return -EINVAL;
257 break;
258
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400259 case SPEED_10:
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700260 if (ecmd->duplex == DUPLEX_FULL)
261 setting = SUPPORTED_10baseT_Full;
262 else if (ecmd->duplex == DUPLEX_HALF)
263 setting = SUPPORTED_10baseT_Half;
264 else
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400265 return -EINVAL;
266 break;
267 default:
268 return -EINVAL;
269 }
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700270
271 if ((setting & supported) == 0)
272 return -EINVAL;
273
274 skge->speed = ecmd->speed;
275 skge->duplex = ecmd->duplex;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400276 }
277
278 skge->autoneg = ecmd->autoneg;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400279 skge->advertising = ecmd->advertising;
280
Stephen Hemmingeree294dc2005-12-14 15:47:44 -0800281 if (netif_running(dev))
282 skge_phy_reset(skge);
283
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400284 return (0);
285}
286
287static void skge_get_drvinfo(struct net_device *dev,
288 struct ethtool_drvinfo *info)
289{
290 struct skge_port *skge = netdev_priv(dev);
291
292 strcpy(info->driver, DRV_NAME);
293 strcpy(info->version, DRV_VERSION);
294 strcpy(info->fw_version, "N/A");
295 strcpy(info->bus_info, pci_name(skge->hw->pdev));
296}
297
298static const struct skge_stat {
299 char name[ETH_GSTRING_LEN];
300 u16 xmac_offset;
301 u16 gma_offset;
302} skge_stats[] = {
303 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
304 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
305
306 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
307 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
308 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
309 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
310 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
311 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
312 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
313 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
314
315 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
316 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
317 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
318 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
319 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
320 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
321
322 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
323 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
324 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
325 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
326 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
327};
328
329static int skge_get_stats_count(struct net_device *dev)
330{
331 return ARRAY_SIZE(skge_stats);
332}
333
334static void skge_get_ethtool_stats(struct net_device *dev,
335 struct ethtool_stats *stats, u64 *data)
336{
337 struct skge_port *skge = netdev_priv(dev);
338
339 if (skge->hw->chip_id == CHIP_ID_GENESIS)
340 genesis_get_stats(skge, data);
341 else
342 yukon_get_stats(skge, data);
343}
344
345/* Use hardware MIB variables for critical path statistics and
346 * transmit feedback not reported at interrupt.
347 * Other errors are accounted for in interrupt handler.
348 */
349static struct net_device_stats *skge_get_stats(struct net_device *dev)
350{
351 struct skge_port *skge = netdev_priv(dev);
352 u64 data[ARRAY_SIZE(skge_stats)];
353
354 if (skge->hw->chip_id == CHIP_ID_GENESIS)
355 genesis_get_stats(skge, data);
356 else
357 yukon_get_stats(skge, data);
358
359 skge->net_stats.tx_bytes = data[0];
360 skge->net_stats.rx_bytes = data[1];
361 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
362 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
Stephen Hemminger4c180fc2006-03-23 11:07:26 -0800363 skge->net_stats.multicast = data[3] + data[5];
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400364 skge->net_stats.collisions = data[10];
365 skge->net_stats.tx_aborted_errors = data[12];
366
367 return &skge->net_stats;
368}
369
370static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
371{
372 int i;
373
Stephen Hemminger95566062005-06-27 11:33:02 -0700374 switch (stringset) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400375 case ETH_SS_STATS:
376 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
377 memcpy(data + i * ETH_GSTRING_LEN,
378 skge_stats[i].name, ETH_GSTRING_LEN);
379 break;
380 }
381}
382
383static void skge_get_ring_param(struct net_device *dev,
384 struct ethtool_ringparam *p)
385{
386 struct skge_port *skge = netdev_priv(dev);
387
388 p->rx_max_pending = MAX_RX_RING_SIZE;
389 p->tx_max_pending = MAX_TX_RING_SIZE;
390 p->rx_mini_max_pending = 0;
391 p->rx_jumbo_max_pending = 0;
392
393 p->rx_pending = skge->rx_ring.count;
394 p->tx_pending = skge->tx_ring.count;
395 p->rx_mini_pending = 0;
396 p->rx_jumbo_pending = 0;
397}
398
399static int skge_set_ring_param(struct net_device *dev,
400 struct ethtool_ringparam *p)
401{
402 struct skge_port *skge = netdev_priv(dev);
Stephen Hemminger3b8bb472005-12-14 15:47:48 -0800403 int err;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400404
405 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
Stephen Hemminger9db96472006-06-06 10:11:12 -0700406 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400407 return -EINVAL;
408
409 skge->rx_ring.count = p->rx_pending;
410 skge->tx_ring.count = p->tx_pending;
411
412 if (netif_running(dev)) {
413 skge_down(dev);
Stephen Hemminger3b8bb472005-12-14 15:47:48 -0800414 err = skge_up(dev);
415 if (err)
416 dev_close(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400417 }
418
419 return 0;
420}
421
422static u32 skge_get_msglevel(struct net_device *netdev)
423{
424 struct skge_port *skge = netdev_priv(netdev);
425 return skge->msg_enable;
426}
427
428static void skge_set_msglevel(struct net_device *netdev, u32 value)
429{
430 struct skge_port *skge = netdev_priv(netdev);
431 skge->msg_enable = value;
432}
433
434static int skge_nway_reset(struct net_device *dev)
435{
436 struct skge_port *skge = netdev_priv(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400437
438 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
439 return -EINVAL;
440
Stephen Hemmingeree294dc2005-12-14 15:47:44 -0800441 skge_phy_reset(skge);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400442 return 0;
443}
444
445static int skge_set_sg(struct net_device *dev, u32 data)
446{
447 struct skge_port *skge = netdev_priv(dev);
448 struct skge_hw *hw = skge->hw;
449
450 if (hw->chip_id == CHIP_ID_GENESIS && data)
451 return -EOPNOTSUPP;
452 return ethtool_op_set_sg(dev, data);
453}
454
455static int skge_set_tx_csum(struct net_device *dev, u32 data)
456{
457 struct skge_port *skge = netdev_priv(dev);
458 struct skge_hw *hw = skge->hw;
459
460 if (hw->chip_id == CHIP_ID_GENESIS && data)
461 return -EOPNOTSUPP;
462
463 return ethtool_op_set_tx_csum(dev, data);
464}
465
466static u32 skge_get_rx_csum(struct net_device *dev)
467{
468 struct skge_port *skge = netdev_priv(dev);
469
470 return skge->rx_csum;
471}
472
473/* Only Yukon supports checksum offload. */
474static int skge_set_rx_csum(struct net_device *dev, u32 data)
475{
476 struct skge_port *skge = netdev_priv(dev);
477
478 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
479 return -EOPNOTSUPP;
480
481 skge->rx_csum = data;
482 return 0;
483}
484
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400485static void skge_get_pauseparam(struct net_device *dev,
486 struct ethtool_pauseparam *ecmd)
487{
488 struct skge_port *skge = netdev_priv(dev);
489
490 ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
491 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
492 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
493 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
494
495 ecmd->autoneg = skge->autoneg;
496}
497
498static int skge_set_pauseparam(struct net_device *dev,
499 struct ethtool_pauseparam *ecmd)
500{
501 struct skge_port *skge = netdev_priv(dev);
502
503 skge->autoneg = ecmd->autoneg;
504 if (ecmd->rx_pause && ecmd->tx_pause)
505 skge->flow_control = FLOW_MODE_SYMMETRIC;
Stephen Hemminger95566062005-06-27 11:33:02 -0700506 else if (ecmd->rx_pause && !ecmd->tx_pause)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400507 skge->flow_control = FLOW_MODE_REM_SEND;
Stephen Hemminger95566062005-06-27 11:33:02 -0700508 else if (!ecmd->rx_pause && ecmd->tx_pause)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400509 skge->flow_control = FLOW_MODE_LOC_SEND;
510 else
511 skge->flow_control = FLOW_MODE_NONE;
512
Stephen Hemmingere8df8552005-12-14 15:47:45 -0800513 if (netif_running(dev))
514 skge_phy_reset(skge);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400515 return 0;
516}
517
518/* Chip internal frequency for clock calculations */
519static inline u32 hwkhz(const struct skge_hw *hw)
520{
Stephen Hemminger187ff3b2006-07-19 14:08:42 -0700521 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400522}
523
Stephen Hemminger8f3f8192005-11-08 10:33:45 -0800524/* Chip HZ to microseconds */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400525static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
526{
527 return (ticks * 1000) / hwkhz(hw);
528}
529
Stephen Hemminger8f3f8192005-11-08 10:33:45 -0800530/* Microseconds to chip HZ */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400531static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
532{
533 return hwkhz(hw) * usec / 1000;
534}
535
536static int skge_get_coalesce(struct net_device *dev,
537 struct ethtool_coalesce *ecmd)
538{
539 struct skge_port *skge = netdev_priv(dev);
540 struct skge_hw *hw = skge->hw;
541 int port = skge->port;
542
543 ecmd->rx_coalesce_usecs = 0;
544 ecmd->tx_coalesce_usecs = 0;
545
546 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
547 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
548 u32 msk = skge_read32(hw, B2_IRQM_MSK);
549
550 if (msk & rxirqmask[port])
551 ecmd->rx_coalesce_usecs = delay;
552 if (msk & txirqmask[port])
553 ecmd->tx_coalesce_usecs = delay;
554 }
555
556 return 0;
557}
558
559/* Note: interrupt timer is per board, but can turn on/off per port */
560static int skge_set_coalesce(struct net_device *dev,
561 struct ethtool_coalesce *ecmd)
562{
563 struct skge_port *skge = netdev_priv(dev);
564 struct skge_hw *hw = skge->hw;
565 int port = skge->port;
566 u32 msk = skge_read32(hw, B2_IRQM_MSK);
567 u32 delay = 25;
568
569 if (ecmd->rx_coalesce_usecs == 0)
570 msk &= ~rxirqmask[port];
571 else if (ecmd->rx_coalesce_usecs < 25 ||
572 ecmd->rx_coalesce_usecs > 33333)
573 return -EINVAL;
574 else {
575 msk |= rxirqmask[port];
576 delay = ecmd->rx_coalesce_usecs;
577 }
578
579 if (ecmd->tx_coalesce_usecs == 0)
580 msk &= ~txirqmask[port];
581 else if (ecmd->tx_coalesce_usecs < 25 ||
582 ecmd->tx_coalesce_usecs > 33333)
583 return -EINVAL;
584 else {
585 msk |= txirqmask[port];
586 delay = min(delay, ecmd->rx_coalesce_usecs);
587 }
588
589 skge_write32(hw, B2_IRQM_MSK, msk);
590 if (msk == 0)
591 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
592 else {
593 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
594 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
595 }
596 return 0;
597}
598
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700599enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
600static void skge_led(struct skge_port *skge, enum led_mode mode)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400601{
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400602 struct skge_hw *hw = skge->hw;
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700603 int port = skge->port;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400604
Stephen Hemmingerd85b5142006-06-06 10:11:11 -0700605 mutex_lock(&hw->phy_mutex);
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700606 if (hw->chip_id == CHIP_ID_GENESIS) {
607 switch (mode) {
608 case LED_MODE_OFF:
Stephen Hemminger64f6b642006-09-23 21:25:28 -0700609 if (hw->phy_type == SK_PHY_BCOM)
610 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
611 else {
612 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
613 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
614 }
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700615 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
616 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
617 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
618 break;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400619
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700620 case LED_MODE_ON:
621 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
622 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
623
624 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
625 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
626
627 break;
628
629 case LED_MODE_TST:
630 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
631 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
632 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
633
Stephen Hemminger64f6b642006-09-23 21:25:28 -0700634 if (hw->phy_type == SK_PHY_BCOM)
635 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
636 else {
637 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
638 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
639 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
640 }
641
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700642 }
643 } else {
644 switch (mode) {
645 case LED_MODE_OFF:
646 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
647 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
648 PHY_M_LED_MO_DUP(MO_LED_OFF) |
649 PHY_M_LED_MO_10(MO_LED_OFF) |
650 PHY_M_LED_MO_100(MO_LED_OFF) |
651 PHY_M_LED_MO_1000(MO_LED_OFF) |
652 PHY_M_LED_MO_RX(MO_LED_OFF));
653 break;
654 case LED_MODE_ON:
655 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
656 PHY_M_LED_PULS_DUR(PULS_170MS) |
657 PHY_M_LED_BLINK_RT(BLINK_84MS) |
658 PHY_M_LEDC_TX_CTRL |
659 PHY_M_LEDC_DP_CTRL);
Stephen Hemminger46a60f22005-09-09 12:54:56 -0700660
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700661 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
662 PHY_M_LED_MO_RX(MO_LED_OFF) |
663 (skge->speed == SPEED_100 ?
664 PHY_M_LED_MO_100(MO_LED_ON) : 0));
665 break;
666 case LED_MODE_TST:
667 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
668 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
669 PHY_M_LED_MO_DUP(MO_LED_ON) |
670 PHY_M_LED_MO_10(MO_LED_ON) |
671 PHY_M_LED_MO_100(MO_LED_ON) |
672 PHY_M_LED_MO_1000(MO_LED_ON) |
673 PHY_M_LED_MO_RX(MO_LED_ON));
674 }
675 }
Stephen Hemmingerd85b5142006-06-06 10:11:11 -0700676 mutex_unlock(&hw->phy_mutex);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400677}
678
679/* blink LED's for finding board */
680static int skge_phys_id(struct net_device *dev, u32 data)
681{
682 struct skge_port *skge = netdev_priv(dev);
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700683 unsigned long ms;
684 enum led_mode mode = LED_MODE_TST;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400685
Stephen Hemminger95566062005-06-27 11:33:02 -0700686 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700687 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
688 else
689 ms = data * 1000;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400690
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700691 while (ms > 0) {
692 skge_led(skge, mode);
693 mode ^= LED_MODE_TST;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400694
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700695 if (msleep_interruptible(BLINK_MS))
696 break;
697 ms -= BLINK_MS;
698 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400699
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700700 /* back to regular LED state */
701 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400702
703 return 0;
704}
705
Jeff Garzik7282d492006-09-13 14:30:00 -0400706static const struct ethtool_ops skge_ethtool_ops = {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400707 .get_settings = skge_get_settings,
708 .set_settings = skge_set_settings,
709 .get_drvinfo = skge_get_drvinfo,
710 .get_regs_len = skge_get_regs_len,
711 .get_regs = skge_get_regs,
712 .get_wol = skge_get_wol,
713 .set_wol = skge_set_wol,
714 .get_msglevel = skge_get_msglevel,
715 .set_msglevel = skge_set_msglevel,
716 .nway_reset = skge_nway_reset,
717 .get_link = ethtool_op_get_link,
718 .get_ringparam = skge_get_ring_param,
719 .set_ringparam = skge_set_ring_param,
720 .get_pauseparam = skge_get_pauseparam,
721 .set_pauseparam = skge_set_pauseparam,
722 .get_coalesce = skge_get_coalesce,
723 .set_coalesce = skge_set_coalesce,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400724 .get_sg = ethtool_op_get_sg,
725 .set_sg = skge_set_sg,
726 .get_tx_csum = ethtool_op_get_tx_csum,
727 .set_tx_csum = skge_set_tx_csum,
728 .get_rx_csum = skge_get_rx_csum,
729 .set_rx_csum = skge_set_rx_csum,
730 .get_strings = skge_get_strings,
731 .phys_id = skge_phys_id,
732 .get_stats_count = skge_get_stats_count,
733 .get_ethtool_stats = skge_get_ethtool_stats,
John W. Linville56230d52005-09-12 10:48:57 -0400734 .get_perm_addr = ethtool_op_get_perm_addr,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400735};
736
737/*
738 * Allocate ring elements and chain them together
739 * One-to-one association of board descriptors with ring elements
740 */
Stephen Hemmingerc3da1442006-03-21 10:57:01 -0800741static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400742{
743 struct skge_tx_desc *d;
744 struct skge_element *e;
745 int i;
746
Stephen Hemmingerff7907a2006-03-21 10:57:03 -0800747 ring->start = kcalloc(sizeof(*e), ring->count, GFP_KERNEL);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400748 if (!ring->start)
749 return -ENOMEM;
750
751 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
752 e->desc = d;
753 if (i == ring->count - 1) {
754 e->next = ring->start;
755 d->next_offset = base;
756 } else {
757 e->next = e + 1;
758 d->next_offset = base + (i+1) * sizeof(*d);
759 }
760 }
761 ring->to_use = ring->to_clean = ring->start;
762
763 return 0;
764}
765
Stephen Hemminger19a33d42005-06-27 11:33:15 -0700766/* Allocate and setup a new buffer for receiving */
767static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
768 struct sk_buff *skb, unsigned int bufsize)
769{
770 struct skge_rx_desc *rd = e->desc;
771 u64 map;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400772
773 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
774 PCI_DMA_FROMDEVICE);
775
776 rd->dma_lo = map;
777 rd->dma_hi = map >> 32;
778 e->skb = skb;
779 rd->csum1_start = ETH_HLEN;
780 rd->csum2_start = ETH_HLEN;
781 rd->csum1 = 0;
782 rd->csum2 = 0;
783
784 wmb();
785
786 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
787 pci_unmap_addr_set(e, mapaddr, map);
788 pci_unmap_len_set(e, maplen, bufsize);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400789}
790
Stephen Hemminger19a33d42005-06-27 11:33:15 -0700791/* Resume receiving using existing skb,
792 * Note: DMA address is not changed by chip.
793 * MTU not changed while receiver active.
794 */
Stephen Hemminger5a011442006-03-23 11:07:25 -0800795static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
Stephen Hemminger19a33d42005-06-27 11:33:15 -0700796{
797 struct skge_rx_desc *rd = e->desc;
798
799 rd->csum2 = 0;
800 rd->csum2_start = ETH_HLEN;
801
802 wmb();
803
804 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
805}
806
807
808/* Free all buffers in receive ring, assumes receiver stopped */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400809static void skge_rx_clean(struct skge_port *skge)
810{
811 struct skge_hw *hw = skge->hw;
812 struct skge_ring *ring = &skge->rx_ring;
813 struct skge_element *e;
814
Stephen Hemminger19a33d42005-06-27 11:33:15 -0700815 e = ring->start;
816 do {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400817 struct skge_rx_desc *rd = e->desc;
818 rd->control = 0;
Stephen Hemminger19a33d42005-06-27 11:33:15 -0700819 if (e->skb) {
820 pci_unmap_single(hw->pdev,
821 pci_unmap_addr(e, mapaddr),
822 pci_unmap_len(e, maplen),
823 PCI_DMA_FROMDEVICE);
824 dev_kfree_skb(e->skb);
825 e->skb = NULL;
826 }
827 } while ((e = e->next) != ring->start);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400828}
829
Stephen Hemminger19a33d42005-06-27 11:33:15 -0700830
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400831/* Allocate buffers for receive ring
Stephen Hemminger19a33d42005-06-27 11:33:15 -0700832 * For receive: to_clean is next received frame.
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400833 */
Stephen Hemmingerc54f9762006-09-01 15:53:47 -0700834static int skge_rx_fill(struct net_device *dev)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400835{
Stephen Hemmingerc54f9762006-09-01 15:53:47 -0700836 struct skge_port *skge = netdev_priv(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400837 struct skge_ring *ring = &skge->rx_ring;
838 struct skge_element *e;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400839
Stephen Hemminger19a33d42005-06-27 11:33:15 -0700840 e = ring->start;
841 do {
Stephen Hemminger383181a2005-09-19 15:37:16 -0700842 struct sk_buff *skb;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400843
Stephen Hemmingerc54f9762006-09-01 15:53:47 -0700844 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
845 GFP_KERNEL);
Stephen Hemminger19a33d42005-06-27 11:33:15 -0700846 if (!skb)
847 return -ENOMEM;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400848
Stephen Hemminger383181a2005-09-19 15:37:16 -0700849 skb_reserve(skb, NET_IP_ALIGN);
850 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
Stephen Hemminger19a33d42005-06-27 11:33:15 -0700851 } while ( (e = e->next) != ring->start);
852
853 ring->to_clean = ring->start;
854 return 0;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400855}
856
857static void skge_link_up(struct skge_port *skge)
858{
Stephen Hemminger46a60f22005-09-09 12:54:56 -0700859 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
Stephen Hemminger54cfb5a2005-08-16 14:01:05 -0700860 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
861
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400862 netif_carrier_on(skge->netdev);
Stephen Hemminger29b4e882006-03-23 11:07:28 -0800863 netif_wake_queue(skge->netdev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400864
865 if (netif_msg_link(skge))
866 printk(KERN_INFO PFX
867 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
868 skge->netdev->name, skge->speed,
869 skge->duplex == DUPLEX_FULL ? "full" : "half",
870 (skge->flow_control == FLOW_MODE_NONE) ? "none" :
871 (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
872 (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
873 (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
874 "unknown");
875}
876
877static void skge_link_down(struct skge_port *skge)
878{
Stephen Hemminger54cfb5a2005-08-16 14:01:05 -0700879 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400880 netif_carrier_off(skge->netdev);
881 netif_stop_queue(skge->netdev);
882
883 if (netif_msg_link(skge))
884 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
885}
886
Stephen Hemmingera1bc9b82006-10-05 15:49:50 -0700887
888static void xm_link_down(struct skge_hw *hw, int port)
889{
890 struct net_device *dev = hw->dev[port];
891 struct skge_port *skge = netdev_priv(dev);
892 u16 cmd, msk;
893
894 if (hw->phy_type == SK_PHY_XMAC) {
895 msk = xm_read16(hw, port, XM_IMSK);
896 msk |= XM_IS_INP_ASS | XM_IS_LIPA_RC | XM_IS_RX_PAGE | XM_IS_AND;
897 xm_write16(hw, port, XM_IMSK, msk);
898 }
899
900 cmd = xm_read16(hw, port, XM_MMU_CMD);
901 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
902 xm_write16(hw, port, XM_MMU_CMD, cmd);
903 /* dummy read to ensure writing */
904 (void) xm_read16(hw, port, XM_MMU_CMD);
905
906 if (netif_carrier_ok(dev))
907 skge_link_down(skge);
908}
909
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -0800910static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400911{
912 int i;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400913
Stephen Hemminger6b0c1482005-06-27 11:33:04 -0700914 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
Stephen Hemminger07811912006-02-22 10:28:34 -0800915 *val = xm_read16(hw, port, XM_PHY_DATA);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400916
Stephen Hemminger64f6b642006-09-23 21:25:28 -0700917 if (hw->phy_type == SK_PHY_XMAC)
918 goto ready;
919
Stephen Hemminger89bf5f22005-06-27 11:33:10 -0700920 for (i = 0; i < PHY_RETRIES; i++) {
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -0800921 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
Stephen Hemminger89bf5f22005-06-27 11:33:10 -0700922 goto ready;
Stephen Hemminger07811912006-02-22 10:28:34 -0800923 udelay(1);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400924 }
925
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -0800926 return -ETIMEDOUT;
Stephen Hemminger89bf5f22005-06-27 11:33:10 -0700927 ready:
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -0800928 *val = xm_read16(hw, port, XM_PHY_DATA);
Stephen Hemminger89bf5f22005-06-27 11:33:10 -0700929
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -0800930 return 0;
931}
932
933static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
934{
935 u16 v = 0;
936 if (__xm_phy_read(hw, port, reg, &v))
937 printk(KERN_WARNING PFX "%s: phy read timed out\n",
938 hw->dev[port]->name);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400939 return v;
940}
941
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -0800942static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400943{
944 int i;
945
Stephen Hemminger6b0c1482005-06-27 11:33:04 -0700946 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400947 for (i = 0; i < PHY_RETRIES; i++) {
Stephen Hemminger6b0c1482005-06-27 11:33:04 -0700948 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400949 goto ready;
Stephen Hemminger89bf5f22005-06-27 11:33:10 -0700950 udelay(1);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400951 }
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -0800952 return -EIO;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400953
954 ready:
Stephen Hemminger6b0c1482005-06-27 11:33:04 -0700955 xm_write16(hw, port, XM_PHY_DATA, val);
Stephen Hemminger07811912006-02-22 10:28:34 -0800956 for (i = 0; i < PHY_RETRIES; i++) {
957 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
958 return 0;
959 udelay(1);
960 }
961 return -ETIMEDOUT;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400962}
963
964static void genesis_init(struct skge_hw *hw)
965{
966 /* set blink source counter */
967 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
968 skge_write8(hw, B2_BSC_CTRL, BSC_START);
969
970 /* configure mac arbiter */
971 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
972
973 /* configure mac arbiter timeout values */
974 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
975 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
976 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
977 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
978
979 skge_write8(hw, B3_MA_RCINI_RX1, 0);
980 skge_write8(hw, B3_MA_RCINI_RX2, 0);
981 skge_write8(hw, B3_MA_RCINI_TX1, 0);
982 skge_write8(hw, B3_MA_RCINI_TX2, 0);
983
984 /* configure packet arbiter timeout */
985 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
986 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
987 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
988 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
989 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
990}
991
992static void genesis_reset(struct skge_hw *hw, int port)
993{
Stephen Hemminger45bada62005-06-27 11:33:12 -0700994 const u8 zero[8] = { 0 };
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400995
Stephen Hemminger46a60f22005-09-09 12:54:56 -0700996 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
997
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400998 /* reset the statistics module */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -0700999 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
1000 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
1001 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1002 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1003 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001004
Stephen Hemminger89bf5f22005-06-27 11:33:10 -07001005 /* disable Broadcom PHY IRQ */
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001006 if (hw->phy_type == SK_PHY_BCOM)
1007 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001008
Stephen Hemminger45bada62005-06-27 11:33:12 -07001009 xm_outhash(hw, port, XM_HSM, zero);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001010}
1011
1012
Stephen Hemminger45bada62005-06-27 11:33:12 -07001013/* Convert mode to MII values */
1014static const u16 phy_pause_map[] = {
1015 [FLOW_MODE_NONE] = 0,
1016 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1017 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
1018 [FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
1019};
1020
Stephen Hemminger4b67be92006-10-05 15:49:51 -07001021/* special defines for FIBER (88E1011S only) */
1022static const u16 fiber_pause_map[] = {
1023 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1024 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1025 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
1026 [FLOW_MODE_REM_SEND] = PHY_X_P_BOTH_MD,
1027};
1028
Stephen Hemminger45bada62005-06-27 11:33:12 -07001029
1030/* Check status of Broadcom phy link */
1031static void bcom_check_link(struct skge_hw *hw, int port)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001032{
Stephen Hemminger45bada62005-06-27 11:33:12 -07001033 struct net_device *dev = hw->dev[port];
1034 struct skge_port *skge = netdev_priv(dev);
1035 u16 status;
1036
1037 /* read twice because of latch */
1038 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
1039 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1040
Stephen Hemminger45bada62005-06-27 11:33:12 -07001041 if ((status & PHY_ST_LSYNC) == 0) {
Stephen Hemmingera1bc9b82006-10-05 15:49:50 -07001042 xm_link_down(hw, port);
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001043 return;
1044 }
Stephen Hemminger45bada62005-06-27 11:33:12 -07001045
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001046 if (skge->autoneg == AUTONEG_ENABLE) {
1047 u16 lpa, aux;
Stephen Hemminger45bada62005-06-27 11:33:12 -07001048
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001049 if (!(status & PHY_ST_AN_OVER))
1050 return;
Stephen Hemminger45bada62005-06-27 11:33:12 -07001051
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001052 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1053 if (lpa & PHY_B_AN_RF) {
1054 printk(KERN_NOTICE PFX "%s: remote fault\n",
1055 dev->name);
1056 return;
Stephen Hemminger45bada62005-06-27 11:33:12 -07001057 }
1058
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001059 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1060
1061 /* Check Duplex mismatch */
1062 switch (aux & PHY_B_AS_AN_RES_MSK) {
1063 case PHY_B_RES_1000FD:
1064 skge->duplex = DUPLEX_FULL;
1065 break;
1066 case PHY_B_RES_1000HD:
1067 skge->duplex = DUPLEX_HALF;
1068 break;
1069 default:
1070 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1071 dev->name);
1072 return;
1073 }
1074
1075
1076 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1077 switch (aux & PHY_B_AS_PAUSE_MSK) {
1078 case PHY_B_AS_PAUSE_MSK:
1079 skge->flow_control = FLOW_MODE_SYMMETRIC;
1080 break;
1081 case PHY_B_AS_PRR:
1082 skge->flow_control = FLOW_MODE_REM_SEND;
1083 break;
1084 case PHY_B_AS_PRT:
1085 skge->flow_control = FLOW_MODE_LOC_SEND;
1086 break;
1087 default:
1088 skge->flow_control = FLOW_MODE_NONE;
1089 }
1090 skge->speed = SPEED_1000;
Stephen Hemminger45bada62005-06-27 11:33:12 -07001091 }
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001092
1093 if (!netif_carrier_ok(dev))
1094 genesis_link_up(skge);
Stephen Hemminger45bada62005-06-27 11:33:12 -07001095}
1096
1097/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1098 * Phy on for 100 or 10Mbit operation
1099 */
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001100static void bcom_phy_init(struct skge_port *skge)
Stephen Hemminger45bada62005-06-27 11:33:12 -07001101{
1102 struct skge_hw *hw = skge->hw;
1103 int port = skge->port;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001104 int i;
Stephen Hemminger45bada62005-06-27 11:33:12 -07001105 u16 id1, r, ext, ctl;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001106
1107 /* magic workaround patterns for Broadcom */
1108 static const struct {
1109 u16 reg;
1110 u16 val;
1111 } A1hack[] = {
1112 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1113 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1114 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1115 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1116 }, C0hack[] = {
1117 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1118 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1119 };
1120
Stephen Hemminger45bada62005-06-27 11:33:12 -07001121 /* read Id from external PHY (all have the same address) */
1122 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1123
1124 /* Optimize MDIO transfer by suppressing preamble. */
1125 r = xm_read16(hw, port, XM_MMU_CMD);
1126 r |= XM_MMU_NO_PRE;
1127 xm_write16(hw, port, XM_MMU_CMD,r);
1128
Stephen Hemminger2c668512005-07-22 16:26:07 -07001129 switch (id1) {
Stephen Hemminger45bada62005-06-27 11:33:12 -07001130 case PHY_BCOM_ID1_C0:
1131 /*
1132 * Workaround BCOM Errata for the C0 type.
1133 * Write magic patterns to reserved registers.
1134 */
1135 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1136 xm_phy_write(hw, port,
1137 C0hack[i].reg, C0hack[i].val);
1138
1139 break;
1140 case PHY_BCOM_ID1_A1:
1141 /*
1142 * Workaround BCOM Errata for the A1 type.
1143 * Write magic patterns to reserved registers.
1144 */
1145 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1146 xm_phy_write(hw, port,
1147 A1hack[i].reg, A1hack[i].val);
1148 break;
1149 }
1150
1151 /*
1152 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1153 * Disable Power Management after reset.
1154 */
1155 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1156 r |= PHY_B_AC_DIS_PM;
1157 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1158
1159 /* Dummy read */
1160 xm_read16(hw, port, XM_ISRC);
1161
1162 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1163 ctl = PHY_CT_SP1000; /* always 1000mbit */
1164
1165 if (skge->autoneg == AUTONEG_ENABLE) {
1166 /*
1167 * Workaround BCOM Errata #1 for the C5 type.
1168 * 1000Base-T Link Acquisition Failure in Slave Mode
1169 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1170 */
1171 u16 adv = PHY_B_1000C_RD;
1172 if (skge->advertising & ADVERTISED_1000baseT_Half)
1173 adv |= PHY_B_1000C_AHD;
1174 if (skge->advertising & ADVERTISED_1000baseT_Full)
1175 adv |= PHY_B_1000C_AFD;
1176 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1177
1178 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1179 } else {
1180 if (skge->duplex == DUPLEX_FULL)
1181 ctl |= PHY_CT_DUP_MD;
1182 /* Force to slave */
1183 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1184 }
1185
1186 /* Set autonegotiation pause parameters */
1187 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1188 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1189
1190 /* Handle Jumbo frames */
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001191 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
Stephen Hemminger45bada62005-06-27 11:33:12 -07001192 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1193 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1194
1195 ext |= PHY_B_PEC_HIGH_LA;
1196
1197 }
1198
1199 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1200 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1201
Stephen Hemminger8f3f8192005-11-08 10:33:45 -08001202 /* Use link status change interrupt */
Stephen Hemminger45bada62005-06-27 11:33:12 -07001203 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001204}
Stephen Hemminger45bada62005-06-27 11:33:12 -07001205
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001206static void xm_phy_init(struct skge_port *skge)
1207{
1208 struct skge_hw *hw = skge->hw;
1209 int port = skge->port;
1210 u16 ctrl = 0;
1211
1212 if (skge->autoneg == AUTONEG_ENABLE) {
1213 if (skge->advertising & ADVERTISED_1000baseT_Half)
1214 ctrl |= PHY_X_AN_HD;
1215 if (skge->advertising & ADVERTISED_1000baseT_Full)
1216 ctrl |= PHY_X_AN_FD;
1217
Stephen Hemminger4b67be92006-10-05 15:49:51 -07001218 ctrl |= fiber_pause_map[skge->flow_control];
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001219
1220 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1221
1222 /* Restart Auto-negotiation */
1223 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1224 } else {
1225 /* Set DuplexMode in Config register */
1226 if (skge->duplex == DUPLEX_FULL)
1227 ctrl |= PHY_CT_DUP_MD;
1228 /*
1229 * Do NOT enable Auto-negotiation here. This would hold
1230 * the link down because no IDLEs are transmitted
1231 */
1232 }
1233
1234 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1235
1236 /* Poll PHY for status changes */
1237 schedule_delayed_work(&skge->link_thread, LINK_HZ);
1238}
1239
1240static void xm_check_link(struct net_device *dev)
1241{
1242 struct skge_port *skge = netdev_priv(dev);
1243 struct skge_hw *hw = skge->hw;
1244 int port = skge->port;
1245 u16 status;
1246
1247 /* read twice because of latch */
1248 (void) xm_phy_read(hw, port, PHY_XMAC_STAT);
1249 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1250
1251 if ((status & PHY_ST_LSYNC) == 0) {
Stephen Hemmingera1bc9b82006-10-05 15:49:50 -07001252 xm_link_down(hw, port);
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001253 return;
1254 }
1255
1256 if (skge->autoneg == AUTONEG_ENABLE) {
1257 u16 lpa, res;
1258
1259 if (!(status & PHY_ST_AN_OVER))
1260 return;
1261
1262 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1263 if (lpa & PHY_B_AN_RF) {
1264 printk(KERN_NOTICE PFX "%s: remote fault\n",
1265 dev->name);
1266 return;
1267 }
1268
1269 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1270
1271 /* Check Duplex mismatch */
1272 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1273 case PHY_X_RS_FD:
1274 skge->duplex = DUPLEX_FULL;
1275 break;
1276 case PHY_X_RS_HD:
1277 skge->duplex = DUPLEX_HALF;
1278 break;
1279 default:
1280 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1281 dev->name);
1282 return;
1283 }
1284
1285 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1286 if (lpa & PHY_X_P_SYM_MD)
1287 skge->flow_control = FLOW_MODE_SYMMETRIC;
1288 else if ((lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1289 skge->flow_control = FLOW_MODE_REM_SEND;
1290 else if ((lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1291 skge->flow_control = FLOW_MODE_LOC_SEND;
1292 else
1293 skge->flow_control = FLOW_MODE_NONE;
1294
1295
1296 skge->speed = SPEED_1000;
1297 }
1298
1299 if (!netif_carrier_ok(dev))
1300 genesis_link_up(skge);
1301}
1302
1303/* Poll to check for link coming up.
1304 * Since internal PHY is wired to a level triggered pin, can't
1305 * get an interrupt when carrier is detected.
1306 */
1307static void xm_link_timer(void *arg)
1308{
1309 struct net_device *dev = arg;
1310 struct skge_port *skge = netdev_priv(arg);
1311 struct skge_hw *hw = skge->hw;
1312 int port = skge->port;
1313
1314 if (!netif_running(dev))
1315 return;
1316
1317 if (netif_carrier_ok(dev)) {
1318 xm_read16(hw, port, XM_ISRC);
1319 if (!(xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS))
1320 goto nochange;
1321 } else {
1322 if (xm_read32(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1323 goto nochange;
1324 xm_read16(hw, port, XM_ISRC);
1325 if (xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS)
1326 goto nochange;
1327 }
1328
1329 mutex_lock(&hw->phy_mutex);
1330 xm_check_link(dev);
1331 mutex_unlock(&hw->phy_mutex);
1332
1333nochange:
1334 schedule_delayed_work(&skge->link_thread, LINK_HZ);
Stephen Hemminger45bada62005-06-27 11:33:12 -07001335}
1336
1337static void genesis_mac_init(struct skge_hw *hw, int port)
1338{
1339 struct net_device *dev = hw->dev[port];
1340 struct skge_port *skge = netdev_priv(dev);
1341 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1342 int i;
1343 u32 r;
1344 const u8 zero[6] = { 0 };
1345
Stephen Hemminger07811912006-02-22 10:28:34 -08001346 for (i = 0; i < 10; i++) {
1347 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1348 MFF_SET_MAC_RST);
1349 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1350 goto reset_ok;
1351 udelay(1);
1352 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001353
Stephen Hemminger07811912006-02-22 10:28:34 -08001354 printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);
1355
1356 reset_ok:
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001357 /* Unreset the XMAC. */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001358 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001359
1360 /*
1361 * Perform additional initialization for external PHYs,
1362 * namely for the 1000baseTX cards that use the XMAC's
1363 * GMII mode.
1364 */
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001365 if (hw->phy_type != SK_PHY_XMAC) {
1366 /* Take external Phy out of reset */
1367 r = skge_read32(hw, B2_GP_IO);
1368 if (port == 0)
1369 r |= GP_DIR_0|GP_IO_0;
1370 else
1371 r |= GP_DIR_2|GP_IO_2;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001372
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001373 skge_write32(hw, B2_GP_IO, r);
1374
1375 /* Enable GMII interface */
1376 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1377 }
Stephen Hemminger07811912006-02-22 10:28:34 -08001378
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001379
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001380 switch(hw->phy_type) {
1381 case SK_PHY_XMAC:
1382 xm_phy_init(skge);
1383 break;
1384 case SK_PHY_BCOM:
1385 bcom_phy_init(skge);
1386 bcom_check_link(hw, port);
1387 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001388
Stephen Hemminger45bada62005-06-27 11:33:12 -07001389 /* Set Station Address */
1390 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001391
Stephen Hemminger45bada62005-06-27 11:33:12 -07001392 /* We don't use match addresses so clear */
1393 for (i = 1; i < 16; i++)
1394 xm_outaddr(hw, port, XM_EXM(i), zero);
Stephen Hemminger89bf5f22005-06-27 11:33:10 -07001395
Stephen Hemminger07811912006-02-22 10:28:34 -08001396 /* Clear MIB counters */
1397 xm_write16(hw, port, XM_STAT_CMD,
1398 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1399 /* Clear two times according to Errata #3 */
1400 xm_write16(hw, port, XM_STAT_CMD,
1401 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1402
Stephen Hemminger45bada62005-06-27 11:33:12 -07001403 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1404 xm_write16(hw, port, XM_RX_HI_WM, 1450);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001405
1406 /* We don't need the FCS appended to the packet. */
Stephen Hemminger45bada62005-06-27 11:33:12 -07001407 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1408 if (jumbo)
1409 r |= XM_RX_BIG_PK_OK;
1410
1411 if (skge->duplex == DUPLEX_HALF) {
1412 /*
1413 * If in manual half duplex mode the other side might be in
1414 * full duplex mode, so ignore if a carrier extension is not seen
1415 * on frames received
1416 */
1417 r |= XM_RX_DIS_CEXT;
1418 }
1419 xm_write16(hw, port, XM_RX_CMD, r);
1420
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001421
1422 /* We want short frames padded to 60 bytes. */
Stephen Hemminger45bada62005-06-27 11:33:12 -07001423 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1424
1425 /*
1426 * Bump up the transmit threshold. This helps hold off transmit
1427 * underruns when we're blasting traffic from both ports at once.
1428 */
1429 xm_write16(hw, port, XM_TX_THR, 512);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001430
1431 /*
1432 * Enable the reception of all error frames. This is is
1433 * a necessary evil due to the design of the XMAC. The
1434 * XMAC's receive FIFO is only 8K in size, however jumbo
1435 * frames can be up to 9000 bytes in length. When bad
1436 * frame filtering is enabled, the XMAC's RX FIFO operates
1437 * in 'store and forward' mode. For this to work, the
1438 * entire frame has to fit into the FIFO, but that means
1439 * that jumbo frames larger than 8192 bytes will be
1440 * truncated. Disabling all bad frame filtering causes
1441 * the RX FIFO to operate in streaming mode, in which
Stephen Hemminger8f3f8192005-11-08 10:33:45 -08001442 * case the XMAC will start transferring frames out of the
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001443 * RX FIFO as soon as the FIFO threshold is reached.
1444 */
Stephen Hemminger45bada62005-06-27 11:33:12 -07001445 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001446
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001447
1448 /*
Stephen Hemminger45bada62005-06-27 11:33:12 -07001449 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1450 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1451 * and 'Octets Rx OK Hi Cnt Ov'.
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001452 */
Stephen Hemminger45bada62005-06-27 11:33:12 -07001453 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1454
1455 /*
1456 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1457 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1458 * and 'Octets Tx OK Hi Cnt Ov'.
1459 */
1460 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001461
1462 /* Configure MAC arbiter */
1463 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1464
1465 /* configure timeout values */
1466 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1467 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1468 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1469 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1470
1471 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1472 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1473 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1474 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1475
1476 /* Configure Rx MAC FIFO */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001477 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1478 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1479 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001480
1481 /* Configure Tx MAC FIFO */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001482 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1483 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1484 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001485
Stephen Hemminger45bada62005-06-27 11:33:12 -07001486 if (jumbo) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001487 /* Enable frame flushing if jumbo frames used */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001488 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001489 } else {
1490 /* enable timeout timers if normal frames */
1491 skge_write16(hw, B3_PA_CTRL,
Stephen Hemminger45bada62005-06-27 11:33:12 -07001492 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001493 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001494}
1495
1496static void genesis_stop(struct skge_port *skge)
1497{
1498 struct skge_hw *hw = skge->hw;
1499 int port = skge->port;
Stephen Hemminger89bf5f22005-06-27 11:33:10 -07001500 u32 reg;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001501
Stephen Hemminger46a60f22005-09-09 12:54:56 -07001502 genesis_reset(hw, port);
1503
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001504 /* Clear Tx packet arbiter timeout IRQ */
1505 skge_write16(hw, B3_PA_CTRL,
1506 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1507
1508 /*
Stephen Hemminger8f3f8192005-11-08 10:33:45 -08001509 * If the transfer sticks at the MAC the STOP command will not
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001510 * terminate if we don't flush the XMAC's transmit FIFO !
1511 */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001512 xm_write32(hw, port, XM_MODE,
1513 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001514
1515
1516 /* Reset the MAC */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001517 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001518
1519 /* For external PHYs there must be special handling */
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001520 if (hw->phy_type != SK_PHY_XMAC) {
1521 reg = skge_read32(hw, B2_GP_IO);
1522 if (port == 0) {
1523 reg |= GP_DIR_0;
1524 reg &= ~GP_IO_0;
1525 } else {
1526 reg |= GP_DIR_2;
1527 reg &= ~GP_IO_2;
1528 }
1529 skge_write32(hw, B2_GP_IO, reg);
1530 skge_read32(hw, B2_GP_IO);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001531 }
1532
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001533 xm_write16(hw, port, XM_MMU_CMD,
1534 xm_read16(hw, port, XM_MMU_CMD)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001535 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1536
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001537 xm_read16(hw, port, XM_MMU_CMD);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001538}
1539
1540
1541static void genesis_get_stats(struct skge_port *skge, u64 *data)
1542{
1543 struct skge_hw *hw = skge->hw;
1544 int port = skge->port;
1545 int i;
1546 unsigned long timeout = jiffies + HZ;
1547
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001548 xm_write16(hw, port,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001549 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1550
1551 /* wait for update to complete */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001552 while (xm_read16(hw, port, XM_STAT_CMD)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001553 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1554 if (time_after(jiffies, timeout))
1555 break;
1556 udelay(10);
1557 }
1558
1559 /* special case for 64 bit octet counter */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001560 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1561 | xm_read32(hw, port, XM_TXO_OK_LO);
1562 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1563 | xm_read32(hw, port, XM_RXO_OK_LO);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001564
1565 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001566 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001567}
1568
1569static void genesis_mac_intr(struct skge_hw *hw, int port)
1570{
1571 struct skge_port *skge = netdev_priv(hw->dev[port]);
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001572 u16 status = xm_read16(hw, port, XM_ISRC);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001573
Stephen Hemminger7e676d92005-06-27 11:33:13 -07001574 if (netif_msg_intr(skge))
1575 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1576 skge->netdev->name, status);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001577
Stephen Hemmingera1bc9b82006-10-05 15:49:50 -07001578 if (hw->phy_type == SK_PHY_XMAC &&
1579 (status & (XM_IS_INP_ASS | XM_IS_LIPA_RC)))
1580 xm_link_down(hw, port);
1581
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001582 if (status & XM_IS_TXF_UR) {
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001583 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001584 ++skge->net_stats.tx_fifo_errors;
1585 }
1586 if (status & XM_IS_RXF_OV) {
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001587 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001588 ++skge->net_stats.rx_fifo_errors;
1589 }
1590}
1591
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001592static void genesis_link_up(struct skge_port *skge)
1593{
1594 struct skge_hw *hw = skge->hw;
1595 int port = skge->port;
Stephen Hemmingera1bc9b82006-10-05 15:49:50 -07001596 u16 cmd, msk;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001597 u32 mode;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001598
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001599 cmd = xm_read16(hw, port, XM_MMU_CMD);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001600
1601 /*
1602 * enabling pause frame reception is required for 1000BT
1603 * because the XMAC is not reset if the link is going down
1604 */
1605 if (skge->flow_control == FLOW_MODE_NONE ||
1606 skge->flow_control == FLOW_MODE_LOC_SEND)
Stephen Hemminger7e676d92005-06-27 11:33:13 -07001607 /* Disable Pause Frame Reception */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001608 cmd |= XM_MMU_IGN_PF;
1609 else
1610 /* Enable Pause Frame Reception */
1611 cmd &= ~XM_MMU_IGN_PF;
1612
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001613 xm_write16(hw, port, XM_MMU_CMD, cmd);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001614
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001615 mode = xm_read32(hw, port, XM_MODE);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001616 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1617 skge->flow_control == FLOW_MODE_LOC_SEND) {
1618 /*
1619 * Configure Pause Frame Generation
1620 * Use internal and external Pause Frame Generation.
1621 * Sending pause frames is edge triggered.
1622 * Send a Pause frame with the maximum pause time if
1623 * internal oder external FIFO full condition occurs.
1624 * Send a zero pause time frame to re-start transmission.
1625 */
1626 /* XM_PAUSE_DA = '010000C28001' (default) */
1627 /* XM_MAC_PTIME = 0xffff (maximum) */
1628 /* remember this value is defined in big endian (!) */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001629 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001630
1631 mode |= XM_PAUSE_MODE;
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001632 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001633 } else {
1634 /*
1635 * disable pause frame generation is required for 1000BT
1636 * because the XMAC is not reset if the link is going down
1637 */
1638 /* Disable Pause Mode in Mode Register */
1639 mode &= ~XM_PAUSE_MODE;
1640
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001641 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001642 }
1643
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001644 xm_write32(hw, port, XM_MODE, mode);
Stephen Hemmingera1bc9b82006-10-05 15:49:50 -07001645 msk = XM_DEF_MSK;
1646 if (hw->phy_type != SK_PHY_XMAC)
1647 msk |= XM_IS_INP_ASS; /* disable GP0 interrupt bit */
1648
1649 xm_write16(hw, port, XM_IMSK, msk);
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001650 xm_read16(hw, port, XM_ISRC);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001651
1652 /* get MMU Command Reg. */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001653 cmd = xm_read16(hw, port, XM_MMU_CMD);
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001654 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001655 cmd |= XM_MMU_GMII_FD;
1656
Stephen Hemminger89bf5f22005-06-27 11:33:10 -07001657 /*
1658 * Workaround BCOM Errata (#10523) for all BCom Phys
1659 * Enable Power Management after link up
1660 */
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001661 if (hw->phy_type == SK_PHY_BCOM) {
1662 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1663 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1664 & ~PHY_B_AC_DIS_PM);
1665 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1666 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001667
1668 /* enable Rx/Tx */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001669 xm_write16(hw, port, XM_MMU_CMD,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001670 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1671 skge_link_up(skge);
1672}
1673
1674
Stephen Hemminger45bada62005-06-27 11:33:12 -07001675static inline void bcom_phy_intr(struct skge_port *skge)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001676{
1677 struct skge_hw *hw = skge->hw;
1678 int port = skge->port;
Stephen Hemminger45bada62005-06-27 11:33:12 -07001679 u16 isrc;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001680
Stephen Hemminger45bada62005-06-27 11:33:12 -07001681 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
Stephen Hemminger7e676d92005-06-27 11:33:13 -07001682 if (netif_msg_intr(skge))
1683 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1684 skge->netdev->name, isrc);
Stephen Hemminger45bada62005-06-27 11:33:12 -07001685
1686 if (isrc & PHY_B_IS_PSE)
1687 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1688 hw->dev[port]->name);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001689
1690 /* Workaround BCom Errata:
1691 * enable and disable loopback mode if "NO HCD" occurs.
1692 */
Stephen Hemminger45bada62005-06-27 11:33:12 -07001693 if (isrc & PHY_B_IS_NO_HDCL) {
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001694 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1695 xm_phy_write(hw, port, PHY_BCOM_CTRL,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001696 ctrl | PHY_CT_LOOP);
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001697 xm_phy_write(hw, port, PHY_BCOM_CTRL,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001698 ctrl & ~PHY_CT_LOOP);
1699 }
1700
Stephen Hemminger45bada62005-06-27 11:33:12 -07001701 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1702 bcom_check_link(hw, port);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001703
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001704}
1705
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08001706static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1707{
1708 int i;
1709
1710 gma_write16(hw, port, GM_SMI_DATA, val);
1711 gma_write16(hw, port, GM_SMI_CTRL,
1712 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1713 for (i = 0; i < PHY_RETRIES; i++) {
1714 udelay(1);
1715
1716 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1717 return 0;
1718 }
1719
1720 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1721 hw->dev[port]->name);
1722 return -EIO;
1723}
1724
1725static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1726{
1727 int i;
1728
1729 gma_write16(hw, port, GM_SMI_CTRL,
1730 GM_SMI_CT_PHY_AD(hw->phy_addr)
1731 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1732
1733 for (i = 0; i < PHY_RETRIES; i++) {
1734 udelay(1);
1735 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1736 goto ready;
1737 }
1738
1739 return -ETIMEDOUT;
1740 ready:
1741 *val = gma_read16(hw, port, GM_SMI_DATA);
1742 return 0;
1743}
1744
1745static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1746{
1747 u16 v = 0;
1748 if (__gm_phy_read(hw, port, reg, &v))
1749 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1750 hw->dev[port]->name);
1751 return v;
1752}
1753
Stephen Hemminger8f3f8192005-11-08 10:33:45 -08001754/* Marvell Phy Initialization */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001755static void yukon_init(struct skge_hw *hw, int port)
1756{
1757 struct skge_port *skge = netdev_priv(hw->dev[port]);
1758 u16 ctrl, ct1000, adv;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001759
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001760 if (skge->autoneg == AUTONEG_ENABLE) {
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001761 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001762
1763 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1764 PHY_M_EC_MAC_S_MSK);
1765 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1766
Stephen Hemmingerc506a502005-06-27 11:33:09 -07001767 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001768
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001769 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001770 }
1771
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001772 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001773 if (skge->autoneg == AUTONEG_DISABLE)
1774 ctrl &= ~PHY_CT_ANE;
1775
1776 ctrl |= PHY_CT_RESET;
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001777 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001778
1779 ctrl = 0;
1780 ct1000 = 0;
Stephen Hemmingerb18f2092005-06-27 11:33:08 -07001781 adv = PHY_AN_CSMA;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001782
1783 if (skge->autoneg == AUTONEG_ENABLE) {
Stephen Hemminger5e1705d2005-08-16 14:00:58 -07001784 if (hw->copper) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001785 if (skge->advertising & ADVERTISED_1000baseT_Full)
1786 ct1000 |= PHY_M_1000C_AFD;
1787 if (skge->advertising & ADVERTISED_1000baseT_Half)
1788 ct1000 |= PHY_M_1000C_AHD;
1789 if (skge->advertising & ADVERTISED_100baseT_Full)
1790 adv |= PHY_M_AN_100_FD;
1791 if (skge->advertising & ADVERTISED_100baseT_Half)
1792 adv |= PHY_M_AN_100_HD;
1793 if (skge->advertising & ADVERTISED_10baseT_Full)
1794 adv |= PHY_M_AN_10_FD;
1795 if (skge->advertising & ADVERTISED_10baseT_Half)
1796 adv |= PHY_M_AN_10_HD;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001797
Stephen Hemminger4b67be92006-10-05 15:49:51 -07001798 /* Set Flow-control capabilities */
1799 adv |= phy_pause_map[skge->flow_control];
1800 } else {
1801 if (skge->advertising & ADVERTISED_1000baseT_Full)
1802 adv |= PHY_M_AN_1000X_AFD;
1803 if (skge->advertising & ADVERTISED_1000baseT_Half)
1804 adv |= PHY_M_AN_1000X_AHD;
1805
1806 adv |= fiber_pause_map[skge->flow_control];
1807 }
Stephen Hemminger45bada62005-06-27 11:33:12 -07001808
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001809 /* Restart Auto-negotiation */
1810 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1811 } else {
1812 /* forced speed/duplex settings */
1813 ct1000 = PHY_M_1000C_MSE;
1814
1815 if (skge->duplex == DUPLEX_FULL)
1816 ctrl |= PHY_CT_DUP_MD;
1817
1818 switch (skge->speed) {
1819 case SPEED_1000:
1820 ctrl |= PHY_CT_SP1000;
1821 break;
1822 case SPEED_100:
1823 ctrl |= PHY_CT_SP100;
1824 break;
1825 }
1826
1827 ctrl |= PHY_CT_RESET;
1828 }
1829
Stephen Hemmingerc506a502005-06-27 11:33:09 -07001830 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001831
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001832 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1833 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001834
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001835 /* Enable phy interrupt on autonegotiation complete (or link up) */
1836 if (skge->autoneg == AUTONEG_ENABLE)
Stephen Hemminger4cde06e2005-07-22 16:26:09 -07001837 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001838 else
Stephen Hemminger4cde06e2005-07-22 16:26:09 -07001839 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001840}
1841
1842static void yukon_reset(struct skge_hw *hw, int port)
1843{
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001844 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1845 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1846 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1847 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1848 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001849
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001850 gma_write16(hw, port, GM_RX_CTRL,
1851 gma_read16(hw, port, GM_RX_CTRL)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001852 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1853}
1854
Stephen Hemmingerc8868612005-09-23 09:08:30 -07001855/* Apparently, early versions of Yukon-Lite had wrong chip_id? */
1856static int is_yukon_lite_a0(struct skge_hw *hw)
1857{
1858 u32 reg;
1859 int ret;
1860
1861 if (hw->chip_id != CHIP_ID_YUKON)
1862 return 0;
1863
1864 reg = skge_read32(hw, B2_FAR);
1865 skge_write8(hw, B2_FAR + 3, 0xff);
1866 ret = (skge_read8(hw, B2_FAR + 3) != 0);
1867 skge_write32(hw, B2_FAR, reg);
1868 return ret;
1869}
1870
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001871static void yukon_mac_init(struct skge_hw *hw, int port)
1872{
1873 struct skge_port *skge = netdev_priv(hw->dev[port]);
1874 int i;
1875 u32 reg;
1876 const u8 *addr = hw->dev[port]->dev_addr;
1877
1878 /* WA code for COMA mode -- set PHY reset */
1879 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
Stephen Hemminger46a60f22005-09-09 12:54:56 -07001880 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1881 reg = skge_read32(hw, B2_GP_IO);
1882 reg |= GP_DIR_9 | GP_IO_9;
1883 skge_write32(hw, B2_GP_IO, reg);
1884 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001885
1886 /* hard reset */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001887 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1888 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001889
1890 /* WA code for COMA mode -- clear PHY reset */
1891 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
Stephen Hemminger46a60f22005-09-09 12:54:56 -07001892 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1893 reg = skge_read32(hw, B2_GP_IO);
1894 reg |= GP_DIR_9;
1895 reg &= ~GP_IO_9;
1896 skge_write32(hw, B2_GP_IO, reg);
1897 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001898
1899 /* Set hardware config mode */
1900 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1901 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
Stephen Hemminger5e1705d2005-08-16 14:00:58 -07001902 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001903
1904 /* Clear GMC reset */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001905 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1906 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1907 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
Stephen Hemminger564f9ab2006-02-13 15:46:48 -08001908
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001909 if (skge->autoneg == AUTONEG_DISABLE) {
1910 reg = GM_GPCR_AU_ALL_DIS;
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001911 gma_write16(hw, port, GM_GP_CTRL,
1912 gma_read16(hw, port, GM_GP_CTRL) | reg);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001913
1914 switch (skge->speed) {
1915 case SPEED_1000:
Stephen Hemminger564f9ab2006-02-13 15:46:48 -08001916 reg &= ~GM_GPCR_SPEED_100;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001917 reg |= GM_GPCR_SPEED_1000;
Stephen Hemminger564f9ab2006-02-13 15:46:48 -08001918 break;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001919 case SPEED_100:
Stephen Hemminger564f9ab2006-02-13 15:46:48 -08001920 reg &= ~GM_GPCR_SPEED_1000;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001921 reg |= GM_GPCR_SPEED_100;
Stephen Hemminger564f9ab2006-02-13 15:46:48 -08001922 break;
1923 case SPEED_10:
1924 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1925 break;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001926 }
1927
1928 if (skge->duplex == DUPLEX_FULL)
1929 reg |= GM_GPCR_DUP_FULL;
1930 } else
1931 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
Stephen Hemminger564f9ab2006-02-13 15:46:48 -08001932
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001933 switch (skge->flow_control) {
1934 case FLOW_MODE_NONE:
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001935 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001936 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1937 break;
1938 case FLOW_MODE_LOC_SEND:
1939 /* disable Rx flow-control */
1940 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1941 }
1942
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001943 gma_write16(hw, port, GM_GP_CTRL, reg);
Stephen Hemminger46a60f22005-09-09 12:54:56 -07001944 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001945
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001946 yukon_init(hw, port);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001947
1948 /* MIB clear */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001949 reg = gma_read16(hw, port, GM_PHY_ADDR);
1950 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001951
1952 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001953 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1954 gma_write16(hw, port, GM_PHY_ADDR, reg);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001955
1956 /* transmit control */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001957 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001958
1959 /* receive control reg: unicast + multicast + no FCS */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001960 gma_write16(hw, port, GM_RX_CTRL,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001961 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1962
1963 /* transmit flow control */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001964 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001965
1966 /* transmit parameter */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001967 gma_write16(hw, port, GM_TX_PARAM,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001968 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1969 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1970 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1971
1972 /* serial mode register */
1973 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1974 if (hw->dev[port]->mtu > 1500)
1975 reg |= GM_SMOD_JUMBO_ENA;
1976
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001977 gma_write16(hw, port, GM_SERIAL_MODE, reg);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001978
1979 /* physical address: used for pause frames */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001980 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001981 /* virtual address for data */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001982 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001983
1984 /* enable interrupt mask for counter overflows */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001985 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1986 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1987 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001988
1989 /* Initialize Mac Fifo */
1990
1991 /* Configure Rx MAC FIFO */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001992 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001993 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
Stephen Hemmingerc8868612005-09-23 09:08:30 -07001994
1995 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
1996 if (is_yukon_lite_a0(hw))
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001997 reg &= ~GMF_RX_F_FL_ON;
Stephen Hemmingerc8868612005-09-23 09:08:30 -07001998
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001999 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2000 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
Stephen Hemmingerc5923082005-08-16 14:01:02 -07002001 /*
2002 * because Pause Packet Truncation in GMAC is not working
2003 * we have to increase the Flush Threshold to 64 bytes
2004 * in order to flush pause packets in Rx FIFO on Yukon-1
2005 */
2006 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002007
2008 /* Configure Tx MAC FIFO */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002009 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2010 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002011}
2012
Stephen Hemminger355ec572005-11-08 10:33:43 -08002013/* Go into power down mode */
2014static void yukon_suspend(struct skge_hw *hw, int port)
2015{
2016 u16 ctrl;
2017
2018 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2019 ctrl |= PHY_M_PC_POL_R_DIS;
2020 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2021
2022 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2023 ctrl |= PHY_CT_RESET;
2024 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2025
2026 /* switch IEEE compatible power down mode on */
2027 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2028 ctrl |= PHY_CT_PDOWN;
2029 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2030}
2031
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002032static void yukon_stop(struct skge_port *skge)
2033{
2034 struct skge_hw *hw = skge->hw;
2035 int port = skge->port;
2036
Stephen Hemminger46a60f22005-09-09 12:54:56 -07002037 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2038 yukon_reset(hw, port);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002039
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002040 gma_write16(hw, port, GM_GP_CTRL,
2041 gma_read16(hw, port, GM_GP_CTRL)
Stephen Hemminger0eedf4a2005-07-22 16:26:04 -07002042 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002043 gma_read16(hw, port, GM_GP_CTRL);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002044
Stephen Hemminger355ec572005-11-08 10:33:43 -08002045 yukon_suspend(hw, port);
Stephen Hemminger46a60f22005-09-09 12:54:56 -07002046
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002047 /* set GPHY Control reset */
Stephen Hemminger46a60f22005-09-09 12:54:56 -07002048 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2049 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002050}
2051
2052static void yukon_get_stats(struct skge_port *skge, u64 *data)
2053{
2054 struct skge_hw *hw = skge->hw;
2055 int port = skge->port;
2056 int i;
2057
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002058 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2059 | gma_read32(hw, port, GM_TXO_OK_LO);
2060 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2061 | gma_read32(hw, port, GM_RXO_OK_LO);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002062
2063 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002064 data[i] = gma_read32(hw, port,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002065 skge_stats[i].gma_offset);
2066}
2067
2068static void yukon_mac_intr(struct skge_hw *hw, int port)
2069{
Stephen Hemminger7e676d92005-06-27 11:33:13 -07002070 struct net_device *dev = hw->dev[port];
2071 struct skge_port *skge = netdev_priv(dev);
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002072 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002073
Stephen Hemminger7e676d92005-06-27 11:33:13 -07002074 if (netif_msg_intr(skge))
2075 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
2076 dev->name, status);
2077
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002078 if (status & GM_IS_RX_FF_OR) {
2079 ++skge->net_stats.rx_fifo_errors;
Stephen Hemmingerd8a09942005-07-22 16:26:08 -07002080 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002081 }
Stephen Hemmingerd8a09942005-07-22 16:26:08 -07002082
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002083 if (status & GM_IS_TX_FF_UR) {
2084 ++skge->net_stats.tx_fifo_errors;
Stephen Hemmingerd8a09942005-07-22 16:26:08 -07002085 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002086 }
2087
2088}
2089
2090static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2091{
Stephen Hemminger95566062005-06-27 11:33:02 -07002092 switch (aux & PHY_M_PS_SPEED_MSK) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002093 case PHY_M_PS_SPEED_1000:
2094 return SPEED_1000;
2095 case PHY_M_PS_SPEED_100:
2096 return SPEED_100;
2097 default:
2098 return SPEED_10;
2099 }
2100}
2101
2102static void yukon_link_up(struct skge_port *skge)
2103{
2104 struct skge_hw *hw = skge->hw;
2105 int port = skge->port;
2106 u16 reg;
2107
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002108 /* Enable Transmit FIFO Underrun */
Stephen Hemminger46a60f22005-09-09 12:54:56 -07002109 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002110
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002111 reg = gma_read16(hw, port, GM_GP_CTRL);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002112 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2113 reg |= GM_GPCR_DUP_FULL;
2114
2115 /* enable Rx/Tx */
2116 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002117 gma_write16(hw, port, GM_GP_CTRL, reg);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002118
Stephen Hemminger4cde06e2005-07-22 16:26:09 -07002119 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002120 skge_link_up(skge);
2121}
2122
2123static void yukon_link_down(struct skge_port *skge)
2124{
2125 struct skge_hw *hw = skge->hw;
2126 int port = skge->port;
Stephen Hemmingerd8a09942005-07-22 16:26:08 -07002127 u16 ctrl;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002128
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002129 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
Stephen Hemmingerd8a09942005-07-22 16:26:08 -07002130
2131 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2132 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2133 gma_write16(hw, port, GM_GP_CTRL, ctrl);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002134
Stephen Hemmingerc506a502005-06-27 11:33:09 -07002135 if (skge->flow_control == FLOW_MODE_REM_SEND) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002136 /* restore Asymmetric Pause bit */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002137 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
2138 gm_phy_read(hw, port,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002139 PHY_MARV_AUNE_ADV)
2140 | PHY_M_AN_ASP);
2141
2142 }
2143
2144 yukon_reset(hw, port);
2145 skge_link_down(skge);
2146
2147 yukon_init(hw, port);
2148}
2149
2150static void yukon_phy_intr(struct skge_port *skge)
2151{
2152 struct skge_hw *hw = skge->hw;
2153 int port = skge->port;
2154 const char *reason = NULL;
2155 u16 istatus, phystat;
2156
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002157 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2158 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
Stephen Hemminger7e676d92005-06-27 11:33:13 -07002159
2160 if (netif_msg_intr(skge))
2161 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
2162 skge->netdev->name, istatus, phystat);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002163
2164 if (istatus & PHY_M_IS_AN_COMPL) {
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002165 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002166 & PHY_M_AN_RF) {
2167 reason = "remote fault";
2168 goto failed;
2169 }
2170
Stephen Hemmingerc506a502005-06-27 11:33:09 -07002171 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002172 reason = "master/slave fault";
2173 goto failed;
2174 }
2175
2176 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2177 reason = "speed/duplex";
2178 goto failed;
2179 }
2180
2181 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2182 ? DUPLEX_FULL : DUPLEX_HALF;
2183 skge->speed = yukon_speed(hw, phystat);
2184
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002185 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2186 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2187 case PHY_M_PS_PAUSE_MSK:
2188 skge->flow_control = FLOW_MODE_SYMMETRIC;
2189 break;
2190 case PHY_M_PS_RX_P_EN:
2191 skge->flow_control = FLOW_MODE_REM_SEND;
2192 break;
2193 case PHY_M_PS_TX_P_EN:
2194 skge->flow_control = FLOW_MODE_LOC_SEND;
2195 break;
2196 default:
2197 skge->flow_control = FLOW_MODE_NONE;
2198 }
2199
2200 if (skge->flow_control == FLOW_MODE_NONE ||
2201 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002202 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002203 else
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002204 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002205 yukon_link_up(skge);
2206 return;
2207 }
2208
2209 if (istatus & PHY_M_IS_LSP_CHANGE)
2210 skge->speed = yukon_speed(hw, phystat);
2211
2212 if (istatus & PHY_M_IS_DUP_CHANGE)
2213 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2214 if (istatus & PHY_M_IS_LST_CHANGE) {
2215 if (phystat & PHY_M_PS_LINK_UP)
2216 yukon_link_up(skge);
2217 else
2218 yukon_link_down(skge);
2219 }
2220 return;
2221 failed:
2222 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2223 skge->netdev->name, reason);
2224
2225 /* XXX restart autonegotiation? */
2226}
2227
Stephen Hemmingeree294dc2005-12-14 15:47:44 -08002228static void skge_phy_reset(struct skge_port *skge)
2229{
2230 struct skge_hw *hw = skge->hw;
2231 int port = skge->port;
2232
2233 netif_stop_queue(skge->netdev);
2234 netif_carrier_off(skge->netdev);
2235
Stephen Hemmingerd85b5142006-06-06 10:11:11 -07002236 mutex_lock(&hw->phy_mutex);
Stephen Hemmingeree294dc2005-12-14 15:47:44 -08002237 if (hw->chip_id == CHIP_ID_GENESIS) {
2238 genesis_reset(hw, port);
2239 genesis_mac_init(hw, port);
2240 } else {
2241 yukon_reset(hw, port);
2242 yukon_init(hw, port);
2243 }
Stephen Hemmingerd85b5142006-06-06 10:11:11 -07002244 mutex_unlock(&hw->phy_mutex);
Stephen Hemmingeree294dc2005-12-14 15:47:44 -08002245}
2246
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08002247/* Basic MII support */
2248static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2249{
2250 struct mii_ioctl_data *data = if_mii(ifr);
2251 struct skge_port *skge = netdev_priv(dev);
2252 struct skge_hw *hw = skge->hw;
2253 int err = -EOPNOTSUPP;
2254
2255 if (!netif_running(dev))
2256 return -ENODEV; /* Phy still in reset */
2257
2258 switch(cmd) {
2259 case SIOCGMIIPHY:
2260 data->phy_id = hw->phy_addr;
2261
2262 /* fallthru */
2263 case SIOCGMIIREG: {
2264 u16 val = 0;
Stephen Hemmingerd85b5142006-06-06 10:11:11 -07002265 mutex_lock(&hw->phy_mutex);
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08002266 if (hw->chip_id == CHIP_ID_GENESIS)
2267 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2268 else
2269 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
Stephen Hemmingerd85b5142006-06-06 10:11:11 -07002270 mutex_unlock(&hw->phy_mutex);
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08002271 data->val_out = val;
2272 break;
2273 }
2274
2275 case SIOCSMIIREG:
2276 if (!capable(CAP_NET_ADMIN))
2277 return -EPERM;
2278
Stephen Hemmingerd85b5142006-06-06 10:11:11 -07002279 mutex_lock(&hw->phy_mutex);
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08002280 if (hw->chip_id == CHIP_ID_GENESIS)
2281 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2282 data->val_in);
2283 else
2284 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2285 data->val_in);
Stephen Hemmingerd85b5142006-06-06 10:11:11 -07002286 mutex_unlock(&hw->phy_mutex);
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08002287 break;
2288 }
2289 return err;
2290}
2291
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002292static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2293{
2294 u32 end;
2295
2296 start /= 8;
2297 len /= 8;
2298 end = start + len - 1;
2299
2300 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2301 skge_write32(hw, RB_ADDR(q, RB_START), start);
2302 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2303 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2304 skge_write32(hw, RB_ADDR(q, RB_END), end);
2305
2306 if (q == Q_R1 || q == Q_R2) {
2307 /* Set thresholds on receive queue's */
2308 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2309 start + (2*len)/3);
2310 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2311 start + (len/3));
2312 } else {
2313 /* Enable store & forward on Tx queue's because
2314 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2315 */
2316 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2317 }
2318
2319 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2320}
2321
2322/* Setup Bus Memory Interface */
2323static void skge_qset(struct skge_port *skge, u16 q,
2324 const struct skge_element *e)
2325{
2326 struct skge_hw *hw = skge->hw;
2327 u32 watermark = 0x600;
2328 u64 base = skge->dma + (e->desc - skge->mem);
2329
2330 /* optimization to reduce window on 32bit/33mhz */
2331 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2332 watermark /= 2;
2333
2334 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2335 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2336 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2337 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2338}
2339
2340static int skge_up(struct net_device *dev)
2341{
2342 struct skge_port *skge = netdev_priv(dev);
2343 struct skge_hw *hw = skge->hw;
2344 int port = skge->port;
2345 u32 chunk, ram_addr;
2346 size_t rx_size, tx_size;
2347 int err;
2348
2349 if (netif_msg_ifup(skge))
2350 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2351
Stephen Hemminger19a33d42005-06-27 11:33:15 -07002352 if (dev->mtu > RX_BUF_SIZE)
Stephen Hemminger901ccef2006-03-23 11:07:23 -08002353 skge->rx_buf_size = dev->mtu + ETH_HLEN;
Stephen Hemminger19a33d42005-06-27 11:33:15 -07002354 else
2355 skge->rx_buf_size = RX_BUF_SIZE;
2356
2357
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002358 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2359 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2360 skge->mem_size = tx_size + rx_size;
2361 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2362 if (!skge->mem)
2363 return -ENOMEM;
2364
Stephen Hemmingerc3da1442006-03-21 10:57:01 -08002365 BUG_ON(skge->dma & 7);
2366
2367 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
2368 printk(KERN_ERR PFX "pci_alloc_consistent region crosses 4G boundary\n");
2369 err = -EINVAL;
2370 goto free_pci_mem;
2371 }
2372
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002373 memset(skge->mem, 0, skge->mem_size);
2374
Stephen Hemminger203babb2006-03-21 10:57:05 -08002375 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2376 if (err)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002377 goto free_pci_mem;
2378
Stephen Hemmingerc54f9762006-09-01 15:53:47 -07002379 err = skge_rx_fill(dev);
Stephen Hemminger19a33d42005-06-27 11:33:15 -07002380 if (err)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002381 goto free_rx_ring;
2382
Stephen Hemminger203babb2006-03-21 10:57:05 -08002383 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2384 skge->dma + rx_size);
2385 if (err)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002386 goto free_rx_ring;
2387
Stephen Hemminger8f3f8192005-11-08 10:33:45 -08002388 /* Initialize MAC */
Stephen Hemmingerd85b5142006-06-06 10:11:11 -07002389 mutex_lock(&hw->phy_mutex);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002390 if (hw->chip_id == CHIP_ID_GENESIS)
2391 genesis_mac_init(hw, port);
2392 else
2393 yukon_mac_init(hw, port);
Stephen Hemmingerd85b5142006-06-06 10:11:11 -07002394 mutex_unlock(&hw->phy_mutex);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002395
2396 /* Configure RAMbuffers */
Stephen Hemminger981d0372005-06-27 11:33:06 -07002397 chunk = hw->ram_size / ((hw->ports + 1)*2);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002398 ram_addr = hw->ram_offset + 2 * chunk * port;
2399
2400 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2401 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2402
2403 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2404 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2405 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2406
2407 /* Start receiver BMU */
2408 wmb();
2409 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
Stephen Hemminger6abebb52005-07-22 16:26:10 -07002410 skge_led(skge, LED_MODE_ON);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002411
Edgar E. Iglesias239e44e2006-08-14 23:00:24 -07002412 netif_poll_enable(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002413 return 0;
2414
2415 free_rx_ring:
2416 skge_rx_clean(skge);
2417 kfree(skge->rx_ring.start);
2418 free_pci_mem:
2419 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
Stephen Hemminger7731a4e2005-12-14 15:47:46 -08002420 skge->mem = NULL;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002421
2422 return err;
2423}
2424
2425static int skge_down(struct net_device *dev)
2426{
2427 struct skge_port *skge = netdev_priv(dev);
2428 struct skge_hw *hw = skge->hw;
2429 int port = skge->port;
2430
Stephen Hemminger7731a4e2005-12-14 15:47:46 -08002431 if (skge->mem == NULL)
2432 return 0;
2433
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002434 if (netif_msg_ifdown(skge))
2435 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2436
2437 netif_stop_queue(dev);
Stephen Hemminger64f6b642006-09-23 21:25:28 -07002438 if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
2439 cancel_rearming_delayed_work(&skge->link_thread);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002440
Stephen Hemminger46a60f22005-09-09 12:54:56 -07002441 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2442 if (hw->chip_id == CHIP_ID_GENESIS)
2443 genesis_stop(skge);
2444 else
2445 yukon_stop(skge);
2446
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002447 /* Stop transmitter */
2448 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2449 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2450 RB_RST_SET|RB_DIS_OP_MD);
2451
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002452
2453 /* Disable Force Sync bit and Enable Alloc bit */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002454 skge_write8(hw, SK_REG(port, TXA_CTRL),
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002455 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2456
2457 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002458 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2459 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002460
2461 /* Reset PCI FIFO */
2462 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2463 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2464
2465 /* Reset the RAM Buffer async Tx queue */
2466 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2467 /* stop receiver */
2468 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2469 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2470 RB_RST_SET|RB_DIS_OP_MD);
2471 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2472
2473 if (hw->chip_id == CHIP_ID_GENESIS) {
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002474 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2475 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002476 } else {
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002477 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2478 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002479 }
2480
Stephen Hemminger6abebb52005-07-22 16:26:10 -07002481 skge_led(skge, LED_MODE_OFF);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002482
Edgar E. Iglesias239e44e2006-08-14 23:00:24 -07002483 netif_poll_disable(dev);
Stephen Hemminger513f5332006-09-01 15:53:49 -07002484 skge_tx_clean(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002485 skge_rx_clean(skge);
2486
2487 kfree(skge->rx_ring.start);
2488 kfree(skge->tx_ring.start);
2489 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
Stephen Hemminger7731a4e2005-12-14 15:47:46 -08002490 skge->mem = NULL;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002491 return 0;
2492}
2493
Stephen Hemminger29b4e882006-03-23 11:07:28 -08002494static inline int skge_avail(const struct skge_ring *ring)
2495{
2496 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2497 + (ring->to_clean - ring->to_use) - 1;
2498}
2499
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002500static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2501{
2502 struct skge_port *skge = netdev_priv(dev);
2503 struct skge_hw *hw = skge->hw;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002504 struct skge_element *e;
2505 struct skge_tx_desc *td;
2506 int i;
2507 u32 control, len;
2508 u64 map;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002509
Herbert Xu5b057c62006-06-23 02:06:41 -07002510 if (skb_padto(skb, ETH_ZLEN))
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002511 return NETDEV_TX_OK;
2512
Stephen Hemminger513f5332006-09-01 15:53:49 -07002513 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002514 return NETDEV_TX_BUSY;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002515
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002516 e = skge->tx_ring.to_use;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002517 td = e->desc;
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002518 BUG_ON(td->control & BMU_OWN);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002519 e->skb = skb;
2520 len = skb_headlen(skb);
2521 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2522 pci_unmap_addr_set(e, mapaddr, map);
2523 pci_unmap_len_set(e, maplen, len);
2524
2525 td->dma_lo = map;
2526 td->dma_hi = map >> 32;
2527
Patrick McHardy84fa7932006-08-29 16:44:56 -07002528 if (skb->ip_summed == CHECKSUM_PARTIAL) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002529 int offset = skb->h.raw - skb->data;
2530
2531 /* This seems backwards, but it is what the sk98lin
2532 * does. Looks like hardware is wrong?
2533 */
Jeff Garzikea182d42005-12-01 04:31:32 -05002534 if (skb->h.ipiph->protocol == IPPROTO_UDP
Stephen Hemminger981d0372005-06-27 11:33:06 -07002535 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002536 control = BMU_TCP_CHECK;
2537 else
2538 control = BMU_UDP_CHECK;
2539
2540 td->csum_offs = 0;
2541 td->csum_start = offset;
2542 td->csum_write = offset + skb->csum;
2543 } else
2544 control = BMU_CHECK;
2545
2546 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2547 control |= BMU_EOF| BMU_IRQ_EOF;
2548 else {
2549 struct skge_tx_desc *tf = td;
2550
2551 control |= BMU_STFWD;
2552 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2553 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2554
2555 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2556 frag->size, PCI_DMA_TODEVICE);
2557
2558 e = e->next;
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002559 e->skb = skb;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002560 tf = e->desc;
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002561 BUG_ON(tf->control & BMU_OWN);
2562
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002563 tf->dma_lo = map;
2564 tf->dma_hi = (u64) map >> 32;
2565 pci_unmap_addr_set(e, mapaddr, map);
2566 pci_unmap_len_set(e, maplen, frag->size);
2567
2568 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2569 }
2570 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2571 }
2572 /* Make sure all the descriptors written */
2573 wmb();
2574 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2575 wmb();
2576
2577 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2578
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002579 if (unlikely(netif_msg_tx_queued(skge)))
Al Viro0b2d7fe2005-04-03 09:15:52 +01002580 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002581 dev->name, e - skge->tx_ring.start, skb->len);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002582
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002583 skge->tx_ring.to_use = e->next;
Stephen Hemminger9db96472006-06-06 10:11:12 -07002584 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002585 pr_debug("%s: transmit queue full\n", dev->name);
2586 netif_stop_queue(dev);
2587 }
2588
Stephen Hemmingerc68ce712006-03-21 10:57:04 -08002589 dev->trans_start = jiffies;
2590
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002591 return NETDEV_TX_OK;
2592}
2593
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002594
2595/* Free resources associated with this reing element */
2596static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2597 u32 control)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002598{
Stephen Hemminger866b4f32006-03-23 11:07:27 -08002599 struct pci_dev *pdev = skge->hw->pdev;
Stephen Hemminger866b4f32006-03-23 11:07:27 -08002600
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002601 BUG_ON(!e->skb);
Stephen Hemminger866b4f32006-03-23 11:07:27 -08002602
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002603 /* skb header vs. fragment */
2604 if (control & BMU_STF)
Stephen Hemminger866b4f32006-03-23 11:07:27 -08002605 pci_unmap_single(pdev, pci_unmap_addr(e, mapaddr),
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002606 pci_unmap_len(e, maplen),
2607 PCI_DMA_TODEVICE);
2608 else
2609 pci_unmap_page(pdev, pci_unmap_addr(e, mapaddr),
2610 pci_unmap_len(e, maplen),
2611 PCI_DMA_TODEVICE);
Stephen Hemminger866b4f32006-03-23 11:07:27 -08002612
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002613 if (control & BMU_EOF) {
2614 if (unlikely(netif_msg_tx_done(skge)))
2615 printk(KERN_DEBUG PFX "%s: tx done slot %td\n",
2616 skge->netdev->name, e - skge->tx_ring.start);
Stephen Hemminger866b4f32006-03-23 11:07:27 -08002617
Stephen Hemminger513f5332006-09-01 15:53:49 -07002618 dev_kfree_skb(e->skb);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002619 }
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002620 e->skb = NULL;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002621}
2622
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002623/* Free all buffers in transmit ring */
Stephen Hemminger513f5332006-09-01 15:53:49 -07002624static void skge_tx_clean(struct net_device *dev)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002625{
Stephen Hemminger513f5332006-09-01 15:53:49 -07002626 struct skge_port *skge = netdev_priv(dev);
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002627 struct skge_element *e;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002628
Stephen Hemminger513f5332006-09-01 15:53:49 -07002629 netif_tx_lock_bh(dev);
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002630 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2631 struct skge_tx_desc *td = e->desc;
2632 skge_tx_free(skge, e, td->control);
2633 td->control = 0;
2634 }
2635
2636 skge->tx_ring.to_clean = e;
Stephen Hemminger513f5332006-09-01 15:53:49 -07002637 netif_wake_queue(dev);
2638 netif_tx_unlock_bh(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002639}
2640
2641static void skge_tx_timeout(struct net_device *dev)
2642{
2643 struct skge_port *skge = netdev_priv(dev);
2644
2645 if (netif_msg_timer(skge))
2646 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2647
2648 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
Stephen Hemminger513f5332006-09-01 15:53:49 -07002649 skge_tx_clean(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002650}
2651
2652static int skge_change_mtu(struct net_device *dev, int new_mtu)
2653{
Stephen Hemminger7731a4e2005-12-14 15:47:46 -08002654 int err;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002655
Stephen Hemminger95566062005-06-27 11:33:02 -07002656 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002657 return -EINVAL;
2658
Stephen Hemminger7731a4e2005-12-14 15:47:46 -08002659 if (!netif_running(dev)) {
2660 dev->mtu = new_mtu;
2661 return 0;
2662 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002663
Stephen Hemminger7731a4e2005-12-14 15:47:46 -08002664 skge_down(dev);
2665
Stephen Hemminger19a33d42005-06-27 11:33:15 -07002666 dev->mtu = new_mtu;
Stephen Hemminger7731a4e2005-12-14 15:47:46 -08002667
2668 err = skge_up(dev);
2669 if (err)
2670 dev_close(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002671
2672 return err;
2673}
2674
2675static void genesis_set_multicast(struct net_device *dev)
2676{
2677 struct skge_port *skge = netdev_priv(dev);
2678 struct skge_hw *hw = skge->hw;
2679 int port = skge->port;
2680 int i, count = dev->mc_count;
2681 struct dev_mc_list *list = dev->mc_list;
2682 u32 mode;
2683 u8 filter[8];
2684
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002685 mode = xm_read32(hw, port, XM_MODE);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002686 mode |= XM_MD_ENA_HASH;
2687 if (dev->flags & IFF_PROMISC)
2688 mode |= XM_MD_ENA_PROM;
2689 else
2690 mode &= ~XM_MD_ENA_PROM;
2691
2692 if (dev->flags & IFF_ALLMULTI)
2693 memset(filter, 0xff, sizeof(filter));
2694 else {
2695 memset(filter, 0, sizeof(filter));
Stephen Hemminger95566062005-06-27 11:33:02 -07002696 for (i = 0; list && i < count; i++, list = list->next) {
Stephen Hemminger45bada62005-06-27 11:33:12 -07002697 u32 crc, bit;
2698 crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
2699 bit = ~crc & 0x3f;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002700 filter[bit/8] |= 1 << (bit%8);
2701 }
2702 }
2703
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002704 xm_write32(hw, port, XM_MODE, mode);
Stephen Hemminger45bada62005-06-27 11:33:12 -07002705 xm_outhash(hw, port, XM_HSM, filter);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002706}
2707
2708static void yukon_set_multicast(struct net_device *dev)
2709{
2710 struct skge_port *skge = netdev_priv(dev);
2711 struct skge_hw *hw = skge->hw;
2712 int port = skge->port;
2713 struct dev_mc_list *list = dev->mc_list;
2714 u16 reg;
2715 u8 filter[8];
2716
2717 memset(filter, 0, sizeof(filter));
2718
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002719 reg = gma_read16(hw, port, GM_RX_CTRL);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002720 reg |= GM_RXCR_UCF_ENA;
2721
Stephen Hemminger8f3f8192005-11-08 10:33:45 -08002722 if (dev->flags & IFF_PROMISC) /* promiscuous */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002723 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2724 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2725 memset(filter, 0xff, sizeof(filter));
2726 else if (dev->mc_count == 0) /* no multicast */
2727 reg &= ~GM_RXCR_MCF_ENA;
2728 else {
2729 int i;
2730 reg |= GM_RXCR_MCF_ENA;
2731
Stephen Hemminger95566062005-06-27 11:33:02 -07002732 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002733 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2734 filter[bit/8] |= 1 << (bit%8);
2735 }
2736 }
2737
2738
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002739 gma_write16(hw, port, GM_MC_ADDR_H1,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002740 (u16)filter[0] | ((u16)filter[1] << 8));
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002741 gma_write16(hw, port, GM_MC_ADDR_H2,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002742 (u16)filter[2] | ((u16)filter[3] << 8));
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002743 gma_write16(hw, port, GM_MC_ADDR_H3,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002744 (u16)filter[4] | ((u16)filter[5] << 8));
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002745 gma_write16(hw, port, GM_MC_ADDR_H4,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002746 (u16)filter[6] | ((u16)filter[7] << 8));
2747
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002748 gma_write16(hw, port, GM_RX_CTRL, reg);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002749}
2750
Stephen Hemminger383181a2005-09-19 15:37:16 -07002751static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2752{
2753 if (hw->chip_id == CHIP_ID_GENESIS)
2754 return status >> XMR_FS_LEN_SHIFT;
2755 else
2756 return status >> GMR_FS_LEN_SHIFT;
2757}
2758
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002759static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2760{
2761 if (hw->chip_id == CHIP_ID_GENESIS)
2762 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2763 else
2764 return (status & GMR_FS_ANY_ERR) ||
2765 (status & GMR_FS_RX_OK) == 0;
2766}
2767
Stephen Hemminger383181a2005-09-19 15:37:16 -07002768
2769/* Get receive buffer from descriptor.
2770 * Handles copy of small buffers and reallocation failures
2771 */
Stephen Hemmingerc54f9762006-09-01 15:53:47 -07002772static struct sk_buff *skge_rx_get(struct net_device *dev,
2773 struct skge_element *e,
2774 u32 control, u32 status, u16 csum)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002775{
Stephen Hemmingerc54f9762006-09-01 15:53:47 -07002776 struct skge_port *skge = netdev_priv(dev);
Stephen Hemminger383181a2005-09-19 15:37:16 -07002777 struct sk_buff *skb;
2778 u16 len = control & BMU_BBC;
2779
2780 if (unlikely(netif_msg_rx_status(skge)))
2781 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
Stephen Hemmingerc54f9762006-09-01 15:53:47 -07002782 dev->name, e - skge->rx_ring.start,
Stephen Hemminger383181a2005-09-19 15:37:16 -07002783 status, len);
2784
2785 if (len > skge->rx_buf_size)
2786 goto error;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002787
Stephen Hemminger19a33d42005-06-27 11:33:15 -07002788 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
Stephen Hemminger383181a2005-09-19 15:37:16 -07002789 goto error;
2790
2791 if (bad_phy_status(skge->hw, status))
2792 goto error;
2793
2794 if (phy_length(skge->hw, status) != len)
2795 goto error;
2796
2797 if (len < RX_COPY_THRESHOLD) {
Stephen Hemmingerc54f9762006-09-01 15:53:47 -07002798 skb = netdev_alloc_skb(dev, len + 2);
Stephen Hemminger383181a2005-09-19 15:37:16 -07002799 if (!skb)
2800 goto resubmit;
2801
2802 skb_reserve(skb, 2);
2803 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2804 pci_unmap_addr(e, mapaddr),
2805 len, PCI_DMA_FROMDEVICE);
2806 memcpy(skb->data, e->skb->data, len);
2807 pci_dma_sync_single_for_device(skge->hw->pdev,
2808 pci_unmap_addr(e, mapaddr),
2809 len, PCI_DMA_FROMDEVICE);
2810 skge_rx_reuse(e, skge->rx_buf_size);
2811 } else {
2812 struct sk_buff *nskb;
Stephen Hemmingerc54f9762006-09-01 15:53:47 -07002813 nskb = netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN);
Stephen Hemminger383181a2005-09-19 15:37:16 -07002814 if (!nskb)
2815 goto resubmit;
2816
Stephen Hemminger901ccef2006-03-23 11:07:23 -08002817 skb_reserve(nskb, NET_IP_ALIGN);
Stephen Hemminger383181a2005-09-19 15:37:16 -07002818 pci_unmap_single(skge->hw->pdev,
2819 pci_unmap_addr(e, mapaddr),
2820 pci_unmap_len(e, maplen),
2821 PCI_DMA_FROMDEVICE);
2822 skb = e->skb;
2823 prefetch(skb->data);
2824 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
2825 }
2826
2827 skb_put(skb, len);
Stephen Hemminger383181a2005-09-19 15:37:16 -07002828 if (skge->rx_csum) {
2829 skb->csum = csum;
Patrick McHardy84fa7932006-08-29 16:44:56 -07002830 skb->ip_summed = CHECKSUM_COMPLETE;
Stephen Hemminger383181a2005-09-19 15:37:16 -07002831 }
2832
Stephen Hemmingerc54f9762006-09-01 15:53:47 -07002833 skb->protocol = eth_type_trans(skb, dev);
Stephen Hemminger383181a2005-09-19 15:37:16 -07002834
2835 return skb;
2836error:
2837
2838 if (netif_msg_rx_err(skge))
2839 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
Stephen Hemmingerc54f9762006-09-01 15:53:47 -07002840 dev->name, e - skge->rx_ring.start,
Stephen Hemminger383181a2005-09-19 15:37:16 -07002841 control, status);
2842
2843 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
Stephen Hemminger19a33d42005-06-27 11:33:15 -07002844 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2845 skge->net_stats.rx_length_errors++;
2846 if (status & XMR_FS_FRA_ERR)
2847 skge->net_stats.rx_frame_errors++;
2848 if (status & XMR_FS_FCS_ERR)
2849 skge->net_stats.rx_crc_errors++;
2850 } else {
2851 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2852 skge->net_stats.rx_length_errors++;
2853 if (status & GMR_FS_FRAGMENT)
2854 skge->net_stats.rx_frame_errors++;
2855 if (status & GMR_FS_CRC_ERR)
2856 skge->net_stats.rx_crc_errors++;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002857 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002858
Stephen Hemminger383181a2005-09-19 15:37:16 -07002859resubmit:
2860 skge_rx_reuse(e, skge->rx_buf_size);
2861 return NULL;
Stephen Hemminger19a33d42005-06-27 11:33:15 -07002862}
2863
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002864/* Free all buffers in Tx ring which are no longer owned by device */
Stephen Hemminger513f5332006-09-01 15:53:49 -07002865static void skge_tx_done(struct net_device *dev)
Stephen Hemminger00a6cae2006-03-21 10:56:59 -08002866{
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002867 struct skge_port *skge = netdev_priv(dev);
Stephen Hemminger00a6cae2006-03-21 10:56:59 -08002868 struct skge_ring *ring = &skge->tx_ring;
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002869 struct skge_element *e;
2870
Stephen Hemminger513f5332006-09-01 15:53:49 -07002871 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
Stephen Hemminger00a6cae2006-03-21 10:56:59 -08002872
Stephen Hemminger513f5332006-09-01 15:53:49 -07002873 netif_tx_lock(dev);
Stephen Hemminger866b4f32006-03-23 11:07:27 -08002874 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
Stephen Hemminger00a6cae2006-03-21 10:56:59 -08002875 struct skge_tx_desc *td = e->desc;
Stephen Hemminger00a6cae2006-03-21 10:56:59 -08002876
Stephen Hemminger866b4f32006-03-23 11:07:27 -08002877 if (td->control & BMU_OWN)
Stephen Hemminger00a6cae2006-03-21 10:56:59 -08002878 break;
2879
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002880 skge_tx_free(skge, e, td->control);
Stephen Hemminger00a6cae2006-03-21 10:56:59 -08002881 }
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002882 skge->tx_ring.to_clean = e;
Stephen Hemminger866b4f32006-03-23 11:07:27 -08002883
Stephen Hemminger513f5332006-09-01 15:53:49 -07002884 if (skge_avail(&skge->tx_ring) > TX_LOW_WATER)
2885 netif_wake_queue(dev);
Stephen Hemminger00a6cae2006-03-21 10:56:59 -08002886
Stephen Hemminger513f5332006-09-01 15:53:49 -07002887 netif_tx_unlock(dev);
Stephen Hemminger00a6cae2006-03-21 10:56:59 -08002888}
Stephen Hemminger19a33d42005-06-27 11:33:15 -07002889
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002890static int skge_poll(struct net_device *dev, int *budget)
2891{
2892 struct skge_port *skge = netdev_priv(dev);
2893 struct skge_hw *hw = skge->hw;
2894 struct skge_ring *ring = &skge->rx_ring;
2895 struct skge_element *e;
Stephen Hemminger00a6cae2006-03-21 10:56:59 -08002896 int to_do = min(dev->quota, *budget);
2897 int work_done = 0;
2898
Stephen Hemminger513f5332006-09-01 15:53:49 -07002899 skge_tx_done(dev);
2900
2901 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2902
Stephen Hemminger1631aef2005-11-08 10:33:44 -08002903 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002904 struct skge_rx_desc *rd = e->desc;
Stephen Hemminger19a33d42005-06-27 11:33:15 -07002905 struct sk_buff *skb;
Stephen Hemminger383181a2005-09-19 15:37:16 -07002906 u32 control;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002907
2908 rmb();
2909 control = rd->control;
2910 if (control & BMU_OWN)
2911 break;
2912
Stephen Hemmingerc54f9762006-09-01 15:53:47 -07002913 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
Stephen Hemminger19a33d42005-06-27 11:33:15 -07002914 if (likely(skb)) {
Stephen Hemminger19a33d42005-06-27 11:33:15 -07002915 dev->last_rx = jiffies;
2916 netif_receive_skb(skb);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002917
Stephen Hemminger19a33d42005-06-27 11:33:15 -07002918 ++work_done;
Stephen Hemminger5a011442006-03-23 11:07:25 -08002919 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002920 }
2921 ring->to_clean = e;
2922
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002923 /* restart receiver */
2924 wmb();
Stephen Hemmingera9cdab82006-02-22 10:28:33 -08002925 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002926
Stephen Hemminger19a33d42005-06-27 11:33:15 -07002927 *budget -= work_done;
2928 dev->quota -= work_done;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002929
Stephen Hemminger19a33d42005-06-27 11:33:15 -07002930 if (work_done >= to_do)
2931 return 1; /* not done */
2932
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002933 spin_lock_irq(&hw->hw_lock);
Stephen Hemminger513f5332006-09-01 15:53:49 -07002934 __netif_rx_complete(dev);
2935 hw->intr_mask |= irqmask[skge->port];
Stephen Hemminger80dd8572006-02-22 10:28:35 -08002936 skge_write32(hw, B0_IMSK, hw->intr_mask);
Stephen Hemminger78bc2182006-08-28 16:19:36 -07002937 skge_read32(hw, B0_IMSK);
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002938 spin_unlock_irq(&hw->hw_lock);
Stephen Hemminger1631aef2005-11-08 10:33:44 -08002939
Stephen Hemminger19a33d42005-06-27 11:33:15 -07002940 return 0;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002941}
2942
Stephen Hemmingerf6620ca2005-07-22 16:26:02 -07002943/* Parity errors seem to happen when Genesis is connected to a switch
2944 * with no other ports present. Heartbeat error??
2945 */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002946static void skge_mac_parity(struct skge_hw *hw, int port)
2947{
Stephen Hemmingerf6620ca2005-07-22 16:26:02 -07002948 struct net_device *dev = hw->dev[port];
2949
2950 if (dev) {
2951 struct skge_port *skge = netdev_priv(dev);
2952 ++skge->net_stats.tx_heartbeat_errors;
2953 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002954
2955 if (hw->chip_id == CHIP_ID_GENESIS)
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002956 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002957 MFF_CLR_PERR);
2958 else
2959 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002960 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
Stephen Hemminger981d0372005-06-27 11:33:06 -07002961 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002962 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2963}
2964
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002965static void skge_mac_intr(struct skge_hw *hw, int port)
2966{
Stephen Hemminger95566062005-06-27 11:33:02 -07002967 if (hw->chip_id == CHIP_ID_GENESIS)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002968 genesis_mac_intr(hw, port);
2969 else
2970 yukon_mac_intr(hw, port);
2971}
2972
2973/* Handle device specific framing and timeout interrupts */
2974static void skge_error_irq(struct skge_hw *hw)
2975{
2976 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2977
2978 if (hw->chip_id == CHIP_ID_GENESIS) {
2979 /* clear xmac errors */
2980 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
Stephen Hemminger46a60f22005-09-09 12:54:56 -07002981 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002982 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
Stephen Hemminger46a60f22005-09-09 12:54:56 -07002983 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002984 } else {
2985 /* Timestamp (unused) overflow */
2986 if (hwstatus & IS_IRQ_TIST_OV)
2987 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002988 }
2989
2990 if (hwstatus & IS_RAM_RD_PAR) {
2991 printk(KERN_ERR PFX "Ram read data parity error\n");
2992 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2993 }
2994
2995 if (hwstatus & IS_RAM_WR_PAR) {
2996 printk(KERN_ERR PFX "Ram write data parity error\n");
2997 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
2998 }
2999
3000 if (hwstatus & IS_M1_PAR_ERR)
3001 skge_mac_parity(hw, 0);
3002
3003 if (hwstatus & IS_M2_PAR_ERR)
3004 skge_mac_parity(hw, 1);
3005
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003006 if (hwstatus & IS_R1_PAR_ERR) {
3007 printk(KERN_ERR PFX "%s: receive queue parity error\n",
3008 hw->dev[0]->name);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003009 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003010 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003011
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003012 if (hwstatus & IS_R2_PAR_ERR) {
3013 printk(KERN_ERR PFX "%s: receive queue parity error\n",
3014 hw->dev[1]->name);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003015 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003016 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003017
3018 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003019 u16 pci_status, pci_cmd;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003020
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003021 pci_read_config_word(hw->pdev, PCI_COMMAND, &pci_cmd);
3022 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3023
3024 printk(KERN_ERR PFX "%s: PCI error cmd=%#x status=%#x\n",
3025 pci_name(hw->pdev), pci_cmd, pci_status);
3026
3027 /* Write the error bits back to clear them. */
3028 pci_status &= PCI_STATUS_ERROR_BITS;
3029 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3030 pci_write_config_word(hw->pdev, PCI_COMMAND,
3031 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
3032 pci_write_config_word(hw->pdev, PCI_STATUS, pci_status);
3033 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003034
Stephen Hemminger050ec182005-08-16 14:00:54 -07003035 /* if error still set then just ignore it */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003036 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3037 if (hwstatus & IS_IRQ_STAT) {
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003038 printk(KERN_INFO PFX "unable to clear error (so ignoring them)\n");
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003039 hw->intr_mask &= ~IS_HW_ERR;
3040 }
3041 }
3042}
3043
3044/*
Stephen Hemmingerd85b5142006-06-06 10:11:11 -07003045 * Interrupt from PHY are handled in work queue
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003046 * because accessing phy registers requires spin wait which might
3047 * cause excess interrupt latency.
3048 */
Stephen Hemmingerd85b5142006-06-06 10:11:11 -07003049static void skge_extirq(void *arg)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003050{
Stephen Hemmingerd85b5142006-06-06 10:11:11 -07003051 struct skge_hw *hw = arg;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003052 int port;
3053
Stephen Hemmingerd85b5142006-06-06 10:11:11 -07003054 mutex_lock(&hw->phy_mutex);
Stephen Hemmingercfc3ed72006-03-21 10:57:00 -08003055 for (port = 0; port < hw->ports; port++) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003056 struct net_device *dev = hw->dev[port];
Stephen Hemmingercfc3ed72006-03-21 10:57:00 -08003057 struct skge_port *skge = netdev_priv(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003058
Stephen Hemmingercfc3ed72006-03-21 10:57:00 -08003059 if (netif_running(dev)) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003060 if (hw->chip_id != CHIP_ID_GENESIS)
3061 yukon_phy_intr(skge);
Stephen Hemminger64f6b642006-09-23 21:25:28 -07003062 else if (hw->phy_type == SK_PHY_BCOM)
Stephen Hemminger45bada62005-06-27 11:33:12 -07003063 bcom_phy_intr(skge);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003064 }
3065 }
Stephen Hemmingerd85b5142006-06-06 10:11:11 -07003066 mutex_unlock(&hw->phy_mutex);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003067
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003068 spin_lock_irq(&hw->hw_lock);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003069 hw->intr_mask |= IS_EXT_REG;
3070 skge_write32(hw, B0_IMSK, hw->intr_mask);
Stephen Hemminger78bc2182006-08-28 16:19:36 -07003071 skge_read32(hw, B0_IMSK);
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003072 spin_unlock_irq(&hw->hw_lock);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003073}
3074
David Howells7d12e782006-10-05 14:55:46 +01003075static irqreturn_t skge_intr(int irq, void *dev_id)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003076{
3077 struct skge_hw *hw = dev_id;
Stephen Hemmingercfc3ed72006-03-21 10:57:00 -08003078 u32 status;
Stephen Hemminger29365c92006-09-01 15:53:48 -07003079 int handled = 0;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003080
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003081 spin_lock(&hw->hw_lock);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003082 /* Reading this register masks IRQ */
3083 status = skge_read32(hw, B0_SP_ISRC);
Stephen Hemminger0486a8c2006-09-06 11:06:10 -07003084 if (status == 0 || status == ~0)
Stephen Hemminger29365c92006-09-01 15:53:48 -07003085 goto out;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003086
Stephen Hemminger29365c92006-09-01 15:53:48 -07003087 handled = 1;
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003088 status &= hw->intr_mask;
Stephen Hemmingercfc3ed72006-03-21 10:57:00 -08003089 if (status & IS_EXT_REG) {
3090 hw->intr_mask &= ~IS_EXT_REG;
Stephen Hemmingerd85b5142006-06-06 10:11:11 -07003091 schedule_work(&hw->phy_work);
Stephen Hemmingercfc3ed72006-03-21 10:57:00 -08003092 }
3093
Stephen Hemminger513f5332006-09-01 15:53:49 -07003094 if (status & (IS_XA1_F|IS_R1_F)) {
3095 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
Stephen Hemmingera9cdab82006-02-22 10:28:33 -08003096 netif_rx_schedule(hw->dev[0]);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003097 }
3098
Stephen Hemmingerd25f5a62005-06-27 11:33:14 -07003099 if (status & IS_PA_TO_TX1)
3100 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
3101
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003102 if (status & IS_PA_TO_RX1) {
3103 struct skge_port *skge = netdev_priv(hw->dev[0]);
3104
3105 ++skge->net_stats.rx_over_errors;
3106 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
3107 }
3108
Stephen Hemmingerd25f5a62005-06-27 11:33:14 -07003109
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003110 if (status & IS_MAC1)
3111 skge_mac_intr(hw, 0);
Stephen Hemminger95566062005-06-27 11:33:02 -07003112
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003113 if (hw->dev[1]) {
Stephen Hemminger513f5332006-09-01 15:53:49 -07003114 if (status & (IS_XA2_F|IS_R2_F)) {
3115 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003116 netif_rx_schedule(hw->dev[1]);
3117 }
3118
3119 if (status & IS_PA_TO_RX2) {
3120 struct skge_port *skge = netdev_priv(hw->dev[1]);
3121 ++skge->net_stats.rx_over_errors;
3122 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3123 }
3124
3125 if (status & IS_PA_TO_TX2)
3126 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3127
3128 if (status & IS_MAC2)
3129 skge_mac_intr(hw, 1);
3130 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003131
3132 if (status & IS_HW_ERR)
3133 skge_error_irq(hw);
3134
Stephen Hemminger7e676d92005-06-27 11:33:13 -07003135 skge_write32(hw, B0_IMSK, hw->intr_mask);
Stephen Hemminger78bc2182006-08-28 16:19:36 -07003136 skge_read32(hw, B0_IMSK);
Stephen Hemminger29365c92006-09-01 15:53:48 -07003137out:
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003138 spin_unlock(&hw->hw_lock);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003139
Stephen Hemminger29365c92006-09-01 15:53:48 -07003140 return IRQ_RETVAL(handled);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003141}
3142
3143#ifdef CONFIG_NET_POLL_CONTROLLER
3144static void skge_netpoll(struct net_device *dev)
3145{
3146 struct skge_port *skge = netdev_priv(dev);
3147
3148 disable_irq(dev->irq);
David Howells7d12e782006-10-05 14:55:46 +01003149 skge_intr(dev->irq, skge->hw);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003150 enable_irq(dev->irq);
3151}
3152#endif
3153
3154static int skge_set_mac_address(struct net_device *dev, void *p)
3155{
3156 struct skge_port *skge = netdev_priv(dev);
Stephen Hemmingerc2681dd2005-10-03 12:03:13 -07003157 struct skge_hw *hw = skge->hw;
3158 unsigned port = skge->port;
3159 const struct sockaddr *addr = p;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003160
3161 if (!is_valid_ether_addr(addr->sa_data))
3162 return -EADDRNOTAVAIL;
3163
Stephen Hemmingerd85b5142006-06-06 10:11:11 -07003164 mutex_lock(&hw->phy_mutex);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003165 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
Stephen Hemmingerc2681dd2005-10-03 12:03:13 -07003166 memcpy_toio(hw->regs + B2_MAC_1 + port*8,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003167 dev->dev_addr, ETH_ALEN);
Stephen Hemmingerc2681dd2005-10-03 12:03:13 -07003168 memcpy_toio(hw->regs + B2_MAC_2 + port*8,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003169 dev->dev_addr, ETH_ALEN);
Stephen Hemmingerc2681dd2005-10-03 12:03:13 -07003170
3171 if (hw->chip_id == CHIP_ID_GENESIS)
3172 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3173 else {
3174 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3175 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3176 }
Stephen Hemmingerd85b5142006-06-06 10:11:11 -07003177 mutex_unlock(&hw->phy_mutex);
Stephen Hemmingerc2681dd2005-10-03 12:03:13 -07003178
3179 return 0;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003180}
3181
3182static const struct {
3183 u8 id;
3184 const char *name;
3185} skge_chips[] = {
3186 { CHIP_ID_GENESIS, "Genesis" },
3187 { CHIP_ID_YUKON, "Yukon" },
3188 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3189 { CHIP_ID_YUKON_LP, "Yukon-LP"},
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003190};
3191
3192static const char *skge_board_name(const struct skge_hw *hw)
3193{
3194 int i;
3195 static char buf[16];
3196
3197 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3198 if (skge_chips[i].id == hw->chip_id)
3199 return skge_chips[i].name;
3200
3201 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3202 return buf;
3203}
3204
3205
3206/*
3207 * Setup the board data structure, but don't bring up
3208 * the port(s)
3209 */
3210static int skge_reset(struct skge_hw *hw)
3211{
Stephen Hemmingeradba9e22005-11-08 10:33:40 -08003212 u32 reg;
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003213 u16 ctst, pci_status;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07003214 u8 t8, mac_cfg, pmd_type;
Stephen Hemminger981d0372005-06-27 11:33:06 -07003215 int i;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003216
3217 ctst = skge_read16(hw, B0_CTST);
3218
3219 /* do a SW reset */
3220 skge_write8(hw, B0_CTST, CS_RST_SET);
3221 skge_write8(hw, B0_CTST, CS_RST_CLR);
3222
3223 /* clear PCI errors, if any */
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003224 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3225 skge_write8(hw, B2_TST_CTRL2, 0);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003226
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003227 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3228 pci_write_config_word(hw->pdev, PCI_STATUS,
3229 pci_status | PCI_STATUS_ERROR_BITS);
3230 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003231 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3232
3233 /* restore CLK_RUN bits (for Yukon-Lite) */
3234 skge_write16(hw, B0_CTST,
3235 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3236
3237 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
Stephen Hemminger64f6b642006-09-23 21:25:28 -07003238 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
Stephen Hemminger5e1705d2005-08-16 14:00:58 -07003239 pmd_type = skge_read8(hw, B2_PMD_TYP);
3240 hw->copper = (pmd_type == 'T' || pmd_type == '1');
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003241
Stephen Hemminger95566062005-06-27 11:33:02 -07003242 switch (hw->chip_id) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003243 case CHIP_ID_GENESIS:
Stephen Hemminger64f6b642006-09-23 21:25:28 -07003244 switch (hw->phy_type) {
3245 case SK_PHY_XMAC:
3246 hw->phy_addr = PHY_ADDR_XMAC;
3247 break;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003248 case SK_PHY_BCOM:
3249 hw->phy_addr = PHY_ADDR_BCOM;
3250 break;
3251 default:
3252 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
Stephen Hemminger64f6b642006-09-23 21:25:28 -07003253 pci_name(hw->pdev), hw->phy_type);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003254 return -EOPNOTSUPP;
3255 }
3256 break;
3257
3258 case CHIP_ID_YUKON:
3259 case CHIP_ID_YUKON_LITE:
3260 case CHIP_ID_YUKON_LP:
Stephen Hemminger64f6b642006-09-23 21:25:28 -07003261 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
Stephen Hemminger5e1705d2005-08-16 14:00:58 -07003262 hw->copper = 1;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003263
3264 hw->phy_addr = PHY_ADDR_MARV;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003265 break;
3266
3267 default:
3268 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
3269 pci_name(hw->pdev), hw->chip_id);
3270 return -EOPNOTSUPP;
3271 }
3272
Stephen Hemminger981d0372005-06-27 11:33:06 -07003273 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3274 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3275 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003276
3277 /* read the adapters RAM size */
3278 t8 = skge_read8(hw, B2_E_0);
3279 if (hw->chip_id == CHIP_ID_GENESIS) {
3280 if (t8 == 3) {
3281 /* special case: 4 x 64k x 36, offset = 0x80000 */
3282 hw->ram_size = 0x100000;
3283 hw->ram_offset = 0x80000;
3284 } else
3285 hw->ram_size = t8 * 512;
3286 }
3287 else if (t8 == 0)
3288 hw->ram_size = 0x20000;
3289 else
3290 hw->ram_size = t8 * 4096;
3291
Stephen Hemminger64f6b642006-09-23 21:25:28 -07003292 hw->intr_mask = IS_HW_ERR | IS_PORT_1;
Stephen Hemmingercfc3ed72006-03-21 10:57:00 -08003293 if (hw->ports > 1)
3294 hw->intr_mask |= IS_PORT_2;
3295
Stephen Hemminger64f6b642006-09-23 21:25:28 -07003296 if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
3297 hw->intr_mask |= IS_EXT_REG;
3298
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003299 if (hw->chip_id == CHIP_ID_GENESIS)
3300 genesis_init(hw);
3301 else {
3302 /* switch power to VCC (WA for VAUX problem) */
3303 skge_write8(hw, B0_POWER_CTRL,
3304 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
Stephen Hemmingeradba9e22005-11-08 10:33:40 -08003305
Stephen Hemminger050ec182005-08-16 14:00:54 -07003306 /* avoid boards with stuck Hardware error bits */
3307 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3308 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3309 printk(KERN_WARNING PFX "stuck hardware sensor bit\n");
3310 hw->intr_mask &= ~IS_HW_ERR;
3311 }
3312
Stephen Hemmingeradba9e22005-11-08 10:33:40 -08003313 /* Clear PHY COMA */
3314 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3315 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3316 reg &= ~PCI_PHY_COMA;
3317 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3318 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3319
3320
Stephen Hemminger981d0372005-06-27 11:33:06 -07003321 for (i = 0; i < hw->ports; i++) {
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07003322 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3323 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003324 }
3325 }
3326
3327 /* turn off hardware timer (unused) */
3328 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3329 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3330 skge_write8(hw, B0_LED, LED_STAT_ON);
3331
3332 /* enable the Tx Arbiters */
Stephen Hemminger981d0372005-06-27 11:33:06 -07003333 for (i = 0; i < hw->ports; i++)
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07003334 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003335
3336 /* Initialize ram interface */
3337 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3338
3339 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3340 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3341 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3342 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3343 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3344 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3345 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3346 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3347 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3348 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3349 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3350 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3351
3352 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3353
3354 /* Set interrupt moderation for Transmit only
3355 * Receive interrupts avoided by NAPI
3356 */
3357 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3358 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3359 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3360
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003361 skge_write32(hw, B0_IMSK, hw->intr_mask);
3362
Stephen Hemmingerd85b5142006-06-06 10:11:11 -07003363 mutex_lock(&hw->phy_mutex);
Stephen Hemminger981d0372005-06-27 11:33:06 -07003364 for (i = 0; i < hw->ports; i++) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003365 if (hw->chip_id == CHIP_ID_GENESIS)
3366 genesis_reset(hw, i);
3367 else
3368 yukon_reset(hw, i);
3369 }
Stephen Hemmingerd85b5142006-06-06 10:11:11 -07003370 mutex_unlock(&hw->phy_mutex);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003371
3372 return 0;
3373}
3374
3375/* Initialize network device */
Stephen Hemminger981d0372005-06-27 11:33:06 -07003376static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3377 int highmem)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003378{
3379 struct skge_port *skge;
3380 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3381
3382 if (!dev) {
3383 printk(KERN_ERR "skge etherdev alloc failed");
3384 return NULL;
3385 }
3386
3387 SET_MODULE_OWNER(dev);
3388 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3389 dev->open = skge_up;
3390 dev->stop = skge_down;
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08003391 dev->do_ioctl = skge_ioctl;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003392 dev->hard_start_xmit = skge_xmit_frame;
3393 dev->get_stats = skge_get_stats;
3394 if (hw->chip_id == CHIP_ID_GENESIS)
3395 dev->set_multicast_list = genesis_set_multicast;
3396 else
3397 dev->set_multicast_list = yukon_set_multicast;
3398
3399 dev->set_mac_address = skge_set_mac_address;
3400 dev->change_mtu = skge_change_mtu;
3401 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3402 dev->tx_timeout = skge_tx_timeout;
3403 dev->watchdog_timeo = TX_WATCHDOG;
3404 dev->poll = skge_poll;
3405 dev->weight = NAPI_WEIGHT;
3406#ifdef CONFIG_NET_POLL_CONTROLLER
3407 dev->poll_controller = skge_netpoll;
3408#endif
3409 dev->irq = hw->pdev->irq;
Stephen Hemminger513f5332006-09-01 15:53:49 -07003410
Stephen Hemminger981d0372005-06-27 11:33:06 -07003411 if (highmem)
3412 dev->features |= NETIF_F_HIGHDMA;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003413
3414 skge = netdev_priv(dev);
3415 skge->netdev = dev;
3416 skge->hw = hw;
3417 skge->msg_enable = netif_msg_init(debug, default_msg);
3418 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3419 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3420
3421 /* Auto speed and flow control */
3422 skge->autoneg = AUTONEG_ENABLE;
3423 skge->flow_control = FLOW_MODE_SYMMETRIC;
3424 skge->duplex = -1;
3425 skge->speed = -1;
Stephen Hemminger31b619c2005-06-27 11:33:11 -07003426 skge->advertising = skge_supported_modes(hw);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003427
3428 hw->dev[port] = dev;
3429
3430 skge->port = port;
3431
Stephen Hemminger64f6b642006-09-23 21:25:28 -07003432 /* Only used for Genesis XMAC */
3433 INIT_WORK(&skge->link_thread, xm_link_timer, dev);
3434
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003435 if (hw->chip_id != CHIP_ID_GENESIS) {
3436 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3437 skge->rx_csum = 1;
3438 }
3439
3440 /* read the mac address */
3441 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
John W. Linville56230d52005-09-12 10:48:57 -04003442 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003443
3444 /* device is off until link detection */
3445 netif_carrier_off(dev);
3446 netif_stop_queue(dev);
3447
3448 return dev;
3449}
3450
3451static void __devinit skge_show_addr(struct net_device *dev)
3452{
3453 const struct skge_port *skge = netdev_priv(dev);
3454
3455 if (netif_msg_probe(skge))
3456 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3457 dev->name,
3458 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3459 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3460}
3461
3462static int __devinit skge_probe(struct pci_dev *pdev,
3463 const struct pci_device_id *ent)
3464{
3465 struct net_device *dev, *dev1;
3466 struct skge_hw *hw;
3467 int err, using_dac = 0;
3468
Stephen Hemminger203babb2006-03-21 10:57:05 -08003469 err = pci_enable_device(pdev);
3470 if (err) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003471 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3472 pci_name(pdev));
3473 goto err_out;
3474 }
3475
Stephen Hemminger203babb2006-03-21 10:57:05 -08003476 err = pci_request_regions(pdev, DRV_NAME);
3477 if (err) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003478 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3479 pci_name(pdev));
3480 goto err_out_disable_pdev;
3481 }
3482
3483 pci_set_master(pdev);
3484
Stephen Hemminger93aea712006-03-21 10:57:02 -08003485 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003486 using_dac = 1;
Stephen Hemminger77783a72006-01-05 16:26:05 -08003487 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
Stephen Hemminger93aea712006-03-21 10:57:02 -08003488 } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3489 using_dac = 0;
3490 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3491 }
3492
3493 if (err) {
3494 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3495 pci_name(pdev));
3496 goto err_out_free_regions;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003497 }
3498
3499#ifdef __BIG_ENDIAN
Stephen Hemminger8f3f8192005-11-08 10:33:45 -08003500 /* byte swap descriptors in hardware */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003501 {
3502 u32 reg;
3503
3504 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3505 reg |= PCI_REV_DESC;
3506 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3507 }
3508#endif
3509
3510 err = -ENOMEM;
Stephen Hemminger7e863062005-11-08 10:33:41 -08003511 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003512 if (!hw) {
3513 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3514 pci_name(pdev));
3515 goto err_out_free_regions;
3516 }
3517
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003518 hw->pdev = pdev;
Stephen Hemmingerd85b5142006-06-06 10:11:11 -07003519 mutex_init(&hw->phy_mutex);
3520 INIT_WORK(&hw->phy_work, skge_extirq, hw);
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07003521 spin_lock_init(&hw->hw_lock);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003522
3523 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3524 if (!hw->regs) {
3525 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3526 pci_name(pdev));
3527 goto err_out_free_hw;
3528 }
3529
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003530 err = skge_reset(hw);
3531 if (err)
Stephen Hemmingerccdaa2a2006-08-28 16:19:38 -07003532 goto err_out_iounmap;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003533
Greg Kroah-Hartman7c7459d2006-06-12 15:13:08 -07003534 printk(KERN_INFO PFX DRV_VERSION " addr 0x%llx irq %d chip %s rev %d\n",
3535 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
Stephen Hemminger981d0372005-06-27 11:33:06 -07003536 skge_board_name(hw), hw->chip_rev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003537
Stephen Hemmingerccdaa2a2006-08-28 16:19:38 -07003538 dev = skge_devinit(hw, 0, using_dac);
3539 if (!dev)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003540 goto err_out_led_off;
3541
Stephen Hemminger631ae322006-06-06 10:11:14 -07003542 if (!is_valid_ether_addr(dev->dev_addr)) {
3543 printk(KERN_ERR PFX "%s: bad (zero?) ethernet address in rom\n",
3544 pci_name(pdev));
3545 err = -EIO;
3546 goto err_out_free_netdev;
3547 }
3548
Stephen Hemminger203babb2006-03-21 10:57:05 -08003549 err = register_netdev(dev);
3550 if (err) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003551 printk(KERN_ERR PFX "%s: cannot register net device\n",
3552 pci_name(pdev));
3553 goto err_out_free_netdev;
3554 }
3555
Stephen Hemmingerccdaa2a2006-08-28 16:19:38 -07003556 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, dev->name, hw);
3557 if (err) {
3558 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3559 dev->name, pdev->irq);
3560 goto err_out_unregister;
3561 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003562 skge_show_addr(dev);
3563
Stephen Hemminger981d0372005-06-27 11:33:06 -07003564 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003565 if (register_netdev(dev1) == 0)
3566 skge_show_addr(dev1);
3567 else {
3568 /* Failure to register second port need not be fatal */
3569 printk(KERN_WARNING PFX "register of second port failed\n");
3570 hw->dev[1] = NULL;
3571 free_netdev(dev1);
3572 }
3573 }
Stephen Hemmingerccdaa2a2006-08-28 16:19:38 -07003574 pci_set_drvdata(pdev, hw);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003575
3576 return 0;
3577
Stephen Hemmingerccdaa2a2006-08-28 16:19:38 -07003578err_out_unregister:
3579 unregister_netdev(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003580err_out_free_netdev:
3581 free_netdev(dev);
3582err_out_led_off:
3583 skge_write16(hw, B0_LED, LED_STAT_OFF);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003584err_out_iounmap:
3585 iounmap(hw->regs);
3586err_out_free_hw:
3587 kfree(hw);
3588err_out_free_regions:
3589 pci_release_regions(pdev);
3590err_out_disable_pdev:
3591 pci_disable_device(pdev);
3592 pci_set_drvdata(pdev, NULL);
3593err_out:
3594 return err;
3595}
3596
3597static void __devexit skge_remove(struct pci_dev *pdev)
3598{
3599 struct skge_hw *hw = pci_get_drvdata(pdev);
3600 struct net_device *dev0, *dev1;
3601
Stephen Hemminger95566062005-06-27 11:33:02 -07003602 if (!hw)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003603 return;
3604
3605 if ((dev1 = hw->dev[1]))
3606 unregister_netdev(dev1);
3607 dev0 = hw->dev[0];
3608 unregister_netdev(dev0);
3609
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003610 spin_lock_irq(&hw->hw_lock);
3611 hw->intr_mask = 0;
Stephen Hemminger46a60f22005-09-09 12:54:56 -07003612 skge_write32(hw, B0_IMSK, 0);
Stephen Hemminger78bc2182006-08-28 16:19:36 -07003613 skge_read32(hw, B0_IMSK);
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003614 spin_unlock_irq(&hw->hw_lock);
3615
Stephen Hemminger46a60f22005-09-09 12:54:56 -07003616 skge_write16(hw, B0_LED, LED_STAT_OFF);
Stephen Hemminger46a60f22005-09-09 12:54:56 -07003617 skge_write8(hw, B0_CTST, CS_RST_SET);
3618
Stephen Hemmingerd85b5142006-06-06 10:11:11 -07003619 flush_scheduled_work();
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003620
3621 free_irq(pdev->irq, hw);
3622 pci_release_regions(pdev);
3623 pci_disable_device(pdev);
3624 if (dev1)
3625 free_netdev(dev1);
3626 free_netdev(dev0);
Stephen Hemminger46a60f22005-09-09 12:54:56 -07003627
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003628 iounmap(hw->regs);
3629 kfree(hw);
3630 pci_set_drvdata(pdev, NULL);
3631}
3632
3633#ifdef CONFIG_PM
Pavel Machek2a569572005-07-07 17:56:40 -07003634static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003635{
3636 struct skge_hw *hw = pci_get_drvdata(pdev);
3637 int i, wol = 0;
3638
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07003639 pci_save_state(pdev);
3640 for (i = 0; i < hw->ports; i++) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003641 struct net_device *dev = hw->dev[i];
3642
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07003643 if (netif_running(dev)) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003644 struct skge_port *skge = netdev_priv(dev);
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07003645
3646 netif_carrier_off(dev);
3647 if (skge->wol)
3648 netif_stop_queue(dev);
3649 else
3650 skge_down(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003651 wol |= skge->wol;
3652 }
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07003653 netif_device_detach(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003654 }
3655
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07003656 skge_write32(hw, B0_IMSK, 0);
Pavel Machek2a569572005-07-07 17:56:40 -07003657 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003658 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3659
3660 return 0;
3661}
3662
3663static int skge_resume(struct pci_dev *pdev)
3664{
3665 struct skge_hw *hw = pci_get_drvdata(pdev);
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07003666 int i, err;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003667
3668 pci_set_power_state(pdev, PCI_D0);
3669 pci_restore_state(pdev);
3670 pci_enable_wake(pdev, PCI_D0, 0);
3671
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07003672 err = skge_reset(hw);
3673 if (err)
3674 goto out;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003675
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07003676 for (i = 0; i < hw->ports; i++) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003677 struct net_device *dev = hw->dev[i];
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07003678
3679 netif_device_attach(dev);
3680 if (netif_running(dev)) {
3681 err = skge_up(dev);
3682
3683 if (err) {
3684 printk(KERN_ERR PFX "%s: could not up: %d\n",
3685 dev->name, err);
Stephen Hemmingeredd702e2005-12-15 12:18:00 -08003686 dev_close(dev);
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07003687 goto out;
3688 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003689 }
3690 }
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07003691out:
3692 return err;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003693}
3694#endif
3695
3696static struct pci_driver skge_driver = {
3697 .name = DRV_NAME,
3698 .id_table = skge_id_table,
3699 .probe = skge_probe,
3700 .remove = __devexit_p(skge_remove),
3701#ifdef CONFIG_PM
3702 .suspend = skge_suspend,
3703 .resume = skge_resume,
3704#endif
3705};
3706
3707static int __init skge_init_module(void)
3708{
Jeff Garzik29917622006-08-19 17:48:59 -04003709 return pci_register_driver(&skge_driver);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003710}
3711
3712static void __exit skge_cleanup_module(void)
3713{
3714 pci_unregister_driver(&skge_driver);
3715}
3716
3717module_init(skge_init_module);
3718module_exit(skge_cleanup_module);