Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Driver for Cirrus Logic CS4281 based PCI soundcard |
| 3 | * Copyright (c) by Jaroslav Kysela <perex@suse.cz>, |
| 4 | * |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 19 | * |
| 20 | */ |
| 21 | |
| 22 | #include <sound/driver.h> |
| 23 | #include <asm/io.h> |
| 24 | #include <linux/delay.h> |
| 25 | #include <linux/interrupt.h> |
| 26 | #include <linux/init.h> |
| 27 | #include <linux/pci.h> |
| 28 | #include <linux/slab.h> |
| 29 | #include <linux/gameport.h> |
| 30 | #include <linux/moduleparam.h> |
| 31 | #include <sound/core.h> |
| 32 | #include <sound/control.h> |
| 33 | #include <sound/pcm.h> |
| 34 | #include <sound/rawmidi.h> |
| 35 | #include <sound/ac97_codec.h> |
| 36 | #include <sound/opl3.h> |
| 37 | #include <sound/initval.h> |
| 38 | |
| 39 | |
| 40 | MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>"); |
| 41 | MODULE_DESCRIPTION("Cirrus Logic CS4281"); |
| 42 | MODULE_LICENSE("GPL"); |
| 43 | MODULE_SUPPORTED_DEVICE("{{Cirrus Logic,CS4281}}"); |
| 44 | |
| 45 | static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ |
| 46 | static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ |
| 47 | static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */ |
| 48 | static int dual_codec[SNDRV_CARDS]; /* dual codec */ |
| 49 | |
| 50 | module_param_array(index, int, NULL, 0444); |
| 51 | MODULE_PARM_DESC(index, "Index value for CS4281 soundcard."); |
| 52 | module_param_array(id, charp, NULL, 0444); |
| 53 | MODULE_PARM_DESC(id, "ID string for CS4281 soundcard."); |
| 54 | module_param_array(enable, bool, NULL, 0444); |
| 55 | MODULE_PARM_DESC(enable, "Enable CS4281 soundcard."); |
| 56 | module_param_array(dual_codec, bool, NULL, 0444); |
| 57 | MODULE_PARM_DESC(dual_codec, "Secondary Codec ID (0 = disabled)."); |
| 58 | |
| 59 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 60 | * Direct registers |
| 61 | */ |
| 62 | |
| 63 | #define CS4281_BA0_SIZE 0x1000 |
| 64 | #define CS4281_BA1_SIZE 0x10000 |
| 65 | |
| 66 | /* |
| 67 | * BA0 registers |
| 68 | */ |
| 69 | #define BA0_HISR 0x0000 /* Host Interrupt Status Register */ |
| 70 | #define BA0_HISR_INTENA (1<<31) /* Internal Interrupt Enable Bit */ |
| 71 | #define BA0_HISR_MIDI (1<<22) /* MIDI port interrupt */ |
| 72 | #define BA0_HISR_FIFOI (1<<20) /* FIFO polled interrupt */ |
| 73 | #define BA0_HISR_DMAI (1<<18) /* DMA interrupt (half or end) */ |
| 74 | #define BA0_HISR_FIFO(c) (1<<(12+(c))) /* FIFO channel interrupt */ |
| 75 | #define BA0_HISR_DMA(c) (1<<(8+(c))) /* DMA channel interrupt */ |
| 76 | #define BA0_HISR_GPPI (1<<5) /* General Purpose Input (Primary chip) */ |
| 77 | #define BA0_HISR_GPSI (1<<4) /* General Purpose Input (Secondary chip) */ |
| 78 | #define BA0_HISR_GP3I (1<<3) /* GPIO3 pin Interrupt */ |
| 79 | #define BA0_HISR_GP1I (1<<2) /* GPIO1 pin Interrupt */ |
| 80 | #define BA0_HISR_VUPI (1<<1) /* VOLUP pin Interrupt */ |
| 81 | #define BA0_HISR_VDNI (1<<0) /* VOLDN pin Interrupt */ |
| 82 | |
| 83 | #define BA0_HICR 0x0008 /* Host Interrupt Control Register */ |
| 84 | #define BA0_HICR_CHGM (1<<1) /* INTENA Change Mask */ |
| 85 | #define BA0_HICR_IEV (1<<0) /* INTENA Value */ |
| 86 | #define BA0_HICR_EOI (3<<0) /* End of Interrupt command */ |
| 87 | |
| 88 | #define BA0_HIMR 0x000c /* Host Interrupt Mask Register */ |
| 89 | /* Use same contants as for BA0_HISR */ |
| 90 | |
| 91 | #define BA0_IIER 0x0010 /* ISA Interrupt Enable Register */ |
| 92 | |
| 93 | #define BA0_HDSR0 0x00f0 /* Host DMA Engine 0 Status Register */ |
| 94 | #define BA0_HDSR1 0x00f4 /* Host DMA Engine 1 Status Register */ |
| 95 | #define BA0_HDSR2 0x00f8 /* Host DMA Engine 2 Status Register */ |
| 96 | #define BA0_HDSR3 0x00fc /* Host DMA Engine 3 Status Register */ |
| 97 | |
| 98 | #define BA0_HDSR_CH1P (1<<25) /* Channel 1 Pending */ |
| 99 | #define BA0_HDSR_CH2P (1<<24) /* Channel 2 Pending */ |
| 100 | #define BA0_HDSR_DHTC (1<<17) /* DMA Half Terminal Count */ |
| 101 | #define BA0_HDSR_DTC (1<<16) /* DMA Terminal Count */ |
| 102 | #define BA0_HDSR_DRUN (1<<15) /* DMA Running */ |
| 103 | #define BA0_HDSR_RQ (1<<7) /* Pending Request */ |
| 104 | |
| 105 | #define BA0_DCA0 0x0110 /* Host DMA Engine 0 Current Address */ |
| 106 | #define BA0_DCC0 0x0114 /* Host DMA Engine 0 Current Count */ |
| 107 | #define BA0_DBA0 0x0118 /* Host DMA Engine 0 Base Address */ |
| 108 | #define BA0_DBC0 0x011c /* Host DMA Engine 0 Base Count */ |
| 109 | #define BA0_DCA1 0x0120 /* Host DMA Engine 1 Current Address */ |
| 110 | #define BA0_DCC1 0x0124 /* Host DMA Engine 1 Current Count */ |
| 111 | #define BA0_DBA1 0x0128 /* Host DMA Engine 1 Base Address */ |
| 112 | #define BA0_DBC1 0x012c /* Host DMA Engine 1 Base Count */ |
| 113 | #define BA0_DCA2 0x0130 /* Host DMA Engine 2 Current Address */ |
| 114 | #define BA0_DCC2 0x0134 /* Host DMA Engine 2 Current Count */ |
| 115 | #define BA0_DBA2 0x0138 /* Host DMA Engine 2 Base Address */ |
| 116 | #define BA0_DBC2 0x013c /* Host DMA Engine 2 Base Count */ |
| 117 | #define BA0_DCA3 0x0140 /* Host DMA Engine 3 Current Address */ |
| 118 | #define BA0_DCC3 0x0144 /* Host DMA Engine 3 Current Count */ |
| 119 | #define BA0_DBA3 0x0148 /* Host DMA Engine 3 Base Address */ |
| 120 | #define BA0_DBC3 0x014c /* Host DMA Engine 3 Base Count */ |
| 121 | #define BA0_DMR0 0x0150 /* Host DMA Engine 0 Mode */ |
| 122 | #define BA0_DCR0 0x0154 /* Host DMA Engine 0 Command */ |
| 123 | #define BA0_DMR1 0x0158 /* Host DMA Engine 1 Mode */ |
| 124 | #define BA0_DCR1 0x015c /* Host DMA Engine 1 Command */ |
| 125 | #define BA0_DMR2 0x0160 /* Host DMA Engine 2 Mode */ |
| 126 | #define BA0_DCR2 0x0164 /* Host DMA Engine 2 Command */ |
| 127 | #define BA0_DMR3 0x0168 /* Host DMA Engine 3 Mode */ |
| 128 | #define BA0_DCR3 0x016c /* Host DMA Engine 3 Command */ |
| 129 | |
| 130 | #define BA0_DMR_DMA (1<<29) /* Enable DMA mode */ |
| 131 | #define BA0_DMR_POLL (1<<28) /* Enable poll mode */ |
| 132 | #define BA0_DMR_TBC (1<<25) /* Transfer By Channel */ |
| 133 | #define BA0_DMR_CBC (1<<24) /* Count By Channel (0 = frame resolution) */ |
| 134 | #define BA0_DMR_SWAPC (1<<22) /* Swap Left/Right Channels */ |
| 135 | #define BA0_DMR_SIZE20 (1<<20) /* Sample is 20-bit */ |
| 136 | #define BA0_DMR_USIGN (1<<19) /* Unsigned */ |
| 137 | #define BA0_DMR_BEND (1<<18) /* Big Endian */ |
| 138 | #define BA0_DMR_MONO (1<<17) /* Mono */ |
| 139 | #define BA0_DMR_SIZE8 (1<<16) /* Sample is 8-bit */ |
| 140 | #define BA0_DMR_TYPE_DEMAND (0<<6) |
| 141 | #define BA0_DMR_TYPE_SINGLE (1<<6) |
| 142 | #define BA0_DMR_TYPE_BLOCK (2<<6) |
| 143 | #define BA0_DMR_TYPE_CASCADE (3<<6) /* Not supported */ |
| 144 | #define BA0_DMR_DEC (1<<5) /* Access Increment (0) or Decrement (1) */ |
| 145 | #define BA0_DMR_AUTO (1<<4) /* Auto-Initialize */ |
| 146 | #define BA0_DMR_TR_VERIFY (0<<2) /* Verify Transfer */ |
| 147 | #define BA0_DMR_TR_WRITE (1<<2) /* Write Transfer */ |
| 148 | #define BA0_DMR_TR_READ (2<<2) /* Read Transfer */ |
| 149 | |
| 150 | #define BA0_DCR_HTCIE (1<<17) /* Half Terminal Count Interrupt */ |
| 151 | #define BA0_DCR_TCIE (1<<16) /* Terminal Count Interrupt */ |
| 152 | #define BA0_DCR_MSK (1<<0) /* DMA Mask bit */ |
| 153 | |
| 154 | #define BA0_FCR0 0x0180 /* FIFO Control 0 */ |
| 155 | #define BA0_FCR1 0x0184 /* FIFO Control 1 */ |
| 156 | #define BA0_FCR2 0x0188 /* FIFO Control 2 */ |
| 157 | #define BA0_FCR3 0x018c /* FIFO Control 3 */ |
| 158 | |
| 159 | #define BA0_FCR_FEN (1<<31) /* FIFO Enable bit */ |
| 160 | #define BA0_FCR_DACZ (1<<30) /* DAC Zero */ |
| 161 | #define BA0_FCR_PSH (1<<29) /* Previous Sample Hold */ |
| 162 | #define BA0_FCR_RS(x) (((x)&0x1f)<<24) /* Right Slot Mapping */ |
| 163 | #define BA0_FCR_LS(x) (((x)&0x1f)<<16) /* Left Slot Mapping */ |
| 164 | #define BA0_FCR_SZ(x) (((x)&0x7f)<<8) /* FIFO buffer size (in samples) */ |
| 165 | #define BA0_FCR_OF(x) (((x)&0x7f)<<0) /* FIFO starting offset (in samples) */ |
| 166 | |
| 167 | #define BA0_FPDR0 0x0190 /* FIFO Polled Data 0 */ |
| 168 | #define BA0_FPDR1 0x0194 /* FIFO Polled Data 1 */ |
| 169 | #define BA0_FPDR2 0x0198 /* FIFO Polled Data 2 */ |
| 170 | #define BA0_FPDR3 0x019c /* FIFO Polled Data 3 */ |
| 171 | |
| 172 | #define BA0_FCHS 0x020c /* FIFO Channel Status */ |
| 173 | #define BA0_FCHS_RCO(x) (1<<(7+(((x)&3)<<3))) /* Right Channel Out */ |
| 174 | #define BA0_FCHS_LCO(x) (1<<(6+(((x)&3)<<3))) /* Left Channel Out */ |
| 175 | #define BA0_FCHS_MRP(x) (1<<(5+(((x)&3)<<3))) /* Move Read Pointer */ |
| 176 | #define BA0_FCHS_FE(x) (1<<(4+(((x)&3)<<3))) /* FIFO Empty */ |
| 177 | #define BA0_FCHS_FF(x) (1<<(3+(((x)&3)<<3))) /* FIFO Full */ |
| 178 | #define BA0_FCHS_IOR(x) (1<<(2+(((x)&3)<<3))) /* Internal Overrun Flag */ |
| 179 | #define BA0_FCHS_RCI(x) (1<<(1+(((x)&3)<<3))) /* Right Channel In */ |
| 180 | #define BA0_FCHS_LCI(x) (1<<(0+(((x)&3)<<3))) /* Left Channel In */ |
| 181 | |
| 182 | #define BA0_FSIC0 0x0210 /* FIFO Status and Interrupt Control 0 */ |
| 183 | #define BA0_FSIC1 0x0214 /* FIFO Status and Interrupt Control 1 */ |
| 184 | #define BA0_FSIC2 0x0218 /* FIFO Status and Interrupt Control 2 */ |
| 185 | #define BA0_FSIC3 0x021c /* FIFO Status and Interrupt Control 3 */ |
| 186 | |
| 187 | #define BA0_FSIC_FIC(x) (((x)&0x7f)<<24) /* FIFO Interrupt Count */ |
| 188 | #define BA0_FSIC_FORIE (1<<23) /* FIFO OverRun Interrupt Enable */ |
| 189 | #define BA0_FSIC_FURIE (1<<22) /* FIFO UnderRun Interrupt Enable */ |
| 190 | #define BA0_FSIC_FSCIE (1<<16) /* FIFO Sample Count Interrupt Enable */ |
| 191 | #define BA0_FSIC_FSC(x) (((x)&0x7f)<<8) /* FIFO Sample Count */ |
| 192 | #define BA0_FSIC_FOR (1<<7) /* FIFO OverRun */ |
| 193 | #define BA0_FSIC_FUR (1<<6) /* FIFO UnderRun */ |
| 194 | #define BA0_FSIC_FSCR (1<<0) /* FIFO Sample Count Reached */ |
| 195 | |
| 196 | #define BA0_PMCS 0x0344 /* Power Management Control/Status */ |
| 197 | #define BA0_CWPR 0x03e0 /* Configuration Write Protect */ |
Arnaud Patard | a488e03 | 2005-05-07 18:51:51 +0200 | [diff] [blame] | 198 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 199 | #define BA0_EPPMC 0x03e4 /* Extended PCI Power Management Control */ |
Arnaud Patard | a488e03 | 2005-05-07 18:51:51 +0200 | [diff] [blame] | 200 | #define BA0_EPPMC_FPDN (1<<14) /* Full Power DowN */ |
| 201 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 202 | #define BA0_GPIOR 0x03e8 /* GPIO Pin Interface Register */ |
| 203 | |
| 204 | #define BA0_SPMC 0x03ec /* Serial Port Power Management Control (& ASDIN2 enable) */ |
| 205 | #define BA0_SPMC_GIPPEN (1<<15) /* GP INT Primary PME# Enable */ |
| 206 | #define BA0_SPMC_GISPEN (1<<14) /* GP INT Secondary PME# Enable */ |
| 207 | #define BA0_SPMC_EESPD (1<<9) /* EEPROM Serial Port Disable */ |
| 208 | #define BA0_SPMC_ASDI2E (1<<8) /* ASDIN2 Enable */ |
| 209 | #define BA0_SPMC_ASDO (1<<7) /* Asynchronous ASDOUT Assertion */ |
| 210 | #define BA0_SPMC_WUP2 (1<<3) /* Wakeup for Secondary Input */ |
| 211 | #define BA0_SPMC_WUP1 (1<<2) /* Wakeup for Primary Input */ |
| 212 | #define BA0_SPMC_ASYNC (1<<1) /* Asynchronous ASYNC Assertion */ |
| 213 | #define BA0_SPMC_RSTN (1<<0) /* Reset Not! */ |
| 214 | |
| 215 | #define BA0_CFLR 0x03f0 /* Configuration Load Register (EEPROM or BIOS) */ |
| 216 | #define BA0_CFLR_DEFAULT 0x00000001 /* CFLR must be in AC97 link mode */ |
| 217 | #define BA0_IISR 0x03f4 /* ISA Interrupt Select */ |
| 218 | #define BA0_TMS 0x03f8 /* Test Register */ |
| 219 | #define BA0_SSVID 0x03fc /* Subsystem ID register */ |
| 220 | |
| 221 | #define BA0_CLKCR1 0x0400 /* Clock Control Register 1 */ |
| 222 | #define BA0_CLKCR1_CLKON (1<<25) /* Read Only */ |
| 223 | #define BA0_CLKCR1_DLLRDY (1<<24) /* DLL Ready */ |
| 224 | #define BA0_CLKCR1_DLLOS (1<<6) /* DLL Output Select */ |
| 225 | #define BA0_CLKCR1_SWCE (1<<5) /* Clock Enable */ |
| 226 | #define BA0_CLKCR1_DLLP (1<<4) /* DLL PowerUp */ |
| 227 | #define BA0_CLKCR1_DLLSS (((x)&3)<<3) /* DLL Source Select */ |
| 228 | |
| 229 | #define BA0_FRR 0x0410 /* Feature Reporting Register */ |
| 230 | #define BA0_SLT12O 0x041c /* Slot 12 GPIO Output Register for AC-Link */ |
| 231 | |
| 232 | #define BA0_SERMC 0x0420 /* Serial Port Master Control */ |
| 233 | #define BA0_SERMC_FCRN (1<<27) /* Force Codec Ready Not */ |
| 234 | #define BA0_SERMC_ODSEN2 (1<<25) /* On-Demand Support Enable ASDIN2 */ |
| 235 | #define BA0_SERMC_ODSEN1 (1<<24) /* On-Demand Support Enable ASDIN1 */ |
| 236 | #define BA0_SERMC_SXLB (1<<21) /* ASDIN2 to ASDOUT Loopback */ |
| 237 | #define BA0_SERMC_SLB (1<<20) /* ASDOUT to ASDIN2 Loopback */ |
| 238 | #define BA0_SERMC_LOVF (1<<19) /* Loopback Output Valid Frame bit */ |
| 239 | #define BA0_SERMC_TCID(x) (((x)&3)<<16) /* Target Secondary Codec ID */ |
| 240 | #define BA0_SERMC_PXLB (5<<1) /* Primary Port External Loopback */ |
| 241 | #define BA0_SERMC_PLB (4<<1) /* Primary Port Internal Loopback */ |
| 242 | #define BA0_SERMC_PTC (7<<1) /* Port Timing Configuration */ |
| 243 | #define BA0_SERMC_PTC_AC97 (1<<1) /* AC97 mode */ |
| 244 | #define BA0_SERMC_MSPE (1<<0) /* Master Serial Port Enable */ |
| 245 | |
| 246 | #define BA0_SERC1 0x0428 /* Serial Port Configuration 1 */ |
| 247 | #define BA0_SERC1_SO1F(x) (((x)&7)>>1) /* Primary Output Port Format */ |
| 248 | #define BA0_SERC1_AC97 (1<<1) |
| 249 | #define BA0_SERC1_SO1EN (1<<0) /* Primary Output Port Enable */ |
| 250 | |
| 251 | #define BA0_SERC2 0x042c /* Serial Port Configuration 2 */ |
| 252 | #define BA0_SERC2_SI1F(x) (((x)&7)>>1) /* Primary Input Port Format */ |
| 253 | #define BA0_SERC2_AC97 (1<<1) |
| 254 | #define BA0_SERC2_SI1EN (1<<0) /* Primary Input Port Enable */ |
| 255 | |
| 256 | #define BA0_SLT12M 0x045c /* Slot 12 Monitor Register for Primary AC-Link */ |
| 257 | |
| 258 | #define BA0_ACCTL 0x0460 /* AC'97 Control */ |
| 259 | #define BA0_ACCTL_TC (1<<6) /* Target Codec */ |
| 260 | #define BA0_ACCTL_CRW (1<<4) /* 0=Write, 1=Read Command */ |
| 261 | #define BA0_ACCTL_DCV (1<<3) /* Dynamic Command Valid */ |
| 262 | #define BA0_ACCTL_VFRM (1<<2) /* Valid Frame */ |
| 263 | #define BA0_ACCTL_ESYN (1<<1) /* Enable Sync */ |
| 264 | |
| 265 | #define BA0_ACSTS 0x0464 /* AC'97 Status */ |
| 266 | #define BA0_ACSTS_VSTS (1<<1) /* Valid Status */ |
| 267 | #define BA0_ACSTS_CRDY (1<<0) /* Codec Ready */ |
| 268 | |
| 269 | #define BA0_ACOSV 0x0468 /* AC'97 Output Slot Valid */ |
| 270 | #define BA0_ACOSV_SLV(x) (1<<((x)-3)) |
| 271 | |
| 272 | #define BA0_ACCAD 0x046c /* AC'97 Command Address */ |
| 273 | #define BA0_ACCDA 0x0470 /* AC'97 Command Data */ |
| 274 | |
| 275 | #define BA0_ACISV 0x0474 /* AC'97 Input Slot Valid */ |
| 276 | #define BA0_ACISV_SLV(x) (1<<((x)-3)) |
| 277 | |
| 278 | #define BA0_ACSAD 0x0478 /* AC'97 Status Address */ |
| 279 | #define BA0_ACSDA 0x047c /* AC'97 Status Data */ |
| 280 | #define BA0_JSPT 0x0480 /* Joystick poll/trigger */ |
| 281 | #define BA0_JSCTL 0x0484 /* Joystick control */ |
| 282 | #define BA0_JSC1 0x0488 /* Joystick control */ |
| 283 | #define BA0_JSC2 0x048c /* Joystick control */ |
| 284 | #define BA0_JSIO 0x04a0 |
| 285 | |
| 286 | #define BA0_MIDCR 0x0490 /* MIDI Control */ |
| 287 | #define BA0_MIDCR_MRST (1<<5) /* Reset MIDI Interface */ |
| 288 | #define BA0_MIDCR_MLB (1<<4) /* MIDI Loop Back Enable */ |
| 289 | #define BA0_MIDCR_TIE (1<<3) /* MIDI Transmuit Interrupt Enable */ |
| 290 | #define BA0_MIDCR_RIE (1<<2) /* MIDI Receive Interrupt Enable */ |
| 291 | #define BA0_MIDCR_RXE (1<<1) /* MIDI Receive Enable */ |
| 292 | #define BA0_MIDCR_TXE (1<<0) /* MIDI Transmit Enable */ |
| 293 | |
| 294 | #define BA0_MIDCMD 0x0494 /* MIDI Command (wo) */ |
| 295 | |
| 296 | #define BA0_MIDSR 0x0494 /* MIDI Status (ro) */ |
| 297 | #define BA0_MIDSR_RDA (1<<15) /* Sticky bit (RBE 1->0) */ |
| 298 | #define BA0_MIDSR_TBE (1<<14) /* Sticky bit (TBF 0->1) */ |
| 299 | #define BA0_MIDSR_RBE (1<<7) /* Receive Buffer Empty */ |
| 300 | #define BA0_MIDSR_TBF (1<<6) /* Transmit Buffer Full */ |
| 301 | |
| 302 | #define BA0_MIDWP 0x0498 /* MIDI Write */ |
| 303 | #define BA0_MIDRP 0x049c /* MIDI Read (ro) */ |
| 304 | |
| 305 | #define BA0_AODSD1 0x04a8 /* AC'97 On-Demand Slot Disable for primary link (ro) */ |
| 306 | #define BA0_AODSD1_NDS(x) (1<<((x)-3)) |
| 307 | |
| 308 | #define BA0_AODSD2 0x04ac /* AC'97 On-Demand Slot Disable for secondary link (ro) */ |
| 309 | #define BA0_AODSD2_NDS(x) (1<<((x)-3)) |
| 310 | |
| 311 | #define BA0_CFGI 0x04b0 /* Configure Interface (EEPROM interface) */ |
| 312 | #define BA0_SLT12M2 0x04dc /* Slot 12 Monitor Register 2 for secondary AC-link */ |
| 313 | #define BA0_ACSTS2 0x04e4 /* AC'97 Status Register 2 */ |
| 314 | #define BA0_ACISV2 0x04f4 /* AC'97 Input Slot Valid Register 2 */ |
| 315 | #define BA0_ACSAD2 0x04f8 /* AC'97 Status Address Register 2 */ |
| 316 | #define BA0_ACSDA2 0x04fc /* AC'97 Status Data Register 2 */ |
| 317 | #define BA0_FMSR 0x0730 /* FM Synthesis Status (ro) */ |
| 318 | #define BA0_B0AP 0x0730 /* FM Bank 0 Address Port (wo) */ |
| 319 | #define BA0_FMDP 0x0734 /* FM Data Port */ |
| 320 | #define BA0_B1AP 0x0738 /* FM Bank 1 Address Port */ |
| 321 | #define BA0_B1DP 0x073c /* FM Bank 1 Data Port */ |
| 322 | |
| 323 | #define BA0_SSPM 0x0740 /* Sound System Power Management */ |
| 324 | #define BA0_SSPM_MIXEN (1<<6) /* Playback SRC + FM/Wavetable MIX */ |
| 325 | #define BA0_SSPM_CSRCEN (1<<5) /* Capture Sample Rate Converter Enable */ |
| 326 | #define BA0_SSPM_PSRCEN (1<<4) /* Playback Sample Rate Converter Enable */ |
| 327 | #define BA0_SSPM_JSEN (1<<3) /* Joystick Enable */ |
| 328 | #define BA0_SSPM_ACLEN (1<<2) /* Serial Port Engine and AC-Link Enable */ |
| 329 | #define BA0_SSPM_FMEN (1<<1) /* FM Synthesis Block Enable */ |
| 330 | |
| 331 | #define BA0_DACSR 0x0744 /* DAC Sample Rate - Playback SRC */ |
| 332 | #define BA0_ADCSR 0x0748 /* ADC Sample Rate - Capture SRC */ |
| 333 | |
| 334 | #define BA0_SSCR 0x074c /* Sound System Control Register */ |
| 335 | #define BA0_SSCR_HVS1 (1<<23) /* Hardwave Volume Step (0=1,1=2) */ |
| 336 | #define BA0_SSCR_MVCS (1<<19) /* Master Volume Codec Select */ |
| 337 | #define BA0_SSCR_MVLD (1<<18) /* Master Volume Line Out Disable */ |
| 338 | #define BA0_SSCR_MVAD (1<<17) /* Master Volume Alternate Out Disable */ |
| 339 | #define BA0_SSCR_MVMD (1<<16) /* Master Volume Mono Out Disable */ |
| 340 | #define BA0_SSCR_XLPSRC (1<<8) /* External SRC Loopback Mode */ |
| 341 | #define BA0_SSCR_LPSRC (1<<7) /* SRC Loopback Mode */ |
| 342 | #define BA0_SSCR_CDTX (1<<5) /* CD Transfer Data */ |
| 343 | #define BA0_SSCR_HVC (1<<3) /* Harware Volume Control Enable */ |
| 344 | |
| 345 | #define BA0_FMLVC 0x0754 /* FM Synthesis Left Volume Control */ |
| 346 | #define BA0_FMRVC 0x0758 /* FM Synthesis Right Volume Control */ |
| 347 | #define BA0_SRCSA 0x075c /* SRC Slot Assignments */ |
| 348 | #define BA0_PPLVC 0x0760 /* PCM Playback Left Volume Control */ |
| 349 | #define BA0_PPRVC 0x0764 /* PCM Playback Right Volume Control */ |
| 350 | #define BA0_PASR 0x0768 /* playback sample rate */ |
| 351 | #define BA0_CASR 0x076C /* capture sample rate */ |
| 352 | |
| 353 | /* Source Slot Numbers - Playback */ |
| 354 | #define SRCSLOT_LEFT_PCM_PLAYBACK 0 |
| 355 | #define SRCSLOT_RIGHT_PCM_PLAYBACK 1 |
| 356 | #define SRCSLOT_PHONE_LINE_1_DAC 2 |
| 357 | #define SRCSLOT_CENTER_PCM_PLAYBACK 3 |
| 358 | #define SRCSLOT_LEFT_SURROUND_PCM_PLAYBACK 4 |
| 359 | #define SRCSLOT_RIGHT_SURROUND_PCM_PLAYBACK 5 |
| 360 | #define SRCSLOT_LFE_PCM_PLAYBACK 6 |
| 361 | #define SRCSLOT_PHONE_LINE_2_DAC 7 |
| 362 | #define SRCSLOT_HEADSET_DAC 8 |
| 363 | #define SRCSLOT_LEFT_WT 29 /* invalid for BA0_SRCSA */ |
| 364 | #define SRCSLOT_RIGHT_WT 30 /* invalid for BA0_SRCSA */ |
| 365 | |
| 366 | /* Source Slot Numbers - Capture */ |
| 367 | #define SRCSLOT_LEFT_PCM_RECORD 10 |
| 368 | #define SRCSLOT_RIGHT_PCM_RECORD 11 |
| 369 | #define SRCSLOT_PHONE_LINE_1_ADC 12 |
| 370 | #define SRCSLOT_MIC_ADC 13 |
| 371 | #define SRCSLOT_PHONE_LINE_2_ADC 17 |
| 372 | #define SRCSLOT_HEADSET_ADC 18 |
| 373 | #define SRCSLOT_SECONDARY_LEFT_PCM_RECORD 20 |
| 374 | #define SRCSLOT_SECONDARY_RIGHT_PCM_RECORD 21 |
| 375 | #define SRCSLOT_SECONDARY_PHONE_LINE_1_ADC 22 |
| 376 | #define SRCSLOT_SECONDARY_MIC_ADC 23 |
| 377 | #define SRCSLOT_SECONDARY_PHONE_LINE_2_ADC 27 |
| 378 | #define SRCSLOT_SECONDARY_HEADSET_ADC 28 |
| 379 | |
| 380 | /* Source Slot Numbers - Others */ |
| 381 | #define SRCSLOT_POWER_DOWN 31 |
| 382 | |
| 383 | /* MIDI modes */ |
| 384 | #define CS4281_MODE_OUTPUT (1<<0) |
| 385 | #define CS4281_MODE_INPUT (1<<1) |
| 386 | |
| 387 | /* joystick bits */ |
| 388 | /* Bits for JSPT */ |
| 389 | #define JSPT_CAX 0x00000001 |
| 390 | #define JSPT_CAY 0x00000002 |
| 391 | #define JSPT_CBX 0x00000004 |
| 392 | #define JSPT_CBY 0x00000008 |
| 393 | #define JSPT_BA1 0x00000010 |
| 394 | #define JSPT_BA2 0x00000020 |
| 395 | #define JSPT_BB1 0x00000040 |
| 396 | #define JSPT_BB2 0x00000080 |
| 397 | |
| 398 | /* Bits for JSCTL */ |
| 399 | #define JSCTL_SP_MASK 0x00000003 |
| 400 | #define JSCTL_SP_SLOW 0x00000000 |
| 401 | #define JSCTL_SP_MEDIUM_SLOW 0x00000001 |
| 402 | #define JSCTL_SP_MEDIUM_FAST 0x00000002 |
| 403 | #define JSCTL_SP_FAST 0x00000003 |
| 404 | #define JSCTL_ARE 0x00000004 |
| 405 | |
| 406 | /* Data register pairs masks */ |
| 407 | #define JSC1_Y1V_MASK 0x0000FFFF |
| 408 | #define JSC1_X1V_MASK 0xFFFF0000 |
| 409 | #define JSC1_Y1V_SHIFT 0 |
| 410 | #define JSC1_X1V_SHIFT 16 |
| 411 | #define JSC2_Y2V_MASK 0x0000FFFF |
| 412 | #define JSC2_X2V_MASK 0xFFFF0000 |
| 413 | #define JSC2_Y2V_SHIFT 0 |
| 414 | #define JSC2_X2V_SHIFT 16 |
| 415 | |
| 416 | /* JS GPIO */ |
| 417 | #define JSIO_DAX 0x00000001 |
| 418 | #define JSIO_DAY 0x00000002 |
| 419 | #define JSIO_DBX 0x00000004 |
| 420 | #define JSIO_DBY 0x00000008 |
| 421 | #define JSIO_AXOE 0x00000010 |
| 422 | #define JSIO_AYOE 0x00000020 |
| 423 | #define JSIO_BXOE 0x00000040 |
| 424 | #define JSIO_BYOE 0x00000080 |
| 425 | |
| 426 | /* |
| 427 | * |
| 428 | */ |
| 429 | |
| 430 | typedef struct snd_cs4281 cs4281_t; |
| 431 | typedef struct snd_cs4281_dma cs4281_dma_t; |
| 432 | |
| 433 | struct snd_cs4281_dma { |
| 434 | snd_pcm_substream_t *substream; |
| 435 | unsigned int regDBA; /* offset to DBA register */ |
| 436 | unsigned int regDCA; /* offset to DCA register */ |
| 437 | unsigned int regDBC; /* offset to DBC register */ |
| 438 | unsigned int regDCC; /* offset to DCC register */ |
| 439 | unsigned int regDMR; /* offset to DMR register */ |
| 440 | unsigned int regDCR; /* offset to DCR register */ |
| 441 | unsigned int regHDSR; /* offset to HDSR register */ |
| 442 | unsigned int regFCR; /* offset to FCR register */ |
| 443 | unsigned int regFSIC; /* offset to FSIC register */ |
| 444 | unsigned int valDMR; /* DMA mode */ |
| 445 | unsigned int valDCR; /* DMA command */ |
| 446 | unsigned int valFCR; /* FIFO control */ |
| 447 | unsigned int fifo_offset; /* FIFO offset within BA1 */ |
| 448 | unsigned char left_slot; /* FIFO left slot */ |
| 449 | unsigned char right_slot; /* FIFO right slot */ |
| 450 | int frag; /* period number */ |
| 451 | }; |
| 452 | |
| 453 | #define SUSPEND_REGISTERS 20 |
| 454 | |
| 455 | struct snd_cs4281 { |
| 456 | int irq; |
| 457 | |
| 458 | void __iomem *ba0; /* virtual (accessible) address */ |
| 459 | void __iomem *ba1; /* virtual (accessible) address */ |
| 460 | unsigned long ba0_addr; |
| 461 | unsigned long ba1_addr; |
| 462 | |
| 463 | int dual_codec; |
| 464 | |
| 465 | ac97_bus_t *ac97_bus; |
| 466 | ac97_t *ac97; |
| 467 | ac97_t *ac97_secondary; |
| 468 | |
| 469 | struct pci_dev *pci; |
| 470 | snd_card_t *card; |
| 471 | snd_pcm_t *pcm; |
| 472 | snd_rawmidi_t *rmidi; |
| 473 | snd_rawmidi_substream_t *midi_input; |
| 474 | snd_rawmidi_substream_t *midi_output; |
| 475 | |
| 476 | cs4281_dma_t dma[4]; |
| 477 | |
| 478 | unsigned char src_left_play_slot; |
| 479 | unsigned char src_right_play_slot; |
| 480 | unsigned char src_left_rec_slot; |
| 481 | unsigned char src_right_rec_slot; |
| 482 | |
| 483 | unsigned int spurious_dhtc_irq; |
| 484 | unsigned int spurious_dtc_irq; |
| 485 | |
| 486 | spinlock_t reg_lock; |
| 487 | unsigned int midcr; |
| 488 | unsigned int uartm; |
| 489 | |
| 490 | struct gameport *gameport; |
| 491 | |
| 492 | #ifdef CONFIG_PM |
| 493 | u32 suspend_regs[SUSPEND_REGISTERS]; |
| 494 | #endif |
| 495 | |
| 496 | }; |
| 497 | |
| 498 | static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id, struct pt_regs *regs); |
| 499 | |
| 500 | static struct pci_device_id snd_cs4281_ids[] = { |
| 501 | { 0x1013, 0x6005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* CS4281 */ |
| 502 | { 0, } |
| 503 | }; |
| 504 | |
| 505 | MODULE_DEVICE_TABLE(pci, snd_cs4281_ids); |
| 506 | |
| 507 | /* |
| 508 | * constants |
| 509 | */ |
| 510 | |
| 511 | #define CS4281_FIFO_SIZE 32 |
| 512 | |
| 513 | /* |
| 514 | * common I/O routines |
| 515 | */ |
| 516 | |
| 517 | static void snd_cs4281_delay(unsigned int delay) |
| 518 | { |
| 519 | if (delay > 999) { |
| 520 | unsigned long end_time; |
| 521 | delay = (delay * HZ) / 1000000; |
| 522 | if (delay < 1) |
| 523 | delay = 1; |
| 524 | end_time = jiffies + delay; |
| 525 | do { |
| 526 | set_current_state(TASK_UNINTERRUPTIBLE); |
| 527 | schedule_timeout(1); |
| 528 | } while (time_after_eq(end_time, jiffies)); |
| 529 | } else { |
| 530 | udelay(delay); |
| 531 | } |
| 532 | } |
| 533 | |
Jesper Juhl | 77933d7 | 2005-07-27 11:46:09 -0700 | [diff] [blame] | 534 | static inline void snd_cs4281_delay_long(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 535 | { |
| 536 | set_current_state(TASK_UNINTERRUPTIBLE); |
| 537 | schedule_timeout(1); |
| 538 | } |
| 539 | |
| 540 | static inline void snd_cs4281_pokeBA0(cs4281_t *chip, unsigned long offset, unsigned int val) |
| 541 | { |
| 542 | writel(val, chip->ba0 + offset); |
| 543 | } |
| 544 | |
| 545 | static inline unsigned int snd_cs4281_peekBA0(cs4281_t *chip, unsigned long offset) |
| 546 | { |
| 547 | return readl(chip->ba0 + offset); |
| 548 | } |
| 549 | |
| 550 | static void snd_cs4281_ac97_write(ac97_t *ac97, |
| 551 | unsigned short reg, unsigned short val) |
| 552 | { |
| 553 | /* |
| 554 | * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address |
| 555 | * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 |
| 556 | * 3. Write ACCTL = Control Register = 460h for initiating the write |
| 557 | * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h |
| 558 | * 5. if DCV not cleared, break and return error |
| 559 | */ |
| 560 | cs4281_t *chip = ac97->private_data; |
| 561 | int count; |
| 562 | |
| 563 | /* |
| 564 | * Setup the AC97 control registers on the CS461x to send the |
| 565 | * appropriate command to the AC97 to perform the read. |
| 566 | * ACCAD = Command Address Register = 46Ch |
| 567 | * ACCDA = Command Data Register = 470h |
| 568 | * ACCTL = Control Register = 460h |
| 569 | * set DCV - will clear when process completed |
| 570 | * reset CRW - Write command |
| 571 | * set VFRM - valid frame enabled |
| 572 | * set ESYN - ASYNC generation enabled |
| 573 | * set RSTN - ARST# inactive, AC97 codec not reset |
| 574 | */ |
| 575 | snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg); |
| 576 | snd_cs4281_pokeBA0(chip, BA0_ACCDA, val); |
| 577 | snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_VFRM | |
| 578 | BA0_ACCTL_ESYN | (ac97->num ? BA0_ACCTL_TC : 0)); |
| 579 | for (count = 0; count < 2000; count++) { |
| 580 | /* |
| 581 | * First, we want to wait for a short time. |
| 582 | */ |
| 583 | udelay(10); |
| 584 | /* |
| 585 | * Now, check to see if the write has completed. |
| 586 | * ACCTL = 460h, DCV should be reset by now and 460h = 07h |
| 587 | */ |
| 588 | if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) { |
| 589 | return; |
| 590 | } |
| 591 | } |
| 592 | snd_printk(KERN_ERR "AC'97 write problem, reg = 0x%x, val = 0x%x\n", reg, val); |
| 593 | } |
| 594 | |
| 595 | static unsigned short snd_cs4281_ac97_read(ac97_t *ac97, |
| 596 | unsigned short reg) |
| 597 | { |
| 598 | cs4281_t *chip = ac97->private_data; |
| 599 | int count; |
| 600 | unsigned short result; |
| 601 | // FIXME: volatile is necessary in the following due to a bug of |
| 602 | // some gcc versions |
| 603 | volatile int ac97_num = ((volatile ac97_t *)ac97)->num; |
| 604 | |
| 605 | /* |
| 606 | * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address |
| 607 | * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 |
| 608 | * 3. Write ACCTL = Control Register = 460h for initiating the write |
| 609 | * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h |
| 610 | * 5. if DCV not cleared, break and return error |
| 611 | * 6. Read ACSTS = Status Register = 464h, check VSTS bit |
| 612 | */ |
| 613 | |
| 614 | snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA); |
| 615 | |
| 616 | /* |
| 617 | * Setup the AC97 control registers on the CS461x to send the |
| 618 | * appropriate command to the AC97 to perform the read. |
| 619 | * ACCAD = Command Address Register = 46Ch |
| 620 | * ACCDA = Command Data Register = 470h |
| 621 | * ACCTL = Control Register = 460h |
| 622 | * set DCV - will clear when process completed |
| 623 | * set CRW - Read command |
| 624 | * set VFRM - valid frame enabled |
| 625 | * set ESYN - ASYNC generation enabled |
| 626 | * set RSTN - ARST# inactive, AC97 codec not reset |
| 627 | */ |
| 628 | |
| 629 | snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg); |
| 630 | snd_cs4281_pokeBA0(chip, BA0_ACCDA, 0); |
| 631 | snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_CRW | |
| 632 | BA0_ACCTL_VFRM | BA0_ACCTL_ESYN | |
| 633 | (ac97_num ? BA0_ACCTL_TC : 0)); |
| 634 | |
| 635 | |
| 636 | /* |
| 637 | * Wait for the read to occur. |
| 638 | */ |
| 639 | for (count = 0; count < 500; count++) { |
| 640 | /* |
| 641 | * First, we want to wait for a short time. |
| 642 | */ |
| 643 | udelay(10); |
| 644 | /* |
| 645 | * Now, check to see if the read has completed. |
| 646 | * ACCTL = 460h, DCV should be reset by now and 460h = 17h |
| 647 | */ |
| 648 | if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) |
| 649 | goto __ok1; |
| 650 | } |
| 651 | |
| 652 | snd_printk(KERN_ERR "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg); |
| 653 | result = 0xffff; |
| 654 | goto __end; |
| 655 | |
| 656 | __ok1: |
| 657 | /* |
| 658 | * Wait for the valid status bit to go active. |
| 659 | */ |
| 660 | for (count = 0; count < 100; count++) { |
| 661 | /* |
| 662 | * Read the AC97 status register. |
| 663 | * ACSTS = Status Register = 464h |
| 664 | * VSTS - Valid Status |
| 665 | */ |
| 666 | if (snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSTS2 : BA0_ACSTS) & BA0_ACSTS_VSTS) |
| 667 | goto __ok2; |
| 668 | udelay(10); |
| 669 | } |
| 670 | |
| 671 | snd_printk(KERN_ERR "AC'97 read problem (ACSTS_VSTS), reg = 0x%x\n", reg); |
| 672 | result = 0xffff; |
| 673 | goto __end; |
| 674 | |
| 675 | __ok2: |
| 676 | /* |
| 677 | * Read the data returned from the AC97 register. |
| 678 | * ACSDA = Status Data Register = 474h |
| 679 | */ |
| 680 | result = snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA); |
| 681 | |
| 682 | __end: |
| 683 | return result; |
| 684 | } |
| 685 | |
| 686 | /* |
| 687 | * PCM part |
| 688 | */ |
| 689 | |
| 690 | static int snd_cs4281_trigger(snd_pcm_substream_t *substream, int cmd) |
| 691 | { |
| 692 | cs4281_dma_t *dma = (cs4281_dma_t *)substream->runtime->private_data; |
| 693 | cs4281_t *chip = snd_pcm_substream_chip(substream); |
| 694 | |
| 695 | spin_lock(&chip->reg_lock); |
| 696 | switch (cmd) { |
| 697 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
| 698 | dma->valDCR |= BA0_DCR_MSK; |
| 699 | dma->valFCR |= BA0_FCR_FEN; |
| 700 | break; |
| 701 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
| 702 | dma->valDCR &= ~BA0_DCR_MSK; |
| 703 | dma->valFCR &= ~BA0_FCR_FEN; |
| 704 | break; |
| 705 | case SNDRV_PCM_TRIGGER_START: |
| 706 | case SNDRV_PCM_TRIGGER_RESUME: |
| 707 | snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR & ~BA0_DMR_DMA); |
| 708 | dma->valDMR |= BA0_DMR_DMA; |
| 709 | dma->valDCR &= ~BA0_DCR_MSK; |
| 710 | dma->valFCR |= BA0_FCR_FEN; |
| 711 | break; |
| 712 | case SNDRV_PCM_TRIGGER_STOP: |
| 713 | case SNDRV_PCM_TRIGGER_SUSPEND: |
| 714 | dma->valDMR &= ~(BA0_DMR_DMA|BA0_DMR_POLL); |
| 715 | dma->valDCR |= BA0_DCR_MSK; |
| 716 | dma->valFCR &= ~BA0_FCR_FEN; |
| 717 | /* Leave wave playback FIFO enabled for FM */ |
| 718 | if (dma->regFCR != BA0_FCR0) |
| 719 | dma->valFCR &= ~BA0_FCR_FEN; |
| 720 | break; |
| 721 | default: |
| 722 | spin_unlock(&chip->reg_lock); |
| 723 | return -EINVAL; |
| 724 | } |
| 725 | snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR); |
| 726 | snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR); |
| 727 | snd_cs4281_pokeBA0(chip, dma->regDCR, dma->valDCR); |
| 728 | spin_unlock(&chip->reg_lock); |
| 729 | return 0; |
| 730 | } |
| 731 | |
| 732 | static unsigned int snd_cs4281_rate(unsigned int rate, unsigned int *real_rate) |
| 733 | { |
| 734 | unsigned int val = ~0; |
| 735 | |
| 736 | if (real_rate) |
| 737 | *real_rate = rate; |
| 738 | /* special "hardcoded" rates */ |
| 739 | switch (rate) { |
| 740 | case 8000: return 5; |
| 741 | case 11025: return 4; |
| 742 | case 16000: return 3; |
| 743 | case 22050: return 2; |
| 744 | case 44100: return 1; |
| 745 | case 48000: return 0; |
| 746 | default: |
| 747 | goto __variable; |
| 748 | } |
| 749 | __variable: |
| 750 | val = 1536000 / rate; |
| 751 | if (real_rate) |
| 752 | *real_rate = 1536000 / val; |
| 753 | return val; |
| 754 | } |
| 755 | |
| 756 | static void snd_cs4281_mode(cs4281_t *chip, cs4281_dma_t *dma, snd_pcm_runtime_t *runtime, int capture, int src) |
| 757 | { |
| 758 | int rec_mono; |
| 759 | |
| 760 | dma->valDMR = BA0_DMR_TYPE_SINGLE | BA0_DMR_AUTO | |
| 761 | (capture ? BA0_DMR_TR_WRITE : BA0_DMR_TR_READ); |
| 762 | if (runtime->channels == 1) |
| 763 | dma->valDMR |= BA0_DMR_MONO; |
| 764 | if (snd_pcm_format_unsigned(runtime->format) > 0) |
| 765 | dma->valDMR |= BA0_DMR_USIGN; |
| 766 | if (snd_pcm_format_big_endian(runtime->format) > 0) |
| 767 | dma->valDMR |= BA0_DMR_BEND; |
| 768 | switch (snd_pcm_format_width(runtime->format)) { |
| 769 | case 8: dma->valDMR |= BA0_DMR_SIZE8; |
| 770 | if (runtime->channels == 1) |
| 771 | dma->valDMR |= BA0_DMR_SWAPC; |
| 772 | break; |
| 773 | case 32: dma->valDMR |= BA0_DMR_SIZE20; break; |
| 774 | } |
| 775 | dma->frag = 0; /* for workaround */ |
| 776 | dma->valDCR = BA0_DCR_TCIE | BA0_DCR_MSK; |
| 777 | if (runtime->buffer_size != runtime->period_size) |
| 778 | dma->valDCR |= BA0_DCR_HTCIE; |
| 779 | /* Initialize DMA */ |
| 780 | snd_cs4281_pokeBA0(chip, dma->regDBA, runtime->dma_addr); |
| 781 | snd_cs4281_pokeBA0(chip, dma->regDBC, runtime->buffer_size - 1); |
| 782 | rec_mono = (chip->dma[1].valDMR & BA0_DMR_MONO) == BA0_DMR_MONO; |
| 783 | snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) | |
| 784 | (chip->src_right_play_slot << 8) | |
| 785 | (chip->src_left_rec_slot << 16) | |
| 786 | ((rec_mono ? 31 : chip->src_right_rec_slot) << 24)); |
| 787 | if (!src) |
| 788 | goto __skip_src; |
| 789 | if (!capture) { |
| 790 | if (dma->left_slot == chip->src_left_play_slot) { |
| 791 | unsigned int val = snd_cs4281_rate(runtime->rate, NULL); |
| 792 | snd_assert(dma->right_slot == chip->src_right_play_slot, ); |
| 793 | snd_cs4281_pokeBA0(chip, BA0_DACSR, val); |
| 794 | } |
| 795 | } else { |
| 796 | if (dma->left_slot == chip->src_left_rec_slot) { |
| 797 | unsigned int val = snd_cs4281_rate(runtime->rate, NULL); |
| 798 | snd_assert(dma->right_slot == chip->src_right_rec_slot, ); |
| 799 | snd_cs4281_pokeBA0(chip, BA0_ADCSR, val); |
| 800 | } |
| 801 | } |
| 802 | __skip_src: |
| 803 | /* Deactivate wave playback FIFO before changing slot assignments */ |
| 804 | if (dma->regFCR == BA0_FCR0) |
| 805 | snd_cs4281_pokeBA0(chip, dma->regFCR, snd_cs4281_peekBA0(chip, dma->regFCR) & ~BA0_FCR_FEN); |
| 806 | /* Initialize FIFO */ |
| 807 | dma->valFCR = BA0_FCR_LS(dma->left_slot) | |
| 808 | BA0_FCR_RS(capture && (dma->valDMR & BA0_DMR_MONO) ? 31 : dma->right_slot) | |
| 809 | BA0_FCR_SZ(CS4281_FIFO_SIZE) | |
| 810 | BA0_FCR_OF(dma->fifo_offset); |
| 811 | snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | (capture ? BA0_FCR_PSH : 0)); |
| 812 | /* Activate FIFO again for FM playback */ |
| 813 | if (dma->regFCR == BA0_FCR0) |
| 814 | snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | BA0_FCR_FEN); |
| 815 | /* Clear FIFO Status and Interrupt Control Register */ |
| 816 | snd_cs4281_pokeBA0(chip, dma->regFSIC, 0); |
| 817 | } |
| 818 | |
| 819 | static int snd_cs4281_hw_params(snd_pcm_substream_t * substream, |
| 820 | snd_pcm_hw_params_t * hw_params) |
| 821 | { |
| 822 | return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); |
| 823 | } |
| 824 | |
| 825 | static int snd_cs4281_hw_free(snd_pcm_substream_t * substream) |
| 826 | { |
| 827 | return snd_pcm_lib_free_pages(substream); |
| 828 | } |
| 829 | |
| 830 | static int snd_cs4281_playback_prepare(snd_pcm_substream_t * substream) |
| 831 | { |
| 832 | snd_pcm_runtime_t *runtime = substream->runtime; |
| 833 | cs4281_dma_t *dma = (cs4281_dma_t *)runtime->private_data; |
| 834 | cs4281_t *chip = snd_pcm_substream_chip(substream); |
| 835 | |
| 836 | spin_lock_irq(&chip->reg_lock); |
| 837 | snd_cs4281_mode(chip, dma, runtime, 0, 1); |
| 838 | spin_unlock_irq(&chip->reg_lock); |
| 839 | return 0; |
| 840 | } |
| 841 | |
| 842 | static int snd_cs4281_capture_prepare(snd_pcm_substream_t * substream) |
| 843 | { |
| 844 | snd_pcm_runtime_t *runtime = substream->runtime; |
| 845 | cs4281_dma_t *dma = (cs4281_dma_t *)runtime->private_data; |
| 846 | cs4281_t *chip = snd_pcm_substream_chip(substream); |
| 847 | |
| 848 | spin_lock_irq(&chip->reg_lock); |
| 849 | snd_cs4281_mode(chip, dma, runtime, 1, 1); |
| 850 | spin_unlock_irq(&chip->reg_lock); |
| 851 | return 0; |
| 852 | } |
| 853 | |
| 854 | static snd_pcm_uframes_t snd_cs4281_pointer(snd_pcm_substream_t * substream) |
| 855 | { |
| 856 | snd_pcm_runtime_t *runtime = substream->runtime; |
| 857 | cs4281_dma_t *dma = (cs4281_dma_t *)runtime->private_data; |
| 858 | cs4281_t *chip = snd_pcm_substream_chip(substream); |
| 859 | |
| 860 | // printk("DCC = 0x%x, buffer_size = 0x%x, jiffies = %li\n", snd_cs4281_peekBA0(chip, dma->regDCC), runtime->buffer_size, jiffies); |
| 861 | return runtime->buffer_size - |
| 862 | snd_cs4281_peekBA0(chip, dma->regDCC) - 1; |
| 863 | } |
| 864 | |
| 865 | static snd_pcm_hardware_t snd_cs4281_playback = |
| 866 | { |
| 867 | .info = (SNDRV_PCM_INFO_MMAP | |
| 868 | SNDRV_PCM_INFO_INTERLEAVED | |
| 869 | SNDRV_PCM_INFO_MMAP_VALID | |
| 870 | SNDRV_PCM_INFO_PAUSE | |
| 871 | SNDRV_PCM_INFO_RESUME | |
| 872 | SNDRV_PCM_INFO_SYNC_START), |
| 873 | .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 | |
| 874 | SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE | |
| 875 | SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE | |
| 876 | SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE | |
| 877 | SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE, |
| 878 | .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, |
| 879 | .rate_min = 4000, |
| 880 | .rate_max = 48000, |
| 881 | .channels_min = 1, |
| 882 | .channels_max = 2, |
| 883 | .buffer_bytes_max = (512*1024), |
| 884 | .period_bytes_min = 64, |
| 885 | .period_bytes_max = (512*1024), |
| 886 | .periods_min = 1, |
| 887 | .periods_max = 2, |
| 888 | .fifo_size = CS4281_FIFO_SIZE, |
| 889 | }; |
| 890 | |
| 891 | static snd_pcm_hardware_t snd_cs4281_capture = |
| 892 | { |
| 893 | .info = (SNDRV_PCM_INFO_MMAP | |
| 894 | SNDRV_PCM_INFO_INTERLEAVED | |
| 895 | SNDRV_PCM_INFO_MMAP_VALID | |
| 896 | SNDRV_PCM_INFO_PAUSE | |
| 897 | SNDRV_PCM_INFO_RESUME | |
| 898 | SNDRV_PCM_INFO_SYNC_START), |
| 899 | .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 | |
| 900 | SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE | |
| 901 | SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE | |
| 902 | SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE | |
| 903 | SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE, |
| 904 | .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, |
| 905 | .rate_min = 4000, |
| 906 | .rate_max = 48000, |
| 907 | .channels_min = 1, |
| 908 | .channels_max = 2, |
| 909 | .buffer_bytes_max = (512*1024), |
| 910 | .period_bytes_min = 64, |
| 911 | .period_bytes_max = (512*1024), |
| 912 | .periods_min = 1, |
| 913 | .periods_max = 2, |
| 914 | .fifo_size = CS4281_FIFO_SIZE, |
| 915 | }; |
| 916 | |
| 917 | static int snd_cs4281_playback_open(snd_pcm_substream_t * substream) |
| 918 | { |
| 919 | cs4281_t *chip = snd_pcm_substream_chip(substream); |
| 920 | snd_pcm_runtime_t *runtime = substream->runtime; |
| 921 | cs4281_dma_t *dma; |
| 922 | |
| 923 | dma = &chip->dma[0]; |
| 924 | dma->substream = substream; |
| 925 | dma->left_slot = 0; |
| 926 | dma->right_slot = 1; |
| 927 | runtime->private_data = dma; |
| 928 | runtime->hw = snd_cs4281_playback; |
| 929 | snd_pcm_set_sync(substream); |
| 930 | /* should be detected from the AC'97 layer, but it seems |
| 931 | that although CS4297A rev B reports 18-bit ADC resolution, |
| 932 | samples are 20-bit */ |
| 933 | snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20); |
| 934 | return 0; |
| 935 | } |
| 936 | |
| 937 | static int snd_cs4281_capture_open(snd_pcm_substream_t * substream) |
| 938 | { |
| 939 | cs4281_t *chip = snd_pcm_substream_chip(substream); |
| 940 | snd_pcm_runtime_t *runtime = substream->runtime; |
| 941 | cs4281_dma_t *dma; |
| 942 | |
| 943 | dma = &chip->dma[1]; |
| 944 | dma->substream = substream; |
| 945 | dma->left_slot = 10; |
| 946 | dma->right_slot = 11; |
| 947 | runtime->private_data = dma; |
| 948 | runtime->hw = snd_cs4281_capture; |
| 949 | snd_pcm_set_sync(substream); |
| 950 | /* should be detected from the AC'97 layer, but it seems |
| 951 | that although CS4297A rev B reports 18-bit ADC resolution, |
| 952 | samples are 20-bit */ |
| 953 | snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20); |
| 954 | return 0; |
| 955 | } |
| 956 | |
| 957 | static int snd_cs4281_playback_close(snd_pcm_substream_t * substream) |
| 958 | { |
| 959 | cs4281_dma_t *dma = (cs4281_dma_t *)substream->runtime->private_data; |
| 960 | |
| 961 | dma->substream = NULL; |
| 962 | return 0; |
| 963 | } |
| 964 | |
| 965 | static int snd_cs4281_capture_close(snd_pcm_substream_t * substream) |
| 966 | { |
| 967 | cs4281_dma_t *dma = (cs4281_dma_t *)substream->runtime->private_data; |
| 968 | |
| 969 | dma->substream = NULL; |
| 970 | return 0; |
| 971 | } |
| 972 | |
| 973 | static snd_pcm_ops_t snd_cs4281_playback_ops = { |
| 974 | .open = snd_cs4281_playback_open, |
| 975 | .close = snd_cs4281_playback_close, |
| 976 | .ioctl = snd_pcm_lib_ioctl, |
| 977 | .hw_params = snd_cs4281_hw_params, |
| 978 | .hw_free = snd_cs4281_hw_free, |
| 979 | .prepare = snd_cs4281_playback_prepare, |
| 980 | .trigger = snd_cs4281_trigger, |
| 981 | .pointer = snd_cs4281_pointer, |
| 982 | }; |
| 983 | |
| 984 | static snd_pcm_ops_t snd_cs4281_capture_ops = { |
| 985 | .open = snd_cs4281_capture_open, |
| 986 | .close = snd_cs4281_capture_close, |
| 987 | .ioctl = snd_pcm_lib_ioctl, |
| 988 | .hw_params = snd_cs4281_hw_params, |
| 989 | .hw_free = snd_cs4281_hw_free, |
| 990 | .prepare = snd_cs4281_capture_prepare, |
| 991 | .trigger = snd_cs4281_trigger, |
| 992 | .pointer = snd_cs4281_pointer, |
| 993 | }; |
| 994 | |
| 995 | static void snd_cs4281_pcm_free(snd_pcm_t *pcm) |
| 996 | { |
| 997 | cs4281_t *chip = pcm->private_data; |
| 998 | chip->pcm = NULL; |
| 999 | snd_pcm_lib_preallocate_free_for_all(pcm); |
| 1000 | } |
| 1001 | |
| 1002 | static int __devinit snd_cs4281_pcm(cs4281_t * chip, int device, snd_pcm_t ** rpcm) |
| 1003 | { |
| 1004 | snd_pcm_t *pcm; |
| 1005 | int err; |
| 1006 | |
| 1007 | if (rpcm) |
| 1008 | *rpcm = NULL; |
| 1009 | err = snd_pcm_new(chip->card, "CS4281", device, 1, 1, &pcm); |
| 1010 | if (err < 0) |
| 1011 | return err; |
| 1012 | |
| 1013 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4281_playback_ops); |
| 1014 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4281_capture_ops); |
| 1015 | |
| 1016 | pcm->private_data = chip; |
| 1017 | pcm->private_free = snd_cs4281_pcm_free; |
| 1018 | pcm->info_flags = 0; |
| 1019 | strcpy(pcm->name, "CS4281"); |
| 1020 | chip->pcm = pcm; |
| 1021 | |
| 1022 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, |
| 1023 | snd_dma_pci_data(chip->pci), 64*1024, 512*1024); |
| 1024 | |
| 1025 | if (rpcm) |
| 1026 | *rpcm = pcm; |
| 1027 | return 0; |
| 1028 | } |
| 1029 | |
| 1030 | /* |
| 1031 | * Mixer section |
| 1032 | */ |
| 1033 | |
| 1034 | #define CS_VOL_MASK 0x1f |
| 1035 | |
| 1036 | static int snd_cs4281_info_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo) |
| 1037 | { |
| 1038 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; |
| 1039 | uinfo->count = 2; |
| 1040 | uinfo->value.integer.min = 0; |
| 1041 | uinfo->value.integer.max = CS_VOL_MASK; |
| 1042 | return 0; |
| 1043 | } |
| 1044 | |
| 1045 | static int snd_cs4281_get_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) |
| 1046 | { |
| 1047 | cs4281_t *chip = snd_kcontrol_chip(kcontrol); |
| 1048 | int regL = (kcontrol->private_value >> 16) & 0xffff; |
| 1049 | int regR = kcontrol->private_value & 0xffff; |
| 1050 | int volL, volR; |
| 1051 | |
| 1052 | volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK); |
| 1053 | volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK); |
| 1054 | |
| 1055 | ucontrol->value.integer.value[0] = volL; |
| 1056 | ucontrol->value.integer.value[1] = volR; |
| 1057 | return 0; |
| 1058 | } |
| 1059 | |
| 1060 | static int snd_cs4281_put_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) |
| 1061 | { |
| 1062 | cs4281_t *chip = snd_kcontrol_chip(kcontrol); |
| 1063 | int change = 0; |
| 1064 | int regL = (kcontrol->private_value >> 16) & 0xffff; |
| 1065 | int regR = kcontrol->private_value & 0xffff; |
| 1066 | int volL, volR; |
| 1067 | |
| 1068 | volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK); |
| 1069 | volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK); |
| 1070 | |
| 1071 | if (ucontrol->value.integer.value[0] != volL) { |
| 1072 | volL = CS_VOL_MASK - (ucontrol->value.integer.value[0] & CS_VOL_MASK); |
| 1073 | snd_cs4281_pokeBA0(chip, regL, volL); |
| 1074 | change = 1; |
| 1075 | } |
| 1076 | if (ucontrol->value.integer.value[0] != volL) { |
| 1077 | volR = CS_VOL_MASK - (ucontrol->value.integer.value[1] & CS_VOL_MASK); |
| 1078 | snd_cs4281_pokeBA0(chip, regR, volR); |
| 1079 | change = 1; |
| 1080 | } |
| 1081 | return change; |
| 1082 | } |
| 1083 | |
| 1084 | static snd_kcontrol_new_t snd_cs4281_fm_vol = |
| 1085 | { |
| 1086 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, |
| 1087 | .name = "Synth Playback Volume", |
| 1088 | .info = snd_cs4281_info_volume, |
| 1089 | .get = snd_cs4281_get_volume, |
| 1090 | .put = snd_cs4281_put_volume, |
| 1091 | .private_value = ((BA0_FMLVC << 16) | BA0_FMRVC), |
| 1092 | }; |
| 1093 | |
| 1094 | static snd_kcontrol_new_t snd_cs4281_pcm_vol = |
| 1095 | { |
| 1096 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, |
| 1097 | .name = "PCM Stream Playback Volume", |
| 1098 | .info = snd_cs4281_info_volume, |
| 1099 | .get = snd_cs4281_get_volume, |
| 1100 | .put = snd_cs4281_put_volume, |
| 1101 | .private_value = ((BA0_PPLVC << 16) | BA0_PPRVC), |
| 1102 | }; |
| 1103 | |
| 1104 | static void snd_cs4281_mixer_free_ac97_bus(ac97_bus_t *bus) |
| 1105 | { |
| 1106 | cs4281_t *chip = bus->private_data; |
| 1107 | chip->ac97_bus = NULL; |
| 1108 | } |
| 1109 | |
| 1110 | static void snd_cs4281_mixer_free_ac97(ac97_t *ac97) |
| 1111 | { |
| 1112 | cs4281_t *chip = ac97->private_data; |
| 1113 | if (ac97->num) |
| 1114 | chip->ac97_secondary = NULL; |
| 1115 | else |
| 1116 | chip->ac97 = NULL; |
| 1117 | } |
| 1118 | |
| 1119 | static int __devinit snd_cs4281_mixer(cs4281_t * chip) |
| 1120 | { |
| 1121 | snd_card_t *card = chip->card; |
| 1122 | ac97_template_t ac97; |
| 1123 | int err; |
| 1124 | static ac97_bus_ops_t ops = { |
| 1125 | .write = snd_cs4281_ac97_write, |
| 1126 | .read = snd_cs4281_ac97_read, |
| 1127 | }; |
| 1128 | |
| 1129 | if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0) |
| 1130 | return err; |
| 1131 | chip->ac97_bus->private_free = snd_cs4281_mixer_free_ac97_bus; |
| 1132 | |
| 1133 | memset(&ac97, 0, sizeof(ac97)); |
| 1134 | ac97.private_data = chip; |
| 1135 | ac97.private_free = snd_cs4281_mixer_free_ac97; |
| 1136 | if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0) |
| 1137 | return err; |
| 1138 | if (chip->dual_codec) { |
| 1139 | ac97.num = 1; |
| 1140 | if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_secondary)) < 0) |
| 1141 | return err; |
| 1142 | } |
| 1143 | if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_fm_vol, chip))) < 0) |
| 1144 | return err; |
| 1145 | if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_pcm_vol, chip))) < 0) |
| 1146 | return err; |
| 1147 | return 0; |
| 1148 | } |
| 1149 | |
| 1150 | |
| 1151 | /* |
| 1152 | * proc interface |
| 1153 | */ |
| 1154 | |
| 1155 | static void snd_cs4281_proc_read(snd_info_entry_t *entry, |
| 1156 | snd_info_buffer_t * buffer) |
| 1157 | { |
| 1158 | cs4281_t *chip = entry->private_data; |
| 1159 | |
| 1160 | snd_iprintf(buffer, "Cirrus Logic CS4281\n\n"); |
| 1161 | snd_iprintf(buffer, "Spurious half IRQs : %u\n", chip->spurious_dhtc_irq); |
| 1162 | snd_iprintf(buffer, "Spurious end IRQs : %u\n", chip->spurious_dtc_irq); |
| 1163 | } |
| 1164 | |
| 1165 | static long snd_cs4281_BA0_read(snd_info_entry_t *entry, void *file_private_data, |
| 1166 | struct file *file, char __user *buf, |
| 1167 | unsigned long count, unsigned long pos) |
| 1168 | { |
| 1169 | long size; |
| 1170 | cs4281_t *chip = entry->private_data; |
| 1171 | |
| 1172 | size = count; |
| 1173 | if (pos + size > CS4281_BA0_SIZE) |
| 1174 | size = (long)CS4281_BA0_SIZE - pos; |
| 1175 | if (size > 0) { |
| 1176 | if (copy_to_user_fromio(buf, chip->ba0 + pos, size)) |
| 1177 | return -EFAULT; |
| 1178 | } |
| 1179 | return size; |
| 1180 | } |
| 1181 | |
| 1182 | static long snd_cs4281_BA1_read(snd_info_entry_t *entry, void *file_private_data, |
| 1183 | struct file *file, char __user *buf, |
| 1184 | unsigned long count, unsigned long pos) |
| 1185 | { |
| 1186 | long size; |
| 1187 | cs4281_t *chip = entry->private_data; |
| 1188 | |
| 1189 | size = count; |
| 1190 | if (pos + size > CS4281_BA1_SIZE) |
| 1191 | size = (long)CS4281_BA1_SIZE - pos; |
| 1192 | if (size > 0) { |
| 1193 | if (copy_to_user_fromio(buf, chip->ba1 + pos, size)) |
| 1194 | return -EFAULT; |
| 1195 | } |
| 1196 | return size; |
| 1197 | } |
| 1198 | |
| 1199 | static struct snd_info_entry_ops snd_cs4281_proc_ops_BA0 = { |
| 1200 | .read = snd_cs4281_BA0_read, |
| 1201 | }; |
| 1202 | |
| 1203 | static struct snd_info_entry_ops snd_cs4281_proc_ops_BA1 = { |
| 1204 | .read = snd_cs4281_BA1_read, |
| 1205 | }; |
| 1206 | |
| 1207 | static void __devinit snd_cs4281_proc_init(cs4281_t * chip) |
| 1208 | { |
| 1209 | snd_info_entry_t *entry; |
| 1210 | |
| 1211 | if (! snd_card_proc_new(chip->card, "cs4281", &entry)) |
| 1212 | snd_info_set_text_ops(entry, chip, 1024, snd_cs4281_proc_read); |
| 1213 | if (! snd_card_proc_new(chip->card, "cs4281_BA0", &entry)) { |
| 1214 | entry->content = SNDRV_INFO_CONTENT_DATA; |
| 1215 | entry->private_data = chip; |
| 1216 | entry->c.ops = &snd_cs4281_proc_ops_BA0; |
| 1217 | entry->size = CS4281_BA0_SIZE; |
| 1218 | } |
| 1219 | if (! snd_card_proc_new(chip->card, "cs4281_BA1", &entry)) { |
| 1220 | entry->content = SNDRV_INFO_CONTENT_DATA; |
| 1221 | entry->private_data = chip; |
| 1222 | entry->c.ops = &snd_cs4281_proc_ops_BA1; |
| 1223 | entry->size = CS4281_BA1_SIZE; |
| 1224 | } |
| 1225 | } |
| 1226 | |
| 1227 | /* |
| 1228 | * joystick support |
| 1229 | */ |
| 1230 | |
| 1231 | #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE)) |
| 1232 | |
| 1233 | static void snd_cs4281_gameport_trigger(struct gameport *gameport) |
| 1234 | { |
| 1235 | cs4281_t *chip = gameport_get_port_data(gameport); |
| 1236 | |
| 1237 | snd_assert(chip, return); |
| 1238 | snd_cs4281_pokeBA0(chip, BA0_JSPT, 0xff); |
| 1239 | } |
| 1240 | |
| 1241 | static unsigned char snd_cs4281_gameport_read(struct gameport *gameport) |
| 1242 | { |
| 1243 | cs4281_t *chip = gameport_get_port_data(gameport); |
| 1244 | |
| 1245 | snd_assert(chip, return 0); |
| 1246 | return snd_cs4281_peekBA0(chip, BA0_JSPT); |
| 1247 | } |
| 1248 | |
| 1249 | #ifdef COOKED_MODE |
| 1250 | static int snd_cs4281_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons) |
| 1251 | { |
| 1252 | cs4281_t *chip = gameport_get_port_data(gameport); |
| 1253 | unsigned js1, js2, jst; |
| 1254 | |
| 1255 | snd_assert(chip, return 0); |
| 1256 | |
| 1257 | js1 = snd_cs4281_peekBA0(chip, BA0_JSC1); |
| 1258 | js2 = snd_cs4281_peekBA0(chip, BA0_JSC2); |
| 1259 | jst = snd_cs4281_peekBA0(chip, BA0_JSPT); |
| 1260 | |
| 1261 | *buttons = (~jst >> 4) & 0x0F; |
| 1262 | |
| 1263 | axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF; |
| 1264 | axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF; |
| 1265 | axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF; |
| 1266 | axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF; |
| 1267 | |
| 1268 | for (jst = 0; jst < 4; ++jst) |
| 1269 | if (axes[jst] == 0xFFFF) axes[jst] = -1; |
| 1270 | return 0; |
| 1271 | } |
| 1272 | #else |
| 1273 | #define snd_cs4281_gameport_cooked_read NULL |
| 1274 | #endif |
| 1275 | |
| 1276 | static int snd_cs4281_gameport_open(struct gameport *gameport, int mode) |
| 1277 | { |
| 1278 | switch (mode) { |
| 1279 | #ifdef COOKED_MODE |
| 1280 | case GAMEPORT_MODE_COOKED: |
| 1281 | return 0; |
| 1282 | #endif |
| 1283 | case GAMEPORT_MODE_RAW: |
| 1284 | return 0; |
| 1285 | default: |
| 1286 | return -1; |
| 1287 | } |
| 1288 | return 0; |
| 1289 | } |
| 1290 | |
| 1291 | static int __devinit snd_cs4281_create_gameport(cs4281_t *chip) |
| 1292 | { |
| 1293 | struct gameport *gp; |
| 1294 | |
| 1295 | chip->gameport = gp = gameport_allocate_port(); |
| 1296 | if (!gp) { |
| 1297 | printk(KERN_ERR "cs4281: cannot allocate memory for gameport\n"); |
| 1298 | return -ENOMEM; |
| 1299 | } |
| 1300 | |
| 1301 | gameport_set_name(gp, "CS4281 Gameport"); |
| 1302 | gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci)); |
| 1303 | gameport_set_dev_parent(gp, &chip->pci->dev); |
| 1304 | gp->open = snd_cs4281_gameport_open; |
| 1305 | gp->read = snd_cs4281_gameport_read; |
| 1306 | gp->trigger = snd_cs4281_gameport_trigger; |
| 1307 | gp->cooked_read = snd_cs4281_gameport_cooked_read; |
| 1308 | gameport_set_port_data(gp, chip); |
| 1309 | |
| 1310 | snd_cs4281_pokeBA0(chip, BA0_JSIO, 0xFF); // ? |
| 1311 | snd_cs4281_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW); |
| 1312 | |
| 1313 | gameport_register_port(gp); |
| 1314 | |
| 1315 | return 0; |
| 1316 | } |
| 1317 | |
| 1318 | static void snd_cs4281_free_gameport(cs4281_t *chip) |
| 1319 | { |
| 1320 | if (chip->gameport) { |
| 1321 | gameport_unregister_port(chip->gameport); |
| 1322 | chip->gameport = NULL; |
| 1323 | } |
| 1324 | } |
| 1325 | #else |
| 1326 | static inline int snd_cs4281_create_gameport(cs4281_t *chip) { return -ENOSYS; } |
| 1327 | static inline void snd_cs4281_free_gameport(cs4281_t *chip) { } |
| 1328 | #endif /* CONFIG_GAMEPORT || (MODULE && CONFIG_GAMEPORT_MODULE) */ |
| 1329 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1330 | static int snd_cs4281_free(cs4281_t *chip) |
| 1331 | { |
| 1332 | snd_cs4281_free_gameport(chip); |
| 1333 | |
| 1334 | if (chip->irq >= 0) |
| 1335 | synchronize_irq(chip->irq); |
| 1336 | |
| 1337 | /* Mask interrupts */ |
| 1338 | snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff); |
| 1339 | /* Stop the DLL Clock logic. */ |
| 1340 | snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0); |
| 1341 | /* Sound System Power Management - Turn Everything OFF */ |
| 1342 | snd_cs4281_pokeBA0(chip, BA0_SSPM, 0); |
| 1343 | /* PCI interface - D3 state */ |
| 1344 | pci_set_power_state(chip->pci, 3); |
| 1345 | |
| 1346 | if (chip->irq >= 0) |
| 1347 | free_irq(chip->irq, (void *)chip); |
| 1348 | if (chip->ba0) |
| 1349 | iounmap(chip->ba0); |
| 1350 | if (chip->ba1) |
| 1351 | iounmap(chip->ba1); |
| 1352 | pci_release_regions(chip->pci); |
| 1353 | pci_disable_device(chip->pci); |
| 1354 | |
| 1355 | kfree(chip); |
| 1356 | return 0; |
| 1357 | } |
| 1358 | |
| 1359 | static int snd_cs4281_dev_free(snd_device_t *device) |
| 1360 | { |
| 1361 | cs4281_t *chip = device->device_data; |
| 1362 | return snd_cs4281_free(chip); |
| 1363 | } |
| 1364 | |
| 1365 | static int snd_cs4281_chip_init(cs4281_t *chip); /* defined below */ |
| 1366 | #ifdef CONFIG_PM |
| 1367 | static int cs4281_suspend(snd_card_t *card, pm_message_t state); |
| 1368 | static int cs4281_resume(snd_card_t *card); |
| 1369 | #endif |
| 1370 | |
| 1371 | static int __devinit snd_cs4281_create(snd_card_t * card, |
| 1372 | struct pci_dev *pci, |
| 1373 | cs4281_t ** rchip, |
| 1374 | int dual_codec) |
| 1375 | { |
| 1376 | cs4281_t *chip; |
| 1377 | unsigned int tmp; |
| 1378 | int err; |
| 1379 | static snd_device_ops_t ops = { |
| 1380 | .dev_free = snd_cs4281_dev_free, |
| 1381 | }; |
| 1382 | |
| 1383 | *rchip = NULL; |
| 1384 | if ((err = pci_enable_device(pci)) < 0) |
| 1385 | return err; |
Takashi Iwai | e560d8d | 2005-09-09 14:21:46 +0200 | [diff] [blame] | 1386 | chip = kzalloc(sizeof(*chip), GFP_KERNEL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1387 | if (chip == NULL) { |
| 1388 | pci_disable_device(pci); |
| 1389 | return -ENOMEM; |
| 1390 | } |
| 1391 | spin_lock_init(&chip->reg_lock); |
| 1392 | chip->card = card; |
| 1393 | chip->pci = pci; |
| 1394 | chip->irq = -1; |
| 1395 | pci_set_master(pci); |
| 1396 | if (dual_codec < 0 || dual_codec > 3) { |
| 1397 | snd_printk(KERN_ERR "invalid dual_codec option %d\n", dual_codec); |
| 1398 | dual_codec = 0; |
| 1399 | } |
| 1400 | chip->dual_codec = dual_codec; |
| 1401 | |
| 1402 | if ((err = pci_request_regions(pci, "CS4281")) < 0) { |
| 1403 | kfree(chip); |
| 1404 | pci_disable_device(pci); |
| 1405 | return err; |
| 1406 | } |
| 1407 | chip->ba0_addr = pci_resource_start(pci, 0); |
| 1408 | chip->ba1_addr = pci_resource_start(pci, 1); |
| 1409 | |
| 1410 | if (request_irq(pci->irq, snd_cs4281_interrupt, SA_INTERRUPT|SA_SHIRQ, "CS4281", (void *)chip)) { |
| 1411 | snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); |
| 1412 | snd_cs4281_free(chip); |
| 1413 | return -ENOMEM; |
| 1414 | } |
| 1415 | chip->irq = pci->irq; |
| 1416 | |
| 1417 | chip->ba0 = ioremap_nocache(chip->ba0_addr, pci_resource_len(pci, 0)); |
| 1418 | chip->ba1 = ioremap_nocache(chip->ba1_addr, pci_resource_len(pci, 1)); |
| 1419 | if (!chip->ba0 || !chip->ba1) { |
| 1420 | snd_cs4281_free(chip); |
| 1421 | return -ENOMEM; |
| 1422 | } |
| 1423 | |
| 1424 | tmp = snd_cs4281_chip_init(chip); |
| 1425 | if (tmp) { |
| 1426 | snd_cs4281_free(chip); |
| 1427 | return tmp; |
| 1428 | } |
| 1429 | |
| 1430 | if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { |
| 1431 | snd_cs4281_free(chip); |
| 1432 | return err; |
| 1433 | } |
| 1434 | |
| 1435 | snd_cs4281_proc_init(chip); |
| 1436 | |
| 1437 | snd_card_set_pm_callback(card, cs4281_suspend, cs4281_resume, chip); |
| 1438 | |
| 1439 | snd_card_set_dev(card, &pci->dev); |
| 1440 | |
| 1441 | *rchip = chip; |
| 1442 | return 0; |
| 1443 | } |
| 1444 | |
| 1445 | static int snd_cs4281_chip_init(cs4281_t *chip) |
| 1446 | { |
| 1447 | unsigned int tmp; |
| 1448 | int timeout; |
| 1449 | int retry_count = 2; |
| 1450 | |
Arnaud Patard | a488e03 | 2005-05-07 18:51:51 +0200 | [diff] [blame] | 1451 | /* Having EPPMC.FPDN=1 prevent proper chip initialisation */ |
| 1452 | tmp = snd_cs4281_peekBA0(chip, BA0_EPPMC); |
| 1453 | if (tmp & BA0_EPPMC_FPDN) |
| 1454 | snd_cs4281_pokeBA0(chip, BA0_EPPMC, tmp & ~BA0_EPPMC_FPDN); |
| 1455 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1456 | __retry: |
| 1457 | tmp = snd_cs4281_peekBA0(chip, BA0_CFLR); |
| 1458 | if (tmp != BA0_CFLR_DEFAULT) { |
| 1459 | snd_cs4281_pokeBA0(chip, BA0_CFLR, BA0_CFLR_DEFAULT); |
| 1460 | tmp = snd_cs4281_peekBA0(chip, BA0_CFLR); |
| 1461 | if (tmp != BA0_CFLR_DEFAULT) { |
| 1462 | snd_printk(KERN_ERR "CFLR setup failed (0x%x)\n", tmp); |
| 1463 | return -EIO; |
| 1464 | } |
| 1465 | } |
| 1466 | |
| 1467 | /* Set the 'Configuration Write Protect' register |
| 1468 | * to 4281h. Allows vendor-defined configuration |
| 1469 | * space between 0e4h and 0ffh to be written. */ |
| 1470 | snd_cs4281_pokeBA0(chip, BA0_CWPR, 0x4281); |
| 1471 | |
| 1472 | if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC1)) != (BA0_SERC1_SO1EN | BA0_SERC1_AC97)) { |
| 1473 | snd_printk(KERN_ERR "SERC1 AC'97 check failed (0x%x)\n", tmp); |
| 1474 | return -EIO; |
| 1475 | } |
| 1476 | if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC2)) != (BA0_SERC2_SI1EN | BA0_SERC2_AC97)) { |
| 1477 | snd_printk(KERN_ERR "SERC2 AC'97 check failed (0x%x)\n", tmp); |
| 1478 | return -EIO; |
| 1479 | } |
| 1480 | |
| 1481 | /* Sound System Power Management */ |
| 1482 | snd_cs4281_pokeBA0(chip, BA0_SSPM, BA0_SSPM_MIXEN | BA0_SSPM_CSRCEN | |
| 1483 | BA0_SSPM_PSRCEN | BA0_SSPM_JSEN | |
| 1484 | BA0_SSPM_ACLEN | BA0_SSPM_FMEN); |
| 1485 | |
| 1486 | /* Serial Port Power Management */ |
| 1487 | /* Blast the clock control register to zero so that the |
| 1488 | * PLL starts out in a known state, and blast the master serial |
| 1489 | * port control register to zero so that the serial ports also |
| 1490 | * start out in a known state. */ |
| 1491 | snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0); |
| 1492 | snd_cs4281_pokeBA0(chip, BA0_SERMC, 0); |
| 1493 | |
| 1494 | /* Make ESYN go to zero to turn off |
| 1495 | * the Sync pulse on the AC97 link. */ |
| 1496 | snd_cs4281_pokeBA0(chip, BA0_ACCTL, 0); |
| 1497 | udelay(50); |
| 1498 | |
| 1499 | /* Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97 |
| 1500 | * spec) and then drive it high. This is done for non AC97 modes since |
| 1501 | * there might be logic external to the CS4281 that uses the ARST# line |
| 1502 | * for a reset. */ |
| 1503 | snd_cs4281_pokeBA0(chip, BA0_SPMC, 0); |
| 1504 | udelay(50); |
| 1505 | snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN); |
| 1506 | snd_cs4281_delay(50000); |
| 1507 | |
| 1508 | if (chip->dual_codec) |
| 1509 | snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN | BA0_SPMC_ASDI2E); |
| 1510 | |
| 1511 | /* |
| 1512 | * Set the serial port timing configuration. |
| 1513 | */ |
| 1514 | snd_cs4281_pokeBA0(chip, BA0_SERMC, |
| 1515 | (chip->dual_codec ? BA0_SERMC_TCID(chip->dual_codec) : BA0_SERMC_TCID(1)) | |
| 1516 | BA0_SERMC_PTC_AC97 | BA0_SERMC_MSPE); |
| 1517 | |
| 1518 | /* |
| 1519 | * Start the DLL Clock logic. |
| 1520 | */ |
| 1521 | snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP); |
| 1522 | snd_cs4281_delay(50000); |
| 1523 | snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP); |
| 1524 | |
| 1525 | /* |
| 1526 | * Wait for the DLL ready signal from the clock logic. |
| 1527 | */ |
| 1528 | timeout = HZ; |
| 1529 | do { |
| 1530 | /* |
| 1531 | * Read the AC97 status register to see if we've seen a CODEC |
| 1532 | * signal from the AC97 codec. |
| 1533 | */ |
| 1534 | if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY) |
| 1535 | goto __ok0; |
| 1536 | snd_cs4281_delay_long(); |
| 1537 | } while (timeout-- > 0); |
| 1538 | |
| 1539 | snd_printk(KERN_ERR "DLLRDY not seen\n"); |
| 1540 | return -EIO; |
| 1541 | |
| 1542 | __ok0: |
| 1543 | |
| 1544 | /* |
| 1545 | * The first thing we do here is to enable sync generation. As soon |
| 1546 | * as we start receiving bit clock, we'll start producing the SYNC |
| 1547 | * signal. |
| 1548 | */ |
| 1549 | snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_ESYN); |
| 1550 | |
| 1551 | /* |
| 1552 | * Wait for the codec ready signal from the AC97 codec. |
| 1553 | */ |
| 1554 | timeout = HZ; |
| 1555 | do { |
| 1556 | /* |
| 1557 | * Read the AC97 status register to see if we've seen a CODEC |
| 1558 | * signal from the AC97 codec. |
| 1559 | */ |
| 1560 | if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY) |
| 1561 | goto __ok1; |
| 1562 | snd_cs4281_delay_long(); |
| 1563 | } while (timeout-- > 0); |
| 1564 | |
| 1565 | snd_printk(KERN_ERR "never read codec ready from AC'97 (0x%x)\n", snd_cs4281_peekBA0(chip, BA0_ACSTS)); |
| 1566 | return -EIO; |
| 1567 | |
| 1568 | __ok1: |
| 1569 | if (chip->dual_codec) { |
| 1570 | timeout = HZ; |
| 1571 | do { |
| 1572 | if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY) |
| 1573 | goto __codec2_ok; |
| 1574 | snd_cs4281_delay_long(); |
| 1575 | } while (timeout-- > 0); |
| 1576 | snd_printk(KERN_INFO "secondary codec doesn't respond. disable it...\n"); |
| 1577 | chip->dual_codec = 0; |
| 1578 | __codec2_ok: ; |
| 1579 | } |
| 1580 | |
| 1581 | /* |
| 1582 | * Assert the valid frame signal so that we can start sending commands |
| 1583 | * to the AC97 codec. |
| 1584 | */ |
| 1585 | |
| 1586 | snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_VFRM | BA0_ACCTL_ESYN); |
| 1587 | |
| 1588 | /* |
| 1589 | * Wait until we've sampled input slots 3 and 4 as valid, meaning that |
| 1590 | * the codec is pumping ADC data across the AC-link. |
| 1591 | */ |
| 1592 | |
| 1593 | timeout = HZ; |
| 1594 | do { |
| 1595 | /* |
| 1596 | * Read the input slot valid register and see if input slots 3 |
| 1597 | * 4 are valid yet. |
| 1598 | */ |
| 1599 | if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) |
| 1600 | goto __ok2; |
| 1601 | snd_cs4281_delay_long(); |
| 1602 | } while (timeout-- > 0); |
| 1603 | |
| 1604 | if (--retry_count > 0) |
| 1605 | goto __retry; |
| 1606 | snd_printk(KERN_ERR "never read ISV3 and ISV4 from AC'97\n"); |
| 1607 | return -EIO; |
| 1608 | |
| 1609 | __ok2: |
| 1610 | |
| 1611 | /* |
| 1612 | * Now, assert valid frame and the slot 3 and 4 valid bits. This will |
| 1613 | * commense the transfer of digital audio data to the AC97 codec. |
| 1614 | */ |
| 1615 | snd_cs4281_pokeBA0(chip, BA0_ACOSV, BA0_ACOSV_SLV(3) | BA0_ACOSV_SLV(4)); |
| 1616 | |
| 1617 | /* |
| 1618 | * Initialize DMA structures |
| 1619 | */ |
| 1620 | for (tmp = 0; tmp < 4; tmp++) { |
| 1621 | cs4281_dma_t *dma = &chip->dma[tmp]; |
| 1622 | dma->regDBA = BA0_DBA0 + (tmp * 0x10); |
| 1623 | dma->regDCA = BA0_DCA0 + (tmp * 0x10); |
| 1624 | dma->regDBC = BA0_DBC0 + (tmp * 0x10); |
| 1625 | dma->regDCC = BA0_DCC0 + (tmp * 0x10); |
| 1626 | dma->regDMR = BA0_DMR0 + (tmp * 8); |
| 1627 | dma->regDCR = BA0_DCR0 + (tmp * 8); |
| 1628 | dma->regHDSR = BA0_HDSR0 + (tmp * 4); |
| 1629 | dma->regFCR = BA0_FCR0 + (tmp * 4); |
| 1630 | dma->regFSIC = BA0_FSIC0 + (tmp * 4); |
| 1631 | dma->fifo_offset = tmp * CS4281_FIFO_SIZE; |
| 1632 | snd_cs4281_pokeBA0(chip, dma->regFCR, |
| 1633 | BA0_FCR_LS(31) | |
| 1634 | BA0_FCR_RS(31) | |
| 1635 | BA0_FCR_SZ(CS4281_FIFO_SIZE) | |
| 1636 | BA0_FCR_OF(dma->fifo_offset)); |
| 1637 | } |
| 1638 | |
| 1639 | chip->src_left_play_slot = 0; /* AC'97 left PCM playback (3) */ |
| 1640 | chip->src_right_play_slot = 1; /* AC'97 right PCM playback (4) */ |
| 1641 | chip->src_left_rec_slot = 10; /* AC'97 left PCM record (3) */ |
| 1642 | chip->src_right_rec_slot = 11; /* AC'97 right PCM record (4) */ |
| 1643 | |
| 1644 | /* Activate wave playback FIFO for FM playback */ |
| 1645 | chip->dma[0].valFCR = BA0_FCR_FEN | BA0_FCR_LS(0) | |
| 1646 | BA0_FCR_RS(1) | |
| 1647 | BA0_FCR_SZ(CS4281_FIFO_SIZE) | |
| 1648 | BA0_FCR_OF(chip->dma[0].fifo_offset); |
| 1649 | snd_cs4281_pokeBA0(chip, chip->dma[0].regFCR, chip->dma[0].valFCR); |
| 1650 | snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) | |
| 1651 | (chip->src_right_play_slot << 8) | |
| 1652 | (chip->src_left_rec_slot << 16) | |
| 1653 | (chip->src_right_rec_slot << 24)); |
| 1654 | |
| 1655 | /* Initialize digital volume */ |
| 1656 | snd_cs4281_pokeBA0(chip, BA0_PPLVC, 0); |
| 1657 | snd_cs4281_pokeBA0(chip, BA0_PPRVC, 0); |
| 1658 | |
| 1659 | /* Enable IRQs */ |
| 1660 | snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI); |
| 1661 | /* Unmask interrupts */ |
| 1662 | snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff & ~( |
| 1663 | BA0_HISR_MIDI | |
| 1664 | BA0_HISR_DMAI | |
| 1665 | BA0_HISR_DMA(0) | |
| 1666 | BA0_HISR_DMA(1) | |
| 1667 | BA0_HISR_DMA(2) | |
| 1668 | BA0_HISR_DMA(3))); |
| 1669 | synchronize_irq(chip->irq); |
| 1670 | |
| 1671 | return 0; |
| 1672 | } |
| 1673 | |
| 1674 | /* |
| 1675 | * MIDI section |
| 1676 | */ |
| 1677 | |
| 1678 | static void snd_cs4281_midi_reset(cs4281_t *chip) |
| 1679 | { |
| 1680 | snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr | BA0_MIDCR_MRST); |
| 1681 | udelay(100); |
| 1682 | snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); |
| 1683 | } |
| 1684 | |
| 1685 | static int snd_cs4281_midi_input_open(snd_rawmidi_substream_t * substream) |
| 1686 | { |
| 1687 | cs4281_t *chip = substream->rmidi->private_data; |
| 1688 | |
| 1689 | spin_lock_irq(&chip->reg_lock); |
| 1690 | chip->midcr |= BA0_MIDCR_RXE; |
| 1691 | chip->midi_input = substream; |
| 1692 | if (!(chip->uartm & CS4281_MODE_OUTPUT)) { |
| 1693 | snd_cs4281_midi_reset(chip); |
| 1694 | } else { |
| 1695 | snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); |
| 1696 | } |
| 1697 | spin_unlock_irq(&chip->reg_lock); |
| 1698 | return 0; |
| 1699 | } |
| 1700 | |
| 1701 | static int snd_cs4281_midi_input_close(snd_rawmidi_substream_t * substream) |
| 1702 | { |
| 1703 | cs4281_t *chip = substream->rmidi->private_data; |
| 1704 | |
| 1705 | spin_lock_irq(&chip->reg_lock); |
| 1706 | chip->midcr &= ~(BA0_MIDCR_RXE | BA0_MIDCR_RIE); |
| 1707 | chip->midi_input = NULL; |
| 1708 | if (!(chip->uartm & CS4281_MODE_OUTPUT)) { |
| 1709 | snd_cs4281_midi_reset(chip); |
| 1710 | } else { |
| 1711 | snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); |
| 1712 | } |
| 1713 | chip->uartm &= ~CS4281_MODE_INPUT; |
| 1714 | spin_unlock_irq(&chip->reg_lock); |
| 1715 | return 0; |
| 1716 | } |
| 1717 | |
| 1718 | static int snd_cs4281_midi_output_open(snd_rawmidi_substream_t * substream) |
| 1719 | { |
| 1720 | cs4281_t *chip = substream->rmidi->private_data; |
| 1721 | |
| 1722 | spin_lock_irq(&chip->reg_lock); |
| 1723 | chip->uartm |= CS4281_MODE_OUTPUT; |
| 1724 | chip->midcr |= BA0_MIDCR_TXE; |
| 1725 | chip->midi_output = substream; |
| 1726 | if (!(chip->uartm & CS4281_MODE_INPUT)) { |
| 1727 | snd_cs4281_midi_reset(chip); |
| 1728 | } else { |
| 1729 | snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); |
| 1730 | } |
| 1731 | spin_unlock_irq(&chip->reg_lock); |
| 1732 | return 0; |
| 1733 | } |
| 1734 | |
| 1735 | static int snd_cs4281_midi_output_close(snd_rawmidi_substream_t * substream) |
| 1736 | { |
| 1737 | cs4281_t *chip = substream->rmidi->private_data; |
| 1738 | |
| 1739 | spin_lock_irq(&chip->reg_lock); |
| 1740 | chip->midcr &= ~(BA0_MIDCR_TXE | BA0_MIDCR_TIE); |
| 1741 | chip->midi_output = NULL; |
| 1742 | if (!(chip->uartm & CS4281_MODE_INPUT)) { |
| 1743 | snd_cs4281_midi_reset(chip); |
| 1744 | } else { |
| 1745 | snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); |
| 1746 | } |
| 1747 | chip->uartm &= ~CS4281_MODE_OUTPUT; |
| 1748 | spin_unlock_irq(&chip->reg_lock); |
| 1749 | return 0; |
| 1750 | } |
| 1751 | |
| 1752 | static void snd_cs4281_midi_input_trigger(snd_rawmidi_substream_t * substream, int up) |
| 1753 | { |
| 1754 | unsigned long flags; |
| 1755 | cs4281_t *chip = substream->rmidi->private_data; |
| 1756 | |
| 1757 | spin_lock_irqsave(&chip->reg_lock, flags); |
| 1758 | if (up) { |
| 1759 | if ((chip->midcr & BA0_MIDCR_RIE) == 0) { |
| 1760 | chip->midcr |= BA0_MIDCR_RIE; |
| 1761 | snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); |
| 1762 | } |
| 1763 | } else { |
| 1764 | if (chip->midcr & BA0_MIDCR_RIE) { |
| 1765 | chip->midcr &= ~BA0_MIDCR_RIE; |
| 1766 | snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); |
| 1767 | } |
| 1768 | } |
| 1769 | spin_unlock_irqrestore(&chip->reg_lock, flags); |
| 1770 | } |
| 1771 | |
| 1772 | static void snd_cs4281_midi_output_trigger(snd_rawmidi_substream_t * substream, int up) |
| 1773 | { |
| 1774 | unsigned long flags; |
| 1775 | cs4281_t *chip = substream->rmidi->private_data; |
| 1776 | unsigned char byte; |
| 1777 | |
| 1778 | spin_lock_irqsave(&chip->reg_lock, flags); |
| 1779 | if (up) { |
| 1780 | if ((chip->midcr & BA0_MIDCR_TIE) == 0) { |
| 1781 | chip->midcr |= BA0_MIDCR_TIE; |
| 1782 | /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */ |
| 1783 | while ((chip->midcr & BA0_MIDCR_TIE) && |
| 1784 | (snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) { |
| 1785 | if (snd_rawmidi_transmit(substream, &byte, 1) != 1) { |
| 1786 | chip->midcr &= ~BA0_MIDCR_TIE; |
| 1787 | } else { |
| 1788 | snd_cs4281_pokeBA0(chip, BA0_MIDWP, byte); |
| 1789 | } |
| 1790 | } |
| 1791 | snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); |
| 1792 | } |
| 1793 | } else { |
| 1794 | if (chip->midcr & BA0_MIDCR_TIE) { |
| 1795 | chip->midcr &= ~BA0_MIDCR_TIE; |
| 1796 | snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); |
| 1797 | } |
| 1798 | } |
| 1799 | spin_unlock_irqrestore(&chip->reg_lock, flags); |
| 1800 | } |
| 1801 | |
| 1802 | static snd_rawmidi_ops_t snd_cs4281_midi_output = |
| 1803 | { |
| 1804 | .open = snd_cs4281_midi_output_open, |
| 1805 | .close = snd_cs4281_midi_output_close, |
| 1806 | .trigger = snd_cs4281_midi_output_trigger, |
| 1807 | }; |
| 1808 | |
| 1809 | static snd_rawmidi_ops_t snd_cs4281_midi_input = |
| 1810 | { |
| 1811 | .open = snd_cs4281_midi_input_open, |
| 1812 | .close = snd_cs4281_midi_input_close, |
| 1813 | .trigger = snd_cs4281_midi_input_trigger, |
| 1814 | }; |
| 1815 | |
| 1816 | static int __devinit snd_cs4281_midi(cs4281_t * chip, int device, snd_rawmidi_t **rrawmidi) |
| 1817 | { |
| 1818 | snd_rawmidi_t *rmidi; |
| 1819 | int err; |
| 1820 | |
| 1821 | if (rrawmidi) |
| 1822 | *rrawmidi = NULL; |
| 1823 | if ((err = snd_rawmidi_new(chip->card, "CS4281", device, 1, 1, &rmidi)) < 0) |
| 1824 | return err; |
| 1825 | strcpy(rmidi->name, "CS4281"); |
| 1826 | snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs4281_midi_output); |
| 1827 | snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs4281_midi_input); |
| 1828 | rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX; |
| 1829 | rmidi->private_data = chip; |
| 1830 | chip->rmidi = rmidi; |
| 1831 | if (rrawmidi) |
| 1832 | *rrawmidi = rmidi; |
| 1833 | return 0; |
| 1834 | } |
| 1835 | |
| 1836 | /* |
| 1837 | * Interrupt handler |
| 1838 | */ |
| 1839 | |
| 1840 | static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id, struct pt_regs *regs) |
| 1841 | { |
| 1842 | cs4281_t *chip = dev_id; |
| 1843 | unsigned int status, dma, val; |
| 1844 | cs4281_dma_t *cdma; |
| 1845 | |
| 1846 | if (chip == NULL) |
| 1847 | return IRQ_NONE; |
| 1848 | status = snd_cs4281_peekBA0(chip, BA0_HISR); |
| 1849 | if ((status & 0x7fffffff) == 0) { |
| 1850 | snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI); |
| 1851 | return IRQ_NONE; |
| 1852 | } |
| 1853 | |
| 1854 | if (status & (BA0_HISR_DMA(0)|BA0_HISR_DMA(1)|BA0_HISR_DMA(2)|BA0_HISR_DMA(3))) { |
| 1855 | for (dma = 0; dma < 4; dma++) |
| 1856 | if (status & BA0_HISR_DMA(dma)) { |
| 1857 | cdma = &chip->dma[dma]; |
| 1858 | spin_lock(&chip->reg_lock); |
| 1859 | /* ack DMA IRQ */ |
| 1860 | val = snd_cs4281_peekBA0(chip, cdma->regHDSR); |
| 1861 | /* workaround, sometimes CS4281 acknowledges */ |
| 1862 | /* end or middle transfer position twice */ |
| 1863 | cdma->frag++; |
| 1864 | if ((val & BA0_HDSR_DHTC) && !(cdma->frag & 1)) { |
| 1865 | cdma->frag--; |
| 1866 | chip->spurious_dhtc_irq++; |
| 1867 | spin_unlock(&chip->reg_lock); |
| 1868 | continue; |
| 1869 | } |
| 1870 | if ((val & BA0_HDSR_DTC) && (cdma->frag & 1)) { |
| 1871 | cdma->frag--; |
| 1872 | chip->spurious_dtc_irq++; |
| 1873 | spin_unlock(&chip->reg_lock); |
| 1874 | continue; |
| 1875 | } |
| 1876 | spin_unlock(&chip->reg_lock); |
| 1877 | snd_pcm_period_elapsed(cdma->substream); |
| 1878 | } |
| 1879 | } |
| 1880 | |
| 1881 | if ((status & BA0_HISR_MIDI) && chip->rmidi) { |
| 1882 | unsigned char c; |
| 1883 | |
| 1884 | spin_lock(&chip->reg_lock); |
| 1885 | while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_RBE) == 0) { |
| 1886 | c = snd_cs4281_peekBA0(chip, BA0_MIDRP); |
| 1887 | if ((chip->midcr & BA0_MIDCR_RIE) == 0) |
| 1888 | continue; |
| 1889 | snd_rawmidi_receive(chip->midi_input, &c, 1); |
| 1890 | } |
| 1891 | while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) { |
| 1892 | if ((chip->midcr & BA0_MIDCR_TIE) == 0) |
| 1893 | break; |
| 1894 | if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) { |
| 1895 | chip->midcr &= ~BA0_MIDCR_TIE; |
| 1896 | snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); |
| 1897 | break; |
| 1898 | } |
| 1899 | snd_cs4281_pokeBA0(chip, BA0_MIDWP, c); |
| 1900 | } |
| 1901 | spin_unlock(&chip->reg_lock); |
| 1902 | } |
| 1903 | |
| 1904 | /* EOI to the PCI part... reenables interrupts */ |
| 1905 | snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI); |
| 1906 | |
| 1907 | return IRQ_HANDLED; |
| 1908 | } |
| 1909 | |
| 1910 | |
| 1911 | /* |
| 1912 | * OPL3 command |
| 1913 | */ |
| 1914 | static void snd_cs4281_opl3_command(opl3_t * opl3, unsigned short cmd, unsigned char val) |
| 1915 | { |
| 1916 | unsigned long flags; |
| 1917 | cs4281_t *chip = opl3->private_data; |
| 1918 | void __iomem *port; |
| 1919 | |
| 1920 | if (cmd & OPL3_RIGHT) |
| 1921 | port = chip->ba0 + BA0_B1AP; /* right port */ |
| 1922 | else |
| 1923 | port = chip->ba0 + BA0_B0AP; /* left port */ |
| 1924 | |
| 1925 | spin_lock_irqsave(&opl3->reg_lock, flags); |
| 1926 | |
| 1927 | writel((unsigned int)cmd, port); |
| 1928 | udelay(10); |
| 1929 | |
| 1930 | writel((unsigned int)val, port + 4); |
| 1931 | udelay(30); |
| 1932 | |
| 1933 | spin_unlock_irqrestore(&opl3->reg_lock, flags); |
| 1934 | } |
| 1935 | |
| 1936 | static int __devinit snd_cs4281_probe(struct pci_dev *pci, |
| 1937 | const struct pci_device_id *pci_id) |
| 1938 | { |
| 1939 | static int dev; |
| 1940 | snd_card_t *card; |
| 1941 | cs4281_t *chip; |
| 1942 | opl3_t *opl3; |
| 1943 | int err; |
| 1944 | |
| 1945 | if (dev >= SNDRV_CARDS) |
| 1946 | return -ENODEV; |
| 1947 | if (!enable[dev]) { |
| 1948 | dev++; |
| 1949 | return -ENOENT; |
| 1950 | } |
| 1951 | |
| 1952 | card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0); |
| 1953 | if (card == NULL) |
| 1954 | return -ENOMEM; |
| 1955 | |
| 1956 | if ((err = snd_cs4281_create(card, pci, &chip, dual_codec[dev])) < 0) { |
| 1957 | snd_card_free(card); |
| 1958 | return err; |
| 1959 | } |
| 1960 | |
| 1961 | if ((err = snd_cs4281_mixer(chip)) < 0) { |
| 1962 | snd_card_free(card); |
| 1963 | return err; |
| 1964 | } |
| 1965 | if ((err = snd_cs4281_pcm(chip, 0, NULL)) < 0) { |
| 1966 | snd_card_free(card); |
| 1967 | return err; |
| 1968 | } |
| 1969 | if ((err = snd_cs4281_midi(chip, 0, NULL)) < 0) { |
| 1970 | snd_card_free(card); |
| 1971 | return err; |
| 1972 | } |
| 1973 | if ((err = snd_opl3_new(card, OPL3_HW_OPL3_CS4281, &opl3)) < 0) { |
| 1974 | snd_card_free(card); |
| 1975 | return err; |
| 1976 | } |
| 1977 | opl3->private_data = chip; |
| 1978 | opl3->command = snd_cs4281_opl3_command; |
| 1979 | snd_opl3_init(opl3); |
| 1980 | if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) { |
| 1981 | snd_card_free(card); |
| 1982 | return err; |
| 1983 | } |
| 1984 | snd_cs4281_create_gameport(chip); |
| 1985 | strcpy(card->driver, "CS4281"); |
| 1986 | strcpy(card->shortname, "Cirrus Logic CS4281"); |
| 1987 | sprintf(card->longname, "%s at 0x%lx, irq %d", |
| 1988 | card->shortname, |
| 1989 | chip->ba0_addr, |
| 1990 | chip->irq); |
| 1991 | |
| 1992 | if ((err = snd_card_register(card)) < 0) { |
| 1993 | snd_card_free(card); |
| 1994 | return err; |
| 1995 | } |
| 1996 | |
| 1997 | pci_set_drvdata(pci, card); |
| 1998 | dev++; |
| 1999 | return 0; |
| 2000 | } |
| 2001 | |
| 2002 | static void __devexit snd_cs4281_remove(struct pci_dev *pci) |
| 2003 | { |
| 2004 | snd_card_free(pci_get_drvdata(pci)); |
| 2005 | pci_set_drvdata(pci, NULL); |
| 2006 | } |
| 2007 | |
| 2008 | /* |
| 2009 | * Power Management |
| 2010 | */ |
| 2011 | #ifdef CONFIG_PM |
| 2012 | |
| 2013 | static int saved_regs[SUSPEND_REGISTERS] = { |
| 2014 | BA0_JSCTL, |
| 2015 | BA0_GPIOR, |
| 2016 | BA0_SSCR, |
| 2017 | BA0_MIDCR, |
| 2018 | BA0_SRCSA, |
| 2019 | BA0_PASR, |
| 2020 | BA0_CASR, |
| 2021 | BA0_DACSR, |
| 2022 | BA0_ADCSR, |
| 2023 | BA0_FMLVC, |
| 2024 | BA0_FMRVC, |
| 2025 | BA0_PPLVC, |
| 2026 | BA0_PPRVC, |
| 2027 | }; |
| 2028 | |
| 2029 | #define CLKCR1_CKRA 0x00010000L |
| 2030 | |
| 2031 | static int cs4281_suspend(snd_card_t *card, pm_message_t state) |
| 2032 | { |
| 2033 | cs4281_t *chip = card->pm_private_data; |
| 2034 | u32 ulCLK; |
| 2035 | unsigned int i; |
| 2036 | |
| 2037 | snd_pcm_suspend_all(chip->pcm); |
| 2038 | |
| 2039 | if (chip->ac97) |
| 2040 | snd_ac97_suspend(chip->ac97); |
| 2041 | if (chip->ac97_secondary) |
| 2042 | snd_ac97_suspend(chip->ac97_secondary); |
| 2043 | |
| 2044 | ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1); |
| 2045 | ulCLK |= CLKCR1_CKRA; |
| 2046 | snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK); |
| 2047 | |
| 2048 | /* Disable interrupts. */ |
| 2049 | snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_CHGM); |
| 2050 | |
| 2051 | /* remember the status registers */ |
| 2052 | for (i = 0; i < ARRAY_SIZE(saved_regs); i++) |
| 2053 | if (saved_regs[i]) |
| 2054 | chip->suspend_regs[i] = snd_cs4281_peekBA0(chip, saved_regs[i]); |
| 2055 | |
| 2056 | /* Turn off the serial ports. */ |
| 2057 | snd_cs4281_pokeBA0(chip, BA0_SERMC, 0); |
| 2058 | |
| 2059 | /* Power off FM, Joystick, AC link, */ |
| 2060 | snd_cs4281_pokeBA0(chip, BA0_SSPM, 0); |
| 2061 | |
| 2062 | /* DLL off. */ |
| 2063 | snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0); |
| 2064 | |
| 2065 | /* AC link off. */ |
| 2066 | snd_cs4281_pokeBA0(chip, BA0_SPMC, 0); |
| 2067 | |
| 2068 | ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1); |
| 2069 | ulCLK &= ~CLKCR1_CKRA; |
| 2070 | snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK); |
| 2071 | |
| 2072 | pci_disable_device(chip->pci); |
| 2073 | return 0; |
| 2074 | } |
| 2075 | |
| 2076 | static int cs4281_resume(snd_card_t *card) |
| 2077 | { |
| 2078 | cs4281_t *chip = card->pm_private_data; |
| 2079 | unsigned int i; |
| 2080 | u32 ulCLK; |
| 2081 | |
| 2082 | pci_enable_device(chip->pci); |
| 2083 | pci_set_master(chip->pci); |
| 2084 | |
| 2085 | ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1); |
| 2086 | ulCLK |= CLKCR1_CKRA; |
| 2087 | snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK); |
| 2088 | |
| 2089 | snd_cs4281_chip_init(chip); |
| 2090 | |
| 2091 | /* restore the status registers */ |
| 2092 | for (i = 0; i < ARRAY_SIZE(saved_regs); i++) |
| 2093 | if (saved_regs[i]) |
| 2094 | snd_cs4281_pokeBA0(chip, saved_regs[i], chip->suspend_regs[i]); |
| 2095 | |
| 2096 | if (chip->ac97) |
| 2097 | snd_ac97_resume(chip->ac97); |
| 2098 | if (chip->ac97_secondary) |
| 2099 | snd_ac97_resume(chip->ac97_secondary); |
| 2100 | |
| 2101 | ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1); |
| 2102 | ulCLK &= ~CLKCR1_CKRA; |
| 2103 | snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK); |
| 2104 | |
| 2105 | return 0; |
| 2106 | } |
| 2107 | #endif /* CONFIG_PM */ |
| 2108 | |
| 2109 | static struct pci_driver driver = { |
| 2110 | .name = "CS4281", |
Clemens Ladisch | 3bcd464 | 2005-09-12 08:20:54 +0200 | [diff] [blame] | 2111 | .owner = THIS_MODULE, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2112 | .id_table = snd_cs4281_ids, |
| 2113 | .probe = snd_cs4281_probe, |
| 2114 | .remove = __devexit_p(snd_cs4281_remove), |
| 2115 | SND_PCI_PM_CALLBACKS |
| 2116 | }; |
| 2117 | |
| 2118 | static int __init alsa_card_cs4281_init(void) |
| 2119 | { |
Takashi Iwai | 01d25d4 | 2005-04-11 16:58:24 +0200 | [diff] [blame] | 2120 | return pci_register_driver(&driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2121 | } |
| 2122 | |
| 2123 | static void __exit alsa_card_cs4281_exit(void) |
| 2124 | { |
| 2125 | pci_unregister_driver(&driver); |
| 2126 | } |
| 2127 | |
| 2128 | module_init(alsa_card_cs4281_init) |
| 2129 | module_exit(alsa_card_cs4281_exit) |