Lennert Buytenhek | 01eb569 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/plat-orion/irq.c |
| 3 | * |
| 4 | * Marvell Orion SoC IRQ handling. |
| 5 | * |
| 6 | * This file is licensed under the terms of the GNU General Public |
| 7 | * License version 2. This program is licensed "as is" without any |
| 8 | * warranty of any kind, whether express or implied. |
| 9 | */ |
| 10 | |
| 11 | #include <linux/kernel.h> |
| 12 | #include <linux/init.h> |
| 13 | #include <linux/irq.h> |
| 14 | #include <linux/io.h> |
Lennert Buytenhek | 6f088f1 | 2008-08-09 13:44:58 +0200 | [diff] [blame] | 15 | #include <plat/irq.h> |
Lennert Buytenhek | 01eb569 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 16 | |
Lennert Buytenhek | 01eb569 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 17 | void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr) |
| 18 | { |
Thomas Gleixner | e59347a | 2011-04-14 19:17:57 +0200 | [diff] [blame] | 19 | struct irq_chip_generic *gc; |
| 20 | struct irq_chip_type *ct; |
Lennert Buytenhek | 01eb569 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 21 | |
| 22 | /* |
| 23 | * Mask all interrupts initially. |
| 24 | */ |
| 25 | writel(0, maskaddr); |
| 26 | |
Thomas Gleixner | e59347a | 2011-04-14 19:17:57 +0200 | [diff] [blame] | 27 | gc = irq_alloc_generic_chip("orion_irq", 1, irq_start, maskaddr, |
| 28 | handle_level_irq); |
| 29 | ct = gc->chip_types; |
| 30 | ct->chip.irq_mask = irq_gc_mask_clr_bit; |
| 31 | ct->chip.irq_unmask = irq_gc_mask_set_bit; |
| 32 | irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE, |
| 33 | IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE); |
Lennert Buytenhek | 01eb569 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 34 | } |