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Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001/*
2 * Driver for DBRI sound chip found on Sparcs.
Martin Habets43388292005-09-10 15:39:00 +02003 * Copyright (C) 2004, 2005 Martin Habets (mhabets@users.sourceforge.net)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02004 *
Krzysztof Helt1be54c82006-08-21 19:30:57 +02005 * Converted to ring buffered version by Krzysztof Helt (krzysztof.h1@wp.pl)
6 *
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02007 * Based entirely upon drivers/sbus/audio/dbri.c which is:
8 * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de)
9 * Copyright (C) 1998, 1999 Brent Baccala (baccala@freesoft.org)
10 *
Krzysztof Helt098ccbc2007-08-20 12:30:54 +020011 * This is the low level driver for the DBRI & MMCODEC duo used for ISDN & AUDIO
12 * on Sun SPARCStation 10, 20, LX and Voyager models.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020013 *
14 * - DBRI: AT&T T5900FX Dual Basic Rates ISDN Interface. It is a 32 channel
15 * data time multiplexer with ISDN support (aka T7259)
16 * Interfaces: SBus,ISDN NT & TE, CHI, 4 bits parallel.
17 * CHI: (spelled ki) Concentration Highway Interface (AT&T or Intel bus ?).
18 * Documentation:
Krzysztof Helt098ccbc2007-08-20 12:30:54 +020019 * - "STP 4000SBus Dual Basic Rate ISDN (DBRI) Transceiver" from
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020020 * Sparc Technology Business (courtesy of Sun Support)
21 * - Data sheet of the T7903, a newer but very similar ISA bus equivalent
Krzysztof Helt098ccbc2007-08-20 12:30:54 +020022 * available from the Lucent (formerly AT&T microelectronics) home
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020023 * page.
24 * - http://www.freesoft.org/Linux/DBRI/
25 * - MMCODEC: Crystal Semiconductor CS4215 16 bit Multimedia Audio Codec
26 * Interfaces: CHI, Audio In & Out, 2 bits parallel
27 * Documentation: from the Crystal Semiconductor home page.
28 *
29 * The DBRI is a 32 pipe machine, each pipe can transfer some bits between
Krzysztof Helt098ccbc2007-08-20 12:30:54 +020030 * memory and a serial device (long pipes, no. 0-15) or between two serial
31 * devices (short pipes, no. 16-31), or simply send a fixed data to a serial
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020032 * device (short pipes).
Krzysztof Helt098ccbc2007-08-20 12:30:54 +020033 * A timeslot defines the bit-offset and no. of bits read from a serial device.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020034 * The timeslots are linked to 6 circular lists, one for each direction for
35 * each serial device (NT,TE,CHI). A timeslot is associated to 1 or 2 pipes
36 * (the second one is a monitor/tee pipe, valid only for serial input).
37 *
38 * The mmcodec is connected via the CHI bus and needs the data & some
Krzysztof Helt098ccbc2007-08-20 12:30:54 +020039 * parameters (volume, output selection) time multiplexed in 8 byte
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020040 * chunks. It also has a control mode, which serves for audio format setting.
41 *
42 * Looking at the CS4215 data sheet it is easy to set up 2 or 4 codecs on
Krzysztof Helt098ccbc2007-08-20 12:30:54 +020043 * the same CHI bus, so I thought perhaps it is possible to use the on-board
44 * & the speakerbox codec simultaneously, giving 2 (not very independent :-)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020045 * audio devices. But the SUN HW group decided against it, at least on my
46 * LX the speakerbox connector has at least 1 pin missing and 1 wrongly
47 * connected.
Martin Habets43388292005-09-10 15:39:00 +020048 *
49 * I've tried to stick to the following function naming conventions:
50 * snd_* ALSA stuff
Adrian Bunkd254c8f2006-06-30 18:29:51 +020051 * cs4215_* CS4215 codec specific stuff
Martin Habets43388292005-09-10 15:39:00 +020052 * dbri_* DBRI high-level stuff
53 * other DBRI low-level stuff
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020054 */
55
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020056#include <linux/interrupt.h>
57#include <linux/delay.h>
Krzysztof Helt098ccbc2007-08-20 12:30:54 +020058#include <linux/irq.h>
59#include <linux/io.h>
David S. Miller738f2b72008-08-27 18:09:11 -070060#include <linux/dma-mapping.h>
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020061
62#include <sound/core.h>
63#include <sound/pcm.h>
64#include <sound/pcm_params.h>
65#include <sound/info.h>
66#include <sound/control.h>
67#include <sound/initval.h>
68
Krzysztof Heltef285fe2007-09-06 15:02:33 +020069#include <linux/of.h>
David S. Miller2bd320f2008-08-27 00:30:59 -070070#include <linux/of_device.h>
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020071#include <asm/atomic.h>
72
73MODULE_AUTHOR("Rudolf Koenig, Brent Baccala and Martin Habets");
74MODULE_DESCRIPTION("Sun DBRI");
75MODULE_LICENSE("GPL");
76MODULE_SUPPORTED_DEVICE("{{Sun,DBRI}}");
77
78static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
79static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +020080/* Enable this card */
81static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020082
83module_param_array(index, int, NULL, 0444);
84MODULE_PARM_DESC(index, "Index value for Sun DBRI soundcard.");
85module_param_array(id, charp, NULL, 0444);
86MODULE_PARM_DESC(id, "ID string for Sun DBRI soundcard.");
87module_param_array(enable, bool, NULL, 0444);
88MODULE_PARM_DESC(enable, "Enable Sun DBRI soundcard.");
89
Krzysztof Heltab93c7a2006-08-23 11:37:36 +020090#undef DBRI_DEBUG
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020091
92#define D_INT (1<<0)
93#define D_GEN (1<<1)
94#define D_CMD (1<<2)
95#define D_MM (1<<3)
96#define D_USR (1<<4)
97#define D_DESC (1<<5)
98
Takashi Iwai6581f4e2006-05-17 17:14:51 +020099static int dbri_debug;
Martin Habets43388292005-09-10 15:39:00 +0200100module_param(dbri_debug, int, 0644);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200101MODULE_PARM_DESC(dbri_debug, "Debug value for Sun DBRI soundcard.");
102
103#ifdef DBRI_DEBUG
104static char *cmds[] = {
105 "WAIT", "PAUSE", "JUMP", "IIQ", "REX", "SDP", "CDP", "DTS",
106 "SSP", "CHI", "NT", "TE", "CDEC", "TEST", "CDM", "RESRV"
107};
108
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200109#define dprintk(a, x...) if (dbri_debug & a) printk(KERN_DEBUG x)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200110
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200111#else
Krzysztof Heltaaad3652006-08-28 12:59:23 +0200112#define dprintk(a, x...) do { } while (0)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200113
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200114#endif /* DBRI_DEBUG */
115
Krzysztof Helt42fe7642006-08-16 12:53:34 +0200116#define DBRI_CMD(cmd, intr, value) ((cmd << 28) | \
117 (intr << 27) | \
118 value)
119
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200120/***************************************************************************
121 CS4215 specific definitions and structures
122****************************************************************************/
123
124struct cs4215 {
125 __u8 data[4]; /* Data mode: Time slots 5-8 */
126 __u8 ctrl[4]; /* Ctrl mode: Time slots 1-4 */
127 __u8 onboard;
128 __u8 offset; /* Bit offset from frame sync to time slot 1 */
129 volatile __u32 status;
130 volatile __u32 version;
131 __u8 precision; /* In bits, either 8 or 16 */
132 __u8 channels; /* 1 or 2 */
133};
134
135/*
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200136 * Control mode first
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200137 */
138
139/* Time Slot 1, Status register */
140#define CS4215_CLB (1<<2) /* Control Latch Bit */
141#define CS4215_OLB (1<<3) /* 1: line: 2.0V, speaker 4V */
142 /* 0: line: 2.8V, speaker 8V */
143#define CS4215_MLB (1<<4) /* 1: Microphone: 20dB gain disabled */
144#define CS4215_RSRVD_1 (1<<5)
145
146/* Time Slot 2, Data Format Register */
147#define CS4215_DFR_LINEAR16 0
148#define CS4215_DFR_ULAW 1
149#define CS4215_DFR_ALAW 2
150#define CS4215_DFR_LINEAR8 3
151#define CS4215_DFR_STEREO (1<<2)
152static struct {
153 unsigned short freq;
154 unsigned char xtal;
155 unsigned char csval;
156} CS4215_FREQ[] = {
157 { 8000, (1 << 4), (0 << 3) },
158 { 16000, (1 << 4), (1 << 3) },
159 { 27429, (1 << 4), (2 << 3) }, /* Actually 24428.57 */
160 { 32000, (1 << 4), (3 << 3) },
161 /* { NA, (1 << 4), (4 << 3) }, */
162 /* { NA, (1 << 4), (5 << 3) }, */
163 { 48000, (1 << 4), (6 << 3) },
164 { 9600, (1 << 4), (7 << 3) },
Krzysztof Heltab93c7a2006-08-23 11:37:36 +0200165 { 5512, (2 << 4), (0 << 3) }, /* Actually 5512.5 */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200166 { 11025, (2 << 4), (1 << 3) },
167 { 18900, (2 << 4), (2 << 3) },
168 { 22050, (2 << 4), (3 << 3) },
169 { 37800, (2 << 4), (4 << 3) },
170 { 44100, (2 << 4), (5 << 3) },
171 { 33075, (2 << 4), (6 << 3) },
172 { 6615, (2 << 4), (7 << 3) },
173 { 0, 0, 0}
174};
175
176#define CS4215_HPF (1<<7) /* High Pass Filter, 1: Enabled */
177
178#define CS4215_12_MASK 0xfcbf /* Mask off reserved bits in slot 1 & 2 */
179
180/* Time Slot 3, Serial Port Control register */
181#define CS4215_XEN (1<<0) /* 0: Enable serial output */
182#define CS4215_XCLK (1<<1) /* 1: Master mode: Generate SCLK */
183#define CS4215_BSEL_64 (0<<2) /* Bitrate: 64 bits per frame */
184#define CS4215_BSEL_128 (1<<2)
185#define CS4215_BSEL_256 (2<<2)
186#define CS4215_MCK_MAST (0<<4) /* Master clock */
187#define CS4215_MCK_XTL1 (1<<4) /* 24.576 MHz clock source */
188#define CS4215_MCK_XTL2 (2<<4) /* 16.9344 MHz clock source */
189#define CS4215_MCK_CLK1 (3<<4) /* Clockin, 256 x Fs */
190#define CS4215_MCK_CLK2 (4<<4) /* Clockin, see DFR */
191
192/* Time Slot 4, Test Register */
193#define CS4215_DAD (1<<0) /* 0:Digital-Dig loop, 1:Dig-Analog-Dig loop */
194#define CS4215_ENL (1<<1) /* Enable Loopback Testing */
195
196/* Time Slot 5, Parallel Port Register */
197/* Read only here and the same as the in data mode */
198
199/* Time Slot 6, Reserved */
200
201/* Time Slot 7, Version Register */
202#define CS4215_VERSION_MASK 0xf /* Known versions 0/C, 1/D, 2/E */
203
204/* Time Slot 8, Reserved */
205
206/*
207 * Data mode
208 */
209/* Time Slot 1-2: Left Channel Data, 2-3: Right Channel Data */
210
211/* Time Slot 5, Output Setting */
212#define CS4215_LO(v) v /* Left Output Attenuation 0x3f: -94.5 dB */
213#define CS4215_LE (1<<6) /* Line Out Enable */
214#define CS4215_HE (1<<7) /* Headphone Enable */
215
216/* Time Slot 6, Output Setting */
217#define CS4215_RO(v) v /* Right Output Attenuation 0x3f: -94.5 dB */
218#define CS4215_SE (1<<6) /* Speaker Enable */
219#define CS4215_ADI (1<<7) /* A/D Data Invalid: Busy in calibration */
220
221/* Time Slot 7, Input Setting */
222#define CS4215_LG(v) v /* Left Gain Setting 0xf: 22.5 dB */
223#define CS4215_IS (1<<4) /* Input Select: 1=Microphone, 0=Line */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200224#define CS4215_OVR (1<<5) /* 1: Over range condition occurred */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200225#define CS4215_PIO0 (1<<6) /* Parallel I/O 0 */
226#define CS4215_PIO1 (1<<7)
227
228/* Time Slot 8, Input Setting */
229#define CS4215_RG(v) v /* Right Gain Setting 0xf: 22.5 dB */
230#define CS4215_MA(v) (v<<4) /* Monitor Path Attenuation 0xf: mute */
231
232/***************************************************************************
233 DBRI specific definitions and structures
234****************************************************************************/
235
236/* DBRI main registers */
Krzysztof Heltcf68d212007-09-04 13:09:20 +0200237#define REG0 0x00 /* Status and Control */
238#define REG1 0x04 /* Mode and Interrupt */
239#define REG2 0x08 /* Parallel IO */
240#define REG3 0x0c /* Test */
241#define REG8 0x20 /* Command Queue Pointer */
242#define REG9 0x24 /* Interrupt Queue Pointer */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200243
244#define DBRI_NO_CMDS 64
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200245#define DBRI_INT_BLK 64
246#define DBRI_NO_DESCS 64
247#define DBRI_NO_PIPES 32
Krzysztof Helt470f1f12006-08-21 19:28:16 +0200248#define DBRI_MAX_PIPE (DBRI_NO_PIPES - 1)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200249
250#define DBRI_REC 0
251#define DBRI_PLAY 1
252#define DBRI_NO_STREAMS 2
253
254/* One transmit/receive descriptor */
Krzysztof Heltc2735442006-08-21 19:27:35 +0200255/* When ba != 0 descriptor is used */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200256struct dbri_mem {
257 volatile __u32 word1;
Krzysztof Helt16727d92006-08-17 16:59:28 +0200258 __u32 ba; /* Transmit/Receive Buffer Address */
259 __u32 nda; /* Next Descriptor Address */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200260 volatile __u32 word4;
261};
262
263/* This structure is in a DMA region where it can accessed by both
264 * the CPU and the DBRI
265 */
266struct dbri_dma {
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200267 s32 cmd[DBRI_NO_CMDS]; /* Place for commands */
Krzysztof Helt6fb98282006-08-16 12:54:29 +0200268 volatile s32 intr[DBRI_INT_BLK]; /* Interrupt field */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200269 struct dbri_mem desc[DBRI_NO_DESCS]; /* Xmit/receive descriptors */
270};
271
272#define dbri_dma_off(member, elem) \
273 ((u32)(unsigned long) \
274 (&(((struct dbri_dma *)0)->member[elem])))
275
276enum in_or_out { PIPEinput, PIPEoutput };
277
278struct dbri_pipe {
279 u32 sdp; /* SDP command word */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200280 int nextpipe; /* Next pipe in linked list */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200281 int length; /* Length of timeslot (bits) */
282 int first_desc; /* Index of first descriptor */
283 int desc; /* Index of active descriptor */
284 volatile __u32 *recv_fixed_ptr; /* Ptr to receive fixed data */
285};
286
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200287/* Per stream (playback or record) information */
Takashi Iwai475675d2005-11-17 15:11:51 +0100288struct dbri_streaminfo {
289 struct snd_pcm_substream *substream;
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200290 u32 dvma_buffer; /* Device view of ALSA DMA buffer */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200291 int size; /* Size of DMA buffer */
292 size_t offset; /* offset in user buffer */
293 int pipe; /* Data pipe used */
294 int left_gain; /* mixer elements */
295 int right_gain;
Takashi Iwai475675d2005-11-17 15:11:51 +0100296};
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200297
298/* This structure holds the information for both chips (DBRI & CS4215) */
Takashi Iwai475675d2005-11-17 15:11:51 +0100299struct snd_dbri {
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200300 int regs_size, irq; /* Needed for unload */
David S. Miller2bd320f2008-08-27 00:30:59 -0700301 struct of_device *op; /* OF device info */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200302 spinlock_t lock;
303
Krzysztof Helt16727d92006-08-17 16:59:28 +0200304 struct dbri_dma *dma; /* Pointer to our DMA block */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200305 u32 dma_dvma; /* DBRI visible DMA address */
306
307 void __iomem *regs; /* dbri HW regs */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200308 int dbri_irqp; /* intr queue pointer */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200309
310 struct dbri_pipe pipes[DBRI_NO_PIPES]; /* DBRI's 32 data pipes */
Krzysztof Heltc2735442006-08-21 19:27:35 +0200311 int next_desc[DBRI_NO_DESCS]; /* Index of next desc, or -1 */
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200312 spinlock_t cmdlock; /* Protects cmd queue accesses */
313 s32 *cmdptr; /* Pointer to the last queued cmd */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200314
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200315 int chi_bpf;
316
317 struct cs4215 mm; /* mmcodec special info */
318 /* per stream (playback/record) info */
319 struct dbri_streaminfo stream_info[DBRI_NO_STREAMS];
Takashi Iwai475675d2005-11-17 15:11:51 +0100320};
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200321
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200322#define DBRI_MAX_VOLUME 63 /* Output volume */
323#define DBRI_MAX_GAIN 15 /* Input gain */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200324
325/* DBRI Reg0 - Status Control Register - defines. (Page 17) */
326#define D_P (1<<15) /* Program command & queue pointer valid */
327#define D_G (1<<14) /* Allow 4-Word SBus Burst */
328#define D_S (1<<13) /* Allow 16-Word SBus Burst */
329#define D_E (1<<12) /* Allow 8-Word SBus Burst */
330#define D_X (1<<7) /* Sanity Timer Disable */
331#define D_T (1<<6) /* Permit activation of the TE interface */
332#define D_N (1<<5) /* Permit activation of the NT interface */
333#define D_C (1<<4) /* Permit activation of the CHI interface */
334#define D_F (1<<3) /* Force Sanity Timer Time-Out */
335#define D_D (1<<2) /* Disable Master Mode */
336#define D_H (1<<1) /* Halt for Analysis */
337#define D_R (1<<0) /* Soft Reset */
338
339/* DBRI Reg1 - Mode and Interrupt Register - defines. (Page 18) */
340#define D_LITTLE_END (1<<8) /* Byte Order */
341#define D_BIG_END (0<<8) /* Byte Order */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200342#define D_MRR (1<<4) /* Multiple Error Ack on SBus (read only) */
343#define D_MLE (1<<3) /* Multiple Late Error on SBus (read only) */
344#define D_LBG (1<<2) /* Lost Bus Grant on SBus (read only) */
345#define D_MBE (1<<1) /* Burst Error on SBus (read only) */
346#define D_IR (1<<0) /* Interrupt Indicator (read only) */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200347
348/* DBRI Reg2 - Parallel IO Register - defines. (Page 18) */
349#define D_ENPIO3 (1<<7) /* Enable Pin 3 */
350#define D_ENPIO2 (1<<6) /* Enable Pin 2 */
351#define D_ENPIO1 (1<<5) /* Enable Pin 1 */
352#define D_ENPIO0 (1<<4) /* Enable Pin 0 */
353#define D_ENPIO (0xf0) /* Enable all the pins */
354#define D_PIO3 (1<<3) /* Pin 3: 1: Data mode, 0: Ctrl mode */
355#define D_PIO2 (1<<2) /* Pin 2: 1: Onboard PDN */
356#define D_PIO1 (1<<1) /* Pin 1: 0: Reset */
357#define D_PIO0 (1<<0) /* Pin 0: 1: Speakerbox PDN */
358
359/* DBRI Commands (Page 20) */
360#define D_WAIT 0x0 /* Stop execution */
361#define D_PAUSE 0x1 /* Flush long pipes */
362#define D_JUMP 0x2 /* New command queue */
363#define D_IIQ 0x3 /* Initialize Interrupt Queue */
364#define D_REX 0x4 /* Report command execution via interrupt */
365#define D_SDP 0x5 /* Setup Data Pipe */
366#define D_CDP 0x6 /* Continue Data Pipe (reread NULL Pointer) */
367#define D_DTS 0x7 /* Define Time Slot */
368#define D_SSP 0x8 /* Set short Data Pipe */
369#define D_CHI 0x9 /* Set CHI Global Mode */
370#define D_NT 0xa /* NT Command */
371#define D_TE 0xb /* TE Command */
372#define D_CDEC 0xc /* Codec setup */
373#define D_TEST 0xd /* No comment */
374#define D_CDM 0xe /* CHI Data mode command */
375
376/* Special bits for some commands */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200377#define D_PIPE(v) ((v)<<0) /* Pipe No.: 0-15 long, 16-21 short */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200378
379/* Setup Data Pipe */
380/* IRM */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200381#define D_SDP_2SAME (1<<18) /* Report 2nd time in a row value received */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200382#define D_SDP_CHANGE (2<<18) /* Report any changes */
383#define D_SDP_EVERY (3<<18) /* Report any changes */
384#define D_SDP_EOL (1<<17) /* EOL interrupt enable */
385#define D_SDP_IDLE (1<<16) /* HDLC idle interrupt enable */
386
387/* Pipe data MODE */
388#define D_SDP_MEM (0<<13) /* To/from memory */
389#define D_SDP_HDLC (2<<13)
390#define D_SDP_HDLC_D (3<<13) /* D Channel (prio control) */
391#define D_SDP_SER (4<<13) /* Serial to serial */
392#define D_SDP_FIXED (6<<13) /* Short only */
393#define D_SDP_MODE(v) ((v)&(7<<13))
394
395#define D_SDP_TO_SER (1<<12) /* Direction */
396#define D_SDP_FROM_SER (0<<12) /* Direction */
397#define D_SDP_MSB (1<<11) /* Bit order within Byte */
398#define D_SDP_LSB (0<<11) /* Bit order within Byte */
399#define D_SDP_P (1<<10) /* Pointer Valid */
400#define D_SDP_A (1<<8) /* Abort */
401#define D_SDP_C (1<<7) /* Clear */
402
403/* Define Time Slot */
404#define D_DTS_VI (1<<17) /* Valid Input Time-Slot Descriptor */
405#define D_DTS_VO (1<<16) /* Valid Output Time-Slot Descriptor */
406#define D_DTS_INS (1<<15) /* Insert Time Slot */
407#define D_DTS_DEL (0<<15) /* Delete Time Slot */
408#define D_DTS_PRVIN(v) ((v)<<10) /* Previous In Pipe */
409#define D_DTS_PRVOUT(v) ((v)<<5) /* Previous Out Pipe */
410
411/* Time Slot defines */
412#define D_TS_LEN(v) ((v)<<24) /* Number of bits in this time slot */
413#define D_TS_CYCLE(v) ((v)<<14) /* Bit Count at start of TS */
414#define D_TS_DI (1<<13) /* Data Invert */
415#define D_TS_1CHANNEL (0<<10) /* Single Channel / Normal mode */
416#define D_TS_MONITOR (2<<10) /* Monitor pipe */
417#define D_TS_NONCONTIG (3<<10) /* Non contiguous mode */
418#define D_TS_ANCHOR (7<<10) /* Starting short pipes */
419#define D_TS_MON(v) ((v)<<5) /* Monitor Pipe */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200420#define D_TS_NEXT(v) ((v)<<0) /* Pipe no.: 0-15 long, 16-21 short */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200421
422/* Concentration Highway Interface Modes */
423#define D_CHI_CHICM(v) ((v)<<16) /* Clock mode */
424#define D_CHI_IR (1<<15) /* Immediate Interrupt Report */
425#define D_CHI_EN (1<<14) /* CHIL Interrupt enabled */
426#define D_CHI_OD (1<<13) /* Open Drain Enable */
427#define D_CHI_FE (1<<12) /* Sample CHIFS on Rising Frame Edge */
428#define D_CHI_FD (1<<11) /* Frame Drive */
429#define D_CHI_BPF(v) ((v)<<0) /* Bits per Frame */
430
431/* NT: These are here for completeness */
432#define D_NT_FBIT (1<<17) /* Frame Bit */
433#define D_NT_NBF (1<<16) /* Number of bad frames to loose framing */
434#define D_NT_IRM_IMM (1<<15) /* Interrupt Report & Mask: Immediate */
435#define D_NT_IRM_EN (1<<14) /* Interrupt Report & Mask: Enable */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200436#define D_NT_ISNT (1<<13) /* Configure interface as NT */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200437#define D_NT_FT (1<<12) /* Fixed Timing */
438#define D_NT_EZ (1<<11) /* Echo Channel is Zeros */
439#define D_NT_IFA (1<<10) /* Inhibit Final Activation */
440#define D_NT_ACT (1<<9) /* Activate Interface */
441#define D_NT_MFE (1<<8) /* Multiframe Enable */
442#define D_NT_RLB(v) ((v)<<5) /* Remote Loopback */
443#define D_NT_LLB(v) ((v)<<2) /* Local Loopback */
444#define D_NT_FACT (1<<1) /* Force Activation */
445#define D_NT_ABV (1<<0) /* Activate Bipolar Violation */
446
447/* Codec Setup */
448#define D_CDEC_CK(v) ((v)<<24) /* Clock Select */
449#define D_CDEC_FED(v) ((v)<<12) /* FSCOD Falling Edge Delay */
450#define D_CDEC_RED(v) ((v)<<0) /* FSCOD Rising Edge Delay */
451
452/* Test */
453#define D_TEST_RAM(v) ((v)<<16) /* RAM Pointer */
454#define D_TEST_SIZE(v) ((v)<<11) /* */
455#define D_TEST_ROMONOFF 0x5 /* Toggle ROM opcode monitor on/off */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200456#define D_TEST_PROC 0x6 /* Microprocessor test */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200457#define D_TEST_SER 0x7 /* Serial-Controller test */
458#define D_TEST_RAMREAD 0x8 /* Copy from Ram to system memory */
459#define D_TEST_RAMWRITE 0x9 /* Copy into Ram from system memory */
460#define D_TEST_RAMBIST 0xa /* RAM Built-In Self Test */
461#define D_TEST_MCBIST 0xb /* Microcontroller Built-In Self Test */
462#define D_TEST_DUMP 0xe /* ROM Dump */
463
464/* CHI Data Mode */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200465#define D_CDM_THI (1 << 8) /* Transmit Data on CHIDR Pin */
466#define D_CDM_RHI (1 << 7) /* Receive Data on CHIDX Pin */
467#define D_CDM_RCE (1 << 6) /* Receive on Rising Edge of CHICK */
468#define D_CDM_XCE (1 << 2) /* Transmit Data on Rising Edge of CHICK */
469#define D_CDM_XEN (1 << 1) /* Transmit Highway Enable */
470#define D_CDM_REN (1 << 0) /* Receive Highway Enable */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200471
472/* The Interrupts */
473#define D_INTR_BRDY 1 /* Buffer Ready for processing */
474#define D_INTR_MINT 2 /* Marked Interrupt in RD/TD */
475#define D_INTR_IBEG 3 /* Flag to idle transition detected (HDLC) */
476#define D_INTR_IEND 4 /* Idle to flag transition detected (HDLC) */
477#define D_INTR_EOL 5 /* End of List */
478#define D_INTR_CMDI 6 /* Command has bean read */
479#define D_INTR_XCMP 8 /* Transmission of frame complete */
480#define D_INTR_SBRI 9 /* BRI status change info */
481#define D_INTR_FXDT 10 /* Fixed data change */
482#define D_INTR_CHIL 11 /* CHI lost frame sync (channel 36 only) */
483#define D_INTR_COLL 11 /* Unrecoverable D-Channel collision */
484#define D_INTR_DBYT 12 /* Dropped by frame slip */
485#define D_INTR_RBYT 13 /* Repeated by frame slip */
486#define D_INTR_LINT 14 /* Lost Interrupt */
487#define D_INTR_UNDR 15 /* DMA underrun */
488
489#define D_INTR_TE 32
490#define D_INTR_NT 34
491#define D_INTR_CHI 36
492#define D_INTR_CMD 38
493
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200494#define D_INTR_GETCHAN(v) (((v) >> 24) & 0x3f)
495#define D_INTR_GETCODE(v) (((v) >> 20) & 0xf)
496#define D_INTR_GETCMD(v) (((v) >> 16) & 0xf)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200497#define D_INTR_GETVAL(v) ((v) & 0xffff)
498#define D_INTR_GETRVAL(v) ((v) & 0xfffff)
499
500#define D_P_0 0 /* TE receive anchor */
501#define D_P_1 1 /* TE transmit anchor */
502#define D_P_2 2 /* NT transmit anchor */
503#define D_P_3 3 /* NT receive anchor */
504#define D_P_4 4 /* CHI send data */
505#define D_P_5 5 /* CHI receive data */
506#define D_P_6 6 /* */
507#define D_P_7 7 /* */
508#define D_P_8 8 /* */
509#define D_P_9 9 /* */
510#define D_P_10 10 /* */
511#define D_P_11 11 /* */
512#define D_P_12 12 /* */
513#define D_P_13 13 /* */
514#define D_P_14 14 /* */
515#define D_P_15 15 /* */
516#define D_P_16 16 /* CHI anchor pipe */
517#define D_P_17 17 /* CHI send */
518#define D_P_18 18 /* CHI receive */
519#define D_P_19 19 /* CHI receive */
520#define D_P_20 20 /* CHI receive */
521#define D_P_21 21 /* */
522#define D_P_22 22 /* */
523#define D_P_23 23 /* */
524#define D_P_24 24 /* */
525#define D_P_25 25 /* */
526#define D_P_26 26 /* */
527#define D_P_27 27 /* */
528#define D_P_28 28 /* */
529#define D_P_29 29 /* */
530#define D_P_30 30 /* */
531#define D_P_31 31 /* */
532
533/* Transmit descriptor defines */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200534#define DBRI_TD_F (1 << 31) /* End of Frame */
535#define DBRI_TD_D (1 << 30) /* Do not append CRC */
536#define DBRI_TD_CNT(v) ((v) << 16) /* Number of valid bytes in the buffer */
537#define DBRI_TD_B (1 << 15) /* Final interrupt */
538#define DBRI_TD_M (1 << 14) /* Marker interrupt */
539#define DBRI_TD_I (1 << 13) /* Transmit Idle Characters */
540#define DBRI_TD_FCNT(v) (v) /* Flag Count */
541#define DBRI_TD_UNR (1 << 3) /* Underrun: transmitter is out of data */
542#define DBRI_TD_ABT (1 << 2) /* Abort: frame aborted */
543#define DBRI_TD_TBC (1 << 0) /* Transmit buffer Complete */
544#define DBRI_TD_STATUS(v) ((v) & 0xff) /* Transmit status */
545 /* Maximum buffer size per TD: almost 8KB */
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200546#define DBRI_TD_MAXCNT ((1 << 13) - 4)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200547
548/* Receive descriptor defines */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200549#define DBRI_RD_F (1 << 31) /* End of Frame */
550#define DBRI_RD_C (1 << 30) /* Completed buffer */
551#define DBRI_RD_B (1 << 15) /* Final interrupt */
552#define DBRI_RD_M (1 << 14) /* Marker interrupt */
553#define DBRI_RD_BCNT(v) (v) /* Buffer size */
554#define DBRI_RD_CRC (1 << 7) /* 0: CRC is correct */
555#define DBRI_RD_BBC (1 << 6) /* 1: Bad Byte received */
556#define DBRI_RD_ABT (1 << 5) /* Abort: frame aborted */
557#define DBRI_RD_OVRN (1 << 3) /* Overrun: data lost */
558#define DBRI_RD_STATUS(v) ((v) & 0xff) /* Receive status */
559#define DBRI_RD_CNT(v) (((v) >> 16) & 0x1fff) /* Valid bytes in the buffer */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200560
561/* stream_info[] access */
562/* Translate the ALSA direction into the array index */
563#define DBRI_STREAMNO(substream) \
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200564 (substream->stream == \
Krzysztof Heltcf68d212007-09-04 13:09:20 +0200565 SNDRV_PCM_STREAM_PLAYBACK ? DBRI_PLAY: DBRI_REC)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200566
567/* Return a pointer to dbri_streaminfo */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200568#define DBRI_STREAM(dbri, substream) \
569 &dbri->stream_info[DBRI_STREAMNO(substream)]
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200570
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200571/*
572 * Short data pipes transmit LSB first. The CS4215 receives MSB first. Grrr.
573 * So we have to reverse the bits. Note: not all bit lengths are supported
574 */
575static __u32 reverse_bytes(__u32 b, int len)
576{
577 switch (len) {
578 case 32:
579 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16);
580 case 16:
581 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8);
582 case 8:
583 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4);
584 case 4:
585 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2);
586 case 2:
587 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1);
588 case 1:
589 case 0:
590 break;
591 default:
592 printk(KERN_ERR "DBRI reverse_bytes: unsupported length\n");
593 };
594
595 return b;
596}
597
598/*
599****************************************************************************
600************** DBRI initialization and command synchronization *************
601****************************************************************************
602
603Commands are sent to the DBRI by building a list of them in memory,
604then writing the address of the first list item to DBRI register 8.
Martin Habets43388292005-09-10 15:39:00 +0200605The list is terminated with a WAIT command, which generates a
606CPU interrupt to signal completion.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200607
608Since the DBRI can run in parallel with the CPU, several means of
Krzysztof Heltcf68d212007-09-04 13:09:20 +0200609synchronization present themselves. The method implemented here uses
610the dbri_cmdwait() to wait for execution of batch of sent commands.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200611
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200612A circular command buffer is used here. A new command is being added
Krzysztof Heltaaad3652006-08-28 12:59:23 +0200613while another can be executed. The scheme works by adding two WAIT commands
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200614after each sent batch of commands. When the next batch is prepared it is
615added after the WAIT commands then the WAITs are replaced with single JUMP
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200616command to the new batch. The the DBRI is forced to reread the last WAIT
617command (replaced by the JUMP by then). If the DBRI is still executing
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200618previous commands the request to reread the WAIT command is ignored.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200619
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200620Every time a routine wants to write commands to the DBRI, it must
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200621first call dbri_cmdlock() and get pointer to a free space in
622dbri->dma->cmd buffer. After this, the commands can be written to
623the buffer, and dbri_cmdsend() is called with the final pointer value
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200624to send them to the DBRI.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200625
626*/
627
Krzysztof Heltaaad3652006-08-28 12:59:23 +0200628#define MAXLOOPS 20
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200629/*
630 * Wait for the current command string to execute
631 */
632static void dbri_cmdwait(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200633{
Martin Habets43388292005-09-10 15:39:00 +0200634 int maxloops = MAXLOOPS;
Krzysztof Heltea543f12006-09-05 20:25:05 +0200635 unsigned long flags;
Martin Habets43388292005-09-10 15:39:00 +0200636
Martin Habets43388292005-09-10 15:39:00 +0200637 /* Delay if previous commands are still being processed */
Krzysztof Heltea543f12006-09-05 20:25:05 +0200638 spin_lock_irqsave(&dbri->lock, flags);
639 while ((--maxloops) > 0 && (sbus_readl(dbri->regs + REG0) & D_P)) {
640 spin_unlock_irqrestore(&dbri->lock, flags);
Martin Habets43388292005-09-10 15:39:00 +0200641 msleep_interruptible(1);
Krzysztof Heltea543f12006-09-05 20:25:05 +0200642 spin_lock_irqsave(&dbri->lock, flags);
643 }
644 spin_unlock_irqrestore(&dbri->lock, flags);
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200645
Krzysztof Heltcf68d212007-09-04 13:09:20 +0200646 if (maxloops == 0)
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200647 printk(KERN_ERR "DBRI: Chip never completed command buffer\n");
Krzysztof Heltcf68d212007-09-04 13:09:20 +0200648 else
Martin Habets43388292005-09-10 15:39:00 +0200649 dprintk(D_CMD, "Chip completed command buffer (%d)\n",
650 MAXLOOPS - maxloops - 1);
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200651}
652/*
Krzysztof Heltcf68d212007-09-04 13:09:20 +0200653 * Lock the command queue and return pointer to space for len cmd words
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200654 * It locks the cmdlock spinlock.
655 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200656static s32 *dbri_cmdlock(struct snd_dbri *dbri, int len)
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200657{
658 /* Space for 2 WAIT cmds (replaced later by 1 JUMP cmd) */
659 len += 2;
660 spin_lock(&dbri->cmdlock);
661 if (dbri->cmdptr - dbri->dma->cmd + len < DBRI_NO_CMDS - 2)
662 return dbri->cmdptr + 2;
663 else if (len < sbus_readl(dbri->regs + REG8) - dbri->dma_dvma)
664 return dbri->dma->cmd;
665 else
666 printk(KERN_ERR "DBRI: no space for commands.");
Martin Habets43388292005-09-10 15:39:00 +0200667
Al Viroae97dd92006-09-24 23:42:57 +0100668 return NULL;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200669}
670
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200671/*
Robert P. J. Daybeb7dd82007-05-09 07:14:03 +0200672 * Send prepared cmd string. It works by writing a JUMP cmd into
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200673 * the last WAIT cmd and force DBRI to reread the cmd.
Krzysztof Heltab93c7a2006-08-23 11:37:36 +0200674 * The JUMP cmd points to the new cmd string.
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200675 * It also releases the cmdlock spinlock.
Krzysztof Heltea543f12006-09-05 20:25:05 +0200676 *
Krzysztof Heltca405872006-12-18 14:41:03 +0100677 * Lock must be held before calling this.
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200678 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200679static void dbri_cmdsend(struct snd_dbri *dbri, s32 *cmd, int len)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200680{
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200681 s32 tmp, addr;
682 static int wait_id = 0;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200683
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200684 wait_id++;
685 wait_id &= 0xffff; /* restrict it to a 16 bit counter. */
686 *(cmd) = DBRI_CMD(D_WAIT, 1, wait_id);
687 *(cmd+1) = DBRI_CMD(D_WAIT, 1, wait_id);
688
689 /* Replace the last command with JUMP */
690 addr = dbri->dma_dvma + (cmd - len - dbri->dma->cmd) * sizeof(s32);
691 *(dbri->cmdptr+1) = addr;
692 *(dbri->cmdptr) = DBRI_CMD(D_JUMP, 0, 0);
693
694#ifdef DBRI_DEBUG
Krzysztof Heltab93c7a2006-08-23 11:37:36 +0200695 if (cmd > dbri->cmdptr) {
696 s32 *ptr;
697
Krzysztof Heltaaad3652006-08-28 12:59:23 +0200698 for (ptr = dbri->cmdptr; ptr < cmd+2; ptr++)
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200699 dprintk(D_CMD, "cmd: %lx:%08x\n",
700 (unsigned long)ptr, *ptr);
Krzysztof Heltab93c7a2006-08-23 11:37:36 +0200701 } else {
702 s32 *ptr = dbri->cmdptr;
703
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200704 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
Krzysztof Heltab93c7a2006-08-23 11:37:36 +0200705 ptr++;
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200706 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200707 for (ptr = dbri->dma->cmd; ptr < cmd+2; ptr++)
708 dprintk(D_CMD, "cmd: %lx:%08x\n",
709 (unsigned long)ptr, *ptr);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200710 }
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200711#endif
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200712
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200713 /* Reread the last command */
714 tmp = sbus_readl(dbri->regs + REG0);
715 tmp |= D_P;
716 sbus_writel(tmp, dbri->regs + REG0);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200717
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200718 dbri->cmdptr = cmd;
719 spin_unlock(&dbri->cmdlock);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200720}
721
722/* Lock must be held when calling this */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200723static void dbri_reset(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200724{
725 int i;
Krzysztof Heltd1fdf072006-08-21 19:29:18 +0200726 u32 tmp;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200727
728 dprintk(D_GEN, "reset 0:%x 2:%x 8:%x 9:%x\n",
729 sbus_readl(dbri->regs + REG0),
730 sbus_readl(dbri->regs + REG2),
731 sbus_readl(dbri->regs + REG8), sbus_readl(dbri->regs + REG9));
732
733 sbus_writel(D_R, dbri->regs + REG0); /* Soft Reset */
734 for (i = 0; (sbus_readl(dbri->regs + REG0) & D_R) && i < 64; i++)
735 udelay(10);
Krzysztof Heltd1fdf072006-08-21 19:29:18 +0200736
737 /* A brute approach - DBRI falls back to working burst size by itself
738 * On SS20 D_S does not work, so do not try so high. */
739 tmp = sbus_readl(dbri->regs + REG0);
740 tmp |= D_G | D_E;
741 tmp &= ~D_S;
742 sbus_writel(tmp, dbri->regs + REG0);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200743}
744
745/* Lock must not be held before calling this */
Krzysztof Heltafeacfd2007-09-05 15:05:08 +0200746static void __devinit dbri_initialize(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200747{
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200748 s32 *cmd;
Krzysztof Heltd1fdf072006-08-21 19:29:18 +0200749 u32 dma_addr;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200750 unsigned long flags;
751 int n;
752
753 spin_lock_irqsave(&dbri->lock, flags);
754
755 dbri_reset(dbri);
756
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200757 /* Initialize pipes */
758 for (n = 0; n < DBRI_NO_PIPES; n++)
759 dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1;
760
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200761 spin_lock_init(&dbri->cmdlock);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200762 /*
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200763 * Initialize the interrupt ring buffer.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200764 */
765 dma_addr = dbri->dma_dvma + dbri_dma_off(intr, 0);
Krzysztof Helt6fb98282006-08-16 12:54:29 +0200766 dbri->dma->intr[0] = dma_addr;
767 dbri->dbri_irqp = 1;
768 /*
769 * Set up the interrupt queue
770 */
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200771 spin_lock(&dbri->cmdlock);
772 cmd = dbri->cmdptr = dbri->dma->cmd;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200773 *(cmd++) = DBRI_CMD(D_IIQ, 0, 0);
774 *(cmd++) = dma_addr;
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200775 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
776 dbri->cmdptr = cmd;
777 *(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
778 *(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
779 dma_addr = dbri->dma_dvma + dbri_dma_off(cmd, 0);
780 sbus_writel(dma_addr, dbri->regs + REG8);
781 spin_unlock(&dbri->cmdlock);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200782
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200783 spin_unlock_irqrestore(&dbri->lock, flags);
Krzysztof Heltea543f12006-09-05 20:25:05 +0200784 dbri_cmdwait(dbri);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200785}
786
787/*
788****************************************************************************
789************************** DBRI data pipe management ***********************
790****************************************************************************
791
792While DBRI control functions use the command and interrupt buffers, the
793main data path takes the form of data pipes, which can be short (command
794and interrupt driven), or long (attached to DMA buffers). These functions
795provide a rudimentary means of setting up and managing the DBRI's pipes,
796but the calling functions have to make sure they respect the pipes' linked
797list ordering, among other things. The transmit and receive functions
798here interface closely with the transmit and receive interrupt code.
799
800*/
Krzysztof Heltcf68d212007-09-04 13:09:20 +0200801static inline int pipe_active(struct snd_dbri *dbri, int pipe)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200802{
803 return ((pipe >= 0) && (dbri->pipes[pipe].desc != -1));
804}
805
806/* reset_pipe(dbri, pipe)
807 *
808 * Called on an in-use pipe to clear anything being transmitted or received
809 * Lock must be held before calling this.
810 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200811static void reset_pipe(struct snd_dbri *dbri, int pipe)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200812{
813 int sdp;
814 int desc;
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200815 s32 *cmd;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200816
Krzysztof Helt470f1f12006-08-21 19:28:16 +0200817 if (pipe < 0 || pipe > DBRI_MAX_PIPE) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200818 printk(KERN_ERR "DBRI: reset_pipe called with "
819 "illegal pipe number\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200820 return;
821 }
822
823 sdp = dbri->pipes[pipe].sdp;
824 if (sdp == 0) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200825 printk(KERN_ERR "DBRI: reset_pipe called "
826 "on uninitialized pipe\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200827 return;
828 }
829
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200830 cmd = dbri_cmdlock(dbri, 3);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200831 *(cmd++) = DBRI_CMD(D_SDP, 0, sdp | D_SDP_C | D_SDP_P);
832 *(cmd++) = 0;
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200833 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
834 dbri_cmdsend(dbri, cmd, 3);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200835
836 desc = dbri->pipes[pipe].first_desc;
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200837 if (desc >= 0)
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200838 do {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200839 dbri->dma->desc[desc].ba = 0;
840 dbri->dma->desc[desc].nda = 0;
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200841 desc = dbri->next_desc[desc];
842 } while (desc != -1 && desc != dbri->pipes[pipe].first_desc);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200843
844 dbri->pipes[pipe].desc = -1;
845 dbri->pipes[pipe].first_desc = -1;
846}
847
Krzysztof Heltea543f12006-09-05 20:25:05 +0200848/*
849 * Lock must be held before calling this.
850 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200851static void setup_pipe(struct snd_dbri *dbri, int pipe, int sdp)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200852{
Krzysztof Helt470f1f12006-08-21 19:28:16 +0200853 if (pipe < 0 || pipe > DBRI_MAX_PIPE) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200854 printk(KERN_ERR "DBRI: setup_pipe called "
855 "with illegal pipe number\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200856 return;
857 }
858
859 if ((sdp & 0xf800) != sdp) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200860 printk(KERN_ERR "DBRI: setup_pipe called "
861 "with strange SDP value\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200862 /* sdp &= 0xf800; */
863 }
864
865 /* If this is a fixed receive pipe, arrange for an interrupt
866 * every time its data changes
867 */
868 if (D_SDP_MODE(sdp) == D_SDP_FIXED && !(sdp & D_SDP_TO_SER))
869 sdp |= D_SDP_CHANGE;
870
871 sdp |= D_PIPE(pipe);
872 dbri->pipes[pipe].sdp = sdp;
873 dbri->pipes[pipe].desc = -1;
874 dbri->pipes[pipe].first_desc = -1;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200875
876 reset_pipe(dbri, pipe);
877}
878
Krzysztof Heltea543f12006-09-05 20:25:05 +0200879/*
880 * Lock must be held before calling this.
881 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200882static void link_time_slot(struct snd_dbri *dbri, int pipe,
Krzysztof Helt294a30d2006-08-21 19:29:59 +0200883 int prevpipe, int nextpipe,
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200884 int length, int cycle)
885{
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200886 s32 *cmd;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200887 int val;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200888
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200889 if (pipe < 0 || pipe > DBRI_MAX_PIPE
Krzysztof Helt294a30d2006-08-21 19:29:59 +0200890 || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE
891 || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200892 printk(KERN_ERR
Martin Habets43388292005-09-10 15:39:00 +0200893 "DBRI: link_time_slot called with illegal pipe number\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200894 return;
895 }
896
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200897 if (dbri->pipes[pipe].sdp == 0
Krzysztof Helt294a30d2006-08-21 19:29:59 +0200898 || dbri->pipes[prevpipe].sdp == 0
899 || dbri->pipes[nextpipe].sdp == 0) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200900 printk(KERN_ERR "DBRI: link_time_slot called "
901 "on uninitialized pipe\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200902 return;
903 }
904
Krzysztof Helt294a30d2006-08-21 19:29:59 +0200905 dbri->pipes[prevpipe].nextpipe = pipe;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200906 dbri->pipes[pipe].nextpipe = nextpipe;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200907 dbri->pipes[pipe].length = length;
908
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200909 cmd = dbri_cmdlock(dbri, 4);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200910
Krzysztof Helt294a30d2006-08-21 19:29:59 +0200911 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
912 /* Deal with CHI special case:
913 * "If transmission on edges 0 or 1 is desired, then cycle n
914 * (where n = # of bit times per frame...) must be used."
915 * - DBRI data sheet, page 11
916 */
917 if (prevpipe == 16 && cycle == 0)
918 cycle = dbri->chi_bpf;
919
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200920 val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(prevpipe) | pipe;
921 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
922 *(cmd++) = 0;
923 *(cmd++) =
924 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
Krzysztof Helt294a30d2006-08-21 19:29:59 +0200925 } else {
926 val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(prevpipe) | pipe;
927 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
928 *(cmd++) =
929 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
930 *(cmd++) = 0;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200931 }
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200932 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200933
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200934 dbri_cmdsend(dbri, cmd, 4);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200935}
936
Krzysztof Heltea543f12006-09-05 20:25:05 +0200937#if 0
938/*
939 * Lock must be held before calling this.
940 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200941static void unlink_time_slot(struct snd_dbri *dbri, int pipe,
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200942 enum in_or_out direction, int prevpipe,
943 int nextpipe)
944{
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200945 s32 *cmd;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200946 int val;
947
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200948 if (pipe < 0 || pipe > DBRI_MAX_PIPE
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200949 || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE
950 || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200951 printk(KERN_ERR
Martin Habets43388292005-09-10 15:39:00 +0200952 "DBRI: unlink_time_slot called with illegal pipe number\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200953 return;
954 }
955
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200956 cmd = dbri_cmdlock(dbri, 4);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200957
958 if (direction == PIPEinput) {
959 val = D_DTS_VI | D_DTS_DEL | D_DTS_PRVIN(prevpipe) | pipe;
960 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
961 *(cmd++) = D_TS_NEXT(nextpipe);
962 *(cmd++) = 0;
963 } else {
964 val = D_DTS_VO | D_DTS_DEL | D_DTS_PRVOUT(prevpipe) | pipe;
965 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
966 *(cmd++) = 0;
967 *(cmd++) = D_TS_NEXT(nextpipe);
968 }
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200969 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200970
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200971 dbri_cmdsend(dbri, cmd, 4);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200972}
Krzysztof Heltea543f12006-09-05 20:25:05 +0200973#endif
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200974
975/* xmit_fixed() / recv_fixed()
976 *
977 * Transmit/receive data on a "fixed" pipe - i.e, one whose contents are not
978 * expected to change much, and which we don't need to buffer.
979 * The DBRI only interrupts us when the data changes (receive pipes),
980 * or only changes the data when this function is called (transmit pipes).
981 * Only short pipes (numbers 16-31) can be used in fixed data mode.
982 *
983 * These function operate on a 32-bit field, no matter how large
984 * the actual time slot is. The interrupt handler takes care of bit
985 * ordering and alignment. An 8-bit time slot will always end up
986 * in the low-order 8 bits, filled either MSB-first or LSB-first,
Krzysztof Heltea543f12006-09-05 20:25:05 +0200987 * depending on the settings passed to setup_pipe().
988 *
989 * Lock must not be held before calling it.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200990 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200991static void xmit_fixed(struct snd_dbri *dbri, int pipe, unsigned int data)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200992{
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200993 s32 *cmd;
Krzysztof Heltea543f12006-09-05 20:25:05 +0200994 unsigned long flags;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200995
Krzysztof Helt470f1f12006-08-21 19:28:16 +0200996 if (pipe < 16 || pipe > DBRI_MAX_PIPE) {
Martin Habets43388292005-09-10 15:39:00 +0200997 printk(KERN_ERR "DBRI: xmit_fixed: Illegal pipe number\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200998 return;
999 }
1000
1001 if (D_SDP_MODE(dbri->pipes[pipe].sdp) == 0) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001002 printk(KERN_ERR "DBRI: xmit_fixed: "
1003 "Uninitialized pipe %d\n", pipe);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001004 return;
1005 }
1006
1007 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
Martin Habets43388292005-09-10 15:39:00 +02001008 printk(KERN_ERR "DBRI: xmit_fixed: Non-fixed pipe %d\n", pipe);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001009 return;
1010 }
1011
1012 if (!(dbri->pipes[pipe].sdp & D_SDP_TO_SER)) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001013 printk(KERN_ERR "DBRI: xmit_fixed: Called on receive pipe %d\n",
1014 pipe);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001015 return;
1016 }
1017
1018 /* DBRI short pipes always transmit LSB first */
1019
1020 if (dbri->pipes[pipe].sdp & D_SDP_MSB)
1021 data = reverse_bytes(data, dbri->pipes[pipe].length);
1022
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001023 cmd = dbri_cmdlock(dbri, 3);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001024
1025 *(cmd++) = DBRI_CMD(D_SSP, 0, pipe);
1026 *(cmd++) = data;
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001027 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001028
Krzysztof Heltea543f12006-09-05 20:25:05 +02001029 spin_lock_irqsave(&dbri->lock, flags);
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001030 dbri_cmdsend(dbri, cmd, 3);
Krzysztof Heltea543f12006-09-05 20:25:05 +02001031 spin_unlock_irqrestore(&dbri->lock, flags);
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001032 dbri_cmdwait(dbri);
Krzysztof Heltea543f12006-09-05 20:25:05 +02001033
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001034}
1035
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001036static void recv_fixed(struct snd_dbri *dbri, int pipe, volatile __u32 *ptr)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001037{
Krzysztof Helt470f1f12006-08-21 19:28:16 +02001038 if (pipe < 16 || pipe > DBRI_MAX_PIPE) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001039 printk(KERN_ERR "DBRI: recv_fixed called with "
1040 "illegal pipe number\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001041 return;
1042 }
1043
1044 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001045 printk(KERN_ERR "DBRI: recv_fixed called on "
1046 "non-fixed pipe %d\n", pipe);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001047 return;
1048 }
1049
1050 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001051 printk(KERN_ERR "DBRI: recv_fixed called on "
1052 "transmit pipe %d\n", pipe);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001053 return;
1054 }
1055
1056 dbri->pipes[pipe].recv_fixed_ptr = ptr;
1057}
1058
1059/* setup_descs()
1060 *
1061 * Setup transmit/receive data on a "long" pipe - i.e, one associated
1062 * with a DMA buffer.
1063 *
1064 * Only pipe numbers 0-15 can be used in this mode.
1065 *
1066 * This function takes a stream number pointing to a data buffer,
1067 * and work by building chains of descriptors which identify the
1068 * data buffers. Buffers too large for a single descriptor will
1069 * be spread across multiple descriptors.
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001070 *
1071 * All descriptors create a ring buffer.
Krzysztof Heltea543f12006-09-05 20:25:05 +02001072 *
1073 * Lock must be held before calling this.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001074 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001075static int setup_descs(struct snd_dbri *dbri, int streamno, unsigned int period)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001076{
Takashi Iwai475675d2005-11-17 15:11:51 +01001077 struct dbri_streaminfo *info = &dbri->stream_info[streamno];
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001078 __u32 dvma_buffer;
Krzysztof Helt99dabfe2006-08-28 13:00:45 +02001079 int desc;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001080 int len;
1081 int first_desc = -1;
1082 int last_desc = -1;
1083
1084 if (info->pipe < 0 || info->pipe > 15) {
Martin Habets43388292005-09-10 15:39:00 +02001085 printk(KERN_ERR "DBRI: setup_descs: Illegal pipe number\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001086 return -2;
1087 }
1088
1089 if (dbri->pipes[info->pipe].sdp == 0) {
Martin Habets43388292005-09-10 15:39:00 +02001090 printk(KERN_ERR "DBRI: setup_descs: Uninitialized pipe %d\n",
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001091 info->pipe);
1092 return -2;
1093 }
1094
1095 dvma_buffer = info->dvma_buffer;
1096 len = info->size;
1097
1098 if (streamno == DBRI_PLAY) {
1099 if (!(dbri->pipes[info->pipe].sdp & D_SDP_TO_SER)) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001100 printk(KERN_ERR "DBRI: setup_descs: "
1101 "Called on receive pipe %d\n", info->pipe);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001102 return -2;
1103 }
1104 } else {
1105 if (dbri->pipes[info->pipe].sdp & D_SDP_TO_SER) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001106 printk(KERN_ERR
Martin Habets43388292005-09-10 15:39:00 +02001107 "DBRI: setup_descs: Called on transmit pipe %d\n",
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001108 info->pipe);
1109 return -2;
1110 }
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001111 /* Should be able to queue multiple buffers
1112 * to receive on a pipe
1113 */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001114 if (pipe_active(dbri, info->pipe)) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001115 printk(KERN_ERR "DBRI: recv_on_pipe: "
1116 "Called on active pipe %d\n", info->pipe);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001117 return -2;
1118 }
1119
1120 /* Make sure buffer size is multiple of four */
1121 len &= ~3;
1122 }
1123
Krzysztof Helt99dabfe2006-08-28 13:00:45 +02001124 /* Free descriptors if pipe has any */
1125 desc = dbri->pipes[info->pipe].first_desc;
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001126 if (desc >= 0)
Krzysztof Helt99dabfe2006-08-28 13:00:45 +02001127 do {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001128 dbri->dma->desc[desc].ba = 0;
1129 dbri->dma->desc[desc].nda = 0;
Krzysztof Helt99dabfe2006-08-28 13:00:45 +02001130 desc = dbri->next_desc[desc];
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001131 } while (desc != -1 &&
1132 desc != dbri->pipes[info->pipe].first_desc);
Krzysztof Helt99dabfe2006-08-28 13:00:45 +02001133
1134 dbri->pipes[info->pipe].desc = -1;
1135 dbri->pipes[info->pipe].first_desc = -1;
1136
1137 desc = 0;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001138 while (len > 0) {
1139 int mylen;
1140
1141 for (; desc < DBRI_NO_DESCS; desc++) {
Krzysztof Heltc2735442006-08-21 19:27:35 +02001142 if (!dbri->dma->desc[desc].ba)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001143 break;
1144 }
Krzysztof Heltcf68d212007-09-04 13:09:20 +02001145
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001146 if (desc == DBRI_NO_DESCS) {
Martin Habets43388292005-09-10 15:39:00 +02001147 printk(KERN_ERR "DBRI: setup_descs: No descriptors\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001148 return -1;
1149 }
1150
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001151 if (len > DBRI_TD_MAXCNT)
1152 mylen = DBRI_TD_MAXCNT; /* 8KB - 4 */
1153 else
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001154 mylen = len;
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001155
1156 if (mylen > period)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001157 mylen = period;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001158
Krzysztof Heltc2735442006-08-21 19:27:35 +02001159 dbri->next_desc[desc] = -1;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001160 dbri->dma->desc[desc].ba = dvma_buffer;
1161 dbri->dma->desc[desc].nda = 0;
1162
1163 if (streamno == DBRI_PLAY) {
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001164 dbri->dma->desc[desc].word1 = DBRI_TD_CNT(mylen);
1165 dbri->dma->desc[desc].word4 = 0;
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001166 dbri->dma->desc[desc].word1 |= DBRI_TD_F | DBRI_TD_B;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001167 } else {
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001168 dbri->dma->desc[desc].word1 = 0;
1169 dbri->dma->desc[desc].word4 =
1170 DBRI_RD_B | DBRI_RD_BCNT(mylen);
1171 }
1172
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001173 if (first_desc == -1)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001174 first_desc = desc;
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001175 else {
Krzysztof Heltc2735442006-08-21 19:27:35 +02001176 dbri->next_desc[last_desc] = desc;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001177 dbri->dma->desc[last_desc].nda =
1178 dbri->dma_dvma + dbri_dma_off(desc, desc);
1179 }
1180
1181 last_desc = desc;
1182 dvma_buffer += mylen;
1183 len -= mylen;
1184 }
1185
1186 if (first_desc == -1 || last_desc == -1) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001187 printk(KERN_ERR "DBRI: setup_descs: "
1188 " Not enough descriptors available\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001189 return -1;
1190 }
1191
Krzysztof Heltaaad3652006-08-28 12:59:23 +02001192 dbri->dma->desc[last_desc].nda =
1193 dbri->dma_dvma + dbri_dma_off(desc, first_desc);
1194 dbri->next_desc[last_desc] = first_desc;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001195 dbri->pipes[info->pipe].first_desc = first_desc;
1196 dbri->pipes[info->pipe].desc = first_desc;
1197
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001198#ifdef DBRI_DEBUG
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001199 for (desc = first_desc; desc != -1;) {
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001200 dprintk(D_DESC, "DESC %d: %08x %08x %08x %08x\n",
1201 desc,
1202 dbri->dma->desc[desc].word1,
1203 dbri->dma->desc[desc].ba,
1204 dbri->dma->desc[desc].nda, dbri->dma->desc[desc].word4);
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001205 desc = dbri->next_desc[desc];
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001206 if (desc == first_desc)
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001207 break;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001208 }
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001209#endif
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001210 return 0;
1211}
1212
1213/*
1214****************************************************************************
1215************************** DBRI - CHI interface ****************************
1216****************************************************************************
1217
1218The CHI is a four-wire (clock, frame sync, data in, data out) time-division
1219multiplexed serial interface which the DBRI can operate in either master
1220(give clock/frame sync) or slave (take clock/frame sync) mode.
1221
1222*/
1223
1224enum master_or_slave { CHImaster, CHIslave };
1225
Krzysztof Heltea543f12006-09-05 20:25:05 +02001226/*
1227 * Lock must not be held before calling it.
1228 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001229static void reset_chi(struct snd_dbri *dbri,
1230 enum master_or_slave master_or_slave,
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001231 int bits_per_frame)
1232{
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001233 s32 *cmd;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001234 int val;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001235
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001236 /* Set CHI Anchor: Pipe 16 */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001237
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001238 cmd = dbri_cmdlock(dbri, 4);
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001239 val = D_DTS_VO | D_DTS_VI | D_DTS_INS
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001240 | D_DTS_PRVIN(16) | D_PIPE(16) | D_DTS_PRVOUT(16);
1241 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
1242 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1243 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1244 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1245 dbri_cmdsend(dbri, cmd, 4);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001246
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001247 dbri->pipes[16].sdp = 1;
1248 dbri->pipes[16].nextpipe = 16;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001249
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001250 cmd = dbri_cmdlock(dbri, 4);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001251
1252 if (master_or_slave == CHIslave) {
1253 /* Setup DBRI for CHI Slave - receive clock, frame sync (FS)
1254 *
1255 * CHICM = 0 (slave mode, 8 kHz frame rate)
1256 * IR = give immediate CHI status interrupt
1257 * EN = give CHI status interrupt upon change
1258 */
1259 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(0));
1260 } else {
1261 /* Setup DBRI for CHI Master - generate clock, FS
1262 *
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001263 * BPF = bits per 8 kHz frame
1264 * 12.288 MHz / CHICM_divisor = clock rate
1265 * FD = 1 - drive CHIFS on rising edge of CHICK
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001266 */
1267 int clockrate = bits_per_frame * 8;
1268 int divisor = 12288 / clockrate;
1269
1270 if (divisor > 255 || divisor * clockrate != 12288)
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001271 printk(KERN_ERR "DBRI: illegal bits_per_frame "
1272 "in setup_chi\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001273
1274 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(divisor) | D_CHI_FD
1275 | D_CHI_BPF(bits_per_frame));
1276 }
1277
1278 dbri->chi_bpf = bits_per_frame;
1279
1280 /* CHI Data Mode
1281 *
1282 * RCE = 0 - receive on falling edge of CHICK
1283 * XCE = 1 - transmit on rising edge of CHICK
1284 * XEN = 1 - enable transmitter
1285 * REN = 1 - enable receiver
1286 */
1287
1288 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1289 *(cmd++) = DBRI_CMD(D_CDM, 0, D_CDM_XCE | D_CDM_XEN | D_CDM_REN);
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001290 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001291
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001292 dbri_cmdsend(dbri, cmd, 4);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001293}
1294
1295/*
1296****************************************************************************
1297*********************** CS4215 audio codec management **********************
1298****************************************************************************
1299
1300In the standard SPARC audio configuration, the CS4215 codec is attached
1301to the DBRI via the CHI interface and few of the DBRI's PIO pins.
1302
Krzysztof Heltea543f12006-09-05 20:25:05 +02001303 * Lock must not be held before calling it.
1304
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001305*/
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02001306static __devinit void cs4215_setup_pipes(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001307{
Krzysztof Heltea543f12006-09-05 20:25:05 +02001308 unsigned long flags;
1309
1310 spin_lock_irqsave(&dbri->lock, flags);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001311 /*
1312 * Data mode:
1313 * Pipe 4: Send timeslots 1-4 (audio data)
1314 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1315 * Pipe 6: Receive timeslots 1-4 (audio data)
1316 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1317 * interrupt, and the rest of the data (slot 5 and 8) is
1318 * not relevant for us (only for doublechecking).
1319 *
1320 * Control mode:
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001321 * Pipe 17: Send timeslots 1-4 (slots 5-8 are read only)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001322 * Pipe 18: Receive timeslot 1 (clb).
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001323 * Pipe 19: Receive timeslot 7 (version).
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001324 */
1325
1326 setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB);
1327 setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1328 setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB);
1329 setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1330
1331 setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1332 setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1333 setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
Krzysztof Heltea543f12006-09-05 20:25:05 +02001334 spin_unlock_irqrestore(&dbri->lock, flags);
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001335
1336 dbri_cmdwait(dbri);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001337}
1338
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02001339static __devinit int cs4215_init_data(struct cs4215 *mm)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001340{
1341 /*
1342 * No action, memory resetting only.
1343 *
1344 * Data Time Slot 5-8
1345 * Speaker,Line and Headphone enable. Gain set to the half.
1346 * Input is mike.
1347 */
1348 mm->data[0] = CS4215_LO(0x20) | CS4215_HE | CS4215_LE;
1349 mm->data[1] = CS4215_RO(0x20) | CS4215_SE;
1350 mm->data[2] = CS4215_LG(0x8) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1;
1351 mm->data[3] = CS4215_RG(0x8) | CS4215_MA(0xf);
1352
1353 /*
1354 * Control Time Slot 1-4
1355 * 0: Default I/O voltage scale
1356 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled
1357 * 2: Serial enable, CHI master, 128 bits per frame, clock 1
1358 * 3: Tests disabled
1359 */
1360 mm->ctrl[0] = CS4215_RSRVD_1 | CS4215_MLB;
1361 mm->ctrl[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval;
1362 mm->ctrl[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal;
1363 mm->ctrl[3] = 0;
1364
1365 mm->status = 0;
1366 mm->version = 0xff;
1367 mm->precision = 8; /* For ULAW */
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001368 mm->channels = 1;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001369
1370 return 0;
1371}
1372
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001373static void cs4215_setdata(struct snd_dbri *dbri, int muted)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001374{
1375 if (muted) {
1376 dbri->mm.data[0] |= 63;
1377 dbri->mm.data[1] |= 63;
1378 dbri->mm.data[2] &= ~15;
1379 dbri->mm.data[3] &= ~15;
1380 } else {
1381 /* Start by setting the playback attenuation. */
Takashi Iwai475675d2005-11-17 15:11:51 +01001382 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
Krzysztof Helt470f1f12006-08-21 19:28:16 +02001383 int left_gain = info->left_gain & 0x3f;
1384 int right_gain = info->right_gain & 0x3f;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001385
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001386 dbri->mm.data[0] &= ~0x3f; /* Reset the volume bits */
1387 dbri->mm.data[1] &= ~0x3f;
1388 dbri->mm.data[0] |= (DBRI_MAX_VOLUME - left_gain);
1389 dbri->mm.data[1] |= (DBRI_MAX_VOLUME - right_gain);
1390
1391 /* Now set the recording gain. */
1392 info = &dbri->stream_info[DBRI_REC];
Krzysztof Helt470f1f12006-08-21 19:28:16 +02001393 left_gain = info->left_gain & 0xf;
1394 right_gain = info->right_gain & 0xf;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001395 dbri->mm.data[2] |= CS4215_LG(left_gain);
1396 dbri->mm.data[3] |= CS4215_RG(right_gain);
1397 }
1398
1399 xmit_fixed(dbri, 20, *(int *)dbri->mm.data);
1400}
1401
1402/*
1403 * Set the CS4215 to data mode.
1404 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001405static void cs4215_open(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001406{
1407 int data_width;
1408 u32 tmp;
Krzysztof Heltea543f12006-09-05 20:25:05 +02001409 unsigned long flags;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001410
1411 dprintk(D_MM, "cs4215_open: %d channels, %d bits\n",
1412 dbri->mm.channels, dbri->mm.precision);
1413
1414 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1415 * to make sure this takes. This avoids clicking noises.
1416 */
1417
1418 cs4215_setdata(dbri, 1);
1419 udelay(125);
1420
1421 /*
1422 * Data mode:
1423 * Pipe 4: Send timeslots 1-4 (audio data)
1424 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1425 * Pipe 6: Receive timeslots 1-4 (audio data)
1426 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1427 * interrupt, and the rest of the data (slot 5 and 8) is
1428 * not relevant for us (only for doublechecking).
1429 *
1430 * Just like in control mode, the time slots are all offset by eight
1431 * bits. The CS4215, it seems, observes TSIN (the delayed signal)
1432 * even if it's the CHI master. Don't ask me...
1433 */
Krzysztof Heltea543f12006-09-05 20:25:05 +02001434 spin_lock_irqsave(&dbri->lock, flags);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001435 tmp = sbus_readl(dbri->regs + REG0);
1436 tmp &= ~(D_C); /* Disable CHI */
1437 sbus_writel(tmp, dbri->regs + REG0);
1438
1439 /* Switch CS4215 to data mode - set PIO3 to 1 */
1440 sbus_writel(D_ENPIO | D_PIO1 | D_PIO3 |
1441 (dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2);
1442
1443 reset_chi(dbri, CHIslave, 128);
1444
1445 /* Note: this next doesn't work for 8-bit stereo, because the two
1446 * channels would be on timeslots 1 and 3, with 2 and 4 idle.
1447 * (See CS4215 datasheet Fig 15)
1448 *
1449 * DBRI non-contiguous mode would be required to make this work.
1450 */
1451 data_width = dbri->mm.channels * dbri->mm.precision;
1452
Krzysztof Helt294a30d2006-08-21 19:29:59 +02001453 link_time_slot(dbri, 4, 16, 16, data_width, dbri->mm.offset);
1454 link_time_slot(dbri, 20, 4, 16, 32, dbri->mm.offset + 32);
1455 link_time_slot(dbri, 6, 16, 16, data_width, dbri->mm.offset);
1456 link_time_slot(dbri, 21, 6, 16, 16, dbri->mm.offset + 40);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001457
1458 /* FIXME: enable CHI after _setdata? */
1459 tmp = sbus_readl(dbri->regs + REG0);
1460 tmp |= D_C; /* Enable CHI */
1461 sbus_writel(tmp, dbri->regs + REG0);
Krzysztof Heltea543f12006-09-05 20:25:05 +02001462 spin_unlock_irqrestore(&dbri->lock, flags);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001463
1464 cs4215_setdata(dbri, 0);
1465}
1466
1467/*
1468 * Send the control information (i.e. audio format)
1469 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001470static int cs4215_setctrl(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001471{
1472 int i, val;
1473 u32 tmp;
Krzysztof Heltea543f12006-09-05 20:25:05 +02001474 unsigned long flags;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001475
1476 /* FIXME - let the CPU do something useful during these delays */
1477
1478 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1479 * to make sure this takes. This avoids clicking noises.
1480 */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001481 cs4215_setdata(dbri, 1);
1482 udelay(125);
1483
1484 /*
1485 * Enable Control mode: Set DBRI's PIO3 (4215's D/~C) to 0, then wait
1486 * 12 cycles <= 12/(5512.5*64) sec = 34.01 usec
1487 */
1488 val = D_ENPIO | D_PIO1 | (dbri->mm.onboard ? D_PIO0 : D_PIO2);
1489 sbus_writel(val, dbri->regs + REG2);
1490 dprintk(D_MM, "cs4215_setctrl: reg2=0x%x\n", val);
1491 udelay(34);
1492
1493 /* In Control mode, the CS4215 is a slave device, so the DBRI must
1494 * operate as CHI master, supplying clocking and frame synchronization.
1495 *
1496 * In Data mode, however, the CS4215 must be CHI master to insure
1497 * that its data stream is synchronous with its codec.
1498 *
1499 * The upshot of all this? We start by putting the DBRI into master
1500 * mode, program the CS4215 in Control mode, then switch the CS4215
1501 * into Data mode and put the DBRI into slave mode. Various timing
1502 * requirements must be observed along the way.
1503 *
1504 * Oh, and one more thing, on a SPARCStation 20 (and maybe
1505 * others?), the addressing of the CS4215's time slots is
1506 * offset by eight bits, so we add eight to all the "cycle"
1507 * values in the Define Time Slot (DTS) commands. This is
1508 * done in hardware by a TI 248 that delays the DBRI->4215
1509 * frame sync signal by eight clock cycles. Anybody know why?
1510 */
Krzysztof Heltea543f12006-09-05 20:25:05 +02001511 spin_lock_irqsave(&dbri->lock, flags);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001512 tmp = sbus_readl(dbri->regs + REG0);
1513 tmp &= ~D_C; /* Disable CHI */
1514 sbus_writel(tmp, dbri->regs + REG0);
1515
1516 reset_chi(dbri, CHImaster, 128);
1517
1518 /*
1519 * Control mode:
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001520 * Pipe 17: Send timeslots 1-4 (slots 5-8 are read only)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001521 * Pipe 18: Receive timeslot 1 (clb).
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001522 * Pipe 19: Receive timeslot 7 (version).
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001523 */
1524
Krzysztof Helt294a30d2006-08-21 19:29:59 +02001525 link_time_slot(dbri, 17, 16, 16, 32, dbri->mm.offset);
1526 link_time_slot(dbri, 18, 16, 16, 8, dbri->mm.offset);
1527 link_time_slot(dbri, 19, 18, 16, 8, dbri->mm.offset + 48);
Krzysztof Heltea543f12006-09-05 20:25:05 +02001528 spin_unlock_irqrestore(&dbri->lock, flags);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001529
1530 /* Wait for the chip to echo back CLB (Control Latch Bit) as zero */
1531 dbri->mm.ctrl[0] &= ~CS4215_CLB;
1532 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1533
Krzysztof Heltea543f12006-09-05 20:25:05 +02001534 spin_lock_irqsave(&dbri->lock, flags);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001535 tmp = sbus_readl(dbri->regs + REG0);
1536 tmp |= D_C; /* Enable CHI */
1537 sbus_writel(tmp, dbri->regs + REG0);
Krzysztof Heltea543f12006-09-05 20:25:05 +02001538 spin_unlock_irqrestore(&dbri->lock, flags);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001539
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001540 for (i = 10; ((dbri->mm.status & 0xe4) != 0x20); --i)
Martin Habets43388292005-09-10 15:39:00 +02001541 msleep_interruptible(1);
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001542
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001543 if (i == 0) {
1544 dprintk(D_MM, "CS4215 didn't respond to CLB (0x%02x)\n",
1545 dbri->mm.status);
1546 return -1;
1547 }
1548
1549 /* Disable changes to our copy of the version number, as we are about
1550 * to leave control mode.
1551 */
1552 recv_fixed(dbri, 19, NULL);
1553
1554 /* Terminate CS4215 control mode - data sheet says
1555 * "Set CLB=1 and send two more frames of valid control info"
1556 */
1557 dbri->mm.ctrl[0] |= CS4215_CLB;
1558 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1559
1560 /* Two frames of control info @ 8kHz frame rate = 250 us delay */
1561 udelay(250);
1562
1563 cs4215_setdata(dbri, 0);
1564
1565 return 0;
1566}
1567
1568/*
1569 * Setup the codec with the sampling rate, audio format and number of
1570 * channels.
1571 * As part of the process we resend the settings for the data
1572 * timeslots as well.
1573 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001574static int cs4215_prepare(struct snd_dbri *dbri, unsigned int rate,
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001575 snd_pcm_format_t format, unsigned int channels)
1576{
1577 int freq_idx;
1578 int ret = 0;
1579
1580 /* Lookup index for this rate */
1581 for (freq_idx = 0; CS4215_FREQ[freq_idx].freq != 0; freq_idx++) {
1582 if (CS4215_FREQ[freq_idx].freq == rate)
1583 break;
1584 }
1585 if (CS4215_FREQ[freq_idx].freq != rate) {
1586 printk(KERN_WARNING "DBRI: Unsupported rate %d Hz\n", rate);
1587 return -1;
1588 }
1589
1590 switch (format) {
1591 case SNDRV_PCM_FORMAT_MU_LAW:
1592 dbri->mm.ctrl[1] = CS4215_DFR_ULAW;
1593 dbri->mm.precision = 8;
1594 break;
1595 case SNDRV_PCM_FORMAT_A_LAW:
1596 dbri->mm.ctrl[1] = CS4215_DFR_ALAW;
1597 dbri->mm.precision = 8;
1598 break;
1599 case SNDRV_PCM_FORMAT_U8:
1600 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR8;
1601 dbri->mm.precision = 8;
1602 break;
1603 case SNDRV_PCM_FORMAT_S16_BE:
1604 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR16;
1605 dbri->mm.precision = 16;
1606 break;
1607 default:
1608 printk(KERN_WARNING "DBRI: Unsupported format %d\n", format);
1609 return -1;
1610 }
1611
1612 /* Add rate parameters */
1613 dbri->mm.ctrl[1] |= CS4215_FREQ[freq_idx].csval;
1614 dbri->mm.ctrl[2] = CS4215_XCLK |
1615 CS4215_BSEL_128 | CS4215_FREQ[freq_idx].xtal;
1616
1617 dbri->mm.channels = channels;
Krzysztof Heltab93c7a2006-08-23 11:37:36 +02001618 if (channels == 2)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001619 dbri->mm.ctrl[1] |= CS4215_DFR_STEREO;
1620
1621 ret = cs4215_setctrl(dbri);
1622 if (ret == 0)
1623 cs4215_open(dbri); /* set codec to data mode */
1624
1625 return ret;
1626}
1627
1628/*
1629 *
1630 */
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02001631static __devinit int cs4215_init(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001632{
1633 u32 reg2 = sbus_readl(dbri->regs + REG2);
1634 dprintk(D_MM, "cs4215_init: reg2=0x%x\n", reg2);
1635
1636 /* Look for the cs4215 chips */
1637 if (reg2 & D_PIO2) {
1638 dprintk(D_MM, "Onboard CS4215 detected\n");
1639 dbri->mm.onboard = 1;
1640 }
1641 if (reg2 & D_PIO0) {
1642 dprintk(D_MM, "Speakerbox detected\n");
1643 dbri->mm.onboard = 0;
1644
1645 if (reg2 & D_PIO2) {
1646 printk(KERN_INFO "DBRI: Using speakerbox / "
1647 "ignoring onboard mmcodec.\n");
1648 sbus_writel(D_ENPIO2, dbri->regs + REG2);
1649 }
1650 }
1651
1652 if (!(reg2 & (D_PIO0 | D_PIO2))) {
1653 printk(KERN_ERR "DBRI: no mmcodec found.\n");
1654 return -EIO;
1655 }
1656
1657 cs4215_setup_pipes(dbri);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001658 cs4215_init_data(&dbri->mm);
1659
1660 /* Enable capture of the status & version timeslots. */
1661 recv_fixed(dbri, 18, &dbri->mm.status);
1662 recv_fixed(dbri, 19, &dbri->mm.version);
1663
1664 dbri->mm.offset = dbri->mm.onboard ? 0 : 8;
1665 if (cs4215_setctrl(dbri) == -1 || dbri->mm.version == 0xff) {
1666 dprintk(D_MM, "CS4215 failed probe at offset %d\n",
1667 dbri->mm.offset);
1668 return -EIO;
1669 }
1670 dprintk(D_MM, "Found CS4215 at offset %d\n", dbri->mm.offset);
1671
1672 return 0;
1673}
1674
1675/*
1676****************************************************************************
1677*************************** DBRI interrupt handler *************************
1678****************************************************************************
1679
1680The DBRI communicates with the CPU mainly via a circular interrupt
1681buffer. When an interrupt is signaled, the CPU walks through the
1682buffer and calls dbri_process_one_interrupt() for each interrupt word.
1683Complicated interrupts are handled by dedicated functions (which
1684appear first in this file). Any pending interrupts can be serviced by
1685calling dbri_process_interrupt_buffer(), which works even if the CPU's
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001686interrupts are disabled.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001687
1688*/
1689
1690/* xmit_descs()
1691 *
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001692 * Starts transmitting the current TD's for recording/playing.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001693 * For playback, ALSA has filled the DMA memory with new data (we hope).
1694 */
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001695static void xmit_descs(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001696{
Takashi Iwai475675d2005-11-17 15:11:51 +01001697 struct dbri_streaminfo *info;
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001698 s32 *cmd;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001699 unsigned long flags;
1700 int first_td;
1701
1702 if (dbri == NULL)
1703 return; /* Disabled */
1704
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001705 info = &dbri->stream_info[DBRI_REC];
1706 spin_lock_irqsave(&dbri->lock, flags);
1707
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001708 if (info->pipe >= 0) {
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001709 first_td = dbri->pipes[info->pipe].first_desc;
1710
1711 dprintk(D_DESC, "xmit_descs rec @ TD %d\n", first_td);
1712
1713 /* Stream could be closed by the time we run. */
Krzysztof Heltaaad3652006-08-28 12:59:23 +02001714 if (first_td >= 0) {
1715 cmd = dbri_cmdlock(dbri, 2);
1716 *(cmd++) = DBRI_CMD(D_SDP, 0,
1717 dbri->pipes[info->pipe].sdp
1718 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001719 *(cmd++) = dbri->dma_dvma +
1720 dbri_dma_off(desc, first_td);
Krzysztof Heltaaad3652006-08-28 12:59:23 +02001721 dbri_cmdsend(dbri, cmd, 2);
1722
1723 /* Reset our admin of the pipe. */
1724 dbri->pipes[info->pipe].desc = first_td;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001725 }
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001726 }
1727
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001728 info = &dbri->stream_info[DBRI_PLAY];
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001729
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001730 if (info->pipe >= 0) {
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001731 first_td = dbri->pipes[info->pipe].first_desc;
1732
1733 dprintk(D_DESC, "xmit_descs play @ TD %d\n", first_td);
1734
1735 /* Stream could be closed by the time we run. */
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001736 if (first_td >= 0) {
1737 cmd = dbri_cmdlock(dbri, 2);
1738 *(cmd++) = DBRI_CMD(D_SDP, 0,
1739 dbri->pipes[info->pipe].sdp
1740 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001741 *(cmd++) = dbri->dma_dvma +
1742 dbri_dma_off(desc, first_td);
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001743 dbri_cmdsend(dbri, cmd, 2);
1744
Krzysztof Heltaaad3652006-08-28 12:59:23 +02001745 /* Reset our admin of the pipe. */
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001746 dbri->pipes[info->pipe].desc = first_td;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001747 }
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001748 }
Krzysztof Heltea543f12006-09-05 20:25:05 +02001749
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001750 spin_unlock_irqrestore(&dbri->lock, flags);
1751}
1752
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001753/* transmission_complete_intr()
1754 *
1755 * Called by main interrupt handler when DBRI signals transmission complete
1756 * on a pipe (interrupt triggered by the B bit in a transmit descriptor).
1757 *
Martin Habets43388292005-09-10 15:39:00 +02001758 * Walks through the pipe's list of transmit buffer descriptors and marks
1759 * them as available. Stops when the first descriptor is found without
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001760 * TBC (Transmit Buffer Complete) set, or we've run through them all.
Martin Habets43388292005-09-10 15:39:00 +02001761 *
Krzysztof Heltab93c7a2006-08-23 11:37:36 +02001762 * The DMA buffers are not released. They form a ring buffer and
1763 * they are filled by ALSA while others are transmitted by DMA.
1764 *
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001765 */
1766
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001767static void transmission_complete_intr(struct snd_dbri *dbri, int pipe)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001768{
Krzysztof Heltcf68d212007-09-04 13:09:20 +02001769 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
1770 int td = dbri->pipes[pipe].desc;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001771 int status;
1772
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001773 while (td >= 0) {
1774 if (td >= DBRI_NO_DESCS) {
1775 printk(KERN_ERR "DBRI: invalid td on pipe %d\n", pipe);
1776 return;
1777 }
1778
1779 status = DBRI_TD_STATUS(dbri->dma->desc[td].word4);
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001780 if (!(status & DBRI_TD_TBC))
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001781 break;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001782
1783 dprintk(D_INT, "TD %d, status 0x%02x\n", td, status);
1784
1785 dbri->dma->desc[td].word4 = 0; /* Reset it for next time. */
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001786 info->offset += DBRI_RD_CNT(dbri->dma->desc[td].word1);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001787
Krzysztof Heltc2735442006-08-21 19:27:35 +02001788 td = dbri->next_desc[td];
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001789 dbri->pipes[pipe].desc = td;
1790 }
1791
1792 /* Notify ALSA */
Krzysztof Heltcf68d212007-09-04 13:09:20 +02001793 spin_unlock(&dbri->lock);
1794 snd_pcm_period_elapsed(info->substream);
1795 spin_lock(&dbri->lock);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001796}
1797
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001798static void reception_complete_intr(struct snd_dbri *dbri, int pipe)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001799{
Takashi Iwai475675d2005-11-17 15:11:51 +01001800 struct dbri_streaminfo *info;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001801 int rd = dbri->pipes[pipe].desc;
1802 s32 status;
1803
1804 if (rd < 0 || rd >= DBRI_NO_DESCS) {
1805 printk(KERN_ERR "DBRI: invalid rd on pipe %d\n", pipe);
1806 return;
1807 }
1808
Krzysztof Heltc2735442006-08-21 19:27:35 +02001809 dbri->pipes[pipe].desc = dbri->next_desc[rd];
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001810 status = dbri->dma->desc[rd].word1;
1811 dbri->dma->desc[rd].word1 = 0; /* Reset it for next time. */
1812
1813 info = &dbri->stream_info[DBRI_REC];
1814 info->offset += DBRI_RD_CNT(status);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001815
1816 /* FIXME: Check status */
1817
1818 dprintk(D_INT, "Recv RD %d, status 0x%02x, len %d\n",
1819 rd, DBRI_RD_STATUS(status), DBRI_RD_CNT(status));
1820
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001821 /* Notify ALSA */
Krzysztof Heltcf68d212007-09-04 13:09:20 +02001822 spin_unlock(&dbri->lock);
1823 snd_pcm_period_elapsed(info->substream);
1824 spin_lock(&dbri->lock);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001825}
1826
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001827static void dbri_process_one_interrupt(struct snd_dbri *dbri, int x)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001828{
1829 int val = D_INTR_GETVAL(x);
1830 int channel = D_INTR_GETCHAN(x);
1831 int command = D_INTR_GETCMD(x);
1832 int code = D_INTR_GETCODE(x);
1833#ifdef DBRI_DEBUG
1834 int rval = D_INTR_GETRVAL(x);
1835#endif
1836
1837 if (channel == D_INTR_CMD) {
1838 dprintk(D_CMD, "INTR: Command: %-5s Value:%d\n",
1839 cmds[command], val);
1840 } else {
1841 dprintk(D_INT, "INTR: Chan:%d Code:%d Val:%#x\n",
1842 channel, code, rval);
1843 }
1844
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001845 switch (code) {
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001846 case D_INTR_CMDI:
1847 if (command != D_WAIT)
1848 printk(KERN_ERR "DBRI: Command read interrupt\n");
1849 break;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001850 case D_INTR_BRDY:
1851 reception_complete_intr(dbri, channel);
1852 break;
1853 case D_INTR_XCMP:
1854 case D_INTR_MINT:
1855 transmission_complete_intr(dbri, channel);
1856 break;
1857 case D_INTR_UNDR:
1858 /* UNDR - Transmission underrun
1859 * resend SDP command with clear pipe bit (C) set
1860 */
1861 {
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001862 /* FIXME: do something useful in case of underrun */
1863 printk(KERN_ERR "DBRI: Underrun error\n");
1864#if 0
1865 s32 *cmd;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001866 int pipe = channel;
1867 int td = dbri->pipes[pipe].desc;
1868
1869 dbri->dma->desc[td].word4 = 0;
1870 cmd = dbri_cmdlock(dbri, NoGetLock);
1871 *(cmd++) = DBRI_CMD(D_SDP, 0,
1872 dbri->pipes[pipe].sdp
1873 | D_SDP_P | D_SDP_C | D_SDP_2SAME);
1874 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, td);
1875 dbri_cmdsend(dbri, cmd);
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001876#endif
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001877 }
1878 break;
1879 case D_INTR_FXDT:
1880 /* FXDT - Fixed data change */
1881 if (dbri->pipes[channel].sdp & D_SDP_MSB)
1882 val = reverse_bytes(val, dbri->pipes[channel].length);
1883
1884 if (dbri->pipes[channel].recv_fixed_ptr)
1885 *(dbri->pipes[channel].recv_fixed_ptr) = val;
1886 break;
1887 default:
1888 if (channel != D_INTR_CMD)
1889 printk(KERN_WARNING
1890 "DBRI: Ignored Interrupt: %d (0x%x)\n", code, x);
1891 }
1892}
1893
1894/* dbri_process_interrupt_buffer advances through the DBRI's interrupt
1895 * buffer until it finds a zero word (indicating nothing more to do
1896 * right now). Non-zero words require processing and are handed off
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001897 * to dbri_process_one_interrupt AFTER advancing the pointer.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001898 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001899static void dbri_process_interrupt_buffer(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001900{
1901 s32 x;
1902
1903 while ((x = dbri->dma->intr[dbri->dbri_irqp]) != 0) {
1904 dbri->dma->intr[dbri->dbri_irqp] = 0;
1905 dbri->dbri_irqp++;
Krzysztof Helt6fb98282006-08-16 12:54:29 +02001906 if (dbri->dbri_irqp == DBRI_INT_BLK)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001907 dbri->dbri_irqp = 1;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001908
1909 dbri_process_one_interrupt(dbri, x);
1910 }
1911}
1912
David Howells7d12e782006-10-05 14:55:46 +01001913static irqreturn_t snd_dbri_interrupt(int irq, void *dev_id)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001914{
Takashi Iwai475675d2005-11-17 15:11:51 +01001915 struct snd_dbri *dbri = dev_id;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001916 static int errcnt = 0;
1917 int x;
1918
1919 if (dbri == NULL)
1920 return IRQ_NONE;
1921 spin_lock(&dbri->lock);
1922
1923 /*
1924 * Read it, so the interrupt goes away.
1925 */
1926 x = sbus_readl(dbri->regs + REG1);
1927
1928 if (x & (D_MRR | D_MLE | D_LBG | D_MBE)) {
1929 u32 tmp;
1930
1931 if (x & D_MRR)
1932 printk(KERN_ERR
1933 "DBRI: Multiple Error Ack on SBus reg1=0x%x\n",
1934 x);
1935 if (x & D_MLE)
1936 printk(KERN_ERR
1937 "DBRI: Multiple Late Error on SBus reg1=0x%x\n",
1938 x);
1939 if (x & D_LBG)
1940 printk(KERN_ERR
1941 "DBRI: Lost Bus Grant on SBus reg1=0x%x\n", x);
1942 if (x & D_MBE)
1943 printk(KERN_ERR
1944 "DBRI: Burst Error on SBus reg1=0x%x\n", x);
1945
1946 /* Some of these SBus errors cause the chip's SBus circuitry
1947 * to be disabled, so just re-enable and try to keep going.
1948 *
1949 * The only one I've seen is MRR, which will be triggered
1950 * if you let a transmit pipe underrun, then try to CDP it.
1951 *
Martin Habets43388292005-09-10 15:39:00 +02001952 * If these things persist, we reset the chip.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001953 */
1954 if ((++errcnt) % 10 == 0) {
1955 dprintk(D_INT, "Interrupt errors exceeded.\n");
1956 dbri_reset(dbri);
1957 } else {
1958 tmp = sbus_readl(dbri->regs + REG0);
1959 tmp &= ~(D_D);
1960 sbus_writel(tmp, dbri->regs + REG0);
1961 }
1962 }
1963
1964 dbri_process_interrupt_buffer(dbri);
1965
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001966 spin_unlock(&dbri->lock);
1967
1968 return IRQ_HANDLED;
1969}
1970
1971/****************************************************************************
1972 PCM Interface
1973****************************************************************************/
Takashi Iwai475675d2005-11-17 15:11:51 +01001974static struct snd_pcm_hardware snd_dbri_pcm_hw = {
Krzysztof Heltcf68d212007-09-04 13:09:20 +02001975 .info = SNDRV_PCM_INFO_MMAP |
1976 SNDRV_PCM_INFO_INTERLEAVED |
1977 SNDRV_PCM_INFO_BLOCK_TRANSFER |
Takashi Iwai2008f132009-04-28 12:25:59 +02001978 SNDRV_PCM_INFO_MMAP_VALID |
1979 SNDRV_PCM_INFO_BATCH,
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001980 .formats = SNDRV_PCM_FMTBIT_MU_LAW |
1981 SNDRV_PCM_FMTBIT_A_LAW |
1982 SNDRV_PCM_FMTBIT_U8 |
1983 SNDRV_PCM_FMTBIT_S16_BE,
1984 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_5512,
Krzysztof Heltab93c7a2006-08-23 11:37:36 +02001985 .rate_min = 5512,
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001986 .rate_max = 48000,
1987 .channels_min = 1,
1988 .channels_max = 2,
Krzysztof Heltcf68d212007-09-04 13:09:20 +02001989 .buffer_bytes_max = 64 * 1024,
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001990 .period_bytes_min = 1,
1991 .period_bytes_max = DBRI_TD_MAXCNT,
1992 .periods_min = 1,
1993 .periods_max = 1024,
1994};
1995
Krzysztof Heltab93c7a2006-08-23 11:37:36 +02001996static int snd_hw_rule_format(struct snd_pcm_hw_params *params,
1997 struct snd_pcm_hw_rule *rule)
1998{
1999 struct snd_interval *c = hw_param_interval(params,
2000 SNDRV_PCM_HW_PARAM_CHANNELS);
2001 struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
2002 struct snd_mask fmt;
2003
2004 snd_mask_any(&fmt);
2005 if (c->min > 1) {
2006 fmt.bits[0] &= SNDRV_PCM_FMTBIT_S16_BE;
2007 return snd_mask_refine(f, &fmt);
2008 }
2009 return 0;
2010}
2011
2012static int snd_hw_rule_channels(struct snd_pcm_hw_params *params,
2013 struct snd_pcm_hw_rule *rule)
2014{
2015 struct snd_interval *c = hw_param_interval(params,
2016 SNDRV_PCM_HW_PARAM_CHANNELS);
2017 struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
2018 struct snd_interval ch;
2019
2020 snd_interval_any(&ch);
2021 if (!(f->bits[0] & SNDRV_PCM_FMTBIT_S16_BE)) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002022 ch.min = 1;
2023 ch.max = 1;
Krzysztof Heltab93c7a2006-08-23 11:37:36 +02002024 ch.integer = 1;
2025 return snd_interval_refine(c, &ch);
2026 }
2027 return 0;
2028}
2029
Takashi Iwai475675d2005-11-17 15:11:51 +01002030static int snd_dbri_open(struct snd_pcm_substream *substream)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002031{
Takashi Iwai475675d2005-11-17 15:11:51 +01002032 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2033 struct snd_pcm_runtime *runtime = substream->runtime;
2034 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002035 unsigned long flags;
2036
2037 dprintk(D_USR, "open audio output.\n");
2038 runtime->hw = snd_dbri_pcm_hw;
2039
2040 spin_lock_irqsave(&dbri->lock, flags);
2041 info->substream = substream;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002042 info->offset = 0;
2043 info->dvma_buffer = 0;
2044 info->pipe = -1;
2045 spin_unlock_irqrestore(&dbri->lock, flags);
2046
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002047 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
Al Viroae97dd92006-09-24 23:42:57 +01002048 snd_hw_rule_format, NULL, SNDRV_PCM_HW_PARAM_FORMAT,
Krzysztof Heltab93c7a2006-08-23 11:37:36 +02002049 -1);
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002050 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_FORMAT,
2051 snd_hw_rule_channels, NULL,
Krzysztof Heltab93c7a2006-08-23 11:37:36 +02002052 SNDRV_PCM_HW_PARAM_CHANNELS,
2053 -1);
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002054
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002055 cs4215_open(dbri);
2056
2057 return 0;
2058}
2059
Takashi Iwai475675d2005-11-17 15:11:51 +01002060static int snd_dbri_close(struct snd_pcm_substream *substream)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002061{
Takashi Iwai475675d2005-11-17 15:11:51 +01002062 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2063 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002064
2065 dprintk(D_USR, "close audio output.\n");
2066 info->substream = NULL;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002067 info->offset = 0;
2068
2069 return 0;
2070}
2071
Takashi Iwai475675d2005-11-17 15:11:51 +01002072static int snd_dbri_hw_params(struct snd_pcm_substream *substream,
2073 struct snd_pcm_hw_params *hw_params)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002074{
Takashi Iwai475675d2005-11-17 15:11:51 +01002075 struct snd_pcm_runtime *runtime = substream->runtime;
2076 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2077 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002078 int direction;
2079 int ret;
2080
2081 /* set sampling rate, audio format and number of channels */
2082 ret = cs4215_prepare(dbri, params_rate(hw_params),
2083 params_format(hw_params),
2084 params_channels(hw_params));
2085 if (ret != 0)
2086 return ret;
2087
2088 if ((ret = snd_pcm_lib_malloc_pages(substream,
2089 params_buffer_bytes(hw_params))) < 0) {
Martin Habets43388292005-09-10 15:39:00 +02002090 printk(KERN_ERR "malloc_pages failed with %d\n", ret);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002091 return ret;
2092 }
2093
2094 /* hw_params can get called multiple times. Only map the DMA once.
2095 */
2096 if (info->dvma_buffer == 0) {
2097 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
David S. Miller738f2b72008-08-27 18:09:11 -07002098 direction = DMA_TO_DEVICE;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002099 else
David S. Miller738f2b72008-08-27 18:09:11 -07002100 direction = DMA_FROM_DEVICE;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002101
David S. Miller7a715f42008-08-27 18:37:58 -07002102 info->dvma_buffer =
David S. Miller2bd320f2008-08-27 00:30:59 -07002103 dma_map_single(&dbri->op->dev,
David S. Miller738f2b72008-08-27 18:09:11 -07002104 runtime->dma_area,
2105 params_buffer_bytes(hw_params),
2106 direction);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002107 }
2108
2109 direction = params_buffer_bytes(hw_params);
2110 dprintk(D_USR, "hw_params: %d bytes, dvma=%x\n",
2111 direction, info->dvma_buffer);
2112 return 0;
2113}
2114
Takashi Iwai475675d2005-11-17 15:11:51 +01002115static int snd_dbri_hw_free(struct snd_pcm_substream *substream)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002116{
Takashi Iwai475675d2005-11-17 15:11:51 +01002117 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2118 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002119 int direction;
Krzysztof Helt99dabfe2006-08-28 13:00:45 +02002120
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002121 dprintk(D_USR, "hw_free.\n");
2122
2123 /* hw_free can get called multiple times. Only unmap the DMA once.
2124 */
2125 if (info->dvma_buffer) {
2126 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
David S. Miller738f2b72008-08-27 18:09:11 -07002127 direction = DMA_TO_DEVICE;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002128 else
David S. Miller738f2b72008-08-27 18:09:11 -07002129 direction = DMA_FROM_DEVICE;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002130
David S. Miller2bd320f2008-08-27 00:30:59 -07002131 dma_unmap_single(&dbri->op->dev, info->dvma_buffer,
David S. Miller738f2b72008-08-27 18:09:11 -07002132 substream->runtime->buffer_size, direction);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002133 info->dvma_buffer = 0;
2134 }
Krzysztof Helt99dabfe2006-08-28 13:00:45 +02002135 if (info->pipe != -1) {
2136 reset_pipe(dbri, info->pipe);
2137 info->pipe = -1;
2138 }
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002139
2140 return snd_pcm_lib_free_pages(substream);
2141}
2142
Takashi Iwai475675d2005-11-17 15:11:51 +01002143static int snd_dbri_prepare(struct snd_pcm_substream *substream)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002144{
Takashi Iwai475675d2005-11-17 15:11:51 +01002145 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2146 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002147 int ret;
2148
2149 info->size = snd_pcm_lib_buffer_bytes(substream);
2150 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2151 info->pipe = 4; /* Send pipe */
Krzysztof Helt1be54c82006-08-21 19:30:57 +02002152 else
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002153 info->pipe = 6; /* Receive pipe */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002154
2155 spin_lock_irq(&dbri->lock);
Krzysztof Heltaaad3652006-08-28 12:59:23 +02002156 info->offset = 0;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002157
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002158 /* Setup the all the transmit/receive descriptors to cover the
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002159 * whole DMA buffer.
2160 */
2161 ret = setup_descs(dbri, DBRI_STREAMNO(substream),
2162 snd_pcm_lib_period_bytes(substream));
2163
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002164 spin_unlock_irq(&dbri->lock);
2165
2166 dprintk(D_USR, "prepare audio output. %d bytes\n", info->size);
2167 return ret;
2168}
2169
Takashi Iwai475675d2005-11-17 15:11:51 +01002170static int snd_dbri_trigger(struct snd_pcm_substream *substream, int cmd)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002171{
Takashi Iwai475675d2005-11-17 15:11:51 +01002172 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2173 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002174 int ret = 0;
2175
2176 switch (cmd) {
2177 case SNDRV_PCM_TRIGGER_START:
2178 dprintk(D_USR, "start audio, period is %d bytes\n",
2179 (int)snd_pcm_lib_period_bytes(substream));
Krzysztof Helt1be54c82006-08-21 19:30:57 +02002180 /* Re-submit the TDs. */
2181 xmit_descs(dbri);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002182 break;
2183 case SNDRV_PCM_TRIGGER_STOP:
2184 dprintk(D_USR, "stop audio.\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002185 reset_pipe(dbri, info->pipe);
2186 break;
2187 default:
2188 ret = -EINVAL;
2189 }
2190
2191 return ret;
2192}
2193
Takashi Iwai475675d2005-11-17 15:11:51 +01002194static snd_pcm_uframes_t snd_dbri_pointer(struct snd_pcm_substream *substream)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002195{
Takashi Iwai475675d2005-11-17 15:11:51 +01002196 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2197 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002198 snd_pcm_uframes_t ret;
2199
2200 ret = bytes_to_frames(substream->runtime, info->offset)
2201 % substream->runtime->buffer_size;
Krzysztof Helt1be54c82006-08-21 19:30:57 +02002202 dprintk(D_USR, "I/O pointer: %ld frames of %ld.\n",
2203 ret, substream->runtime->buffer_size);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002204 return ret;
2205}
2206
Takashi Iwai475675d2005-11-17 15:11:51 +01002207static struct snd_pcm_ops snd_dbri_ops = {
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002208 .open = snd_dbri_open,
2209 .close = snd_dbri_close,
2210 .ioctl = snd_pcm_lib_ioctl,
2211 .hw_params = snd_dbri_hw_params,
2212 .hw_free = snd_dbri_hw_free,
2213 .prepare = snd_dbri_prepare,
2214 .trigger = snd_dbri_trigger,
2215 .pointer = snd_dbri_pointer,
2216};
2217
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002218static int __devinit snd_dbri_pcm(struct snd_card *card)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002219{
Takashi Iwai475675d2005-11-17 15:11:51 +01002220 struct snd_pcm *pcm;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002221 int err;
2222
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002223 if ((err = snd_pcm_new(card,
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002224 /* ID */ "sun_dbri",
2225 /* device */ 0,
2226 /* playback count */ 1,
2227 /* capture count */ 1, &pcm)) < 0)
2228 return err;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002229
2230 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_dbri_ops);
2231 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_dbri_ops);
2232
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002233 pcm->private_data = card->private_data;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002234 pcm->info_flags = 0;
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002235 strcpy(pcm->name, card->shortname);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002236
2237 if ((err = snd_pcm_lib_preallocate_pages_for_all(pcm,
2238 SNDRV_DMA_TYPE_CONTINUOUS,
2239 snd_dma_continuous_data(GFP_KERNEL),
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002240 64 * 1024, 64 * 1024)) < 0)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002241 return err;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002242
2243 return 0;
2244}
2245
2246/*****************************************************************************
2247 Mixer interface
2248*****************************************************************************/
2249
Takashi Iwai475675d2005-11-17 15:11:51 +01002250static int snd_cs4215_info_volume(struct snd_kcontrol *kcontrol,
2251 struct snd_ctl_elem_info *uinfo)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002252{
2253 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2254 uinfo->count = 2;
2255 uinfo->value.integer.min = 0;
Krzysztof Heltcf68d212007-09-04 13:09:20 +02002256 if (kcontrol->private_value == DBRI_PLAY)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002257 uinfo->value.integer.max = DBRI_MAX_VOLUME;
Krzysztof Heltcf68d212007-09-04 13:09:20 +02002258 else
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002259 uinfo->value.integer.max = DBRI_MAX_GAIN;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002260 return 0;
2261}
2262
Takashi Iwai475675d2005-11-17 15:11:51 +01002263static int snd_cs4215_get_volume(struct snd_kcontrol *kcontrol,
2264 struct snd_ctl_elem_value *ucontrol)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002265{
Takashi Iwai475675d2005-11-17 15:11:51 +01002266 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2267 struct dbri_streaminfo *info;
Takashi Iwai5e246b82008-08-08 17:12:47 +02002268
2269 if (snd_BUG_ON(!dbri))
2270 return -EINVAL;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002271 info = &dbri->stream_info[kcontrol->private_value];
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002272
2273 ucontrol->value.integer.value[0] = info->left_gain;
2274 ucontrol->value.integer.value[1] = info->right_gain;
2275 return 0;
2276}
2277
Takashi Iwai475675d2005-11-17 15:11:51 +01002278static int snd_cs4215_put_volume(struct snd_kcontrol *kcontrol,
2279 struct snd_ctl_elem_value *ucontrol)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002280{
Takashi Iwai475675d2005-11-17 15:11:51 +01002281 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002282 struct dbri_streaminfo *info =
2283 &dbri->stream_info[kcontrol->private_value];
Takashi Iwai3b892462007-11-15 16:17:24 +01002284 unsigned int vol[2];
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002285 int changed = 0;
2286
Takashi Iwai3b892462007-11-15 16:17:24 +01002287 vol[0] = ucontrol->value.integer.value[0];
2288 vol[1] = ucontrol->value.integer.value[1];
2289 if (kcontrol->private_value == DBRI_PLAY) {
2290 if (vol[0] > DBRI_MAX_VOLUME || vol[1] > DBRI_MAX_VOLUME)
2291 return -EINVAL;
2292 } else {
2293 if (vol[0] > DBRI_MAX_GAIN || vol[1] > DBRI_MAX_GAIN)
2294 return -EINVAL;
2295 }
2296
Takashi Iwai4581aa32007-11-20 18:31:22 +01002297 if (info->left_gain != vol[0]) {
2298 info->left_gain = vol[0];
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002299 changed = 1;
2300 }
Takashi Iwai4581aa32007-11-20 18:31:22 +01002301 if (info->right_gain != vol[1]) {
2302 info->right_gain = vol[1];
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002303 changed = 1;
2304 }
Krzysztof Heltcf68d212007-09-04 13:09:20 +02002305 if (changed) {
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002306 /* First mute outputs, and wait 1/8000 sec (125 us)
2307 * to make sure this takes. This avoids clicking noises.
2308 */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002309 cs4215_setdata(dbri, 1);
2310 udelay(125);
2311 cs4215_setdata(dbri, 0);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002312 }
2313 return changed;
2314}
2315
Takashi Iwai475675d2005-11-17 15:11:51 +01002316static int snd_cs4215_info_single(struct snd_kcontrol *kcontrol,
2317 struct snd_ctl_elem_info *uinfo)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002318{
2319 int mask = (kcontrol->private_value >> 16) & 0xff;
2320
2321 uinfo->type = (mask == 1) ?
2322 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2323 uinfo->count = 1;
2324 uinfo->value.integer.min = 0;
2325 uinfo->value.integer.max = mask;
2326 return 0;
2327}
2328
Takashi Iwai475675d2005-11-17 15:11:51 +01002329static int snd_cs4215_get_single(struct snd_kcontrol *kcontrol,
2330 struct snd_ctl_elem_value *ucontrol)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002331{
Takashi Iwai475675d2005-11-17 15:11:51 +01002332 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002333 int elem = kcontrol->private_value & 0xff;
2334 int shift = (kcontrol->private_value >> 8) & 0xff;
2335 int mask = (kcontrol->private_value >> 16) & 0xff;
2336 int invert = (kcontrol->private_value >> 24) & 1;
Takashi Iwai5e246b82008-08-08 17:12:47 +02002337
2338 if (snd_BUG_ON(!dbri))
2339 return -EINVAL;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002340
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002341 if (elem < 4)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002342 ucontrol->value.integer.value[0] =
2343 (dbri->mm.data[elem] >> shift) & mask;
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002344 else
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002345 ucontrol->value.integer.value[0] =
2346 (dbri->mm.ctrl[elem - 4] >> shift) & mask;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002347
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002348 if (invert == 1)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002349 ucontrol->value.integer.value[0] =
2350 mask - ucontrol->value.integer.value[0];
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002351 return 0;
2352}
2353
Takashi Iwai475675d2005-11-17 15:11:51 +01002354static int snd_cs4215_put_single(struct snd_kcontrol *kcontrol,
2355 struct snd_ctl_elem_value *ucontrol)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002356{
Takashi Iwai475675d2005-11-17 15:11:51 +01002357 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002358 int elem = kcontrol->private_value & 0xff;
2359 int shift = (kcontrol->private_value >> 8) & 0xff;
2360 int mask = (kcontrol->private_value >> 16) & 0xff;
2361 int invert = (kcontrol->private_value >> 24) & 1;
2362 int changed = 0;
2363 unsigned short val;
Takashi Iwai5e246b82008-08-08 17:12:47 +02002364
2365 if (snd_BUG_ON(!dbri))
2366 return -EINVAL;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002367
2368 val = (ucontrol->value.integer.value[0] & mask);
2369 if (invert == 1)
2370 val = mask - val;
2371 val <<= shift;
2372
2373 if (elem < 4) {
2374 dbri->mm.data[elem] = (dbri->mm.data[elem] &
2375 ~(mask << shift)) | val;
2376 changed = (val != dbri->mm.data[elem]);
2377 } else {
2378 dbri->mm.ctrl[elem - 4] = (dbri->mm.ctrl[elem - 4] &
2379 ~(mask << shift)) | val;
2380 changed = (val != dbri->mm.ctrl[elem - 4]);
2381 }
2382
2383 dprintk(D_GEN, "put_single: mask=0x%x, changed=%d, "
2384 "mixer-value=%ld, mm-value=0x%x\n",
2385 mask, changed, ucontrol->value.integer.value[0],
2386 dbri->mm.data[elem & 3]);
2387
2388 if (changed) {
2389 /* First mute outputs, and wait 1/8000 sec (125 us)
2390 * to make sure this takes. This avoids clicking noises.
2391 */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002392 cs4215_setdata(dbri, 1);
2393 udelay(125);
2394 cs4215_setdata(dbri, 0);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002395 }
2396 return changed;
2397}
2398
2399/* Entries 0-3 map to the 4 data timeslots, entries 4-7 map to the 4 control
2400 timeslots. Shift is the bit offset in the timeslot, mask defines the
2401 number of bits. invert is a boolean for use with attenuation.
2402 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002403#define CS4215_SINGLE(xname, entry, shift, mask, invert) \
2404{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
2405 .info = snd_cs4215_info_single, \
2406 .get = snd_cs4215_get_single, .put = snd_cs4215_put_single, \
2407 .private_value = (entry) | ((shift) << 8) | ((mask) << 16) | \
2408 ((invert) << 24) },
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002409
Takashi Iwai475675d2005-11-17 15:11:51 +01002410static struct snd_kcontrol_new dbri_controls[] __devinitdata = {
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002411 {
2412 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2413 .name = "Playback Volume",
2414 .info = snd_cs4215_info_volume,
2415 .get = snd_cs4215_get_volume,
2416 .put = snd_cs4215_put_volume,
2417 .private_value = DBRI_PLAY,
2418 },
2419 CS4215_SINGLE("Headphone switch", 0, 7, 1, 0)
2420 CS4215_SINGLE("Line out switch", 0, 6, 1, 0)
2421 CS4215_SINGLE("Speaker switch", 1, 6, 1, 0)
2422 {
2423 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2424 .name = "Capture Volume",
2425 .info = snd_cs4215_info_volume,
2426 .get = snd_cs4215_get_volume,
2427 .put = snd_cs4215_put_volume,
2428 .private_value = DBRI_REC,
2429 },
2430 /* FIXME: mic/line switch */
2431 CS4215_SINGLE("Line in switch", 2, 4, 1, 0)
2432 CS4215_SINGLE("High Pass Filter switch", 5, 7, 1, 0)
2433 CS4215_SINGLE("Monitor Volume", 3, 4, 0xf, 1)
2434 CS4215_SINGLE("Mic boost", 4, 4, 1, 1)
2435};
2436
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002437static int __devinit snd_dbri_mixer(struct snd_card *card)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002438{
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002439 int idx, err;
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002440 struct snd_dbri *dbri;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002441
Takashi Iwai5e246b82008-08-08 17:12:47 +02002442 if (snd_BUG_ON(!card || !card->private_data))
2443 return -EINVAL;
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002444 dbri = card->private_data;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002445
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002446 strcpy(card->mixername, card->shortname);
2447
Tobias Klauser6c2d8b52006-09-29 02:00:21 -07002448 for (idx = 0; idx < ARRAY_SIZE(dbri_controls); idx++) {
Krzysztof Heltcf68d212007-09-04 13:09:20 +02002449 err = snd_ctl_add(card,
2450 snd_ctl_new1(&dbri_controls[idx], dbri));
2451 if (err < 0)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002452 return err;
2453 }
2454
2455 for (idx = DBRI_REC; idx < DBRI_NO_STREAMS; idx++) {
2456 dbri->stream_info[idx].left_gain = 0;
2457 dbri->stream_info[idx].right_gain = 0;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002458 }
2459
2460 return 0;
2461}
2462
2463/****************************************************************************
2464 /proc interface
2465****************************************************************************/
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002466static void dbri_regs_read(struct snd_info_entry *entry,
2467 struct snd_info_buffer *buffer)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002468{
Takashi Iwai475675d2005-11-17 15:11:51 +01002469 struct snd_dbri *dbri = entry->private_data;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002470
2471 snd_iprintf(buffer, "REG0: 0x%x\n", sbus_readl(dbri->regs + REG0));
2472 snd_iprintf(buffer, "REG2: 0x%x\n", sbus_readl(dbri->regs + REG2));
2473 snd_iprintf(buffer, "REG8: 0x%x\n", sbus_readl(dbri->regs + REG8));
2474 snd_iprintf(buffer, "REG9: 0x%x\n", sbus_readl(dbri->regs + REG9));
2475}
2476
2477#ifdef DBRI_DEBUG
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002478static void dbri_debug_read(struct snd_info_entry *entry,
Takashi Iwai475675d2005-11-17 15:11:51 +01002479 struct snd_info_buffer *buffer)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002480{
Takashi Iwai475675d2005-11-17 15:11:51 +01002481 struct snd_dbri *dbri = entry->private_data;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002482 int pipe;
2483 snd_iprintf(buffer, "debug=%d\n", dbri_debug);
2484
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002485 for (pipe = 0; pipe < 32; pipe++) {
2486 if (pipe_active(dbri, pipe)) {
2487 struct dbri_pipe *pptr = &dbri->pipes[pipe];
2488 snd_iprintf(buffer,
2489 "Pipe %d: %s SDP=0x%x desc=%d, "
Krzysztof Helt294a30d2006-08-21 19:29:59 +02002490 "len=%d next %d\n",
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002491 pipe,
Krzysztof Heltcf68d212007-09-04 13:09:20 +02002492 (pptr->sdp & D_SDP_TO_SER) ? "output" :
2493 "input",
Krzysztof Helt5fc3a2b2006-08-17 16:58:45 +02002494 pptr->sdp, pptr->desc,
Krzysztof Helt294a30d2006-08-21 19:29:59 +02002495 pptr->length, pptr->nextpipe);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002496 }
2497 }
2498}
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002499#endif
2500
Adrian Bunke7bd3de2008-06-05 21:29:18 +03002501static void __devinit snd_dbri_proc(struct snd_card *card)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002502{
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002503 struct snd_dbri *dbri = card->private_data;
Takashi Iwai475675d2005-11-17 15:11:51 +01002504 struct snd_info_entry *entry;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002505
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002506 if (!snd_card_proc_new(card, "regs", &entry))
Takashi Iwaibf850202006-04-28 15:13:41 +02002507 snd_info_set_text_ops(entry, dbri, dbri_regs_read);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002508
2509#ifdef DBRI_DEBUG
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002510 if (!snd_card_proc_new(card, "debug", &entry)) {
Takashi Iwaibf850202006-04-28 15:13:41 +02002511 snd_info_set_text_ops(entry, dbri, dbri_debug_read);
Takashi Iwai8cb7b632005-12-01 10:48:37 +01002512 entry->mode = S_IFREG | S_IRUGO; /* Readable only. */
2513 }
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002514#endif
2515}
2516
2517/*
2518****************************************************************************
2519**************************** Initialization ********************************
2520****************************************************************************
2521*/
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002522static void snd_dbri_free(struct snd_dbri *dbri);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002523
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002524static int __devinit snd_dbri_create(struct snd_card *card,
David S. Miller2bd320f2008-08-27 00:30:59 -07002525 struct of_device *op,
2526 int irq, int dev)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002527{
Takashi Iwai475675d2005-11-17 15:11:51 +01002528 struct snd_dbri *dbri = card->private_data;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002529 int err;
2530
2531 spin_lock_init(&dbri->lock);
David S. Miller2bd320f2008-08-27 00:30:59 -07002532 dbri->op = op;
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002533 dbri->irq = irq;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002534
David S. Miller2bd320f2008-08-27 00:30:59 -07002535 dbri->dma = dma_alloc_coherent(&op->dev,
David S. Miller738f2b72008-08-27 18:09:11 -07002536 sizeof(struct dbri_dma),
2537 &dbri->dma_dvma, GFP_ATOMIC);
FUJITA Tomonoribe376642008-10-29 15:34:39 -07002538 if (!dbri->dma)
2539 return -ENOMEM;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002540 memset((void *)dbri->dma, 0, sizeof(struct dbri_dma));
2541
2542 dprintk(D_GEN, "DMA Cmd Block 0x%p (0x%08x)\n",
2543 dbri->dma, dbri->dma_dvma);
2544
2545 /* Map the registers into memory. */
David S. Miller2bd320f2008-08-27 00:30:59 -07002546 dbri->regs_size = resource_size(&op->resource[0]);
2547 dbri->regs = of_ioremap(&op->resource[0], 0,
2548 dbri->regs_size, "DBRI Registers");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002549 if (!dbri->regs) {
2550 printk(KERN_ERR "DBRI: could not allocate registers\n");
David S. Miller2bd320f2008-08-27 00:30:59 -07002551 dma_free_coherent(&op->dev, sizeof(struct dbri_dma),
David S. Miller738f2b72008-08-27 18:09:11 -07002552 (void *)dbri->dma, dbri->dma_dvma);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002553 return -EIO;
2554 }
2555
Thomas Gleixner65ca68b2006-07-01 19:29:46 -07002556 err = request_irq(dbri->irq, snd_dbri_interrupt, IRQF_SHARED,
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002557 "DBRI audio", dbri);
2558 if (err) {
2559 printk(KERN_ERR "DBRI: Can't get irq %d\n", dbri->irq);
David S. Miller2bd320f2008-08-27 00:30:59 -07002560 of_iounmap(&op->resource[0], dbri->regs, dbri->regs_size);
2561 dma_free_coherent(&op->dev, sizeof(struct dbri_dma),
David S. Miller738f2b72008-08-27 18:09:11 -07002562 (void *)dbri->dma, dbri->dma_dvma);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002563 return err;
2564 }
2565
2566 /* Do low level initialization of the DBRI and CS4215 chips */
2567 dbri_initialize(dbri);
2568 err = cs4215_init(dbri);
2569 if (err) {
2570 snd_dbri_free(dbri);
2571 return err;
2572 }
2573
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002574 return 0;
2575}
2576
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002577static void snd_dbri_free(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002578{
2579 dprintk(D_GEN, "snd_dbri_free\n");
2580 dbri_reset(dbri);
2581
2582 if (dbri->irq)
2583 free_irq(dbri->irq, dbri);
2584
2585 if (dbri->regs)
David S. Miller2bd320f2008-08-27 00:30:59 -07002586 of_iounmap(&dbri->op->resource[0], dbri->regs, dbri->regs_size);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002587
2588 if (dbri->dma)
David S. Miller2bd320f2008-08-27 00:30:59 -07002589 dma_free_coherent(&dbri->op->dev,
David S. Miller738f2b72008-08-27 18:09:11 -07002590 sizeof(struct dbri_dma),
2591 (void *)dbri->dma, dbri->dma_dvma);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002592}
2593
David S. Miller2bd320f2008-08-27 00:30:59 -07002594static int __devinit dbri_probe(struct of_device *op, const struct of_device_id *match)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002595{
Takashi Iwai475675d2005-11-17 15:11:51 +01002596 struct snd_dbri *dbri;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002597 struct resource *rp;
Takashi Iwai475675d2005-11-17 15:11:51 +01002598 struct snd_card *card;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002599 static int dev = 0;
David S. Miller2bd320f2008-08-27 00:30:59 -07002600 int irq;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002601 int err;
2602
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002603 if (dev >= SNDRV_CARDS)
2604 return -ENODEV;
2605 if (!enable[dev]) {
2606 dev++;
2607 return -ENOENT;
2608 }
2609
David S. Miller2bd320f2008-08-27 00:30:59 -07002610 irq = op->irqs[0];
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002611 if (irq <= 0) {
2612 printk(KERN_ERR "DBRI-%d: No IRQ.\n", dev);
Martin Habets43388292005-09-10 15:39:00 +02002613 return -ENODEV;
2614 }
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002615
Takashi Iwaibd7dd772008-12-28 16:45:02 +01002616 err = snd_card_create(index[dev], id[dev], THIS_MODULE,
2617 sizeof(struct snd_dbri), &card);
2618 if (err < 0)
2619 return err;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002620
2621 strcpy(card->driver, "DBRI");
2622 strcpy(card->shortname, "Sun DBRI");
David S. Miller2bd320f2008-08-27 00:30:59 -07002623 rp = &op->resource[0];
Andrew Morton5863aa62006-07-03 00:24:22 -07002624 sprintf(card->longname, "%s at 0x%02lx:0x%016Lx, irq %d",
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002625 card->shortname,
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002626 rp->flags & 0xffL, (unsigned long long)rp->start, irq);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002627
David S. Miller2bd320f2008-08-27 00:30:59 -07002628 err = snd_dbri_create(card, op, irq, dev);
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002629 if (err < 0) {
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002630 snd_card_free(card);
2631 return err;
2632 }
2633
Takashi Iwai475675d2005-11-17 15:11:51 +01002634 dbri = card->private_data;
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002635 err = snd_dbri_pcm(card);
Krzysztof Heltcf68d212007-09-04 13:09:20 +02002636 if (err < 0)
Takashi Iwai16dab542005-09-05 17:17:58 +02002637 goto _err;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002638
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002639 err = snd_dbri_mixer(card);
Krzysztof Heltcf68d212007-09-04 13:09:20 +02002640 if (err < 0)
Takashi Iwai16dab542005-09-05 17:17:58 +02002641 goto _err;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002642
2643 /* /proc file handling */
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002644 snd_dbri_proc(card);
David S. Miller2bd320f2008-08-27 00:30:59 -07002645 dev_set_drvdata(&op->dev, card);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002646
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002647 err = snd_card_register(card);
2648 if (err < 0)
Takashi Iwai16dab542005-09-05 17:17:58 +02002649 goto _err;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002650
2651 printk(KERN_INFO "audio%d at %p (irq %d) is DBRI(%c)+CS4215(%d)\n",
2652 dev, dbri->regs,
David S. Miller2bd320f2008-08-27 00:30:59 -07002653 dbri->irq, op->node->name[9], dbri->mm.version);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002654 dev++;
2655
2656 return 0;
Takashi Iwai16dab542005-09-05 17:17:58 +02002657
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002658_err:
Takashi Iwai16dab542005-09-05 17:17:58 +02002659 snd_dbri_free(dbri);
2660 snd_card_free(card);
2661 return err;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002662}
2663
David S. Miller2bd320f2008-08-27 00:30:59 -07002664static int __devexit dbri_remove(struct of_device *op)
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002665{
David S. Miller2bd320f2008-08-27 00:30:59 -07002666 struct snd_card *card = dev_get_drvdata(&op->dev);
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002667
2668 snd_dbri_free(card->private_data);
2669 snd_card_free(card);
2670
David S. Miller2bd320f2008-08-27 00:30:59 -07002671 dev_set_drvdata(&op->dev, NULL);
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002672
2673 return 0;
2674}
2675
David S. Millerfd098312008-08-31 01:23:17 -07002676static const struct of_device_id dbri_match[] = {
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002677 {
2678 .name = "SUNW,DBRIe",
2679 },
2680 {
2681 .name = "SUNW,DBRIf",
2682 },
2683 {},
2684};
2685
2686MODULE_DEVICE_TABLE(of, dbri_match);
2687
2688static struct of_platform_driver dbri_sbus_driver = {
2689 .name = "dbri",
2690 .match_table = dbri_match,
2691 .probe = dbri_probe,
2692 .remove = __devexit_p(dbri_remove),
2693};
2694
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002695/* Probe for the dbri chip and then attach the driver. */
2696static int __init dbri_init(void)
2697{
David S. Miller2bd320f2008-08-27 00:30:59 -07002698 return of_register_driver(&dbri_sbus_driver, &of_bus_type);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002699}
2700
2701static void __exit dbri_exit(void)
2702{
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002703 of_unregister_driver(&dbri_sbus_driver);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002704}
2705
2706module_init(dbri_init);
2707module_exit(dbri_exit);