Siddartha Mohanadoss | c4a6af1 | 2012-07-13 18:50:12 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2012, Code Aurora Forum. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #define pr_fmt(fmt) "%s: " fmt, __func__ |
| 14 | |
| 15 | #include <linux/kernel.h> |
| 16 | #include <linux/of.h> |
| 17 | #include <linux/err.h> |
| 18 | #include <linux/init.h> |
| 19 | #include <linux/slab.h> |
| 20 | #include <linux/delay.h> |
| 21 | #include <linux/mutex.h> |
| 22 | #include <linux/types.h> |
| 23 | #include <linux/hwmon.h> |
| 24 | #include <linux/module.h> |
| 25 | #include <linux/debugfs.h> |
| 26 | #include <linux/spmi.h> |
| 27 | #include <linux/of_irq.h> |
| 28 | #include <linux/wakelock.h> |
| 29 | #include <linux/interrupt.h> |
| 30 | #include <linux/completion.h> |
| 31 | #include <linux/hwmon-sysfs.h> |
| 32 | #include <linux/qpnp/qpnp-adc.h> |
| 33 | #include <linux/platform_device.h> |
| 34 | |
| 35 | /* QPNP IADC register definition */ |
Siddartha Mohanadoss | 5ace110 | 2012-08-20 23:18:10 -0700 | [diff] [blame^] | 36 | #define QPNP_IADC_REVISION1 0x0 |
| 37 | #define QPNP_IADC_REVISION2 0x1 |
| 38 | #define QPNP_IADC_REVISION3 0x2 |
| 39 | #define QPNP_IADC_REVISION4 0x3 |
| 40 | #define QPNP_IADC_PERPH_TYPE 0x4 |
| 41 | #define QPNP_IADC_PERH_SUBTYPE 0x5 |
| 42 | |
| 43 | #define QPNP_IADC_SUPPORTED_REVISION2 1 |
| 44 | |
Siddartha Mohanadoss | c4a6af1 | 2012-07-13 18:50:12 -0700 | [diff] [blame] | 45 | #define QPNP_STATUS1 0x8 |
| 46 | #define QPNP_STATUS1_OP_MODE 4 |
| 47 | #define QPNP_STATUS1_MULTI_MEAS_EN BIT(3) |
| 48 | #define QPNP_STATUS1_MEAS_INTERVAL_EN_STS BIT(2) |
| 49 | #define QPNP_STATUS1_REQ_STS BIT(1) |
| 50 | #define QPNP_STATUS1_EOC BIT(0) |
| 51 | #define QPNP_STATUS2 0x9 |
| 52 | #define QPNP_STATUS2_CONV_SEQ_STATE_SHIFT 4 |
| 53 | #define QPNP_STATUS2_FIFO_NOT_EMPTY_FLAG BIT(1) |
| 54 | #define QPNP_STATUS2_CONV_SEQ_TIMEOUT_STS BIT(0) |
| 55 | #define QPNP_CONV_TIMEOUT_ERR 2 |
| 56 | |
| 57 | #define QPNP_INT_RT_ST 0x10 |
| 58 | #define QPNP_INT_SET_TYPE 0x11 |
| 59 | #define QPNP_INT_SET_TYPE_LOW_THR_INT_SET BIT(4) |
| 60 | #define QPNP_INT_SET_TYPE_HIGH_THR_INT_SET BIT(3) |
| 61 | #define QPNP_INT_SET_TYPE_CONV_SEQ_TIMEOUT_INT_SET BIT(2) |
| 62 | #define QPNP_INT_SET_TYPE_FIFO_NOT_EMPTY_INT_SET BIT(1) |
| 63 | #define QPNP_INT_SET_TYPE_EOC_SET_INT_TYPE BIT(0) |
| 64 | #define QPNP_INT_POLARITY_HIGH 0x12 |
| 65 | #define QPNP_INT_POLARITY_LOW 0x13 |
| 66 | #define QPNP_INT_EN_SET 0x15 |
| 67 | #define QPNP_INT_EN_SET_LOW_THR_INT_EN_SET BIT(4) |
| 68 | #define QPNP_INT_EN_SET_HIGH_THR_INT_EN_SET BIT(3) |
| 69 | #define QPNP_INT_EN_SET_CONV_SEQ_TIMEOUT_INT_EN BIT(2) |
| 70 | #define QPNP_INT_EN_SET_FIFO_NOT_EMPTY_INT_EN BIT(1) |
| 71 | #define QPNP_INT_EN_SET_EOC_INT_EN_SET BIT(0) |
| 72 | #define QPNP_INT_CLR 0x16 |
| 73 | #define QPNP_INT_CLR_LOW_THR_INT_EN_CLR BIT(4) |
| 74 | #define QPNP_INT_CLR_HIGH_THR_INT_EN_CLKR BIT(3) |
| 75 | #define QPNP_INT_CLR_CONV_SEQ_TIMEOUT_INT_EN BIT(2) |
| 76 | #define QPNP_INT_CLR_FIFO_NOT_EMPTY_INT_EN BIT(1) |
| 77 | #define QPNP_INT_CLR_EOC_INT_EN_CLR BIT(0) |
| 78 | #define QPNP_INT_CLR_MASK 0x1f |
Siddartha Mohanadoss | 5ace110 | 2012-08-20 23:18:10 -0700 | [diff] [blame^] | 79 | #define QPNP_IADC_MODE_CTL 0x40 |
Siddartha Mohanadoss | c4a6af1 | 2012-07-13 18:50:12 -0700 | [diff] [blame] | 80 | #define QPNP_OP_MODE_SHIFT 4 |
| 81 | #define QPNP_USE_BMS_DATA BIT(4) |
| 82 | #define QPNP_VADC_SYNCH_EN BIT(2) |
| 83 | #define QPNP_OFFSET_RMV_EN BIT(1) |
| 84 | #define QPNP_ADC_TRIM_EN BIT(0) |
Siddartha Mohanadoss | 5ace110 | 2012-08-20 23:18:10 -0700 | [diff] [blame^] | 85 | #define QPNP_IADC_EN_CTL1 0x46 |
| 86 | #define QPNP_IADC_ADC_EN BIT(7) |
Siddartha Mohanadoss | c4a6af1 | 2012-07-13 18:50:12 -0700 | [diff] [blame] | 87 | #define QPNP_ADC_CH_SEL_CTL 0x48 |
| 88 | #define QPNP_ADC_DIG_PARAM 0x50 |
| 89 | #define QPNP_ADC_CLK_SEL_MASK 0x3 |
| 90 | #define QPNP_ADC_DEC_RATIO_SEL_MASK 0xc |
| 91 | #define QPNP_ADC_DIG_DEC_RATIO_SEL_SHIFT 2 |
| 92 | |
| 93 | #define QPNP_HW_SETTLE_DELAY 0x51 |
| 94 | #define QPNP_CONV_REQ 0x52 |
| 95 | #define QPNP_CONV_REQ_SET BIT(7) |
| 96 | #define QPNP_CONV_SEQ_CTL 0x54 |
| 97 | #define QPNP_CONV_SEQ_HOLDOFF_SHIFT 4 |
| 98 | #define QPNP_CONV_SEQ_TRIG_CTL 0x55 |
| 99 | #define QPNP_FAST_AVG_CTL 0x5a |
| 100 | |
| 101 | #define QPNP_M0_LOW_THR_LSB 0x5c |
| 102 | #define QPNP_M0_LOW_THR_MSB 0x5d |
| 103 | #define QPNP_M0_HIGH_THR_LSB 0x5e |
| 104 | #define QPNP_M0_HIGH_THR_MSB 0x5f |
| 105 | #define QPNP_M1_LOW_THR_LSB 0x69 |
| 106 | #define QPNP_M1_LOW_THR_MSB 0x6a |
| 107 | #define QPNP_M1_HIGH_THR_LSB 0x6b |
| 108 | #define QPNP_M1_HIGH_THR_MSB 0x6c |
| 109 | |
| 110 | #define QPNP_DATA0 0x60 |
| 111 | #define QPNP_DATA1 0x61 |
| 112 | #define QPNP_CONV_TIMEOUT_ERR 2 |
| 113 | |
Siddartha Mohanadoss | c4a6af1 | 2012-07-13 18:50:12 -0700 | [diff] [blame] | 114 | #define QPNP_IADC_ADC_CH_SEL_CTL 0x48 |
| 115 | #define QPNP_IADC_ADC_CHX_SEL_SHIFT 3 |
| 116 | |
| 117 | #define QPNP_IADC_ADC_DIG_PARAM 0x50 |
| 118 | #define QPNP_IADC_CLK_SEL_SHIFT 1 |
| 119 | #define QPNP_IADC_DEC_RATIO_SEL 3 |
| 120 | |
| 121 | #define QPNP_IADC_CONV_REQUEST 0x52 |
| 122 | #define QPNP_IADC_CONV_REQ BIT(7) |
| 123 | |
| 124 | #define QPNP_IADC_DATA0 0x60 |
| 125 | #define QPNP_IADC_DATA1 0x61 |
| 126 | |
Siddartha Mohanadoss | 5ace110 | 2012-08-20 23:18:10 -0700 | [diff] [blame^] | 127 | #define QPNP_ADC_CONV_TIME_MIN 8000 |
| 128 | #define QPNP_ADC_CONV_TIME_MAX 8200 |
Siddartha Mohanadoss | c4a6af1 | 2012-07-13 18:50:12 -0700 | [diff] [blame] | 129 | |
Siddartha Mohanadoss | 5ace110 | 2012-08-20 23:18:10 -0700 | [diff] [blame^] | 130 | #define QPNP_ADC_GAIN_CALCULATION_UV 17857 |
| 131 | #define QPNP_IADC_RSENSE_MILLI_FACTOR 1000 |
Siddartha Mohanadoss | c4a6af1 | 2012-07-13 18:50:12 -0700 | [diff] [blame] | 132 | |
| 133 | struct qpnp_iadc_drv { |
| 134 | struct qpnp_adc_drv *adc; |
| 135 | int32_t rsense; |
| 136 | struct device *iadc_hwmon; |
| 137 | bool iadc_init_calib; |
Siddartha Mohanadoss | 5ace110 | 2012-08-20 23:18:10 -0700 | [diff] [blame^] | 138 | bool iadc_initialized; |
Siddartha Mohanadoss | c4a6af1 | 2012-07-13 18:50:12 -0700 | [diff] [blame] | 139 | struct sensor_device_attribute sens_attr[0]; |
| 140 | }; |
| 141 | |
| 142 | struct qpnp_iadc_drv *qpnp_iadc; |
| 143 | |
| 144 | static int32_t qpnp_iadc_read_reg(uint32_t reg, u8 *data) |
| 145 | { |
| 146 | struct qpnp_iadc_drv *iadc = qpnp_iadc; |
| 147 | int rc; |
| 148 | |
| 149 | rc = spmi_ext_register_readl(iadc->adc->spmi->ctrl, iadc->adc->slave, |
Siddartha Mohanadoss | ae1da73 | 2012-08-08 16:39:02 -0700 | [diff] [blame] | 150 | (iadc->adc->offset + reg), data, 1); |
Siddartha Mohanadoss | c4a6af1 | 2012-07-13 18:50:12 -0700 | [diff] [blame] | 151 | if (rc < 0) { |
| 152 | pr_err("qpnp iadc read reg %d failed with %d\n", reg, rc); |
| 153 | return rc; |
| 154 | } |
| 155 | |
| 156 | return 0; |
| 157 | } |
| 158 | |
| 159 | static int32_t qpnp_iadc_write_reg(uint32_t reg, u8 data) |
| 160 | { |
| 161 | struct qpnp_iadc_drv *iadc = qpnp_iadc; |
| 162 | int rc; |
| 163 | u8 *buf; |
| 164 | |
| 165 | buf = &data; |
| 166 | rc = spmi_ext_register_writel(iadc->adc->spmi->ctrl, iadc->adc->slave, |
Siddartha Mohanadoss | ae1da73 | 2012-08-08 16:39:02 -0700 | [diff] [blame] | 167 | (iadc->adc->offset + reg), buf, 1); |
Siddartha Mohanadoss | c4a6af1 | 2012-07-13 18:50:12 -0700 | [diff] [blame] | 168 | if (rc < 0) { |
| 169 | pr_err("qpnp iadc write reg %d failed with %d\n", reg, rc); |
| 170 | return rc; |
| 171 | } |
| 172 | |
| 173 | return 0; |
| 174 | } |
| 175 | |
| 176 | static int32_t qpnp_iadc_configure_interrupt(void) |
| 177 | { |
| 178 | int rc = 0; |
| 179 | u8 data = 0; |
| 180 | |
| 181 | /* Configure interrupt as an Edge trigger */ |
| 182 | rc = qpnp_iadc_write_reg(QPNP_INT_SET_TYPE, |
| 183 | QPNP_INT_CLR_MASK); |
| 184 | if (rc < 0) { |
| 185 | pr_err("%s Interrupt configure failed\n", __func__); |
| 186 | return rc; |
| 187 | } |
| 188 | |
| 189 | /* Configure interrupt for rising edge trigger */ |
| 190 | rc = qpnp_iadc_write_reg(QPNP_INT_POLARITY_HIGH, |
| 191 | QPNP_INT_CLR_MASK); |
| 192 | if (rc < 0) { |
| 193 | pr_err("%s Rising edge trigger configure failed\n", __func__); |
| 194 | return rc; |
| 195 | } |
| 196 | |
| 197 | /* Disable low level interrupt triggering */ |
| 198 | data = QPNP_INT_CLR_MASK; |
| 199 | rc = qpnp_iadc_write_reg(QPNP_INT_POLARITY_LOW, |
| 200 | (~data & QPNP_INT_CLR_MASK)); |
| 201 | if (rc < 0) { |
| 202 | pr_err("%s Setting level low to disable failed\n", __func__); |
| 203 | return rc; |
| 204 | } |
| 205 | |
| 206 | return 0; |
| 207 | } |
| 208 | |
| 209 | static void trigger_iadc_completion(struct work_struct *work) |
| 210 | { |
| 211 | struct qpnp_iadc_drv *iadc = qpnp_iadc; |
| 212 | int rc; |
| 213 | |
| 214 | rc = qpnp_iadc_write_reg(QPNP_INT_CLR, QPNP_INT_CLR_MASK); |
| 215 | if (rc < 0) |
| 216 | pr_err("qpnp iadc interrupt mask failed with %d\n", rc); |
| 217 | |
| 218 | complete(&iadc->adc->adc_rslt_completion); |
| 219 | |
| 220 | return; |
| 221 | } |
| 222 | DECLARE_WORK(trigger_iadc_completion_work, trigger_iadc_completion); |
| 223 | |
| 224 | static irqreturn_t qpnp_iadc_isr(int irq, void *dev_id) |
| 225 | { |
| 226 | schedule_work(&trigger_iadc_completion_work); |
| 227 | |
| 228 | return IRQ_HANDLED; |
| 229 | } |
| 230 | |
Siddartha Mohanadoss | 5ace110 | 2012-08-20 23:18:10 -0700 | [diff] [blame^] | 231 | static int32_t qpnp_iadc_enable(bool state) |
| 232 | { |
| 233 | int rc = 0; |
| 234 | u8 data = 0; |
| 235 | |
| 236 | data = QPNP_IADC_ADC_EN; |
| 237 | if (state) { |
| 238 | rc = qpnp_iadc_write_reg(QPNP_IADC_EN_CTL1, |
| 239 | data); |
| 240 | if (rc < 0) { |
| 241 | pr_err("IADC enable failed\n"); |
| 242 | return rc; |
| 243 | } |
| 244 | } else { |
| 245 | rc = qpnp_iadc_write_reg(QPNP_IADC_EN_CTL1, |
| 246 | (~data & QPNP_IADC_ADC_EN)); |
| 247 | if (rc < 0) { |
| 248 | pr_err("IADC disable failed\n"); |
| 249 | return rc; |
| 250 | } |
| 251 | } |
| 252 | |
| 253 | return 0; |
| 254 | } |
| 255 | |
Siddartha Mohanadoss | c4a6af1 | 2012-07-13 18:50:12 -0700 | [diff] [blame] | 256 | static int32_t qpnp_iadc_read_conversion_result(int32_t *data) |
| 257 | { |
| 258 | uint8_t rslt_lsb, rslt_msb; |
| 259 | int32_t rc; |
| 260 | |
| 261 | rc = qpnp_iadc_read_reg(QPNP_IADC_DATA0, &rslt_lsb); |
| 262 | if (rc < 0) { |
| 263 | pr_err("qpnp adc result read failed with %d\n", rc); |
| 264 | return rc; |
| 265 | } |
| 266 | |
| 267 | rc = qpnp_iadc_read_reg(QPNP_IADC_DATA1, &rslt_msb); |
| 268 | if (rc < 0) { |
| 269 | pr_err("qpnp adc result read failed with %d\n", rc); |
| 270 | return rc; |
| 271 | } |
| 272 | |
| 273 | *data = (rslt_msb << 8) | rslt_lsb; |
| 274 | |
Siddartha Mohanadoss | 5ace110 | 2012-08-20 23:18:10 -0700 | [diff] [blame^] | 275 | rc = qpnp_iadc_enable(false); |
| 276 | if (rc) |
Siddartha Mohanadoss | c4a6af1 | 2012-07-13 18:50:12 -0700 | [diff] [blame] | 277 | return rc; |
Siddartha Mohanadoss | c4a6af1 | 2012-07-13 18:50:12 -0700 | [diff] [blame] | 278 | return 0; |
| 279 | } |
| 280 | |
| 281 | static int32_t qpnp_iadc_configure(enum qpnp_iadc_channels channel, |
| 282 | int32_t *result) |
| 283 | { |
| 284 | struct qpnp_iadc_drv *iadc = qpnp_iadc; |
| 285 | u8 qpnp_iadc_mode_reg = 0, qpnp_iadc_ch_sel_reg = 0; |
| 286 | u8 qpnp_iadc_conv_req = 0, qpnp_iadc_dig_param_reg = 0; |
| 287 | int32_t rc = 0; |
| 288 | |
Siddartha Mohanadoss | 5ace110 | 2012-08-20 23:18:10 -0700 | [diff] [blame^] | 289 | qpnp_iadc_ch_sel_reg = channel; |
Siddartha Mohanadoss | c4a6af1 | 2012-07-13 18:50:12 -0700 | [diff] [blame] | 290 | |
| 291 | qpnp_iadc_dig_param_reg |= iadc->adc->amux_prop->decimation << |
| 292 | QPNP_IADC_DEC_RATIO_SEL; |
| 293 | |
| 294 | qpnp_iadc_conv_req = QPNP_IADC_CONV_REQ; |
| 295 | |
| 296 | rc = qpnp_iadc_write_reg(QPNP_INT_EN_SET, |
| 297 | QPNP_INT_EN_SET_EOC_INT_EN_SET); |
| 298 | if (rc < 0) { |
| 299 | pr_err("qpnp adc configure error for interrupt setup\n"); |
| 300 | return rc; |
| 301 | } |
| 302 | |
| 303 | rc = qpnp_iadc_write_reg(QPNP_IADC_MODE_CTL, qpnp_iadc_mode_reg); |
| 304 | if (rc) { |
| 305 | pr_err("qpnp adc read adc failed with %d\n", rc); |
| 306 | return rc; |
| 307 | } |
| 308 | |
| 309 | rc = qpnp_iadc_write_reg(QPNP_IADC_ADC_CH_SEL_CTL, |
| 310 | qpnp_iadc_ch_sel_reg); |
| 311 | if (rc) { |
| 312 | pr_err("qpnp adc read adc failed with %d\n", rc); |
| 313 | return rc; |
| 314 | } |
| 315 | |
| 316 | rc = qpnp_iadc_write_reg(QPNP_ADC_DIG_PARAM, |
| 317 | qpnp_iadc_dig_param_reg); |
| 318 | if (rc) { |
| 319 | pr_err("qpnp adc read adc failed with %d\n", rc); |
| 320 | return rc; |
| 321 | } |
| 322 | |
| 323 | rc = qpnp_iadc_write_reg(QPNP_HW_SETTLE_DELAY, |
| 324 | iadc->adc->amux_prop->hw_settle_time); |
| 325 | if (rc < 0) { |
| 326 | pr_err("qpnp adc configure error for hw settling time setup\n"); |
| 327 | return rc; |
| 328 | } |
| 329 | |
| 330 | rc = qpnp_iadc_write_reg(QPNP_FAST_AVG_CTL, |
| 331 | iadc->adc->amux_prop->fast_avg_setup); |
| 332 | if (rc < 0) { |
| 333 | pr_err("qpnp adc fast averaging configure error\n"); |
| 334 | return rc; |
| 335 | } |
| 336 | |
Siddartha Mohanadoss | 5ace110 | 2012-08-20 23:18:10 -0700 | [diff] [blame^] | 337 | rc = qpnp_iadc_enable(true); |
| 338 | if (rc) |
| 339 | return rc; |
| 340 | |
Siddartha Mohanadoss | c4a6af1 | 2012-07-13 18:50:12 -0700 | [diff] [blame] | 341 | rc = qpnp_iadc_write_reg(QPNP_CONV_REQ, qpnp_iadc_conv_req); |
| 342 | if (rc) { |
| 343 | pr_err("qpnp adc read adc failed with %d\n", rc); |
| 344 | return rc; |
| 345 | } |
| 346 | |
| 347 | wait_for_completion(&iadc->adc->adc_rslt_completion); |
| 348 | |
| 349 | rc = qpnp_iadc_read_conversion_result(result); |
| 350 | if (rc) { |
| 351 | pr_err("qpnp adc read adc failed with %d\n", rc); |
| 352 | return rc; |
| 353 | } |
| 354 | |
| 355 | return 0; |
| 356 | } |
| 357 | |
| 358 | static int32_t qpnp_iadc_init_calib(void) |
| 359 | { |
| 360 | struct qpnp_iadc_drv *iadc = qpnp_iadc; |
| 361 | int32_t rc = 0, result; |
| 362 | |
| 363 | rc = qpnp_iadc_configure(GAIN_CALIBRATION_25MV, &result); |
| 364 | if (rc < 0) { |
| 365 | pr_err("qpnp adc result read failed with %d\n", rc); |
| 366 | goto fail; |
| 367 | } |
| 368 | |
| 369 | iadc->adc->calib.gain = result; |
| 370 | |
| 371 | rc = qpnp_iadc_configure(OFFSET_CALIBRATION_SHORT_CADC_LEADS, |
| 372 | &result); |
| 373 | if (rc < 0) { |
| 374 | pr_err("qpnp adc result read failed with %d\n", rc); |
| 375 | goto fail; |
| 376 | } |
| 377 | |
| 378 | iadc->adc->calib.offset = result; |
| 379 | |
| 380 | fail: |
| 381 | return rc; |
| 382 | } |
| 383 | |
Siddartha Mohanadoss | 5ace110 | 2012-08-20 23:18:10 -0700 | [diff] [blame^] | 384 | static int32_t qpnp_iadc_version_check(void) |
| 385 | { |
| 386 | uint8_t revision; |
| 387 | int rc; |
| 388 | |
| 389 | rc = qpnp_iadc_read_reg(QPNP_IADC_REVISION2, &revision); |
| 390 | if (rc < 0) { |
| 391 | pr_err("qpnp adc result read failed with %d\n", rc); |
| 392 | return rc; |
| 393 | } |
| 394 | |
| 395 | if (revision < QPNP_IADC_SUPPORTED_REVISION2) { |
| 396 | pr_err("IADC Version not supported\n"); |
| 397 | return -EINVAL; |
| 398 | } |
| 399 | |
| 400 | return 0; |
| 401 | } |
| 402 | |
| 403 | int32_t qpnp_iadc_is_ready(void) |
| 404 | { |
| 405 | struct qpnp_iadc_drv *iadc = qpnp_iadc; |
| 406 | |
| 407 | if (!iadc || !iadc->iadc_initialized) |
| 408 | return -EPROBE_DEFER; |
| 409 | else |
| 410 | return 0; |
| 411 | } |
| 412 | EXPORT_SYMBOL(qpnp_iadc_is_ready); |
| 413 | |
Siddartha Mohanadoss | c4a6af1 | 2012-07-13 18:50:12 -0700 | [diff] [blame] | 414 | int32_t qpnp_iadc_read(enum qpnp_iadc_channels channel, |
| 415 | int32_t *result) |
| 416 | { |
| 417 | struct qpnp_iadc_drv *iadc = qpnp_iadc; |
| 418 | int32_t vsense_mv = 0, rc; |
| 419 | |
Siddartha Mohanadoss | 5ace110 | 2012-08-20 23:18:10 -0700 | [diff] [blame^] | 420 | if (!iadc || !iadc->iadc_initialized) |
| 421 | return -EPROBE_DEFER; |
| 422 | |
Siddartha Mohanadoss | c4a6af1 | 2012-07-13 18:50:12 -0700 | [diff] [blame] | 423 | mutex_lock(&iadc->adc->adc_lock); |
| 424 | |
| 425 | if (!iadc->iadc_init_calib) { |
Siddartha Mohanadoss | 5ace110 | 2012-08-20 23:18:10 -0700 | [diff] [blame^] | 426 | rc = qpnp_iadc_version_check(); |
| 427 | if (rc) |
| 428 | goto fail; |
Siddartha Mohanadoss | c4a6af1 | 2012-07-13 18:50:12 -0700 | [diff] [blame] | 429 | rc = qpnp_iadc_init_calib(); |
Siddartha Mohanadoss | 5ace110 | 2012-08-20 23:18:10 -0700 | [diff] [blame^] | 430 | if (rc) { |
Siddartha Mohanadoss | c4a6af1 | 2012-07-13 18:50:12 -0700 | [diff] [blame] | 431 | pr_err("Calibration failed\n"); |
| 432 | goto fail; |
| 433 | } else |
| 434 | iadc->iadc_init_calib = true; |
| 435 | } |
| 436 | |
| 437 | rc = qpnp_iadc_configure(channel, result); |
| 438 | if (rc < 0) { |
| 439 | pr_err("qpnp adc result read failed with %d\n", rc); |
| 440 | goto fail; |
| 441 | } |
| 442 | |
Siddartha Mohanadoss | 5ace110 | 2012-08-20 23:18:10 -0700 | [diff] [blame^] | 443 | *result = ((vsense_mv - iadc->adc->calib.offset) * |
| 444 | QPNP_ADC_GAIN_CALCULATION_UV)/ |
| 445 | (iadc->adc->calib.gain - iadc->adc->calib.offset); |
Siddartha Mohanadoss | c4a6af1 | 2012-07-13 18:50:12 -0700 | [diff] [blame] | 446 | |
Siddartha Mohanadoss | 5ace110 | 2012-08-20 23:18:10 -0700 | [diff] [blame^] | 447 | *result = (*result / (qpnp_iadc->rsense)); |
Siddartha Mohanadoss | c4a6af1 | 2012-07-13 18:50:12 -0700 | [diff] [blame] | 448 | fail: |
| 449 | mutex_unlock(&iadc->adc->adc_lock); |
| 450 | |
| 451 | return rc; |
| 452 | } |
| 453 | EXPORT_SYMBOL(qpnp_iadc_read); |
| 454 | |
| 455 | int32_t qpnp_iadc_get_gain(int32_t *result) |
| 456 | { |
| 457 | return qpnp_iadc_read(GAIN_CALIBRATION_25MV, result); |
| 458 | } |
| 459 | EXPORT_SYMBOL(qpnp_iadc_get_gain); |
| 460 | |
| 461 | int32_t qpnp_iadc_get_offset(enum qpnp_iadc_channels channel, |
| 462 | int32_t *result) |
| 463 | { |
| 464 | return qpnp_iadc_read(channel, result); |
| 465 | } |
| 466 | EXPORT_SYMBOL(qpnp_iadc_get_offset); |
| 467 | |
| 468 | static ssize_t qpnp_iadc_show(struct device *dev, |
| 469 | struct device_attribute *devattr, char *buf) |
| 470 | { |
| 471 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); |
| 472 | int32_t result; |
| 473 | int rc = -1; |
| 474 | |
| 475 | rc = qpnp_iadc_read(attr->index, &result); |
| 476 | |
| 477 | if (rc) |
| 478 | return 0; |
| 479 | |
| 480 | return snprintf(buf, QPNP_ADC_HWMON_NAME_LENGTH, |
| 481 | "Result:%d\n", result); |
| 482 | } |
| 483 | |
| 484 | static struct sensor_device_attribute qpnp_adc_attr = |
| 485 | SENSOR_ATTR(NULL, S_IRUGO, qpnp_iadc_show, NULL, 0); |
| 486 | |
| 487 | static int32_t qpnp_iadc_init_hwmon(struct spmi_device *spmi) |
| 488 | { |
| 489 | struct qpnp_iadc_drv *iadc = qpnp_iadc; |
| 490 | struct device_node *child; |
| 491 | struct device_node *node = spmi->dev.of_node; |
| 492 | int rc = 0, i = 0, channel; |
| 493 | |
| 494 | for_each_child_of_node(node, child) { |
| 495 | channel = iadc->adc->adc_channels[i].channel_num; |
| 496 | qpnp_adc_attr.index = iadc->adc->adc_channels[i].channel_num; |
| 497 | qpnp_adc_attr.dev_attr.attr.name = |
| 498 | iadc->adc->adc_channels[i].name; |
| 499 | sysfs_attr_init(&iadc->sens_attr[i].dev_attr.attr); |
| 500 | memcpy(&iadc->sens_attr[i], &qpnp_adc_attr, |
| 501 | sizeof(qpnp_adc_attr)); |
| 502 | rc = device_create_file(&spmi->dev, |
| 503 | &iadc->sens_attr[i].dev_attr); |
| 504 | if (rc) { |
| 505 | dev_err(&spmi->dev, |
| 506 | "device_create_file failed for dev %s\n", |
| 507 | iadc->adc->adc_channels[i].name); |
| 508 | goto hwmon_err_sens; |
| 509 | } |
| 510 | i++; |
| 511 | } |
| 512 | |
| 513 | return 0; |
| 514 | hwmon_err_sens: |
| 515 | pr_err("Init HWMON failed for qpnp_iadc with %d\n", rc); |
| 516 | return rc; |
| 517 | } |
| 518 | |
| 519 | static int __devinit qpnp_iadc_probe(struct spmi_device *spmi) |
| 520 | { |
| 521 | struct qpnp_iadc_drv *iadc; |
| 522 | struct qpnp_adc_drv *adc_qpnp; |
| 523 | struct device_node *node = spmi->dev.of_node; |
| 524 | struct device_node *child; |
| 525 | int rc, count_adc_channel_list = 0; |
| 526 | |
| 527 | if (!node) |
| 528 | return -EINVAL; |
| 529 | |
| 530 | if (qpnp_iadc) { |
| 531 | pr_err("IADC already in use\n"); |
| 532 | return -EBUSY; |
| 533 | } |
| 534 | |
| 535 | for_each_child_of_node(node, child) |
| 536 | count_adc_channel_list++; |
| 537 | |
| 538 | if (!count_adc_channel_list) { |
| 539 | pr_err("No channel listing\n"); |
| 540 | return -EINVAL; |
| 541 | } |
| 542 | |
| 543 | iadc = devm_kzalloc(&spmi->dev, sizeof(struct qpnp_iadc_drv) + |
| 544 | (sizeof(struct sensor_device_attribute) * |
| 545 | count_adc_channel_list), GFP_KERNEL); |
| 546 | if (!iadc) { |
| 547 | dev_err(&spmi->dev, "Unable to allocate memory\n"); |
| 548 | return -ENOMEM; |
| 549 | } |
| 550 | |
| 551 | adc_qpnp = devm_kzalloc(&spmi->dev, sizeof(struct qpnp_adc_drv), |
| 552 | GFP_KERNEL); |
| 553 | if (!adc_qpnp) { |
| 554 | dev_err(&spmi->dev, "Unable to allocate memory\n"); |
| 555 | return -ENOMEM; |
| 556 | } |
| 557 | |
| 558 | iadc->adc = adc_qpnp; |
| 559 | |
| 560 | rc = qpnp_adc_get_devicetree_data(spmi, iadc->adc); |
| 561 | if (rc) { |
| 562 | dev_err(&spmi->dev, "failed to read device tree\n"); |
| 563 | return rc; |
| 564 | } |
| 565 | |
| 566 | rc = of_property_read_u32(node, "qcom,rsense", |
| 567 | &iadc->rsense); |
| 568 | if (rc) { |
| 569 | pr_err("Invalid rsens reference property\n"); |
| 570 | return -EINVAL; |
| 571 | } |
| 572 | |
| 573 | rc = devm_request_irq(&spmi->dev, iadc->adc->adc_irq, |
| 574 | qpnp_iadc_isr, |
| 575 | IRQF_TRIGGER_RISING, "qpnp_iadc_interrupt", iadc); |
| 576 | if (rc) { |
| 577 | dev_err(&spmi->dev, "failed to request adc irq\n"); |
| 578 | return rc; |
| 579 | } else |
| 580 | enable_irq_wake(iadc->adc->adc_irq); |
| 581 | |
| 582 | iadc->iadc_init_calib = false; |
| 583 | dev_set_drvdata(&spmi->dev, iadc); |
| 584 | qpnp_iadc = iadc; |
| 585 | |
| 586 | rc = qpnp_iadc_init_hwmon(spmi); |
| 587 | if (rc) { |
| 588 | dev_err(&spmi->dev, "failed to initialize qpnp hwmon adc\n"); |
| 589 | return rc; |
| 590 | } |
| 591 | iadc->iadc_hwmon = hwmon_device_register(&iadc->adc->spmi->dev); |
| 592 | |
| 593 | rc = qpnp_iadc_configure_interrupt(); |
| 594 | if (rc) { |
| 595 | dev_err(&spmi->dev, "failed to configure interrupt"); |
| 596 | return rc; |
| 597 | } |
| 598 | |
| 599 | return 0; |
| 600 | } |
| 601 | |
| 602 | static int __devexit qpnp_iadc_remove(struct spmi_device *spmi) |
| 603 | { |
| 604 | struct qpnp_iadc_drv *iadc = dev_get_drvdata(&spmi->dev); |
| 605 | struct device_node *node = spmi->dev.of_node; |
| 606 | struct device_node *child; |
| 607 | int i = 0; |
| 608 | |
| 609 | for_each_child_of_node(node, child) { |
| 610 | device_remove_file(&spmi->dev, |
| 611 | &iadc->sens_attr[i].dev_attr); |
| 612 | i++; |
| 613 | } |
| 614 | dev_set_drvdata(&spmi->dev, NULL); |
| 615 | |
| 616 | return 0; |
| 617 | } |
| 618 | |
| 619 | static const struct of_device_id qpnp_iadc_match_table[] = { |
| 620 | { .compatible = "qcom,qpnp-iadc", |
| 621 | }, |
| 622 | {} |
| 623 | }; |
| 624 | |
| 625 | static struct spmi_driver qpnp_iadc_driver = { |
| 626 | .driver = { |
| 627 | .name = "qcom,qpnp-iadc", |
| 628 | .of_match_table = qpnp_iadc_match_table, |
| 629 | }, |
| 630 | .probe = qpnp_iadc_probe, |
| 631 | .remove = qpnp_iadc_remove, |
| 632 | }; |
| 633 | |
| 634 | static int __init qpnp_iadc_init(void) |
| 635 | { |
| 636 | return spmi_driver_register(&qpnp_iadc_driver); |
| 637 | } |
| 638 | module_init(qpnp_iadc_init); |
| 639 | |
| 640 | static void __exit qpnp_iadc_exit(void) |
| 641 | { |
| 642 | spmi_driver_unregister(&qpnp_iadc_driver); |
| 643 | } |
| 644 | module_exit(qpnp_iadc_exit); |
| 645 | |
| 646 | MODULE_DESCRIPTION("QPNP PMIC current ADC driver"); |
| 647 | MODULE_LICENSE("GPL v2"); |