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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04002 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
Alan Coxab771632008-10-27 15:09:10 +000017 * Copyright (C) 2003 Red Hat Inc
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040018 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
Alan Coxd96212e2005-12-08 19:19:50 +000040 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
Alan2c5ff672006-12-04 16:33:20 +000043 * driver the list of errata that are relevant is below, going back to
Alan Coxd96212e2005-12-08 19:19:50 +000044 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
Linus Torvalds1da177e2005-04-16 15:20:36 -070083 */
84
85#include <linux/kernel.h>
86#include <linux/module.h>
87#include <linux/pci.h>
88#include <linux/init.h>
89#include <linux/blkdev.h>
90#include <linux/delay.h>
Jeff Garzik6248e642005-10-30 06:42:18 -050091#include <linux/device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070092#include <scsi/scsi_host.h>
93#include <linux/libata.h>
Tejun Heob8b275e2007-07-10 15:55:43 +090094#include <linux/dmi.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070095
96#define DRV_NAME "ata_piix"
Jeff Garzik2a3103c2007-08-31 04:54:06 -040097#define DRV_VERSION "2.12"
Linus Torvalds1da177e2005-04-16 15:20:36 -070098
99enum {
100 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
101 ICH5_PMR = 0x90, /* port mapping register */
102 ICH5_PCS = 0x92, /* port control and status */
Tejun Heoc7290722008-01-18 18:36:30 +0900103 PIIX_SIDPR_BAR = 5,
104 PIIX_SIDPR_LEN = 16,
105 PIIX_SIDPR_IDX = 0,
106 PIIX_SIDPR_DATA = 4,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700107
Tejun Heoff0fc142005-12-18 17:17:07 +0900108 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
Tejun Heoc7290722008-01-18 18:36:30 +0900109 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700110
Tejun Heo800b3992006-12-03 21:34:13 +0900111 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
112 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
Tejun Heob3362f82006-11-10 18:08:10 +0900113
Linus Torvalds1da177e2005-04-16 15:20:36 -0700114 PIIX_80C_PRI = (1 << 5) | (1 << 4),
115 PIIX_80C_SEC = (1 << 7) | (1 << 6),
116
Tejun Heod33f58b2006-03-01 01:25:39 +0900117 /* constants for mapping table */
118 P0 = 0, /* port 0 */
119 P1 = 1, /* port 1 */
120 P2 = 2, /* port 2 */
121 P3 = 3, /* port 3 */
122 IDE = -1, /* IDE */
123 NA = -2, /* not avaliable */
124 RV = -3, /* reserved */
125
Greg Felix7b6dbd62005-07-28 15:54:15 -0400126 PIIX_AHCI_DEVICE = 6,
Tejun Heob8b275e2007-07-10 15:55:43 +0900127
128 /* host->flags bits */
129 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700130};
131
Tejun Heo9cde9ed12007-11-24 21:16:07 +0900132enum piix_controller_ids {
133 /* controller IDs */
134 piix_pata_mwdma, /* PIIX3 MWDMA only */
135 piix_pata_33, /* PIIX4 at 33Mhz */
136 ich_pata_33, /* ICH up to UDMA 33 only */
137 ich_pata_66, /* ICH up to 66 Mhz */
138 ich_pata_100, /* ICH up to UDMA 100 */
139 ich5_sata,
140 ich6_sata,
Tejun Heo9c0bf672008-03-26 16:00:58 +0900141 ich6m_sata,
142 ich8_sata,
Tejun Heo9cde9ed12007-11-24 21:16:07 +0900143 ich8_2port_sata,
Tejun Heo9c0bf672008-03-26 16:00:58 +0900144 ich8m_apple_sata, /* locks up on second port enable */
145 tolapai_sata,
Tejun Heo9cde9ed12007-11-24 21:16:07 +0900146 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
147};
148
Tejun Heod33f58b2006-03-01 01:25:39 +0900149struct piix_map_db {
150 const u32 mask;
Jeff Garzik73291a12006-07-11 13:11:17 -0400151 const u16 port_enable;
Tejun Heod33f58b2006-03-01 01:25:39 +0900152 const int map[][4];
153};
154
Tejun Heod96715c2006-06-29 01:58:28 +0900155struct piix_host_priv {
156 const int *map;
Tejun Heo2852bcf2009-01-02 12:04:48 +0900157 u32 saved_iocfg;
Tejun Heoc7290722008-01-18 18:36:30 +0900158 void __iomem *sidpr;
Tejun Heod96715c2006-06-29 01:58:28 +0900159};
160
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400161static int piix_init_one(struct pci_dev *pdev,
162 const struct pci_device_id *ent);
Tejun Heo2852bcf2009-01-02 12:04:48 +0900163static void piix_remove_one(struct pci_dev *pdev);
Tejun Heoa1efdab2008-03-25 12:22:50 +0900164static int piix_pata_prereset(struct ata_link *link, unsigned long deadline);
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400165static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev);
166static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
167static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
Alan Coxeb4a2c72007-04-11 00:04:20 +0100168static int ich_pata_cable_detect(struct ata_port *ap);
Tejun Heo25f98132008-01-07 19:38:53 +0900169static u8 piix_vmw_bmdma_status(struct ata_port *ap);
Tejun Heo82ef04f2008-07-31 17:02:40 +0900170static int piix_sidpr_scr_read(struct ata_link *link,
171 unsigned int reg, u32 *val);
172static int piix_sidpr_scr_write(struct ata_link *link,
173 unsigned int reg, u32 val);
Tejun Heob8b275e2007-07-10 15:55:43 +0900174#ifdef CONFIG_PM
175static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
176static int piix_pci_device_resume(struct pci_dev *pdev);
177#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700178
179static unsigned int in_module_init = 1;
180
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500181static const struct pci_device_id piix_pci_tbl[] = {
Aland2cdfc02007-01-10 17:13:38 +0000182 /* Intel PIIX3 for the 430HX etc */
183 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
Tejun Heo25f98132008-01-07 19:38:53 +0900184 /* VMware ICH4 */
185 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400186 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
187 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
188 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400189 /* Intel PIIX4 */
190 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
191 /* Intel PIIX4 */
192 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
193 /* Intel PIIX */
194 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
195 /* Intel ICH (i810, i815, i840) UDMA 66*/
196 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
197 /* Intel ICH0 : UDMA 33*/
198 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
199 /* Intel ICH2M */
200 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
201 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
202 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
203 /* Intel ICH3M */
204 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
205 /* Intel ICH3 (E7500/1) UDMA 100 */
206 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
207 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
208 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
209 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
210 /* Intel ICH5 */
Christian Lamparter2eb829e2007-08-10 13:59:51 -0700211 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400212 /* C-ICH (i810E2) */
213 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
Jeff Garzik85cd7252006-08-31 00:03:49 -0400214 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400215 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
216 /* ICH6 (and 6) (i915) UDMA 100 */
217 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
218 /* ICH7/7-R (i945, i975) UDMA 100*/
Christian Lamparter2eb829e2007-08-10 13:59:51 -0700219 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400220 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
Christian Lamparterc1e6f282007-07-03 10:19:20 -0400221 /* ICH8 Mobile PATA Controller */
222 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700223
224 /* NOTE: The following PCI ids must be kept in sync with the
225 * list in drivers/pci/quirks.c.
226 */
227
Tejun Heo1d076e52006-03-01 01:25:39 +0900228 /* 82801EB (ICH5) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700229 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
Tejun Heo1d076e52006-03-01 01:25:39 +0900230 /* 82801EB (ICH5) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700231 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
Tejun Heo1d076e52006-03-01 01:25:39 +0900232 /* 6300ESB (ICH5 variant with broken PCS present bits) */
Tejun Heo5e56a372006-11-10 18:08:10 +0900233 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
Tejun Heo1d076e52006-03-01 01:25:39 +0900234 /* 6300ESB pretending RAID */
Tejun Heo5e56a372006-11-10 18:08:10 +0900235 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
Tejun Heo1d076e52006-03-01 01:25:39 +0900236 /* 82801FB/FW (ICH6/ICH6W) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700237 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
Tejun Heo1d076e52006-03-01 01:25:39 +0900238 /* 82801FR/FRW (ICH6R/ICH6RW) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900239 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
Tejun Heo5016d7d2008-03-26 15:46:58 +0900240 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
241 * Attach iff the controller is in IDE mode. */
242 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
Tejun Heo9c0bf672008-03-26 16:00:58 +0900243 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata },
Tejun Heo1d076e52006-03-01 01:25:39 +0900244 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900245 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
Tejun Heo1d076e52006-03-01 01:25:39 +0900246 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900247 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800248 /* Enterprise Southbridge 2 (631xESB/632xESB) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900249 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800250 /* SATA Controller 1 IDE (ICH8) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900251 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800252 /* SATA Controller 2 IDE (ICH8) */
Tejun Heo00242ec2007-11-19 11:24:25 +0900253 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
Thomas Rohwer8d8ef2f2007-11-19 11:54:24 +0900254 /* Mobile SATA Controller IDE (ICH8M), Apple */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900255 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
Tejun Heo23cf2962008-05-29 22:04:22 +0900256 { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata },
Tejun Heo487eff62008-07-29 15:06:26 +0900257 { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata },
Tejun Heo23cf2962008-05-29 22:04:22 +0900258 /* Mobile SATA Controller IDE (ICH8M) */
259 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800260 /* SATA Controller IDE (ICH9) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900261 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800262 /* SATA Controller IDE (ICH9) */
Tejun Heo00242ec2007-11-19 11:24:25 +0900263 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800264 /* SATA Controller IDE (ICH9) */
Tejun Heo00242ec2007-11-19 11:24:25 +0900265 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800266 /* SATA Controller IDE (ICH9M) */
Tejun Heo00242ec2007-11-19 11:24:25 +0900267 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800268 /* SATA Controller IDE (ICH9M) */
Tejun Heo00242ec2007-11-19 11:24:25 +0900269 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800270 /* SATA Controller IDE (ICH9M) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900271 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
Jason Gastonc5cf0ff2007-08-30 21:36:56 -0700272 /* SATA Controller IDE (Tolapai) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900273 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata },
Jason Gastonbf7f22b2008-01-28 17:36:45 -0800274 /* SATA Controller IDE (ICH10) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900275 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
Jason Gastonbf7f22b2008-01-28 17:36:45 -0800276 /* SATA Controller IDE (ICH10) */
277 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
278 /* SATA Controller IDE (ICH10) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900279 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
Jason Gastonbf7f22b2008-01-28 17:36:45 -0800280 /* SATA Controller IDE (ICH10) */
281 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
Seth Heasleyc6c6a1a2008-08-11 17:03:18 -0700282 /* SATA Controller IDE (PCH) */
283 { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
284 /* SATA Controller IDE (PCH) */
Seth Heasley0395e612008-08-27 16:40:06 -0700285 { 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
286 /* SATA Controller IDE (PCH) */
Seth Heasleyc6c6a1a2008-08-11 17:03:18 -0700287 { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
288 /* SATA Controller IDE (PCH) */
Seth Heasley0395e612008-08-27 16:40:06 -0700289 { 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
290 /* SATA Controller IDE (PCH) */
Seth Heasleyc6c6a1a2008-08-11 17:03:18 -0700291 { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
292 /* SATA Controller IDE (PCH) */
293 { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700294 { } /* terminate list */
295};
296
297static struct pci_driver piix_pci_driver = {
298 .name = DRV_NAME,
299 .id_table = piix_pci_tbl,
300 .probe = piix_init_one,
Tejun Heo2852bcf2009-01-02 12:04:48 +0900301 .remove = piix_remove_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900302#ifdef CONFIG_PM
Tejun Heob8b275e2007-07-10 15:55:43 +0900303 .suspend = piix_pci_device_suspend,
304 .resume = piix_pci_device_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900305#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700306};
307
Jeff Garzik193515d2005-11-07 00:59:37 -0500308static struct scsi_host_template piix_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900309 ATA_BMDMA_SHT(DRV_NAME),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700310};
311
Tejun Heo029cfd62008-03-25 12:22:49 +0900312static struct ata_port_operations piix_pata_ops = {
Alan Cox871af122009-01-05 14:16:39 +0000313 .inherits = &ata_bmdma32_port_ops,
Alan Coxeb4a2c72007-04-11 00:04:20 +0100314 .cable_detect = ata_cable_40wire,
Tejun Heo25f98132008-01-07 19:38:53 +0900315 .set_piomode = piix_set_piomode,
316 .set_dmamode = piix_set_dmamode,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900317 .prereset = piix_pata_prereset,
Tejun Heo029cfd62008-03-25 12:22:49 +0900318};
Tejun Heo25f98132008-01-07 19:38:53 +0900319
Tejun Heo029cfd62008-03-25 12:22:49 +0900320static struct ata_port_operations piix_vmw_ops = {
321 .inherits = &piix_pata_ops,
Tejun Heo25f98132008-01-07 19:38:53 +0900322 .bmdma_status = piix_vmw_bmdma_status,
Tejun Heo25f98132008-01-07 19:38:53 +0900323};
324
Tejun Heo029cfd62008-03-25 12:22:49 +0900325static struct ata_port_operations ich_pata_ops = {
326 .inherits = &piix_pata_ops,
327 .cable_detect = ich_pata_cable_detect,
328 .set_dmamode = ich_set_dmamode,
329};
Tejun Heoc7290722008-01-18 18:36:30 +0900330
Tejun Heo029cfd62008-03-25 12:22:49 +0900331static struct ata_port_operations piix_sata_ops = {
332 .inherits = &ata_bmdma_port_ops,
333};
Tejun Heoc7290722008-01-18 18:36:30 +0900334
Tejun Heo029cfd62008-03-25 12:22:49 +0900335static struct ata_port_operations piix_sidpr_sata_ops = {
336 .inherits = &piix_sata_ops,
Tejun Heo57c9efd2008-04-07 22:47:19 +0900337 .hardreset = sata_std_hardreset,
Tejun Heoc7290722008-01-18 18:36:30 +0900338 .scr_read = piix_sidpr_scr_read,
339 .scr_write = piix_sidpr_scr_write,
Tejun Heoc7290722008-01-18 18:36:30 +0900340};
341
Tejun Heod96715c2006-06-29 01:58:28 +0900342static const struct piix_map_db ich5_map_db = {
Tejun Heod33f58b2006-03-01 01:25:39 +0900343 .mask = 0x7,
Jeff Garzikea35d292006-07-11 11:48:50 -0400344 .port_enable = 0x3,
Tejun Heod33f58b2006-03-01 01:25:39 +0900345 .map = {
346 /* PM PS SM SS MAP */
347 { P0, NA, P1, NA }, /* 000b */
348 { P1, NA, P0, NA }, /* 001b */
349 { RV, RV, RV, RV },
350 { RV, RV, RV, RV },
351 { P0, P1, IDE, IDE }, /* 100b */
352 { P1, P0, IDE, IDE }, /* 101b */
353 { IDE, IDE, P0, P1 }, /* 110b */
354 { IDE, IDE, P1, P0 }, /* 111b */
355 },
356};
357
Tejun Heod96715c2006-06-29 01:58:28 +0900358static const struct piix_map_db ich6_map_db = {
Tejun Heod33f58b2006-03-01 01:25:39 +0900359 .mask = 0x3,
Jeff Garzikea35d292006-07-11 11:48:50 -0400360 .port_enable = 0xf,
Tejun Heod33f58b2006-03-01 01:25:39 +0900361 .map = {
362 /* PM PS SM SS MAP */
Tejun Heo79ea24e2006-03-31 20:01:50 +0900363 { P0, P2, P1, P3 }, /* 00b */
Tejun Heod33f58b2006-03-01 01:25:39 +0900364 { IDE, IDE, P1, P3 }, /* 01b */
365 { P0, P2, IDE, IDE }, /* 10b */
366 { RV, RV, RV, RV },
367 },
368};
369
Tejun Heod96715c2006-06-29 01:58:28 +0900370static const struct piix_map_db ich6m_map_db = {
Tejun Heod33f58b2006-03-01 01:25:39 +0900371 .mask = 0x3,
Jeff Garzikea35d292006-07-11 11:48:50 -0400372 .port_enable = 0x5,
Tejun Heo67083742006-09-11 06:29:03 +0900373
374 /* Map 01b isn't specified in the doc but some notebooks use
Tejun Heoc6446a42006-10-09 13:23:58 +0900375 * it anyway. MAP 01b have been spotted on both ICH6M and
376 * ICH7M.
Tejun Heo67083742006-09-11 06:29:03 +0900377 */
378 .map = {
379 /* PM PS SM SS MAP */
Tejun Heoe04b3b92007-07-10 17:58:21 +0900380 { P0, P2, NA, NA }, /* 00b */
Tejun Heo67083742006-09-11 06:29:03 +0900381 { IDE, IDE, P1, P3 }, /* 01b */
382 { P0, P2, IDE, IDE }, /* 10b */
383 { RV, RV, RV, RV },
384 },
385};
386
Jeff Garzik08f12ed2006-07-11 11:57:44 -0400387static const struct piix_map_db ich8_map_db = {
388 .mask = 0x3,
Tejun Heoa0ce9ac2007-11-19 12:06:37 +0900389 .port_enable = 0xf,
Jeff Garzik08f12ed2006-07-11 11:57:44 -0400390 .map = {
391 /* PM PS SM SS MAP */
Kristen Carlson Accardi158f30c82006-10-19 13:27:39 -0700392 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
Jeff Garzik08f12ed2006-07-11 11:57:44 -0400393 { RV, RV, RV, RV },
Tejun Heoac2b0432007-08-07 02:43:27 +0900394 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
Jeff Garzik08f12ed2006-07-11 11:57:44 -0400395 { RV, RV, RV, RV },
396 },
397};
398
Tejun Heo00242ec2007-11-19 11:24:25 +0900399static const struct piix_map_db ich8_2port_map_db = {
Jason Gastone2d352a2007-09-07 17:21:03 -0700400 .mask = 0x3,
401 .port_enable = 0x3,
402 .map = {
403 /* PM PS SM SS MAP */
404 { P0, NA, P1, NA }, /* 00b */
405 { RV, RV, RV, RV }, /* 01b */
406 { RV, RV, RV, RV }, /* 10b */
407 { RV, RV, RV, RV },
408 },
Jason Gastonc5cf0ff2007-08-30 21:36:56 -0700409};
410
Thomas Rohwer8d8ef2f2007-11-19 11:54:24 +0900411static const struct piix_map_db ich8m_apple_map_db = {
412 .mask = 0x3,
413 .port_enable = 0x1,
414 .map = {
415 /* PM PS SM SS MAP */
416 { P0, NA, NA, NA }, /* 00b */
417 { RV, RV, RV, RV },
418 { P0, P2, IDE, IDE }, /* 10b */
419 { RV, RV, RV, RV },
420 },
421};
422
Tejun Heo00242ec2007-11-19 11:24:25 +0900423static const struct piix_map_db tolapai_map_db = {
Jason Gaston8f73a682007-10-11 16:05:15 -0700424 .mask = 0x3,
425 .port_enable = 0x3,
426 .map = {
427 /* PM PS SM SS MAP */
428 { P0, NA, P1, NA }, /* 00b */
429 { RV, RV, RV, RV }, /* 01b */
430 { RV, RV, RV, RV }, /* 10b */
431 { RV, RV, RV, RV },
432 },
433};
434
Tejun Heod96715c2006-06-29 01:58:28 +0900435static const struct piix_map_db *piix_map_db_table[] = {
436 [ich5_sata] = &ich5_map_db,
Tejun Heod96715c2006-06-29 01:58:28 +0900437 [ich6_sata] = &ich6_map_db,
Tejun Heo9c0bf672008-03-26 16:00:58 +0900438 [ich6m_sata] = &ich6m_map_db,
439 [ich8_sata] = &ich8_map_db,
Tejun Heo00242ec2007-11-19 11:24:25 +0900440 [ich8_2port_sata] = &ich8_2port_map_db,
Tejun Heo9c0bf672008-03-26 16:00:58 +0900441 [ich8m_apple_sata] = &ich8m_apple_map_db,
442 [tolapai_sata] = &tolapai_map_db,
Tejun Heod96715c2006-06-29 01:58:28 +0900443};
444
Linus Torvalds1da177e2005-04-16 15:20:36 -0700445static struct ata_port_info piix_port_info[] = {
Tejun Heo00242ec2007-11-19 11:24:25 +0900446 [piix_pata_mwdma] = /* PIIX3 MWDMA only */
447 {
Tejun Heo00242ec2007-11-19 11:24:25 +0900448 .flags = PIIX_PATA_FLAGS,
449 .pio_mask = 0x1f, /* pio0-4 */
450 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
451 .port_ops = &piix_pata_ops,
452 },
453
Jeff Garzikec300d92007-09-01 07:17:36 -0400454 [piix_pata_33] = /* PIIX4 at 33MHz */
Tejun Heo1d076e52006-03-01 01:25:39 +0900455 {
Tejun Heob3362f82006-11-10 18:08:10 +0900456 .flags = PIIX_PATA_FLAGS,
Tejun Heo1d076e52006-03-01 01:25:39 +0900457 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400458 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
Tejun Heo1d076e52006-03-01 01:25:39 +0900459 .udma_mask = ATA_UDMA_MASK_40C,
460 .port_ops = &piix_pata_ops,
461 },
462
Jeff Garzikec300d92007-09-01 07:17:36 -0400463 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
Linus Torvalds1da177e2005-04-16 15:20:36 -0700464 {
Tejun Heob3362f82006-11-10 18:08:10 +0900465 .flags = PIIX_PATA_FLAGS,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400466 .pio_mask = 0x1f, /* pio 0-4 */
467 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
468 .udma_mask = ATA_UDMA2, /* UDMA33 */
469 .port_ops = &ich_pata_ops,
470 },
Jeff Garzikec300d92007-09-01 07:17:36 -0400471
472 [ich_pata_66] = /* ICH controllers up to 66MHz */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400473 {
Tejun Heob3362f82006-11-10 18:08:10 +0900474 .flags = PIIX_PATA_FLAGS,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400475 .pio_mask = 0x1f, /* pio 0-4 */
476 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */
477 .udma_mask = ATA_UDMA4,
478 .port_ops = &ich_pata_ops,
479 },
Jeff Garzik85cd7252006-08-31 00:03:49 -0400480
Jeff Garzikec300d92007-09-01 07:17:36 -0400481 [ich_pata_100] =
Jeff Garzik669a5db2006-08-29 18:12:40 -0400482 {
Tejun Heob3362f82006-11-10 18:08:10 +0900483 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700484 .pio_mask = 0x1f, /* pio0-4 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700485 .mwdma_mask = 0x06, /* mwdma1-2 */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400486 .udma_mask = ATA_UDMA5, /* udma0-5 */
487 .port_ops = &ich_pata_ops,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700488 },
489
Jeff Garzikec300d92007-09-01 07:17:36 -0400490 [ich5_sata] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700491 {
Tejun Heo228c1592006-11-10 18:08:10 +0900492 .flags = PIIX_SATA_FLAGS,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700493 .pio_mask = 0x1f, /* pio0-4 */
494 .mwdma_mask = 0x07, /* mwdma0-2 */
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400495 .udma_mask = ATA_UDMA6,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700496 .port_ops = &piix_sata_ops,
497 },
498
Jeff Garzikec300d92007-09-01 07:17:36 -0400499 [ich6_sata] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700500 {
Tejun Heo723159c2008-01-04 18:42:20 +0900501 .flags = PIIX_SATA_FLAGS,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700502 .pio_mask = 0x1f, /* pio0-4 */
503 .mwdma_mask = 0x07, /* mwdma0-2 */
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400504 .udma_mask = ATA_UDMA6,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700505 .port_ops = &piix_sata_ops,
506 },
507
Tejun Heo9c0bf672008-03-26 16:00:58 +0900508 [ich6m_sata] =
Jason Gastonc368ca42005-04-16 15:24:44 -0700509 {
Tejun Heo5016d7d2008-03-26 15:46:58 +0900510 .flags = PIIX_SATA_FLAGS,
Jason Gastonc368ca42005-04-16 15:24:44 -0700511 .pio_mask = 0x1f, /* pio0-4 */
512 .mwdma_mask = 0x07, /* mwdma0-2 */
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400513 .udma_mask = ATA_UDMA6,
Jason Gastonc368ca42005-04-16 15:24:44 -0700514 .port_ops = &piix_sata_ops,
515 },
Tejun Heo1d076e52006-03-01 01:25:39 +0900516
Tejun Heo9c0bf672008-03-26 16:00:58 +0900517 [ich8_sata] =
Jeff Garzik08f12ed2006-07-11 11:57:44 -0400518 {
Tejun Heo5016d7d2008-03-26 15:46:58 +0900519 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
Jeff Garzik08f12ed2006-07-11 11:57:44 -0400520 .pio_mask = 0x1f, /* pio0-4 */
521 .mwdma_mask = 0x07, /* mwdma0-2 */
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400522 .udma_mask = ATA_UDMA6,
Jeff Garzik08f12ed2006-07-11 11:57:44 -0400523 .port_ops = &piix_sata_ops,
524 },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400525
Tejun Heo00242ec2007-11-19 11:24:25 +0900526 [ich8_2port_sata] =
Jason Gastonc5cf0ff2007-08-30 21:36:56 -0700527 {
Tejun Heo5016d7d2008-03-26 15:46:58 +0900528 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
Jason Gastonc5cf0ff2007-08-30 21:36:56 -0700529 .pio_mask = 0x1f, /* pio0-4 */
530 .mwdma_mask = 0x07, /* mwdma0-2 */
531 .udma_mask = ATA_UDMA6,
532 .port_ops = &piix_sata_ops,
533 },
Jason Gaston8f73a682007-10-11 16:05:15 -0700534
Tejun Heo9c0bf672008-03-26 16:00:58 +0900535 [tolapai_sata] =
Jason Gaston8f73a682007-10-11 16:05:15 -0700536 {
Tejun Heo5016d7d2008-03-26 15:46:58 +0900537 .flags = PIIX_SATA_FLAGS,
Jason Gaston8f73a682007-10-11 16:05:15 -0700538 .pio_mask = 0x1f, /* pio0-4 */
539 .mwdma_mask = 0x07, /* mwdma0-2 */
540 .udma_mask = ATA_UDMA6,
541 .port_ops = &piix_sata_ops,
542 },
Thomas Rohwer8d8ef2f2007-11-19 11:54:24 +0900543
Tejun Heo9c0bf672008-03-26 16:00:58 +0900544 [ich8m_apple_sata] =
Thomas Rohwer8d8ef2f2007-11-19 11:54:24 +0900545 {
Tejun Heo23cf2962008-05-29 22:04:22 +0900546 .flags = PIIX_SATA_FLAGS,
Thomas Rohwer8d8ef2f2007-11-19 11:54:24 +0900547 .pio_mask = 0x1f, /* pio0-4 */
548 .mwdma_mask = 0x07, /* mwdma0-2 */
549 .udma_mask = ATA_UDMA6,
550 .port_ops = &piix_sata_ops,
551 },
552
Tejun Heo25f98132008-01-07 19:38:53 +0900553 [piix_pata_vmw] =
554 {
Tejun Heo25f98132008-01-07 19:38:53 +0900555 .flags = PIIX_PATA_FLAGS,
556 .pio_mask = 0x1f, /* pio0-4 */
557 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
558 .udma_mask = ATA_UDMA_MASK_40C,
559 .port_ops = &piix_vmw_ops,
560 },
561
Linus Torvalds1da177e2005-04-16 15:20:36 -0700562};
563
564static struct pci_bits piix_enable_bits[] = {
565 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
566 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
567};
568
569MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
570MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
571MODULE_LICENSE("GPL");
572MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
573MODULE_VERSION(DRV_VERSION);
574
Alan Coxfc085152006-10-10 14:28:11 -0700575struct ich_laptop {
576 u16 device;
577 u16 subvendor;
578 u16 subdevice;
579};
580
581/*
582 * List of laptops that use short cables rather than 80 wire
583 */
584
585static const struct ich_laptop ich_laptop[] = {
586 /* devid, subvendor, subdev */
587 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
Alan Cox2655e2c2007-11-05 22:51:09 +0000588 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
J Jbabfb682007-01-09 02:26:30 +0900589 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
Robin H\. Johnson12340102007-03-28 18:02:07 -0700590 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
Jeff Garzik54174db2007-09-29 04:01:43 -0400591 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
Herton Ronaldo Krzesinskid09addf2008-09-17 14:29:05 -0300592 { 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */
Tejun Heob33620f2007-05-22 11:34:22 +0200593 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
Colin Ian Kinge1fefea2008-06-03 18:59:02 +0200594 { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */
595 { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */
Dan McGee01ce2602008-04-20 22:03:27 -0500596 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
Alan Coxfc085152006-10-10 14:28:11 -0700597 /* end marker */
598 { 0, }
599};
600
Linus Torvalds1da177e2005-04-16 15:20:36 -0700601/**
Alan Coxeb4a2c72007-04-11 00:04:20 +0100602 * ich_pata_cable_detect - Probe host controller cable detect info
Linus Torvalds1da177e2005-04-16 15:20:36 -0700603 * @ap: Port for which cable detect info is desired
604 *
605 * Read 80c cable indicator from ATA PCI device's PCI config
606 * register. This register is normally set by firmware (BIOS).
607 *
608 * LOCKING:
609 * None (inherited from caller).
610 */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400611
Alan Coxeb4a2c72007-04-11 00:04:20 +0100612static int ich_pata_cable_detect(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700613{
Jeff Garzikcca39742006-08-24 03:19:22 -0400614 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Tejun Heo2852bcf2009-01-02 12:04:48 +0900615 struct piix_host_priv *hpriv = ap->host->private_data;
Alan Coxfc085152006-10-10 14:28:11 -0700616 const struct ich_laptop *lap = &ich_laptop[0];
Tejun Heo2852bcf2009-01-02 12:04:48 +0900617 u8 mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700618
Alan Coxfc085152006-10-10 14:28:11 -0700619 /* Check for specials - Acer Aspire 5602WLMi */
620 while (lap->device) {
621 if (lap->device == pdev->device &&
622 lap->subvendor == pdev->subsystem_vendor &&
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400623 lap->subdevice == pdev->subsystem_device)
Alan Coxeb4a2c72007-04-11 00:04:20 +0100624 return ATA_CBL_PATA40_SHORT;
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400625
Alan Coxfc085152006-10-10 14:28:11 -0700626 lap++;
627 }
628
Linus Torvalds1da177e2005-04-16 15:20:36 -0700629 /* check BIOS cable detect results */
Tejun Heo2a88d1a2006-08-10 16:59:16 +0900630 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
Tejun Heo2852bcf2009-01-02 12:04:48 +0900631 if ((hpriv->saved_iocfg & mask) == 0)
Alan Coxeb4a2c72007-04-11 00:04:20 +0100632 return ATA_CBL_PATA40;
633 return ATA_CBL_PATA80;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700634}
635
636/**
Tejun Heoccc46722006-05-31 18:28:14 +0900637 * piix_pata_prereset - prereset for PATA host controller
Tejun Heocc0680a2007-08-06 18:36:23 +0900638 * @link: Target link
Tejun Heod4b2bab2007-02-02 16:50:52 +0900639 * @deadline: deadline jiffies for the operation
Linus Torvalds1da177e2005-04-16 15:20:36 -0700640 *
Linus Torvalds1da177e2005-04-16 15:20:36 -0700641 * LOCKING:
642 * None (inherited from caller).
643 */
Tejun Heocc0680a2007-08-06 18:36:23 +0900644static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700645{
Tejun Heocc0680a2007-08-06 18:36:23 +0900646 struct ata_port *ap = link->ap;
Jeff Garzikcca39742006-08-24 03:19:22 -0400647 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700648
Alan Coxc9619222006-09-26 17:53:38 +0100649 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
650 return -ENOENT;
Tejun Heo9363c382008-04-07 22:47:16 +0900651 return ata_sff_prereset(link, deadline);
Tejun Heoccc46722006-05-31 18:28:14 +0900652}
653
Linus Torvalds1da177e2005-04-16 15:20:36 -0700654/**
655 * piix_set_piomode - Initialize host controller PATA PIO timings
656 * @ap: Port whose timings we are configuring
657 * @adev: um
Linus Torvalds1da177e2005-04-16 15:20:36 -0700658 *
659 * Set PIO mode for device, in host controller PCI config space.
660 *
661 * LOCKING:
662 * None (inherited from caller).
663 */
664
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400665static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700666{
667 unsigned int pio = adev->pio_mode - XFER_PIO_0;
Jeff Garzikcca39742006-08-24 03:19:22 -0400668 struct pci_dev *dev = to_pci_dev(ap->host->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700669 unsigned int is_slave = (adev->devno != 0);
Tejun Heo2a88d1a2006-08-10 16:59:16 +0900670 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700671 unsigned int slave_port = 0x44;
672 u16 master_data;
673 u8 slave_data;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400674 u8 udma_enable;
675 int control = 0;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400676
Jeff Garzik669a5db2006-08-29 18:12:40 -0400677 /*
678 * See Intel Document 298600-004 for the timing programing rules
679 * for ICH controllers.
680 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700681
682 static const /* ISP RTC */
683 u8 timings[][2] = { { 0, 0 },
684 { 0, 0 },
685 { 1, 0 },
686 { 2, 1 },
687 { 2, 3 }, };
688
Jeff Garzik669a5db2006-08-29 18:12:40 -0400689 if (pio >= 2)
690 control |= 1; /* TIME1 enable */
691 if (ata_pio_need_iordy(adev))
692 control |= 2; /* IE enable */
693
Jeff Garzik85cd7252006-08-31 00:03:49 -0400694 /* Intel specifies that the PPE functionality is for disk only */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400695 if (adev->class == ATA_DEV_ATA)
696 control |= 4; /* PPE enable */
697
Tejun Heoa5bf5f52007-05-25 19:16:58 +0200698 /* PIO configuration clears DTE unconditionally. It will be
699 * programmed in set_dmamode which is guaranteed to be called
700 * after set_piomode if any DMA mode is available.
701 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700702 pci_read_config_word(dev, master_port, &master_data);
703 if (is_slave) {
Tejun Heoa5bf5f52007-05-25 19:16:58 +0200704 /* clear TIME1|IE1|PPE1|DTE1 */
705 master_data &= 0xff0f;
Joe Perches1967b7f2008-02-03 17:08:11 +0200706 /* Enable SITRE (separate slave timing register) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700707 master_data |= 0x4000;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400708 /* enable PPE1, IE1 and TIME1 as needed */
709 master_data |= (control << 4);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700710 pci_read_config_byte(dev, slave_port, &slave_data);
Tejun Heo2a88d1a2006-08-10 16:59:16 +0900711 slave_data &= (ap->port_no ? 0x0f : 0xf0);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400712 /* Load the timing nibble for this slave */
Tejun Heoa5bf5f52007-05-25 19:16:58 +0200713 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
714 << (ap->port_no ? 4 : 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700715 } else {
Tejun Heoa5bf5f52007-05-25 19:16:58 +0200716 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
717 master_data &= 0xccf0;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400718 /* Enable PPE, IE and TIME as appropriate */
719 master_data |= control;
Tejun Heoa5bf5f52007-05-25 19:16:58 +0200720 /* load ISP and RCT */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700721 master_data |=
722 (timings[pio][0] << 12) |
723 (timings[pio][1] << 8);
724 }
725 pci_write_config_word(dev, master_port, master_data);
726 if (is_slave)
727 pci_write_config_byte(dev, slave_port, slave_data);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400728
729 /* Ensure the UDMA bit is off - it will be turned back on if
730 UDMA is selected */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400731
Jeff Garzik669a5db2006-08-29 18:12:40 -0400732 if (ap->udma_mask) {
733 pci_read_config_byte(dev, 0x48, &udma_enable);
734 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
735 pci_write_config_byte(dev, 0x48, udma_enable);
736 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700737}
738
739/**
Jeff Garzik669a5db2006-08-29 18:12:40 -0400740 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
Linus Torvalds1da177e2005-04-16 15:20:36 -0700741 * @ap: Port whose timings we are configuring
Jeff Garzik669a5db2006-08-29 18:12:40 -0400742 * @adev: Drive in question
Hennec32a8fd2006-09-25 22:00:46 +0200743 * @isich: set if the chip is an ICH device
Linus Torvalds1da177e2005-04-16 15:20:36 -0700744 *
745 * Set UDMA mode for device, in host controller PCI config space.
746 *
747 * LOCKING:
748 * None (inherited from caller).
749 */
750
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400751static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700752{
Jeff Garzikcca39742006-08-24 03:19:22 -0400753 struct pci_dev *dev = to_pci_dev(ap->host->dev);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400754 u8 master_port = ap->port_no ? 0x42 : 0x40;
755 u16 master_data;
756 u8 speed = adev->dma_mode;
757 int devid = adev->devno + 2 * ap->port_no;
Andrew Mortondedf61d2007-01-10 17:20:34 -0800758 u8 udma_enable = 0;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400759
Jeff Garzik669a5db2006-08-29 18:12:40 -0400760 static const /* ISP RTC */
761 u8 timings[][2] = { { 0, 0 },
762 { 0, 0 },
763 { 1, 0 },
764 { 2, 1 },
765 { 2, 3 }, };
Linus Torvalds1da177e2005-04-16 15:20:36 -0700766
Jeff Garzik669a5db2006-08-29 18:12:40 -0400767 pci_read_config_word(dev, master_port, &master_data);
Aland2cdfc02007-01-10 17:13:38 +0000768 if (ap->udma_mask)
769 pci_read_config_byte(dev, 0x48, &udma_enable);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700770
771 if (speed >= XFER_UDMA_0) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400772 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
773 u16 udma_timing;
774 u16 ideconf;
775 int u_clock, u_speed;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400776
Jeff Garzik669a5db2006-08-29 18:12:40 -0400777 /*
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400778 * UDMA is handled by a combination of clock switching and
Jeff Garzik85cd7252006-08-31 00:03:49 -0400779 * selection of dividers
780 *
Jeff Garzik669a5db2006-08-29 18:12:40 -0400781 * Handy rule: Odd modes are UDMATIMx 01, even are 02
Jeff Garzik85cd7252006-08-31 00:03:49 -0400782 * except UDMA0 which is 00
Jeff Garzik669a5db2006-08-29 18:12:40 -0400783 */
784 u_speed = min(2 - (udma & 1), udma);
785 if (udma == 5)
786 u_clock = 0x1000; /* 100Mhz */
787 else if (udma > 2)
788 u_clock = 1; /* 66Mhz */
789 else
790 u_clock = 0; /* 33Mhz */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400791
Jeff Garzik669a5db2006-08-29 18:12:40 -0400792 udma_enable |= (1 << devid);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400793
Jeff Garzik669a5db2006-08-29 18:12:40 -0400794 /* Load the CT/RP selection */
795 pci_read_config_word(dev, 0x4A, &udma_timing);
796 udma_timing &= ~(3 << (4 * devid));
797 udma_timing |= u_speed << (4 * devid);
798 pci_write_config_word(dev, 0x4A, udma_timing);
799
Jeff Garzik85cd7252006-08-31 00:03:49 -0400800 if (isich) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400801 /* Select a 33/66/100Mhz clock */
802 pci_read_config_word(dev, 0x54, &ideconf);
803 ideconf &= ~(0x1001 << devid);
804 ideconf |= u_clock << devid;
805 /* For ICH or later we should set bit 10 for better
806 performance (WR_PingPong_En) */
807 pci_write_config_word(dev, 0x54, ideconf);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700808 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700809 } else {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400810 /*
811 * MWDMA is driven by the PIO timings. We must also enable
812 * IORDY unconditionally along with TIME1. PPE has already
813 * been set when the PIO timing was set.
814 */
815 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
816 unsigned int control;
817 u8 slave_data;
818 const unsigned int needed_pio[3] = {
819 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
820 };
821 int pio = needed_pio[mwdma] - XFER_PIO_0;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400822
Jeff Garzik669a5db2006-08-29 18:12:40 -0400823 control = 3; /* IORDY|TIME1 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400824
Jeff Garzik669a5db2006-08-29 18:12:40 -0400825 /* If the drive MWDMA is faster than it can do PIO then
826 we must force PIO into PIO0 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400827
Jeff Garzik669a5db2006-08-29 18:12:40 -0400828 if (adev->pio_mode < needed_pio[mwdma])
829 /* Enable DMA timing only */
830 control |= 8; /* PIO cycles in PIO0 */
831
832 if (adev->devno) { /* Slave */
833 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
834 master_data |= control << 4;
835 pci_read_config_byte(dev, 0x44, &slave_data);
Tejun Heoa5bf5f52007-05-25 19:16:58 +0200836 slave_data &= (ap->port_no ? 0x0f : 0xf0);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400837 /* Load the matching timing */
838 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
839 pci_write_config_byte(dev, 0x44, slave_data);
840 } else { /* Master */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400841 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
Jeff Garzik669a5db2006-08-29 18:12:40 -0400842 and master timing bits */
843 master_data |= control;
844 master_data |=
845 (timings[pio][0] << 12) |
846 (timings[pio][1] << 8);
847 }
Tejun Heoa5bf5f52007-05-25 19:16:58 +0200848
849 if (ap->udma_mask) {
850 udma_enable &= ~(1 << devid);
851 pci_write_config_word(dev, master_port, master_data);
852 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700853 }
Jeff Garzik669a5db2006-08-29 18:12:40 -0400854 /* Don't scribble on 0x48 if the controller does not support UDMA */
855 if (ap->udma_mask)
856 pci_write_config_byte(dev, 0x48, udma_enable);
857}
858
859/**
860 * piix_set_dmamode - Initialize host controller PATA DMA timings
861 * @ap: Port whose timings we are configuring
862 * @adev: um
863 *
864 * Set MW/UDMA mode for device, in host controller PCI config space.
865 *
866 * LOCKING:
867 * None (inherited from caller).
868 */
869
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400870static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400871{
872 do_pata_set_dmamode(ap, adev, 0);
873}
874
875/**
876 * ich_set_dmamode - Initialize host controller PATA DMA timings
877 * @ap: Port whose timings we are configuring
878 * @adev: um
879 *
880 * Set MW/UDMA mode for device, in host controller PCI config space.
881 *
882 * LOCKING:
883 * None (inherited from caller).
884 */
885
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400886static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400887{
888 do_pata_set_dmamode(ap, adev, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700889}
890
Tejun Heoc7290722008-01-18 18:36:30 +0900891/*
892 * Serial ATA Index/Data Pair Superset Registers access
893 *
894 * Beginning from ICH8, there's a sane way to access SCRs using index
Tejun Heobe77e432008-07-31 17:02:44 +0900895 * and data register pair located at BAR5 which means that we have
896 * separate SCRs for master and slave. This is handled using libata
897 * slave_link facility.
Tejun Heoc7290722008-01-18 18:36:30 +0900898 */
899static const int piix_sidx_map[] = {
900 [SCR_STATUS] = 0,
901 [SCR_ERROR] = 2,
902 [SCR_CONTROL] = 1,
903};
904
Tejun Heobe77e432008-07-31 17:02:44 +0900905static void piix_sidpr_sel(struct ata_link *link, unsigned int reg)
Tejun Heoc7290722008-01-18 18:36:30 +0900906{
Tejun Heobe77e432008-07-31 17:02:44 +0900907 struct ata_port *ap = link->ap;
Tejun Heoc7290722008-01-18 18:36:30 +0900908 struct piix_host_priv *hpriv = ap->host->private_data;
909
Tejun Heobe77e432008-07-31 17:02:44 +0900910 iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg],
Tejun Heoc7290722008-01-18 18:36:30 +0900911 hpriv->sidpr + PIIX_SIDPR_IDX);
912}
913
Tejun Heo82ef04f2008-07-31 17:02:40 +0900914static int piix_sidpr_scr_read(struct ata_link *link,
915 unsigned int reg, u32 *val)
Tejun Heoc7290722008-01-18 18:36:30 +0900916{
Tejun Heobe77e432008-07-31 17:02:44 +0900917 struct piix_host_priv *hpriv = link->ap->host->private_data;
Tejun Heoc7290722008-01-18 18:36:30 +0900918
919 if (reg >= ARRAY_SIZE(piix_sidx_map))
920 return -EINVAL;
921
Tejun Heobe77e432008-07-31 17:02:44 +0900922 piix_sidpr_sel(link, reg);
923 *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
Tejun Heoc7290722008-01-18 18:36:30 +0900924 return 0;
925}
926
Tejun Heo82ef04f2008-07-31 17:02:40 +0900927static int piix_sidpr_scr_write(struct ata_link *link,
928 unsigned int reg, u32 val)
Tejun Heoc7290722008-01-18 18:36:30 +0900929{
Tejun Heobe77e432008-07-31 17:02:44 +0900930 struct piix_host_priv *hpriv = link->ap->host->private_data;
Tejun Heo82ef04f2008-07-31 17:02:40 +0900931
Tejun Heoc7290722008-01-18 18:36:30 +0900932 if (reg >= ARRAY_SIZE(piix_sidx_map))
933 return -EINVAL;
934
Tejun Heobe77e432008-07-31 17:02:44 +0900935 piix_sidpr_sel(link, reg);
936 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
Tejun Heoc7290722008-01-18 18:36:30 +0900937 return 0;
938}
939
Tejun Heob8b275e2007-07-10 15:55:43 +0900940#ifdef CONFIG_PM
Tejun Heo8c3832e2007-07-27 14:53:28 +0900941static int piix_broken_suspend(void)
942{
Jeff Garzik18552562007-10-03 15:15:40 -0400943 static const struct dmi_system_id sysids[] = {
Tejun Heo8c3832e2007-07-27 14:53:28 +0900944 {
Tejun Heo4c74d4e2007-09-30 01:11:20 -0700945 .ident = "TECRA M3",
946 .matches = {
947 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
948 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
949 },
950 },
951 {
Peter Schwenke04d86d62007-11-30 15:28:29 +0900952 .ident = "TECRA M3",
953 .matches = {
954 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
955 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
956 },
957 },
958 {
Peter Schwenked1aa6902007-12-05 10:39:49 +0900959 .ident = "TECRA M4",
960 .matches = {
961 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
962 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
963 },
964 },
965 {
Tejun Heo040dee52008-06-13 18:05:02 +0900966 .ident = "TECRA M4",
967 .matches = {
968 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
969 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"),
970 },
971 },
972 {
Tejun Heo8c3832e2007-07-27 14:53:28 +0900973 .ident = "TECRA M5",
974 .matches = {
975 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
976 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
977 },
Tejun Heob8b275e2007-07-10 15:55:43 +0900978 },
Tejun Heo8c3832e2007-07-27 14:53:28 +0900979 {
Peter Schwenkeffe188d2008-01-17 23:08:55 +1000980 .ident = "TECRA M6",
981 .matches = {
982 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
983 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
984 },
985 },
986 {
Tejun Heo5c08ea02007-08-14 19:56:04 +0900987 .ident = "TECRA M7",
988 .matches = {
989 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
990 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
991 },
992 },
993 {
Peter Schwenke04d86d62007-11-30 15:28:29 +0900994 .ident = "TECRA A8",
995 .matches = {
996 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
997 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
998 },
999 },
1000 {
Peter Schwenkeffe188d2008-01-17 23:08:55 +10001001 .ident = "Satellite R20",
1002 .matches = {
1003 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1004 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
1005 },
1006 },
1007 {
Peter Schwenke04d86d62007-11-30 15:28:29 +09001008 .ident = "Satellite R25",
1009 .matches = {
1010 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1011 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
1012 },
1013 },
1014 {
Tejun Heo3cc0b9d2007-08-25 08:31:02 +09001015 .ident = "Satellite U200",
1016 .matches = {
1017 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1018 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
1019 },
1020 },
1021 {
Peter Schwenke04d86d62007-11-30 15:28:29 +09001022 .ident = "Satellite U200",
1023 .matches = {
1024 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1025 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
1026 },
1027 },
1028 {
Yann Chachkoff62320e22007-11-07 12:02:27 +09001029 .ident = "Satellite Pro U200",
1030 .matches = {
1031 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1032 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
1033 },
1034 },
1035 {
Tejun Heo8c3832e2007-07-27 14:53:28 +09001036 .ident = "Satellite U205",
1037 .matches = {
1038 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1039 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
1040 },
Tejun Heob8b275e2007-07-10 15:55:43 +09001041 },
Tejun Heo8c3832e2007-07-27 14:53:28 +09001042 {
Tejun Heode753e52007-11-12 17:56:24 +09001043 .ident = "SATELLITE U205",
1044 .matches = {
1045 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1046 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
1047 },
1048 },
1049 {
Tejun Heo8c3832e2007-07-27 14:53:28 +09001050 .ident = "Portege M500",
1051 .matches = {
1052 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1053 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
1054 },
Tejun Heob8b275e2007-07-10 15:55:43 +09001055 },
Jeff Garzik7d051542007-09-01 06:48:52 -04001056
1057 { } /* terminate list */
Tejun Heo8c3832e2007-07-27 14:53:28 +09001058 };
Tejun Heo7abe79c2007-07-27 14:55:07 +09001059 static const char *oemstrs[] = {
1060 "Tecra M3,",
1061 };
1062 int i;
Tejun Heo8c3832e2007-07-27 14:53:28 +09001063
1064 if (dmi_check_system(sysids))
1065 return 1;
1066
Tejun Heo7abe79c2007-07-27 14:55:07 +09001067 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
1068 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
1069 return 1;
1070
Tejun Heo1eedb4a2008-11-29 22:37:21 +09001071 /* TECRA M4 sometimes forgets its identify and reports bogus
1072 * DMI information. As the bogus information is a bit
1073 * generic, match as many entries as possible. This manual
1074 * matching is necessary because dmi_system_id.matches is
1075 * limited to four entries.
1076 */
Jiri Slaby3c387732008-12-10 14:07:22 +01001077 if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") &&
1078 dmi_match(DMI_PRODUCT_NAME, "000000") &&
1079 dmi_match(DMI_PRODUCT_VERSION, "000000") &&
1080 dmi_match(DMI_PRODUCT_SERIAL, "000000") &&
1081 dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") &&
1082 dmi_match(DMI_BOARD_NAME, "Portable PC") &&
1083 dmi_match(DMI_BOARD_VERSION, "Version A0"))
Tejun Heo1eedb4a2008-11-29 22:37:21 +09001084 return 1;
1085
Tejun Heo8c3832e2007-07-27 14:53:28 +09001086 return 0;
1087}
Tejun Heob8b275e2007-07-10 15:55:43 +09001088
1089static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1090{
1091 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1092 unsigned long flags;
1093 int rc = 0;
1094
1095 rc = ata_host_suspend(host, mesg);
1096 if (rc)
1097 return rc;
1098
1099 /* Some braindamaged ACPI suspend implementations expect the
1100 * controller to be awake on entry; otherwise, it burns cpu
1101 * cycles and power trying to do something to the sleeping
1102 * beauty.
1103 */
Rafael J. Wysocki3a2d5b72008-02-23 19:13:25 +01001104 if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) {
Tejun Heob8b275e2007-07-10 15:55:43 +09001105 pci_save_state(pdev);
1106
1107 /* mark its power state as "unknown", since we don't
1108 * know if e.g. the BIOS will change its device state
1109 * when we suspend.
1110 */
1111 if (pdev->current_state == PCI_D0)
1112 pdev->current_state = PCI_UNKNOWN;
1113
1114 /* tell resume that it's waking up from broken suspend */
1115 spin_lock_irqsave(&host->lock, flags);
1116 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1117 spin_unlock_irqrestore(&host->lock, flags);
1118 } else
1119 ata_pci_device_do_suspend(pdev, mesg);
1120
1121 return 0;
1122}
1123
1124static int piix_pci_device_resume(struct pci_dev *pdev)
1125{
1126 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1127 unsigned long flags;
1128 int rc;
1129
1130 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1131 spin_lock_irqsave(&host->lock, flags);
1132 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1133 spin_unlock_irqrestore(&host->lock, flags);
1134
1135 pci_set_power_state(pdev, PCI_D0);
1136 pci_restore_state(pdev);
1137
1138 /* PCI device wasn't disabled during suspend. Use
Tejun Heo0b62e132007-07-27 14:43:35 +09001139 * pci_reenable_device() to avoid affecting the enable
1140 * count.
Tejun Heob8b275e2007-07-10 15:55:43 +09001141 */
Tejun Heo0b62e132007-07-27 14:43:35 +09001142 rc = pci_reenable_device(pdev);
Tejun Heob8b275e2007-07-10 15:55:43 +09001143 if (rc)
1144 dev_printk(KERN_ERR, &pdev->dev, "failed to enable "
1145 "device after resume (%d)\n", rc);
1146 } else
1147 rc = ata_pci_device_do_resume(pdev);
1148
1149 if (rc == 0)
1150 ata_host_resume(host);
1151
1152 return rc;
1153}
1154#endif
1155
Tejun Heo25f98132008-01-07 19:38:53 +09001156static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1157{
1158 return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1159}
1160
Linus Torvalds1da177e2005-04-16 15:20:36 -07001161#define AHCI_PCI_BAR 5
1162#define AHCI_GLOBAL_CTL 0x04
1163#define AHCI_ENABLE (1 << 31)
1164static int piix_disable_ahci(struct pci_dev *pdev)
1165{
Jeff Garzikea6ba102005-08-30 05:18:18 -04001166 void __iomem *mmio;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001167 u32 tmp;
1168 int rc = 0;
1169
1170 /* BUG: pci_enable_device has not yet been called. This
1171 * works because this device is usually set up by BIOS.
1172 */
1173
Jeff Garzik374b1872005-08-30 05:42:52 -04001174 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1175 !pci_resource_len(pdev, AHCI_PCI_BAR))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001176 return 0;
Greg Felix7b6dbd62005-07-28 15:54:15 -04001177
Jeff Garzik374b1872005-08-30 05:42:52 -04001178 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001179 if (!mmio)
1180 return -ENOMEM;
Greg Felix7b6dbd62005-07-28 15:54:15 -04001181
Alan Coxc47a6312007-11-19 14:28:28 +00001182 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001183 if (tmp & AHCI_ENABLE) {
1184 tmp &= ~AHCI_ENABLE;
Alan Coxc47a6312007-11-19 14:28:28 +00001185 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001186
Alan Coxc47a6312007-11-19 14:28:28 +00001187 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001188 if (tmp & AHCI_ENABLE)
1189 rc = -EIO;
1190 }
Greg Felix7b6dbd62005-07-28 15:54:15 -04001191
Jeff Garzik374b1872005-08-30 05:42:52 -04001192 pci_iounmap(pdev, mmio);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001193 return rc;
1194}
1195
1196/**
Alan Coxc621b142005-12-08 19:22:28 +00001197 * piix_check_450nx_errata - Check for problem 450NX setup
Randy Dunlapc893a3a2006-01-28 13:15:32 -05001198 * @ata_dev: the PCI device to check
Jeff Garzik2e9edbf2006-03-24 09:56:57 -05001199 *
Alan Coxc621b142005-12-08 19:22:28 +00001200 * Check for the present of 450NX errata #19 and errata #25. If
1201 * they are found return an error code so we can turn off DMA
1202 */
1203
1204static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1205{
1206 struct pci_dev *pdev = NULL;
1207 u16 cfg;
Alan Coxc621b142005-12-08 19:22:28 +00001208 int no_piix_dma = 0;
Jeff Garzik2e9edbf2006-03-24 09:56:57 -05001209
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001210 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
Alan Coxc621b142005-12-08 19:22:28 +00001211 /* Look for 450NX PXB. Check for problem configurations
1212 A PCI quirk checks bit 6 already */
Alan Coxc621b142005-12-08 19:22:28 +00001213 pci_read_config_word(pdev, 0x41, &cfg);
1214 /* Only on the original revision: IDE DMA can hang */
Auke Kok44c10132007-06-08 15:46:36 -07001215 if (pdev->revision == 0x00)
Alan Coxc621b142005-12-08 19:22:28 +00001216 no_piix_dma = 1;
1217 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
Auke Kok44c10132007-06-08 15:46:36 -07001218 else if (cfg & (1<<14) && pdev->revision < 5)
Alan Coxc621b142005-12-08 19:22:28 +00001219 no_piix_dma = 2;
1220 }
Alan Cox31a34fe2006-05-22 22:58:14 +01001221 if (no_piix_dma)
Alan Coxc621b142005-12-08 19:22:28 +00001222 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
Alan Cox31a34fe2006-05-22 22:58:14 +01001223 if (no_piix_dma == 2)
Alan Coxc621b142005-12-08 19:22:28 +00001224 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
1225 return no_piix_dma;
Jeff Garzik2e9edbf2006-03-24 09:56:57 -05001226}
Alan Coxc621b142005-12-08 19:22:28 +00001227
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001228static void __devinit piix_init_pcs(struct ata_host *host,
Jeff Garzikea35d292006-07-11 11:48:50 -04001229 const struct piix_map_db *map_db)
1230{
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001231 struct pci_dev *pdev = to_pci_dev(host->dev);
Jeff Garzikea35d292006-07-11 11:48:50 -04001232 u16 pcs, new_pcs;
1233
1234 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1235
1236 new_pcs = pcs | map_db->port_enable;
1237
1238 if (new_pcs != pcs) {
1239 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1240 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1241 msleep(150);
1242 }
1243}
1244
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001245static const int *__devinit piix_init_sata_map(struct pci_dev *pdev,
1246 struct ata_port_info *pinfo,
1247 const struct piix_map_db *map_db)
Tejun Heod33f58b2006-03-01 01:25:39 +09001248{
Al Virob4482a42007-10-14 19:35:40 +01001249 const int *map;
Tejun Heod33f58b2006-03-01 01:25:39 +09001250 int i, invalid_map = 0;
1251 u8 map_value;
1252
1253 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1254
1255 map = map_db->map[map_value & map_db->mask];
1256
1257 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
1258 for (i = 0; i < 4; i++) {
1259 switch (map[i]) {
1260 case RV:
1261 invalid_map = 1;
1262 printk(" XX");
1263 break;
1264
1265 case NA:
1266 printk(" --");
1267 break;
1268
1269 case IDE:
1270 WARN_ON((i & 1) || map[i + 1] != IDE);
Jeff Garzik669a5db2006-08-29 18:12:40 -04001271 pinfo[i / 2] = piix_port_info[ich_pata_100];
Tejun Heod33f58b2006-03-01 01:25:39 +09001272 i++;
1273 printk(" IDE IDE");
1274 break;
1275
1276 default:
1277 printk(" P%d", map[i]);
1278 if (i & 1)
Jeff Garzikcca39742006-08-24 03:19:22 -04001279 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
Tejun Heod33f58b2006-03-01 01:25:39 +09001280 break;
1281 }
1282 }
1283 printk(" ]\n");
1284
1285 if (invalid_map)
1286 dev_printk(KERN_ERR, &pdev->dev,
1287 "invalid MAP value %u\n", map_value);
1288
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001289 return map;
Tejun Heod33f58b2006-03-01 01:25:39 +09001290}
1291
Tejun Heobe77e432008-07-31 17:02:44 +09001292static int __devinit piix_init_sidpr(struct ata_host *host)
Tejun Heoc7290722008-01-18 18:36:30 +09001293{
1294 struct pci_dev *pdev = to_pci_dev(host->dev);
1295 struct piix_host_priv *hpriv = host->private_data;
Tejun Heobe77e432008-07-31 17:02:44 +09001296 struct ata_link *link0 = &host->ports[0]->link;
Tejun Heocb6716c2008-05-01 10:03:08 +09001297 u32 scontrol;
Tejun Heobe77e432008-07-31 17:02:44 +09001298 int i, rc;
Tejun Heoc7290722008-01-18 18:36:30 +09001299
1300 /* check for availability */
1301 for (i = 0; i < 4; i++)
1302 if (hpriv->map[i] == IDE)
Tejun Heobe77e432008-07-31 17:02:44 +09001303 return 0;
Tejun Heoc7290722008-01-18 18:36:30 +09001304
1305 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
Tejun Heobe77e432008-07-31 17:02:44 +09001306 return 0;
Tejun Heoc7290722008-01-18 18:36:30 +09001307
1308 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
1309 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
Tejun Heobe77e432008-07-31 17:02:44 +09001310 return 0;
Tejun Heoc7290722008-01-18 18:36:30 +09001311
1312 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
Tejun Heobe77e432008-07-31 17:02:44 +09001313 return 0;
Tejun Heoc7290722008-01-18 18:36:30 +09001314
1315 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
Tejun Heocb6716c2008-05-01 10:03:08 +09001316
1317 /* SCR access via SIDPR doesn't work on some configurations.
1318 * Give it a test drive by inhibiting power save modes which
1319 * we'll do anyway.
1320 */
Tejun Heobe77e432008-07-31 17:02:44 +09001321 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
Tejun Heocb6716c2008-05-01 10:03:08 +09001322
1323 /* if IPM is already 3, SCR access is probably working. Don't
1324 * un-inhibit power save modes as BIOS might have inhibited
1325 * them for a reason.
1326 */
1327 if ((scontrol & 0xf00) != 0x300) {
1328 scontrol |= 0x300;
Tejun Heobe77e432008-07-31 17:02:44 +09001329 piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol);
1330 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
Tejun Heocb6716c2008-05-01 10:03:08 +09001331
1332 if ((scontrol & 0xf00) != 0x300) {
1333 dev_printk(KERN_INFO, host->dev, "SCR access via "
1334 "SIDPR is available but doesn't work\n");
Tejun Heobe77e432008-07-31 17:02:44 +09001335 return 0;
Tejun Heocb6716c2008-05-01 10:03:08 +09001336 }
1337 }
1338
Tejun Heobe77e432008-07-31 17:02:44 +09001339 /* okay, SCRs available, set ops and ask libata for slave_link */
1340 for (i = 0; i < 2; i++) {
1341 struct ata_port *ap = host->ports[i];
1342
1343 ap->ops = &piix_sidpr_sata_ops;
1344
1345 if (ap->flags & ATA_FLAG_SLAVE_POSS) {
1346 rc = ata_slave_link_init(ap);
1347 if (rc)
1348 return rc;
1349 }
1350 }
1351
1352 return 0;
Tejun Heoc7290722008-01-18 18:36:30 +09001353}
1354
Tejun Heo2852bcf2009-01-02 12:04:48 +09001355static void piix_iocfg_bit18_quirk(struct ata_host *host)
Tejun Heo43a98f02007-08-23 10:15:18 +09001356{
Jeff Garzik18552562007-10-03 15:15:40 -04001357 static const struct dmi_system_id sysids[] = {
Tejun Heo43a98f02007-08-23 10:15:18 +09001358 {
1359 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1360 * isn't used to boot the system which
1361 * disables the channel.
1362 */
1363 .ident = "M570U",
1364 .matches = {
1365 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1366 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1367 },
1368 },
Jeff Garzik7d051542007-09-01 06:48:52 -04001369
1370 { } /* terminate list */
Tejun Heo43a98f02007-08-23 10:15:18 +09001371 };
Tejun Heo2852bcf2009-01-02 12:04:48 +09001372 struct pci_dev *pdev = to_pci_dev(host->dev);
1373 struct piix_host_priv *hpriv = host->private_data;
Tejun Heo43a98f02007-08-23 10:15:18 +09001374
1375 if (!dmi_check_system(sysids))
1376 return;
1377
1378 /* The datasheet says that bit 18 is NOOP but certain systems
1379 * seem to use it to disable a channel. Clear the bit on the
1380 * affected systems.
1381 */
Tejun Heo2852bcf2009-01-02 12:04:48 +09001382 if (hpriv->saved_iocfg & (1 << 18)) {
Tejun Heo43a98f02007-08-23 10:15:18 +09001383 dev_printk(KERN_INFO, &pdev->dev,
1384 "applying IOCFG bit18 quirk\n");
Tejun Heo2852bcf2009-01-02 12:04:48 +09001385 pci_write_config_dword(pdev, PIIX_IOCFG,
1386 hpriv->saved_iocfg & ~(1 << 18));
Tejun Heo43a98f02007-08-23 10:15:18 +09001387 }
1388}
1389
Alan Coxc621b142005-12-08 19:22:28 +00001390/**
Linus Torvalds1da177e2005-04-16 15:20:36 -07001391 * piix_init_one - Register PIIX ATA PCI device with kernel services
1392 * @pdev: PCI device to register
1393 * @ent: Entry in piix_pci_tbl matching with @pdev
1394 *
1395 * Called from kernel PCI layer. We probe for combined mode (sigh),
1396 * and then hand over control to libata, for it to do the rest.
1397 *
1398 * LOCKING:
1399 * Inherited from PCI layer (may sleep).
1400 *
1401 * RETURNS:
1402 * Zero on success, or -ERRNO value.
1403 */
1404
Adrian Bunkbc5468f2008-01-30 22:02:02 +02001405static int __devinit piix_init_one(struct pci_dev *pdev,
1406 const struct pci_device_id *ent)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001407{
1408 static int printed_version;
Tejun Heo24dc5f32007-01-20 16:00:28 +09001409 struct device *dev = &pdev->dev;
Tejun Heod33f58b2006-03-01 01:25:39 +09001410 struct ata_port_info port_info[2];
Tejun Heo1626aeb2007-05-04 12:43:58 +02001411 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
Jeff Garzikcca39742006-08-24 03:19:22 -04001412 unsigned long port_flags;
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001413 struct ata_host *host;
1414 struct piix_host_priv *hpriv;
1415 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001416
1417 if (!printed_version++)
Jeff Garzik6248e642005-10-30 06:42:18 -05001418 dev_printk(KERN_DEBUG, &pdev->dev,
1419 "version " DRV_VERSION "\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001420
1421 /* no hotplugging support (FIXME) */
1422 if (!in_module_init)
1423 return -ENODEV;
1424
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001425 port_info[0] = piix_port_info[ent->driver_data];
1426 port_info[1] = piix_port_info[ent->driver_data];
1427
1428 port_flags = port_info[0].flags;
1429
1430 /* enable device and prepare host */
1431 rc = pcim_enable_device(pdev);
1432 if (rc)
1433 return rc;
1434
Tejun Heo2852bcf2009-01-02 12:04:48 +09001435 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1436 if (!hpriv)
1437 return -ENOMEM;
1438
1439 /* Save IOCFG, this will be used for cable detection, quirk
1440 * detection and restoration on detach. This is necessary
1441 * because some ACPI implementations mess up cable related
1442 * bits on _STM. Reported on kernel bz#11879.
1443 */
1444 pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg);
1445
Tejun Heo5016d7d2008-03-26 15:46:58 +09001446 /* ICH6R may be driven by either ata_piix or ahci driver
1447 * regardless of BIOS configuration. Make sure AHCI mode is
1448 * off.
1449 */
1450 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) {
Stephen Hemmingerda3ceb22008-09-08 09:31:39 -07001451 rc = piix_disable_ahci(pdev);
Tejun Heo5016d7d2008-03-26 15:46:58 +09001452 if (rc)
1453 return rc;
1454 }
1455
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001456 /* SATA map init can change port_info, do it before prepping host */
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001457 if (port_flags & ATA_FLAG_SATA)
1458 hpriv->map = piix_init_sata_map(pdev, port_info,
1459 piix_map_db_table[ent->driver_data]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001460
Tejun Heo9363c382008-04-07 22:47:16 +09001461 rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001462 if (rc)
1463 return rc;
1464 host->private_data = hpriv;
Tejun Heoff0fc142005-12-18 17:17:07 +09001465
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001466 /* initialize controller */
Tejun Heoc7290722008-01-18 18:36:30 +09001467 if (port_flags & ATA_FLAG_SATA) {
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001468 piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
Tejun Heobe77e432008-07-31 17:02:44 +09001469 rc = piix_init_sidpr(host);
1470 if (rc)
1471 return rc;
Tejun Heoc7290722008-01-18 18:36:30 +09001472 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001473
Tejun Heo43a98f02007-08-23 10:15:18 +09001474 /* apply IOCFG bit18 quirk */
Tejun Heo2852bcf2009-01-02 12:04:48 +09001475 piix_iocfg_bit18_quirk(host);
Tejun Heo43a98f02007-08-23 10:15:18 +09001476
Linus Torvalds1da177e2005-04-16 15:20:36 -07001477 /* On ICH5, some BIOSen disable the interrupt using the
1478 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1479 * On ICH6, this bit has the same effect, but only when
1480 * MSI is disabled (and it is disabled, as we don't use
1481 * message-signalled interrupts currently).
1482 */
Jeff Garzikcca39742006-08-24 03:19:22 -04001483 if (port_flags & PIIX_FLAG_CHECKINTR)
Brett M Russa04ce0f2005-08-15 15:23:41 -04001484 pci_intx(pdev, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001485
Alan Coxc621b142005-12-08 19:22:28 +00001486 if (piix_check_450nx_errata(pdev)) {
1487 /* This writes into the master table but it does not
1488 really matter for this errata as we will apply it to
1489 all the PIIX devices on the board */
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001490 host->ports[0]->mwdma_mask = 0;
1491 host->ports[0]->udma_mask = 0;
1492 host->ports[1]->mwdma_mask = 0;
1493 host->ports[1]->udma_mask = 0;
Alan Coxc621b142005-12-08 19:22:28 +00001494 }
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001495
1496 pci_set_master(pdev);
Tejun Heo9363c382008-04-07 22:47:16 +09001497 return ata_pci_sff_activate_host(host, ata_sff_interrupt, &piix_sht);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001498}
1499
Tejun Heo2852bcf2009-01-02 12:04:48 +09001500static void piix_remove_one(struct pci_dev *pdev)
1501{
1502 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1503 struct piix_host_priv *hpriv = host->private_data;
1504
1505 pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg);
1506
1507 ata_pci_remove_one(pdev);
1508}
1509
Linus Torvalds1da177e2005-04-16 15:20:36 -07001510static int __init piix_init(void)
1511{
1512 int rc;
1513
Pavel Roskinb7887192006-08-10 18:13:18 +09001514 DPRINTK("pci_register_driver\n");
1515 rc = pci_register_driver(&piix_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001516 if (rc)
1517 return rc;
1518
1519 in_module_init = 0;
1520
1521 DPRINTK("done\n");
1522 return 0;
1523}
1524
Linus Torvalds1da177e2005-04-16 15:20:36 -07001525static void __exit piix_exit(void)
1526{
1527 pci_unregister_driver(&piix_pci_driver);
1528}
1529
1530module_init(piix_init);
1531module_exit(piix_exit);