Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * PCI handling of I2O controller |
| 3 | * |
| 4 | * Copyright (C) 1999-2002 Red Hat Software |
| 5 | * |
| 6 | * Written by Alan Cox, Building Number Three Ltd |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify it |
| 9 | * under the terms of the GNU General Public License as published by the |
| 10 | * Free Software Foundation; either version 2 of the License, or (at your |
| 11 | * option) any later version. |
| 12 | * |
| 13 | * A lot of the I2O message side code from this is taken from the Red |
| 14 | * Creek RCPCI45 adapter driver by Red Creek Communications |
| 15 | * |
| 16 | * Fixes/additions: |
| 17 | * Philipp Rumpf |
| 18 | * Juha Sievänen <Juha.Sievanen@cs.Helsinki.FI> |
| 19 | * Auvo Häkkinen <Auvo.Hakkinen@cs.Helsinki.FI> |
| 20 | * Deepak Saxena <deepak@plexity.net> |
| 21 | * Boji T Kannanthanam <boji.t.kannanthanam@intel.com> |
| 22 | * Alan Cox <alan@redhat.com>: |
| 23 | * Ported to Linux 2.5. |
| 24 | * Markus Lidel <Markus.Lidel@shadowconnect.com>: |
| 25 | * Minor fixes for 2.6. |
| 26 | * Markus Lidel <Markus.Lidel@shadowconnect.com>: |
| 27 | * Support for sysfs included. |
| 28 | */ |
| 29 | |
| 30 | #include <linux/pci.h> |
| 31 | #include <linux/interrupt.h> |
| 32 | #include <linux/i2o.h> |
| 33 | |
| 34 | #ifdef CONFIG_MTRR |
| 35 | #include <asm/mtrr.h> |
| 36 | #endif // CONFIG_MTRR |
| 37 | |
| 38 | /* Module internal functions from other sources */ |
| 39 | extern struct i2o_controller *i2o_iop_alloc(void); |
| 40 | extern void i2o_iop_free(struct i2o_controller *); |
| 41 | |
| 42 | extern int i2o_iop_add(struct i2o_controller *); |
| 43 | extern void i2o_iop_remove(struct i2o_controller *); |
| 44 | |
| 45 | extern int i2o_driver_dispatch(struct i2o_controller *, u32, |
| 46 | struct i2o_message *); |
| 47 | |
| 48 | /* PCI device id table for all I2O controllers */ |
| 49 | static struct pci_device_id __devinitdata i2o_pci_ids[] = { |
| 50 | {PCI_DEVICE_CLASS(PCI_CLASS_INTELLIGENT_I2O << 8, 0xffff00)}, |
| 51 | {PCI_DEVICE(PCI_VENDOR_ID_DPT, 0xa511)}, |
| 52 | {0} |
| 53 | }; |
| 54 | |
| 55 | /** |
| 56 | * i2o_dma_realloc - Realloc DMA memory |
| 57 | * @dev: struct device pointer to the PCI device of the I2O controller |
| 58 | * @addr: pointer to a i2o_dma struct DMA buffer |
| 59 | * @len: new length of memory |
| 60 | * @gfp_mask: GFP mask |
| 61 | * |
| 62 | * If there was something allocated in the addr, free it first. If len > 0 |
| 63 | * than try to allocate it and write the addresses back to the addr |
| 64 | * structure. If len == 0 set the virtual address to NULL. |
| 65 | * |
| 66 | * Returns the 0 on success or negative error code on failure. |
| 67 | */ |
| 68 | int i2o_dma_realloc(struct device *dev, struct i2o_dma *addr, size_t len, |
| 69 | unsigned int gfp_mask) |
| 70 | { |
| 71 | i2o_dma_free(dev, addr); |
| 72 | |
| 73 | if (len) |
| 74 | return i2o_dma_alloc(dev, addr, len, gfp_mask); |
| 75 | |
| 76 | return 0; |
| 77 | }; |
| 78 | |
| 79 | /** |
| 80 | * i2o_pci_free - Frees the DMA memory for the I2O controller |
| 81 | * @c: I2O controller to free |
| 82 | * |
| 83 | * Remove all allocated DMA memory and unmap memory IO regions. If MTRR |
| 84 | * is enabled, also remove it again. |
| 85 | */ |
| 86 | static void i2o_pci_free(struct i2o_controller *c) |
| 87 | { |
| 88 | struct device *dev; |
| 89 | |
| 90 | dev = &c->pdev->dev; |
| 91 | |
| 92 | i2o_dma_free(dev, &c->out_queue); |
| 93 | i2o_dma_free(dev, &c->status_block); |
| 94 | if (c->lct) |
| 95 | kfree(c->lct); |
| 96 | i2o_dma_free(dev, &c->dlct); |
| 97 | i2o_dma_free(dev, &c->hrt); |
| 98 | i2o_dma_free(dev, &c->status); |
| 99 | |
| 100 | #ifdef CONFIG_MTRR |
| 101 | if (c->mtrr_reg0 >= 0) |
| 102 | mtrr_del(c->mtrr_reg0, 0, 0); |
| 103 | if (c->mtrr_reg1 >= 0) |
| 104 | mtrr_del(c->mtrr_reg1, 0, 0); |
| 105 | #endif |
| 106 | |
| 107 | if (c->raptor && c->in_queue.virt) |
| 108 | iounmap(c->in_queue.virt); |
| 109 | |
| 110 | if (c->base.virt) |
| 111 | iounmap(c->base.virt); |
| 112 | } |
| 113 | |
| 114 | /** |
| 115 | * i2o_pci_alloc - Allocate DMA memory, map IO memory for I2O controller |
| 116 | * @c: I2O controller |
| 117 | * |
| 118 | * Allocate DMA memory for a PCI (or in theory AGP) I2O controller. All |
| 119 | * IO mappings are also done here. If MTRR is enabled, also do add memory |
| 120 | * regions here. |
| 121 | * |
| 122 | * Returns 0 on success or negative error code on failure. |
| 123 | */ |
| 124 | static int __devinit i2o_pci_alloc(struct i2o_controller *c) |
| 125 | { |
| 126 | struct pci_dev *pdev = c->pdev; |
| 127 | struct device *dev = &pdev->dev; |
| 128 | int i; |
| 129 | |
| 130 | for (i = 0; i < 6; i++) { |
| 131 | /* Skip I/O spaces */ |
| 132 | if (!(pci_resource_flags(pdev, i) & IORESOURCE_IO)) { |
| 133 | if (!c->base.phys) { |
| 134 | c->base.phys = pci_resource_start(pdev, i); |
| 135 | c->base.len = pci_resource_len(pdev, i); |
| 136 | |
| 137 | /* |
| 138 | * If we know what card it is, set the size |
| 139 | * correctly. Code is taken from dpt_i2o.c |
| 140 | */ |
| 141 | if (pdev->device == 0xa501) { |
| 142 | if (pdev->subsystem_device >= 0xc032 && |
| 143 | pdev->subsystem_device <= 0xc03b) { |
| 144 | if (c->base.len > 0x400000) |
| 145 | c->base.len = 0x400000; |
| 146 | } else { |
| 147 | if (c->base.len > 0x100000) |
| 148 | c->base.len = 0x100000; |
| 149 | } |
| 150 | } |
| 151 | if (!c->raptor) |
| 152 | break; |
| 153 | } else { |
| 154 | c->in_queue.phys = pci_resource_start(pdev, i); |
| 155 | c->in_queue.len = pci_resource_len(pdev, i); |
| 156 | break; |
| 157 | } |
| 158 | } |
| 159 | } |
| 160 | |
| 161 | if (i == 6) { |
| 162 | printk(KERN_ERR "%s: I2O controller has no memory regions" |
| 163 | " defined.\n", c->name); |
| 164 | i2o_pci_free(c); |
| 165 | return -EINVAL; |
| 166 | } |
| 167 | |
| 168 | /* Map the I2O controller */ |
| 169 | if (c->raptor) { |
| 170 | printk(KERN_INFO "%s: PCI I2O controller\n", c->name); |
| 171 | printk(KERN_INFO " BAR0 at 0x%08lX size=%ld\n", |
| 172 | (unsigned long)c->base.phys, (unsigned long)c->base.len); |
| 173 | printk(KERN_INFO " BAR1 at 0x%08lX size=%ld\n", |
| 174 | (unsigned long)c->in_queue.phys, |
| 175 | (unsigned long)c->in_queue.len); |
| 176 | } else |
| 177 | printk(KERN_INFO "%s: PCI I2O controller at %08lX size=%ld\n", |
| 178 | c->name, (unsigned long)c->base.phys, |
| 179 | (unsigned long)c->base.len); |
| 180 | |
| 181 | c->base.virt = ioremap(c->base.phys, c->base.len); |
| 182 | if (!c->base.virt) { |
| 183 | printk(KERN_ERR "%s: Unable to map controller.\n", c->name); |
| 184 | return -ENOMEM; |
| 185 | } |
| 186 | |
| 187 | if (c->raptor) { |
| 188 | c->in_queue.virt = ioremap(c->in_queue.phys, c->in_queue.len); |
| 189 | if (!c->in_queue.virt) { |
| 190 | printk(KERN_ERR "%s: Unable to map controller.\n", |
| 191 | c->name); |
| 192 | i2o_pci_free(c); |
| 193 | return -ENOMEM; |
| 194 | } |
| 195 | } else |
| 196 | c->in_queue = c->base; |
| 197 | |
| 198 | c->irq_mask = c->base.virt + 0x34; |
| 199 | c->post_port = c->base.virt + 0x40; |
| 200 | c->reply_port = c->base.virt + 0x44; |
| 201 | |
| 202 | #ifdef CONFIG_MTRR |
| 203 | /* Enable Write Combining MTRR for IOP's memory region */ |
| 204 | c->mtrr_reg0 = mtrr_add(c->in_queue.phys, c->in_queue.len, |
| 205 | MTRR_TYPE_WRCOMB, 1); |
| 206 | c->mtrr_reg1 = -1; |
| 207 | |
| 208 | if (c->mtrr_reg0 < 0) |
| 209 | printk(KERN_WARNING "%s: could not enable write combining " |
| 210 | "MTRR\n", c->name); |
| 211 | else |
| 212 | printk(KERN_INFO "%s: using write combining MTRR\n", c->name); |
| 213 | |
| 214 | /* |
| 215 | * If it is an INTEL i960 I/O processor then set the first 64K to |
| 216 | * Uncacheable since the region contains the messaging unit which |
| 217 | * shouldn't be cached. |
| 218 | */ |
| 219 | if ((pdev->vendor == PCI_VENDOR_ID_INTEL || |
| 220 | pdev->vendor == PCI_VENDOR_ID_DPT) && !c->raptor) { |
| 221 | printk(KERN_INFO "%s: MTRR workaround for Intel i960 processor" |
| 222 | "\n", c->name); |
| 223 | c->mtrr_reg1 = mtrr_add(c->base.phys, 0x10000, |
| 224 | MTRR_TYPE_UNCACHABLE, 1); |
| 225 | |
| 226 | if (c->mtrr_reg1 < 0) { |
| 227 | printk(KERN_WARNING "%s: Error in setting " |
| 228 | "MTRR_TYPE_UNCACHABLE\n", c->name); |
| 229 | mtrr_del(c->mtrr_reg0, c->in_queue.phys, |
| 230 | c->in_queue.len); |
| 231 | c->mtrr_reg0 = -1; |
| 232 | } |
| 233 | } |
| 234 | #endif |
| 235 | |
| 236 | if (i2o_dma_alloc(dev, &c->status, 8, GFP_KERNEL)) { |
| 237 | i2o_pci_free(c); |
| 238 | return -ENOMEM; |
| 239 | } |
| 240 | |
| 241 | if (i2o_dma_alloc(dev, &c->hrt, sizeof(i2o_hrt), GFP_KERNEL)) { |
| 242 | i2o_pci_free(c); |
| 243 | return -ENOMEM; |
| 244 | } |
| 245 | |
| 246 | if (i2o_dma_alloc(dev, &c->dlct, 8192, GFP_KERNEL)) { |
| 247 | i2o_pci_free(c); |
| 248 | return -ENOMEM; |
| 249 | } |
| 250 | |
| 251 | if (i2o_dma_alloc(dev, &c->status_block, sizeof(i2o_status_block), |
| 252 | GFP_KERNEL)) { |
| 253 | i2o_pci_free(c); |
| 254 | return -ENOMEM; |
| 255 | } |
| 256 | |
| 257 | if (i2o_dma_alloc(dev, &c->out_queue, MSG_POOL_SIZE, GFP_KERNEL)) { |
| 258 | i2o_pci_free(c); |
| 259 | return -ENOMEM; |
| 260 | } |
| 261 | |
| 262 | pci_set_drvdata(pdev, c); |
| 263 | |
| 264 | return 0; |
| 265 | } |
| 266 | |
| 267 | /** |
| 268 | * i2o_pci_interrupt - Interrupt handler for I2O controller |
| 269 | * @irq: interrupt line |
| 270 | * @dev_id: pointer to the I2O controller |
| 271 | * @r: pointer to registers |
| 272 | * |
| 273 | * Handle an interrupt from a PCI based I2O controller. This turns out |
| 274 | * to be rather simple. We keep the controller pointer in the cookie. |
| 275 | */ |
| 276 | static irqreturn_t i2o_pci_interrupt(int irq, void *dev_id, struct pt_regs *r) |
| 277 | { |
| 278 | struct i2o_controller *c = dev_id; |
| 279 | struct device *dev = &c->pdev->dev; |
| 280 | struct i2o_message *m; |
| 281 | u32 mv; |
| 282 | |
| 283 | /* |
| 284 | * Old 960 steppings had a bug in the I2O unit that caused |
| 285 | * the queue to appear empty when it wasn't. |
| 286 | */ |
| 287 | mv = I2O_REPLY_READ32(c); |
| 288 | if (mv == I2O_QUEUE_EMPTY) { |
| 289 | mv = I2O_REPLY_READ32(c); |
| 290 | if (unlikely(mv == I2O_QUEUE_EMPTY)) { |
| 291 | return IRQ_NONE; |
| 292 | } else |
| 293 | pr_debug("%s: 960 bug detected\n", c->name); |
| 294 | } |
| 295 | |
| 296 | while (mv != I2O_QUEUE_EMPTY) { |
| 297 | /* |
| 298 | * Map the message from the page frame map to kernel virtual. |
| 299 | * Because bus_to_virt is deprecated, we have calculate the |
| 300 | * location by ourself! |
| 301 | */ |
| 302 | m = i2o_msg_out_to_virt(c, mv); |
| 303 | |
| 304 | /* |
| 305 | * Ensure this message is seen coherently but cachably by |
| 306 | * the processor |
| 307 | */ |
| 308 | dma_sync_single_for_cpu(dev, mv, MSG_FRAME_SIZE * 4, |
| 309 | PCI_DMA_FROMDEVICE); |
| 310 | |
| 311 | /* dispatch it */ |
| 312 | if (i2o_driver_dispatch(c, mv, m)) |
| 313 | /* flush it if result != 0 */ |
| 314 | i2o_flush_reply(c, mv); |
| 315 | |
| 316 | /* |
| 317 | * That 960 bug again... |
| 318 | */ |
| 319 | mv = I2O_REPLY_READ32(c); |
| 320 | if (mv == I2O_QUEUE_EMPTY) |
| 321 | mv = I2O_REPLY_READ32(c); |
| 322 | } |
| 323 | return IRQ_HANDLED; |
| 324 | } |
| 325 | |
| 326 | /** |
| 327 | * i2o_pci_irq_enable - Allocate interrupt for I2O controller |
| 328 | * |
| 329 | * Allocate an interrupt for the I2O controller, and activate interrupts |
| 330 | * on the I2O controller. |
| 331 | * |
| 332 | * Returns 0 on success or negative error code on failure. |
| 333 | */ |
| 334 | static int i2o_pci_irq_enable(struct i2o_controller *c) |
| 335 | { |
| 336 | struct pci_dev *pdev = c->pdev; |
| 337 | int rc; |
| 338 | |
| 339 | I2O_IRQ_WRITE32(c, 0xffffffff); |
| 340 | |
| 341 | if (pdev->irq) { |
| 342 | rc = request_irq(pdev->irq, i2o_pci_interrupt, SA_SHIRQ, |
| 343 | c->name, c); |
| 344 | if (rc < 0) { |
| 345 | printk(KERN_ERR "%s: unable to allocate interrupt %d." |
| 346 | "\n", c->name, pdev->irq); |
| 347 | return rc; |
| 348 | } |
| 349 | } |
| 350 | |
| 351 | I2O_IRQ_WRITE32(c, 0x00000000); |
| 352 | |
| 353 | printk(KERN_INFO "%s: Installed at IRQ %d\n", c->name, pdev->irq); |
| 354 | |
| 355 | return 0; |
| 356 | } |
| 357 | |
| 358 | /** |
| 359 | * i2o_pci_irq_disable - Free interrupt for I2O controller |
| 360 | * @c: I2O controller |
| 361 | * |
| 362 | * Disable interrupts in I2O controller and then free interrupt. |
| 363 | */ |
| 364 | static void i2o_pci_irq_disable(struct i2o_controller *c) |
| 365 | { |
| 366 | I2O_IRQ_WRITE32(c, 0xffffffff); |
| 367 | |
| 368 | if (c->pdev->irq > 0) |
| 369 | free_irq(c->pdev->irq, c); |
| 370 | } |
| 371 | |
| 372 | /** |
| 373 | * i2o_pci_probe - Probe the PCI device for an I2O controller |
| 374 | * @dev: PCI device to test |
| 375 | * @id: id which matched with the PCI device id table |
| 376 | * |
| 377 | * Probe the PCI device for any device which is a memory of the |
| 378 | * Intelligent, I2O class or an Adaptec Zero Channel Controller. We |
| 379 | * attempt to set up each such device and register it with the core. |
| 380 | * |
| 381 | * Returns 0 on success or negative error code on failure. |
| 382 | */ |
| 383 | static int __devinit i2o_pci_probe(struct pci_dev *pdev, |
| 384 | const struct pci_device_id *id) |
| 385 | { |
| 386 | struct i2o_controller *c; |
| 387 | int rc; |
| 388 | |
| 389 | printk(KERN_INFO "i2o: Checking for PCI I2O controllers...\n"); |
| 390 | |
| 391 | if ((pdev->class & 0xff) > 1) { |
| 392 | printk(KERN_WARNING "i2o: I2O controller found but does not " |
| 393 | "support I2O 1.5 (skipping).\n"); |
| 394 | return -ENODEV; |
| 395 | } |
| 396 | |
| 397 | if ((rc = pci_enable_device(pdev))) { |
| 398 | printk(KERN_WARNING "i2o: I2O controller found but could not be" |
| 399 | " enabled.\n"); |
| 400 | return rc; |
| 401 | } |
| 402 | |
| 403 | printk(KERN_INFO "i2o: I2O controller found on bus %d at %d.\n", |
| 404 | pdev->bus->number, pdev->devfn); |
| 405 | |
| 406 | if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) { |
| 407 | printk(KERN_WARNING "i2o: I2O controller on bus %d at %d: No " |
| 408 | "suitable DMA available!\n", pdev->bus->number, |
| 409 | pdev->devfn); |
| 410 | rc = -ENODEV; |
| 411 | goto disable; |
| 412 | } |
| 413 | |
| 414 | pci_set_master(pdev); |
| 415 | |
| 416 | c = i2o_iop_alloc(); |
| 417 | if (IS_ERR(c)) { |
| 418 | printk(KERN_ERR "i2o: memory for I2O controller could not be " |
| 419 | "allocated\n"); |
| 420 | rc = PTR_ERR(c); |
| 421 | goto disable; |
| 422 | } |
| 423 | |
| 424 | c->pdev = pdev; |
| 425 | c->device = pdev->dev; |
| 426 | |
| 427 | /* Cards that fall apart if you hit them with large I/O loads... */ |
| 428 | if (pdev->vendor == PCI_VENDOR_ID_NCR && pdev->device == 0x0630) { |
| 429 | c->short_req = 1; |
| 430 | printk(KERN_INFO "%s: Symbios FC920 workarounds activated.\n", |
| 431 | c->name); |
| 432 | } |
| 433 | |
| 434 | if (pdev->subsystem_vendor == PCI_VENDOR_ID_PROMISE) { |
| 435 | c->promise = 1; |
| 436 | printk(KERN_INFO "%s: Promise workarounds activated.\n", |
| 437 | c->name); |
| 438 | } |
| 439 | |
| 440 | /* Cards that go bananas if you quiesce them before you reset them. */ |
| 441 | if (pdev->vendor == PCI_VENDOR_ID_DPT) { |
| 442 | c->no_quiesce = 1; |
| 443 | if (pdev->device == 0xa511) |
| 444 | c->raptor = 1; |
| 445 | } |
| 446 | |
| 447 | if ((rc = i2o_pci_alloc(c))) { |
| 448 | printk(KERN_ERR "%s: DMA / IO allocation for I2O controller " |
| 449 | " failed\n", c->name); |
| 450 | goto free_controller; |
| 451 | } |
| 452 | |
| 453 | if (i2o_pci_irq_enable(c)) { |
| 454 | printk(KERN_ERR "%s: unable to enable interrupts for I2O " |
| 455 | "controller\n", c->name); |
| 456 | goto free_pci; |
| 457 | } |
| 458 | |
| 459 | if ((rc = i2o_iop_add(c))) |
| 460 | goto uninstall; |
| 461 | |
| 462 | return 0; |
| 463 | |
| 464 | uninstall: |
| 465 | i2o_pci_irq_disable(c); |
| 466 | |
| 467 | free_pci: |
| 468 | i2o_pci_free(c); |
| 469 | |
| 470 | free_controller: |
| 471 | i2o_iop_free(c); |
| 472 | |
| 473 | disable: |
| 474 | pci_disable_device(pdev); |
| 475 | |
| 476 | return rc; |
| 477 | } |
| 478 | |
| 479 | /** |
| 480 | * i2o_pci_remove - Removes a I2O controller from the system |
| 481 | * pdev: I2O controller which should be removed |
| 482 | * |
| 483 | * Reset the I2O controller, disable interrupts and remove all allocated |
| 484 | * resources. |
| 485 | */ |
| 486 | static void __devexit i2o_pci_remove(struct pci_dev *pdev) |
| 487 | { |
| 488 | struct i2o_controller *c; |
| 489 | c = pci_get_drvdata(pdev); |
| 490 | |
| 491 | i2o_iop_remove(c); |
| 492 | i2o_pci_irq_disable(c); |
| 493 | i2o_pci_free(c); |
| 494 | |
| 495 | printk(KERN_INFO "%s: Controller removed.\n", c->name); |
| 496 | |
| 497 | i2o_iop_free(c); |
| 498 | pci_disable_device(pdev); |
| 499 | }; |
| 500 | |
| 501 | /* PCI driver for I2O controller */ |
| 502 | static struct pci_driver i2o_pci_driver = { |
| 503 | .name = "I2O controller", |
| 504 | .id_table = i2o_pci_ids, |
| 505 | .probe = i2o_pci_probe, |
| 506 | .remove = __devexit_p(i2o_pci_remove), |
| 507 | }; |
| 508 | |
| 509 | /** |
| 510 | * i2o_pci_init - registers I2O PCI driver in PCI subsystem |
| 511 | * |
| 512 | * Returns > 0 on success or negative error code on failure. |
| 513 | */ |
| 514 | int __init i2o_pci_init(void) |
| 515 | { |
| 516 | return pci_register_driver(&i2o_pci_driver); |
| 517 | }; |
| 518 | |
| 519 | /** |
| 520 | * i2o_pci_exit - unregisters I2O PCI driver from PCI subsystem |
| 521 | */ |
| 522 | void __exit i2o_pci_exit(void) |
| 523 | { |
| 524 | pci_unregister_driver(&i2o_pci_driver); |
| 525 | }; |
| 526 | |
| 527 | EXPORT_SYMBOL(i2o_dma_realloc); |
| 528 | MODULE_DEVICE_TABLE(pci, i2o_pci_ids); |