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gerrit-public.fairphone.software / fp2-dev / kernel / msm / 36e2bdcdf3e325449daa899c08aab3511923415d / . / arch / arm / mach-msm / clock-pcom-lookup.c
blob: 06bb542293a3dd33f92931b90d85687804353dd1 [file] [log] [blame]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include "clock.h"
14#include "clock-pcom.h"
15#include "clock-voter.h"
16
17static DEFINE_CLK_PCOM(adm_clk, ADM_CLK, CLKFLAG_SKIP_AUTO_OFF);
18static DEFINE_CLK_PCOM(adsp_clk, ADSP_CLK, CLKFLAG_SKIP_AUTO_OFF);
19static DEFINE_CLK_PCOM(ahb_m_clk, AHB_M_CLK, CLKFLAG_SKIP_AUTO_OFF);
20static DEFINE_CLK_PCOM(ahb_s_clk, AHB_S_CLK, CLKFLAG_SKIP_AUTO_OFF);
21static DEFINE_CLK_PCOM(cam_m_clk, CAM_M_CLK, CLKFLAG_SKIP_AUTO_OFF);
22static DEFINE_CLK_PCOM(axi_rotator_clk, AXI_ROTATOR_CLK, 0);
23static DEFINE_CLK_PCOM(ce_clk, CE_CLK, CLKFLAG_SKIP_AUTO_OFF);
24static DEFINE_CLK_PCOM(csi0_clk, CSI0_CLK, CLKFLAG_SKIP_AUTO_OFF);
25static DEFINE_CLK_PCOM(csi0_p_clk, CSI0_P_CLK, CLKFLAG_SKIP_AUTO_OFF);
26static DEFINE_CLK_PCOM(csi0_vfe_clk, CSI0_VFE_CLK, CLKFLAG_SKIP_AUTO_OFF);
27static DEFINE_CLK_PCOM(csi1_clk, CSI1_CLK, CLKFLAG_SKIP_AUTO_OFF);
28static DEFINE_CLK_PCOM(csi1_p_clk, CSI1_P_CLK, CLKFLAG_SKIP_AUTO_OFF);
29static DEFINE_CLK_PCOM(csi1_vfe_clk, CSI1_VFE_CLK, CLKFLAG_SKIP_AUTO_OFF);
30
31static struct pcom_clk dsi_byte_clk = {
32 .id = P_DSI_BYTE_CLK,
33 .c = {
34 .ops = &clk_ops_pcom_ext_config,
35 .dbg_name = "dsi_byte_clk",
36 CLK_INIT(dsi_byte_clk.c),
37 },
38};
39
40static struct pcom_clk dsi_clk = {
41 .id = P_DSI_CLK,
42 .c = {
43 .ops = &clk_ops_pcom_ext_config,
44 .dbg_name = "dsi_clk",
45 CLK_INIT(dsi_clk.c),
46 },
47};
48
49static struct pcom_clk dsi_esc_clk = {
50 .id = P_DSI_ESC_CLK,
51 .c = {
52 .ops = &clk_ops_pcom_ext_config,
53 .dbg_name = "dsi_esc_clk",
54 CLK_INIT(dsi_esc_clk.c),
55 },
56};
57
58static struct pcom_clk dsi_pixel_clk = {
59 .id = P_DSI_PIXEL_CLK,
60 .c = {
61 .ops = &clk_ops_pcom_ext_config,
62 .dbg_name = "dsi_pixel_clk",
63 CLK_INIT(dsi_pixel_clk.c),
64 },
65};
66
67static DEFINE_CLK_PCOM(dsi_ref_clk, DSI_REF_CLK, 0);
68static DEFINE_CLK_PCOM(ebi1_clk, EBI1_CLK,
69 CLKFLAG_SKIP_AUTO_OFF | CLKFLAG_MIN);
70static DEFINE_CLK_PCOM(ebi2_clk, EBI2_CLK, CLKFLAG_SKIP_AUTO_OFF);
71static DEFINE_CLK_PCOM(ecodec_clk, ECODEC_CLK, CLKFLAG_SKIP_AUTO_OFF);
72static DEFINE_CLK_PCOM(emdh_clk, EMDH_CLK, CLKFLAG_MIN | CLKFLAG_MAX);
73static DEFINE_CLK_PCOM(gp_clk, GP_CLK, CLKFLAG_SKIP_AUTO_OFF);
74static DEFINE_CLK_PCOM(grp_2d_clk, GRP_2D_CLK, CLKFLAG_SKIP_AUTO_OFF);
75static DEFINE_CLK_PCOM(grp_2d_p_clk, GRP_2D_P_CLK, CLKFLAG_SKIP_AUTO_OFF);
76static DEFINE_CLK_PCOM(grp_3d_clk, GRP_3D_CLK, 0);
77static DEFINE_CLK_PCOM(grp_3d_p_clk, GRP_3D_P_CLK, CLKFLAG_SKIP_AUTO_OFF);
78static DEFINE_CLK_PCOM(gsbi1_qup_clk, GSBI1_QUP_CLK, 0);
79static DEFINE_CLK_PCOM(gsbi1_qup_p_clk, GSBI1_QUP_P_CLK, 0);
80static DEFINE_CLK_PCOM(gsbi2_qup_clk, GSBI2_QUP_CLK, 0);
81static DEFINE_CLK_PCOM(gsbi2_qup_p_clk, GSBI2_QUP_P_CLK, 0);
82static DEFINE_CLK_PCOM(gsbi_clk, GSBI_CLK, CLKFLAG_SKIP_AUTO_OFF);
83static DEFINE_CLK_PCOM(gsbi_p_clk, GSBI_P_CLK, CLKFLAG_SKIP_AUTO_OFF);
84static DEFINE_CLK_PCOM(hdmi_clk, HDMI_CLK, CLKFLAG_SKIP_AUTO_OFF);
85static DEFINE_CLK_PCOM(i2c_clk, I2C_CLK, CLKFLAG_SKIP_AUTO_OFF);
86static DEFINE_CLK_PCOM(icodec_rx_clk, ICODEC_RX_CLK, CLKFLAG_SKIP_AUTO_OFF);
87static DEFINE_CLK_PCOM(icodec_tx_clk, ICODEC_TX_CLK, CLKFLAG_SKIP_AUTO_OFF);
88static DEFINE_CLK_PCOM(imem_clk, IMEM_CLK, 0);
89static DEFINE_CLK_PCOM(mdc_clk, MDC_CLK, CLKFLAG_SKIP_AUTO_OFF);
90static DEFINE_CLK_PCOM(mdp_clk, MDP_CLK, 0);
91static DEFINE_CLK_PCOM(mdp_lcdc_pad_pclk_clk, MDP_LCDC_PAD_PCLK_CLK,
92 CLKFLAG_SKIP_AUTO_OFF);
93static DEFINE_CLK_PCOM(mdp_lcdc_pclk_clk, MDP_LCDC_PCLK_CLK,
94 CLKFLAG_SKIP_AUTO_OFF);
95static DEFINE_CLK_PCOM(mdp_vsync_clk, MDP_VSYNC_CLK, 0);
96static DEFINE_CLK_PCOM(mdp_dsi_p_clk, MDP_DSI_P_CLK, 0);
97static DEFINE_CLK_PCOM(pbus_clk, PBUS_CLK,
98 CLKFLAG_SKIP_AUTO_OFF | CLKFLAG_MIN);
99static DEFINE_CLK_PCOM(pcm_clk, PCM_CLK, CLKFLAG_SKIP_AUTO_OFF);
100static DEFINE_CLK_PCOM(pmdh_clk, PMDH_CLK, CLKFLAG_MIN | CLKFLAG_MAX);
101static DEFINE_CLK_PCOM(sdac_clk, SDAC_CLK, 0);
102static DEFINE_CLK_PCOM(sdc1_clk, SDC1_CLK, 0);
103static DEFINE_CLK_PCOM(sdc1_p_clk, SDC1_P_CLK, 0);
104static DEFINE_CLK_PCOM(sdc2_clk, SDC2_CLK, 0);
105static DEFINE_CLK_PCOM(sdc2_p_clk, SDC2_P_CLK, 0);
106static DEFINE_CLK_PCOM(sdc3_clk, SDC3_CLK, 0);
107static DEFINE_CLK_PCOM(sdc3_p_clk, SDC3_P_CLK, 0);
108static DEFINE_CLK_PCOM(sdc4_clk, SDC4_CLK, 0);
109static DEFINE_CLK_PCOM(sdc4_p_clk, SDC4_P_CLK, 0);
110static DEFINE_CLK_PCOM(spi_clk, SPI_CLK, CLKFLAG_SKIP_AUTO_OFF);
111static DEFINE_CLK_PCOM(tsif_clk, TSIF_CLK, CLKFLAG_SKIP_AUTO_OFF);
112static DEFINE_CLK_PCOM(tsif_p_clk, TSIF_P_CLK, CLKFLAG_SKIP_AUTO_OFF);
113static DEFINE_CLK_PCOM(tsif_ref_clk, TSIF_REF_CLK, CLKFLAG_SKIP_AUTO_OFF);
114static DEFINE_CLK_PCOM(tv_dac_clk, TV_DAC_CLK, CLKFLAG_SKIP_AUTO_OFF);
115static DEFINE_CLK_PCOM(tv_enc_clk, TV_ENC_CLK, CLKFLAG_SKIP_AUTO_OFF);
116static DEFINE_CLK_PCOM(uart1_clk, UART1_CLK, 0);
117static DEFINE_CLK_PCOM(uart1dm_clk, UART1DM_CLK, 0);
118static DEFINE_CLK_PCOM(uart2_clk, UART2_CLK, 0);
119static DEFINE_CLK_PCOM(uart2dm_clk, UART2DM_CLK, 0);
120static DEFINE_CLK_PCOM(uart3_clk, UART3_CLK, 0);
121static DEFINE_CLK_PCOM(usb_hs2_clk, USB_HS2_CLK, 0);
122static DEFINE_CLK_PCOM(usb_hs2_p_clk, USB_HS2_P_CLK, 0);
123static DEFINE_CLK_PCOM(usb_hs3_clk, USB_HS3_CLK, 0);
124static DEFINE_CLK_PCOM(usb_hs3_p_clk, USB_HS3_P_CLK, 0);
125static DEFINE_CLK_PCOM(usb_hs_clk, USB_HS_CLK, 0);
126static DEFINE_CLK_PCOM(usb_hs_core_clk, USB_HS_CORE_CLK, 0);
127static DEFINE_CLK_PCOM(usb_hs_p_clk, USB_HS_P_CLK, 0);
128static DEFINE_CLK_PCOM(usb_otg_clk, USB_OTG_CLK, CLKFLAG_SKIP_AUTO_OFF);
129static DEFINE_CLK_PCOM(usb_phy_clk, USB_PHY_CLK, CLKFLAG_SKIP_AUTO_OFF);
130static DEFINE_CLK_PCOM(vdc_clk, VDC_CLK, CLKFLAG_MIN);
131static DEFINE_CLK_PCOM(vfe_axi_clk, VFE_AXI_CLK, 0);
132static DEFINE_CLK_PCOM(vfe_clk, VFE_CLK, 0);
133static DEFINE_CLK_PCOM(vfe_mdc_clk, VFE_MDC_CLK, 0);
134
135static DEFINE_CLK_VOTER(ebi_acpu_clk, &ebi1_clk.c);
136static DEFINE_CLK_VOTER(ebi_kgsl_clk, &ebi1_clk.c);
137static DEFINE_CLK_VOTER(ebi_lcdc_clk, &ebi1_clk.c);
138static DEFINE_CLK_VOTER(ebi_mddi_clk, &ebi1_clk.c);
139static DEFINE_CLK_VOTER(ebi_tv_clk, &ebi1_clk.c);
140static DEFINE_CLK_VOTER(ebi_usb_clk, &ebi1_clk.c);
141static DEFINE_CLK_VOTER(ebi_vfe_clk, &ebi1_clk.c);
142static DEFINE_CLK_VOTER(ebi_adm_clk, &ebi1_clk.c);
143
Stephen Boydbb600ae2011-08-02 20:11:40 -0700[diff] [blame]144static struct clk_lookup msm_clocks_7x01a[] = {
Matt Wagantalle1a86062011-08-18 17:46:10 -0700[diff] [blame]145 CLK_LOOKUP("core_clk", adm_clk.c, "msm_dmov"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]146 CLK_LOOKUP("adsp_clk", adsp_clk.c, NULL),
147 CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL),
148 CLK_LOOKUP("ebi2_clk", ebi2_clk.c, NULL),
149 CLK_LOOKUP("ecodec_clk", ecodec_clk.c, NULL),
150 CLK_LOOKUP("emdh_clk", emdh_clk.c, NULL),
151 CLK_LOOKUP("gp_clk", gp_clk.c, NULL),
152 CLK_LOOKUP("grp_clk", grp_3d_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -0700[diff] [blame]153 CLK_LOOKUP("core_clk", i2c_clk.c, "msm_i2c.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]154 CLK_LOOKUP("icodec_rx_clk", icodec_rx_clk.c, NULL),
155 CLK_LOOKUP("icodec_tx_clk", icodec_tx_clk.c, NULL),
156 CLK_LOOKUP("imem_clk", imem_clk.c, NULL),
157 CLK_LOOKUP("mdc_clk", mdc_clk.c, NULL),
158 CLK_LOOKUP("mddi_clk", pmdh_clk.c, NULL),
159 CLK_LOOKUP("mdp_clk", mdp_clk.c, NULL),
160 CLK_LOOKUP("pbus_clk", pbus_clk.c, NULL),
161 CLK_LOOKUP("pcm_clk", pcm_clk.c, NULL),
162 CLK_LOOKUP("sdac_clk", sdac_clk.c, NULL),
Matt Wagantall37ce3842011-08-17 16:00:36 -0700[diff] [blame]163 CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
164 CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"),
165 CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
166 CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"),
167 CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"),
168 CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"),
169 CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
170 CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]171 CLK_LOOKUP("tsif_clk", tsif_clk.c, NULL),
172 CLK_LOOKUP("tsif_ref_clk", tsif_ref_clk.c, NULL),
173 CLK_LOOKUP("tv_dac_clk", tv_dac_clk.c, NULL),
174 CLK_LOOKUP("tv_enc_clk", tv_enc_clk.c, NULL),
Matt Wagantalle2522372011-08-17 14:52:21 -0700[diff] [blame]175 CLK_LOOKUP("core_clk", uart1_clk.c, "msm_serial.0"),
176 CLK_LOOKUP("core_clk", uart2_clk.c, "msm_serial.1"),
177 CLK_LOOKUP("core_clk", uart3_clk.c, "msm_serial.2"),
178 CLK_LOOKUP("core_clk", uart1dm_clk.c, "msm_serial_hs.0"),
179 CLK_LOOKUP("core_clk", uart2dm_clk.c, "msm_serial_hs.1"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]180 CLK_LOOKUP("usb_hs_clk", usb_hs_clk.c, "msm_otg"),
181 CLK_LOOKUP("usb_hs_pclk", usb_hs_p_clk.c, "msm_otg"),
182 CLK_LOOKUP("usb_otg_clk", usb_otg_clk.c, NULL),
183 CLK_LOOKUP("vdc_clk", vdc_clk.c, NULL),
184 CLK_LOOKUP("vfe_clk", vfe_clk.c, NULL),
185 CLK_LOOKUP("vfe_mdc_clk", vfe_mdc_clk.c, NULL),
186};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]187
Stephen Boydbb600ae2011-08-02 20:11:40 -0700[diff] [blame]188struct clock_init_data msm7x01a_clock_init_data __initdata = {
189 .table = msm_clocks_7x01a,
190 .size = ARRAY_SIZE(msm_clocks_7x01a),
191};
192
193static struct clk_lookup msm_clocks_7x27[] = {
Matt Wagantalle1a86062011-08-18 17:46:10 -0700[diff] [blame]194 CLK_LOOKUP("core_clk", adm_clk.c, "msm_dmov"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]195 CLK_LOOKUP("adsp_clk", adsp_clk.c, NULL),
196 CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL),
197 CLK_LOOKUP("ebi2_clk", ebi2_clk.c, NULL),
198 CLK_LOOKUP("ecodec_clk", ecodec_clk.c, NULL),
199 CLK_LOOKUP("gp_clk", gp_clk.c, NULL),
200 CLK_LOOKUP("grp_clk", grp_3d_clk.c, NULL),
201 CLK_LOOKUP("grp_pclk", grp_3d_p_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -0700[diff] [blame]202 CLK_LOOKUP("core_clk", i2c_clk.c, "msm_i2c.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]203 CLK_LOOKUP("icodec_rx_clk", icodec_rx_clk.c, NULL),
204 CLK_LOOKUP("icodec_tx_clk", icodec_tx_clk.c, NULL),
205 CLK_LOOKUP("imem_clk", imem_clk.c, NULL),
206 CLK_LOOKUP("mdc_clk", mdc_clk.c, NULL),
207 CLK_LOOKUP("mddi_clk", pmdh_clk.c, NULL),
208 CLK_LOOKUP("mdp_clk", mdp_clk.c, NULL),
209 CLK_LOOKUP("mdp_lcdc_pclk_clk", mdp_lcdc_pclk_clk.c, NULL),
210 CLK_LOOKUP("mdp_lcdc_pad_pclk_clk", mdp_lcdc_pad_pclk_clk.c, NULL),
211 CLK_LOOKUP("mdp_vsync_clk", mdp_vsync_clk.c, NULL),
212 CLK_LOOKUP("pbus_clk", pbus_clk.c, NULL),
213 CLK_LOOKUP("pcm_clk", pcm_clk.c, NULL),
214 CLK_LOOKUP("sdac_clk", sdac_clk.c, NULL),
Matt Wagantall37ce3842011-08-17 16:00:36 -0700[diff] [blame]215 CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
216 CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"),
217 CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
218 CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"),
219 CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"),
220 CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"),
221 CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
222 CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]223 CLK_LOOKUP("tsif_clk", tsif_clk.c, NULL),
224 CLK_LOOKUP("tsif_ref_clk", tsif_ref_clk.c, NULL),
225 CLK_LOOKUP("tsif_pclk", tsif_p_clk.c, NULL),
Matt Wagantalle2522372011-08-17 14:52:21 -0700[diff] [blame]226 CLK_LOOKUP("core_clk", uart1_clk.c, "msm_serial.0"),
227 CLK_LOOKUP("core_clk", uart2_clk.c, "msm_serial.1"),
228 CLK_LOOKUP("core_clk", uart1dm_clk.c, "msm_serial_hs.0"),
229 CLK_LOOKUP("core_clk", uart2dm_clk.c, "msm_serial_hs.1"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]230 CLK_LOOKUP("usb_hs_clk", usb_hs_clk.c, NULL),
231 CLK_LOOKUP("usb_hs_pclk", usb_hs_p_clk.c, NULL),
232 CLK_LOOKUP("usb_otg_clk", usb_otg_clk.c, NULL),
233 CLK_LOOKUP("usb_phy_clk", usb_phy_clk.c, NULL),
234 CLK_LOOKUP("vdc_clk", vdc_clk.c, NULL),
235 CLK_LOOKUP("vfe_clk", vfe_clk.c, NULL),
236 CLK_LOOKUP("vfe_mdc_clk", vfe_mdc_clk.c, NULL),
237
238 CLK_LOOKUP("ebi1_acpu_clk", ebi_acpu_clk.c, NULL),
239 CLK_LOOKUP("ebi1_kgsl_clk", ebi_kgsl_clk.c, NULL),
240 CLK_LOOKUP("ebi1_lcdc_clk", ebi_lcdc_clk.c, NULL),
241 CLK_LOOKUP("ebi1_mddi_clk", ebi_mddi_clk.c, NULL),
242 CLK_LOOKUP("ebi1_usb_clk", ebi_usb_clk.c, NULL),
243 CLK_LOOKUP("ebi1_vfe_clk", ebi_vfe_clk.c, NULL),
Matt Wagantalle1a86062011-08-18 17:46:10 -0700[diff] [blame]244 CLK_LOOKUP("mem_clk", ebi_adm_clk.c, "msm_dmov"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]245};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]246
Stephen Boydbb600ae2011-08-02 20:11:40 -0700[diff] [blame]247struct clock_init_data msm7x27_clock_init_data __initdata = {
248 .table = msm_clocks_7x27,
249 .size = ARRAY_SIZE(msm_clocks_7x27),
250};
251
252static struct clk_lookup msm_clocks_7x27a[] = {
Matt Wagantalle1a86062011-08-18 17:46:10 -0700[diff] [blame]253 CLK_LOOKUP("core_clk", adm_clk.c, "msm_dmov"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]254 CLK_LOOKUP("adsp_clk", adsp_clk.c, NULL),
255 CLK_LOOKUP("ahb_m_clk", ahb_m_clk.c, NULL),
256 CLK_LOOKUP("ahb_s_clk", ahb_s_clk.c, NULL),
257 CLK_LOOKUP("cam_m_clk", cam_m_clk.c, NULL),
258 CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_camera_ov9726.0"),
259 CLK_LOOKUP("csi_pclk", csi0_p_clk.c, "msm_camera_ov9726.0"),
260 CLK_LOOKUP("csi_vfe_clk", csi0_vfe_clk.c, "msm_camera_ov9726.0"),
261 CLK_LOOKUP("csi_clk", csi1_clk.c, NULL),
262 CLK_LOOKUP("csi_pclk", csi1_p_clk.c, NULL),
263 CLK_LOOKUP("csi_vfe_clk", csi1_vfe_clk.c, NULL),
264 CLK_LOOKUP("dsi_byte_clk", dsi_byte_clk.c, NULL),
265 CLK_LOOKUP("dsi_clk", dsi_clk.c, NULL),
266 CLK_LOOKUP("dsi_esc_clk", dsi_esc_clk.c, NULL),
267 CLK_LOOKUP("dsi_pixel_clk", dsi_pixel_clk.c, NULL),
268 CLK_LOOKUP("dsi_ref_clk", dsi_ref_clk.c, NULL),
269 CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL),
270 CLK_LOOKUP("ebi2_clk", ebi2_clk.c, NULL),
271 CLK_LOOKUP("ecodec_clk", ecodec_clk.c, NULL),
272 CLK_LOOKUP("gp_clk", gp_clk.c, NULL),
273 CLK_LOOKUP("grp_clk", grp_3d_clk.c, NULL),
274 CLK_LOOKUP("grp_pclk", grp_3d_p_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -0700[diff] [blame]275 CLK_LOOKUP("core_clk", gsbi1_qup_clk.c, "qup_i2c.0"),
276 CLK_LOOKUP("core_clk", gsbi2_qup_clk.c, "qup_i2c.1"),
277 CLK_LOOKUP("iface_clk", gsbi1_qup_p_clk.c, "qup_i2c.0"),
278 CLK_LOOKUP("iface_clk", gsbi2_qup_p_clk.c, "qup_i2c.1"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]279 CLK_LOOKUP("icodec_rx_clk", icodec_rx_clk.c, NULL),
280 CLK_LOOKUP("icodec_tx_clk", icodec_tx_clk.c, NULL),
281 CLK_LOOKUP("imem_clk", imem_clk.c, NULL),
282 CLK_LOOKUP("mddi_clk", pmdh_clk.c, NULL),
283 CLK_LOOKUP("mdp_clk", mdp_clk.c, NULL),
284 CLK_LOOKUP("mdp_lcdc_pclk_clk", mdp_lcdc_pclk_clk.c, NULL),
285 CLK_LOOKUP("mdp_lcdc_pad_pclk_clk", mdp_lcdc_pad_pclk_clk.c, NULL),
286 CLK_LOOKUP("mdp_vsync_clk", mdp_vsync_clk.c, NULL),
287 CLK_LOOKUP("mdp_dsi_pclk", mdp_dsi_p_clk.c, NULL),
288 CLK_LOOKUP("pbus_clk", pbus_clk.c, NULL),
289 CLK_LOOKUP("pcm_clk", pcm_clk.c, NULL),
290 CLK_LOOKUP("sdac_clk", sdac_clk.c, NULL),
Matt Wagantall37ce3842011-08-17 16:00:36 -0700[diff] [blame]291 CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
292 CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"),
293 CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
294 CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"),
295 CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"),
296 CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"),
297 CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
298 CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]299 CLK_LOOKUP("tsif_ref_clk", tsif_ref_clk.c, NULL),
300 CLK_LOOKUP("tsif_pclk", tsif_p_clk.c, NULL),
Matt Wagantalle2522372011-08-17 14:52:21 -0700[diff] [blame]301 CLK_LOOKUP("core_clk", uart1_clk.c, "msm_serial.0"),
302 CLK_LOOKUP("core_clk", uart2_clk.c, "msm_serial.1"),
303 CLK_LOOKUP("core_clk", uart1dm_clk.c, "msm_serial_hs.0"),
304 CLK_LOOKUP("core_clk", uart2dm_clk.c, "msm_serial_hsl.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]305 CLK_LOOKUP("usb_hs_core_clk", usb_hs_core_clk.c, NULL),
306 CLK_LOOKUP("usb_hs2_clk", usb_hs2_clk.c, NULL),
307 CLK_LOOKUP("usb_hs_clk", usb_hs_clk.c, NULL),
308 CLK_LOOKUP("usb_hs_pclk", usb_hs_p_clk.c, NULL),
309 CLK_LOOKUP("usb_phy_clk", usb_phy_clk.c, NULL),
310 CLK_LOOKUP("vdc_clk", vdc_clk.c, NULL),
311 CLK_LOOKUP("vfe_clk", vfe_clk.c, NULL),
312 CLK_LOOKUP("vfe_mdc_clk", vfe_mdc_clk.c, NULL),
313
314 CLK_LOOKUP("ebi1_acpu_clk", ebi_acpu_clk.c, NULL),
315 CLK_LOOKUP("ebi1_kgsl_clk", ebi_kgsl_clk.c, NULL),
316 CLK_LOOKUP("ebi1_lcdc_clk", ebi_lcdc_clk.c, NULL),
317 CLK_LOOKUP("ebi1_mddi_clk", ebi_mddi_clk.c, NULL),
318 CLK_LOOKUP("ebi1_usb_clk", ebi_usb_clk.c, NULL),
319 CLK_LOOKUP("ebi1_vfe_clk", ebi_vfe_clk.c, NULL),
Matt Wagantalle1a86062011-08-18 17:46:10 -0700[diff] [blame]320 CLK_LOOKUP("mem_clk", ebi_adm_clk.c, "msm_dmov"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]321};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]322
Stephen Boydbb600ae2011-08-02 20:11:40 -0700[diff] [blame]323struct clock_init_data msm7x27a_clock_init_data __initdata = {
324 .table = msm_clocks_7x27a,
325 .size = ARRAY_SIZE(msm_clocks_7x27a),
326};
327
328static struct clk_lookup msm_clocks_8x50[] = {
Matt Wagantalle1a86062011-08-18 17:46:10 -0700[diff] [blame]329 CLK_LOOKUP("core_clk", adm_clk.c, "msm_dmov"),
Matt Wagantallc4b3a4d2011-08-17 16:58:39 -0700[diff] [blame]330 CLK_LOOKUP("core_clk", ce_clk.c, "qce.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]331 CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL),
332 CLK_LOOKUP("ebi2_clk", ebi2_clk.c, NULL),
333 CLK_LOOKUP("ecodec_clk", ecodec_clk.c, NULL),
334 CLK_LOOKUP("emdh_clk", emdh_clk.c, NULL),
335 CLK_LOOKUP("gp_clk", gp_clk.c, NULL),
336 CLK_LOOKUP("grp_clk", grp_3d_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -0700[diff] [blame]337 CLK_LOOKUP("core_clk", i2c_clk.c, "msm_i2c.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]338 CLK_LOOKUP("icodec_rx_clk", icodec_rx_clk.c, NULL),
339 CLK_LOOKUP("icodec_tx_clk", icodec_tx_clk.c, NULL),
340 CLK_LOOKUP("imem_clk", imem_clk.c, NULL),
341 CLK_LOOKUP("mdc_clk", mdc_clk.c, NULL),
342 CLK_LOOKUP("mddi_clk", pmdh_clk.c, NULL),
343 CLK_LOOKUP("mdp_clk", mdp_clk.c, NULL),
344 CLK_LOOKUP("mdp_lcdc_pclk_clk", mdp_lcdc_pclk_clk.c, NULL),
345 CLK_LOOKUP("mdp_lcdc_pad_pclk_clk", mdp_lcdc_pad_pclk_clk.c, NULL),
346 CLK_LOOKUP("mdp_vsync_clk", mdp_vsync_clk.c, NULL),
347 CLK_LOOKUP("pbus_clk", pbus_clk.c, NULL),
348 CLK_LOOKUP("pcm_clk", pcm_clk.c, NULL),
349 CLK_LOOKUP("sdac_clk", sdac_clk.c, NULL),
Matt Wagantall37ce3842011-08-17 16:00:36 -0700[diff] [blame]350 CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
351 CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"),
352 CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
353 CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"),
354 CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"),
355 CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"),
356 CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
357 CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"),
Matt Wagantallac294852011-08-17 15:44:58 -0700[diff] [blame]358 CLK_LOOKUP("core_clk", spi_clk.c, "spi_qsd.0"),
359 CLK_DUMMY("iface_clk", SPI_P_CLK, "spi_qsd.0", 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]360 CLK_LOOKUP("tsif_clk", tsif_clk.c, NULL),
361 CLK_LOOKUP("tsif_ref_clk", tsif_ref_clk.c, NULL),
362 CLK_LOOKUP("tv_dac_clk", tv_dac_clk.c, NULL),
363 CLK_LOOKUP("tv_enc_clk", tv_enc_clk.c, NULL),
Matt Wagantalle2522372011-08-17 14:52:21 -0700[diff] [blame]364 CLK_LOOKUP("core_clk", uart1_clk.c, "msm_serial.0"),
365 CLK_LOOKUP("core_clk", uart2_clk.c, "msm_serial.1"),
366 CLK_LOOKUP("core_clk", uart3_clk.c, "msm_serial.2"),
367 CLK_LOOKUP("core_clk", uart1dm_clk.c, "msm_serial_hs.0"),
368 CLK_LOOKUP("core_clk", uart2dm_clk.c, "msm_serial_hs.1"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]369 CLK_LOOKUP("usb_hs_clk", usb_hs_clk.c, NULL),
370 CLK_LOOKUP("usb_hs_pclk", usb_hs_p_clk.c, NULL),
371 CLK_LOOKUP("usb_otg_clk", usb_otg_clk.c, NULL),
372 CLK_LOOKUP("vdc_clk", vdc_clk.c, NULL),
373 CLK_LOOKUP("vfe_clk", vfe_clk.c, NULL),
374 CLK_LOOKUP("vfe_mdc_clk", vfe_mdc_clk.c, NULL),
375 CLK_LOOKUP("vfe_axi_clk", vfe_axi_clk.c, NULL),
376 CLK_LOOKUP("usb_hs2_clk", usb_hs2_clk.c, NULL),
377 CLK_LOOKUP("usb_hs2_pclk", usb_hs2_p_clk.c, NULL),
378 CLK_LOOKUP("usb_hs3_clk", usb_hs3_clk.c, NULL),
379 CLK_LOOKUP("usb_hs3_pclk", usb_hs3_p_clk.c, NULL),
380 CLK_LOOKUP("usb_phy_clk", usb_phy_clk.c, NULL),
381
382 CLK_LOOKUP("ebi1_acpu_clk", ebi_acpu_clk.c, NULL),
383 CLK_LOOKUP("ebi1_kgsl_clk", ebi_kgsl_clk.c, NULL),
384 CLK_LOOKUP("ebi1_lcdc_clk", ebi_lcdc_clk.c, NULL),
385 CLK_LOOKUP("ebi1_mddi_clk", ebi_mddi_clk.c, NULL),
386 CLK_LOOKUP("ebi1_tv_clk", ebi_tv_clk.c, NULL),
387 CLK_LOOKUP("ebi1_usb_clk", ebi_usb_clk.c, NULL),
388 CLK_LOOKUP("ebi1_vfe_clk", ebi_vfe_clk.c, NULL),
Matt Wagantalle1a86062011-08-18 17:46:10 -0700[diff] [blame]389 CLK_LOOKUP("mem_clk", ebi_adm_clk.c, "msm_dmov"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]390
391 CLK_LOOKUP("grp_pclk", grp_3d_p_clk.c, NULL),
392 CLK_LOOKUP("grp_2d_clk", grp_2d_clk.c, NULL),
393 CLK_LOOKUP("grp_2d_pclk", grp_2d_p_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -0700[diff] [blame]394 CLK_LOOKUP("core_clk", gsbi_clk.c, "qup_i2c.4"),
395 CLK_LOOKUP("iface_clk", gsbi_p_clk.c, "qup_i2c.4"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]396};
Stephen Boydbb600ae2011-08-02 20:11:40 -0700[diff] [blame]397
398struct clock_init_data qds8x50_clock_init_data __initdata = {
399 .table = msm_clocks_8x50,
400 .size = ARRAY_SIZE(msm_clocks_8x50),
401};