blob: d83b77f821e96200812c59ad46c023ad79d6004f [file] [log] [blame]
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001/*
Sujithcee075a2009-03-13 09:07:23 +05302 * Copyright (c) 2008-2009 Atheros Communications Inc.
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef REG_H
18#define REG_H
19
20#define AR_CR 0x0008
21#define AR_CR_RXE 0x00000004
22#define AR_CR_RXD 0x00000020
23#define AR_CR_SWI 0x00000040
24
25#define AR_RXDP 0x000C
26
27#define AR_CFG 0x0014
28#define AR_CFG_SWTD 0x00000001
29#define AR_CFG_SWTB 0x00000002
30#define AR_CFG_SWRD 0x00000004
31#define AR_CFG_SWRB 0x00000008
32#define AR_CFG_SWRG 0x00000010
33#define AR_CFG_AP_ADHOC_INDICATION 0x00000020
34#define AR_CFG_PHOK 0x00000100
35#define AR_CFG_CLK_GATE_DIS 0x00000400
36#define AR_CFG_EEBS 0x00000200
37#define AR_CFG_PCI_MASTER_REQ_Q_THRESH 0x00060000
38#define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S 17
39
40#define AR_MIRT 0x0020
41#define AR_MIRT_VAL 0x0000ffff
42#define AR_MIRT_VAL_S 16
43
44#define AR_IER 0x0024
45#define AR_IER_ENABLE 0x00000001
46#define AR_IER_DISABLE 0x00000000
47
48#define AR_TIMT 0x0028
49#define AR_TIMT_LAST 0x0000ffff
50#define AR_TIMT_LAST_S 0
51#define AR_TIMT_FIRST 0xffff0000
52#define AR_TIMT_FIRST_S 16
53
54#define AR_RIMT 0x002C
55#define AR_RIMT_LAST 0x0000ffff
56#define AR_RIMT_LAST_S 0
57#define AR_RIMT_FIRST 0xffff0000
58#define AR_RIMT_FIRST_S 16
59
60#define AR_DMASIZE_4B 0x00000000
61#define AR_DMASIZE_8B 0x00000001
62#define AR_DMASIZE_16B 0x00000002
63#define AR_DMASIZE_32B 0x00000003
64#define AR_DMASIZE_64B 0x00000004
65#define AR_DMASIZE_128B 0x00000005
66#define AR_DMASIZE_256B 0x00000006
67#define AR_DMASIZE_512B 0x00000007
68
69#define AR_TXCFG 0x0030
Gabor Juhosaebe2b52009-03-03 10:49:59 +010070#define AR_TXCFG_DMASZ_MASK 0x00000007
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070071#define AR_TXCFG_DMASZ_4B 0
72#define AR_TXCFG_DMASZ_8B 1
73#define AR_TXCFG_DMASZ_16B 2
74#define AR_TXCFG_DMASZ_32B 3
75#define AR_TXCFG_DMASZ_64B 4
76#define AR_TXCFG_DMASZ_128B 5
77#define AR_TXCFG_DMASZ_256B 6
78#define AR_TXCFG_DMASZ_512B 7
79#define AR_FTRIG 0x000003F0
80#define AR_FTRIG_S 4
81#define AR_FTRIG_IMMED 0x00000000
82#define AR_FTRIG_64B 0x00000010
83#define AR_FTRIG_128B 0x00000020
84#define AR_FTRIG_192B 0x00000030
85#define AR_FTRIG_256B 0x00000040
86#define AR_FTRIG_512B 0x00000080
87#define AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY 0x00000800
88
89#define AR_RXCFG 0x0034
90#define AR_RXCFG_CHIRP 0x00000008
91#define AR_RXCFG_ZLFDMA 0x00000010
92#define AR_RXCFG_DMASZ_MASK 0x00000007
93#define AR_RXCFG_DMASZ_4B 0
94#define AR_RXCFG_DMASZ_8B 1
95#define AR_RXCFG_DMASZ_16B 2
96#define AR_RXCFG_DMASZ_32B 3
97#define AR_RXCFG_DMASZ_64B 4
98#define AR_RXCFG_DMASZ_128B 5
99#define AR_RXCFG_DMASZ_256B 6
100#define AR_RXCFG_DMASZ_512B 7
101
102#define AR_MIBC 0x0040
103#define AR_MIBC_COW 0x00000001
104#define AR_MIBC_FMC 0x00000002
105#define AR_MIBC_CMC 0x00000004
106#define AR_MIBC_MCS 0x00000008
107
108#define AR_TOPS 0x0044
109#define AR_TOPS_MASK 0x0000FFFF
110
111#define AR_RXNPTO 0x0048
112#define AR_RXNPTO_MASK 0x000003FF
113
114#define AR_TXNPTO 0x004C
115#define AR_TXNPTO_MASK 0x000003FF
116#define AR_TXNPTO_QCU_MASK 0x000FFC00
117
118#define AR_RPGTO 0x0050
119#define AR_RPGTO_MASK 0x000003FF
120
121#define AR_RPCNT 0x0054
122#define AR_RPCNT_MASK 0x0000001F
123
124#define AR_MACMISC 0x0058
125#define AR_MACMISC_PCI_EXT_FORCE 0x00000010
126#define AR_MACMISC_DMA_OBS 0x000001E0
127#define AR_MACMISC_DMA_OBS_S 5
128#define AR_MACMISC_DMA_OBS_LINE_0 0
129#define AR_MACMISC_DMA_OBS_LINE_1 1
130#define AR_MACMISC_DMA_OBS_LINE_2 2
131#define AR_MACMISC_DMA_OBS_LINE_3 3
132#define AR_MACMISC_DMA_OBS_LINE_4 4
133#define AR_MACMISC_DMA_OBS_LINE_5 5
134#define AR_MACMISC_DMA_OBS_LINE_6 6
135#define AR_MACMISC_DMA_OBS_LINE_7 7
136#define AR_MACMISC_DMA_OBS_LINE_8 8
137#define AR_MACMISC_MISC_OBS 0x00000E00
138#define AR_MACMISC_MISC_OBS_S 9
139#define AR_MACMISC_MISC_OBS_BUS_LSB 0x00007000
140#define AR_MACMISC_MISC_OBS_BUS_LSB_S 12
141#define AR_MACMISC_MISC_OBS_BUS_MSB 0x00038000
142#define AR_MACMISC_MISC_OBS_BUS_MSB_S 15
143#define AR_MACMISC_MISC_OBS_BUS_1 1
144
145#define AR_GTXTO 0x0064
146#define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF
147#define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000
148#define AR_GTXTO_TIMEOUT_LIMIT_S 16
149
150#define AR_GTTM 0x0068
151#define AR_GTTM_USEC 0x00000001
152#define AR_GTTM_IGNORE_IDLE 0x00000002
153#define AR_GTTM_RESET_IDLE 0x00000004
154#define AR_GTTM_CST_USEC 0x00000008
155
156#define AR_CST 0x006C
157#define AR_CST_TIMEOUT_COUNTER 0x0000FFFF
158#define AR_CST_TIMEOUT_LIMIT 0xFFFF0000
159#define AR_CST_TIMEOUT_LIMIT_S 16
160
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700161#define AR_ISR 0x0080
162#define AR_ISR_RXOK 0x00000001
163#define AR_ISR_RXDESC 0x00000002
164#define AR_ISR_RXERR 0x00000004
165#define AR_ISR_RXNOPKT 0x00000008
166#define AR_ISR_RXEOL 0x00000010
167#define AR_ISR_RXORN 0x00000020
168#define AR_ISR_TXOK 0x00000040
169#define AR_ISR_TXDESC 0x00000080
170#define AR_ISR_TXERR 0x00000100
171#define AR_ISR_TXNOPKT 0x00000200
172#define AR_ISR_TXEOL 0x00000400
173#define AR_ISR_TXURN 0x00000800
174#define AR_ISR_MIB 0x00001000
175#define AR_ISR_SWI 0x00002000
176#define AR_ISR_RXPHY 0x00004000
177#define AR_ISR_RXKCM 0x00008000
178#define AR_ISR_SWBA 0x00010000
179#define AR_ISR_BRSSI 0x00020000
180#define AR_ISR_BMISS 0x00040000
181#define AR_ISR_BNR 0x00100000
182#define AR_ISR_RXCHIRP 0x00200000
183#define AR_ISR_BCNMISC 0x00800000
184#define AR_ISR_TIM 0x00800000
185#define AR_ISR_QCBROVF 0x02000000
186#define AR_ISR_QCBRURN 0x04000000
187#define AR_ISR_QTRIG 0x08000000
188#define AR_ISR_GENTMR 0x10000000
189
190#define AR_ISR_TXMINTR 0x00080000
191#define AR_ISR_RXMINTR 0x01000000
192#define AR_ISR_TXINTM 0x40000000
193#define AR_ISR_RXINTM 0x80000000
194
195#define AR_ISR_S0 0x0084
196#define AR_ISR_S0_QCU_TXOK 0x000003FF
197#define AR_ISR_S0_QCU_TXOK_S 0
198#define AR_ISR_S0_QCU_TXDESC 0x03FF0000
199#define AR_ISR_S0_QCU_TXDESC_S 16
200
201#define AR_ISR_S1 0x0088
202#define AR_ISR_S1_QCU_TXERR 0x000003FF
203#define AR_ISR_S1_QCU_TXERR_S 0
204#define AR_ISR_S1_QCU_TXEOL 0x03FF0000
205#define AR_ISR_S1_QCU_TXEOL_S 16
206
207#define AR_ISR_S2 0x008c
208#define AR_ISR_S2_QCU_TXURN 0x000003FF
209#define AR_ISR_S2_CST 0x00400000
210#define AR_ISR_S2_GTT 0x00800000
211#define AR_ISR_S2_TIM 0x01000000
212#define AR_ISR_S2_CABEND 0x02000000
213#define AR_ISR_S2_DTIMSYNC 0x04000000
214#define AR_ISR_S2_BCNTO 0x08000000
215#define AR_ISR_S2_CABTO 0x10000000
216#define AR_ISR_S2_DTIM 0x20000000
217#define AR_ISR_S2_TSFOOR 0x40000000
218#define AR_ISR_S2_TBTT_TIME 0x80000000
219
220#define AR_ISR_S3 0x0090
221#define AR_ISR_S3_QCU_QCBROVF 0x000003FF
222#define AR_ISR_S3_QCU_QCBRURN 0x03FF0000
223
224#define AR_ISR_S4 0x0094
225#define AR_ISR_S4_QCU_QTRIG 0x000003FF
226#define AR_ISR_S4_RESV0 0xFFFFFC00
227
228#define AR_ISR_S5 0x0098
229#define AR_ISR_S5_TIMER_TRIG 0x000000FF
230#define AR_ISR_S5_TIMER_THRESH 0x0007FE00
231#define AR_ISR_S5_TIM_TIMER 0x00000010
232#define AR_ISR_S5_DTIM_TIMER 0x00000020
233#define AR_ISR_S5_S 0x00d8
234#define AR_IMR_S5 0x00b8
235#define AR_IMR_S5_TIM_TIMER 0x00000010
236#define AR_IMR_S5_DTIM_TIMER 0x00000020
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +0530237#define AR_ISR_S5_GENTIMER_TRIG 0x0000FF80
238#define AR_ISR_S5_GENTIMER_TRIG_S 0
239#define AR_ISR_S5_GENTIMER_THRESH 0xFF800000
240#define AR_ISR_S5_GENTIMER_THRESH_S 16
241#define AR_ISR_S5_S 0x00d8
242#define AR_IMR_S5_GENTIMER_TRIG 0x0000FF80
243#define AR_IMR_S5_GENTIMER_TRIG_S 0
244#define AR_IMR_S5_GENTIMER_THRESH 0xFF800000
245#define AR_IMR_S5_GENTIMER_THRESH_S 16
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700246
247#define AR_IMR 0x00a0
248#define AR_IMR_RXOK 0x00000001
249#define AR_IMR_RXDESC 0x00000002
250#define AR_IMR_RXERR 0x00000004
251#define AR_IMR_RXNOPKT 0x00000008
252#define AR_IMR_RXEOL 0x00000010
253#define AR_IMR_RXORN 0x00000020
254#define AR_IMR_TXOK 0x00000040
255#define AR_IMR_TXDESC 0x00000080
256#define AR_IMR_TXERR 0x00000100
257#define AR_IMR_TXNOPKT 0x00000200
258#define AR_IMR_TXEOL 0x00000400
259#define AR_IMR_TXURN 0x00000800
260#define AR_IMR_MIB 0x00001000
261#define AR_IMR_SWI 0x00002000
262#define AR_IMR_RXPHY 0x00004000
263#define AR_IMR_RXKCM 0x00008000
264#define AR_IMR_SWBA 0x00010000
265#define AR_IMR_BRSSI 0x00020000
266#define AR_IMR_BMISS 0x00040000
267#define AR_IMR_BNR 0x00100000
268#define AR_IMR_RXCHIRP 0x00200000
269#define AR_IMR_BCNMISC 0x00800000
270#define AR_IMR_TIM 0x00800000
271#define AR_IMR_QCBROVF 0x02000000
272#define AR_IMR_QCBRURN 0x04000000
273#define AR_IMR_QTRIG 0x08000000
274#define AR_IMR_GENTMR 0x10000000
275
276#define AR_IMR_TXMINTR 0x00080000
277#define AR_IMR_RXMINTR 0x01000000
278#define AR_IMR_TXINTM 0x40000000
279#define AR_IMR_RXINTM 0x80000000
280
281#define AR_IMR_S0 0x00a4
282#define AR_IMR_S0_QCU_TXOK 0x000003FF
283#define AR_IMR_S0_QCU_TXOK_S 0
284#define AR_IMR_S0_QCU_TXDESC 0x03FF0000
285#define AR_IMR_S0_QCU_TXDESC_S 16
286
287#define AR_IMR_S1 0x00a8
288#define AR_IMR_S1_QCU_TXERR 0x000003FF
289#define AR_IMR_S1_QCU_TXERR_S 0
290#define AR_IMR_S1_QCU_TXEOL 0x03FF0000
291#define AR_IMR_S1_QCU_TXEOL_S 16
292
293#define AR_IMR_S2 0x00ac
294#define AR_IMR_S2_QCU_TXURN 0x000003FF
295#define AR_IMR_S2_QCU_TXURN_S 0
296#define AR_IMR_S2_CST 0x00400000
297#define AR_IMR_S2_GTT 0x00800000
298#define AR_IMR_S2_TIM 0x01000000
299#define AR_IMR_S2_CABEND 0x02000000
300#define AR_IMR_S2_DTIMSYNC 0x04000000
301#define AR_IMR_S2_BCNTO 0x08000000
302#define AR_IMR_S2_CABTO 0x10000000
303#define AR_IMR_S2_DTIM 0x20000000
304#define AR_IMR_S2_TSFOOR 0x40000000
305
306#define AR_IMR_S3 0x00b0
307#define AR_IMR_S3_QCU_QCBROVF 0x000003FF
308#define AR_IMR_S3_QCU_QCBRURN 0x03FF0000
309#define AR_IMR_S3_QCU_QCBRURN_S 16
310
311#define AR_IMR_S4 0x00b4
312#define AR_IMR_S4_QCU_QTRIG 0x000003FF
313#define AR_IMR_S4_RESV0 0xFFFFFC00
314
315#define AR_IMR_S5 0x00b8
316#define AR_IMR_S5_TIMER_TRIG 0x000000FF
317#define AR_IMR_S5_TIMER_THRESH 0x0000FF00
318
319
320#define AR_ISR_RAC 0x00c0
321#define AR_ISR_S0_S 0x00c4
322#define AR_ISR_S0_QCU_TXOK 0x000003FF
323#define AR_ISR_S0_QCU_TXOK_S 0
324#define AR_ISR_S0_QCU_TXDESC 0x03FF0000
325#define AR_ISR_S0_QCU_TXDESC_S 16
326
327#define AR_ISR_S1_S 0x00c8
328#define AR_ISR_S1_QCU_TXERR 0x000003FF
329#define AR_ISR_S1_QCU_TXERR_S 0
330#define AR_ISR_S1_QCU_TXEOL 0x03FF0000
331#define AR_ISR_S1_QCU_TXEOL_S 16
332
333#define AR_ISR_S2_S 0x00cc
334#define AR_ISR_S3_S 0x00d0
335#define AR_ISR_S4_S 0x00d4
336#define AR_ISR_S5_S 0x00d8
337#define AR_DMADBG_0 0x00e0
338#define AR_DMADBG_1 0x00e4
339#define AR_DMADBG_2 0x00e8
340#define AR_DMADBG_3 0x00ec
341#define AR_DMADBG_4 0x00f0
342#define AR_DMADBG_5 0x00f4
343#define AR_DMADBG_6 0x00f8
344#define AR_DMADBG_7 0x00fc
345
346#define AR_NUM_QCU 10
347#define AR_QCU_0 0x0001
348#define AR_QCU_1 0x0002
349#define AR_QCU_2 0x0004
350#define AR_QCU_3 0x0008
351#define AR_QCU_4 0x0010
352#define AR_QCU_5 0x0020
353#define AR_QCU_6 0x0040
354#define AR_QCU_7 0x0080
355#define AR_QCU_8 0x0100
356#define AR_QCU_9 0x0200
357
358#define AR_Q0_TXDP 0x0800
359#define AR_Q1_TXDP 0x0804
360#define AR_Q2_TXDP 0x0808
361#define AR_Q3_TXDP 0x080c
362#define AR_Q4_TXDP 0x0810
363#define AR_Q5_TXDP 0x0814
364#define AR_Q6_TXDP 0x0818
365#define AR_Q7_TXDP 0x081c
366#define AR_Q8_TXDP 0x0820
367#define AR_Q9_TXDP 0x0824
368#define AR_QTXDP(_i) (AR_Q0_TXDP + ((_i)<<2))
369
370#define AR_Q_TXE 0x0840
371#define AR_Q_TXE_M 0x000003FF
372
373#define AR_Q_TXD 0x0880
374#define AR_Q_TXD_M 0x000003FF
375
376#define AR_Q0_CBRCFG 0x08c0
377#define AR_Q1_CBRCFG 0x08c4
378#define AR_Q2_CBRCFG 0x08c8
379#define AR_Q3_CBRCFG 0x08cc
380#define AR_Q4_CBRCFG 0x08d0
381#define AR_Q5_CBRCFG 0x08d4
382#define AR_Q6_CBRCFG 0x08d8
383#define AR_Q7_CBRCFG 0x08dc
384#define AR_Q8_CBRCFG 0x08e0
385#define AR_Q9_CBRCFG 0x08e4
386#define AR_QCBRCFG(_i) (AR_Q0_CBRCFG + ((_i)<<2))
387#define AR_Q_CBRCFG_INTERVAL 0x00FFFFFF
388#define AR_Q_CBRCFG_INTERVAL_S 0
389#define AR_Q_CBRCFG_OVF_THRESH 0xFF000000
390#define AR_Q_CBRCFG_OVF_THRESH_S 24
391
392#define AR_Q0_RDYTIMECFG 0x0900
393#define AR_Q1_RDYTIMECFG 0x0904
394#define AR_Q2_RDYTIMECFG 0x0908
395#define AR_Q3_RDYTIMECFG 0x090c
396#define AR_Q4_RDYTIMECFG 0x0910
397#define AR_Q5_RDYTIMECFG 0x0914
398#define AR_Q6_RDYTIMECFG 0x0918
399#define AR_Q7_RDYTIMECFG 0x091c
400#define AR_Q8_RDYTIMECFG 0x0920
401#define AR_Q9_RDYTIMECFG 0x0924
402#define AR_QRDYTIMECFG(_i) (AR_Q0_RDYTIMECFG + ((_i)<<2))
403#define AR_Q_RDYTIMECFG_DURATION 0x00FFFFFF
404#define AR_Q_RDYTIMECFG_DURATION_S 0
405#define AR_Q_RDYTIMECFG_EN 0x01000000
406
407#define AR_Q_ONESHOTARM_SC 0x0940
408#define AR_Q_ONESHOTARM_SC_M 0x000003FF
409#define AR_Q_ONESHOTARM_SC_RESV0 0xFFFFFC00
410
411#define AR_Q_ONESHOTARM_CC 0x0980
412#define AR_Q_ONESHOTARM_CC_M 0x000003FF
413#define AR_Q_ONESHOTARM_CC_RESV0 0xFFFFFC00
414
415#define AR_Q0_MISC 0x09c0
416#define AR_Q1_MISC 0x09c4
417#define AR_Q2_MISC 0x09c8
418#define AR_Q3_MISC 0x09cc
419#define AR_Q4_MISC 0x09d0
420#define AR_Q5_MISC 0x09d4
421#define AR_Q6_MISC 0x09d8
422#define AR_Q7_MISC 0x09dc
423#define AR_Q8_MISC 0x09e0
424#define AR_Q9_MISC 0x09e4
425#define AR_QMISC(_i) (AR_Q0_MISC + ((_i)<<2))
426#define AR_Q_MISC_FSP 0x0000000F
427#define AR_Q_MISC_FSP_ASAP 0
428#define AR_Q_MISC_FSP_CBR 1
429#define AR_Q_MISC_FSP_DBA_GATED 2
430#define AR_Q_MISC_FSP_TIM_GATED 3
431#define AR_Q_MISC_FSP_BEACON_SENT_GATED 4
432#define AR_Q_MISC_FSP_BEACON_RCVD_GATED 5
433#define AR_Q_MISC_ONE_SHOT_EN 0x00000010
434#define AR_Q_MISC_CBR_INCR_DIS1 0x00000020
435#define AR_Q_MISC_CBR_INCR_DIS0 0x00000040
436#define AR_Q_MISC_BEACON_USE 0x00000080
437#define AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN 0x00000100
438#define AR_Q_MISC_RDYTIME_EXP_POLICY 0x00000200
439#define AR_Q_MISC_RESET_CBR_EXP_CTR 0x00000400
440#define AR_Q_MISC_DCU_EARLY_TERM_REQ 0x00000800
441#define AR_Q_MISC_RESV0 0xFFFFF000
442
443#define AR_Q0_STS 0x0a00
444#define AR_Q1_STS 0x0a04
445#define AR_Q2_STS 0x0a08
446#define AR_Q3_STS 0x0a0c
447#define AR_Q4_STS 0x0a10
448#define AR_Q5_STS 0x0a14
449#define AR_Q6_STS 0x0a18
450#define AR_Q7_STS 0x0a1c
451#define AR_Q8_STS 0x0a20
452#define AR_Q9_STS 0x0a24
453#define AR_QSTS(_i) (AR_Q0_STS + ((_i)<<2))
454#define AR_Q_STS_PEND_FR_CNT 0x00000003
455#define AR_Q_STS_RESV0 0x000000FC
456#define AR_Q_STS_CBR_EXP_CNT 0x0000FF00
457#define AR_Q_STS_RESV1 0xFFFF0000
458
459#define AR_Q_RDYTIMESHDN 0x0a40
460#define AR_Q_RDYTIMESHDN_M 0x000003FF
461
462
463#define AR_NUM_DCU 10
464#define AR_DCU_0 0x0001
465#define AR_DCU_1 0x0002
466#define AR_DCU_2 0x0004
467#define AR_DCU_3 0x0008
468#define AR_DCU_4 0x0010
469#define AR_DCU_5 0x0020
470#define AR_DCU_6 0x0040
471#define AR_DCU_7 0x0080
472#define AR_DCU_8 0x0100
473#define AR_DCU_9 0x0200
474
475#define AR_D0_QCUMASK 0x1000
476#define AR_D1_QCUMASK 0x1004
477#define AR_D2_QCUMASK 0x1008
478#define AR_D3_QCUMASK 0x100c
479#define AR_D4_QCUMASK 0x1010
480#define AR_D5_QCUMASK 0x1014
481#define AR_D6_QCUMASK 0x1018
482#define AR_D7_QCUMASK 0x101c
483#define AR_D8_QCUMASK 0x1020
484#define AR_D9_QCUMASK 0x1024
485#define AR_DQCUMASK(_i) (AR_D0_QCUMASK + ((_i)<<2))
486#define AR_D_QCUMASK 0x000003FF
487#define AR_D_QCUMASK_RESV0 0xFFFFFC00
488
489#define AR_D_TXBLK_CMD 0x1038
490#define AR_D_TXBLK_DATA(i) (AR_D_TXBLK_CMD+(i))
491
492#define AR_D0_LCL_IFS 0x1040
493#define AR_D1_LCL_IFS 0x1044
494#define AR_D2_LCL_IFS 0x1048
495#define AR_D3_LCL_IFS 0x104c
496#define AR_D4_LCL_IFS 0x1050
497#define AR_D5_LCL_IFS 0x1054
498#define AR_D6_LCL_IFS 0x1058
499#define AR_D7_LCL_IFS 0x105c
500#define AR_D8_LCL_IFS 0x1060
501#define AR_D9_LCL_IFS 0x1064
502#define AR_DLCL_IFS(_i) (AR_D0_LCL_IFS + ((_i)<<2))
503#define AR_D_LCL_IFS_CWMIN 0x000003FF
504#define AR_D_LCL_IFS_CWMIN_S 0
505#define AR_D_LCL_IFS_CWMAX 0x000FFC00
506#define AR_D_LCL_IFS_CWMAX_S 10
507#define AR_D_LCL_IFS_AIFS 0x0FF00000
508#define AR_D_LCL_IFS_AIFS_S 20
509
510#define AR_D_LCL_IFS_RESV0 0xF0000000
511
512#define AR_D0_RETRY_LIMIT 0x1080
513#define AR_D1_RETRY_LIMIT 0x1084
514#define AR_D2_RETRY_LIMIT 0x1088
515#define AR_D3_RETRY_LIMIT 0x108c
516#define AR_D4_RETRY_LIMIT 0x1090
517#define AR_D5_RETRY_LIMIT 0x1094
518#define AR_D6_RETRY_LIMIT 0x1098
519#define AR_D7_RETRY_LIMIT 0x109c
520#define AR_D8_RETRY_LIMIT 0x10a0
521#define AR_D9_RETRY_LIMIT 0x10a4
522#define AR_DRETRY_LIMIT(_i) (AR_D0_RETRY_LIMIT + ((_i)<<2))
523#define AR_D_RETRY_LIMIT_FR_SH 0x0000000F
524#define AR_D_RETRY_LIMIT_FR_SH_S 0
525#define AR_D_RETRY_LIMIT_STA_SH 0x00003F00
526#define AR_D_RETRY_LIMIT_STA_SH_S 8
527#define AR_D_RETRY_LIMIT_STA_LG 0x000FC000
528#define AR_D_RETRY_LIMIT_STA_LG_S 14
529#define AR_D_RETRY_LIMIT_RESV0 0xFFF00000
530
531#define AR_D0_CHNTIME 0x10c0
532#define AR_D1_CHNTIME 0x10c4
533#define AR_D2_CHNTIME 0x10c8
534#define AR_D3_CHNTIME 0x10cc
535#define AR_D4_CHNTIME 0x10d0
536#define AR_D5_CHNTIME 0x10d4
537#define AR_D6_CHNTIME 0x10d8
538#define AR_D7_CHNTIME 0x10dc
539#define AR_D8_CHNTIME 0x10e0
540#define AR_D9_CHNTIME 0x10e4
541#define AR_DCHNTIME(_i) (AR_D0_CHNTIME + ((_i)<<2))
542#define AR_D_CHNTIME_DUR 0x000FFFFF
543#define AR_D_CHNTIME_DUR_S 0
544#define AR_D_CHNTIME_EN 0x00100000
545#define AR_D_CHNTIME_RESV0 0xFFE00000
546
547#define AR_D0_MISC 0x1100
548#define AR_D1_MISC 0x1104
549#define AR_D2_MISC 0x1108
550#define AR_D3_MISC 0x110c
551#define AR_D4_MISC 0x1110
552#define AR_D5_MISC 0x1114
553#define AR_D6_MISC 0x1118
554#define AR_D7_MISC 0x111c
555#define AR_D8_MISC 0x1120
556#define AR_D9_MISC 0x1124
557#define AR_DMISC(_i) (AR_D0_MISC + ((_i)<<2))
558#define AR_D_MISC_BKOFF_THRESH 0x0000003F
559#define AR_D_MISC_RETRY_CNT_RESET_EN 0x00000040
560#define AR_D_MISC_CW_RESET_EN 0x00000080
561#define AR_D_MISC_FRAG_WAIT_EN 0x00000100
562#define AR_D_MISC_FRAG_BKOFF_EN 0x00000200
563#define AR_D_MISC_CW_BKOFF_EN 0x00001000
564#define AR_D_MISC_VIR_COL_HANDLING 0x0000C000
565#define AR_D_MISC_VIR_COL_HANDLING_S 14
566#define AR_D_MISC_VIR_COL_HANDLING_DEFAULT 0
567#define AR_D_MISC_VIR_COL_HANDLING_IGNORE 1
568#define AR_D_MISC_BEACON_USE 0x00010000
569#define AR_D_MISC_ARB_LOCKOUT_CNTRL 0x00060000
570#define AR_D_MISC_ARB_LOCKOUT_CNTRL_S 17
571#define AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0
572#define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1
573#define AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL 2
574#define AR_D_MISC_ARB_LOCKOUT_IGNORE 0x00080000
575#define AR_D_MISC_SEQ_NUM_INCR_DIS 0x00100000
576#define AR_D_MISC_POST_FR_BKOFF_DIS 0x00200000
577#define AR_D_MISC_VIT_COL_CW_BKOFF_EN 0x00400000
578#define AR_D_MISC_BLOWN_IFS_RETRY_EN 0x00800000
579#define AR_D_MISC_RESV0 0xFF000000
580
581#define AR_D_SEQNUM 0x1140
582
583#define AR_D_GBL_IFS_SIFS 0x1030
584#define AR_D_GBL_IFS_SIFS_M 0x0000FFFF
Vivek Natarajan04dc8822009-07-15 08:51:17 +0530585#define AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR 0x000003AB
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700586#define AR_D_GBL_IFS_SIFS_RESV0 0xFFFFFFFF
587
588#define AR_D_TXBLK_BASE 0x1038
589#define AR_D_TXBLK_WRITE_BITMASK 0x0000FFFF
590#define AR_D_TXBLK_WRITE_BITMASK_S 0
591#define AR_D_TXBLK_WRITE_SLICE 0x000F0000
592#define AR_D_TXBLK_WRITE_SLICE_S 16
593#define AR_D_TXBLK_WRITE_DCU 0x00F00000
594#define AR_D_TXBLK_WRITE_DCU_S 20
595#define AR_D_TXBLK_WRITE_COMMAND 0x0F000000
596#define AR_D_TXBLK_WRITE_COMMAND_S 24
597
598#define AR_D_GBL_IFS_SLOT 0x1070
599#define AR_D_GBL_IFS_SLOT_M 0x0000FFFF
600#define AR_D_GBL_IFS_SLOT_RESV0 0xFFFF0000
Vivek Natarajan04dc8822009-07-15 08:51:17 +0530601#define AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR 0x00000420
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700602
603#define AR_D_GBL_IFS_EIFS 0x10b0
604#define AR_D_GBL_IFS_EIFS_M 0x0000FFFF
605#define AR_D_GBL_IFS_EIFS_RESV0 0xFFFF0000
Vivek Natarajan04dc8822009-07-15 08:51:17 +0530606#define AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR 0x0000A5EB
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700607
608#define AR_D_GBL_IFS_MISC 0x10f0
609#define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL 0x00000007
610#define AR_D_GBL_IFS_MISC_TURBO_MODE 0x00000008
611#define AR_D_GBL_IFS_MISC_USEC_DURATION 0x000FFC00
612#define AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY 0x00300000
613#define AR_D_GBL_IFS_MISC_RANDOM_LFSR_SLICE_DIS 0x01000000
614#define AR_D_GBL_IFS_MISC_SLOT_XMIT_WIND_LEN 0x06000000
615#define AR_D_GBL_IFS_MISC_FORCE_XMIT_SLOT_BOUND 0x08000000
616#define AR_D_GBL_IFS_MISC_IGNORE_BACKOFF 0x10000000
617
618#define AR_D_FPCTL 0x1230
619#define AR_D_FPCTL_DCU 0x0000000F
620#define AR_D_FPCTL_DCU_S 0
621#define AR_D_FPCTL_PREFETCH_EN 0x00000010
622#define AR_D_FPCTL_BURST_PREFETCH 0x00007FE0
623#define AR_D_FPCTL_BURST_PREFETCH_S 5
624
625#define AR_D_TXPSE 0x1270
626#define AR_D_TXPSE_CTRL 0x000003FF
627#define AR_D_TXPSE_RESV0 0x0000FC00
628#define AR_D_TXPSE_STATUS 0x00010000
629#define AR_D_TXPSE_RESV1 0xFFFE0000
630
631#define AR_D_TXSLOTMASK 0x12f0
632#define AR_D_TXSLOTMASK_NUM 0x0000000F
633
634#define AR_CFG_LED 0x1f04
635#define AR_CFG_SCLK_RATE_IND 0x00000003
636#define AR_CFG_SCLK_RATE_IND_S 0
637#define AR_CFG_SCLK_32MHZ 0x00000000
638#define AR_CFG_SCLK_4MHZ 0x00000001
639#define AR_CFG_SCLK_1MHZ 0x00000002
640#define AR_CFG_SCLK_32KHZ 0x00000003
641#define AR_CFG_LED_BLINK_SLOW 0x00000008
642#define AR_CFG_LED_BLINK_THRESH_SEL 0x00000070
643#define AR_CFG_LED_MODE_SEL 0x00000380
644#define AR_CFG_LED_MODE_SEL_S 7
645#define AR_CFG_LED_POWER 0x00000280
646#define AR_CFG_LED_POWER_S 7
647#define AR_CFG_LED_NETWORK 0x00000300
648#define AR_CFG_LED_NETWORK_S 7
649#define AR_CFG_LED_MODE_PROP 0x0
650#define AR_CFG_LED_MODE_RPROP 0x1
651#define AR_CFG_LED_MODE_SPLIT 0x2
652#define AR_CFG_LED_MODE_RAND 0x3
653#define AR_CFG_LED_MODE_POWER_OFF 0x4
654#define AR_CFG_LED_MODE_POWER_ON 0x5
655#define AR_CFG_LED_MODE_NETWORK_OFF 0x4
656#define AR_CFG_LED_MODE_NETWORK_ON 0x6
657#define AR_CFG_LED_ASSOC_CTL 0x00000c00
658#define AR_CFG_LED_ASSOC_CTL_S 10
659#define AR_CFG_LED_ASSOC_NONE 0x0
660#define AR_CFG_LED_ASSOC_ACTIVE 0x1
661#define AR_CFG_LED_ASSOC_PENDING 0x2
662
663#define AR_CFG_LED_BLINK_SLOW 0x00000008
664#define AR_CFG_LED_BLINK_SLOW_S 3
665
666#define AR_CFG_LED_BLINK_THRESH_SEL 0x00000070
667#define AR_CFG_LED_BLINK_THRESH_SEL_S 4
668
669#define AR_MAC_SLEEP 0x1f00
670#define AR_MAC_SLEEP_MAC_AWAKE 0x00000000
671#define AR_MAC_SLEEP_MAC_ASLEEP 0x00000001
672
673#define AR_RC 0x4000
674#define AR_RC_AHB 0x00000001
675#define AR_RC_APB 0x00000002
676#define AR_RC_HOSTIF 0x00000100
677
Senthil Balasubramanian02e90d62008-12-08 19:43:46 +0530678#define AR_WA 0x4004
Vivek Natarajan93b1b372009-09-17 09:24:58 +0530679#define AR_WA_D3_L1_DISABLE (1 << 14)
Senthil Balasubramanian02e90d62008-12-08 19:43:46 +0530680#define AR9285_WA_DEFAULT 0x004a05cb
Vivek Natarajan93b1b372009-09-17 09:24:58 +0530681#define AR9280_WA_DEFAULT 0x0040073b
Senthil Balasubramanian02e90d62008-12-08 19:43:46 +0530682#define AR_WA_DEFAULT 0x0000073f
683
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700684
685#define AR_PM_STATE 0x4008
686#define AR_PM_STATE_PME_D3COLD_VAUX 0x00100000
687
688#define AR_HOST_TIMEOUT 0x4018
689#define AR_HOST_TIMEOUT_APB_CNTR 0x0000FFFF
690#define AR_HOST_TIMEOUT_APB_CNTR_S 0
691#define AR_HOST_TIMEOUT_LCL_CNTR 0xFFFF0000
692#define AR_HOST_TIMEOUT_LCL_CNTR_S 16
693
694#define AR_EEPROM 0x401c
695#define AR_EEPROM_ABSENT 0x00000100
696#define AR_EEPROM_CORRUPT 0x00000200
697#define AR_EEPROM_PROT_MASK 0x03FFFC00
698#define AR_EEPROM_PROT_MASK_S 10
699
700#define EEPROM_PROTECT_RP_0_31 0x0001
701#define EEPROM_PROTECT_WP_0_31 0x0002
702#define EEPROM_PROTECT_RP_32_63 0x0004
703#define EEPROM_PROTECT_WP_32_63 0x0008
704#define EEPROM_PROTECT_RP_64_127 0x0010
705#define EEPROM_PROTECT_WP_64_127 0x0020
706#define EEPROM_PROTECT_RP_128_191 0x0040
707#define EEPROM_PROTECT_WP_128_191 0x0080
708#define EEPROM_PROTECT_RP_192_255 0x0100
709#define EEPROM_PROTECT_WP_192_255 0x0200
710#define EEPROM_PROTECT_RP_256_511 0x0400
711#define EEPROM_PROTECT_WP_256_511 0x0800
712#define EEPROM_PROTECT_RP_512_1023 0x1000
713#define EEPROM_PROTECT_WP_512_1023 0x2000
714#define EEPROM_PROTECT_RP_1024_2047 0x4000
715#define EEPROM_PROTECT_WP_1024_2047 0x8000
716
717#define AR_SREV \
718 ((AR_SREV_9100(ah)) ? 0x0600 : 0x4020)
719
720#define AR_SREV_ID \
721 ((AR_SREV_9100(ah)) ? 0x00000FFF : 0x000000FF)
722#define AR_SREV_VERSION 0x000000F0
723#define AR_SREV_VERSION_S 4
724#define AR_SREV_REVISION 0x00000007
725
726#define AR_SREV_ID2 0xFFFFFFFF
727#define AR_SREV_VERSION2 0xFFFC0000
728#define AR_SREV_VERSION2_S 18
729#define AR_SREV_TYPE2 0x0003F000
730#define AR_SREV_TYPE2_S 12
731#define AR_SREV_TYPE2_CHAIN 0x00001000
732#define AR_SREV_TYPE2_HOST_MODE 0x00002000
733#define AR_SREV_REVISION2 0x00000F00
734#define AR_SREV_REVISION2_S 8
735
736#define AR_SREV_VERSION_5416_PCI 0xD
737#define AR_SREV_VERSION_5416_PCIE 0xC
738#define AR_SREV_REVISION_5416_10 0
739#define AR_SREV_REVISION_5416_20 1
740#define AR_SREV_REVISION_5416_22 2
Gabor Juhosd4376eb2009-03-06 09:08:52 +0100741#define AR_SREV_VERSION_9100 0x14
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700742#define AR_SREV_VERSION_9160 0x40
743#define AR_SREV_REVISION_9160_10 0
744#define AR_SREV_REVISION_9160_11 1
745#define AR_SREV_VERSION_9280 0x80
746#define AR_SREV_REVISION_9280_10 0
747#define AR_SREV_REVISION_9280_20 1
748#define AR_SREV_REVISION_9280_21 2
749#define AR_SREV_VERSION_9285 0xC0
750#define AR_SREV_REVISION_9285_10 0
Senthil Balasubramanian02e90d62008-12-08 19:43:46 +0530751#define AR_SREV_REVISION_9285_11 1
752#define AR_SREV_REVISION_9285_12 2
Vivek Natarajan04dc8822009-07-15 08:51:17 +0530753#define AR_SREV_VERSION_9287 0x180
754#define AR_SREV_REVISION_9287_10 0
755#define AR_SREV_REVISION_9287_11 1
Vivek Natarajan326bebb2009-08-14 11:33:36 +0530756#define AR_SREV_REVISION_9287_12 2
Luis R. Rodriguezedb1f912009-08-03 23:14:10 -0400757#define AR_SREV_VERSION_9271 0x140
758#define AR_SREV_REVISION_9271_10 0
759#define AR_SREV_REVISION_9271_11 1
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700760
Gabor Juhosa8c96d32009-03-06 09:08:51 +0100761#define AR_SREV_5416(_ah) \
762 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \
763 ((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE))
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700764#define AR_SREV_5416_20_OR_LATER(_ah) \
Gabor Juhosa8c96d32009-03-06 09:08:51 +0100765 (((AR_SREV_5416(_ah)) && \
766 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_5416_20)) || \
767 ((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9100))
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700768#define AR_SREV_5416_22_OR_LATER(_ah) \
Gabor Juhosa8c96d32009-03-06 09:08:51 +0100769 (((AR_SREV_5416(_ah)) && \
770 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_5416_22)) || \
771 ((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9100))
772
Gabor Juhosd4376eb2009-03-06 09:08:52 +0100773#define AR_SREV_9100(ah) \
774 ((ah->hw_version.macVersion) == AR_SREV_VERSION_9100)
775#define AR_SREV_9100_OR_LATER(_ah) \
Gabor Juhos6b765de2009-03-06 09:08:53 +0100776 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9100))
Gabor Juhosd4376eb2009-03-06 09:08:52 +0100777
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700778#define AR_SREV_9160(_ah) \
Sujithd535a422009-02-09 13:27:06 +0530779 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9160))
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700780#define AR_SREV_9160_10_OR_LATER(_ah) \
Sujithd535a422009-02-09 13:27:06 +0530781 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9160))
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700782#define AR_SREV_9160_11(_ah) \
Sujithd535a422009-02-09 13:27:06 +0530783 (AR_SREV_9160(_ah) && \
784 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9160_11))
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700785#define AR_SREV_9280(_ah) \
Sujithd535a422009-02-09 13:27:06 +0530786 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280))
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700787#define AR_SREV_9280_10_OR_LATER(_ah) \
Sujithd535a422009-02-09 13:27:06 +0530788 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9280))
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700789#define AR_SREV_9280_20(_ah) \
Sujithd535a422009-02-09 13:27:06 +0530790 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280) && \
791 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9280_20))
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700792#define AR_SREV_9280_20_OR_LATER(_ah) \
Sujithd535a422009-02-09 13:27:06 +0530793 (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9280) || \
794 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280) && \
795 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9280_20)))
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700796
Sujithd535a422009-02-09 13:27:06 +0530797#define AR_SREV_9285(_ah) \
798 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9285))
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700799#define AR_SREV_9285_10_OR_LATER(_ah) \
Sujithd535a422009-02-09 13:27:06 +0530800 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9285))
Senthil Balasubramanian02e90d62008-12-08 19:43:46 +0530801#define AR_SREV_9285_11(_ah) \
Senthil Balasubramanian978b5322009-03-06 11:24:11 +0530802 (AR_SREV_9285(ah) && \
Sujithd535a422009-02-09 13:27:06 +0530803 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9285_11))
Senthil Balasubramanian02e90d62008-12-08 19:43:46 +0530804#define AR_SREV_9285_11_OR_LATER(_ah) \
Sujithd535a422009-02-09 13:27:06 +0530805 (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9285) || \
806 (AR_SREV_9285(ah) && ((_ah)->hw_version.macRev >= \
807 AR_SREV_REVISION_9285_11)))
Senthil Balasubramanian02e90d62008-12-08 19:43:46 +0530808#define AR_SREV_9285_12(_ah) \
Senthil Balasubramanian978b5322009-03-06 11:24:11 +0530809 (AR_SREV_9285(ah) && \
Sujithd535a422009-02-09 13:27:06 +0530810 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9285_12))
Senthil Balasubramanian02e90d62008-12-08 19:43:46 +0530811#define AR_SREV_9285_12_OR_LATER(_ah) \
Sujithd535a422009-02-09 13:27:06 +0530812 (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9285) || \
813 (AR_SREV_9285(ah) && ((_ah)->hw_version.macRev >= \
814 AR_SREV_REVISION_9285_12)))
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700815
Vivek Natarajan04dc8822009-07-15 08:51:17 +0530816#define AR_SREV_9287(_ah) \
817 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287))
818#define AR_SREV_9287_10_OR_LATER(_ah) \
819 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9287))
820#define AR_SREV_9287_10(_ah) \
821 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \
822 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9287_10))
823#define AR_SREV_9287_11(_ah) \
824 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \
825 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9287_11))
826#define AR_SREV_9287_11_OR_LATER(_ah) \
827 (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9287) || \
828 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \
829 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9287_11)))
Vivek Natarajan326bebb2009-08-14 11:33:36 +0530830#define AR_SREV_9287_12(_ah) \
831 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \
832 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9287_12))
833#define AR_SREV_9287_12_OR_LATER(_ah) \
834 (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9287) || \
835 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \
836 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9287_12)))
Luis R. Rodriguezedb1f912009-08-03 23:14:10 -0400837#define AR_SREV_9271(_ah) \
838 (((_ah))->hw_version.macVersion == AR_SREV_VERSION_9271)
839#define AR_SREV_9271_10(_ah) \
840 (AR_SREV_9271(_ah) && \
841 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9271_10))
842#define AR_SREV_9271_11(_ah) \
843 (AR_SREV_9271(_ah) && \
844 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9271_11))
845
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700846#define AR_RADIO_SREV_MAJOR 0xf0
847#define AR_RAD5133_SREV_MAJOR 0xc0
848#define AR_RAD2133_SREV_MAJOR 0xd0
849#define AR_RAD5122_SREV_MAJOR 0xe0
850#define AR_RAD2122_SREV_MAJOR 0xf0
851
852#define AR_AHB_MODE 0x4024
853#define AR_AHB_EXACT_WR_EN 0x00000000
854#define AR_AHB_BUF_WR_EN 0x00000001
855#define AR_AHB_EXACT_RD_EN 0x00000000
856#define AR_AHB_CACHELINE_RD_EN 0x00000002
857#define AR_AHB_PREFETCH_RD_EN 0x00000004
858#define AR_AHB_PAGE_SIZE_1K 0x00000000
859#define AR_AHB_PAGE_SIZE_2K 0x00000008
860#define AR_AHB_PAGE_SIZE_4K 0x00000010
Vivek Natarajan04dc8822009-07-15 08:51:17 +0530861#define AR_AHB_CUSTOM_BURST_EN 0x000000C0
862#define AR_AHB_CUSTOM_BURST_EN_S 6
863#define AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL 3
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700864
865#define AR_INTR_RTC_IRQ 0x00000001
866#define AR_INTR_MAC_IRQ 0x00000002
867#define AR_INTR_EEP_PROT_ACCESS 0x00000004
868#define AR_INTR_MAC_AWAKE 0x00020000
869#define AR_INTR_MAC_ASLEEP 0x00040000
870#define AR_INTR_SPURIOUS 0xFFFFFFFF
871
872
873#define AR_INTR_SYNC_CAUSE_CLR 0x4028
874
875#define AR_INTR_SYNC_CAUSE 0x4028
876
877#define AR_INTR_SYNC_ENABLE 0x402c
878#define AR_INTR_SYNC_ENABLE_GPIO 0xFFFC0000
879#define AR_INTR_SYNC_ENABLE_GPIO_S 18
880
881enum {
882 AR_INTR_SYNC_RTC_IRQ = 0x00000001,
883 AR_INTR_SYNC_MAC_IRQ = 0x00000002,
884 AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS = 0x00000004,
885 AR_INTR_SYNC_APB_TIMEOUT = 0x00000008,
886 AR_INTR_SYNC_PCI_MODE_CONFLICT = 0x00000010,
887 AR_INTR_SYNC_HOST1_FATAL = 0x00000020,
888 AR_INTR_SYNC_HOST1_PERR = 0x00000040,
889 AR_INTR_SYNC_TRCV_FIFO_PERR = 0x00000080,
890 AR_INTR_SYNC_RADM_CPL_EP = 0x00000100,
891 AR_INTR_SYNC_RADM_CPL_DLLP_ABORT = 0x00000200,
892 AR_INTR_SYNC_RADM_CPL_TLP_ABORT = 0x00000400,
893 AR_INTR_SYNC_RADM_CPL_ECRC_ERR = 0x00000800,
894 AR_INTR_SYNC_RADM_CPL_TIMEOUT = 0x00001000,
895 AR_INTR_SYNC_LOCAL_TIMEOUT = 0x00002000,
896 AR_INTR_SYNC_PM_ACCESS = 0x00004000,
897 AR_INTR_SYNC_MAC_AWAKE = 0x00008000,
898 AR_INTR_SYNC_MAC_ASLEEP = 0x00010000,
899 AR_INTR_SYNC_MAC_SLEEP_ACCESS = 0x00020000,
900 AR_INTR_SYNC_ALL = 0x0003FFFF,
901
902
903 AR_INTR_SYNC_DEFAULT = (AR_INTR_SYNC_HOST1_FATAL |
904 AR_INTR_SYNC_HOST1_PERR |
905 AR_INTR_SYNC_RADM_CPL_EP |
906 AR_INTR_SYNC_RADM_CPL_DLLP_ABORT |
907 AR_INTR_SYNC_RADM_CPL_TLP_ABORT |
908 AR_INTR_SYNC_RADM_CPL_ECRC_ERR |
909 AR_INTR_SYNC_RADM_CPL_TIMEOUT |
910 AR_INTR_SYNC_LOCAL_TIMEOUT |
911 AR_INTR_SYNC_MAC_SLEEP_ACCESS),
912
913 AR_INTR_SYNC_SPURIOUS = 0xFFFFFFFF,
914
915};
916
917#define AR_INTR_ASYNC_MASK 0x4030
918#define AR_INTR_ASYNC_MASK_GPIO 0xFFFC0000
919#define AR_INTR_ASYNC_MASK_GPIO_S 18
920
921#define AR_INTR_SYNC_MASK 0x4034
922#define AR_INTR_SYNC_MASK_GPIO 0xFFFC0000
923#define AR_INTR_SYNC_MASK_GPIO_S 18
924
925#define AR_INTR_ASYNC_CAUSE_CLR 0x4038
926#define AR_INTR_ASYNC_CAUSE 0x4038
927
928#define AR_INTR_ASYNC_ENABLE 0x403c
929#define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000
930#define AR_INTR_ASYNC_ENABLE_GPIO_S 18
931
932#define AR_PCIE_SERDES 0x4040
933#define AR_PCIE_SERDES2 0x4044
934#define AR_PCIE_PM_CTRL 0x4014
935#define AR_PCIE_PM_CTRL_ENA 0x00080000
936
937#define AR_NUM_GPIO 14
938#define AR928X_NUM_GPIO 10
Senthil Balasubramaniancb33c412008-12-24 18:03:58 +0530939#define AR9285_NUM_GPIO 12
Vivek Natarajan04dc8822009-07-15 08:51:17 +0530940#define AR9287_NUM_GPIO 11
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700941
942#define AR_GPIO_IN_OUT 0x4048
943#define AR_GPIO_IN_VAL 0x0FFFC000
944#define AR_GPIO_IN_VAL_S 14
945#define AR928X_GPIO_IN_VAL 0x000FFC00
946#define AR928X_GPIO_IN_VAL_S 10
Senthil Balasubramaniancb33c412008-12-24 18:03:58 +0530947#define AR9285_GPIO_IN_VAL 0x00FFF000
948#define AR9285_GPIO_IN_VAL_S 12
Vivek Natarajan04dc8822009-07-15 08:51:17 +0530949#define AR9287_GPIO_IN_VAL 0x003FF800
950#define AR9287_GPIO_IN_VAL_S 11
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700951
952#define AR_GPIO_OE_OUT 0x404c
953#define AR_GPIO_OE_OUT_DRV 0x3
954#define AR_GPIO_OE_OUT_DRV_NO 0x0
955#define AR_GPIO_OE_OUT_DRV_LOW 0x1
956#define AR_GPIO_OE_OUT_DRV_HI 0x2
957#define AR_GPIO_OE_OUT_DRV_ALL 0x3
958
959#define AR_GPIO_INTR_POL 0x4050
960#define AR_GPIO_INTR_POL_VAL 0x00001FFF
961#define AR_GPIO_INTR_POL_VAL_S 0
962
963#define AR_GPIO_INPUT_EN_VAL 0x4054
Vasanthakumar Thiagarajanc97c92d2009-01-02 15:35:46 +0530964#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF 0x00000004
965#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_S 2
966#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF 0x00000008
967#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_S 3
968#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_DEF 0x00000010
969#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_S 4
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700970#define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF 0x00000080
971#define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF_S 7
Vasanthakumar Thiagarajanc97c92d2009-01-02 15:35:46 +0530972#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB 0x00001000
973#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB_S 12
Vasanthakumar Thiagarajan17739122009-08-26 21:08:50 +0530974#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB 0x00001000
975#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB_S 1
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700976#define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB 0x00008000
977#define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB_S 15
978#define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000
979#define AR_GPIO_JTAG_DISABLE 0x00020000
980
981#define AR_GPIO_INPUT_MUX1 0x4058
Vasanthakumar Thiagarajanc97c92d2009-01-02 15:35:46 +0530982#define AR_GPIO_INPUT_MUX1_BT_ACTIVE 0x000f0000
983#define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S 16
Vasanthakumar Thiagarajan17739122009-08-26 21:08:50 +0530984#define AR_GPIO_INPUT_MUX1_BT_PRIORITY 0x00000f00
985#define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S 8
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700986
987#define AR_GPIO_INPUT_MUX2 0x405c
988#define AR_GPIO_INPUT_MUX2_CLK25 0x0000000f
989#define AR_GPIO_INPUT_MUX2_CLK25_S 0
990#define AR_GPIO_INPUT_MUX2_RFSILENT 0x000000f0
991#define AR_GPIO_INPUT_MUX2_RFSILENT_S 4
992#define AR_GPIO_INPUT_MUX2_RTC_RESET 0x00000f00
993#define AR_GPIO_INPUT_MUX2_RTC_RESET_S 8
994
995#define AR_GPIO_OUTPUT_MUX1 0x4060
996#define AR_GPIO_OUTPUT_MUX2 0x4064
997#define AR_GPIO_OUTPUT_MUX3 0x4068
998
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700999#define AR_INPUT_STATE 0x406c
1000
1001#define AR_EEPROM_STATUS_DATA 0x407c
1002#define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff
1003#define AR_EEPROM_STATUS_DATA_VAL_S 0
1004#define AR_EEPROM_STATUS_DATA_BUSY 0x00010000
1005#define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000
1006#define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000
1007#define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000
1008
1009#define AR_OBS 0x4080
1010
Vasanthakumar Thiagarajan17739122009-08-26 21:08:50 +05301011#define AR_GPIO_PDPU 0x4088
1012
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001013#define AR_PCIE_MSI 0x4094
1014#define AR_PCIE_MSI_ENABLE 0x00000001
1015
1016
1017#define AR_RTC_9160_PLL_DIV 0x000003ff
1018#define AR_RTC_9160_PLL_DIV_S 0
1019#define AR_RTC_9160_PLL_REFDIV 0x00003C00
1020#define AR_RTC_9160_PLL_REFDIV_S 10
1021#define AR_RTC_9160_PLL_CLKSEL 0x0000C000
1022#define AR_RTC_9160_PLL_CLKSEL_S 14
1023
1024#define AR_RTC_BASE 0x00020000
1025#define AR_RTC_RC \
Gabor Juhosd03a66c2009-01-14 20:17:09 +01001026 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0000) : 0x7000)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001027#define AR_RTC_RC_M 0x00000003
1028#define AR_RTC_RC_MAC_WARM 0x00000001
1029#define AR_RTC_RC_MAC_COLD 0x00000002
1030#define AR_RTC_RC_COLD_RESET 0x00000004
1031#define AR_RTC_RC_WARM_RESET 0x00000008
1032
1033#define AR_RTC_PLL_CONTROL \
Gabor Juhosd03a66c2009-01-14 20:17:09 +01001034 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0014) : 0x7014)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001035
1036#define AR_RTC_PLL_DIV 0x0000001f
1037#define AR_RTC_PLL_DIV_S 0
1038#define AR_RTC_PLL_DIV2 0x00000020
1039#define AR_RTC_PLL_REFDIV_5 0x000000c0
1040#define AR_RTC_PLL_CLKSEL 0x00000300
1041#define AR_RTC_PLL_CLKSEL_S 8
1042
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001043#define AR_RTC_RESET \
1044 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0040) : 0x7040)
1045#define AR_RTC_RESET_EN (0x00000001)
1046
1047#define AR_RTC_STATUS \
1048 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0044) : 0x7044)
1049
1050#define AR_RTC_STATUS_M \
1051 ((AR_SREV_9100(ah)) ? 0x0000003f : 0x0000000f)
1052
1053#define AR_RTC_PM_STATUS_M 0x0000000f
1054
1055#define AR_RTC_STATUS_SHUTDOWN 0x00000001
1056#define AR_RTC_STATUS_ON 0x00000002
1057#define AR_RTC_STATUS_SLEEP 0x00000004
1058#define AR_RTC_STATUS_WAKEUP 0x00000008
1059
1060#define AR_RTC_SLEEP_CLK \
1061 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0048) : 0x7048)
1062#define AR_RTC_FORCE_DERIVED_CLK 0x2
1063
1064#define AR_RTC_FORCE_WAKE \
1065 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x004c) : 0x704c)
1066#define AR_RTC_FORCE_WAKE_EN 0x00000001
1067#define AR_RTC_FORCE_WAKE_ON_INT 0x00000002
1068
1069
1070#define AR_RTC_INTR_CAUSE \
1071 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0050) : 0x7050)
1072
1073#define AR_RTC_INTR_ENABLE \
1074 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0054) : 0x7054)
1075
1076#define AR_RTC_INTR_MASK \
1077 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0058) : 0x7058)
1078
Sujith70768492009-02-16 13:23:12 +05301079/* RTC_DERIVED_* - only for AR9100 */
1080
1081#define AR_RTC_DERIVED_CLK (AR_RTC_BASE + 0x0038)
1082#define AR_RTC_DERIVED_CLK_PERIOD 0x0000fffe
1083#define AR_RTC_DERIVED_CLK_PERIOD_S 1
1084
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001085#define AR_SEQ_MASK 0x8060
1086
1087#define AR_AN_RF2G1_CH0 0x7810
1088#define AR_AN_RF2G1_CH0_OB 0x03800000
1089#define AR_AN_RF2G1_CH0_OB_S 23
1090#define AR_AN_RF2G1_CH0_DB 0x1C000000
1091#define AR_AN_RF2G1_CH0_DB_S 26
1092
1093#define AR_AN_RF5G1_CH0 0x7818
1094#define AR_AN_RF5G1_CH0_OB5 0x00070000
1095#define AR_AN_RF5G1_CH0_OB5_S 16
1096#define AR_AN_RF5G1_CH0_DB5 0x00380000
1097#define AR_AN_RF5G1_CH0_DB5_S 19
1098
1099#define AR_AN_RF2G1_CH1 0x7834
1100#define AR_AN_RF2G1_CH1_OB 0x03800000
1101#define AR_AN_RF2G1_CH1_OB_S 23
1102#define AR_AN_RF2G1_CH1_DB 0x1C000000
1103#define AR_AN_RF2G1_CH1_DB_S 26
1104
1105#define AR_AN_RF5G1_CH1 0x783C
1106#define AR_AN_RF5G1_CH1_OB5 0x00070000
1107#define AR_AN_RF5G1_CH1_OB5_S 16
1108#define AR_AN_RF5G1_CH1_DB5 0x00380000
1109#define AR_AN_RF5G1_CH1_DB5_S 19
1110
Senthil Balasubramaniancb33c412008-12-24 18:03:58 +05301111#define AR_AN_TOP1 0x7890
1112#define AR_AN_TOP1_DACIPMODE 0x00040000
1113#define AR_AN_TOP1_DACIPMODE_S 18
1114
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001115#define AR_AN_TOP2 0x7894
1116#define AR_AN_TOP2_XPABIAS_LVL 0xC0000000
1117#define AR_AN_TOP2_XPABIAS_LVL_S 30
1118#define AR_AN_TOP2_LOCALBIAS 0x00200000
1119#define AR_AN_TOP2_LOCALBIAS_S 21
1120#define AR_AN_TOP2_PWDCLKIND 0x00400000
1121#define AR_AN_TOP2_PWDCLKIND_S 22
1122
1123#define AR_AN_SYNTH9 0x7868
1124#define AR_AN_SYNTH9_REFDIVA 0xf8000000
1125#define AR_AN_SYNTH9_REFDIVA_S 27
1126
Senthil Balasubramanian02e90d62008-12-08 19:43:46 +05301127#define AR9285_AN_RF2G1 0x7820
1128#define AR9285_AN_RF2G1_ENPACAL 0x00000800
1129#define AR9285_AN_RF2G1_ENPACAL_S 11
1130#define AR9285_AN_RF2G1_PDPADRV1 0x02000000
1131#define AR9285_AN_RF2G1_PDPADRV1_S 25
1132#define AR9285_AN_RF2G1_PDPADRV2 0x01000000
1133#define AR9285_AN_RF2G1_PDPADRV2_S 24
1134#define AR9285_AN_RF2G1_PDPAOUT 0x00800000
1135#define AR9285_AN_RF2G1_PDPAOUT_S 23
1136
1137
1138#define AR9285_AN_RF2G2 0x7824
1139#define AR9285_AN_RF2G2_OFFCAL 0x00001000
1140#define AR9285_AN_RF2G2_OFFCAL_S 12
1141
1142#define AR9285_AN_RF2G3 0x7828
1143#define AR9285_AN_RF2G3_PDVCCOMP 0x02000000
1144#define AR9285_AN_RF2G3_PDVCCOMP_S 25
1145#define AR9285_AN_RF2G3_OB_0 0x00E00000
1146#define AR9285_AN_RF2G3_OB_0_S 21
1147#define AR9285_AN_RF2G3_OB_1 0x001C0000
1148#define AR9285_AN_RF2G3_OB_1_S 18
1149#define AR9285_AN_RF2G3_OB_2 0x00038000
1150#define AR9285_AN_RF2G3_OB_2_S 15
1151#define AR9285_AN_RF2G3_OB_3 0x00007000
1152#define AR9285_AN_RF2G3_OB_3_S 12
1153#define AR9285_AN_RF2G3_OB_4 0x00000E00
1154#define AR9285_AN_RF2G3_OB_4_S 9
1155
1156#define AR9285_AN_RF2G3_DB1_0 0x000001C0
1157#define AR9285_AN_RF2G3_DB1_0_S 6
1158#define AR9285_AN_RF2G3_DB1_1 0x00000038
1159#define AR9285_AN_RF2G3_DB1_1_S 3
1160#define AR9285_AN_RF2G3_DB1_2 0x00000007
1161#define AR9285_AN_RF2G3_DB1_2_S 0
1162#define AR9285_AN_RF2G4 0x782C
1163#define AR9285_AN_RF2G4_DB1_3 0xE0000000
1164#define AR9285_AN_RF2G4_DB1_3_S 29
1165#define AR9285_AN_RF2G4_DB1_4 0x1C000000
1166#define AR9285_AN_RF2G4_DB1_4_S 26
1167
1168#define AR9285_AN_RF2G4_DB2_0 0x03800000
1169#define AR9285_AN_RF2G4_DB2_0_S 23
1170#define AR9285_AN_RF2G4_DB2_1 0x00700000
1171#define AR9285_AN_RF2G4_DB2_1_S 20
1172#define AR9285_AN_RF2G4_DB2_2 0x000E0000
1173#define AR9285_AN_RF2G4_DB2_2_S 17
1174#define AR9285_AN_RF2G4_DB2_3 0x0001C000
1175#define AR9285_AN_RF2G4_DB2_3_S 14
1176#define AR9285_AN_RF2G4_DB2_4 0x00003800
1177#define AR9285_AN_RF2G4_DB2_4_S 11
1178
Luis R. Rodriguez670388c2009-08-03 23:14:11 -04001179/* AR9271 : 0x7828, 0x782c different setting from AR9285 */
1180#define AR9271_AN_RF2G3_OB_cck 0x001C0000
1181#define AR9271_AN_RF2G3_OB_cck_S 18
1182#define AR9271_AN_RF2G3_OB_psk 0x00038000
1183#define AR9271_AN_RF2G3_OB_psk_S 15
1184#define AR9271_AN_RF2G3_OB_qam 0x00007000
1185#define AR9271_AN_RF2G3_OB_qam_S 12
1186
1187#define AR9271_AN_RF2G3_DB_1 0x00E00000
1188#define AR9271_AN_RF2G3_DB_1_S 21
1189
1190#define AR9271_AN_RF2G3_CCOMP 0xFFF
1191#define AR9271_AN_RF2G3_CCOMP_S 0
1192
1193#define AR9271_AN_RF2G4_DB_2 0xE0000000
1194#define AR9271_AN_RF2G4_DB_2_S 29
1195
Senthil Balasubramanian02e90d62008-12-08 19:43:46 +05301196#define AR9285_AN_RF2G6 0x7834
1197#define AR9285_AN_RF2G6_CCOMP 0x00007800
1198#define AR9285_AN_RF2G6_CCOMP_S 11
1199#define AR9285_AN_RF2G6_OFFS 0x03f00000
1200#define AR9285_AN_RF2G6_OFFS_S 20
1201
Luis R. Rodriguez670388c2009-08-03 23:14:11 -04001202#define AR9271_AN_RF2G6_OFFS 0x07f00000
1203#define AR9271_AN_RF2G6_OFFS_S 20
1204
Senthil Balasubramanian02e90d62008-12-08 19:43:46 +05301205#define AR9285_AN_RF2G7 0x7838
1206#define AR9285_AN_RF2G7_PWDDB 0x00000002
1207#define AR9285_AN_RF2G7_PWDDB_S 1
1208#define AR9285_AN_RF2G7_PADRVGN2TAB0 0xE0000000
1209#define AR9285_AN_RF2G7_PADRVGN2TAB0_S 29
1210
1211#define AR9285_AN_RF2G8 0x783C
1212#define AR9285_AN_RF2G8_PADRVGN2TAB0 0x0001C000
1213#define AR9285_AN_RF2G8_PADRVGN2TAB0_S 14
1214
1215
1216#define AR9285_AN_RF2G9 0x7840
1217#define AR9285_AN_RXTXBB1 0x7854
1218#define AR9285_AN_RXTXBB1_PDRXTXBB1 0x00000020
1219#define AR9285_AN_RXTXBB1_PDRXTXBB1_S 5
1220#define AR9285_AN_RXTXBB1_PDV2I 0x00000080
1221#define AR9285_AN_RXTXBB1_PDV2I_S 7
1222#define AR9285_AN_RXTXBB1_PDDACIF 0x00000100
1223#define AR9285_AN_RXTXBB1_PDDACIF_S 8
1224#define AR9285_AN_RXTXBB1_SPARE9 0x00000001
1225#define AR9285_AN_RXTXBB1_SPARE9_S 0
1226
1227#define AR9285_AN_TOP2 0x7868
1228
1229#define AR9285_AN_TOP3 0x786c
1230#define AR9285_AN_TOP3_XPABIAS_LVL 0x0000000C
1231#define AR9285_AN_TOP3_XPABIAS_LVL_S 2
1232#define AR9285_AN_TOP3_PWDDAC 0x00800000
1233#define AR9285_AN_TOP3_PWDDAC_S 23
1234
1235#define AR9285_AN_TOP4 0x7870
1236#define AR9285_AN_TOP4_DEFAULT 0x10142c00
1237
Vivek Natarajan04dc8822009-07-15 08:51:17 +05301238#define AR9287_AN_RF2G3_CH0 0x7808
1239#define AR9287_AN_RF2G3_CH1 0x785c
1240#define AR9287_AN_RF2G3_DB1 0xE0000000
1241#define AR9287_AN_RF2G3_DB1_S 29
1242#define AR9287_AN_RF2G3_DB2 0x1C000000
1243#define AR9287_AN_RF2G3_DB2_S 26
1244#define AR9287_AN_RF2G3_OB_CCK 0x03800000
1245#define AR9287_AN_RF2G3_OB_CCK_S 23
1246#define AR9287_AN_RF2G3_OB_PSK 0x00700000
1247#define AR9287_AN_RF2G3_OB_PSK_S 20
1248#define AR9287_AN_RF2G3_OB_QAM 0x000E0000
1249#define AR9287_AN_RF2G3_OB_QAM_S 17
1250#define AR9287_AN_RF2G3_OB_PAL_OFF 0x0001C000
1251#define AR9287_AN_RF2G3_OB_PAL_OFF_S 14
1252
1253#define AR9287_AN_TXPC0 0x7898
1254#define AR9287_AN_TXPC0_TXPCMODE 0x0000C000
1255#define AR9287_AN_TXPC0_TXPCMODE_S 14
1256#define AR9287_AN_TXPC0_TXPCMODE_NORMAL 0
1257#define AR9287_AN_TXPC0_TXPCMODE_TEST 1
1258#define AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE 2
1259#define AR9287_AN_TXPC0_TXPCMODE_ATBTEST 3
1260
1261#define AR9287_AN_TOP2 0x78b4
1262#define AR9287_AN_TOP2_XPABIAS_LVL 0xC0000000
1263#define AR9287_AN_TOP2_XPABIAS_LVL_S 30
1264
Luis R. Rodriguez670388c2009-08-03 23:14:11 -04001265/* AR9271 specific stuff */
1266#define AR9271_RESET_POWER_DOWN_CONTROL 0x50044
1267#define AR9271_RADIO_RF_RST 0x20
1268#define AR9271_GATE_MAC_CTL 0x4000
1269
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001270#define AR_STA_ID0 0x8000
1271#define AR_STA_ID1 0x8004
1272#define AR_STA_ID1_SADH_MASK 0x0000FFFF
1273#define AR_STA_ID1_STA_AP 0x00010000
1274#define AR_STA_ID1_ADHOC 0x00020000
1275#define AR_STA_ID1_PWR_SAV 0x00040000
1276#define AR_STA_ID1_KSRCHDIS 0x00080000
1277#define AR_STA_ID1_PCF 0x00100000
1278#define AR_STA_ID1_USE_DEFANT 0x00200000
1279#define AR_STA_ID1_DEFANT_UPDATE 0x00400000
1280#define AR_STA_ID1_RTS_USE_DEF 0x00800000
1281#define AR_STA_ID1_ACKCTS_6MB 0x01000000
1282#define AR_STA_ID1_BASE_RATE_11B 0x02000000
1283#define AR_STA_ID1_SECTOR_SELF_GEN 0x04000000
1284#define AR_STA_ID1_CRPT_MIC_ENABLE 0x08000000
1285#define AR_STA_ID1_KSRCH_MODE 0x10000000
1286#define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000
1287#define AR_STA_ID1_CBCIV_ENDIAN 0x40000000
1288#define AR_STA_ID1_MCAST_KSRCH 0x80000000
1289
1290#define AR_BSS_ID0 0x8008
1291#define AR_BSS_ID1 0x800C
1292#define AR_BSS_ID1_U16 0x0000FFFF
1293#define AR_BSS_ID1_AID 0x07FF0000
1294#define AR_BSS_ID1_AID_S 16
1295
1296#define AR_BCN_RSSI_AVE 0x8010
1297#define AR_BCN_RSSI_AVE_MASK 0x00000FFF
1298
1299#define AR_TIME_OUT 0x8014
1300#define AR_TIME_OUT_ACK 0x00003FFF
1301#define AR_TIME_OUT_ACK_S 0
1302#define AR_TIME_OUT_CTS 0x3FFF0000
1303#define AR_TIME_OUT_CTS_S 16
Vivek Natarajan04dc8822009-07-15 08:51:17 +05301304#define AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR 0x16001D56
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001305
1306#define AR_RSSI_THR 0x8018
1307#define AR_RSSI_THR_MASK 0x000000FF
1308#define AR_RSSI_THR_BM_THR 0x0000FF00
1309#define AR_RSSI_THR_BM_THR_S 8
1310#define AR_RSSI_BCN_WEIGHT 0x1F000000
1311#define AR_RSSI_BCN_WEIGHT_S 24
1312#define AR_RSSI_BCN_RSSI_RST 0x20000000
1313
1314#define AR_USEC 0x801c
1315#define AR_USEC_USEC 0x0000007F
1316#define AR_USEC_TX_LAT 0x007FC000
1317#define AR_USEC_TX_LAT_S 14
1318#define AR_USEC_RX_LAT 0x1F800000
1319#define AR_USEC_RX_LAT_S 23
Vivek Natarajan04dc8822009-07-15 08:51:17 +05301320#define AR_USEC_ASYNC_FIFO_DUR 0x12e00074
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001321
1322#define AR_RESET_TSF 0x8020
1323#define AR_RESET_TSF_ONCE 0x01000000
1324
1325#define AR_MAX_CFP_DUR 0x8038
1326#define AR_CFP_VAL 0x0000FFFF
1327
1328#define AR_RX_FILTER 0x803C
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001329
1330#define AR_MCAST_FIL0 0x8040
1331#define AR_MCAST_FIL1 0x8044
1332
1333#define AR_DIAG_SW 0x8048
1334#define AR_DIAG_CACHE_ACK 0x00000001
1335#define AR_DIAG_ACK_DIS 0x00000002
1336#define AR_DIAG_CTS_DIS 0x00000004
1337#define AR_DIAG_ENCRYPT_DIS 0x00000008
1338#define AR_DIAG_DECRYPT_DIS 0x00000010
1339#define AR_DIAG_RX_DIS 0x00000020
1340#define AR_DIAG_LOOP_BACK 0x00000040
1341#define AR_DIAG_CORR_FCS 0x00000080
1342#define AR_DIAG_CHAN_INFO 0x00000100
1343#define AR_DIAG_SCRAM_SEED 0x0001FE00
1344#define AR_DIAG_SCRAM_SEED_S 8
1345#define AR_DIAG_FRAME_NV0 0x00020000
1346#define AR_DIAG_OBS_PT_SEL1 0x000C0000
1347#define AR_DIAG_OBS_PT_SEL1_S 18
1348#define AR_DIAG_FORCE_RX_CLEAR 0x00100000
1349#define AR_DIAG_IGNORE_VIRT_CS 0x00200000
1350#define AR_DIAG_FORCE_CH_IDLE_HIGH 0x00400000
1351#define AR_DIAG_EIFS_CTRL_ENA 0x00800000
1352#define AR_DIAG_DUAL_CHAIN_INFO 0x01000000
1353#define AR_DIAG_RX_ABORT 0x02000000
1354#define AR_DIAG_SATURATE_CYCLE_CNT 0x04000000
1355#define AR_DIAG_OBS_PT_SEL2 0x08000000
1356#define AR_DIAG_RX_CLEAR_CTL_LOW 0x10000000
1357#define AR_DIAG_RX_CLEAR_EXT_LOW 0x20000000
1358
1359#define AR_TSF_L32 0x804c
1360#define AR_TSF_U32 0x8050
1361
1362#define AR_TST_ADDAC 0x8054
1363#define AR_DEF_ANTENNA 0x8058
1364
1365#define AR_AES_MUTE_MASK0 0x805c
1366#define AR_AES_MUTE_MASK0_FC 0x0000FFFF
1367#define AR_AES_MUTE_MASK0_QOS 0xFFFF0000
1368#define AR_AES_MUTE_MASK0_QOS_S 16
1369
1370#define AR_AES_MUTE_MASK1 0x8060
1371#define AR_AES_MUTE_MASK1_SEQ 0x0000FFFF
Jouni Malinen0ced0e12009-01-08 13:32:13 +02001372#define AR_AES_MUTE_MASK1_FC_MGMT 0xFFFF0000
1373#define AR_AES_MUTE_MASK1_FC_MGMT_S 16
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001374
1375#define AR_GATED_CLKS 0x8064
1376#define AR_GATED_CLKS_TX 0x00000002
1377#define AR_GATED_CLKS_RX 0x00000004
1378#define AR_GATED_CLKS_REG 0x00000008
1379
1380#define AR_OBS_BUS_CTRL 0x8068
1381#define AR_OBS_BUS_SEL_1 0x00040000
1382#define AR_OBS_BUS_SEL_2 0x00080000
1383#define AR_OBS_BUS_SEL_3 0x000C0000
1384#define AR_OBS_BUS_SEL_4 0x08040000
1385#define AR_OBS_BUS_SEL_5 0x08080000
1386
1387#define AR_OBS_BUS_1 0x806c
1388#define AR_OBS_BUS_1_PCU 0x00000001
1389#define AR_OBS_BUS_1_RX_END 0x00000002
1390#define AR_OBS_BUS_1_RX_WEP 0x00000004
1391#define AR_OBS_BUS_1_RX_BEACON 0x00000008
1392#define AR_OBS_BUS_1_RX_FILTER 0x00000010
1393#define AR_OBS_BUS_1_TX_HCF 0x00000020
1394#define AR_OBS_BUS_1_QUIET_TIME 0x00000040
1395#define AR_OBS_BUS_1_CHAN_IDLE 0x00000080
1396#define AR_OBS_BUS_1_TX_HOLD 0x00000100
1397#define AR_OBS_BUS_1_TX_FRAME 0x00000200
1398#define AR_OBS_BUS_1_RX_FRAME 0x00000400
1399#define AR_OBS_BUS_1_RX_CLEAR 0x00000800
1400#define AR_OBS_BUS_1_WEP_STATE 0x0003F000
1401#define AR_OBS_BUS_1_WEP_STATE_S 12
1402#define AR_OBS_BUS_1_RX_STATE 0x01F00000
1403#define AR_OBS_BUS_1_RX_STATE_S 20
1404#define AR_OBS_BUS_1_TX_STATE 0x7E000000
1405#define AR_OBS_BUS_1_TX_STATE_S 25
1406
1407#define AR_LAST_TSTP 0x8080
1408#define AR_NAV 0x8084
1409#define AR_RTS_OK 0x8088
1410#define AR_RTS_FAIL 0x808c
1411#define AR_ACK_FAIL 0x8090
1412#define AR_FCS_FAIL 0x8094
1413#define AR_BEACON_CNT 0x8098
1414
1415#define AR_SLEEP1 0x80d4
1416#define AR_SLEEP1_ASSUME_DTIM 0x00080000
1417#define AR_SLEEP1_CAB_TIMEOUT 0xFFE00000
1418#define AR_SLEEP1_CAB_TIMEOUT_S 21
1419
1420#define AR_SLEEP2 0x80d8
1421#define AR_SLEEP2_BEACON_TIMEOUT 0xFFE00000
1422#define AR_SLEEP2_BEACON_TIMEOUT_S 21
1423
1424#define AR_BSSMSKL 0x80e0
1425#define AR_BSSMSKU 0x80e4
1426
1427#define AR_TPC 0x80e8
1428#define AR_TPC_ACK 0x0000003f
1429#define AR_TPC_ACK_S 0x00
1430#define AR_TPC_CTS 0x00003f00
1431#define AR_TPC_CTS_S 0x08
1432#define AR_TPC_CHIRP 0x003f0000
1433#define AR_TPC_CHIRP_S 0x16
1434
1435#define AR_TFCNT 0x80ec
1436#define AR_RFCNT 0x80f0
1437#define AR_RCCNT 0x80f4
1438#define AR_CCCNT 0x80f8
1439
1440#define AR_QUIET1 0x80fc
1441#define AR_QUIET1_NEXT_QUIET_S 0
1442#define AR_QUIET1_NEXT_QUIET_M 0x0000ffff
1443#define AR_QUIET1_QUIET_ENABLE 0x00010000
1444#define AR_QUIET1_QUIET_ACK_CTS_ENABLE 0x00020000
Vasanthakumar Thiagarajan17739122009-08-26 21:08:50 +05301445#define AR_QUIET1_QUIET_ACK_CTS_ENABLE_S 17
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001446#define AR_QUIET2 0x8100
1447#define AR_QUIET2_QUIET_PERIOD_S 0
1448#define AR_QUIET2_QUIET_PERIOD_M 0x0000ffff
1449#define AR_QUIET2_QUIET_DUR_S 16
1450#define AR_QUIET2_QUIET_DUR 0xffff0000
1451
1452#define AR_TSF_PARM 0x8104
1453#define AR_TSF_INCREMENT_M 0x000000ff
1454#define AR_TSF_INCREMENT_S 0x00
1455
1456#define AR_QOS_NO_ACK 0x8108
1457#define AR_QOS_NO_ACK_TWO_BIT 0x0000000f
1458#define AR_QOS_NO_ACK_TWO_BIT_S 0
1459#define AR_QOS_NO_ACK_BIT_OFF 0x00000070
1460#define AR_QOS_NO_ACK_BIT_OFF_S 4
1461#define AR_QOS_NO_ACK_BYTE_OFF 0x00000180
1462#define AR_QOS_NO_ACK_BYTE_OFF_S 7
1463
1464#define AR_PHY_ERR 0x810c
1465
1466#define AR_PHY_ERR_DCHIRP 0x00000008
1467#define AR_PHY_ERR_RADAR 0x00000020
1468#define AR_PHY_ERR_OFDM_TIMING 0x00020000
1469#define AR_PHY_ERR_CCK_TIMING 0x02000000
1470
1471#define AR_RXFIFO_CFG 0x8114
1472
1473
1474#define AR_MIC_QOS_CONTROL 0x8118
1475#define AR_MIC_QOS_SELECT 0x811c
1476
1477#define AR_PCU_MISC 0x8120
1478#define AR_PCU_FORCE_BSSID_MATCH 0x00000001
1479#define AR_PCU_MIC_NEW_LOC_ENA 0x00000004
1480#define AR_PCU_TX_ADD_TSF 0x00000008
1481#define AR_PCU_CCK_SIFS_MODE 0x00000010
1482#define AR_PCU_RX_ANT_UPDT 0x00000800
1483#define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000
1484#define AR_PCU_MISS_BCN_IN_SLEEP 0x00004000
1485#define AR_PCU_BUG_12306_FIX_ENA 0x00020000
1486#define AR_PCU_FORCE_QUIET_COLL 0x00040000
1487#define AR_PCU_TBTT_PROTECT 0x00200000
1488#define AR_PCU_CLEAR_VMF 0x01000000
1489#define AR_PCU_CLEAR_BA_VALID 0x04000000
1490
Vasanthakumar Thiagarajan17739122009-08-26 21:08:50 +05301491#define AR_PCU_BT_ANT_PREVENT_RX 0x00100000
1492#define AR_PCU_BT_ANT_PREVENT_RX_S 20
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001493
1494#define AR_FILT_OFDM 0x8124
1495#define AR_FILT_OFDM_COUNT 0x00FFFFFF
1496
1497#define AR_FILT_CCK 0x8128
1498#define AR_FILT_CCK_COUNT 0x00FFFFFF
1499
1500#define AR_PHY_ERR_1 0x812c
1501#define AR_PHY_ERR_1_COUNT 0x00FFFFFF
1502#define AR_PHY_ERR_MASK_1 0x8130
1503
1504#define AR_PHY_ERR_2 0x8134
1505#define AR_PHY_ERR_2_COUNT 0x00FFFFFF
1506#define AR_PHY_ERR_MASK_2 0x8138
1507
1508#define AR_PHY_COUNTMAX (3 << 22)
1509#define AR_MIBCNT_INTRMASK (3 << 22)
1510
Sujith4af9cf42009-02-12 10:06:47 +05301511#define AR_TSFOOR_THRESHOLD 0x813c
1512#define AR_TSFOOR_THRESHOLD_VAL 0x0000FFFF
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001513
1514#define AR_PHY_ERR_EIFS_MASK 8144
1515
1516#define AR_PHY_ERR_3 0x8168
1517#define AR_PHY_ERR_3_COUNT 0x00FFFFFF
1518#define AR_PHY_ERR_MASK_3 0x816c
1519
Vasanthakumar Thiagarajan17739122009-08-26 21:08:50 +05301520#define AR_BT_COEX_MODE 0x8170
1521#define AR_BT_TIME_EXTEND 0x000000ff
1522#define AR_BT_TIME_EXTEND_S 0
1523#define AR_BT_TXSTATE_EXTEND 0x00000100
1524#define AR_BT_TXSTATE_EXTEND_S 8
1525#define AR_BT_TX_FRAME_EXTEND 0x00000200
1526#define AR_BT_TX_FRAME_EXTEND_S 9
1527#define AR_BT_MODE 0x00000c00
1528#define AR_BT_MODE_S 10
1529#define AR_BT_QUIET 0x00001000
1530#define AR_BT_QUIET_S 12
1531#define AR_BT_QCU_THRESH 0x0001e000
1532#define AR_BT_QCU_THRESH_S 13
1533#define AR_BT_RX_CLEAR_POLARITY 0x00020000
1534#define AR_BT_RX_CLEAR_POLARITY_S 17
1535#define AR_BT_PRIORITY_TIME 0x00fc0000
1536#define AR_BT_PRIORITY_TIME_S 18
1537#define AR_BT_FIRST_SLOT_TIME 0xff000000
1538#define AR_BT_FIRST_SLOT_TIME_S 24
1539
1540#define AR_BT_COEX_WEIGHT 0x8174
1541#define AR_BT_COEX_WGHT 0xff55
1542#define AR_STOMP_ALL_WLAN_WGHT 0xffcc
1543#define AR_STOMP_LOW_WLAN_WGHT 0xaaa8
1544#define AR_STOMP_NONE_WLAN_WGHT 0xaa00
1545#define AR_BTCOEX_BT_WGHT 0x0000ffff
1546#define AR_BTCOEX_BT_WGHT_S 0
1547#define AR_BTCOEX_WL_WGHT 0xffff0000
1548#define AR_BTCOEX_WL_WGHT_S 16
1549
1550#define AR_BT_COEX_MODE2 0x817c
1551#define AR_BT_BCN_MISS_THRESH 0x000000ff
1552#define AR_BT_BCN_MISS_THRESH_S 0
1553#define AR_BT_BCN_MISS_CNT 0x0000ff00
1554#define AR_BT_BCN_MISS_CNT_S 8
1555#define AR_BT_HOLD_RX_CLEAR 0x00010000
1556#define AR_BT_HOLD_RX_CLEAR_S 16
1557#define AR_BT_DISABLE_BT_ANT 0x00100000
1558#define AR_BT_DISABLE_BT_ANT_S 20
1559
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001560#define AR_TXSIFS 0x81d0
1561#define AR_TXSIFS_TIME 0x000000FF
1562#define AR_TXSIFS_TX_LATENCY 0x00000F00
1563#define AR_TXSIFS_TX_LATENCY_S 8
1564#define AR_TXSIFS_ACK_SHIFT 0x00007000
1565#define AR_TXSIFS_ACK_SHIFT_S 12
1566
1567#define AR_TXOP_X 0x81ec
1568#define AR_TXOP_X_VAL 0x000000FF
1569
1570
1571#define AR_TXOP_0_3 0x81f0
1572#define AR_TXOP_4_7 0x81f4
1573#define AR_TXOP_8_11 0x81f8
1574#define AR_TXOP_12_15 0x81fc
1575
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05301576#define AR_NEXT_NDP2_TIMER 0x8180
1577#define AR_FIRST_NDP_TIMER 7
1578#define AR_NDP2_PERIOD 0x81a0
1579#define AR_NDP2_TIMER_MODE 0x81c0
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001580#define AR_NEXT_TBTT_TIMER 0x8200
1581#define AR_NEXT_DMA_BEACON_ALERT 0x8204
1582#define AR_NEXT_SWBA 0x8208
1583#define AR_NEXT_CFP 0x8208
1584#define AR_NEXT_HCF 0x820C
1585#define AR_NEXT_TIM 0x8210
1586#define AR_NEXT_DTIM 0x8214
1587#define AR_NEXT_QUIET_TIMER 0x8218
1588#define AR_NEXT_NDP_TIMER 0x821C
1589
1590#define AR_BEACON_PERIOD 0x8220
1591#define AR_DMA_BEACON_PERIOD 0x8224
1592#define AR_SWBA_PERIOD 0x8228
1593#define AR_HCF_PERIOD 0x822C
1594#define AR_TIM_PERIOD 0x8230
1595#define AR_DTIM_PERIOD 0x8234
1596#define AR_QUIET_PERIOD 0x8238
1597#define AR_NDP_PERIOD 0x823C
1598
1599#define AR_TIMER_MODE 0x8240
1600#define AR_TBTT_TIMER_EN 0x00000001
1601#define AR_DBA_TIMER_EN 0x00000002
1602#define AR_SWBA_TIMER_EN 0x00000004
1603#define AR_HCF_TIMER_EN 0x00000008
1604#define AR_TIM_TIMER_EN 0x00000010
1605#define AR_DTIM_TIMER_EN 0x00000020
1606#define AR_QUIET_TIMER_EN 0x00000040
1607#define AR_NDP_TIMER_EN 0x00000080
1608#define AR_TIMER_OVERFLOW_INDEX 0x00000700
1609#define AR_TIMER_OVERFLOW_INDEX_S 8
1610#define AR_TIMER_THRESH 0xFFFFF000
1611#define AR_TIMER_THRESH_S 12
1612
1613#define AR_SLP32_MODE 0x8244
1614#define AR_SLP32_HALF_CLK_LATENCY 0x000FFFFF
1615#define AR_SLP32_ENA 0x00100000
1616#define AR_SLP32_TSF_WRITE_STATUS 0x00200000
1617
1618#define AR_SLP32_WAKE 0x8248
1619#define AR_SLP32_WAKE_XTL_TIME 0x0000FFFF
1620
1621#define AR_SLP32_INC 0x824c
1622#define AR_SLP32_TST_INC 0x000FFFFF
1623
1624#define AR_SLP_CNT 0x8250
1625#define AR_SLP_CYCLE_CNT 0x8254
1626
1627#define AR_SLP_MIB_CTRL 0x8258
1628#define AR_SLP_MIB_CLEAR 0x00000001
1629#define AR_SLP_MIB_PENDING 0x00000002
1630
Vivek Natarajan04dc8822009-07-15 08:51:17 +05301631#define AR_MAC_PCU_LOGIC_ANALYZER 0x8264
1632#define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768 0x20000000
1633
1634
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001635#define AR_2040_MODE 0x8318
1636#define AR_2040_JOINED_RX_CLEAR 0x00000001
1637
1638
1639#define AR_EXTRCCNT 0x8328
1640
1641#define AR_SELFGEN_MASK 0x832c
1642
1643#define AR_PCU_TXBUF_CTRL 0x8340
1644#define AR_PCU_TXBUF_CTRL_SIZE_MASK 0x7FF
1645#define AR_PCU_TXBUF_CTRL_USABLE_SIZE 0x700
1646#define AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE 0x380
1647
Jouni Malinen0ced0e12009-01-08 13:32:13 +02001648#define AR_PCU_MISC_MODE2 0x8344
1649#define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE 0x00000002
1650#define AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT 0x00000004
1651
Vivek Natarajan04dc8822009-07-15 08:51:17 +05301652#define AR_PCU_MISC_MODE2_RESERVED 0x00000038
1653#define AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE 0x00000040
1654#define AR_PCU_MISC_MODE2_CFP_IGNORE 0x00000080
1655#define AR_PCU_MISC_MODE2_MGMT_QOS 0x0000FF00
1656#define AR_PCU_MISC_MODE2_MGMT_QOS_S 8
1657#define AR_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION 0x00010000
1658#define AR_PCU_MISC_MODE2_ENABLE_AGGWEP 0x00020000
1659#define AR_PCU_MISC_MODE2_HWWAR1 0x00100000
1660#define AR_PCU_MISC_MODE2_HWWAR2 0x02000000
1661#define AR_PCU_MISC_MODE2_RESERVED2 0xFFFE0000
1662
1663#define AR_MAC_PCU_ASYNC_FIFO_REG3 0x8358
1664#define AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL 0x00000400
1665#define AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET 0x80000000
1666
1667
1668#define AR_AES_MUTE_MASK0 0x805c
1669#define AR_AES_MUTE_MASK0_FC 0x0000FFFF
1670#define AR_AES_MUTE_MASK0_QOS 0xFFFF0000
1671#define AR_AES_MUTE_MASK0_QOS_S 16
1672
1673#define AR_AES_MUTE_MASK1 0x8060
1674#define AR_AES_MUTE_MASK1_SEQ 0x0000FFFF
1675#define AR_AES_MUTE_MASK1_SEQ_S 0
1676#define AR_AES_MUTE_MASK1_FC_MGMT 0xFFFF0000
1677#define AR_AES_MUTE_MASK1_FC_MGMT_S 16
1678
1679#define AR_RATE_DURATION_0 0x8700
1680#define AR_RATE_DURATION_31 0x87CC
1681#define AR_RATE_DURATION_32 0x8780
1682#define AR_RATE_DURATION(_n) (AR_RATE_DURATION_0 + ((_n)<<2))
1683
1684
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001685#define AR_KEYTABLE_0 0x8800
1686#define AR_KEYTABLE(_n) (AR_KEYTABLE_0 + ((_n)*32))
1687#define AR_KEY_CACHE_SIZE 128
1688#define AR_RSVD_KEYTABLE_ENTRIES 4
1689#define AR_KEY_TYPE 0x00000007
1690#define AR_KEYTABLE_TYPE_40 0x00000000
1691#define AR_KEYTABLE_TYPE_104 0x00000001
1692#define AR_KEYTABLE_TYPE_128 0x00000003
1693#define AR_KEYTABLE_TYPE_TKIP 0x00000004
1694#define AR_KEYTABLE_TYPE_AES 0x00000005
1695#define AR_KEYTABLE_TYPE_CCM 0x00000006
1696#define AR_KEYTABLE_TYPE_CLR 0x00000007
1697#define AR_KEYTABLE_ANT 0x00000008
1698#define AR_KEYTABLE_VALID 0x00008000
1699#define AR_KEYTABLE_KEY0(_n) (AR_KEYTABLE(_n) + 0)
1700#define AR_KEYTABLE_KEY1(_n) (AR_KEYTABLE(_n) + 4)
1701#define AR_KEYTABLE_KEY2(_n) (AR_KEYTABLE(_n) + 8)
1702#define AR_KEYTABLE_KEY3(_n) (AR_KEYTABLE(_n) + 12)
1703#define AR_KEYTABLE_KEY4(_n) (AR_KEYTABLE(_n) + 16)
1704#define AR_KEYTABLE_TYPE(_n) (AR_KEYTABLE(_n) + 20)
1705#define AR_KEYTABLE_MAC0(_n) (AR_KEYTABLE(_n) + 24)
1706#define AR_KEYTABLE_MAC1(_n) (AR_KEYTABLE(_n) + 28)
1707
1708#endif