Maciej W. Rozycki | b45d527 | 2007-07-17 04:03:50 -0700 | [diff] [blame] | 1 | /* |
| 2 | * drivers/serial/sb1250-duart.c |
| 3 | * |
| 4 | * Support for the asynchronous serial interface (DUART) included |
| 5 | * in the BCM1250 and derived System-On-a-Chip (SOC) devices. |
| 6 | * |
| 7 | * Copyright (c) 2007 Maciej W. Rozycki |
| 8 | * |
| 9 | * Derived from drivers/char/sb1250_duart.c for which the following |
| 10 | * copyright applies: |
| 11 | * |
| 12 | * Copyright (c) 2000, 2001, 2002, 2003, 2004 Broadcom Corporation |
| 13 | * |
| 14 | * This program is free software; you can redistribute it and/or |
| 15 | * modify it under the terms of the GNU General Public License |
| 16 | * as published by the Free Software Foundation; either version |
| 17 | * 2 of the License, or (at your option) any later version. |
| 18 | * |
| 19 | * References: |
| 20 | * |
| 21 | * "BCM1250/BCM1125/BCM1125H User Manual", Broadcom Corporation |
| 22 | */ |
| 23 | |
| 24 | #if defined(CONFIG_SERIAL_SB1250_DUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
| 25 | #define SUPPORT_SYSRQ |
| 26 | #endif |
| 27 | |
Maciej W. Rozycki | 86d0004 | 2007-07-31 00:39:22 -0700 | [diff] [blame] | 28 | #include <linux/compiler.h> |
Maciej W. Rozycki | b45d527 | 2007-07-17 04:03:50 -0700 | [diff] [blame] | 29 | #include <linux/console.h> |
| 30 | #include <linux/delay.h> |
| 31 | #include <linux/errno.h> |
| 32 | #include <linux/init.h> |
| 33 | #include <linux/interrupt.h> |
| 34 | #include <linux/ioport.h> |
| 35 | #include <linux/kernel.h> |
| 36 | #include <linux/major.h> |
| 37 | #include <linux/serial.h> |
| 38 | #include <linux/serial_core.h> |
| 39 | #include <linux/spinlock.h> |
| 40 | #include <linux/sysrq.h> |
| 41 | #include <linux/tty.h> |
| 42 | #include <linux/types.h> |
| 43 | |
| 44 | #include <asm/atomic.h> |
| 45 | #include <asm/io.h> |
| 46 | #include <asm/war.h> |
| 47 | |
| 48 | #include <asm/sibyte/sb1250.h> |
| 49 | #include <asm/sibyte/sb1250_uart.h> |
| 50 | #include <asm/sibyte/swarm.h> |
| 51 | |
| 52 | |
| 53 | #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) |
| 54 | #include <asm/sibyte/bcm1480_regs.h> |
| 55 | #include <asm/sibyte/bcm1480_int.h> |
| 56 | |
| 57 | #define SBD_CHANREGS(line) A_BCM1480_DUART_CHANREG((line), 0) |
| 58 | #define SBD_CTRLREGS(line) A_BCM1480_DUART_CTRLREG((line), 0) |
| 59 | #define SBD_INT(line) (K_BCM1480_INT_UART_0 + (line)) |
| 60 | |
Thiemo Seufer | 719b6f2 | 2007-09-11 15:23:33 -0700 | [diff] [blame^] | 61 | #define DUART_CHANREG_SPACING BCM1480_DUART_CHANREG_SPACING |
| 62 | |
| 63 | #define R_DUART_IMRREG(line) R_BCM1480_DUART_IMRREG(line) |
| 64 | #define R_DUART_INCHREG(line) R_BCM1480_DUART_INCHREG(line) |
| 65 | #define R_DUART_ISRREG(line) R_BCM1480_DUART_ISRREG(line) |
| 66 | |
Maciej W. Rozycki | b45d527 | 2007-07-17 04:03:50 -0700 | [diff] [blame] | 67 | #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) |
| 68 | #include <asm/sibyte/sb1250_regs.h> |
| 69 | #include <asm/sibyte/sb1250_int.h> |
| 70 | |
| 71 | #define SBD_CHANREGS(line) A_DUART_CHANREG((line), 0) |
| 72 | #define SBD_CTRLREGS(line) A_DUART_CTRLREG(0) |
| 73 | #define SBD_INT(line) (K_INT_UART_0 + (line)) |
| 74 | |
| 75 | #else |
| 76 | #error invalid SB1250 UART configuration |
| 77 | |
| 78 | #endif |
| 79 | |
| 80 | |
| 81 | MODULE_AUTHOR("Maciej W. Rozycki <macro@linux-mips.org>"); |
| 82 | MODULE_DESCRIPTION("BCM1xxx on-chip DUART serial driver"); |
| 83 | MODULE_LICENSE("GPL"); |
| 84 | |
| 85 | |
| 86 | #define DUART_MAX_CHIP 2 |
| 87 | #define DUART_MAX_SIDE 2 |
| 88 | |
| 89 | /* |
| 90 | * Per-port state. |
| 91 | */ |
| 92 | struct sbd_port { |
| 93 | struct sbd_duart *duart; |
| 94 | struct uart_port port; |
| 95 | unsigned char __iomem *memctrl; |
| 96 | int tx_stopped; |
| 97 | int initialised; |
| 98 | }; |
| 99 | |
| 100 | /* |
| 101 | * Per-DUART state for the shared register space. |
| 102 | */ |
| 103 | struct sbd_duart { |
| 104 | struct sbd_port sport[2]; |
| 105 | unsigned long mapctrl; |
| 106 | atomic_t map_guard; |
| 107 | }; |
| 108 | |
| 109 | #define to_sport(uport) container_of(uport, struct sbd_port, port) |
| 110 | |
| 111 | static struct sbd_duart sbd_duarts[DUART_MAX_CHIP]; |
| 112 | |
Maciej W. Rozycki | b45d527 | 2007-07-17 04:03:50 -0700 | [diff] [blame] | 113 | |
| 114 | /* |
| 115 | * Reading and writing SB1250 DUART registers. |
| 116 | * |
| 117 | * There are three register spaces: two per-channel ones and |
| 118 | * a shared one. We have to define accessors appropriately. |
| 119 | * All registers are 64-bit and all but the Baud Rate Clock |
| 120 | * registers only define 8 least significant bits. There is |
| 121 | * also a workaround to take into account. Raw accessors use |
| 122 | * the full register width, but cooked ones truncate it |
| 123 | * intentionally so that the rest of the driver does not care. |
| 124 | */ |
| 125 | static u64 __read_sbdchn(struct sbd_port *sport, int reg) |
| 126 | { |
| 127 | void __iomem *csr = sport->port.membase + reg; |
| 128 | |
| 129 | return __raw_readq(csr); |
| 130 | } |
| 131 | |
| 132 | static u64 __read_sbdshr(struct sbd_port *sport, int reg) |
| 133 | { |
| 134 | void __iomem *csr = sport->memctrl + reg; |
| 135 | |
| 136 | return __raw_readq(csr); |
| 137 | } |
| 138 | |
| 139 | static void __write_sbdchn(struct sbd_port *sport, int reg, u64 value) |
| 140 | { |
| 141 | void __iomem *csr = sport->port.membase + reg; |
| 142 | |
| 143 | __raw_writeq(value, csr); |
| 144 | } |
| 145 | |
| 146 | static void __write_sbdshr(struct sbd_port *sport, int reg, u64 value) |
| 147 | { |
| 148 | void __iomem *csr = sport->memctrl + reg; |
| 149 | |
| 150 | __raw_writeq(value, csr); |
| 151 | } |
| 152 | |
| 153 | /* |
| 154 | * In bug 1956, we get glitches that can mess up uart registers. This |
| 155 | * "read-mode-reg after any register access" is an accepted workaround. |
| 156 | */ |
| 157 | static void __war_sbd1956(struct sbd_port *sport) |
| 158 | { |
| 159 | __read_sbdchn(sport, R_DUART_MODE_REG_1); |
| 160 | __read_sbdchn(sport, R_DUART_MODE_REG_2); |
| 161 | } |
| 162 | |
| 163 | static unsigned char read_sbdchn(struct sbd_port *sport, int reg) |
| 164 | { |
| 165 | unsigned char retval; |
| 166 | |
| 167 | retval = __read_sbdchn(sport, reg); |
| 168 | if (SIBYTE_1956_WAR) |
| 169 | __war_sbd1956(sport); |
| 170 | return retval; |
| 171 | } |
| 172 | |
| 173 | static unsigned char read_sbdshr(struct sbd_port *sport, int reg) |
| 174 | { |
| 175 | unsigned char retval; |
| 176 | |
| 177 | retval = __read_sbdshr(sport, reg); |
| 178 | if (SIBYTE_1956_WAR) |
| 179 | __war_sbd1956(sport); |
| 180 | return retval; |
| 181 | } |
| 182 | |
| 183 | static void write_sbdchn(struct sbd_port *sport, int reg, unsigned int value) |
| 184 | { |
| 185 | __write_sbdchn(sport, reg, value); |
| 186 | if (SIBYTE_1956_WAR) |
| 187 | __war_sbd1956(sport); |
| 188 | } |
| 189 | |
| 190 | static void write_sbdshr(struct sbd_port *sport, int reg, unsigned int value) |
| 191 | { |
| 192 | __write_sbdshr(sport, reg, value); |
| 193 | if (SIBYTE_1956_WAR) |
| 194 | __war_sbd1956(sport); |
| 195 | } |
| 196 | |
| 197 | |
| 198 | static int sbd_receive_ready(struct sbd_port *sport) |
| 199 | { |
| 200 | return read_sbdchn(sport, R_DUART_STATUS) & M_DUART_RX_RDY; |
| 201 | } |
| 202 | |
| 203 | static int sbd_receive_drain(struct sbd_port *sport) |
| 204 | { |
| 205 | int loops = 10000; |
| 206 | |
| 207 | while (sbd_receive_ready(sport) && loops--) |
| 208 | read_sbdchn(sport, R_DUART_RX_HOLD); |
| 209 | return loops; |
| 210 | } |
| 211 | |
Maciej W. Rozycki | 86d0004 | 2007-07-31 00:39:22 -0700 | [diff] [blame] | 212 | static int __maybe_unused sbd_transmit_ready(struct sbd_port *sport) |
Maciej W. Rozycki | b45d527 | 2007-07-17 04:03:50 -0700 | [diff] [blame] | 213 | { |
| 214 | return read_sbdchn(sport, R_DUART_STATUS) & M_DUART_TX_RDY; |
| 215 | } |
| 216 | |
Maciej W. Rozycki | 86d0004 | 2007-07-31 00:39:22 -0700 | [diff] [blame] | 217 | static int __maybe_unused sbd_transmit_drain(struct sbd_port *sport) |
Maciej W. Rozycki | b45d527 | 2007-07-17 04:03:50 -0700 | [diff] [blame] | 218 | { |
| 219 | int loops = 10000; |
| 220 | |
| 221 | while (!sbd_transmit_ready(sport) && loops--) |
| 222 | udelay(2); |
| 223 | return loops; |
| 224 | } |
| 225 | |
| 226 | static int sbd_transmit_empty(struct sbd_port *sport) |
| 227 | { |
| 228 | return read_sbdchn(sport, R_DUART_STATUS) & M_DUART_TX_EMT; |
| 229 | } |
| 230 | |
| 231 | static int sbd_line_drain(struct sbd_port *sport) |
| 232 | { |
| 233 | int loops = 10000; |
| 234 | |
| 235 | while (!sbd_transmit_empty(sport) && loops--) |
| 236 | udelay(2); |
| 237 | return loops; |
| 238 | } |
| 239 | |
| 240 | |
| 241 | static unsigned int sbd_tx_empty(struct uart_port *uport) |
| 242 | { |
| 243 | struct sbd_port *sport = to_sport(uport); |
| 244 | |
| 245 | return sbd_transmit_empty(sport) ? TIOCSER_TEMT : 0; |
| 246 | } |
| 247 | |
| 248 | static unsigned int sbd_get_mctrl(struct uart_port *uport) |
| 249 | { |
| 250 | struct sbd_port *sport = to_sport(uport); |
| 251 | unsigned int mctrl, status; |
| 252 | |
| 253 | status = read_sbdshr(sport, R_DUART_IN_PORT); |
| 254 | status >>= (uport->line) % 2; |
| 255 | mctrl = (!(status & M_DUART_IN_PIN0_VAL) ? TIOCM_CTS : 0) | |
| 256 | (!(status & M_DUART_IN_PIN4_VAL) ? TIOCM_CAR : 0) | |
| 257 | (!(status & M_DUART_RIN0_PIN) ? TIOCM_RNG : 0) | |
| 258 | (!(status & M_DUART_IN_PIN2_VAL) ? TIOCM_DSR : 0); |
| 259 | return mctrl; |
| 260 | } |
| 261 | |
| 262 | static void sbd_set_mctrl(struct uart_port *uport, unsigned int mctrl) |
| 263 | { |
| 264 | struct sbd_port *sport = to_sport(uport); |
| 265 | unsigned int clr = 0, set = 0, mode2; |
| 266 | |
| 267 | if (mctrl & TIOCM_DTR) |
| 268 | set |= M_DUART_SET_OPR2; |
| 269 | else |
| 270 | clr |= M_DUART_CLR_OPR2; |
| 271 | if (mctrl & TIOCM_RTS) |
| 272 | set |= M_DUART_SET_OPR0; |
| 273 | else |
| 274 | clr |= M_DUART_CLR_OPR0; |
| 275 | clr <<= (uport->line) % 2; |
| 276 | set <<= (uport->line) % 2; |
| 277 | |
| 278 | mode2 = read_sbdchn(sport, R_DUART_MODE_REG_2); |
| 279 | mode2 &= ~M_DUART_CHAN_MODE; |
| 280 | if (mctrl & TIOCM_LOOP) |
| 281 | mode2 |= V_DUART_CHAN_MODE_LCL_LOOP; |
| 282 | else |
| 283 | mode2 |= V_DUART_CHAN_MODE_NORMAL; |
| 284 | |
| 285 | write_sbdshr(sport, R_DUART_CLEAR_OPR, clr); |
| 286 | write_sbdshr(sport, R_DUART_SET_OPR, set); |
| 287 | write_sbdchn(sport, R_DUART_MODE_REG_2, mode2); |
| 288 | } |
| 289 | |
| 290 | static void sbd_stop_tx(struct uart_port *uport) |
| 291 | { |
| 292 | struct sbd_port *sport = to_sport(uport); |
| 293 | |
| 294 | write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS); |
| 295 | sport->tx_stopped = 1; |
| 296 | }; |
| 297 | |
| 298 | static void sbd_start_tx(struct uart_port *uport) |
| 299 | { |
| 300 | struct sbd_port *sport = to_sport(uport); |
| 301 | unsigned int mask; |
| 302 | |
| 303 | /* Enable tx interrupts. */ |
| 304 | mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2)); |
| 305 | mask |= M_DUART_IMR_TX; |
| 306 | write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask); |
| 307 | |
| 308 | /* Go!, go!, go!... */ |
| 309 | write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_EN); |
| 310 | sport->tx_stopped = 0; |
| 311 | }; |
| 312 | |
| 313 | static void sbd_stop_rx(struct uart_port *uport) |
| 314 | { |
| 315 | struct sbd_port *sport = to_sport(uport); |
| 316 | |
| 317 | write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), 0); |
| 318 | }; |
| 319 | |
| 320 | static void sbd_enable_ms(struct uart_port *uport) |
| 321 | { |
| 322 | struct sbd_port *sport = to_sport(uport); |
| 323 | |
| 324 | write_sbdchn(sport, R_DUART_AUXCTL_X, |
| 325 | M_DUART_CIN_CHNG_ENA | M_DUART_CTS_CHNG_ENA); |
| 326 | } |
| 327 | |
| 328 | static void sbd_break_ctl(struct uart_port *uport, int break_state) |
| 329 | { |
| 330 | struct sbd_port *sport = to_sport(uport); |
| 331 | |
| 332 | if (break_state == -1) |
| 333 | write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_START_BREAK); |
| 334 | else |
| 335 | write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_STOP_BREAK); |
| 336 | } |
| 337 | |
| 338 | |
| 339 | static void sbd_receive_chars(struct sbd_port *sport) |
| 340 | { |
| 341 | struct uart_port *uport = &sport->port; |
| 342 | struct uart_icount *icount; |
| 343 | unsigned int status, ch, flag; |
| 344 | int count; |
| 345 | |
| 346 | for (count = 16; count; count--) { |
| 347 | status = read_sbdchn(sport, R_DUART_STATUS); |
| 348 | if (!(status & M_DUART_RX_RDY)) |
| 349 | break; |
| 350 | |
| 351 | ch = read_sbdchn(sport, R_DUART_RX_HOLD); |
| 352 | |
| 353 | flag = TTY_NORMAL; |
| 354 | |
| 355 | icount = &uport->icount; |
| 356 | icount->rx++; |
| 357 | |
| 358 | if (unlikely(status & |
| 359 | (M_DUART_RCVD_BRK | M_DUART_FRM_ERR | |
| 360 | M_DUART_PARITY_ERR | M_DUART_OVRUN_ERR))) { |
| 361 | if (status & M_DUART_RCVD_BRK) { |
| 362 | icount->brk++; |
| 363 | if (uart_handle_break(uport)) |
| 364 | continue; |
| 365 | } else if (status & M_DUART_FRM_ERR) |
| 366 | icount->frame++; |
| 367 | else if (status & M_DUART_PARITY_ERR) |
| 368 | icount->parity++; |
| 369 | if (status & M_DUART_OVRUN_ERR) |
| 370 | icount->overrun++; |
| 371 | |
| 372 | status &= uport->read_status_mask; |
| 373 | if (status & M_DUART_RCVD_BRK) |
| 374 | flag = TTY_BREAK; |
| 375 | else if (status & M_DUART_FRM_ERR) |
| 376 | flag = TTY_FRAME; |
| 377 | else if (status & M_DUART_PARITY_ERR) |
| 378 | flag = TTY_PARITY; |
| 379 | } |
| 380 | |
| 381 | if (uart_handle_sysrq_char(uport, ch)) |
| 382 | continue; |
| 383 | |
| 384 | uart_insert_char(uport, status, M_DUART_OVRUN_ERR, ch, flag); |
| 385 | } |
| 386 | |
| 387 | tty_flip_buffer_push(uport->info->tty); |
| 388 | } |
| 389 | |
| 390 | static void sbd_transmit_chars(struct sbd_port *sport) |
| 391 | { |
| 392 | struct uart_port *uport = &sport->port; |
| 393 | struct circ_buf *xmit = &sport->port.info->xmit; |
| 394 | unsigned int mask; |
| 395 | int stop_tx; |
| 396 | |
| 397 | /* XON/XOFF chars. */ |
| 398 | if (sport->port.x_char) { |
| 399 | write_sbdchn(sport, R_DUART_TX_HOLD, sport->port.x_char); |
| 400 | sport->port.icount.tx++; |
| 401 | sport->port.x_char = 0; |
| 402 | return; |
| 403 | } |
| 404 | |
| 405 | /* If nothing to do or stopped or hardware stopped. */ |
| 406 | stop_tx = (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)); |
| 407 | |
| 408 | /* Send char. */ |
| 409 | if (!stop_tx) { |
| 410 | write_sbdchn(sport, R_DUART_TX_HOLD, xmit->buf[xmit->tail]); |
| 411 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
| 412 | sport->port.icount.tx++; |
| 413 | |
| 414 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
| 415 | uart_write_wakeup(&sport->port); |
| 416 | } |
| 417 | |
| 418 | /* Are we are done? */ |
| 419 | if (stop_tx || uart_circ_empty(xmit)) { |
| 420 | /* Disable tx interrupts. */ |
| 421 | mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2)); |
| 422 | mask &= ~M_DUART_IMR_TX; |
| 423 | write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask); |
| 424 | } |
| 425 | } |
| 426 | |
| 427 | static void sbd_status_handle(struct sbd_port *sport) |
| 428 | { |
| 429 | struct uart_port *uport = &sport->port; |
| 430 | unsigned int delta; |
| 431 | |
| 432 | delta = read_sbdshr(sport, R_DUART_INCHREG((uport->line) % 2)); |
| 433 | delta >>= (uport->line) % 2; |
| 434 | |
| 435 | if (delta & (M_DUART_IN_PIN0_VAL << S_DUART_IN_PIN_CHNG)) |
| 436 | uart_handle_cts_change(uport, !(delta & M_DUART_IN_PIN0_VAL)); |
| 437 | |
| 438 | if (delta & (M_DUART_IN_PIN2_VAL << S_DUART_IN_PIN_CHNG)) |
| 439 | uport->icount.dsr++; |
| 440 | |
| 441 | if (delta & ((M_DUART_IN_PIN2_VAL | M_DUART_IN_PIN0_VAL) << |
| 442 | S_DUART_IN_PIN_CHNG)) |
| 443 | wake_up_interruptible(&uport->info->delta_msr_wait); |
| 444 | } |
| 445 | |
| 446 | static irqreturn_t sbd_interrupt(int irq, void *dev_id) |
| 447 | { |
| 448 | struct sbd_port *sport = dev_id; |
| 449 | struct uart_port *uport = &sport->port; |
| 450 | irqreturn_t status = IRQ_NONE; |
| 451 | unsigned int intstat; |
| 452 | int count; |
| 453 | |
| 454 | for (count = 16; count; count--) { |
| 455 | intstat = read_sbdshr(sport, |
| 456 | R_DUART_ISRREG((uport->line) % 2)); |
| 457 | intstat &= read_sbdshr(sport, |
| 458 | R_DUART_IMRREG((uport->line) % 2)); |
| 459 | intstat &= M_DUART_ISR_ALL; |
| 460 | if (!intstat) |
| 461 | break; |
| 462 | |
| 463 | if (intstat & M_DUART_ISR_RX) |
| 464 | sbd_receive_chars(sport); |
| 465 | if (intstat & M_DUART_ISR_IN) |
| 466 | sbd_status_handle(sport); |
| 467 | if (intstat & M_DUART_ISR_TX) |
| 468 | sbd_transmit_chars(sport); |
| 469 | |
| 470 | status = IRQ_HANDLED; |
| 471 | } |
| 472 | |
| 473 | return status; |
| 474 | } |
| 475 | |
| 476 | |
| 477 | static int sbd_startup(struct uart_port *uport) |
| 478 | { |
| 479 | struct sbd_port *sport = to_sport(uport); |
| 480 | unsigned int mode1; |
| 481 | int ret; |
| 482 | |
| 483 | ret = request_irq(sport->port.irq, sbd_interrupt, |
| 484 | IRQF_SHARED, "sb1250-duart", sport); |
| 485 | if (ret) |
| 486 | return ret; |
| 487 | |
| 488 | /* Clear the receive FIFO. */ |
| 489 | sbd_receive_drain(sport); |
| 490 | |
| 491 | /* Clear the interrupt registers. */ |
| 492 | write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT); |
| 493 | read_sbdshr(sport, R_DUART_INCHREG((uport->line) % 2)); |
| 494 | |
| 495 | /* Set rx/tx interrupt to FIFO available. */ |
| 496 | mode1 = read_sbdchn(sport, R_DUART_MODE_REG_1); |
| 497 | mode1 &= ~(M_DUART_RX_IRQ_SEL_RXFULL | M_DUART_TX_IRQ_SEL_TXEMPT); |
| 498 | write_sbdchn(sport, R_DUART_MODE_REG_1, mode1); |
| 499 | |
| 500 | /* Disable tx, enable rx. */ |
| 501 | write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS | M_DUART_RX_EN); |
| 502 | sport->tx_stopped = 1; |
| 503 | |
| 504 | /* Enable interrupts. */ |
| 505 | write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), |
| 506 | M_DUART_IMR_IN | M_DUART_IMR_RX); |
| 507 | |
| 508 | return 0; |
| 509 | } |
| 510 | |
| 511 | static void sbd_shutdown(struct uart_port *uport) |
| 512 | { |
| 513 | struct sbd_port *sport = to_sport(uport); |
| 514 | |
| 515 | write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS | M_DUART_RX_DIS); |
| 516 | sport->tx_stopped = 1; |
| 517 | free_irq(sport->port.irq, sport); |
| 518 | } |
| 519 | |
| 520 | |
| 521 | static void sbd_init_port(struct sbd_port *sport) |
| 522 | { |
| 523 | struct uart_port *uport = &sport->port; |
| 524 | |
| 525 | if (sport->initialised) |
| 526 | return; |
| 527 | |
| 528 | /* There is no DUART reset feature, so just set some sane defaults. */ |
| 529 | write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_RESET_TX); |
| 530 | write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_RESET_RX); |
| 531 | write_sbdchn(sport, R_DUART_MODE_REG_1, V_DUART_BITS_PER_CHAR_8); |
| 532 | write_sbdchn(sport, R_DUART_MODE_REG_2, 0); |
| 533 | write_sbdchn(sport, R_DUART_FULL_CTL, |
| 534 | V_DUART_INT_TIME(0) | V_DUART_SIG_FULL(15)); |
| 535 | write_sbdchn(sport, R_DUART_OPCR_X, 0); |
| 536 | write_sbdchn(sport, R_DUART_AUXCTL_X, 0); |
| 537 | write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), 0); |
| 538 | |
| 539 | sport->initialised = 1; |
| 540 | } |
| 541 | |
| 542 | static void sbd_set_termios(struct uart_port *uport, struct ktermios *termios, |
| 543 | struct ktermios *old_termios) |
| 544 | { |
| 545 | struct sbd_port *sport = to_sport(uport); |
| 546 | unsigned int mode1 = 0, mode2 = 0, aux = 0; |
| 547 | unsigned int mode1mask = 0, mode2mask = 0, auxmask = 0; |
| 548 | unsigned int oldmode1, oldmode2, oldaux; |
| 549 | unsigned int baud, brg; |
| 550 | unsigned int command; |
| 551 | |
| 552 | mode1mask |= ~(M_DUART_PARITY_MODE | M_DUART_PARITY_TYPE_ODD | |
| 553 | M_DUART_BITS_PER_CHAR); |
| 554 | mode2mask |= ~M_DUART_STOP_BIT_LEN_2; |
| 555 | auxmask |= ~M_DUART_CTS_CHNG_ENA; |
| 556 | |
| 557 | /* Byte size. */ |
| 558 | switch (termios->c_cflag & CSIZE) { |
| 559 | case CS5: |
| 560 | case CS6: |
| 561 | /* Unsupported, leave unchanged. */ |
| 562 | mode1mask |= M_DUART_PARITY_MODE; |
| 563 | break; |
| 564 | case CS7: |
| 565 | mode1 |= V_DUART_BITS_PER_CHAR_7; |
| 566 | break; |
| 567 | case CS8: |
| 568 | default: |
| 569 | mode1 |= V_DUART_BITS_PER_CHAR_8; |
| 570 | break; |
| 571 | } |
| 572 | |
| 573 | /* Parity and stop bits. */ |
| 574 | if (termios->c_cflag & CSTOPB) |
| 575 | mode2 |= M_DUART_STOP_BIT_LEN_2; |
| 576 | else |
| 577 | mode2 |= M_DUART_STOP_BIT_LEN_1; |
| 578 | if (termios->c_cflag & PARENB) |
| 579 | mode1 |= V_DUART_PARITY_MODE_ADD; |
| 580 | else |
| 581 | mode1 |= V_DUART_PARITY_MODE_NONE; |
| 582 | if (termios->c_cflag & PARODD) |
| 583 | mode1 |= M_DUART_PARITY_TYPE_ODD; |
| 584 | else |
| 585 | mode1 |= M_DUART_PARITY_TYPE_EVEN; |
| 586 | |
| 587 | baud = uart_get_baud_rate(uport, termios, old_termios, 1200, 5000000); |
| 588 | brg = V_DUART_BAUD_RATE(baud); |
| 589 | /* The actual lower bound is 1221bps, so compensate. */ |
| 590 | if (brg > M_DUART_CLK_COUNTER) |
| 591 | brg = M_DUART_CLK_COUNTER; |
| 592 | |
| 593 | uart_update_timeout(uport, termios->c_cflag, baud); |
| 594 | |
| 595 | uport->read_status_mask = M_DUART_OVRUN_ERR; |
| 596 | if (termios->c_iflag & INPCK) |
| 597 | uport->read_status_mask |= M_DUART_FRM_ERR | |
| 598 | M_DUART_PARITY_ERR; |
| 599 | if (termios->c_iflag & (BRKINT | PARMRK)) |
| 600 | uport->read_status_mask |= M_DUART_RCVD_BRK; |
| 601 | |
| 602 | uport->ignore_status_mask = 0; |
| 603 | if (termios->c_iflag & IGNPAR) |
| 604 | uport->ignore_status_mask |= M_DUART_FRM_ERR | |
| 605 | M_DUART_PARITY_ERR; |
| 606 | if (termios->c_iflag & IGNBRK) { |
| 607 | uport->ignore_status_mask |= M_DUART_RCVD_BRK; |
| 608 | if (termios->c_iflag & IGNPAR) |
| 609 | uport->ignore_status_mask |= M_DUART_OVRUN_ERR; |
| 610 | } |
| 611 | |
| 612 | if (termios->c_cflag & CREAD) |
| 613 | command = M_DUART_RX_EN; |
| 614 | else |
| 615 | command = M_DUART_RX_DIS; |
| 616 | |
| 617 | if (termios->c_cflag & CRTSCTS) |
| 618 | aux |= M_DUART_CTS_CHNG_ENA; |
| 619 | else |
| 620 | aux &= ~M_DUART_CTS_CHNG_ENA; |
| 621 | |
| 622 | spin_lock(&uport->lock); |
| 623 | |
| 624 | if (sport->tx_stopped) |
| 625 | command |= M_DUART_TX_DIS; |
| 626 | else |
| 627 | command |= M_DUART_TX_EN; |
| 628 | |
| 629 | oldmode1 = read_sbdchn(sport, R_DUART_MODE_REG_1) & mode1mask; |
| 630 | oldmode2 = read_sbdchn(sport, R_DUART_MODE_REG_2) & mode2mask; |
| 631 | oldaux = read_sbdchn(sport, R_DUART_AUXCTL_X) & auxmask; |
| 632 | |
| 633 | if (!sport->tx_stopped) |
| 634 | sbd_line_drain(sport); |
| 635 | write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS | M_DUART_RX_DIS); |
| 636 | |
| 637 | write_sbdchn(sport, R_DUART_MODE_REG_1, mode1 | oldmode1); |
| 638 | write_sbdchn(sport, R_DUART_MODE_REG_2, mode2 | oldmode2); |
| 639 | write_sbdchn(sport, R_DUART_CLK_SEL, brg); |
| 640 | write_sbdchn(sport, R_DUART_AUXCTL_X, aux | oldaux); |
| 641 | |
| 642 | write_sbdchn(sport, R_DUART_CMD, command); |
| 643 | |
| 644 | spin_unlock(&uport->lock); |
| 645 | } |
| 646 | |
| 647 | |
| 648 | static const char *sbd_type(struct uart_port *uport) |
| 649 | { |
| 650 | return "SB1250 DUART"; |
| 651 | } |
| 652 | |
| 653 | static void sbd_release_port(struct uart_port *uport) |
| 654 | { |
| 655 | struct sbd_port *sport = to_sport(uport); |
| 656 | struct sbd_duart *duart = sport->duart; |
| 657 | int map_guard; |
| 658 | |
| 659 | iounmap(sport->memctrl); |
| 660 | sport->memctrl = NULL; |
| 661 | iounmap(uport->membase); |
| 662 | uport->membase = NULL; |
| 663 | |
| 664 | map_guard = atomic_add_return(-1, &duart->map_guard); |
| 665 | if (!map_guard) |
| 666 | release_mem_region(duart->mapctrl, DUART_CHANREG_SPACING); |
| 667 | release_mem_region(uport->mapbase, DUART_CHANREG_SPACING); |
| 668 | } |
| 669 | |
| 670 | static int sbd_map_port(struct uart_port *uport) |
| 671 | { |
Maciej W. Rozycki | 86d0004 | 2007-07-31 00:39:22 -0700 | [diff] [blame] | 672 | const char *err = KERN_ERR "sbd: Cannot map MMIO\n"; |
Maciej W. Rozycki | b45d527 | 2007-07-17 04:03:50 -0700 | [diff] [blame] | 673 | struct sbd_port *sport = to_sport(uport); |
| 674 | struct sbd_duart *duart = sport->duart; |
| 675 | |
| 676 | if (!uport->membase) |
| 677 | uport->membase = ioremap_nocache(uport->mapbase, |
| 678 | DUART_CHANREG_SPACING); |
| 679 | if (!uport->membase) { |
| 680 | printk(err); |
| 681 | return -ENOMEM; |
| 682 | } |
| 683 | |
| 684 | if (!sport->memctrl) |
| 685 | sport->memctrl = ioremap_nocache(duart->mapctrl, |
| 686 | DUART_CHANREG_SPACING); |
| 687 | if (!sport->memctrl) { |
| 688 | printk(err); |
| 689 | iounmap(uport->membase); |
| 690 | uport->membase = NULL; |
| 691 | return -ENOMEM; |
| 692 | } |
| 693 | |
| 694 | return 0; |
| 695 | } |
| 696 | |
| 697 | static int sbd_request_port(struct uart_port *uport) |
| 698 | { |
Maciej W. Rozycki | 86d0004 | 2007-07-31 00:39:22 -0700 | [diff] [blame] | 699 | const char *err = KERN_ERR "sbd: Unable to reserve MMIO resource\n"; |
Maciej W. Rozycki | b45d527 | 2007-07-17 04:03:50 -0700 | [diff] [blame] | 700 | struct sbd_duart *duart = to_sport(uport)->duart; |
| 701 | int map_guard; |
| 702 | int ret = 0; |
| 703 | |
| 704 | if (!request_mem_region(uport->mapbase, DUART_CHANREG_SPACING, |
| 705 | "sb1250-duart")) { |
| 706 | printk(err); |
| 707 | return -EBUSY; |
| 708 | } |
| 709 | map_guard = atomic_add_return(1, &duart->map_guard); |
| 710 | if (map_guard == 1) { |
| 711 | if (!request_mem_region(duart->mapctrl, DUART_CHANREG_SPACING, |
| 712 | "sb1250-duart")) { |
| 713 | atomic_add(-1, &duart->map_guard); |
| 714 | printk(err); |
| 715 | ret = -EBUSY; |
| 716 | } |
| 717 | } |
| 718 | if (!ret) { |
| 719 | ret = sbd_map_port(uport); |
| 720 | if (ret) { |
| 721 | map_guard = atomic_add_return(-1, &duart->map_guard); |
| 722 | if (!map_guard) |
| 723 | release_mem_region(duart->mapctrl, |
| 724 | DUART_CHANREG_SPACING); |
| 725 | } |
| 726 | } |
| 727 | if (ret) { |
| 728 | release_mem_region(uport->mapbase, DUART_CHANREG_SPACING); |
| 729 | return ret; |
| 730 | } |
| 731 | return 0; |
| 732 | } |
| 733 | |
| 734 | static void sbd_config_port(struct uart_port *uport, int flags) |
| 735 | { |
| 736 | struct sbd_port *sport = to_sport(uport); |
| 737 | |
| 738 | if (flags & UART_CONFIG_TYPE) { |
| 739 | if (sbd_request_port(uport)) |
| 740 | return; |
| 741 | |
| 742 | uport->type = PORT_SB1250_DUART; |
| 743 | |
| 744 | sbd_init_port(sport); |
| 745 | } |
| 746 | } |
| 747 | |
| 748 | static int sbd_verify_port(struct uart_port *uport, struct serial_struct *ser) |
| 749 | { |
| 750 | int ret = 0; |
| 751 | |
| 752 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_SB1250_DUART) |
| 753 | ret = -EINVAL; |
| 754 | if (ser->irq != uport->irq) |
| 755 | ret = -EINVAL; |
| 756 | if (ser->baud_base != uport->uartclk / 16) |
| 757 | ret = -EINVAL; |
| 758 | return ret; |
| 759 | } |
| 760 | |
| 761 | |
Maciej W. Rozycki | 86d0004 | 2007-07-31 00:39:22 -0700 | [diff] [blame] | 762 | static const struct uart_ops sbd_ops = { |
Maciej W. Rozycki | b45d527 | 2007-07-17 04:03:50 -0700 | [diff] [blame] | 763 | .tx_empty = sbd_tx_empty, |
| 764 | .set_mctrl = sbd_set_mctrl, |
| 765 | .get_mctrl = sbd_get_mctrl, |
| 766 | .stop_tx = sbd_stop_tx, |
| 767 | .start_tx = sbd_start_tx, |
| 768 | .stop_rx = sbd_stop_rx, |
| 769 | .enable_ms = sbd_enable_ms, |
| 770 | .break_ctl = sbd_break_ctl, |
| 771 | .startup = sbd_startup, |
| 772 | .shutdown = sbd_shutdown, |
| 773 | .set_termios = sbd_set_termios, |
| 774 | .type = sbd_type, |
| 775 | .release_port = sbd_release_port, |
| 776 | .request_port = sbd_request_port, |
| 777 | .config_port = sbd_config_port, |
| 778 | .verify_port = sbd_verify_port, |
| 779 | }; |
| 780 | |
| 781 | /* Initialize SB1250 DUART port structures. */ |
| 782 | static void __init sbd_probe_duarts(void) |
| 783 | { |
| 784 | static int probed; |
| 785 | int chip, side; |
| 786 | int max_lines, line; |
| 787 | |
| 788 | if (probed) |
| 789 | return; |
| 790 | |
| 791 | /* Set the number of available units based on the SOC type. */ |
| 792 | switch (soc_type) { |
| 793 | case K_SYS_SOC_TYPE_BCM1x55: |
| 794 | case K_SYS_SOC_TYPE_BCM1x80: |
| 795 | max_lines = 4; |
| 796 | break; |
| 797 | default: |
| 798 | /* Assume at least two serial ports at the normal address. */ |
| 799 | max_lines = 2; |
| 800 | break; |
| 801 | } |
| 802 | |
| 803 | probed = 1; |
| 804 | |
| 805 | for (chip = 0, line = 0; chip < DUART_MAX_CHIP && line < max_lines; |
| 806 | chip++) { |
| 807 | sbd_duarts[chip].mapctrl = SBD_CTRLREGS(line); |
| 808 | |
| 809 | for (side = 0; side < DUART_MAX_SIDE && line < max_lines; |
| 810 | side++, line++) { |
| 811 | struct sbd_port *sport = &sbd_duarts[chip].sport[side]; |
| 812 | struct uart_port *uport = &sport->port; |
| 813 | |
| 814 | sport->duart = &sbd_duarts[chip]; |
| 815 | |
| 816 | uport->irq = SBD_INT(line); |
| 817 | uport->uartclk = 100000000 / 20 * 16; |
| 818 | uport->fifosize = 16; |
| 819 | uport->iotype = UPIO_MEM; |
| 820 | uport->flags = UPF_BOOT_AUTOCONF; |
| 821 | uport->ops = &sbd_ops; |
| 822 | uport->line = line; |
| 823 | uport->mapbase = SBD_CHANREGS(line); |
| 824 | } |
| 825 | } |
| 826 | } |
| 827 | |
| 828 | |
| 829 | #ifdef CONFIG_SERIAL_SB1250_DUART_CONSOLE |
| 830 | /* |
| 831 | * Serial console stuff. Very basic, polling driver for doing serial |
| 832 | * console output. The console_sem is held by the caller, so we |
| 833 | * shouldn't be interrupted for more console activity. |
| 834 | */ |
| 835 | static void sbd_console_putchar(struct uart_port *uport, int ch) |
| 836 | { |
| 837 | struct sbd_port *sport = to_sport(uport); |
| 838 | |
| 839 | sbd_transmit_drain(sport); |
| 840 | write_sbdchn(sport, R_DUART_TX_HOLD, ch); |
| 841 | } |
| 842 | |
| 843 | static void sbd_console_write(struct console *co, const char *s, |
| 844 | unsigned int count) |
| 845 | { |
| 846 | int chip = co->index / DUART_MAX_SIDE; |
| 847 | int side = co->index % DUART_MAX_SIDE; |
| 848 | struct sbd_port *sport = &sbd_duarts[chip].sport[side]; |
| 849 | struct uart_port *uport = &sport->port; |
| 850 | unsigned long flags; |
| 851 | unsigned int mask; |
| 852 | |
| 853 | /* Disable transmit interrupts and enable the transmitter. */ |
| 854 | spin_lock_irqsave(&uport->lock, flags); |
| 855 | mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2)); |
| 856 | write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), |
| 857 | mask & ~M_DUART_IMR_TX); |
| 858 | write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_EN); |
| 859 | spin_unlock_irqrestore(&uport->lock, flags); |
| 860 | |
| 861 | uart_console_write(&sport->port, s, count, sbd_console_putchar); |
| 862 | |
| 863 | /* Restore transmit interrupts and the transmitter enable. */ |
| 864 | spin_lock_irqsave(&uport->lock, flags); |
| 865 | sbd_line_drain(sport); |
| 866 | if (sport->tx_stopped) |
| 867 | write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS); |
| 868 | write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask); |
| 869 | spin_unlock_irqrestore(&uport->lock, flags); |
| 870 | } |
| 871 | |
| 872 | static int __init sbd_console_setup(struct console *co, char *options) |
| 873 | { |
| 874 | int chip = co->index / DUART_MAX_SIDE; |
| 875 | int side = co->index % DUART_MAX_SIDE; |
| 876 | struct sbd_port *sport = &sbd_duarts[chip].sport[side]; |
| 877 | struct uart_port *uport = &sport->port; |
| 878 | int baud = 115200; |
| 879 | int bits = 8; |
| 880 | int parity = 'n'; |
| 881 | int flow = 'n'; |
| 882 | int ret; |
| 883 | |
| 884 | if (!sport->duart) |
| 885 | return -ENXIO; |
| 886 | |
| 887 | ret = sbd_map_port(uport); |
| 888 | if (ret) |
| 889 | return ret; |
| 890 | |
| 891 | sbd_init_port(sport); |
| 892 | |
| 893 | if (options) |
| 894 | uart_parse_options(options, &baud, &parity, &bits, &flow); |
| 895 | return uart_set_options(uport, co, baud, parity, bits, flow); |
| 896 | } |
| 897 | |
| 898 | static struct uart_driver sbd_reg; |
| 899 | static struct console sbd_console = { |
| 900 | .name = "duart", |
| 901 | .write = sbd_console_write, |
| 902 | .device = uart_console_device, |
| 903 | .setup = sbd_console_setup, |
| 904 | .flags = CON_PRINTBUFFER, |
| 905 | .index = -1, |
| 906 | .data = &sbd_reg |
| 907 | }; |
| 908 | |
| 909 | static int __init sbd_serial_console_init(void) |
| 910 | { |
| 911 | sbd_probe_duarts(); |
| 912 | register_console(&sbd_console); |
| 913 | |
| 914 | return 0; |
| 915 | } |
| 916 | |
| 917 | console_initcall(sbd_serial_console_init); |
| 918 | |
| 919 | #define SERIAL_SB1250_DUART_CONSOLE &sbd_console |
| 920 | #else |
| 921 | #define SERIAL_SB1250_DUART_CONSOLE NULL |
| 922 | #endif /* CONFIG_SERIAL_SB1250_DUART_CONSOLE */ |
| 923 | |
| 924 | |
| 925 | static struct uart_driver sbd_reg = { |
| 926 | .owner = THIS_MODULE, |
| 927 | .driver_name = "serial", |
| 928 | .dev_name = "duart", |
| 929 | .major = TTY_MAJOR, |
| 930 | .minor = SB1250_DUART_MINOR_BASE, |
| 931 | .nr = DUART_MAX_CHIP * DUART_MAX_SIDE, |
| 932 | .cons = SERIAL_SB1250_DUART_CONSOLE, |
| 933 | }; |
| 934 | |
| 935 | /* Set up the driver and register it. */ |
| 936 | static int __init sbd_init(void) |
| 937 | { |
| 938 | int i, ret; |
| 939 | |
| 940 | sbd_probe_duarts(); |
| 941 | |
| 942 | ret = uart_register_driver(&sbd_reg); |
| 943 | if (ret) |
| 944 | return ret; |
| 945 | |
| 946 | for (i = 0; i < DUART_MAX_CHIP * DUART_MAX_SIDE; i++) { |
| 947 | struct sbd_duart *duart = &sbd_duarts[i / DUART_MAX_SIDE]; |
| 948 | struct sbd_port *sport = &duart->sport[i % DUART_MAX_SIDE]; |
| 949 | struct uart_port *uport = &sport->port; |
| 950 | |
| 951 | if (sport->duart) |
| 952 | uart_add_one_port(&sbd_reg, uport); |
| 953 | } |
| 954 | |
| 955 | return 0; |
| 956 | } |
| 957 | |
| 958 | /* Unload the driver. Unregister stuff, get ready to go away. */ |
| 959 | static void __exit sbd_exit(void) |
| 960 | { |
| 961 | int i; |
| 962 | |
| 963 | for (i = DUART_MAX_CHIP * DUART_MAX_SIDE - 1; i >= 0; i--) { |
| 964 | struct sbd_duart *duart = &sbd_duarts[i / DUART_MAX_SIDE]; |
| 965 | struct sbd_port *sport = &duart->sport[i % DUART_MAX_SIDE]; |
| 966 | struct uart_port *uport = &sport->port; |
| 967 | |
| 968 | if (sport->duart) |
| 969 | uart_remove_one_port(&sbd_reg, uport); |
| 970 | } |
| 971 | |
| 972 | uart_unregister_driver(&sbd_reg); |
| 973 | } |
| 974 | |
| 975 | module_init(sbd_init); |
| 976 | module_exit(sbd_exit); |