blob: 88c362651445c7bf4259fd251f9a9f3b748cd9fa [file] [log] [blame]
eric miao8f58de72007-12-19 17:14:02 +08001#include <linux/module.h>
2#include <linux/kernel.h>
3#include <linux/init.h>
4#include <linux/platform_device.h>
5#include <linux/dma-mapping.h>
6
Eric Miao80796f22008-11-25 11:03:03 +08007#include <mach/pxa-regs.h>
Russell Kinga09e64f2008-08-05 16:14:15 +01008#include <mach/udc.h>
9#include <mach/pxafb.h>
10#include <mach/mmc.h>
11#include <mach/irda.h>
12#include <mach/i2c.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010013#include <mach/ohci.h>
14#include <mach/pxa27x_keypad.h>
15#include <mach/pxa2xx_spi.h>
16#include <mach/camera.h>
17#include <mach/audio.h>
18#include <mach/pxa3xx_nand.h>
eric miao8f58de72007-12-19 17:14:02 +080019
20#include "devices.h"
Philipp Zabelbc3a5952008-06-02 18:49:27 +010021#include "generic.h"
eric miao8f58de72007-12-19 17:14:02 +080022
23void __init pxa_register_device(struct platform_device *dev, void *data)
24{
25 int ret;
26
27 dev->dev.platform_data = data;
28
29 ret = platform_device_register(dev);
30 if (ret)
31 dev_err(&dev->dev, "unable to register device: %d\n", ret);
32}
33
34static struct resource pxamci_resources[] = {
35 [0] = {
36 .start = 0x41100000,
37 .end = 0x41100fff,
38 .flags = IORESOURCE_MEM,
39 },
40 [1] = {
41 .start = IRQ_MMC,
42 .end = IRQ_MMC,
43 .flags = IORESOURCE_IRQ,
44 },
45 [2] = {
46 .start = 21,
47 .end = 21,
48 .flags = IORESOURCE_DMA,
49 },
50 [3] = {
51 .start = 22,
52 .end = 22,
53 .flags = IORESOURCE_DMA,
54 },
55};
56
57static u64 pxamci_dmamask = 0xffffffffUL;
58
59struct platform_device pxa_device_mci = {
60 .name = "pxa2xx-mci",
Bridge Wufafc9d32007-12-21 19:00:13 +080061 .id = 0,
eric miao8f58de72007-12-19 17:14:02 +080062 .dev = {
63 .dma_mask = &pxamci_dmamask,
64 .coherent_dma_mask = 0xffffffff,
65 },
66 .num_resources = ARRAY_SIZE(pxamci_resources),
67 .resource = pxamci_resources,
68};
69
70void __init pxa_set_mci_info(struct pxamci_platform_data *info)
71{
72 pxa_register_device(&pxa_device_mci, info);
73}
74
75
76static struct pxa2xx_udc_mach_info pxa_udc_info;
77
78void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
79{
80 memcpy(&pxa_udc_info, info, sizeof *info);
81}
82
83static struct resource pxa2xx_udc_resources[] = {
84 [0] = {
85 .start = 0x40600000,
86 .end = 0x4060ffff,
87 .flags = IORESOURCE_MEM,
88 },
89 [1] = {
90 .start = IRQ_USB,
91 .end = IRQ_USB,
92 .flags = IORESOURCE_IRQ,
93 },
94};
95
96static u64 udc_dma_mask = ~(u32)0;
97
Philipp Zabel7a857622008-06-22 23:36:39 +010098struct platform_device pxa25x_device_udc = {
99 .name = "pxa25x-udc",
100 .id = -1,
101 .resource = pxa2xx_udc_resources,
102 .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
103 .dev = {
104 .platform_data = &pxa_udc_info,
105 .dma_mask = &udc_dma_mask,
106 }
107};
108
109struct platform_device pxa27x_device_udc = {
110 .name = "pxa27x-udc",
eric miao8f58de72007-12-19 17:14:02 +0800111 .id = -1,
112 .resource = pxa2xx_udc_resources,
113 .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
114 .dev = {
115 .platform_data = &pxa_udc_info,
116 .dma_mask = &udc_dma_mask,
117 }
118};
119
120static struct resource pxafb_resources[] = {
121 [0] = {
122 .start = 0x44000000,
123 .end = 0x4400ffff,
124 .flags = IORESOURCE_MEM,
125 },
126 [1] = {
127 .start = IRQ_LCD,
128 .end = IRQ_LCD,
129 .flags = IORESOURCE_IRQ,
130 },
131};
132
133static u64 fb_dma_mask = ~(u64)0;
134
135struct platform_device pxa_device_fb = {
136 .name = "pxa2xx-fb",
137 .id = -1,
138 .dev = {
139 .dma_mask = &fb_dma_mask,
140 .coherent_dma_mask = 0xffffffff,
141 },
142 .num_resources = ARRAY_SIZE(pxafb_resources),
143 .resource = pxafb_resources,
144};
145
146void __init set_pxa_fb_info(struct pxafb_mach_info *info)
147{
148 pxa_register_device(&pxa_device_fb, info);
149}
150
151void __init set_pxa_fb_parent(struct device *parent_dev)
152{
153 pxa_device_fb.dev.parent = parent_dev;
154}
155
156static struct resource pxa_resource_ffuart[] = {
157 {
Eric Miao02f65262008-11-28 14:08:53 +0800158 .start = 0x40100000,
159 .end = 0x40100023,
eric miao8f58de72007-12-19 17:14:02 +0800160 .flags = IORESOURCE_MEM,
161 }, {
162 .start = IRQ_FFUART,
163 .end = IRQ_FFUART,
164 .flags = IORESOURCE_IRQ,
165 }
166};
167
168struct platform_device pxa_device_ffuart= {
169 .name = "pxa2xx-uart",
170 .id = 0,
171 .resource = pxa_resource_ffuart,
172 .num_resources = ARRAY_SIZE(pxa_resource_ffuart),
173};
174
175static struct resource pxa_resource_btuart[] = {
176 {
Eric Miao02f65262008-11-28 14:08:53 +0800177 .start = 0x40200000,
178 .end = 0x40200023,
eric miao8f58de72007-12-19 17:14:02 +0800179 .flags = IORESOURCE_MEM,
180 }, {
181 .start = IRQ_BTUART,
182 .end = IRQ_BTUART,
183 .flags = IORESOURCE_IRQ,
184 }
185};
186
187struct platform_device pxa_device_btuart = {
188 .name = "pxa2xx-uart",
189 .id = 1,
190 .resource = pxa_resource_btuart,
191 .num_resources = ARRAY_SIZE(pxa_resource_btuart),
192};
193
194static struct resource pxa_resource_stuart[] = {
195 {
Eric Miao02f65262008-11-28 14:08:53 +0800196 .start = 0x40700000,
197 .end = 0x40700023,
eric miao8f58de72007-12-19 17:14:02 +0800198 .flags = IORESOURCE_MEM,
199 }, {
200 .start = IRQ_STUART,
201 .end = IRQ_STUART,
202 .flags = IORESOURCE_IRQ,
203 }
204};
205
206struct platform_device pxa_device_stuart = {
207 .name = "pxa2xx-uart",
208 .id = 2,
209 .resource = pxa_resource_stuart,
210 .num_resources = ARRAY_SIZE(pxa_resource_stuart),
211};
212
213static struct resource pxa_resource_hwuart[] = {
214 {
Eric Miao02f65262008-11-28 14:08:53 +0800215 .start = 0x41600000,
216 .end = 0x4160002F,
eric miao8f58de72007-12-19 17:14:02 +0800217 .flags = IORESOURCE_MEM,
218 }, {
219 .start = IRQ_HWUART,
220 .end = IRQ_HWUART,
221 .flags = IORESOURCE_IRQ,
222 }
223};
224
225struct platform_device pxa_device_hwuart = {
226 .name = "pxa2xx-uart",
227 .id = 3,
228 .resource = pxa_resource_hwuart,
229 .num_resources = ARRAY_SIZE(pxa_resource_hwuart),
230};
231
232static struct resource pxai2c_resources[] = {
233 {
234 .start = 0x40301680,
235 .end = 0x403016a3,
236 .flags = IORESOURCE_MEM,
237 }, {
238 .start = IRQ_I2C,
239 .end = IRQ_I2C,
240 .flags = IORESOURCE_IRQ,
241 },
242};
243
244struct platform_device pxa_device_i2c = {
245 .name = "pxa2xx-i2c",
246 .id = 0,
247 .resource = pxai2c_resources,
248 .num_resources = ARRAY_SIZE(pxai2c_resources),
249};
250
251void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
252{
253 pxa_register_device(&pxa_device_i2c, info);
254}
255
Eric Miao99464292008-11-28 15:01:55 +0800256#ifdef CONFIG_PXA27x
257static struct resource pxa27x_resources_i2c_power[] = {
258 {
259 .start = 0x40f00180,
260 .end = 0x40f001a3,
261 .flags = IORESOURCE_MEM,
262 }, {
263 .start = IRQ_PWRI2C,
264 .end = IRQ_PWRI2C,
265 .flags = IORESOURCE_IRQ,
266 },
267};
268
269struct platform_device pxa27x_device_i2c_power = {
270 .name = "pxa2xx-i2c",
271 .id = 1,
272 .resource = pxa27x_resources_i2c_power,
273 .num_resources = ARRAY_SIZE(pxa27x_resources_i2c_power),
274};
275#endif
276
277#ifdef CONFIG_PXA3xx
278static struct resource pxa3xx_resources_i2c_power[] = {
279 {
280 .start = 0x40f500c0,
281 .end = 0x40f500d3,
282 .flags = IORESOURCE_MEM,
283 }, {
284 .start = IRQ_PWRI2C,
285 .end = IRQ_PWRI2C,
286 .flags = IORESOURCE_IRQ,
287 },
288};
289
290struct platform_device pxa3xx_device_i2c_power = {
291 .name = "pxa2xx-i2c",
292 .id = 1,
293 .resource = pxa3xx_resources_i2c_power,
294 .num_resources = ARRAY_SIZE(pxa3xx_resources_i2c_power),
295};
296#endif
297
eric miao8f58de72007-12-19 17:14:02 +0800298static struct resource pxai2s_resources[] = {
299 {
300 .start = 0x40400000,
301 .end = 0x40400083,
302 .flags = IORESOURCE_MEM,
303 }, {
304 .start = IRQ_I2S,
305 .end = IRQ_I2S,
306 .flags = IORESOURCE_IRQ,
307 },
308};
309
310struct platform_device pxa_device_i2s = {
311 .name = "pxa2xx-i2s",
312 .id = -1,
313 .resource = pxai2s_resources,
314 .num_resources = ARRAY_SIZE(pxai2s_resources),
315};
316
317static u64 pxaficp_dmamask = ~(u32)0;
318
319struct platform_device pxa_device_ficp = {
320 .name = "pxa2xx-ir",
321 .id = -1,
322 .dev = {
323 .dma_mask = &pxaficp_dmamask,
324 .coherent_dma_mask = 0xffffffff,
325 },
326};
327
328void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
329{
330 pxa_register_device(&pxa_device_ficp, info);
331}
332
333struct platform_device pxa_device_rtc = {
334 .name = "sa1100-rtc",
335 .id = -1,
336};
337
Mark Brown9f19d632008-06-10 12:30:05 +0100338static struct resource pxa_ac97_resources[] = {
339 [0] = {
340 .start = 0x40500000,
341 .end = 0x40500000 + 0xfff,
342 .flags = IORESOURCE_MEM,
343 },
344 [1] = {
345 .start = IRQ_AC97,
346 .end = IRQ_AC97,
347 .flags = IORESOURCE_IRQ,
348 },
349};
350
351static u64 pxa_ac97_dmamask = 0xffffffffUL;
352
353struct platform_device pxa_device_ac97 = {
354 .name = "pxa2xx-ac97",
355 .id = -1,
356 .dev = {
357 .dma_mask = &pxa_ac97_dmamask,
358 .coherent_dma_mask = 0xffffffff,
359 },
360 .num_resources = ARRAY_SIZE(pxa_ac97_resources),
361 .resource = pxa_ac97_resources,
362};
363
364void __init pxa_set_ac97_info(pxa2xx_audio_ops_t *ops)
365{
366 pxa_register_device(&pxa_device_ac97, ops);
367}
368
eric miao8f58de72007-12-19 17:14:02 +0800369#ifdef CONFIG_PXA25x
370
eric miao75540c12008-04-13 21:44:04 +0100371static struct resource pxa25x_resource_pwm0[] = {
372 [0] = {
373 .start = 0x40b00000,
374 .end = 0x40b0000f,
375 .flags = IORESOURCE_MEM,
376 },
377};
378
379struct platform_device pxa25x_device_pwm0 = {
380 .name = "pxa25x-pwm",
381 .id = 0,
382 .resource = pxa25x_resource_pwm0,
383 .num_resources = ARRAY_SIZE(pxa25x_resource_pwm0),
384};
385
386static struct resource pxa25x_resource_pwm1[] = {
387 [0] = {
388 .start = 0x40c00000,
389 .end = 0x40c0000f,
390 .flags = IORESOURCE_MEM,
391 },
392};
393
394struct platform_device pxa25x_device_pwm1 = {
395 .name = "pxa25x-pwm",
396 .id = 1,
397 .resource = pxa25x_resource_pwm1,
398 .num_resources = ARRAY_SIZE(pxa25x_resource_pwm1),
399};
400
eric miao8f58de72007-12-19 17:14:02 +0800401static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
402
403static struct resource pxa25x_resource_ssp[] = {
404 [0] = {
405 .start = 0x41000000,
406 .end = 0x4100001f,
407 .flags = IORESOURCE_MEM,
408 },
409 [1] = {
410 .start = IRQ_SSP,
411 .end = IRQ_SSP,
412 .flags = IORESOURCE_IRQ,
413 },
414 [2] = {
415 /* DRCMR for RX */
416 .start = 13,
417 .end = 13,
418 .flags = IORESOURCE_DMA,
419 },
420 [3] = {
421 /* DRCMR for TX */
422 .start = 14,
423 .end = 14,
424 .flags = IORESOURCE_DMA,
425 },
426};
427
428struct platform_device pxa25x_device_ssp = {
429 .name = "pxa25x-ssp",
430 .id = 0,
431 .dev = {
432 .dma_mask = &pxa25x_ssp_dma_mask,
433 .coherent_dma_mask = DMA_BIT_MASK(32),
434 },
435 .resource = pxa25x_resource_ssp,
436 .num_resources = ARRAY_SIZE(pxa25x_resource_ssp),
437};
438
439static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
440
441static struct resource pxa25x_resource_nssp[] = {
442 [0] = {
443 .start = 0x41400000,
444 .end = 0x4140002f,
445 .flags = IORESOURCE_MEM,
446 },
447 [1] = {
448 .start = IRQ_NSSP,
449 .end = IRQ_NSSP,
450 .flags = IORESOURCE_IRQ,
451 },
452 [2] = {
453 /* DRCMR for RX */
454 .start = 15,
455 .end = 15,
456 .flags = IORESOURCE_DMA,
457 },
458 [3] = {
459 /* DRCMR for TX */
460 .start = 16,
461 .end = 16,
462 .flags = IORESOURCE_DMA,
463 },
464};
465
466struct platform_device pxa25x_device_nssp = {
467 .name = "pxa25x-nssp",
468 .id = 1,
469 .dev = {
470 .dma_mask = &pxa25x_nssp_dma_mask,
471 .coherent_dma_mask = DMA_BIT_MASK(32),
472 },
473 .resource = pxa25x_resource_nssp,
474 .num_resources = ARRAY_SIZE(pxa25x_resource_nssp),
475};
476
477static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
478
479static struct resource pxa25x_resource_assp[] = {
480 [0] = {
481 .start = 0x41500000,
482 .end = 0x4150002f,
483 .flags = IORESOURCE_MEM,
484 },
485 [1] = {
486 .start = IRQ_ASSP,
487 .end = IRQ_ASSP,
488 .flags = IORESOURCE_IRQ,
489 },
490 [2] = {
491 /* DRCMR for RX */
492 .start = 23,
493 .end = 23,
494 .flags = IORESOURCE_DMA,
495 },
496 [3] = {
497 /* DRCMR for TX */
498 .start = 24,
499 .end = 24,
500 .flags = IORESOURCE_DMA,
501 },
502};
503
504struct platform_device pxa25x_device_assp = {
505 /* ASSP is basically equivalent to NSSP */
506 .name = "pxa25x-nssp",
507 .id = 2,
508 .dev = {
509 .dma_mask = &pxa25x_assp_dma_mask,
510 .coherent_dma_mask = DMA_BIT_MASK(32),
511 },
512 .resource = pxa25x_resource_assp,
513 .num_resources = ARRAY_SIZE(pxa25x_resource_assp),
514};
515#endif /* CONFIG_PXA25x */
516
517#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
518
eric miao37320982008-01-23 13:39:13 +0800519static struct resource pxa27x_resource_keypad[] = {
520 [0] = {
521 .start = 0x41500000,
522 .end = 0x4150004c,
523 .flags = IORESOURCE_MEM,
524 },
525 [1] = {
526 .start = IRQ_KEYPAD,
527 .end = IRQ_KEYPAD,
528 .flags = IORESOURCE_IRQ,
529 },
530};
531
532struct platform_device pxa27x_device_keypad = {
533 .name = "pxa27x-keypad",
534 .id = -1,
535 .resource = pxa27x_resource_keypad,
536 .num_resources = ARRAY_SIZE(pxa27x_resource_keypad),
537};
538
539void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
540{
541 pxa_register_device(&pxa27x_device_keypad, info);
542}
543
eric miaoec68e452007-12-12 09:29:33 +0800544static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
545
546static struct resource pxa27x_resource_ohci[] = {
547 [0] = {
548 .start = 0x4C000000,
549 .end = 0x4C00ff6f,
550 .flags = IORESOURCE_MEM,
551 },
552 [1] = {
553 .start = IRQ_USBH1,
554 .end = IRQ_USBH1,
555 .flags = IORESOURCE_IRQ,
556 },
557};
558
559struct platform_device pxa27x_device_ohci = {
560 .name = "pxa27x-ohci",
561 .id = -1,
562 .dev = {
563 .dma_mask = &pxa27x_ohci_dma_mask,
564 .coherent_dma_mask = DMA_BIT_MASK(32),
565 },
566 .num_resources = ARRAY_SIZE(pxa27x_resource_ohci),
567 .resource = pxa27x_resource_ohci,
568};
569
570void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
571{
572 pxa_register_device(&pxa27x_device_ohci, info);
573}
574
eric miao8f58de72007-12-19 17:14:02 +0800575static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
576
577static struct resource pxa27x_resource_ssp1[] = {
578 [0] = {
579 .start = 0x41000000,
580 .end = 0x4100003f,
581 .flags = IORESOURCE_MEM,
582 },
583 [1] = {
584 .start = IRQ_SSP,
585 .end = IRQ_SSP,
586 .flags = IORESOURCE_IRQ,
587 },
588 [2] = {
589 /* DRCMR for RX */
590 .start = 13,
591 .end = 13,
592 .flags = IORESOURCE_DMA,
593 },
594 [3] = {
595 /* DRCMR for TX */
596 .start = 14,
597 .end = 14,
598 .flags = IORESOURCE_DMA,
599 },
600};
601
602struct platform_device pxa27x_device_ssp1 = {
603 .name = "pxa27x-ssp",
604 .id = 0,
605 .dev = {
606 .dma_mask = &pxa27x_ssp1_dma_mask,
607 .coherent_dma_mask = DMA_BIT_MASK(32),
608 },
609 .resource = pxa27x_resource_ssp1,
610 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
611};
612
613static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
614
615static struct resource pxa27x_resource_ssp2[] = {
616 [0] = {
617 .start = 0x41700000,
618 .end = 0x4170003f,
619 .flags = IORESOURCE_MEM,
620 },
621 [1] = {
622 .start = IRQ_SSP2,
623 .end = IRQ_SSP2,
624 .flags = IORESOURCE_IRQ,
625 },
626 [2] = {
627 /* DRCMR for RX */
628 .start = 15,
629 .end = 15,
630 .flags = IORESOURCE_DMA,
631 },
632 [3] = {
633 /* DRCMR for TX */
634 .start = 16,
635 .end = 16,
636 .flags = IORESOURCE_DMA,
637 },
638};
639
640struct platform_device pxa27x_device_ssp2 = {
641 .name = "pxa27x-ssp",
642 .id = 1,
643 .dev = {
644 .dma_mask = &pxa27x_ssp2_dma_mask,
645 .coherent_dma_mask = DMA_BIT_MASK(32),
646 },
647 .resource = pxa27x_resource_ssp2,
648 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
649};
650
651static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
652
653static struct resource pxa27x_resource_ssp3[] = {
654 [0] = {
655 .start = 0x41900000,
656 .end = 0x4190003f,
657 .flags = IORESOURCE_MEM,
658 },
659 [1] = {
660 .start = IRQ_SSP3,
661 .end = IRQ_SSP3,
662 .flags = IORESOURCE_IRQ,
663 },
664 [2] = {
665 /* DRCMR for RX */
666 .start = 66,
667 .end = 66,
668 .flags = IORESOURCE_DMA,
669 },
670 [3] = {
671 /* DRCMR for TX */
672 .start = 67,
673 .end = 67,
674 .flags = IORESOURCE_DMA,
675 },
676};
677
678struct platform_device pxa27x_device_ssp3 = {
679 .name = "pxa27x-ssp",
680 .id = 2,
681 .dev = {
682 .dma_mask = &pxa27x_ssp3_dma_mask,
683 .coherent_dma_mask = DMA_BIT_MASK(32),
684 },
685 .resource = pxa27x_resource_ssp3,
686 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
687};
Guennadi Liakhovetski3f3acef2008-04-11 22:19:45 +0200688
eric miao75540c12008-04-13 21:44:04 +0100689static struct resource pxa27x_resource_pwm0[] = {
690 [0] = {
691 .start = 0x40b00000,
692 .end = 0x40b0001f,
693 .flags = IORESOURCE_MEM,
694 },
695};
696
697struct platform_device pxa27x_device_pwm0 = {
698 .name = "pxa27x-pwm",
699 .id = 0,
700 .resource = pxa27x_resource_pwm0,
701 .num_resources = ARRAY_SIZE(pxa27x_resource_pwm0),
702};
703
704static struct resource pxa27x_resource_pwm1[] = {
705 [0] = {
706 .start = 0x40c00000,
707 .end = 0x40c0001f,
708 .flags = IORESOURCE_MEM,
709 },
710};
711
712struct platform_device pxa27x_device_pwm1 = {
713 .name = "pxa27x-pwm",
714 .id = 1,
715 .resource = pxa27x_resource_pwm1,
716 .num_resources = ARRAY_SIZE(pxa27x_resource_pwm1),
717};
718
Guennadi Liakhovetski3f3acef2008-04-11 22:19:45 +0200719static struct resource pxa27x_resource_camera[] = {
720 [0] = {
721 .start = 0x50000000,
722 .end = 0x50000fff,
723 .flags = IORESOURCE_MEM,
724 },
725 [1] = {
726 .start = IRQ_CAMERA,
727 .end = IRQ_CAMERA,
728 .flags = IORESOURCE_IRQ,
729 },
730};
731
732static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
733
734static struct platform_device pxa27x_device_camera = {
735 .name = "pxa27x-camera",
736 .id = 0, /* This is used to put cameras on this interface */
737 .dev = {
738 .dma_mask = &pxa27x_dma_mask_camera,
739 .coherent_dma_mask = 0xffffffff,
740 },
741 .num_resources = ARRAY_SIZE(pxa27x_resource_camera),
742 .resource = pxa27x_resource_camera,
743};
744
745void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
746{
747 pxa_register_device(&pxa27x_device_camera, info);
748}
eric miao8f58de72007-12-19 17:14:02 +0800749#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
750
751#ifdef CONFIG_PXA3xx
752static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
753
754static struct resource pxa3xx_resource_ssp4[] = {
755 [0] = {
756 .start = 0x41a00000,
757 .end = 0x41a0003f,
758 .flags = IORESOURCE_MEM,
759 },
760 [1] = {
761 .start = IRQ_SSP4,
762 .end = IRQ_SSP4,
763 .flags = IORESOURCE_IRQ,
764 },
765 [2] = {
766 /* DRCMR for RX */
767 .start = 2,
768 .end = 2,
769 .flags = IORESOURCE_DMA,
770 },
771 [3] = {
772 /* DRCMR for TX */
773 .start = 3,
774 .end = 3,
775 .flags = IORESOURCE_DMA,
776 },
777};
778
779struct platform_device pxa3xx_device_ssp4 = {
780 /* PXA3xx SSP is basically equivalent to PXA27x */
781 .name = "pxa27x-ssp",
782 .id = 3,
783 .dev = {
784 .dma_mask = &pxa3xx_ssp4_dma_mask,
785 .coherent_dma_mask = DMA_BIT_MASK(32),
786 },
787 .resource = pxa3xx_resource_ssp4,
788 .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
789};
Bridge Wu8d33b052007-12-21 19:15:36 +0800790
791static struct resource pxa3xx_resources_mci2[] = {
792 [0] = {
793 .start = 0x42000000,
794 .end = 0x42000fff,
795 .flags = IORESOURCE_MEM,
796 },
797 [1] = {
798 .start = IRQ_MMC2,
799 .end = IRQ_MMC2,
800 .flags = IORESOURCE_IRQ,
801 },
802 [2] = {
803 .start = 93,
804 .end = 93,
805 .flags = IORESOURCE_DMA,
806 },
807 [3] = {
808 .start = 94,
809 .end = 94,
810 .flags = IORESOURCE_DMA,
811 },
812};
813
814struct platform_device pxa3xx_device_mci2 = {
815 .name = "pxa2xx-mci",
816 .id = 1,
817 .dev = {
818 .dma_mask = &pxamci_dmamask,
819 .coherent_dma_mask = 0xffffffff,
820 },
821 .num_resources = ARRAY_SIZE(pxa3xx_resources_mci2),
822 .resource = pxa3xx_resources_mci2,
823};
824
825void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
826{
827 pxa_register_device(&pxa3xx_device_mci2, info);
828}
829
Bridge Wu5a1f21b2007-12-21 19:27:08 +0800830static struct resource pxa3xx_resources_mci3[] = {
831 [0] = {
832 .start = 0x42500000,
833 .end = 0x42500fff,
834 .flags = IORESOURCE_MEM,
835 },
836 [1] = {
837 .start = IRQ_MMC3,
838 .end = IRQ_MMC3,
839 .flags = IORESOURCE_IRQ,
840 },
841 [2] = {
842 .start = 100,
843 .end = 100,
844 .flags = IORESOURCE_DMA,
845 },
846 [3] = {
847 .start = 101,
848 .end = 101,
849 .flags = IORESOURCE_DMA,
850 },
851};
852
853struct platform_device pxa3xx_device_mci3 = {
854 .name = "pxa2xx-mci",
855 .id = 2,
856 .dev = {
857 .dma_mask = &pxamci_dmamask,
858 .coherent_dma_mask = 0xffffffff,
859 },
860 .num_resources = ARRAY_SIZE(pxa3xx_resources_mci3),
861 .resource = pxa3xx_resources_mci3,
862};
863
864void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
865{
866 pxa_register_device(&pxa3xx_device_mci3, info);
867}
868
Eric Miao9ae819a2008-06-02 15:22:03 +0800869static struct resource pxa3xx_resources_nand[] = {
870 [0] = {
871 .start = 0x43100000,
872 .end = 0x43100053,
873 .flags = IORESOURCE_MEM,
874 },
875 [1] = {
876 .start = IRQ_NAND,
877 .end = IRQ_NAND,
878 .flags = IORESOURCE_IRQ,
879 },
880 [2] = {
881 /* DRCMR for Data DMA */
882 .start = 97,
883 .end = 97,
884 .flags = IORESOURCE_DMA,
885 },
886 [3] = {
887 /* DRCMR for Command DMA */
888 .start = 99,
889 .end = 99,
890 .flags = IORESOURCE_DMA,
891 },
892};
893
894static u64 pxa3xx_nand_dma_mask = DMA_BIT_MASK(32);
895
896struct platform_device pxa3xx_device_nand = {
897 .name = "pxa3xx-nand",
898 .id = -1,
899 .dev = {
900 .dma_mask = &pxa3xx_nand_dma_mask,
901 .coherent_dma_mask = DMA_BIT_MASK(32),
902 },
903 .num_resources = ARRAY_SIZE(pxa3xx_resources_nand),
904 .resource = pxa3xx_resources_nand,
905};
906
907void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info)
908{
909 pxa_register_device(&pxa3xx_device_nand, info);
910}
eric miao8f58de72007-12-19 17:14:02 +0800911#endif /* CONFIG_PXA3xx */
Guennadi Liakhovetskie172274c2008-06-13 09:17:31 +0100912
913/* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
914 * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */
915void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info)
916{
917 struct platform_device *pd;
918
919 pd = platform_device_alloc("pxa2xx-spi", id);
920 if (pd == NULL) {
921 printk(KERN_ERR "pxa2xx-spi: failed to allocate device id %d\n",
922 id);
923 return;
924 }
925
926 pd->dev.platform_data = info;
927 platform_device_add(pd);
928}