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gerrit-public.fairphone.software / fp2-dev / kernel / msm / 746d9ab0dabf7165b88906860ed3b52b351bcfe8 / . / include / linux / msm_vidc_dec.h
blob: d127a3b752eca2475aa8b94e51b968078eb716dc [file] [log] [blame]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1#ifndef _MSM_VIDC_DEC_H_
2#define _MSM_VIDC_DEC_H_
3
4#include <linux/types.h>
5#include <linux/ioctl.h>
6
7/* STATUS CODES */
8/* Base value for status codes */
9#define VDEC_S_BASE 0x40000000
10/* Success */
11#define VDEC_S_SUCCESS (VDEC_S_BASE)
12/* General failure */
13#define VDEC_S_EFAIL (VDEC_S_BASE + 1)
14/* Fatal irrecoverable failure. Need to tear down session. */
15#define VDEC_S_EFATAL (VDEC_S_BASE + 2)
16/* Error detected in the passed parameters */
17#define VDEC_S_EBADPARAM (VDEC_S_BASE + 3)
18/* Command called in invalid state. */
19#define VDEC_S_EINVALSTATE (VDEC_S_BASE + 4)
20 /* Insufficient OS resources - thread, memory etc. */
21#define VDEC_S_ENOSWRES (VDEC_S_BASE + 5)
22 /* Insufficient HW resources - core capacity maxed out. */
23#define VDEC_S_ENOHWRES (VDEC_S_BASE + 6)
24/* Invalid command called */
25#define VDEC_S_EINVALCMD (VDEC_S_BASE + 7)
26/* Command timeout. */
27#define VDEC_S_ETIMEOUT (VDEC_S_BASE + 8)
28/* Pre-requirement is not met for API. */
29#define VDEC_S_ENOPREREQ (VDEC_S_BASE + 9)
30/* Command queue is full. */
31#define VDEC_S_ECMDQFULL (VDEC_S_BASE + 10)
32/* Command is not supported by this driver */
33#define VDEC_S_ENOTSUPP (VDEC_S_BASE + 11)
34/* Command is not implemented by thedriver. */
35#define VDEC_S_ENOTIMPL (VDEC_S_BASE + 12)
36/* Command is not implemented by the driver. */
37#define VDEC_S_BUSY (VDEC_S_BASE + 13)
Gopikrishnaiah Anandan746d9ab2011-07-07 11:55:13 -0700[diff] [blame^]38#define VDEC_S_INPUT_BITSTREAM_ERR (VDEC_S_BASE + 14)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]39
40#define VDEC_INTF_VER 1
41#define VDEC_MSG_BASE 0x0000000
42/* Codes to identify asynchronous message responses and events that driver
43 wants to communicate to the app.*/
44#define VDEC_MSG_INVALID (VDEC_MSG_BASE + 0)
45#define VDEC_MSG_RESP_INPUT_BUFFER_DONE (VDEC_MSG_BASE + 1)
46#define VDEC_MSG_RESP_OUTPUT_BUFFER_DONE (VDEC_MSG_BASE + 2)
47#define VDEC_MSG_RESP_INPUT_FLUSHED (VDEC_MSG_BASE + 3)
48#define VDEC_MSG_RESP_OUTPUT_FLUSHED (VDEC_MSG_BASE + 4)
49#define VDEC_MSG_RESP_FLUSH_INPUT_DONE (VDEC_MSG_BASE + 5)
50#define VDEC_MSG_RESP_FLUSH_OUTPUT_DONE (VDEC_MSG_BASE + 6)
51#define VDEC_MSG_RESP_START_DONE (VDEC_MSG_BASE + 7)
52#define VDEC_MSG_RESP_STOP_DONE (VDEC_MSG_BASE + 8)
53#define VDEC_MSG_RESP_PAUSE_DONE (VDEC_MSG_BASE + 9)
54#define VDEC_MSG_RESP_RESUME_DONE (VDEC_MSG_BASE + 10)
55#define VDEC_MSG_RESP_RESOURCE_LOADED (VDEC_MSG_BASE + 11)
56#define VDEC_EVT_RESOURCES_LOST (VDEC_MSG_BASE + 12)
57#define VDEC_MSG_EVT_CONFIG_CHANGED (VDEC_MSG_BASE + 13)
58#define VDEC_MSG_EVT_HW_ERROR (VDEC_MSG_BASE + 14)
59#define VDEC_MSG_EVT_INFO_CONFIG_CHANGED (VDEC_MSG_BASE + 15)
60
61/*Buffer flags bits masks.*/
62#define VDEC_BUFFERFLAG_EOS 0x00000001
63#define VDEC_BUFFERFLAG_DECODEONLY 0x00000004
64#define VDEC_BUFFERFLAG_DATACORRUPT 0x00000008
65#define VDEC_BUFFERFLAG_ENDOFFRAME 0x00000010
66#define VDEC_BUFFERFLAG_SYNCFRAME 0x00000020
67#define VDEC_BUFFERFLAG_EXTRADATA 0x00000040
68#define VDEC_BUFFERFLAG_CODECCONFIG 0x00000080
69
70/*Post processing flags bit masks*/
71#define VDEC_EXTRADATA_NONE 0x001
72#define VDEC_EXTRADATA_QP 0x004
73#define VDEC_EXTRADATA_MB_ERROR_MAP 0x008
74#define VDEC_EXTRADATA_SEI 0x010
75#define VDEC_EXTRADATA_VUI 0x020
76#define VDEC_EXTRADATA_VC1 0x040
77
78#define VDEC_CMDBASE 0x800
79#define VDEC_CMD_SET_INTF_VERSION (VDEC_CMDBASE)
80
81#define VDEC_IOCTL_MAGIC 'v'
82
83struct vdec_ioctl_msg {
84 void __user *in;
85 void __user *out;
86};
87
88/* CMD params: InputParam:enum vdec_codec
89 OutputParam: struct vdec_profile_level*/
90#define VDEC_IOCTL_GET_PROFILE_LEVEL_SUPPORTED \
91 _IOWR(VDEC_IOCTL_MAGIC, 0, struct vdec_ioctl_msg)
92
93/*CMD params:InputParam: NULL
94 OutputParam: uint32_t(bitmask)*/
95#define VDEC_IOCTL_GET_INTERLACE_FORMAT \
96 _IOR(VDEC_IOCTL_MAGIC, 1, struct vdec_ioctl_msg)
97
98/* CMD params: InputParam: enum vdec_codec
99 OutputParam: struct vdec_profile_level*/
100#define VDEC_IOCTL_GET_CURRENT_PROFILE_LEVEL \
101 _IOWR(VDEC_IOCTL_MAGIC, 2, struct vdec_ioctl_msg)
102
103/*CMD params: SET: InputParam: enum vdec_output_fromat OutputParam: NULL
104 GET: InputParam: NULL OutputParam: enum vdec_output_fromat*/
105#define VDEC_IOCTL_SET_OUTPUT_FORMAT \
106 _IOWR(VDEC_IOCTL_MAGIC, 3, struct vdec_ioctl_msg)
107#define VDEC_IOCTL_GET_OUTPUT_FORMAT \
108 _IOWR(VDEC_IOCTL_MAGIC, 4, struct vdec_ioctl_msg)
109
110/*CMD params: SET: InputParam: enum vdec_codec OutputParam: NULL
111 GET: InputParam: NULL OutputParam: enum vdec_codec*/
112#define VDEC_IOCTL_SET_CODEC \
113 _IOW(VDEC_IOCTL_MAGIC, 5, struct vdec_ioctl_msg)
114#define VDEC_IOCTL_GET_CODEC \
115 _IOR(VDEC_IOCTL_MAGIC, 6, struct vdec_ioctl_msg)
116
117/*CMD params: SET: InputParam: struct vdec_picsize outputparam: NULL
118 GET: InputParam: NULL outputparam: struct vdec_picsize*/
119#define VDEC_IOCTL_SET_PICRES \
120 _IOW(VDEC_IOCTL_MAGIC, 7, struct vdec_ioctl_msg)
121#define VDEC_IOCTL_GET_PICRES \
122 _IOR(VDEC_IOCTL_MAGIC, 8, struct vdec_ioctl_msg)
123
124#define VDEC_IOCTL_SET_EXTRADATA \
125 _IOW(VDEC_IOCTL_MAGIC, 9, struct vdec_ioctl_msg)
126#define VDEC_IOCTL_GET_EXTRADATA \
127 _IOR(VDEC_IOCTL_MAGIC, 10, struct vdec_ioctl_msg)
128
129#define VDEC_IOCTL_SET_SEQUENCE_HEADER \
130 _IOW(VDEC_IOCTL_MAGIC, 11, struct vdec_ioctl_msg)
131
132/* CMD params: SET: InputParam - vdec_allocatorproperty, OutputParam - NULL
133 GET: InputParam - NULL, OutputParam - vdec_allocatorproperty*/
134#define VDEC_IOCTL_SET_BUFFER_REQ \
135 _IOW(VDEC_IOCTL_MAGIC, 12, struct vdec_ioctl_msg)
136#define VDEC_IOCTL_GET_BUFFER_REQ \
137 _IOR(VDEC_IOCTL_MAGIC, 13, struct vdec_ioctl_msg)
138/* CMD params: InputParam - vdec_buffer, OutputParam - uint8_t** */
139#define VDEC_IOCTL_ALLOCATE_BUFFER \
140 _IOWR(VDEC_IOCTL_MAGIC, 14, struct vdec_ioctl_msg)
141/* CMD params: InputParam - uint8_t *, OutputParam - NULL.*/
142#define VDEC_IOCTL_FREE_BUFFER \
143 _IOW(VDEC_IOCTL_MAGIC, 15, struct vdec_ioctl_msg)
144
145/*CMD params: CMD: InputParam - struct vdec_setbuffer_cmd, OutputParam - NULL*/
146#define VDEC_IOCTL_SET_BUFFER \
147 _IOW(VDEC_IOCTL_MAGIC, 16, struct vdec_ioctl_msg)
148
149/* CMD params: InputParam - struct vdec_fillbuffer_cmd, OutputParam - NULL*/
150#define VDEC_IOCTL_FILL_OUTPUT_BUFFER \
151 _IOW(VDEC_IOCTL_MAGIC, 17, struct vdec_ioctl_msg)
152
153/*CMD params: InputParam - struct vdec_frameinfo , OutputParam - NULL*/
154#define VDEC_IOCTL_DECODE_FRAME \
155 _IOW(VDEC_IOCTL_MAGIC, 18, struct vdec_ioctl_msg)
156
157#define VDEC_IOCTL_LOAD_RESOURCES _IO(VDEC_IOCTL_MAGIC, 19)
158#define VDEC_IOCTL_CMD_START _IO(VDEC_IOCTL_MAGIC, 20)
159#define VDEC_IOCTL_CMD_STOP _IO(VDEC_IOCTL_MAGIC, 21)
160#define VDEC_IOCTL_CMD_PAUSE _IO(VDEC_IOCTL_MAGIC, 22)
161#define VDEC_IOCTL_CMD_RESUME _IO(VDEC_IOCTL_MAGIC, 23)
162
163/*CMD params: InputParam - enum vdec_bufferflush , OutputParam - NULL */
164#define VDEC_IOCTL_CMD_FLUSH _IOW(VDEC_IOCTL_MAGIC, 24, struct vdec_ioctl_msg)
165
166/* ========================================================
167 * IOCTL for getting asynchronous notification from driver
168 * ========================================================*/
169
170/*IOCTL params: InputParam - NULL, OutputParam - struct vdec_msginfo*/
171#define VDEC_IOCTL_GET_NEXT_MSG \
172 _IOR(VDEC_IOCTL_MAGIC, 25, struct vdec_ioctl_msg)
173
174#define VDEC_IOCTL_STOP_NEXT_MSG _IO(VDEC_IOCTL_MAGIC, 26)
175
176#define VDEC_IOCTL_GET_NUMBER_INSTANCES \
177 _IOR(VDEC_IOCTL_MAGIC, 27, struct vdec_ioctl_msg)
178
179#define VDEC_IOCTL_SET_PICTURE_ORDER \
180 _IOW(VDEC_IOCTL_MAGIC, 28, struct vdec_ioctl_msg)
181
182#define VDEC_IOCTL_SET_FRAME_RATE \
183 _IOW(VDEC_IOCTL_MAGIC, 29, struct vdec_ioctl_msg)
184
185#define VDEC_IOCTL_SET_H264_MV_BUFFER \
186 _IOW(VDEC_IOCTL_MAGIC, 30, struct vdec_ioctl_msg)
187
188#define VDEC_IOCTL_FREE_H264_MV_BUFFER \
189 _IOW(VDEC_IOCTL_MAGIC, 31, struct vdec_ioctl_msg)
190
191#define VDEC_IOCTL_GET_MV_BUFFER_SIZE \
192 _IOR(VDEC_IOCTL_MAGIC, 32, struct vdec_ioctl_msg)
193
194#define VDEC_IOCTL_SET_IDR_ONLY_DECODING \
195 _IO(VDEC_IOCTL_MAGIC, 33)
196
197#define VDEC_IOCTL_SET_CONT_ON_RECONFIG \
198 _IO(VDEC_IOCTL_MAGIC, 34)
199
200enum vdec_picture {
201 PICTURE_TYPE_I,
202 PICTURE_TYPE_P,
203 PICTURE_TYPE_B,
204 PICTURE_TYPE_BI,
205 PICTURE_TYPE_SKIP,
206 PICTURE_TYPE_UNKNOWN
207};
208
209enum vdec_buffer {
210 VDEC_BUFFER_TYPE_INPUT,
211 VDEC_BUFFER_TYPE_OUTPUT
212};
213
214struct vdec_allocatorproperty {
215 enum vdec_buffer buffer_type;
216 uint32_t mincount;
217 uint32_t maxcount;
218 uint32_t actualcount;
219 size_t buffer_size;
220 uint32_t alignment;
221 uint32_t buf_poolid;
222};
223
224struct vdec_bufferpayload {
225 void __user *bufferaddr;
226 size_t buffer_len;
227 int pmem_fd;
228 size_t offset;
229 size_t mmaped_size;
230};
231
232struct vdec_setbuffer_cmd {
233 enum vdec_buffer buffer_type;
234 struct vdec_bufferpayload buffer;
235};
236
237struct vdec_fillbuffer_cmd {
238 struct vdec_bufferpayload buffer;
239 void *client_data;
240};
241
242enum vdec_bufferflush {
243 VDEC_FLUSH_TYPE_INPUT,
244 VDEC_FLUSH_TYPE_OUTPUT,
245 VDEC_FLUSH_TYPE_ALL
246};
247
248enum vdec_codec {
249 VDEC_CODECTYPE_H264 = 0x1,
250 VDEC_CODECTYPE_H263 = 0x2,
251 VDEC_CODECTYPE_MPEG4 = 0x3,
252 VDEC_CODECTYPE_DIVX_3 = 0x4,
253 VDEC_CODECTYPE_DIVX_4 = 0x5,
254 VDEC_CODECTYPE_DIVX_5 = 0x6,
255 VDEC_CODECTYPE_DIVX_6 = 0x7,
256 VDEC_CODECTYPE_XVID = 0x8,
257 VDEC_CODECTYPE_MPEG1 = 0x9,
258 VDEC_CODECTYPE_MPEG2 = 0xa,
259 VDEC_CODECTYPE_VC1 = 0xb,
260 VDEC_CODECTYPE_VC1_RCV = 0xc
261};
262
263enum vdec_mpeg2_profile {
264 VDEC_MPEG2ProfileSimple = 0x1,
265 VDEC_MPEG2ProfileMain = 0x2,
266 VDEC_MPEG2Profile422 = 0x4,
267 VDEC_MPEG2ProfileSNR = 0x8,
268 VDEC_MPEG2ProfileSpatial = 0x10,
269 VDEC_MPEG2ProfileHigh = 0x20,
270 VDEC_MPEG2ProfileKhronosExtensions = 0x6F000000,
271 VDEC_MPEG2ProfileVendorStartUnused = 0x7F000000,
272 VDEC_MPEG2ProfileMax = 0x7FFFFFFF
273};
274
275enum vdec_mpeg2_level {
276
277 VDEC_MPEG2LevelLL = 0x1,
278 VDEC_MPEG2LevelML = 0x2,
279 VDEC_MPEG2LevelH14 = 0x4,
280 VDEC_MPEG2LevelHL = 0x8,
281 VDEC_MPEG2LevelKhronosExtensions = 0x6F000000,
282 VDEC_MPEG2LevelVendorStartUnused = 0x7F000000,
283 VDEC_MPEG2LevelMax = 0x7FFFFFFF
284};
285
286enum vdec_mpeg4_profile {
287 VDEC_MPEG4ProfileSimple = 0x01,
288 VDEC_MPEG4ProfileSimpleScalable = 0x02,
289 VDEC_MPEG4ProfileCore = 0x04,
290 VDEC_MPEG4ProfileMain = 0x08,
291 VDEC_MPEG4ProfileNbit = 0x10,
292 VDEC_MPEG4ProfileScalableTexture = 0x20,
293 VDEC_MPEG4ProfileSimpleFace = 0x40,
294 VDEC_MPEG4ProfileSimpleFBA = 0x80,
295 VDEC_MPEG4ProfileBasicAnimated = 0x100,
296 VDEC_MPEG4ProfileHybrid = 0x200,
297 VDEC_MPEG4ProfileAdvancedRealTime = 0x400,
298 VDEC_MPEG4ProfileCoreScalable = 0x800,
299 VDEC_MPEG4ProfileAdvancedCoding = 0x1000,
300 VDEC_MPEG4ProfileAdvancedCore = 0x2000,
301 VDEC_MPEG4ProfileAdvancedScalable = 0x4000,
302 VDEC_MPEG4ProfileAdvancedSimple = 0x8000,
303 VDEC_MPEG4ProfileKhronosExtensions = 0x6F000000,
304 VDEC_MPEG4ProfileVendorStartUnused = 0x7F000000,
305 VDEC_MPEG4ProfileMax = 0x7FFFFFFF
306};
307
308enum vdec_mpeg4_level {
309 VDEC_MPEG4Level0 = 0x01,
310 VDEC_MPEG4Level0b = 0x02,
311 VDEC_MPEG4Level1 = 0x04,
312 VDEC_MPEG4Level2 = 0x08,
313 VDEC_MPEG4Level3 = 0x10,
314 VDEC_MPEG4Level4 = 0x20,
315 VDEC_MPEG4Level4a = 0x40,
316 VDEC_MPEG4Level5 = 0x80,
317 VDEC_MPEG4LevelKhronosExtensions = 0x6F000000,
318 VDEC_MPEG4LevelVendorStartUnused = 0x7F000000,
319 VDEC_MPEG4LevelMax = 0x7FFFFFFF
320};
321
322enum vdec_avc_profile {
323 VDEC_AVCProfileBaseline = 0x01,
324 VDEC_AVCProfileMain = 0x02,
325 VDEC_AVCProfileExtended = 0x04,
326 VDEC_AVCProfileHigh = 0x08,
327 VDEC_AVCProfileHigh10 = 0x10,
328 VDEC_AVCProfileHigh422 = 0x20,
329 VDEC_AVCProfileHigh444 = 0x40,
330 VDEC_AVCProfileKhronosExtensions = 0x6F000000,
331 VDEC_AVCProfileVendorStartUnused = 0x7F000000,
332 VDEC_AVCProfileMax = 0x7FFFFFFF
333};
334
335enum vdec_avc_level {
336 VDEC_AVCLevel1 = 0x01,
337 VDEC_AVCLevel1b = 0x02,
338 VDEC_AVCLevel11 = 0x04,
339 VDEC_AVCLevel12 = 0x08,
340 VDEC_AVCLevel13 = 0x10,
341 VDEC_AVCLevel2 = 0x20,
342 VDEC_AVCLevel21 = 0x40,
343 VDEC_AVCLevel22 = 0x80,
344 VDEC_AVCLevel3 = 0x100,
345 VDEC_AVCLevel31 = 0x200,
346 VDEC_AVCLevel32 = 0x400,
347 VDEC_AVCLevel4 = 0x800,
348 VDEC_AVCLevel41 = 0x1000,
349 VDEC_AVCLevel42 = 0x2000,
350 VDEC_AVCLevel5 = 0x4000,
351 VDEC_AVCLevel51 = 0x8000,
352 VDEC_AVCLevelKhronosExtensions = 0x6F000000,
353 VDEC_AVCLevelVendorStartUnused = 0x7F000000,
354 VDEC_AVCLevelMax = 0x7FFFFFFF
355};
356
357enum vdec_divx_profile {
358 VDEC_DIVXProfile_qMobile = 0x01,
359 VDEC_DIVXProfile_Mobile = 0x02,
360 VDEC_DIVXProfile_HD = 0x04,
361 VDEC_DIVXProfile_Handheld = 0x08,
362 VDEC_DIVXProfile_Portable = 0x10,
363 VDEC_DIVXProfile_HomeTheater = 0x20
364};
365
366enum vdec_xvid_profile {
367 VDEC_XVIDProfile_Simple = 0x1,
368 VDEC_XVIDProfile_Advanced_Realtime_Simple = 0x2,
369 VDEC_XVIDProfile_Advanced_Simple = 0x4
370};
371
372enum vdec_xvid_level {
373 VDEC_XVID_LEVEL_S_L0 = 0x1,
374 VDEC_XVID_LEVEL_S_L1 = 0x2,
375 VDEC_XVID_LEVEL_S_L2 = 0x4,
376 VDEC_XVID_LEVEL_S_L3 = 0x8,
377 VDEC_XVID_LEVEL_ARTS_L1 = 0x10,
378 VDEC_XVID_LEVEL_ARTS_L2 = 0x20,
379 VDEC_XVID_LEVEL_ARTS_L3 = 0x40,
380 VDEC_XVID_LEVEL_ARTS_L4 = 0x80,
381 VDEC_XVID_LEVEL_AS_L0 = 0x100,
382 VDEC_XVID_LEVEL_AS_L1 = 0x200,
383 VDEC_XVID_LEVEL_AS_L2 = 0x400,
384 VDEC_XVID_LEVEL_AS_L3 = 0x800,
385 VDEC_XVID_LEVEL_AS_L4 = 0x1000
386};
387
388enum vdec_h263profile {
389 VDEC_H263ProfileBaseline = 0x01,
390 VDEC_H263ProfileH320Coding = 0x02,
391 VDEC_H263ProfileBackwardCompatible = 0x04,
392 VDEC_H263ProfileISWV2 = 0x08,
393 VDEC_H263ProfileISWV3 = 0x10,
394 VDEC_H263ProfileHighCompression = 0x20,
395 VDEC_H263ProfileInternet = 0x40,
396 VDEC_H263ProfileInterlace = 0x80,
397 VDEC_H263ProfileHighLatency = 0x100,
398 VDEC_H263ProfileKhronosExtensions = 0x6F000000,
399 VDEC_H263ProfileVendorStartUnused = 0x7F000000,
400 VDEC_H263ProfileMax = 0x7FFFFFFF
401};
402
403enum vdec_h263level {
404 VDEC_H263Level10 = 0x01,
405 VDEC_H263Level20 = 0x02,
406 VDEC_H263Level30 = 0x04,
407 VDEC_H263Level40 = 0x08,
408 VDEC_H263Level45 = 0x10,
409 VDEC_H263Level50 = 0x20,
410 VDEC_H263Level60 = 0x40,
411 VDEC_H263Level70 = 0x80,
412 VDEC_H263LevelKhronosExtensions = 0x6F000000,
413 VDEC_H263LevelVendorStartUnused = 0x7F000000,
414 VDEC_H263LevelMax = 0x7FFFFFFF
415};
416
417enum vdec_wmv_format {
418 VDEC_WMVFormatUnused = 0x01,
419 VDEC_WMVFormat7 = 0x02,
420 VDEC_WMVFormat8 = 0x04,
421 VDEC_WMVFormat9 = 0x08,
422 VDEC_WMFFormatKhronosExtensions = 0x6F000000,
423 VDEC_WMFFormatVendorStartUnused = 0x7F000000,
424 VDEC_WMVFormatMax = 0x7FFFFFFF
425};
426
427enum vdec_vc1_profile {
428 VDEC_VC1ProfileSimple = 0x1,
429 VDEC_VC1ProfileMain = 0x2,
430 VDEC_VC1ProfileAdvanced = 0x4
431};
432
433enum vdec_vc1_level {
434 VDEC_VC1_LEVEL_S_Low = 0x1,
435 VDEC_VC1_LEVEL_S_Medium = 0x2,
436 VDEC_VC1_LEVEL_M_Low = 0x4,
437 VDEC_VC1_LEVEL_M_Medium = 0x8,
438 VDEC_VC1_LEVEL_M_High = 0x10,
439 VDEC_VC1_LEVEL_A_L0 = 0x20,
440 VDEC_VC1_LEVEL_A_L1 = 0x40,
441 VDEC_VC1_LEVEL_A_L2 = 0x80,
442 VDEC_VC1_LEVEL_A_L3 = 0x100,
443 VDEC_VC1_LEVEL_A_L4 = 0x200
444};
445
446struct vdec_profile_level {
447 uint32_t profiles;
448 uint32_t levels;
449};
450
451enum vdec_interlaced_format {
452 VDEC_InterlaceFrameProgressive = 0x1,
453 VDEC_InterlaceInterleaveFrameTopFieldFirst = 0x2,
454 VDEC_InterlaceInterleaveFrameBottomFieldFirst = 0x4
455};
456
457enum vdec_output_fromat {
458 VDEC_YUV_FORMAT_NV12 = 0x1,
459 VDEC_YUV_FORMAT_TILE_4x2 = 0x2
460};
461
462enum vdec_output_order {
463 VDEC_ORDER_DISPLAY = 0x1,
464 VDEC_ORDER_DECODE = 0x2
465};
466
467struct vdec_picsize {
468 uint32_t frame_width;
469 uint32_t frame_height;
470 uint32_t stride;
471 uint32_t scan_lines;
472};
473
474struct vdec_seqheader {
475 void __user *ptr_seqheader;
476 size_t seq_header_len;
477 int pmem_fd;
478 size_t pmem_offset;
479};
480
481struct vdec_mberror {
482 void __user *ptr_errormap;
483 size_t err_mapsize;
484};
485
486struct vdec_input_frameinfo {
487 void __user *bufferaddr;
488 size_t offset;
489 size_t datalen;
490 uint32_t flags;
491 int64_t timestamp;
492 void *client_data;
493 int pmem_fd;
494 size_t pmem_offset;
495};
496
497struct vdec_framesize {
498 uint32_t left;
499 uint32_t top;
500 uint32_t right;
501 uint32_t bottom;
502};
503
504struct vdec_output_frameinfo {
505 void __user *bufferaddr;
506 size_t offset;
507 size_t len;
508 uint32_t flags;
509 int64_t time_stamp;
510 enum vdec_picture pic_type;
511 void *client_data;
512 void *input_frame_clientdata;
513 struct vdec_framesize framesize;
514 enum vdec_interlaced_format interlaced_format;
515};
516
517union vdec_msgdata {
518 struct vdec_output_frameinfo output_frame;
519 void *input_frame_clientdata;
520};
521
522struct vdec_msginfo {
523 uint32_t status_code;
524 uint32_t msgcode;
525 union vdec_msgdata msgdata;
526 size_t msgdatasize;
527};
528
529struct vdec_framerate {
530 unsigned long fps_denominator;
531 unsigned long fps_numerator;
532};
533
534struct vdec_h264_mv{
535 size_t size;
536 int count;
537 int pmem_fd;
538 int offset;
539};
540
541struct vdec_mv_buff_size{
542 int width;
543 int height;
544 int size;
545 int alignment;
546};
547
548#endif /* end of macro _VDECDECODER_H_ */