Gitiles
Code Review Sign In
gerrit-public.fairphone.software / fp2-dev / kernel / msm / e0b5a5078675f58736787982af811244eeb98081 / . / drivers / net / wireless / rtlwifi / rtl8192cu / hw.c
blob: 861f39fad3ec9d1c08535a3acf7670f36e3d5acb [file] [log] [blame]
Georgedc0313f2011-02-19 16:29:22 -0600[diff] [blame]1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../efuse.h"
32#include "../base.h"
33#include "../cam.h"
34#include "../ps.h"
35#include "../usb.h"
36#include "reg.h"
37#include "def.h"
38#include "phy.h"
39#include "mac.h"
40#include "dm.h"
Georgedc0313f2011-02-19 16:29:22 -0600[diff] [blame]41#include "hw.h"
42#include "trx.h"
43#include "led.h"
44#include "table.h"
Chaoming_Lif73b2792011-04-25 12:53:50 -0500[diff] [blame]45#include "../rtl8192ce/hw.h"
Georgedc0313f2011-02-19 16:29:22 -0600[diff] [blame]46
47static void _rtl92cu_phy_param_tab_init(struct ieee80211_hw *hw)
48{
49 struct rtl_priv *rtlpriv = rtl_priv(hw);
50 struct rtl_phy *rtlphy = &(rtlpriv->phy);
51 struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
52
53 rtlphy->hwparam_tables[MAC_REG].length = RTL8192CUMAC_2T_ARRAYLENGTH;
54 rtlphy->hwparam_tables[MAC_REG].pdata = RTL8192CUMAC_2T_ARRAY;
55 if (IS_HIGHT_PA(rtlefuse->board_type)) {
56 rtlphy->hwparam_tables[PHY_REG_PG].length =
57 RTL8192CUPHY_REG_Array_PG_HPLength;
58 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
59 RTL8192CUPHY_REG_Array_PG_HP;
60 } else {
61 rtlphy->hwparam_tables[PHY_REG_PG].length =
62 RTL8192CUPHY_REG_ARRAY_PGLENGTH;
63 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
64 RTL8192CUPHY_REG_ARRAY_PG;
65 }
66 /* 2T */
67 rtlphy->hwparam_tables[PHY_REG_2T].length =
68 RTL8192CUPHY_REG_2TARRAY_LENGTH;
69 rtlphy->hwparam_tables[PHY_REG_2T].pdata =
70 RTL8192CUPHY_REG_2TARRAY;
71 rtlphy->hwparam_tables[RADIOA_2T].length =
72 RTL8192CURADIOA_2TARRAYLENGTH;
73 rtlphy->hwparam_tables[RADIOA_2T].pdata =
74 RTL8192CURADIOA_2TARRAY;
75 rtlphy->hwparam_tables[RADIOB_2T].length =
76 RTL8192CURADIOB_2TARRAYLENGTH;
77 rtlphy->hwparam_tables[RADIOB_2T].pdata =
78 RTL8192CU_RADIOB_2TARRAY;
79 rtlphy->hwparam_tables[AGCTAB_2T].length =
80 RTL8192CUAGCTAB_2TARRAYLENGTH;
81 rtlphy->hwparam_tables[AGCTAB_2T].pdata =
82 RTL8192CUAGCTAB_2TARRAY;
83 /* 1T */
84 if (IS_HIGHT_PA(rtlefuse->board_type)) {
85 rtlphy->hwparam_tables[PHY_REG_1T].length =
86 RTL8192CUPHY_REG_1T_HPArrayLength;
87 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
88 RTL8192CUPHY_REG_1T_HPArray;
89 rtlphy->hwparam_tables[RADIOA_1T].length =
90 RTL8192CURadioA_1T_HPArrayLength;
91 rtlphy->hwparam_tables[RADIOA_1T].pdata =
92 RTL8192CURadioA_1T_HPArray;
93 rtlphy->hwparam_tables[RADIOB_1T].length =
94 RTL8192CURADIOB_1TARRAYLENGTH;
95 rtlphy->hwparam_tables[RADIOB_1T].pdata =
96 RTL8192CU_RADIOB_1TARRAY;
97 rtlphy->hwparam_tables[AGCTAB_1T].length =
98 RTL8192CUAGCTAB_1T_HPArrayLength;
99 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
100 Rtl8192CUAGCTAB_1T_HPArray;
101 } else {
102 rtlphy->hwparam_tables[PHY_REG_1T].length =
103 RTL8192CUPHY_REG_1TARRAY_LENGTH;
104 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
105 RTL8192CUPHY_REG_1TARRAY;
106 rtlphy->hwparam_tables[RADIOA_1T].length =
107 RTL8192CURADIOA_1TARRAYLENGTH;
108 rtlphy->hwparam_tables[RADIOA_1T].pdata =
109 RTL8192CU_RADIOA_1TARRAY;
110 rtlphy->hwparam_tables[RADIOB_1T].length =
111 RTL8192CURADIOB_1TARRAYLENGTH;
112 rtlphy->hwparam_tables[RADIOB_1T].pdata =
113 RTL8192CU_RADIOB_1TARRAY;
114 rtlphy->hwparam_tables[AGCTAB_1T].length =
115 RTL8192CUAGCTAB_1TARRAYLENGTH;
116 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
117 RTL8192CUAGCTAB_1TARRAY;
118 }
119}
120
121static void _rtl92cu_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
122 bool autoload_fail,
123 u8 *hwinfo)
124{
125 struct rtl_priv *rtlpriv = rtl_priv(hw);
126 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
127 u8 rf_path, index, tempval;
128 u16 i;
129
130 for (rf_path = 0; rf_path < 2; rf_path++) {
131 for (i = 0; i < 3; i++) {
132 if (!autoload_fail) {
133 rtlefuse->
134 eeprom_chnlarea_txpwr_cck[rf_path][i] =
135 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
136 rtlefuse->
137 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
138 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
139 i];
140 } else {
141 rtlefuse->
142 eeprom_chnlarea_txpwr_cck[rf_path][i] =
143 EEPROM_DEFAULT_TXPOWERLEVEL;
144 rtlefuse->
145 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
146 EEPROM_DEFAULT_TXPOWERLEVEL;
147 }
148 }
149 }
150 for (i = 0; i < 3; i++) {
151 if (!autoload_fail)
152 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
153 else
154 tempval = EEPROM_DEFAULT_HT40_2SDIFF;
155 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_A][i] =
156 (tempval & 0xf);
157 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_B][i] =
158 ((tempval & 0xf0) >> 4);
159 }
160 for (rf_path = 0; rf_path < 2; rf_path++)
161 for (i = 0; i < 3; i++)
162 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
163 ("RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path,
164 i, rtlefuse->
165 eeprom_chnlarea_txpwr_cck[rf_path][i]));
166 for (rf_path = 0; rf_path < 2; rf_path++)
167 for (i = 0; i < 3; i++)
168 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
169 ("RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
170 rf_path, i,
171 rtlefuse->
172 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]));
173 for (rf_path = 0; rf_path < 2; rf_path++)
174 for (i = 0; i < 3; i++)
175 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
176 ("RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
177 rf_path, i,
178 rtlefuse->
179 eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
180 [i]));
181 for (rf_path = 0; rf_path < 2; rf_path++) {
182 for (i = 0; i < 14; i++) {
183 index = _rtl92c_get_chnl_group((u8) i);
184 rtlefuse->txpwrlevel_cck[rf_path][i] =
185 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
186 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
187 rtlefuse->
188 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
189 if ((rtlefuse->
190 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
191 rtlefuse->
192 eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path][index])
193 > 0) {
194 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
195 rtlefuse->
196 eeprom_chnlarea_txpwr_ht40_1s[rf_path]
197 [index] - rtlefuse->
198 eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
199 [index];
200 } else {
201 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
202 }
203 }
204 for (i = 0; i < 14; i++) {
205 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
206 ("RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = "
207 "[0x%x / 0x%x / 0x%x]\n", rf_path, i,
208 rtlefuse->txpwrlevel_cck[rf_path][i],
209 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
210 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]));
211 }
212 }
213 for (i = 0; i < 3; i++) {
214 if (!autoload_fail) {
215 rtlefuse->eeprom_pwrlimit_ht40[i] =
216 hwinfo[EEPROM_TXPWR_GROUP + i];
217 rtlefuse->eeprom_pwrlimit_ht20[i] =
218 hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
219 } else {
220 rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
221 rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
222 }
223 }
224 for (rf_path = 0; rf_path < 2; rf_path++) {
225 for (i = 0; i < 14; i++) {
226 index = _rtl92c_get_chnl_group((u8) i);
227 if (rf_path == RF90_PATH_A) {
228 rtlefuse->pwrgroup_ht20[rf_path][i] =
229 (rtlefuse->eeprom_pwrlimit_ht20[index]
230 & 0xf);
231 rtlefuse->pwrgroup_ht40[rf_path][i] =
232 (rtlefuse->eeprom_pwrlimit_ht40[index]
233 & 0xf);
234 } else if (rf_path == RF90_PATH_B) {
235 rtlefuse->pwrgroup_ht20[rf_path][i] =
236 ((rtlefuse->eeprom_pwrlimit_ht20[index]
237 & 0xf0) >> 4);
238 rtlefuse->pwrgroup_ht40[rf_path][i] =
239 ((rtlefuse->eeprom_pwrlimit_ht40[index]
240 & 0xf0) >> 4);
241 }
242 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
243 ("RF-%d pwrgroup_ht20[%d] = 0x%x\n",
244 rf_path, i,
245 rtlefuse->pwrgroup_ht20[rf_path][i]));
246 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
247 ("RF-%d pwrgroup_ht40[%d] = 0x%x\n",
248 rf_path, i,
249 rtlefuse->pwrgroup_ht40[rf_path][i]));
250 }
251 }
252 for (i = 0; i < 14; i++) {
253 index = _rtl92c_get_chnl_group((u8) i);
254 if (!autoload_fail)
255 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
256 else
257 tempval = EEPROM_DEFAULT_HT20_DIFF;
258 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
259 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
260 ((tempval >> 4) & 0xF);
261 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
262 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
263 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
264 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
265 index = _rtl92c_get_chnl_group((u8) i);
266 if (!autoload_fail)
267 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
268 else
269 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
270 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
271 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
272 ((tempval >> 4) & 0xF);
273 }
274 rtlefuse->legacy_ht_txpowerdiff =
275 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
276 for (i = 0; i < 14; i++)
277 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
278 ("RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i,
279 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]));
280 for (i = 0; i < 14; i++)
281 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
282 ("RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i,
283 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]));
284 for (i = 0; i < 14; i++)
285 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
286 ("RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i,
287 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]));
288 for (i = 0; i < 14; i++)
289 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
290 ("RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i,
291 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]));
292 if (!autoload_fail)
293 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
294 else
295 rtlefuse->eeprom_regulatory = 0;
296 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
297 ("eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory));
298 if (!autoload_fail) {
299 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
300 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
301 } else {
302 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
303 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
304 }
305 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
306 ("TSSI_A = 0x%x, TSSI_B = 0x%x\n",
307 rtlefuse->eeprom_tssi[RF90_PATH_A],
308 rtlefuse->eeprom_tssi[RF90_PATH_B]));
309 if (!autoload_fail)
310 tempval = hwinfo[EEPROM_THERMAL_METER];
311 else
312 tempval = EEPROM_DEFAULT_THERMALMETER;
313 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
314 if (rtlefuse->eeprom_thermalmeter < 0x06 ||
315 rtlefuse->eeprom_thermalmeter > 0x1c)
316 rtlefuse->eeprom_thermalmeter = 0x12;
317 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
318 rtlefuse->apk_thermalmeterignore = true;
319 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
320 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
321 ("thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter));
322}
323
324static void _rtl92cu_read_board_type(struct ieee80211_hw *hw, u8 *contents)
325{
326 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
327 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
328 u8 boardType;
329
330 if (IS_NORMAL_CHIP(rtlhal->version)) {
331 boardType = ((contents[EEPROM_RF_OPT1]) &
332 BOARD_TYPE_NORMAL_MASK) >> 5; /*bit[7:5]*/
333 } else {
334 boardType = contents[EEPROM_RF_OPT4];
335 boardType &= BOARD_TYPE_TEST_MASK;
336 }
337 rtlefuse->board_type = boardType;
338 if (IS_HIGHT_PA(rtlefuse->board_type))
339 rtlefuse->external_pa = 1;
340 printk(KERN_INFO "rtl8192cu: Board Type %x\n", rtlefuse->board_type);
341
342#ifdef CONFIG_ANTENNA_DIVERSITY
343 /* Antenna Diversity setting. */
344 if (registry_par->antdiv_cfg == 2) /* 2: From Efuse */
345 rtl_efuse->antenna_cfg = (contents[EEPROM_RF_OPT1]&0x18)>>3;
346 else
347 rtl_efuse->antenna_cfg = registry_par->antdiv_cfg; /* 0:OFF, */
348
349 printk(KERN_INFO "rtl8192cu: Antenna Config %x\n",
350 rtl_efuse->antenna_cfg);
351#endif
352}
353
354#ifdef CONFIG_BT_COEXIST
355static void _update_bt_param(_adapter *padapter)
356{
357 struct btcoexist_priv *pbtpriv = &(padapter->halpriv.bt_coexist);
358 struct registry_priv *registry_par = &padapter->registrypriv;
359 if (2 != registry_par->bt_iso) {
360 /* 0:Low, 1:High, 2:From Efuse */
361 pbtpriv->BT_Ant_isolation = registry_par->bt_iso;
362 }
363 if (registry_par->bt_sco == 1) {
364 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter, 4.Busy,
365 * 5.OtherBusy */
366 pbtpriv->BT_Service = BT_OtherAction;
367 } else if (registry_par->bt_sco == 2) {
368 pbtpriv->BT_Service = BT_SCO;
369 } else if (registry_par->bt_sco == 4) {
370 pbtpriv->BT_Service = BT_Busy;
371 } else if (registry_par->bt_sco == 5) {
372 pbtpriv->BT_Service = BT_OtherBusy;
373 } else {
374 pbtpriv->BT_Service = BT_Idle;
375 }
376 pbtpriv->BT_Ampdu = registry_par->bt_ampdu;
377 pbtpriv->bCOBT = _TRUE;
378 pbtpriv->BtEdcaUL = 0;
379 pbtpriv->BtEdcaDL = 0;
380 pbtpriv->BtRssiState = 0xff;
381 pbtpriv->bInitSet = _FALSE;
382 pbtpriv->bBTBusyTraffic = _FALSE;
383 pbtpriv->bBTTrafficModeSet = _FALSE;
384 pbtpriv->bBTNonTrafficModeSet = _FALSE;
385 pbtpriv->CurrentState = 0;
386 pbtpriv->PreviousState = 0;
387 printk(KERN_INFO "rtl8192cu: BT Coexistance = %s\n",
388 (pbtpriv->BT_Coexist == _TRUE) ? "enable" : "disable");
389 if (pbtpriv->BT_Coexist) {
390 if (pbtpriv->BT_Ant_Num == Ant_x2)
391 printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
392 "Ant_Num = Antx2\n");
393 else if (pbtpriv->BT_Ant_Num == Ant_x1)
394 printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
395 "Ant_Num = Antx1\n");
396 switch (pbtpriv->BT_CoexistType) {
397 case BT_2Wire:
398 printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
399 "CoexistType = BT_2Wire\n");
400 break;
401 case BT_ISSC_3Wire:
402 printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
403 "CoexistType = BT_ISSC_3Wire\n");
404 break;
405 case BT_Accel:
406 printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
407 "CoexistType = BT_Accel\n");
408 break;
409 case BT_CSR_BC4:
410 printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
411 "CoexistType = BT_CSR_BC4\n");
412 break;
413 case BT_CSR_BC8:
414 printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
415 "CoexistType = BT_CSR_BC8\n");
416 break;
417 case BT_RTL8756:
418 printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
419 "CoexistType = BT_RTL8756\n");
420 break;
421 default:
422 printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
423 "CoexistType = Unknown\n");
424 break;
425 }
426 printk(KERN_INFO "rtl8192cu: BlueTooth BT_Ant_isolation = %d\n",
427 pbtpriv->BT_Ant_isolation);
428 switch (pbtpriv->BT_Service) {
429 case BT_OtherAction:
430 printk(KERN_INFO "rtl8192cu: BlueTooth BT_Service = "
431 "BT_OtherAction\n");
432 break;
433 case BT_SCO:
434 printk(KERN_INFO "rtl8192cu: BlueTooth BT_Service = "
435 "BT_SCO\n");
436 break;
437 case BT_Busy:
438 printk(KERN_INFO "rtl8192cu: BlueTooth BT_Service = "
439 "BT_Busy\n");
440 break;
441 case BT_OtherBusy:
442 printk(KERN_INFO "rtl8192cu: BlueTooth BT_Service = "
443 "BT_OtherBusy\n");
444 break;
445 default:
446 printk(KERN_INFO "rtl8192cu: BlueTooth BT_Service = "
447 "BT_Idle\n");
448 break;
449 }
450 printk(KERN_INFO "rtl8192cu: BT_RadioSharedType = 0x%x\n",
451 pbtpriv->BT_RadioSharedType);
452 }
453}
454
455#define GET_BT_COEXIST(priv) (&priv->bt_coexist)
456
457static void _rtl92cu_read_bluetooth_coexistInfo(struct ieee80211_hw *hw,
458 u8 *contents,
459 bool bautoloadfailed);
460{
461 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
462 bool isNormal = IS_NORMAL_CHIP(pHalData->VersionID);
463 struct btcoexist_priv *pbtpriv = &pHalData->bt_coexist;
464 u8 rf_opt4;
465
466 _rtw_memset(pbtpriv, 0, sizeof(struct btcoexist_priv));
467 if (AutoloadFail) {
468 pbtpriv->BT_Coexist = _FALSE;
469 pbtpriv->BT_CoexistType = BT_2Wire;
470 pbtpriv->BT_Ant_Num = Ant_x2;
471 pbtpriv->BT_Ant_isolation = 0;
472 pbtpriv->BT_RadioSharedType = BT_Radio_Shared;
473 return;
474 }
475 if (isNormal) {
476 if (pHalData->BoardType == BOARD_USB_COMBO)
477 pbtpriv->BT_Coexist = _TRUE;
478 else
479 pbtpriv->BT_Coexist = ((PROMContent[EEPROM_RF_OPT3] &
480 0x20) >> 5); /* bit[5] */
481 rf_opt4 = PROMContent[EEPROM_RF_OPT4];
482 pbtpriv->BT_CoexistType = ((rf_opt4&0xe)>>1); /* bit [3:1] */
483 pbtpriv->BT_Ant_Num = (rf_opt4&0x1); /* bit [0] */
484 pbtpriv->BT_Ant_isolation = ((rf_opt4&0x10)>>4); /* bit [4] */
485 pbtpriv->BT_RadioSharedType = ((rf_opt4&0x20)>>5); /* bit [5] */
486 } else {
487 pbtpriv->BT_Coexist = (PROMContent[EEPROM_RF_OPT4] >> 4) ?
488 _TRUE : _FALSE;
489 }
490 _update_bt_param(Adapter);
491}
492#endif
493
494static void _rtl92cu_read_adapter_info(struct ieee80211_hw *hw)
495{
496 struct rtl_priv *rtlpriv = rtl_priv(hw);
497 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
498 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
499 u16 i, usvalue;
500 u8 hwinfo[HWSET_MAX_SIZE] = {0};
501 u16 eeprom_id;
502
503 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
504 rtl_efuse_shadow_map_update(hw);
505 memcpy((void *)hwinfo,
506 (void *)&rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
507 HWSET_MAX_SIZE);
508 } else if (rtlefuse->epromtype == EEPROM_93C46) {
509 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
510 ("RTL819X Not boot from eeprom, check it !!"));
511 }
512 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_LOUD, ("MAP\n"),
513 hwinfo, HWSET_MAX_SIZE);
514 eeprom_id = *((u16 *)&hwinfo[0]);
515 if (eeprom_id != RTL8190_EEPROM_ID) {
516 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
517 ("EEPROM ID(%#x) is invalid!!\n", eeprom_id));
518 rtlefuse->autoload_failflag = true;
519 } else {
520 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
521 rtlefuse->autoload_failflag = false;
522 }
523 if (rtlefuse->autoload_failflag == true)
524 return;
525 for (i = 0; i < 6; i += 2) {
526 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
527 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
528 }
529 printk(KERN_INFO "rtl8192cu: MAC address: %pM\n", rtlefuse->dev_addr);
530 _rtl92cu_read_txpower_info_from_hwpg(hw,
531 rtlefuse->autoload_failflag, hwinfo);
532 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
533 rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
534 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
535 (" VID = 0x%02x PID = 0x%02x\n",
536 rtlefuse->eeprom_vid, rtlefuse->eeprom_did));
537 rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
538 rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
539 rtlefuse->txpwr_fromeprom = true;
540 rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID];
541 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
542 ("EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid));
543 if (rtlhal->oem_id == RT_CID_DEFAULT) {
544 switch (rtlefuse->eeprom_oemid) {
545 case EEPROM_CID_DEFAULT:
546 if (rtlefuse->eeprom_did == 0x8176) {
547 if ((rtlefuse->eeprom_svid == 0x103C &&
548 rtlefuse->eeprom_smid == 0x1629))
549 rtlhal->oem_id = RT_CID_819x_HP;
550 else
551 rtlhal->oem_id = RT_CID_DEFAULT;
552 } else {
553 rtlhal->oem_id = RT_CID_DEFAULT;
554 }
555 break;
556 case EEPROM_CID_TOSHIBA:
557 rtlhal->oem_id = RT_CID_TOSHIBA;
558 break;
559 case EEPROM_CID_QMI:
560 rtlhal->oem_id = RT_CID_819x_QMI;
561 break;
562 case EEPROM_CID_WHQL:
563 default:
564 rtlhal->oem_id = RT_CID_DEFAULT;
565 break;
566 }
567 }
568 _rtl92cu_read_board_type(hw, hwinfo);
569#ifdef CONFIG_BT_COEXIST
570 _rtl92cu_read_bluetooth_coexistInfo(hw, hwinfo,
571 rtlefuse->autoload_failflag);
572#endif
573}
574
575static void _rtl92cu_hal_customized_behavior(struct ieee80211_hw *hw)
576{
577 struct rtl_priv *rtlpriv = rtl_priv(hw);
578 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
579 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
580
581 switch (rtlhal->oem_id) {
582 case RT_CID_819x_HP:
583 usb_priv->ledctl.led_opendrain = true;
584 break;
585 case RT_CID_819x_Lenovo:
586 case RT_CID_DEFAULT:
587 case RT_CID_TOSHIBA:
588 case RT_CID_CCX:
589 case RT_CID_819x_Acer:
590 case RT_CID_WHQL:
591 default:
592 break;
593 }
594 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
595 ("RT Customized ID: 0x%02X\n", rtlhal->oem_id));
596}
597
598void rtl92cu_read_eeprom_info(struct ieee80211_hw *hw)
599{
600
601 struct rtl_priv *rtlpriv = rtl_priv(hw);
602 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
603 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
604 u8 tmp_u1b;
605
606 if (!IS_NORMAL_CHIP(rtlhal->version))
607 return;
608 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
Chaoming_Li2b8359f2011-04-25 12:53:55 -0500[diff] [blame]609#if 0 /* temporary */
Georgedc0313f2011-02-19 16:29:22 -0600[diff] [blame]610 rtlefuse->epromtype = (tmp_u1b & EEPROMSEL) ?
611 EEPROM_93C46 : EEPROM_BOOT_EFUSE;
612 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from %s\n",
613 (tmp_u1b & EEPROMSEL) ? "EERROM" : "EFUSE"));
Chaoming_Li2b8359f2011-04-25 12:53:55 -0500[diff] [blame]614#endif
Georgedc0313f2011-02-19 16:29:22 -0600[diff] [blame]615 rtlefuse->autoload_failflag = (tmp_u1b & EEPROM_EN) ? false : true;
616 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload %s\n",
617 (tmp_u1b & EEPROM_EN) ? "OK!!" : "ERR!!"));
618 _rtl92cu_read_adapter_info(hw);
619 _rtl92cu_hal_customized_behavior(hw);
620 return;
621}
622
623static int _rtl92cu_init_power_on(struct ieee80211_hw *hw)
624{
625 struct rtl_priv *rtlpriv = rtl_priv(hw);
626 int status = 0;
627 u16 value16;
628 u8 value8;
629 /* polling autoload done. */
630 u32 pollingCount = 0;
631
632 do {
633 if (rtl_read_byte(rtlpriv, REG_APS_FSMCO) & PFM_ALDN) {
634 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
635 ("Autoload Done!\n"));
636 break;
637 }
638 if (pollingCount++ > 100) {
639 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
640 ("Failed to polling REG_APS_FSMCO[PFM_ALDN]"
641 " done!\n"));
642 return -ENODEV;
643 }
644 } while (true);
645 /* 0. RSV_CTRL 0x1C[7:0] = 0 unlock ISO/CLK/Power control register */
646 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
647 /* Power on when re-enter from IPS/Radio off/card disable */
648 /* enable SPS into PWM mode */
649 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
650 udelay(100);
651 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
652 if (0 == (value8 & LDV12_EN)) {
653 value8 |= LDV12_EN;
654 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
655 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
656 (" power-on :REG_LDOV12D_CTRL Reg0x21:0x%02x.\n",
657 value8));
658 udelay(100);
659 value8 = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);
660 value8 &= ~ISO_MD2PP;
661 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, value8);
662 }
663 /* auto enable WLAN */
664 pollingCount = 0;
665 value16 = rtl_read_word(rtlpriv, REG_APS_FSMCO);
666 value16 |= APFM_ONMAC;
667 rtl_write_word(rtlpriv, REG_APS_FSMCO, value16);
668 do {
669 if (!(rtl_read_word(rtlpriv, REG_APS_FSMCO) & APFM_ONMAC)) {
670 printk(KERN_INFO "rtl8192cu: MAC auto ON okay!\n");
671 break;
672 }
673 if (pollingCount++ > 100) {
674 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
675 ("Failed to polling REG_APS_FSMCO[APFM_ONMAC]"
676 " done!\n"));
677 return -ENODEV;
678 }
679 } while (true);
680 /* Enable Radio ,GPIO ,and LED function */
681 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x0812);
682 /* release RF digital isolation */
683 value16 = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
684 value16 &= ~ISO_DIOR;
685 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, value16);
686 /* Reconsider when to do this operation after asking HWSD. */
687 pollingCount = 0;
688 rtl_write_byte(rtlpriv, REG_APSD_CTRL, (rtl_read_byte(rtlpriv,
689 REG_APSD_CTRL) & ~BIT(6)));
690 do {
691 pollingCount++;
692 } while ((pollingCount < 200) &&
693 (rtl_read_byte(rtlpriv, REG_APSD_CTRL) & BIT(7)));
694 /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
695 value16 = rtl_read_word(rtlpriv, REG_CR);
696 value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN |
697 PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN | ENSEC);
698 rtl_write_word(rtlpriv, REG_CR, value16);
699 return status;
700}
701
702static void _rtl92cu_init_queue_reserved_page(struct ieee80211_hw *hw,
703 bool wmm_enable,
704 u8 out_ep_num,
705 u8 queue_sel)
706{
707 struct rtl_priv *rtlpriv = rtl_priv(hw);
708 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
709 bool isChipN = IS_NORMAL_CHIP(rtlhal->version);
710 u32 outEPNum = (u32)out_ep_num;
711 u32 numHQ = 0;
712 u32 numLQ = 0;
713 u32 numNQ = 0;
714 u32 numPubQ;
715 u32 value32;
716 u8 value8;
717 u32 txQPageNum, txQPageUnit, txQRemainPage;
718
719 if (!wmm_enable) {
720 numPubQ = (isChipN) ? CHIP_B_PAGE_NUM_PUBQ :
721 CHIP_A_PAGE_NUM_PUBQ;
722 txQPageNum = TX_TOTAL_PAGE_NUMBER - numPubQ;
723
724 txQPageUnit = txQPageNum/outEPNum;
725 txQRemainPage = txQPageNum % outEPNum;
726 if (queue_sel & TX_SELE_HQ)
727 numHQ = txQPageUnit;
728 if (queue_sel & TX_SELE_LQ)
729 numLQ = txQPageUnit;
730 /* HIGH priority queue always present in the configuration of
731 * 2 out-ep. Remainder pages have assigned to High queue */
732 if ((outEPNum > 1) && (txQRemainPage))
733 numHQ += txQRemainPage;
734 /* NOTE: This step done before writting REG_RQPN. */
735 if (isChipN) {
736 if (queue_sel & TX_SELE_NQ)
737 numNQ = txQPageUnit;
738 value8 = (u8)_NPQ(numNQ);
739 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
740 }
741 } else {
742 /* for WMM ,number of out-ep must more than or equal to 2! */
743 numPubQ = isChipN ? WMM_CHIP_B_PAGE_NUM_PUBQ :
744 WMM_CHIP_A_PAGE_NUM_PUBQ;
745 if (queue_sel & TX_SELE_HQ) {
746 numHQ = isChipN ? WMM_CHIP_B_PAGE_NUM_HPQ :
747 WMM_CHIP_A_PAGE_NUM_HPQ;
748 }
749 if (queue_sel & TX_SELE_LQ) {
750 numLQ = isChipN ? WMM_CHIP_B_PAGE_NUM_LPQ :
751 WMM_CHIP_A_PAGE_NUM_LPQ;
752 }
753 /* NOTE: This step done before writting REG_RQPN. */
754 if (isChipN) {
755 if (queue_sel & TX_SELE_NQ)
756 numNQ = WMM_CHIP_B_PAGE_NUM_NPQ;
757 value8 = (u8)_NPQ(numNQ);
758 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
759 }
760 }
761 /* TX DMA */
762 value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
763 rtl_write_dword(rtlpriv, REG_RQPN, value32);
764}
765
766static void _rtl92c_init_trx_buffer(struct ieee80211_hw *hw, bool wmm_enable)
767{
768 struct rtl_priv *rtlpriv = rtl_priv(hw);
769 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
770 u8 txpktbuf_bndy;
771 u8 value8;
772
773 if (!wmm_enable)
774 txpktbuf_bndy = TX_PAGE_BOUNDARY;
775 else /* for WMM */
776 txpktbuf_bndy = (IS_NORMAL_CHIP(rtlhal->version))
777 ? WMM_CHIP_B_TX_PAGE_BOUNDARY
778 : WMM_CHIP_A_TX_PAGE_BOUNDARY;
779 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
780 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
781 rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
782 rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
783 rtl_write_byte(rtlpriv, REG_TDECTRL+1, txpktbuf_bndy);
784 rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF);
785 value8 = _PSRX(RX_PAGE_SIZE_REG_VALUE) | _PSTX(PBP_128);
786 rtl_write_byte(rtlpriv, REG_PBP, value8);
787}
788
789static void _rtl92c_init_chipN_reg_priority(struct ieee80211_hw *hw, u16 beQ,
790 u16 bkQ, u16 viQ, u16 voQ,
791 u16 mgtQ, u16 hiQ)
792{
793 struct rtl_priv *rtlpriv = rtl_priv(hw);
794 u16 value16 = (rtl_read_word(rtlpriv, REG_TRXDMA_CTRL) & 0x7);
795
796 value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
797 _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
798 _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
799 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, value16);
800}
801
802static void _rtl92cu_init_chipN_one_out_ep_priority(struct ieee80211_hw *hw,
803 bool wmm_enable,
804 u8 queue_sel)
805{
806 u16 uninitialized_var(value);
807
808 switch (queue_sel) {
809 case TX_SELE_HQ:
810 value = QUEUE_HIGH;
811 break;
812 case TX_SELE_LQ:
813 value = QUEUE_LOW;
814 break;
815 case TX_SELE_NQ:
816 value = QUEUE_NORMAL;
817 break;
818 default:
819 WARN_ON(1); /* Shall not reach here! */
820 break;
821 }
822 _rtl92c_init_chipN_reg_priority(hw, value, value, value, value,
823 value, value);
824 printk(KERN_INFO "rtl8192cu: Tx queue select: 0x%02x\n", queue_sel);
825}
826
827static void _rtl92cu_init_chipN_two_out_ep_priority(struct ieee80211_hw *hw,
828 bool wmm_enable,
829 u8 queue_sel)
830{
831 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
832 u16 uninitialized_var(valueHi);
833 u16 uninitialized_var(valueLow);
834
835 switch (queue_sel) {
836 case (TX_SELE_HQ | TX_SELE_LQ):
837 valueHi = QUEUE_HIGH;
838 valueLow = QUEUE_LOW;
839 break;
840 case (TX_SELE_NQ | TX_SELE_LQ):
841 valueHi = QUEUE_NORMAL;
842 valueLow = QUEUE_LOW;
843 break;
844 case (TX_SELE_HQ | TX_SELE_NQ):
845 valueHi = QUEUE_HIGH;
846 valueLow = QUEUE_NORMAL;
847 break;
848 default:
849 WARN_ON(1);
850 break;
851 }
852 if (!wmm_enable) {
853 beQ = valueLow;
854 bkQ = valueLow;
855 viQ = valueHi;
856 voQ = valueHi;
857 mgtQ = valueHi;
858 hiQ = valueHi;
859 } else {/* for WMM ,CONFIG_OUT_EP_WIFI_MODE */
860 beQ = valueHi;
861 bkQ = valueLow;
862 viQ = valueLow;
863 voQ = valueHi;
864 mgtQ = valueHi;
865 hiQ = valueHi;
866 }
867 _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
868 printk(KERN_INFO "rtl8192cu: Tx queue select: 0x%02x\n", queue_sel);
869}
870
871static void _rtl92cu_init_chipN_three_out_ep_priority(struct ieee80211_hw *hw,
872 bool wmm_enable,
873 u8 queue_sel)
874{
875 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
876 struct rtl_priv *rtlpriv = rtl_priv(hw);
877
878 if (!wmm_enable) { /* typical setting */
879 beQ = QUEUE_LOW;
880 bkQ = QUEUE_LOW;
881 viQ = QUEUE_NORMAL;
882 voQ = QUEUE_HIGH;
883 mgtQ = QUEUE_HIGH;
884 hiQ = QUEUE_HIGH;
885 } else { /* for WMM */
886 beQ = QUEUE_LOW;
887 bkQ = QUEUE_NORMAL;
888 viQ = QUEUE_NORMAL;
889 voQ = QUEUE_HIGH;
890 mgtQ = QUEUE_HIGH;
891 hiQ = QUEUE_HIGH;
892 }
893 _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
894 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
895 ("Tx queue select :0x%02x..\n", queue_sel));
896}
897
898static void _rtl92cu_init_chipN_queue_priority(struct ieee80211_hw *hw,
899 bool wmm_enable,
900 u8 out_ep_num,
901 u8 queue_sel)
902{
903 switch (out_ep_num) {
904 case 1:
905 _rtl92cu_init_chipN_one_out_ep_priority(hw, wmm_enable,
906 queue_sel);
907 break;
908 case 2:
909 _rtl92cu_init_chipN_two_out_ep_priority(hw, wmm_enable,
910 queue_sel);
911 break;
912 case 3:
913 _rtl92cu_init_chipN_three_out_ep_priority(hw, wmm_enable,
914 queue_sel);
915 break;
916 default:
917 WARN_ON(1); /* Shall not reach here! */
918 break;
919 }
920}
921
922static void _rtl92cu_init_chipT_queue_priority(struct ieee80211_hw *hw,
923 bool wmm_enable,
924 u8 out_ep_num,
925 u8 queue_sel)
926{
Larry Finger9f219bd2011-04-13 21:00:02 -0500[diff] [blame]927 u8 hq_sele = 0;
Georgedc0313f2011-02-19 16:29:22 -0600[diff] [blame]928 struct rtl_priv *rtlpriv = rtl_priv(hw);
929
930 switch (out_ep_num) {
931 case 2: /* (TX_SELE_HQ|TX_SELE_LQ) */
932 if (!wmm_enable) /* typical setting */
933 hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_MGTQ |
934 HQSEL_HIQ;
935 else /* for WMM */
936 hq_sele = HQSEL_VOQ | HQSEL_BEQ | HQSEL_MGTQ |
937 HQSEL_HIQ;
938 break;
939 case 1:
940 if (TX_SELE_LQ == queue_sel) {
941 /* map all endpoint to Low queue */
942 hq_sele = 0;
943 } else if (TX_SELE_HQ == queue_sel) {
944 /* map all endpoint to High queue */
945 hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_BEQ |
946 HQSEL_BKQ | HQSEL_MGTQ | HQSEL_HIQ;
947 }
948 break;
949 default:
950 WARN_ON(1); /* Shall not reach here! */
951 break;
952 }
953 rtl_write_byte(rtlpriv, (REG_TRXDMA_CTRL+1), hq_sele);
954 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
955 ("Tx queue select :0x%02x..\n", hq_sele));
956}
957
958static void _rtl92cu_init_queue_priority(struct ieee80211_hw *hw,
959 bool wmm_enable,
960 u8 out_ep_num,
961 u8 queue_sel)
962{
963 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
964 if (IS_NORMAL_CHIP(rtlhal->version))
965 _rtl92cu_init_chipN_queue_priority(hw, wmm_enable, out_ep_num,
966 queue_sel);
967 else
968 _rtl92cu_init_chipT_queue_priority(hw, wmm_enable, out_ep_num,
969 queue_sel);
970}
971
972static void _rtl92cu_init_usb_aggregation(struct ieee80211_hw *hw)
973{
974}
975
976static void _rtl92cu_init_wmac_setting(struct ieee80211_hw *hw)
977{
978 u16 value16;
979
980 struct rtl_priv *rtlpriv = rtl_priv(hw);
981 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
982
983 mac->rx_conf = (RCR_APM | RCR_AM | RCR_ADF | RCR_AB | RCR_APP_FCS |
984 RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL |
985 RCR_APP_MIC | RCR_APP_PHYSTS | RCR_ACRC32);
986 rtl_write_dword(rtlpriv, REG_RCR, mac->rx_conf);
987 /* Accept all multicast address */
988 rtl_write_dword(rtlpriv, REG_MAR, 0xFFFFFFFF);
989 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xFFFFFFFF);
990 /* Accept all management frames */
991 value16 = 0xFFFF;
992 rtl92c_set_mgt_filter(hw, value16);
993 /* Reject all control frame - default value is 0 */
994 rtl92c_set_ctrl_filter(hw, 0x0);
995 /* Accept all data frames */
996 value16 = 0xFFFF;
997 rtl92c_set_data_filter(hw, value16);
998}
999
1000static int _rtl92cu_init_mac(struct ieee80211_hw *hw)
1001{
1002 struct rtl_priv *rtlpriv = rtl_priv(hw);
1003 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1004 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
1005 struct rtl_usb *rtlusb = rtl_usbdev(usb_priv);
1006 int err = 0;
1007 u32 boundary = 0;
1008 u8 wmm_enable = false; /* TODO */
1009 u8 out_ep_nums = rtlusb->out_ep_nums;
1010 u8 queue_sel = rtlusb->out_queue_sel;
1011 err = _rtl92cu_init_power_on(hw);
1012
1013 if (err) {
1014 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1015 ("Failed to init power on!\n"));
1016 return err;
1017 }
1018 if (!wmm_enable) {
1019 boundary = TX_PAGE_BOUNDARY;
1020 } else { /* for WMM */
1021 boundary = (IS_NORMAL_CHIP(rtlhal->version))
1022 ? WMM_CHIP_B_TX_PAGE_BOUNDARY
1023 : WMM_CHIP_A_TX_PAGE_BOUNDARY;
1024 }
1025 if (false == rtl92c_init_llt_table(hw, boundary)) {
1026 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1027 ("Failed to init LLT Table!\n"));
1028 return -EINVAL;
1029 }
1030 _rtl92cu_init_queue_reserved_page(hw, wmm_enable, out_ep_nums,
1031 queue_sel);
1032 _rtl92c_init_trx_buffer(hw, wmm_enable);
1033 _rtl92cu_init_queue_priority(hw, wmm_enable, out_ep_nums,
1034 queue_sel);
1035 /* Get Rx PHY status in order to report RSSI and others. */
1036 rtl92c_init_driver_info_size(hw, RTL92C_DRIVER_INFO_SIZE);
1037 rtl92c_init_interrupt(hw);
1038 rtl92c_init_network_type(hw);
1039 _rtl92cu_init_wmac_setting(hw);
1040 rtl92c_init_adaptive_ctrl(hw);
1041 rtl92c_init_edca(hw);
1042 rtl92c_init_rate_fallback(hw);
1043 rtl92c_init_retry_function(hw);
1044 _rtl92cu_init_usb_aggregation(hw);
1045 rtlpriv->cfg->ops->set_bw_mode(hw, NL80211_CHAN_HT20);
1046 rtl92c_set_min_space(hw, IS_92C_SERIAL(rtlhal->version));
1047 rtl92c_init_beacon_parameters(hw, rtlhal->version);
1048 rtl92c_init_ampdu_aggregation(hw);
1049 rtl92c_init_beacon_max_error(hw, true);
1050 return err;
1051}
1052
1053void rtl92cu_enable_hw_security_config(struct ieee80211_hw *hw)
1054{
1055 struct rtl_priv *rtlpriv = rtl_priv(hw);
1056 u8 sec_reg_value = 0x0;
1057 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1058
1059 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1060 ("PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1061 rtlpriv->sec.pairwise_enc_algorithm,
1062 rtlpriv->sec.group_enc_algorithm));
1063 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1064 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1065 ("not open sw encryption\n"));
1066 return;
1067 }
1068 sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
1069 if (rtlpriv->sec.use_defaultkey) {
1070 sec_reg_value |= SCR_TxUseDK;
1071 sec_reg_value |= SCR_RxUseDK;
1072 }
1073 if (IS_NORMAL_CHIP(rtlhal->version))
1074 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1075 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1076 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
1077 ("The SECR-value %x\n", sec_reg_value));
1078 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1079}
1080
1081static void _rtl92cu_hw_configure(struct ieee80211_hw *hw)
1082{
1083 struct rtl_priv *rtlpriv = rtl_priv(hw);
1084 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1085
1086 /* To Fix MAC loopback mode fail. */
1087 rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f);
1088 rtl_write_byte(rtlpriv, 0x15, 0xe9);
1089 /* HW SEQ CTRL */
1090 /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
1091 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
1092 /* fixed USB interface interference issue */
1093 rtl_write_byte(rtlpriv, 0xfe40, 0xe0);
1094 rtl_write_byte(rtlpriv, 0xfe41, 0x8d);
1095 rtl_write_byte(rtlpriv, 0xfe42, 0x80);
1096 rtlusb->reg_bcn_ctrl_val = 0x18;
1097 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val);
1098}
1099
1100static void _InitPABias(struct ieee80211_hw *hw)
1101{
1102 struct rtl_priv *rtlpriv = rtl_priv(hw);
1103 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1104 u8 pa_setting;
1105
1106 /* FIXED PA current issue */
1107 pa_setting = efuse_read_1byte(hw, 0x1FA);
1108 if (!(pa_setting & BIT(0))) {
1109 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x0F406);
1110 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x4F406);
1111 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x8F406);
1112 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0xCF406);
1113 }
1114 if (!(pa_setting & BIT(1)) && IS_NORMAL_CHIP(rtlhal->version) &&
1115 IS_92C_SERIAL(rtlhal->version)) {
1116 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x0F406);
1117 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x4F406);
1118 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x8F406);
1119 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0xCF406);
1120 }
1121 if (!(pa_setting & BIT(4))) {
1122 pa_setting = rtl_read_byte(rtlpriv, 0x16);
1123 pa_setting &= 0x0F;
1124 rtl_write_byte(rtlpriv, 0x16, pa_setting | 0x90);
1125 }
1126}
1127
1128static void _InitAntenna_Selection(struct ieee80211_hw *hw)
1129{
1130#ifdef CONFIG_ANTENNA_DIVERSITY
1131 struct rtl_priv *rtlpriv = rtl_priv(hw);
1132 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1133 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1134
1135 if (pHalData->AntDivCfg == 0)
1136 return;
1137
1138 if (rtlphy->rf_type == RF_1T1R) {
1139 rtl_write_dword(rtlpriv, REG_LEDCFG0,
1140 rtl_read_dword(rtlpriv,
1141 REG_LEDCFG0)|BIT(23));
1142 rtl_set_bbreg(hw, rFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
1143 if (rtl_get_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300) ==
1144 Antenna_A)
1145 pHalData->CurAntenna = Antenna_A;
1146 else
1147 pHalData->CurAntenna = Antenna_B;
1148 }
1149#endif
1150}
1151
1152static void _dump_registers(struct ieee80211_hw *hw)
1153{
1154}
1155
1156static void _update_mac_setting(struct ieee80211_hw *hw)
1157{
1158 struct rtl_priv *rtlpriv = rtl_priv(hw);
1159 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1160
1161 mac->rx_conf = rtl_read_dword(rtlpriv, REG_RCR);
1162 mac->rx_mgt_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP0);
1163 mac->rx_ctrl_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP1);
1164 mac->rx_data_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP2);
1165}
1166
1167int rtl92cu_hw_init(struct ieee80211_hw *hw)
1168{
1169 struct rtl_priv *rtlpriv = rtl_priv(hw);
1170 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1171 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1172 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1173 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1174 int err = 0;
1175 static bool iqk_initialized;
1176
1177 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CU;
1178 err = _rtl92cu_init_mac(hw);
1179 if (err) {
1180 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("init mac failed!\n"));
1181 return err;
1182 }
1183 err = rtl92c_download_fw(hw);
1184 if (err) {
1185 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1186 ("Failed to download FW. Init HW without FW now..\n"));
1187 err = 1;
1188 rtlhal->fw_ready = false;
1189 return err;
1190 } else {
1191 rtlhal->fw_ready = true;
1192 }
1193 rtlhal->last_hmeboxnum = 0; /* h2c */
1194 _rtl92cu_phy_param_tab_init(hw);
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]1195 rtl92cu_phy_mac_config(hw);
1196 rtl92cu_phy_bb_config(hw);
Georgedc0313f2011-02-19 16:29:22 -0600[diff] [blame]1197 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1198 rtl92c_phy_rf_config(hw);
1199 if (IS_VENDOR_UMC_A_CUT(rtlhal->version) &&
1200 !IS_92C_SERIAL(rtlhal->version)) {
1201 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
1202 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
1203 }
1204 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1205 RF_CHNLBW, RFREG_OFFSET_MASK);
1206 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
1207 RF_CHNLBW, RFREG_OFFSET_MASK);
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]1208 rtl92cu_bb_block_on(hw);
Georgedc0313f2011-02-19 16:29:22 -0600[diff] [blame]1209 rtl_cam_reset_all_entry(hw);
1210 rtl92cu_enable_hw_security_config(hw);
1211 ppsc->rfpwr_state = ERFON;
1212 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1213 if (ppsc->rfpwr_state == ERFON) {
1214 rtl92c_phy_set_rfpath_switch(hw, 1);
1215 if (iqk_initialized) {
1216 rtl92c_phy_iq_calibrate(hw, false);
1217 } else {
1218 rtl92c_phy_iq_calibrate(hw, false);
1219 iqk_initialized = true;
1220 }
1221 rtl92c_dm_check_txpower_tracking(hw);
1222 rtl92c_phy_lc_calibrate(hw);
1223 }
1224 _rtl92cu_hw_configure(hw);
1225 _InitPABias(hw);
1226 _InitAntenna_Selection(hw);
1227 _update_mac_setting(hw);
1228 rtl92c_dm_init(hw);
1229 _dump_registers(hw);
1230 return err;
1231}
1232
1233static void _DisableRFAFEAndResetBB(struct ieee80211_hw *hw)
1234{
1235 struct rtl_priv *rtlpriv = rtl_priv(hw);
1236/**************************************
1237a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue
1238b. RF path 0 offset 0x00 = 0x00 disable RF
1239c. APSD_CTRL 0x600[7:0] = 0x40
1240d. SYS_FUNC_EN 0x02[7:0] = 0x16 reset BB state machine
1241e. SYS_FUNC_EN 0x02[7:0] = 0x14 reset BB state machine
1242***************************************/
1243 u8 eRFPath = 0, value8 = 0;
1244 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1245 rtl_set_rfreg(hw, (enum radio_path)eRFPath, 0x0, MASKBYTE0, 0x0);
1246
1247 value8 |= APSDOFF;
1248 rtl_write_byte(rtlpriv, REG_APSD_CTRL, value8); /*0x40*/
1249 value8 = 0;
1250 value8 |= (FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn);
1251 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8);/*0x16*/
1252 value8 &= (~FEN_BB_GLB_RSTn);
1253 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8); /*0x14*/
1254}
1255
1256static void _ResetDigitalProcedure1(struct ieee80211_hw *hw, bool bWithoutHWSM)
1257{
1258 struct rtl_priv *rtlpriv = rtl_priv(hw);
1259 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1260
1261 if (rtlhal->fw_version <= 0x20) {
1262 /*****************************
1263 f. MCUFWDL 0x80[7:0]=0 reset MCU ready status
1264 g. SYS_FUNC_EN 0x02[10]= 0 reset MCU reg, (8051 reset)
1265 h. SYS_FUNC_EN 0x02[15-12]= 5 reset MAC reg, DCORE
1266 i. SYS_FUNC_EN 0x02[10]= 1 enable MCU reg, (8051 enable)
1267 ******************************/
1268 u16 valu16 = 0;
1269
1270 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1271 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1272 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 &
1273 (~FEN_CPUEN))); /* reset MCU ,8051 */
1274 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN)&0x0FFF;
1275 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
1276 (FEN_HWPDN|FEN_ELDR))); /* reset MAC */
1277 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1278 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
1279 FEN_CPUEN)); /* enable MCU ,8051 */
1280 } else {
1281 u8 retry_cnts = 0;
1282
1283 /* IF fw in RAM code, do reset */
1284 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(1)) {
1285 /* reset MCU ready status */
1286 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1287 if (rtlhal->fw_ready) {
1288 /* 8051 reset by self */
1289 rtl_write_byte(rtlpriv, REG_HMETFR+3, 0x20);
1290 while ((retry_cnts++ < 100) &&
1291 (FEN_CPUEN & rtl_read_word(rtlpriv,
1292 REG_SYS_FUNC_EN))) {
1293 udelay(50);
1294 }
1295 if (retry_cnts >= 100) {
1296 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1297 ("#####=> 8051 reset failed!.."
1298 ".......................\n"););
1299 /* if 8051 reset fail, reset MAC. */
1300 rtl_write_byte(rtlpriv,
1301 REG_SYS_FUNC_EN + 1,
1302 0x50);
1303 udelay(100);
1304 }
1305 }
1306 }
1307 /* Reset MAC and Enable 8051 */
1308 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x54);
1309 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1310 }
1311 if (bWithoutHWSM) {
1312 /*****************************
1313 Without HW auto state machine
1314 g.SYS_CLKR 0x08[15:0] = 0x30A3 disable MAC clock
1315 h.AFE_PLL_CTRL 0x28[7:0] = 0x80 disable AFE PLL
1316 i.AFE_XTAL_CTRL 0x24[15:0] = 0x880F gated AFE DIG_CLOCK
1317 j.SYS_ISu_CTRL 0x00[7:0] = 0xF9 isolated digital to PON
1318 ******************************/
1319 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1320 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1321 rtl_write_word(rtlpriv, REG_AFE_XTAL_CTRL, 0x880F);
1322 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xF9);
1323 }
1324}
1325
1326static void _ResetDigitalProcedure2(struct ieee80211_hw *hw)
1327{
1328 struct rtl_priv *rtlpriv = rtl_priv(hw);
1329/*****************************
1330k. SYS_FUNC_EN 0x03[7:0] = 0x44 disable ELDR runction
1331l. SYS_CLKR 0x08[15:0] = 0x3083 disable ELDR clock
1332m. SYS_ISO_CTRL 0x01[7:0] = 0x83 isolated ELDR to PON
1333******************************/
1334 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1335 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL+1, 0x82);
1336}
1337
1338static void _DisableGPIO(struct ieee80211_hw *hw)
1339{
1340 struct rtl_priv *rtlpriv = rtl_priv(hw);
1341/***************************************
1342j. GPIO_PIN_CTRL 0x44[31:0]=0x000
1343k. Value = GPIO_PIN_CTRL[7:0]
1344l. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); write ext PIN level
1345m. GPIO_MUXCFG 0x42 [15:0] = 0x0780
1346n. LEDCFG 0x4C[15:0] = 0x8080
1347***************************************/
1348 u8 value8;
1349 u16 value16;
1350 u32 value32;
1351
1352 /* 1. Disable GPIO[7:0] */
1353 rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, 0x0000);
1354 value32 = rtl_read_dword(rtlpriv, REG_GPIO_PIN_CTRL) & 0xFFFF00FF;
1355 value8 = (u8) (value32&0x000000FF);
1356 value32 |= ((value8<<8) | 0x00FF0000);
1357 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, value32);
1358 /* 2. Disable GPIO[10:8] */
1359 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+3, 0x00);
1360 value16 = rtl_read_word(rtlpriv, REG_GPIO_MUXCFG+2) & 0xFF0F;
1361 value8 = (u8) (value16&0x000F);
1362 value16 |= ((value8<<4) | 0x0780);
1363 rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, value16);
1364 /* 3. Disable LED0 & 1 */
1365 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1366}
1367
1368static void _DisableAnalog(struct ieee80211_hw *hw, bool bWithoutHWSM)
1369{
1370 struct rtl_priv *rtlpriv = rtl_priv(hw);
1371 u16 value16 = 0;
1372 u8 value8 = 0;
1373
1374 if (bWithoutHWSM) {
1375 /*****************************
1376 n. LDOA15_CTRL 0x20[7:0] = 0x04 disable A15 power
1377 o. LDOV12D_CTRL 0x21[7:0] = 0x54 disable digital core power
1378 r. When driver call disable, the ASIC will turn off remaining
1379 clock automatically
1380 ******************************/
1381 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04);
1382 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
1383 value8 &= (~LDV12_EN);
1384 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
1385 }
1386
1387/*****************************
1388h. SPS0_CTRL 0x11[7:0] = 0x23 enter PFM mode
1389i. APS_FSMCO 0x04[15:0] = 0x4802 set USB suspend
1390******************************/
1391 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1392 value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN);
1393 rtl_write_word(rtlpriv, REG_APS_FSMCO, (u16)value16);
1394 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);
1395}
1396
1397static void _CardDisableHWSM(struct ieee80211_hw *hw)
1398{
1399 /* ==== RF Off Sequence ==== */
1400 _DisableRFAFEAndResetBB(hw);
1401 /* ==== Reset digital sequence ====== */
1402 _ResetDigitalProcedure1(hw, false);
1403 /* ==== Pull GPIO PIN to balance level and LED control ====== */
1404 _DisableGPIO(hw);
1405 /* ==== Disable analog sequence === */
1406 _DisableAnalog(hw, false);
1407}
1408
1409static void _CardDisableWithoutHWSM(struct ieee80211_hw *hw)
1410{
1411 /*==== RF Off Sequence ==== */
1412 _DisableRFAFEAndResetBB(hw);
1413 /* ==== Reset digital sequence ====== */
1414 _ResetDigitalProcedure1(hw, true);
1415 /* ==== Pull GPIO PIN to balance level and LED control ====== */
1416 _DisableGPIO(hw);
1417 /* ==== Reset digital sequence ====== */
1418 _ResetDigitalProcedure2(hw);
1419 /* ==== Disable analog sequence === */
1420 _DisableAnalog(hw, true);
1421}
1422
1423static void _rtl92cu_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
1424 u8 set_bits, u8 clear_bits)
1425{
1426 struct rtl_priv *rtlpriv = rtl_priv(hw);
1427 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1428
1429 rtlusb->reg_bcn_ctrl_val |= set_bits;
1430 rtlusb->reg_bcn_ctrl_val &= ~clear_bits;
1431 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlusb->reg_bcn_ctrl_val);
1432}
1433
1434static void _rtl92cu_stop_tx_beacon(struct ieee80211_hw *hw)
1435{
1436 struct rtl_priv *rtlpriv = rtl_priv(hw);
1437 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1438 u8 tmp1byte = 0;
1439 if (IS_NORMAL_CHIP(rtlhal->version)) {
1440 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1441 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1442 tmp1byte & (~BIT(6)));
1443 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
1444 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1445 tmp1byte &= ~(BIT(0));
1446 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1447 } else {
1448 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1449 rtl_read_byte(rtlpriv, REG_TXPAUSE) | BIT(6));
1450 }
1451}
1452
1453static void _rtl92cu_resume_tx_beacon(struct ieee80211_hw *hw)
1454{
1455 struct rtl_priv *rtlpriv = rtl_priv(hw);
1456 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1457 u8 tmp1byte = 0;
1458
1459 if (IS_NORMAL_CHIP(rtlhal->version)) {
1460 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1461 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1462 tmp1byte | BIT(6));
1463 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
1464 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1465 tmp1byte |= BIT(0);
1466 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1467 } else {
1468 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1469 rtl_read_byte(rtlpriv, REG_TXPAUSE) & (~BIT(6)));
1470 }
1471}
1472
1473static void _rtl92cu_enable_bcn_sub_func(struct ieee80211_hw *hw)
1474{
1475 struct rtl_priv *rtlpriv = rtl_priv(hw);
1476 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1477
1478 if (IS_NORMAL_CHIP(rtlhal->version))
1479 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(1));
1480 else
1481 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1482}
1483
1484static void _rtl92cu_disable_bcn_sub_func(struct ieee80211_hw *hw)
1485{
1486 struct rtl_priv *rtlpriv = rtl_priv(hw);
1487 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1488
1489 if (IS_NORMAL_CHIP(rtlhal->version))
1490 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(1), 0);
1491 else
1492 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1493}
1494
1495static int _rtl92cu_set_media_status(struct ieee80211_hw *hw,
1496 enum nl80211_iftype type)
1497{
1498 struct rtl_priv *rtlpriv = rtl_priv(hw);
1499 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1500 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1501
1502 bt_msr &= 0xfc;
1503 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xFF);
1504 if (type == NL80211_IFTYPE_UNSPECIFIED || type ==
1505 NL80211_IFTYPE_STATION) {
1506 _rtl92cu_stop_tx_beacon(hw);
1507 _rtl92cu_enable_bcn_sub_func(hw);
1508 } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) {
1509 _rtl92cu_resume_tx_beacon(hw);
1510 _rtl92cu_disable_bcn_sub_func(hw);
1511 } else {
1512 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, ("Set HW_VAR_MEDIA_"
1513 "STATUS:No such media status(%x).\n", type));
1514 }
1515 switch (type) {
1516 case NL80211_IFTYPE_UNSPECIFIED:
1517 bt_msr |= MSR_NOLINK;
1518 ledaction = LED_CTL_LINK;
1519 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1520 ("Set Network type to NO LINK!\n"));
1521 break;
1522 case NL80211_IFTYPE_ADHOC:
1523 bt_msr |= MSR_ADHOC;
1524 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1525 ("Set Network type to Ad Hoc!\n"));
1526 break;
1527 case NL80211_IFTYPE_STATION:
1528 bt_msr |= MSR_INFRA;
1529 ledaction = LED_CTL_LINK;
1530 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1531 ("Set Network type to STA!\n"));
1532 break;
1533 case NL80211_IFTYPE_AP:
1534 bt_msr |= MSR_AP;
1535 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1536 ("Set Network type to AP!\n"));
1537 break;
1538 default:
1539 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1540 ("Network type %d not support!\n", type));
1541 goto error_out;
1542 }
1543 rtl_write_byte(rtlpriv, (MSR), bt_msr);
1544 rtlpriv->cfg->ops->led_control(hw, ledaction);
1545 if ((bt_msr & 0xfc) == MSR_AP)
1546 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1547 else
1548 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1549 return 0;
1550error_out:
1551 return 1;
1552}
1553
1554void rtl92cu_card_disable(struct ieee80211_hw *hw)
1555{
1556 struct rtl_priv *rtlpriv = rtl_priv(hw);
1557 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1558 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1559 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1560 enum nl80211_iftype opmode;
1561
1562 mac->link_state = MAC80211_NOLINK;
1563 opmode = NL80211_IFTYPE_UNSPECIFIED;
1564 _rtl92cu_set_media_status(hw, opmode);
1565 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1566 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1567 if (rtlusb->disableHWSM)
1568 _CardDisableHWSM(hw);
1569 else
1570 _CardDisableWithoutHWSM(hw);
1571}
1572
1573void rtl92cu_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1574{
1575 /* dummy routine needed for callback from rtl_op_configure_filter() */
1576}
1577
1578/*========================================================================== */
1579
1580static void _rtl92cu_set_check_bssid(struct ieee80211_hw *hw,
1581 enum nl80211_iftype type)
1582{
1583 struct rtl_priv *rtlpriv = rtl_priv(hw);
1584 u32 reg_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1585 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1586 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1587 u8 filterout_non_associated_bssid = false;
1588
1589 switch (type) {
1590 case NL80211_IFTYPE_ADHOC:
1591 case NL80211_IFTYPE_STATION:
1592 filterout_non_associated_bssid = true;
1593 break;
1594 case NL80211_IFTYPE_UNSPECIFIED:
1595 case NL80211_IFTYPE_AP:
1596 default:
1597 break;
1598 }
1599 if (filterout_non_associated_bssid == true) {
1600 if (IS_NORMAL_CHIP(rtlhal->version)) {
1601 switch (rtlphy->current_io_type) {
1602 case IO_CMD_RESUME_DM_BY_SCAN:
1603 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1604 rtlpriv->cfg->ops->set_hw_reg(hw,
1605 HW_VAR_RCR, (u8 *)(&reg_rcr));
1606 /* enable update TSF */
1607 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1608 break;
1609 case IO_CMD_PAUSE_DM_BY_SCAN:
1610 reg_rcr &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1611 rtlpriv->cfg->ops->set_hw_reg(hw,
1612 HW_VAR_RCR, (u8 *)(&reg_rcr));
1613 /* disable update TSF */
1614 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1615 break;
1616 }
1617 } else {
1618 reg_rcr |= (RCR_CBSSID);
1619 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1620 (u8 *)(&reg_rcr));
1621 _rtl92cu_set_bcn_ctrl_reg(hw, 0, (BIT(4)|BIT(5)));
1622 }
1623 } else if (filterout_non_associated_bssid == false) {
1624 if (IS_NORMAL_CHIP(rtlhal->version)) {
1625 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1626 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1627 (u8 *)(&reg_rcr));
1628 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1629 } else {
1630 reg_rcr &= (~RCR_CBSSID);
1631 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1632 (u8 *)(&reg_rcr));
1633 _rtl92cu_set_bcn_ctrl_reg(hw, (BIT(4)|BIT(5)), 0);
1634 }
1635 }
1636}
1637
1638int rtl92cu_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1639{
1640 if (_rtl92cu_set_media_status(hw, type))
1641 return -EOPNOTSUPP;
1642 _rtl92cu_set_check_bssid(hw, type);
1643 return 0;
1644}
1645
1646static void _InitBeaconParameters(struct ieee80211_hw *hw)
1647{
1648 struct rtl_priv *rtlpriv = rtl_priv(hw);
1649 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1650
1651 rtl_write_word(rtlpriv, REG_BCN_CTRL, 0x1010);
1652
1653 /* TODO: Remove these magic number */
1654 rtl_write_word(rtlpriv, REG_TBTT_PROHIBIT, 0x6404);
1655 rtl_write_byte(rtlpriv, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);
1656 rtl_write_byte(rtlpriv, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME);
1657 /* Change beacon AIFS to the largest number
1658 * beacause test chip does not contension before sending beacon. */
1659 if (IS_NORMAL_CHIP(rtlhal->version))
1660 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660F);
1661 else
1662 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x66FF);
1663}
1664
1665static void _beacon_function_enable(struct ieee80211_hw *hw, bool Enable,
1666 bool Linked)
1667{
1668 struct rtl_priv *rtlpriv = rtl_priv(hw);
1669
1670 _rtl92cu_set_bcn_ctrl_reg(hw, (BIT(4) | BIT(3) | BIT(1)), 0x00);
1671 rtl_write_byte(rtlpriv, REG_RD_CTRL+1, 0x6F);
1672}
1673
1674void rtl92cu_set_beacon_related_registers(struct ieee80211_hw *hw)
1675{
1676
1677 struct rtl_priv *rtlpriv = rtl_priv(hw);
1678 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1679 u16 bcn_interval, atim_window;
1680 u32 value32;
1681
1682 bcn_interval = mac->beacon_interval;
1683 atim_window = 2; /*FIX MERGE */
1684 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1685 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1686 _InitBeaconParameters(hw);
1687 rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
1688 /*
1689 * Force beacon frame transmission even after receiving beacon frame
1690 * from other ad hoc STA
1691 *
1692 *
1693 * Reset TSF Timer to zero, added by Roger. 2008.06.24
1694 */
1695 value32 = rtl_read_dword(rtlpriv, REG_TCR);
1696 value32 &= ~TSFRST;
1697 rtl_write_dword(rtlpriv, REG_TCR, value32);
1698 value32 |= TSFRST;
1699 rtl_write_dword(rtlpriv, REG_TCR, value32);
1700 RT_TRACE(rtlpriv, COMP_INIT|COMP_BEACON, DBG_LOUD,
1701 ("SetBeaconRelatedRegisters8192CUsb(): Set TCR(%x)\n",
1702 value32));
1703 /* TODO: Modify later (Find the right parameters)
1704 * NOTE: Fix test chip's bug (about contention windows's randomness) */
1705 if ((mac->opmode == NL80211_IFTYPE_ADHOC) ||
1706 (mac->opmode == NL80211_IFTYPE_AP)) {
1707 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x50);
1708 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x50);
1709 }
1710 _beacon_function_enable(hw, true, true);
1711}
1712
1713void rtl92cu_set_beacon_interval(struct ieee80211_hw *hw)
1714{
1715 struct rtl_priv *rtlpriv = rtl_priv(hw);
1716 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1717 u16 bcn_interval = mac->beacon_interval;
1718
1719 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1720 ("beacon_interval:%d\n", bcn_interval));
1721 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1722}
1723
1724void rtl92cu_update_interrupt_mask(struct ieee80211_hw *hw,
1725 u32 add_msr, u32 rm_msr)
1726{
1727}
1728
1729void rtl92cu_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1730{
1731 struct rtl_priv *rtlpriv = rtl_priv(hw);
1732 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1733 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1734
1735 switch (variable) {
1736 case HW_VAR_RCR:
1737 *((u32 *)(val)) = mac->rx_conf;
1738 break;
1739 case HW_VAR_RF_STATE:
1740 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
1741 break;
1742 case HW_VAR_FWLPS_RF_ON:{
1743 enum rf_pwrstate rfState;
1744 u32 val_rcr;
1745
1746 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
1747 (u8 *)(&rfState));
1748 if (rfState == ERFOFF) {
1749 *((bool *) (val)) = true;
1750 } else {
1751 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1752 val_rcr &= 0x00070000;
1753 if (val_rcr)
1754 *((bool *) (val)) = false;
1755 else
1756 *((bool *) (val)) = true;
1757 }
1758 break;
1759 }
1760 case HW_VAR_FW_PSMODE_STATUS:
1761 *((bool *) (val)) = ppsc->fw_current_inpsmode;
1762 break;
1763 case HW_VAR_CORRECT_TSF:{
1764 u64 tsf;
1765 u32 *ptsf_low = (u32 *)&tsf;
1766 u32 *ptsf_high = ((u32 *)&tsf) + 1;
1767
1768 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
1769 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
1770 *((u64 *)(val)) = tsf;
1771 break;
1772 }
1773 case HW_VAR_MGT_FILTER:
1774 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP0);
1775 break;
1776 case HW_VAR_CTRL_FILTER:
1777 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP1);
1778 break;
1779 case HW_VAR_DATA_FILTER:
1780 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP2);
1781 break;
1782 default:
1783 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1784 ("switch case not process\n"));
1785 break;
1786 }
1787}
1788
1789void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1790{
1791 struct rtl_priv *rtlpriv = rtl_priv(hw);
1792 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1793 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1794 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1795 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1796 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1797 enum wireless_mode wirelessmode = mac->mode;
1798 u8 idx = 0;
1799
1800 switch (variable) {
1801 case HW_VAR_ETHER_ADDR:{
1802 for (idx = 0; idx < ETH_ALEN; idx++) {
1803 rtl_write_byte(rtlpriv, (REG_MACID + idx),
1804 val[idx]);
1805 }
1806 break;
1807 }
1808 case HW_VAR_BASIC_RATE:{
1809 u16 rate_cfg = ((u16 *) val)[0];
1810 u8 rate_index = 0;
1811
1812 rate_cfg &= 0x15f;
1813 /* TODO */
1814 /* if (mac->current_network.vender == HT_IOT_PEER_CISCO
1815 * && ((rate_cfg & 0x150) == 0)) {
1816 * rate_cfg |= 0x010;
1817 * } */
1818 rate_cfg |= 0x01;
1819 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
1820 rtl_write_byte(rtlpriv, REG_RRSR + 1,
1821 (rate_cfg >> 8) & 0xff);
1822 while (rate_cfg > 0x1) {
1823 rate_cfg >>= 1;
1824 rate_index++;
1825 }
1826 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
1827 rate_index);
1828 break;
1829 }
1830 case HW_VAR_BSSID:{
1831 for (idx = 0; idx < ETH_ALEN; idx++) {
1832 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
1833 val[idx]);
1834 }
1835 break;
1836 }
1837 case HW_VAR_SIFS:{
1838 rtl_write_byte(rtlpriv, REG_SIFS_CCK + 1, val[0]);
1839 rtl_write_byte(rtlpriv, REG_SIFS_OFDM + 1, val[1]);
1840 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
1841 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
1842 rtl_write_byte(rtlpriv, REG_R2T_SIFS+1, val[0]);
1843 rtl_write_byte(rtlpriv, REG_T2T_SIFS+1, val[0]);
1844 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1845 ("HW_VAR_SIFS\n"));
1846 break;
1847 }
1848 case HW_VAR_SLOT_TIME:{
1849 u8 e_aci;
1850 u8 QOS_MODE = 1;
1851
1852 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
1853 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1854 ("HW_VAR_SLOT_TIME %x\n", val[0]));
1855 if (QOS_MODE) {
1856 for (e_aci = 0; e_aci < AC_MAX; e_aci++)
1857 rtlpriv->cfg->ops->set_hw_reg(hw,
1858 HW_VAR_AC_PARAM,
1859 (u8 *)(&e_aci));
1860 } else {
1861 u8 sifstime = 0;
1862 u8 u1bAIFS;
1863
1864 if (IS_WIRELESS_MODE_A(wirelessmode) ||
1865 IS_WIRELESS_MODE_N_24G(wirelessmode) ||
1866 IS_WIRELESS_MODE_N_5G(wirelessmode))
1867 sifstime = 16;
1868 else
1869 sifstime = 10;
1870 u1bAIFS = sifstime + (2 * val[0]);
1871 rtl_write_byte(rtlpriv, REG_EDCA_VO_PARAM,
1872 u1bAIFS);
1873 rtl_write_byte(rtlpriv, REG_EDCA_VI_PARAM,
1874 u1bAIFS);
1875 rtl_write_byte(rtlpriv, REG_EDCA_BE_PARAM,
1876 u1bAIFS);
1877 rtl_write_byte(rtlpriv, REG_EDCA_BK_PARAM,
1878 u1bAIFS);
1879 }
1880 break;
1881 }
1882 case HW_VAR_ACK_PREAMBLE:{
1883 u8 reg_tmp;
1884 u8 short_preamble = (bool) (*(u8 *) val);
1885 reg_tmp = 0;
1886 if (short_preamble)
1887 reg_tmp |= 0x80;
1888 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
1889 break;
1890 }
1891 case HW_VAR_AMPDU_MIN_SPACE:{
1892 u8 min_spacing_to_set;
1893 u8 sec_min_space;
1894
1895 min_spacing_to_set = *((u8 *) val);
1896 if (min_spacing_to_set <= 7) {
1897 switch (rtlpriv->sec.pairwise_enc_algorithm) {
1898 case NO_ENCRYPTION:
1899 case AESCCMP_ENCRYPTION:
1900 sec_min_space = 0;
1901 break;
1902 case WEP40_ENCRYPTION:
1903 case WEP104_ENCRYPTION:
1904 case TKIP_ENCRYPTION:
1905 sec_min_space = 6;
1906 break;
1907 default:
1908 sec_min_space = 7;
1909 break;
1910 }
1911 if (min_spacing_to_set < sec_min_space)
1912 min_spacing_to_set = sec_min_space;
1913 mac->min_space_cfg = ((mac->min_space_cfg &
1914 0xf8) |
1915 min_spacing_to_set);
1916 *val = min_spacing_to_set;
1917 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1918 ("Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
1919 mac->min_space_cfg));
1920 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1921 mac->min_space_cfg);
1922 }
1923 break;
1924 }
1925 case HW_VAR_SHORTGI_DENSITY:{
1926 u8 density_to_set;
1927
1928 density_to_set = *((u8 *) val);
1929 density_to_set &= 0x1f;
1930 mac->min_space_cfg &= 0x07;
1931 mac->min_space_cfg |= (density_to_set << 3);
1932 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1933 ("Set HW_VAR_SHORTGI_DENSITY: %#x\n",
1934 mac->min_space_cfg));
1935 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1936 mac->min_space_cfg);
1937 break;
1938 }
1939 case HW_VAR_AMPDU_FACTOR:{
1940 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
1941 u8 factor_toset;
1942 u8 *p_regtoset = NULL;
1943 u8 index = 0;
1944
1945 p_regtoset = regtoset_normal;
1946 factor_toset = *((u8 *) val);
1947 if (factor_toset <= 3) {
1948 factor_toset = (1 << (factor_toset + 2));
1949 if (factor_toset > 0xf)
1950 factor_toset = 0xf;
1951 for (index = 0; index < 4; index++) {
1952 if ((p_regtoset[index] & 0xf0) >
1953 (factor_toset << 4))
1954 p_regtoset[index] =
1955 (p_regtoset[index] & 0x0f)
1956 | (factor_toset << 4);
1957 if ((p_regtoset[index] & 0x0f) >
1958 factor_toset)
1959 p_regtoset[index] =
1960 (p_regtoset[index] & 0xf0)
1961 | (factor_toset);
1962 rtl_write_byte(rtlpriv,
1963 (REG_AGGLEN_LMT + index),
1964 p_regtoset[index]);
1965 }
1966 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1967 ("Set HW_VAR_AMPDU_FACTOR: %#x\n",
1968 factor_toset));
1969 }
1970 break;
1971 }
1972 case HW_VAR_AC_PARAM:{
1973 u8 e_aci = *((u8 *) val);
1974 u32 u4b_ac_param;
1975 u16 cw_min = le16_to_cpu(mac->ac[e_aci].cw_min);
1976 u16 cw_max = le16_to_cpu(mac->ac[e_aci].cw_max);
1977 u16 tx_op = le16_to_cpu(mac->ac[e_aci].tx_op);
1978
1979 u4b_ac_param = (u32) mac->ac[e_aci].aifs;
1980 u4b_ac_param |= (u32) ((cw_min & 0xF) <<
1981 AC_PARAM_ECW_MIN_OFFSET);
1982 u4b_ac_param |= (u32) ((cw_max & 0xF) <<
1983 AC_PARAM_ECW_MAX_OFFSET);
1984 u4b_ac_param |= (u32) tx_op << AC_PARAM_TXOP_OFFSET;
1985 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1986 ("queue:%x, ac_param:%x\n", e_aci,
1987 u4b_ac_param));
1988 switch (e_aci) {
1989 case AC1_BK:
1990 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM,
1991 u4b_ac_param);
1992 break;
1993 case AC0_BE:
1994 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM,
1995 u4b_ac_param);
1996 break;
1997 case AC2_VI:
1998 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM,
1999 u4b_ac_param);
2000 break;
2001 case AC3_VO:
2002 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM,
2003 u4b_ac_param);
2004 break;
2005 default:
2006 RT_ASSERT(false, ("SetHwReg8185(): invalid"
2007 " aci: %d !\n", e_aci));
2008 break;
2009 }
2010 if (rtlusb->acm_method != eAcmWay2_SW)
2011 rtlpriv->cfg->ops->set_hw_reg(hw,
2012 HW_VAR_ACM_CTRL, (u8 *)(&e_aci));
2013 break;
2014 }
2015 case HW_VAR_ACM_CTRL:{
2016 u8 e_aci = *((u8 *) val);
2017 union aci_aifsn *p_aci_aifsn = (union aci_aifsn *)
2018 (&(mac->ac[0].aifs));
2019 u8 acm = p_aci_aifsn->f.acm;
2020 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
2021
2022 acm_ctrl =
2023 acm_ctrl | ((rtlusb->acm_method == 2) ? 0x0 : 0x1);
2024 if (acm) {
2025 switch (e_aci) {
2026 case AC0_BE:
2027 acm_ctrl |= AcmHw_BeqEn;
2028 break;
2029 case AC2_VI:
2030 acm_ctrl |= AcmHw_ViqEn;
2031 break;
2032 case AC3_VO:
2033 acm_ctrl |= AcmHw_VoqEn;
2034 break;
2035 default:
2036 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2037 ("HW_VAR_ACM_CTRL acm set "
2038 "failed: eACI is %d\n", acm));
2039 break;
2040 }
2041 } else {
2042 switch (e_aci) {
2043 case AC0_BE:
2044 acm_ctrl &= (~AcmHw_BeqEn);
2045 break;
2046 case AC2_VI:
2047 acm_ctrl &= (~AcmHw_ViqEn);
2048 break;
2049 case AC3_VO:
2050 acm_ctrl &= (~AcmHw_BeqEn);
2051 break;
2052 default:
2053 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2054 ("switch case not process\n"));
2055 break;
2056 }
2057 }
2058 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
2059 ("SetHwReg8190pci(): [HW_VAR_ACM_CTRL] "
2060 "Write 0x%X\n", acm_ctrl));
2061 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
2062 break;
2063 }
2064 case HW_VAR_RCR:{
2065 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
2066 mac->rx_conf = ((u32 *) (val))[0];
2067 RT_TRACE(rtlpriv, COMP_RECV, DBG_DMESG,
2068 ("### Set RCR(0x%08x) ###\n", mac->rx_conf));
2069 break;
2070 }
2071 case HW_VAR_RETRY_LIMIT:{
2072 u8 retry_limit = ((u8 *) (val))[0];
2073
2074 rtl_write_word(rtlpriv, REG_RL,
2075 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
2076 retry_limit << RETRY_LIMIT_LONG_SHIFT);
2077 RT_TRACE(rtlpriv, COMP_MLME, DBG_DMESG, ("Set HW_VAR_R"
2078 "ETRY_LIMIT(0x%08x)\n", retry_limit));
2079 break;
2080 }
2081 case HW_VAR_DUAL_TSF_RST:
2082 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
2083 break;
2084 case HW_VAR_EFUSE_BYTES:
2085 rtlefuse->efuse_usedbytes = *((u16 *) val);
2086 break;
2087 case HW_VAR_EFUSE_USAGE:
2088 rtlefuse->efuse_usedpercentage = *((u8 *) val);
2089 break;
2090 case HW_VAR_IO_CMD:
2091 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
2092 break;
2093 case HW_VAR_WPA_CONFIG:
2094 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *) val));
2095 break;
2096 case HW_VAR_SET_RPWM:{
2097 u8 rpwm_val = rtl_read_byte(rtlpriv, REG_USB_HRPWM);
2098
2099 if (rpwm_val & BIT(7))
2100 rtl_write_byte(rtlpriv, REG_USB_HRPWM,
2101 (*(u8 *)val));
2102 else
2103 rtl_write_byte(rtlpriv, REG_USB_HRPWM,
2104 ((*(u8 *)val) | BIT(7)));
2105 break;
2106 }
2107 case HW_VAR_H2C_FW_PWRMODE:{
2108 u8 psmode = (*(u8 *) val);
2109
2110 if ((psmode != FW_PS_ACTIVE_MODE) &&
2111 (!IS_92C_SERIAL(rtlhal->version)))
2112 rtl92c_dm_rf_saving(hw, true);
2113 rtl92c_set_fw_pwrmode_cmd(hw, (*(u8 *) val));
2114 break;
2115 }
2116 case HW_VAR_FW_PSMODE_STATUS:
2117 ppsc->fw_current_inpsmode = *((bool *) val);
2118 break;
2119 case HW_VAR_H2C_FW_JOINBSSRPT:{
2120 u8 mstatus = (*(u8 *) val);
2121 u8 tmp_reg422;
2122 bool recover = false;
2123
2124 if (mstatus == RT_MEDIA_CONNECT) {
2125 rtlpriv->cfg->ops->set_hw_reg(hw,
2126 HW_VAR_AID, NULL);
2127 rtl_write_byte(rtlpriv, REG_CR + 1, 0x03);
2128 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
2129 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
2130 tmp_reg422 = rtl_read_byte(rtlpriv,
2131 REG_FWHW_TXQ_CTRL + 2);
2132 if (tmp_reg422 & BIT(6))
2133 recover = true;
2134 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
2135 tmp_reg422 & (~BIT(6)));
2136 rtl92c_set_fw_rsvdpagepkt(hw, 0);
2137 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
2138 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
2139 if (recover)
2140 rtl_write_byte(rtlpriv,
2141 REG_FWHW_TXQ_CTRL + 2,
2142 tmp_reg422 | BIT(6));
2143 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
2144 }
2145 rtl92c_set_fw_joinbss_report_cmd(hw, (*(u8 *) val));
2146 break;
2147 }
2148 case HW_VAR_AID:{
2149 u16 u2btmp;
2150
2151 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
2152 u2btmp &= 0xC000;
2153 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
2154 (u2btmp | mac->assoc_id));
2155 break;
2156 }
2157 case HW_VAR_CORRECT_TSF:{
2158 u8 btype_ibss = ((u8 *) (val))[0];
2159
2160 if (btype_ibss == true)
2161 _rtl92cu_stop_tx_beacon(hw);
2162 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
2163 rtl_write_dword(rtlpriv, REG_TSFTR, (u32)(mac->tsf &
2164 0xffffffff));
2165 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
2166 (u32)((mac->tsf >> 32) & 0xffffffff));
2167 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
2168 if (btype_ibss == true)
2169 _rtl92cu_resume_tx_beacon(hw);
2170 break;
2171 }
2172 case HW_VAR_MGT_FILTER:
2173 rtl_write_word(rtlpriv, REG_RXFLTMAP0, *(u16 *)val);
2174 break;
2175 case HW_VAR_CTRL_FILTER:
2176 rtl_write_word(rtlpriv, REG_RXFLTMAP1, *(u16 *)val);
2177 break;
2178 case HW_VAR_DATA_FILTER:
2179 rtl_write_word(rtlpriv, REG_RXFLTMAP2, *(u16 *)val);
2180 break;
2181 default:
2182 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("switch case "
2183 "not process\n"));
2184 break;
2185 }
2186}
2187
2188void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw)
2189{
2190 struct rtl_priv *rtlpriv = rtl_priv(hw);
2191 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2192 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2193 u32 ratr_value = (u32) mac->basic_rates;
2194 u8 *mcsrate = mac->mcs;
2195 u8 ratr_index = 0;
2196 u8 nmode = mac->ht_enable;
2197 u8 mimo_ps = 1;
2198 u16 shortgi_rate = 0;
2199 u32 tmp_ratr_value = 0;
2200 u8 curtxbw_40mhz = mac->bw_40;
2201 u8 curshortgi_40mhz = mac->sgi_40;
2202 u8 curshortgi_20mhz = mac->sgi_20;
2203 enum wireless_mode wirelessmode = mac->mode;
2204
2205 ratr_value |= ((*(u16 *) (mcsrate))) << 12;
2206 switch (wirelessmode) {
2207 case WIRELESS_MODE_B:
2208 if (ratr_value & 0x0000000c)
2209 ratr_value &= 0x0000000d;
2210 else
2211 ratr_value &= 0x0000000f;
2212 break;
2213 case WIRELESS_MODE_G:
2214 ratr_value &= 0x00000FF5;
2215 break;
2216 case WIRELESS_MODE_N_24G:
2217 case WIRELESS_MODE_N_5G:
2218 nmode = 1;
2219 if (mimo_ps == 0) {
2220 ratr_value &= 0x0007F005;
2221 } else {
2222 u32 ratr_mask;
2223
2224 if (get_rf_type(rtlphy) == RF_1T2R ||
2225 get_rf_type(rtlphy) == RF_1T1R)
2226 ratr_mask = 0x000ff005;
2227 else
2228 ratr_mask = 0x0f0ff005;
2229 if (curtxbw_40mhz)
2230 ratr_mask |= 0x00000010;
2231 ratr_value &= ratr_mask;
2232 }
2233 break;
2234 default:
2235 if (rtlphy->rf_type == RF_1T2R)
2236 ratr_value &= 0x000ff0ff;
2237 else
2238 ratr_value &= 0x0f0ff0ff;
2239 break;
2240 }
2241 ratr_value &= 0x0FFFFFFF;
2242 if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) ||
2243 (!curtxbw_40mhz && curshortgi_20mhz))) {
2244 ratr_value |= 0x10000000;
2245 tmp_ratr_value = (ratr_value >> 12);
2246 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2247 if ((1 << shortgi_rate) & tmp_ratr_value)
2248 break;
2249 }
2250 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2251 (shortgi_rate << 4) | (shortgi_rate);
2252 }
2253 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
2254 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, ("%x\n", rtl_read_dword(rtlpriv,
2255 REG_ARFR0)));
2256}
2257
2258void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level)
2259{
2260 struct rtl_priv *rtlpriv = rtl_priv(hw);
2261 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2262 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2263 u32 ratr_bitmap = (u32) mac->basic_rates;
2264 u8 *p_mcsrate = mac->mcs;
2265 u8 ratr_index = 0;
2266 u8 curtxbw_40mhz = mac->bw_40;
2267 u8 curshortgi_40mhz = mac->sgi_40;
2268 u8 curshortgi_20mhz = mac->sgi_20;
2269 enum wireless_mode wirelessmode = mac->mode;
2270 bool shortgi = false;
2271 u8 rate_mask[5];
2272 u8 macid = 0;
2273 u8 mimops = 1;
2274
2275 ratr_bitmap |= (p_mcsrate[1] << 20) | (p_mcsrate[0] << 12);
2276 switch (wirelessmode) {
2277 case WIRELESS_MODE_B:
2278 ratr_index = RATR_INX_WIRELESS_B;
2279 if (ratr_bitmap & 0x0000000c)
2280 ratr_bitmap &= 0x0000000d;
2281 else
2282 ratr_bitmap &= 0x0000000f;
2283 break;
2284 case WIRELESS_MODE_G:
2285 ratr_index = RATR_INX_WIRELESS_GB;
2286 if (rssi_level == 1)
2287 ratr_bitmap &= 0x00000f00;
2288 else if (rssi_level == 2)
2289 ratr_bitmap &= 0x00000ff0;
2290 else
2291 ratr_bitmap &= 0x00000ff5;
2292 break;
2293 case WIRELESS_MODE_A:
2294 ratr_index = RATR_INX_WIRELESS_A;
2295 ratr_bitmap &= 0x00000ff0;
2296 break;
2297 case WIRELESS_MODE_N_24G:
2298 case WIRELESS_MODE_N_5G:
2299 ratr_index = RATR_INX_WIRELESS_NGB;
2300 if (mimops == 0) {
2301 if (rssi_level == 1)
2302 ratr_bitmap &= 0x00070000;
2303 else if (rssi_level == 2)
2304 ratr_bitmap &= 0x0007f000;
2305 else
2306 ratr_bitmap &= 0x0007f005;
2307 } else {
2308 if (rtlphy->rf_type == RF_1T2R ||
2309 rtlphy->rf_type == RF_1T1R) {
2310 if (curtxbw_40mhz) {
2311 if (rssi_level == 1)
2312 ratr_bitmap &= 0x000f0000;
2313 else if (rssi_level == 2)
2314 ratr_bitmap &= 0x000ff000;
2315 else
2316 ratr_bitmap &= 0x000ff015;
2317 } else {
2318 if (rssi_level == 1)
2319 ratr_bitmap &= 0x000f0000;
2320 else if (rssi_level == 2)
2321 ratr_bitmap &= 0x000ff000;
2322 else
2323 ratr_bitmap &= 0x000ff005;
2324 }
2325 } else {
2326 if (curtxbw_40mhz) {
2327 if (rssi_level == 1)
2328 ratr_bitmap &= 0x0f0f0000;
2329 else if (rssi_level == 2)
2330 ratr_bitmap &= 0x0f0ff000;
2331 else
2332 ratr_bitmap &= 0x0f0ff015;
2333 } else {
2334 if (rssi_level == 1)
2335 ratr_bitmap &= 0x0f0f0000;
2336 else if (rssi_level == 2)
2337 ratr_bitmap &= 0x0f0ff000;
2338 else
2339 ratr_bitmap &= 0x0f0ff005;
2340 }
2341 }
2342 }
2343 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2344 (!curtxbw_40mhz && curshortgi_20mhz)) {
2345 if (macid == 0)
2346 shortgi = true;
2347 else if (macid == 1)
2348 shortgi = false;
2349 }
2350 break;
2351 default:
2352 ratr_index = RATR_INX_WIRELESS_NGB;
2353 if (rtlphy->rf_type == RF_1T2R)
2354 ratr_bitmap &= 0x000ff0ff;
2355 else
2356 ratr_bitmap &= 0x0f0ff0ff;
2357 break;
2358 }
2359 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, ("ratr_bitmap :%x\n",
2360 ratr_bitmap));
2361 *(u32 *)&rate_mask = ((ratr_bitmap & 0x0fffffff) |
2362 ratr_index << 28);
2363 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2364 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, ("Rate_index:%x, "
2365 "ratr_val:%x, %x:%x:%x:%x:%x\n",
2366 ratr_index, ratr_bitmap,
2367 rate_mask[0], rate_mask[1],
2368 rate_mask[2], rate_mask[3],
2369 rate_mask[4]));
2370 rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
2371}
2372
2373void rtl92cu_update_channel_access_setting(struct ieee80211_hw *hw)
2374{
2375 struct rtl_priv *rtlpriv = rtl_priv(hw);
2376 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2377 u16 sifs_timer;
2378
2379 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2380 (u8 *)&mac->slot_time);
2381 if (!mac->ht_enable)
2382 sifs_timer = 0x0a0a;
2383 else
2384 sifs_timer = 0x0e0e;
2385 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2386}
2387
2388bool rtl92cu_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid)
2389{
2390 struct rtl_priv *rtlpriv = rtl_priv(hw);
2391 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2392 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2393 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
2394 u8 u1tmp = 0;
2395 bool actuallyset = false;
2396 unsigned long flag = 0;
2397 /* to do - usb autosuspend */
2398 u8 usb_autosuspend = 0;
2399
2400 if (ppsc->swrf_processing)
2401 return false;
2402 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2403 if (ppsc->rfchange_inprogress) {
2404 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2405 return false;
2406 } else {
2407 ppsc->rfchange_inprogress = true;
2408 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2409 }
2410 cur_rfstate = ppsc->rfpwr_state;
2411 if (usb_autosuspend) {
2412 /* to do................... */
2413 } else {
2414 if (ppsc->pwrdown_mode) {
2415 u1tmp = rtl_read_byte(rtlpriv, REG_HSISR);
2416 e_rfpowerstate_toset = (u1tmp & BIT(7)) ?
2417 ERFOFF : ERFON;
2418 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
2419 ("pwrdown, 0x5c(BIT7)=%02x\n", u1tmp));
2420 } else {
2421 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG,
2422 rtl_read_byte(rtlpriv,
2423 REG_MAC_PINMUX_CFG) & ~(BIT(3)));
2424 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2425 e_rfpowerstate_toset = (u1tmp & BIT(3)) ?
2426 ERFON : ERFOFF;
2427 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
2428 ("GPIO_IN=%02x\n", u1tmp));
2429 }
2430 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, ("N-SS RF =%x\n",
2431 e_rfpowerstate_toset));
2432 }
2433 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2434 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, ("GPIOChangeRF - HW "
2435 "Radio ON, RF ON\n"));
2436 ppsc->hwradiooff = false;
2437 actuallyset = true;
2438 } else if ((!ppsc->hwradiooff) && (e_rfpowerstate_toset ==
2439 ERFOFF)) {
2440 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, ("GPIOChangeRF - HW"
2441 " Radio OFF\n"));
2442 ppsc->hwradiooff = true;
2443 actuallyset = true;
2444 } else {
2445 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD ,
2446 ("pHalData->bHwRadioOff and eRfPowerStateToSet do not"
2447 " match: pHalData->bHwRadioOff %x, eRfPowerStateToSet "
2448 "%x\n", ppsc->hwradiooff, e_rfpowerstate_toset));
2449 }
2450 if (actuallyset) {
2451 ppsc->hwradiooff = 1;
2452 if (e_rfpowerstate_toset == ERFON) {
2453 if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) &&
2454 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM))
2455 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2456 else if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2457 && RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3))
2458 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2459 }
2460 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2461 ppsc->rfchange_inprogress = false;
2462 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2463 /* For power down module, we need to enable register block
2464 * contrl reg at 0x1c. Then enable power down control bit
2465 * of register 0x04 BIT4 and BIT15 as 1.
2466 */
2467 if (ppsc->pwrdown_mode && e_rfpowerstate_toset == ERFOFF) {
2468 /* Enable register area 0x0-0xc. */
2469 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
2470 if (IS_HARDWARE_TYPE_8723U(rtlhal)) {
2471 /*
2472 * We should configure HW PDn source for WiFi
2473 * ONLY, and then our HW will be set in
2474 * power-down mode if PDn source from all
2475 * functions are configured.
2476 */
2477 u1tmp = rtl_read_byte(rtlpriv,
2478 REG_MULTI_FUNC_CTRL);
2479 rtl_write_byte(rtlpriv, REG_MULTI_FUNC_CTRL,
2480 (u1tmp|WL_HWPDN_EN));
2481 } else {
2482 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x8812);
2483 }
2484 }
2485 if (e_rfpowerstate_toset == ERFOFF) {
2486 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM)
2487 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2488 else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2489 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2490 }
2491 } else if (e_rfpowerstate_toset == ERFOFF || cur_rfstate == ERFOFF) {
2492 /* Enter D3 or ASPM after GPIO had been done. */
2493 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM)
2494 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2495 else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2496 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2497 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2498 ppsc->rfchange_inprogress = false;
2499 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2500 } else {
2501 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2502 ppsc->rfchange_inprogress = false;
2503 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2504 }
2505 *valid = 1;
2506 return !ppsc->hwradiooff;
2507}