Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 1 | /* arch/arm/mach-s3c2410/include/mach/regs-serial.h |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | * |
| 3 | * From linux/include/asm-arm/hardware/serial_s3c2410.h |
| 4 | * |
| 5 | * Internal header file for Samsung S3C2410 serial ports (UART0-2) |
| 6 | * |
| 7 | * Copyright (C) 2002 Shane Nay (shane@minirl.com) |
| 8 | * |
Ben Dooks | 50f430e | 2009-11-13 22:54:12 +0000 | [diff] [blame] | 9 | * Additional defines, Copyright 2003 Simtec Electronics (linux@simtec.co.uk) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10 | * |
| 11 | * Adapted from: |
| 12 | * |
| 13 | * Internal header file for MX1ADS serial ports (UART1 & 2) |
| 14 | * |
| 15 | * Copyright (C) 2002 Shane Nay (shane@minirl.com) |
| 16 | * |
| 17 | * This program is free software; you can redistribute it and/or modify |
| 18 | * it under the terms of the GNU General Public License as published by |
| 19 | * the Free Software Foundation; either version 2 of the License, or |
| 20 | * (at your option) any later version. |
| 21 | * |
| 22 | * This program is distributed in the hope that it will be useful, |
| 23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 25 | * GNU General Public License for more details. |
| 26 | * |
| 27 | * You should have received a copy of the GNU General Public License |
| 28 | * along with this program; if not, write to the Free Software |
| 29 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
Ben Dooks | 92e4805 | 2006-09-09 19:44:54 +0100 | [diff] [blame] | 30 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 31 | |
| 32 | #ifndef __ASM_ARM_REGS_SERIAL_H |
| 33 | #define __ASM_ARM_REGS_SERIAL_H |
| 34 | |
Ben Dooks | 530ef3c | 2007-07-22 16:59:44 +0100 | [diff] [blame] | 35 | #define S3C24XX_VA_UART0 (S3C_VA_UART) |
| 36 | #define S3C24XX_VA_UART1 (S3C_VA_UART + 0x4000 ) |
| 37 | #define S3C24XX_VA_UART2 (S3C_VA_UART + 0x8000 ) |
| 38 | #define S3C24XX_VA_UART3 (S3C_VA_UART + 0xC000 ) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 39 | |
Lucas Correia Villa Real | 0367a8d | 2006-01-26 15:20:50 +0000 | [diff] [blame] | 40 | #define S3C2410_PA_UART0 (S3C24XX_PA_UART) |
| 41 | #define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 ) |
| 42 | #define S3C2410_PA_UART2 (S3C24XX_PA_UART + 0x8000 ) |
Ben Dooks | 092651c | 2007-02-15 12:57:20 +0100 | [diff] [blame] | 43 | #define S3C2443_PA_UART3 (S3C24XX_PA_UART + 0xC000 ) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 44 | |
| 45 | #define S3C2410_URXH (0x24) |
| 46 | #define S3C2410_UTXH (0x20) |
| 47 | #define S3C2410_ULCON (0x00) |
| 48 | #define S3C2410_UCON (0x04) |
| 49 | #define S3C2410_UFCON (0x08) |
| 50 | #define S3C2410_UMCON (0x0C) |
| 51 | #define S3C2410_UBRDIV (0x28) |
| 52 | #define S3C2410_UTRSTAT (0x10) |
| 53 | #define S3C2410_UERSTAT (0x14) |
| 54 | #define S3C2410_UFSTAT (0x18) |
| 55 | #define S3C2410_UMSTAT (0x1C) |
| 56 | |
| 57 | #define S3C2410_LCON_CFGMASK ((0xF<<3)|(0x3)) |
| 58 | |
| 59 | #define S3C2410_LCON_CS5 (0x0) |
| 60 | #define S3C2410_LCON_CS6 (0x1) |
| 61 | #define S3C2410_LCON_CS7 (0x2) |
| 62 | #define S3C2410_LCON_CS8 (0x3) |
| 63 | #define S3C2410_LCON_CSMASK (0x3) |
| 64 | |
| 65 | #define S3C2410_LCON_PNONE (0x0) |
| 66 | #define S3C2410_LCON_PEVEN (0x5 << 3) |
| 67 | #define S3C2410_LCON_PODD (0x4 << 3) |
| 68 | #define S3C2410_LCON_PMASK (0x7 << 3) |
| 69 | |
| 70 | #define S3C2410_LCON_STOPB (1<<2) |
| 71 | #define S3C2410_LCON_IRM (1<<6) |
| 72 | |
| 73 | #define S3C2440_UCON_CLKMASK (3<<10) |
| 74 | #define S3C2440_UCON_PCLK (0<<10) |
| 75 | #define S3C2440_UCON_UCLK (1<<10) |
| 76 | #define S3C2440_UCON_PCLK2 (2<<10) |
| 77 | #define S3C2440_UCON_FCLK (3<<10) |
Ben Dooks | 092651c | 2007-02-15 12:57:20 +0100 | [diff] [blame] | 78 | #define S3C2443_UCON_EPLL (3<<10) |
| 79 | |
Ben Dooks | b690ace | 2008-10-21 14:07:03 +0100 | [diff] [blame] | 80 | #define S3C6400_UCON_CLKMASK (3<<10) |
| 81 | #define S3C6400_UCON_PCLK (0<<10) |
| 82 | #define S3C6400_UCON_PCLK2 (2<<10) |
| 83 | #define S3C6400_UCON_UCLK0 (1<<10) |
| 84 | #define S3C6400_UCON_UCLK1 (3<<10) |
| 85 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 86 | #define S3C2440_UCON2_FCLK_EN (1<<15) |
| 87 | #define S3C2440_UCON0_DIVMASK (15 << 12) |
| 88 | #define S3C2440_UCON1_DIVMASK (15 << 12) |
| 89 | #define S3C2440_UCON2_DIVMASK (7 << 12) |
| 90 | #define S3C2440_UCON_DIVSHIFT (12) |
| 91 | |
Ben Dooks | 73e55cb | 2006-06-24 21:21:32 +0100 | [diff] [blame] | 92 | #define S3C2412_UCON_CLKMASK (3<<10) |
| 93 | #define S3C2412_UCON_UCLK (1<<10) |
| 94 | #define S3C2412_UCON_USYSCLK (3<<10) |
| 95 | #define S3C2412_UCON_PCLK (0<<10) |
| 96 | #define S3C2412_UCON_PCLK2 (2<<10) |
| 97 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 98 | #define S3C2410_UCON_UCLK (1<<10) |
| 99 | #define S3C2410_UCON_SBREAK (1<<4) |
| 100 | |
| 101 | #define S3C2410_UCON_TXILEVEL (1<<9) |
| 102 | #define S3C2410_UCON_RXILEVEL (1<<8) |
| 103 | #define S3C2410_UCON_TXIRQMODE (1<<2) |
| 104 | #define S3C2410_UCON_RXIRQMODE (1<<0) |
| 105 | #define S3C2410_UCON_RXFIFO_TOI (1<<7) |
Ben Dooks | 092651c | 2007-02-15 12:57:20 +0100 | [diff] [blame] | 106 | #define S3C2443_UCON_RXERR_IRQEN (1<<6) |
| 107 | #define S3C2443_UCON_LOOPBACK (1<<5) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 108 | |
| 109 | #define S3C2410_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ |
| 110 | S3C2410_UCON_RXILEVEL | \ |
| 111 | S3C2410_UCON_TXIRQMODE | \ |
| 112 | S3C2410_UCON_RXIRQMODE | \ |
| 113 | S3C2410_UCON_RXFIFO_TOI) |
| 114 | |
| 115 | #define S3C2410_UFCON_FIFOMODE (1<<0) |
| 116 | #define S3C2410_UFCON_TXTRIG0 (0<<6) |
| 117 | #define S3C2410_UFCON_RXTRIG8 (1<<4) |
| 118 | #define S3C2410_UFCON_RXTRIG12 (2<<4) |
| 119 | |
| 120 | /* S3C2440 FIFO trigger levels */ |
| 121 | #define S3C2440_UFCON_RXTRIG1 (0<<4) |
| 122 | #define S3C2440_UFCON_RXTRIG8 (1<<4) |
| 123 | #define S3C2440_UFCON_RXTRIG16 (2<<4) |
| 124 | #define S3C2440_UFCON_RXTRIG32 (3<<4) |
| 125 | |
| 126 | #define S3C2440_UFCON_TXTRIG0 (0<<6) |
| 127 | #define S3C2440_UFCON_TXTRIG16 (1<<6) |
| 128 | #define S3C2440_UFCON_TXTRIG32 (2<<6) |
| 129 | #define S3C2440_UFCON_TXTRIG48 (3<<6) |
| 130 | |
| 131 | #define S3C2410_UFCON_RESETBOTH (3<<1) |
| 132 | #define S3C2410_UFCON_RESETTX (1<<2) |
| 133 | #define S3C2410_UFCON_RESETRX (1<<1) |
| 134 | |
| 135 | #define S3C2410_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ |
| 136 | S3C2410_UFCON_TXTRIG0 | \ |
| 137 | S3C2410_UFCON_RXTRIG8 ) |
| 138 | |
| 139 | #define S3C2410_UMCOM_AFC (1<<4) |
| 140 | #define S3C2410_UMCOM_RTS_LOW (1<<0) |
| 141 | |
Ben Dooks | 092651c | 2007-02-15 12:57:20 +0100 | [diff] [blame] | 142 | #define S3C2412_UMCON_AFC_63 (0<<5) /* same as s3c2443 */ |
Ben Dooks | 73e55cb | 2006-06-24 21:21:32 +0100 | [diff] [blame] | 143 | #define S3C2412_UMCON_AFC_56 (1<<5) |
| 144 | #define S3C2412_UMCON_AFC_48 (2<<5) |
| 145 | #define S3C2412_UMCON_AFC_40 (3<<5) |
| 146 | #define S3C2412_UMCON_AFC_32 (4<<5) |
| 147 | #define S3C2412_UMCON_AFC_24 (5<<5) |
| 148 | #define S3C2412_UMCON_AFC_16 (6<<5) |
| 149 | #define S3C2412_UMCON_AFC_8 (7<<5) |
| 150 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 151 | #define S3C2410_UFSTAT_TXFULL (1<<9) |
| 152 | #define S3C2410_UFSTAT_RXFULL (1<<8) |
| 153 | #define S3C2410_UFSTAT_TXMASK (15<<4) |
| 154 | #define S3C2410_UFSTAT_TXSHIFT (4) |
| 155 | #define S3C2410_UFSTAT_RXMASK (15<<0) |
| 156 | #define S3C2410_UFSTAT_RXSHIFT (0) |
| 157 | |
Sandeep Patil | 1d4bab0 | 2008-10-21 14:06:30 +0100 | [diff] [blame] | 158 | /* UFSTAT S3C24A0 */ |
| 159 | #define S3C24A0_UFSTAT_TXFULL (1 << 14) |
| 160 | #define S3C24A0_UFSTAT_RXFULL (1 << 6) |
| 161 | #define S3C24A0_UFSTAT_TXMASK (63 << 8) |
| 162 | #define S3C24A0_UFSTAT_TXSHIFT (8) |
| 163 | #define S3C24A0_UFSTAT_RXMASK (63) |
| 164 | #define S3C24A0_UFSTAT_RXSHIFT (0) |
| 165 | |
Ben Dooks | 092651c | 2007-02-15 12:57:20 +0100 | [diff] [blame] | 166 | /* UFSTAT S3C2443 same as S3C2440 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 167 | #define S3C2440_UFSTAT_TXFULL (1<<14) |
| 168 | #define S3C2440_UFSTAT_RXFULL (1<<6) |
| 169 | #define S3C2440_UFSTAT_TXSHIFT (8) |
| 170 | #define S3C2440_UFSTAT_RXSHIFT (0) |
| 171 | #define S3C2440_UFSTAT_TXMASK (63<<8) |
| 172 | #define S3C2440_UFSTAT_RXMASK (63) |
| 173 | |
| 174 | #define S3C2410_UTRSTAT_TXE (1<<2) |
| 175 | #define S3C2410_UTRSTAT_TXFE (1<<1) |
| 176 | #define S3C2410_UTRSTAT_RXDR (1<<0) |
| 177 | |
| 178 | #define S3C2410_UERSTAT_OVERRUN (1<<0) |
| 179 | #define S3C2410_UERSTAT_FRAME (1<<2) |
| 180 | #define S3C2410_UERSTAT_BREAK (1<<3) |
Ben Dooks | 092651c | 2007-02-15 12:57:20 +0100 | [diff] [blame] | 181 | #define S3C2443_UERSTAT_PARITY (1<<1) |
| 182 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 183 | #define S3C2410_UERSTAT_ANY (S3C2410_UERSTAT_OVERRUN | \ |
| 184 | S3C2410_UERSTAT_FRAME | \ |
| 185 | S3C2410_UERSTAT_BREAK) |
| 186 | |
| 187 | #define S3C2410_UMSTAT_CTS (1<<0) |
| 188 | #define S3C2410_UMSTAT_DeltaCTS (1<<2) |
| 189 | |
Ben Dooks | 092651c | 2007-02-15 12:57:20 +0100 | [diff] [blame] | 190 | #define S3C2443_DIVSLOT (0x2C) |
| 191 | |
Ben Dooks | 966bcc1 | 2008-12-12 00:24:32 +0000 | [diff] [blame] | 192 | /* S3C64XX interrupt registers. */ |
| 193 | #define S3C64XX_UINTP 0x30 |
| 194 | #define S3C64XX_UINTSP 0x34 |
| 195 | #define S3C64XX_UINTM 0x38 |
| 196 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 197 | #ifndef __ASSEMBLY__ |
| 198 | |
| 199 | /* struct s3c24xx_uart_clksrc |
| 200 | * |
| 201 | * this structure defines a named clock source that can be used for the |
| 202 | * uart, so that the best clock can be selected for the requested baud |
| 203 | * rate. |
| 204 | * |
| 205 | * min_baud and max_baud define the range of baud-rates this clock is |
| 206 | * acceptable for, if they are both zero, it is assumed any baud rate that |
| 207 | * can be generated from this clock will be used. |
| 208 | * |
| 209 | * divisor gives the divisor from the clock to the one seen by the uart |
| 210 | */ |
| 211 | |
| 212 | struct s3c24xx_uart_clksrc { |
| 213 | const char *name; |
| 214 | unsigned int divisor; |
| 215 | unsigned int min_baud; |
| 216 | unsigned int max_baud; |
| 217 | }; |
| 218 | |
| 219 | /* configuration structure for per-machine configurations for the |
| 220 | * serial port |
| 221 | * |
| 222 | * the pointer is setup by the machine specific initialisation from the |
| 223 | * arch/arm/mach-s3c2410/ directory. |
| 224 | */ |
| 225 | |
| 226 | struct s3c2410_uartcfg { |
| 227 | unsigned char hwport; /* hardware port number */ |
| 228 | unsigned char unused; |
| 229 | unsigned short flags; |
Ben Dooks | b6d1f54 | 2006-12-17 23:22:26 +0100 | [diff] [blame] | 230 | upf_t uart_flags; /* default uart flags */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 231 | |
| 232 | unsigned long ucon; /* value of ucon for port */ |
| 233 | unsigned long ulcon; /* value of ulcon for port */ |
| 234 | unsigned long ufcon; /* value of ufcon for port */ |
| 235 | |
| 236 | struct s3c24xx_uart_clksrc *clocks; |
| 237 | unsigned int clocks_size; |
| 238 | }; |
| 239 | |
| 240 | /* s3c24xx_uart_devs |
| 241 | * |
| 242 | * this is exported from the core as we cannot use driver_register(), |
| 243 | * or platform_add_device() before the console_initcall() |
| 244 | */ |
| 245 | |
Ben Dooks | dbf3599 | 2008-11-04 15:29:09 +0000 | [diff] [blame] | 246 | extern struct platform_device *s3c24xx_uart_devs[4]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 247 | |
| 248 | #endif /* __ASSEMBLY__ */ |
| 249 | |
| 250 | #endif /* __ASM_ARM_REGS_SERIAL_H */ |
| 251 | |