blob: ab83f688263afc0df50c9820116da6fadc86cfc0 [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
Jerome Glisse3ce0a232009-09-08 10:10:24 +100028#include <linux/firmware.h>
29#include <linux/platform_device.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090030#include <linux/slab.h>
Jerome Glisse771fe6b2009-06-05 14:42:42 +020031#include "drmP.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020032#include "radeon.h"
Daniel Vettere6990372010-03-11 21:19:17 +000033#include "radeon_asic.h"
Dave Airlie4153e582009-09-18 18:41:24 +100034#include "radeon_drm.h"
Jerome Glisse3ce0a232009-09-08 10:10:24 +100035#include "rv770d.h"
Jerome Glisse3ce0a232009-09-08 10:10:24 +100036#include "atom.h"
Jerome Glissed39c3b82009-09-28 18:34:43 +020037#include "avivod.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020038
Jerome Glisse3ce0a232009-09-08 10:10:24 +100039#define R700_PFP_UCODE_SIZE 848
40#define R700_PM4_UCODE_SIZE 1360
Jerome Glisse771fe6b2009-06-05 14:42:42 +020041
Jerome Glisse3ce0a232009-09-08 10:10:24 +100042static void rv770_gpu_init(struct radeon_device *rdev);
43void rv770_fini(struct radeon_device *rdev);
44
Alex Deucher21a81222010-07-02 12:58:16 -040045/* get temperature in millidegrees */
46u32 rv770_get_temp(struct radeon_device *rdev)
47{
48 u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
49 ASIC_T_SHIFT;
50 u32 actual_temp = 0;
51
52 if ((temp >> 9) & 1)
53 actual_temp = 0;
54 else
55 actual_temp = (temp >> 1) & 0xff;
56
57 return actual_temp * 1000;
58}
59
Alex Deucher49e02b72010-04-23 17:57:27 -040060void rv770_pm_misc(struct radeon_device *rdev)
61{
Rafał Miłeckia081a9d2010-06-07 18:20:25 -040062 int req_ps_idx = rdev->pm.requested_power_state_index;
63 int req_cm_idx = rdev->pm.requested_clock_mode_index;
64 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
65 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
Alex Deucher4d601732010-06-07 18:15:18 -040066
67 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
68 if (voltage->voltage != rdev->pm.current_vddc) {
69 radeon_atom_set_voltage(rdev, voltage->voltage);
70 rdev->pm.current_vddc = voltage->voltage;
Rafał Miłecki0fcbe942010-06-07 18:25:21 -040071 DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
Alex Deucher4d601732010-06-07 18:15:18 -040072 }
73 }
Alex Deucher49e02b72010-04-23 17:57:27 -040074}
Jerome Glisse3ce0a232009-09-08 10:10:24 +100075
76/*
77 * GART
Jerome Glisse771fe6b2009-06-05 14:42:42 +020078 */
Jerome Glisse3ce0a232009-09-08 10:10:24 +100079int rv770_pcie_gart_enable(struct radeon_device *rdev)
80{
81 u32 tmp;
82 int r, i;
83
Jerome Glisse4aac0472009-09-14 18:29:49 +020084 if (rdev->gart.table.vram.robj == NULL) {
85 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
86 return -EINVAL;
Jerome Glisse3ce0a232009-09-08 10:10:24 +100087 }
Jerome Glisse4aac0472009-09-14 18:29:49 +020088 r = radeon_gart_table_vram_pin(rdev);
89 if (r)
Jerome Glisse3ce0a232009-09-08 10:10:24 +100090 return r;
Dave Airlie82568562010-02-05 16:00:07 +100091 radeon_gart_restore(rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +100092 /* Setup L2 cache */
93 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
94 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
95 EFFECTIVE_L2_QUEUE_SIZE(7));
96 WREG32(VM_L2_CNTL2, 0);
97 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
98 /* Setup TLB control */
99 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
100 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
101 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
102 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
103 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
104 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
105 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
106 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
107 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
108 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
109 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
110 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
Jerome Glisse1a029b72009-10-06 19:04:30 +0200111 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000112 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
113 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
114 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
115 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
116 (u32)(rdev->dummy_page.addr >> 12));
117 for (i = 1; i < 7; i++)
118 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
119
120 r600_pcie_gart_tlb_flush(rdev);
121 rdev->gart.ready = true;
122 return 0;
123}
124
125void rv770_pcie_gart_disable(struct radeon_device *rdev)
126{
127 u32 tmp;
Jerome Glisse4c788672009-11-20 14:29:23 +0100128 int i, r;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000129
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000130 /* Disable all tables */
131 for (i = 0; i < 7; i++)
132 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
133
134 /* Setup L2 cache */
135 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
136 EFFECTIVE_L2_QUEUE_SIZE(7));
137 WREG32(VM_L2_CNTL2, 0);
138 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
139 /* Setup TLB control */
140 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
141 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
142 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
143 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
144 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
145 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
146 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
147 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
Jerome Glisse4aac0472009-09-14 18:29:49 +0200148 if (rdev->gart.table.vram.robj) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100149 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
150 if (likely(r == 0)) {
151 radeon_bo_kunmap(rdev->gart.table.vram.robj);
152 radeon_bo_unpin(rdev->gart.table.vram.robj);
153 radeon_bo_unreserve(rdev->gart.table.vram.robj);
154 }
Jerome Glisse4aac0472009-09-14 18:29:49 +0200155 }
156}
157
158void rv770_pcie_gart_fini(struct radeon_device *rdev)
159{
Jerome Glissef9274562010-03-17 14:44:29 +0000160 radeon_gart_fini(rdev);
Jerome Glisse4aac0472009-09-14 18:29:49 +0200161 rv770_pcie_gart_disable(rdev);
162 radeon_gart_table_vram_free(rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000163}
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200164
165
Jerome Glisse1a029b72009-10-06 19:04:30 +0200166void rv770_agp_enable(struct radeon_device *rdev)
167{
168 u32 tmp;
169 int i;
170
171 /* Setup L2 cache */
172 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
173 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
174 EFFECTIVE_L2_QUEUE_SIZE(7));
175 WREG32(VM_L2_CNTL2, 0);
176 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
177 /* Setup TLB control */
178 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
179 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
180 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
181 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
182 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
183 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
184 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
185 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
186 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
187 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
188 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
189 for (i = 0; i < 7; i++)
190 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
191}
192
Jerome Glissea3c19452009-10-01 18:02:13 +0200193static void rv770_mc_program(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200194{
Jerome Glissea3c19452009-10-01 18:02:13 +0200195 struct rv515_mc_save save;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000196 u32 tmp;
197 int i, j;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200198
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000199 /* Initialize HDP */
200 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
201 WREG32((0x2c14 + j), 0x00000000);
202 WREG32((0x2c18 + j), 0x00000000);
203 WREG32((0x2c1c + j), 0x00000000);
204 WREG32((0x2c20 + j), 0x00000000);
205 WREG32((0x2c24 + j), 0x00000000);
206 }
Alex Deucher812d0462010-07-26 18:51:53 -0400207 /* r7xx hw bug. Read from HDP_DEBUG1 rather
208 * than writing to HDP_REG_COHERENCY_FLUSH_CNTL
209 */
210 tmp = RREG32(HDP_DEBUG1);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200211
Jerome Glissea3c19452009-10-01 18:02:13 +0200212 rv515_mc_stop(rdev, &save);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000213 if (r600_mc_wait_for_idle(rdev)) {
Jerome Glissea3c19452009-10-01 18:02:13 +0200214 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200215 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000216 /* Lockout access through VGA aperture*/
217 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000218 /* Update configuration */
Jerome Glisse1a029b72009-10-06 19:04:30 +0200219 if (rdev->flags & RADEON_IS_AGP) {
220 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
221 /* VRAM before AGP */
222 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
223 rdev->mc.vram_start >> 12);
224 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
225 rdev->mc.gtt_end >> 12);
226 } else {
227 /* VRAM after AGP */
228 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
229 rdev->mc.gtt_start >> 12);
230 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
231 rdev->mc.vram_end >> 12);
232 }
233 } else {
234 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
235 rdev->mc.vram_start >> 12);
236 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
237 rdev->mc.vram_end >> 12);
238 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000239 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
Jerome Glisse1a029b72009-10-06 19:04:30 +0200240 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000241 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
242 WREG32(MC_VM_FB_LOCATION, tmp);
243 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
244 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
Jerome Glisse46fcd2b2010-06-03 19:34:48 +0200245 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000246 if (rdev->flags & RADEON_IS_AGP) {
Jerome Glisse1a029b72009-10-06 19:04:30 +0200247 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000248 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
249 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
250 } else {
251 WREG32(MC_VM_AGP_BASE, 0);
252 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
253 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
254 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000255 if (r600_mc_wait_for_idle(rdev)) {
Jerome Glissea3c19452009-10-01 18:02:13 +0200256 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000257 }
Jerome Glissea3c19452009-10-01 18:02:13 +0200258 rv515_mc_resume(rdev, &save);
Dave Airlie698443d2009-09-18 14:16:38 +1000259 /* we need to own VRAM, so turn off the VGA renderer here
260 * to stop it overwriting our objects */
Jerome Glissed39c3b82009-09-28 18:34:43 +0200261 rv515_vga_render_disable(rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200262}
263
264
265/*
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000266 * CP.
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200267 */
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000268void r700_cp_stop(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200269{
Jerome Glissec919b372010-08-10 17:41:31 -0400270 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000271 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
Alex Deucher724c80e2010-08-27 18:25:25 -0400272 WREG32(SCRATCH_UMSK, 0);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200273}
274
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000275static int rv770_cp_load_microcode(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200276{
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000277 const __be32 *fw_data;
278 int i;
279
280 if (!rdev->me_fw || !rdev->pfp_fw)
281 return -EINVAL;
282
283 r700_cp_stop(rdev);
284 WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
285
286 /* Reset cp */
287 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
288 RREG32(GRBM_SOFT_RESET);
289 mdelay(15);
290 WREG32(GRBM_SOFT_RESET, 0);
291
292 fw_data = (const __be32 *)rdev->pfp_fw->data;
293 WREG32(CP_PFP_UCODE_ADDR, 0);
294 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
295 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
296 WREG32(CP_PFP_UCODE_ADDR, 0);
297
298 fw_data = (const __be32 *)rdev->me_fw->data;
299 WREG32(CP_ME_RAM_WADDR, 0);
300 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
301 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
302
303 WREG32(CP_PFP_UCODE_ADDR, 0);
304 WREG32(CP_ME_RAM_WADDR, 0);
305 WREG32(CP_ME_RAM_RADDR, 0);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200306 return 0;
307}
308
Alex Deucherfe251e22010-03-24 13:36:43 -0400309void r700_cp_fini(struct radeon_device *rdev)
310{
311 r700_cp_stop(rdev);
312 radeon_ring_fini(rdev);
313}
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200314
315/*
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000316 * Core functions
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200317 */
Alex Deucherd03f5d52010-02-19 16:22:31 -0500318static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
319 u32 num_tile_pipes,
320 u32 num_backends,
321 u32 backend_disable_mask)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200322{
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000323 u32 backend_map = 0;
324 u32 enabled_backends_mask;
325 u32 enabled_backends_count;
326 u32 cur_pipe;
327 u32 swizzle_pipe[R7XX_MAX_PIPES];
328 u32 cur_backend;
329 u32 i;
Alex Deucherd03f5d52010-02-19 16:22:31 -0500330 bool force_no_swizzle;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000331
332 if (num_tile_pipes > R7XX_MAX_PIPES)
333 num_tile_pipes = R7XX_MAX_PIPES;
334 if (num_tile_pipes < 1)
335 num_tile_pipes = 1;
336 if (num_backends > R7XX_MAX_BACKENDS)
337 num_backends = R7XX_MAX_BACKENDS;
338 if (num_backends < 1)
339 num_backends = 1;
340
341 enabled_backends_mask = 0;
342 enabled_backends_count = 0;
343 for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
344 if (((backend_disable_mask >> i) & 1) == 0) {
345 enabled_backends_mask |= (1 << i);
346 ++enabled_backends_count;
347 }
348 if (enabled_backends_count == num_backends)
349 break;
350 }
351
352 if (enabled_backends_count == 0) {
353 enabled_backends_mask = 1;
354 enabled_backends_count = 1;
355 }
356
357 if (enabled_backends_count != num_backends)
358 num_backends = enabled_backends_count;
359
Alex Deucherd03f5d52010-02-19 16:22:31 -0500360 switch (rdev->family) {
361 case CHIP_RV770:
362 case CHIP_RV730:
363 force_no_swizzle = false;
364 break;
365 case CHIP_RV710:
366 case CHIP_RV740:
367 default:
368 force_no_swizzle = true;
369 break;
370 }
371
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000372 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
373 switch (num_tile_pipes) {
374 case 1:
375 swizzle_pipe[0] = 0;
376 break;
377 case 2:
378 swizzle_pipe[0] = 0;
379 swizzle_pipe[1] = 1;
380 break;
381 case 3:
Alex Deucherd03f5d52010-02-19 16:22:31 -0500382 if (force_no_swizzle) {
383 swizzle_pipe[0] = 0;
384 swizzle_pipe[1] = 1;
385 swizzle_pipe[2] = 2;
386 } else {
387 swizzle_pipe[0] = 0;
388 swizzle_pipe[1] = 2;
389 swizzle_pipe[2] = 1;
390 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000391 break;
392 case 4:
Alex Deucherd03f5d52010-02-19 16:22:31 -0500393 if (force_no_swizzle) {
394 swizzle_pipe[0] = 0;
395 swizzle_pipe[1] = 1;
396 swizzle_pipe[2] = 2;
397 swizzle_pipe[3] = 3;
398 } else {
399 swizzle_pipe[0] = 0;
400 swizzle_pipe[1] = 2;
401 swizzle_pipe[2] = 3;
402 swizzle_pipe[3] = 1;
403 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000404 break;
405 case 5:
Alex Deucherd03f5d52010-02-19 16:22:31 -0500406 if (force_no_swizzle) {
407 swizzle_pipe[0] = 0;
408 swizzle_pipe[1] = 1;
409 swizzle_pipe[2] = 2;
410 swizzle_pipe[3] = 3;
411 swizzle_pipe[4] = 4;
412 } else {
413 swizzle_pipe[0] = 0;
414 swizzle_pipe[1] = 2;
415 swizzle_pipe[2] = 4;
416 swizzle_pipe[3] = 1;
417 swizzle_pipe[4] = 3;
418 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000419 break;
420 case 6:
Alex Deucherd03f5d52010-02-19 16:22:31 -0500421 if (force_no_swizzle) {
422 swizzle_pipe[0] = 0;
423 swizzle_pipe[1] = 1;
424 swizzle_pipe[2] = 2;
425 swizzle_pipe[3] = 3;
426 swizzle_pipe[4] = 4;
427 swizzle_pipe[5] = 5;
428 } else {
429 swizzle_pipe[0] = 0;
430 swizzle_pipe[1] = 2;
431 swizzle_pipe[2] = 4;
432 swizzle_pipe[3] = 5;
433 swizzle_pipe[4] = 3;
434 swizzle_pipe[5] = 1;
435 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000436 break;
437 case 7:
Alex Deucherd03f5d52010-02-19 16:22:31 -0500438 if (force_no_swizzle) {
439 swizzle_pipe[0] = 0;
440 swizzle_pipe[1] = 1;
441 swizzle_pipe[2] = 2;
442 swizzle_pipe[3] = 3;
443 swizzle_pipe[4] = 4;
444 swizzle_pipe[5] = 5;
445 swizzle_pipe[6] = 6;
446 } else {
447 swizzle_pipe[0] = 0;
448 swizzle_pipe[1] = 2;
449 swizzle_pipe[2] = 4;
450 swizzle_pipe[3] = 6;
451 swizzle_pipe[4] = 3;
452 swizzle_pipe[5] = 1;
453 swizzle_pipe[6] = 5;
454 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000455 break;
456 case 8:
Alex Deucherd03f5d52010-02-19 16:22:31 -0500457 if (force_no_swizzle) {
458 swizzle_pipe[0] = 0;
459 swizzle_pipe[1] = 1;
460 swizzle_pipe[2] = 2;
461 swizzle_pipe[3] = 3;
462 swizzle_pipe[4] = 4;
463 swizzle_pipe[5] = 5;
464 swizzle_pipe[6] = 6;
465 swizzle_pipe[7] = 7;
466 } else {
467 swizzle_pipe[0] = 0;
468 swizzle_pipe[1] = 2;
469 swizzle_pipe[2] = 4;
470 swizzle_pipe[3] = 6;
471 swizzle_pipe[4] = 3;
472 swizzle_pipe[5] = 1;
473 swizzle_pipe[6] = 7;
474 swizzle_pipe[7] = 5;
475 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000476 break;
477 }
478
479 cur_backend = 0;
480 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
481 while (((1 << cur_backend) & enabled_backends_mask) == 0)
482 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
483
484 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
485
486 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
487 }
488
489 return backend_map;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200490}
491
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000492static void rv770_gpu_init(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200493{
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000494 int i, j, num_qd_pipes;
Alex Deucherd03f5d52010-02-19 16:22:31 -0500495 u32 ta_aux_cntl;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000496 u32 sx_debug_1;
497 u32 smx_dc_ctl0;
Alex Deucherd03f5d52010-02-19 16:22:31 -0500498 u32 db_debug3;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000499 u32 num_gs_verts_per_thread;
500 u32 vgt_gs_per_es;
501 u32 gs_prim_buffer_depth = 0;
502 u32 sq_ms_fifo_sizes;
503 u32 sq_config;
504 u32 sq_thread_resource_mgmt;
505 u32 hdp_host_path_cntl;
506 u32 sq_dyn_gpr_size_simd_ab_0;
507 u32 backend_map;
508 u32 gb_tiling_config = 0;
509 u32 cc_rb_backend_disable = 0;
510 u32 cc_gc_shader_pipe_config = 0;
511 u32 mc_arb_ramcfg;
512 u32 db_debug4;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200513
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000514 /* setup chip specs */
515 switch (rdev->family) {
516 case CHIP_RV770:
517 rdev->config.rv770.max_pipes = 4;
518 rdev->config.rv770.max_tile_pipes = 8;
519 rdev->config.rv770.max_simds = 10;
520 rdev->config.rv770.max_backends = 4;
521 rdev->config.rv770.max_gprs = 256;
522 rdev->config.rv770.max_threads = 248;
523 rdev->config.rv770.max_stack_entries = 512;
524 rdev->config.rv770.max_hw_contexts = 8;
525 rdev->config.rv770.max_gs_threads = 16 * 2;
526 rdev->config.rv770.sx_max_export_size = 128;
527 rdev->config.rv770.sx_max_export_pos_size = 16;
528 rdev->config.rv770.sx_max_export_smx_size = 112;
529 rdev->config.rv770.sq_num_cf_insts = 2;
530
531 rdev->config.rv770.sx_num_of_sets = 7;
532 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
533 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
534 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
535 break;
536 case CHIP_RV730:
537 rdev->config.rv770.max_pipes = 2;
538 rdev->config.rv770.max_tile_pipes = 4;
539 rdev->config.rv770.max_simds = 8;
540 rdev->config.rv770.max_backends = 2;
541 rdev->config.rv770.max_gprs = 128;
542 rdev->config.rv770.max_threads = 248;
543 rdev->config.rv770.max_stack_entries = 256;
544 rdev->config.rv770.max_hw_contexts = 8;
545 rdev->config.rv770.max_gs_threads = 16 * 2;
546 rdev->config.rv770.sx_max_export_size = 256;
547 rdev->config.rv770.sx_max_export_pos_size = 32;
548 rdev->config.rv770.sx_max_export_smx_size = 224;
549 rdev->config.rv770.sq_num_cf_insts = 2;
550
551 rdev->config.rv770.sx_num_of_sets = 7;
552 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
553 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
554 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
555 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
556 rdev->config.rv770.sx_max_export_pos_size -= 16;
557 rdev->config.rv770.sx_max_export_smx_size += 16;
558 }
559 break;
560 case CHIP_RV710:
561 rdev->config.rv770.max_pipes = 2;
562 rdev->config.rv770.max_tile_pipes = 2;
563 rdev->config.rv770.max_simds = 2;
564 rdev->config.rv770.max_backends = 1;
565 rdev->config.rv770.max_gprs = 256;
566 rdev->config.rv770.max_threads = 192;
567 rdev->config.rv770.max_stack_entries = 256;
568 rdev->config.rv770.max_hw_contexts = 4;
569 rdev->config.rv770.max_gs_threads = 8 * 2;
570 rdev->config.rv770.sx_max_export_size = 128;
571 rdev->config.rv770.sx_max_export_pos_size = 16;
572 rdev->config.rv770.sx_max_export_smx_size = 112;
573 rdev->config.rv770.sq_num_cf_insts = 1;
574
575 rdev->config.rv770.sx_num_of_sets = 7;
576 rdev->config.rv770.sc_prim_fifo_size = 0x40;
577 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
578 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
579 break;
580 case CHIP_RV740:
581 rdev->config.rv770.max_pipes = 4;
582 rdev->config.rv770.max_tile_pipes = 4;
583 rdev->config.rv770.max_simds = 8;
584 rdev->config.rv770.max_backends = 4;
585 rdev->config.rv770.max_gprs = 256;
586 rdev->config.rv770.max_threads = 248;
587 rdev->config.rv770.max_stack_entries = 512;
588 rdev->config.rv770.max_hw_contexts = 8;
589 rdev->config.rv770.max_gs_threads = 16 * 2;
590 rdev->config.rv770.sx_max_export_size = 256;
591 rdev->config.rv770.sx_max_export_pos_size = 32;
592 rdev->config.rv770.sx_max_export_smx_size = 224;
593 rdev->config.rv770.sq_num_cf_insts = 2;
594
595 rdev->config.rv770.sx_num_of_sets = 7;
596 rdev->config.rv770.sc_prim_fifo_size = 0x100;
597 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
598 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
599
600 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
601 rdev->config.rv770.sx_max_export_pos_size -= 16;
602 rdev->config.rv770.sx_max_export_smx_size += 16;
603 }
604 break;
605 default:
606 break;
607 }
608
609 /* Initialize HDP */
610 j = 0;
611 for (i = 0; i < 32; i++) {
612 WREG32((0x2c14 + j), 0x00000000);
613 WREG32((0x2c18 + j), 0x00000000);
614 WREG32((0x2c1c + j), 0x00000000);
615 WREG32((0x2c20 + j), 0x00000000);
616 WREG32((0x2c24 + j), 0x00000000);
617 j += 0x18;
618 }
619
620 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
621
622 /* setup tiling, simd, pipe config */
623 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
624
625 switch (rdev->config.rv770.max_tile_pipes) {
626 case 1:
Alex Deucherd03f5d52010-02-19 16:22:31 -0500627 default:
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000628 gb_tiling_config |= PIPE_TILING(0);
629 break;
630 case 2:
631 gb_tiling_config |= PIPE_TILING(1);
632 break;
633 case 4:
634 gb_tiling_config |= PIPE_TILING(2);
635 break;
636 case 8:
637 gb_tiling_config |= PIPE_TILING(3);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000638 break;
639 }
Alex Deucherd03f5d52010-02-19 16:22:31 -0500640 rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000641
642 if (rdev->family == CHIP_RV770)
643 gb_tiling_config |= BANK_TILING(1);
644 else
Alex Deuchere29649d2009-11-03 10:04:01 -0500645 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
Jerome Glisse961fb592010-02-10 22:30:05 +0000646 rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000647
648 gb_tiling_config |= GROUP_SIZE(0);
Jerome Glisse961fb592010-02-10 22:30:05 +0000649 rdev->config.rv770.tiling_group_size = 256;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000650
Alex Deuchere29649d2009-11-03 10:04:01 -0500651 if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000652 gb_tiling_config |= ROW_TILING(3);
653 gb_tiling_config |= SAMPLE_SPLIT(3);
654 } else {
655 gb_tiling_config |=
656 ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
657 gb_tiling_config |=
658 SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
659 }
660
661 gb_tiling_config |= BANK_SWAPS(1);
662
Alex Deucherd03f5d52010-02-19 16:22:31 -0500663 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
664 cc_rb_backend_disable |=
665 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000666
Alex Deucherd03f5d52010-02-19 16:22:31 -0500667 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
668 cc_gc_shader_pipe_config |=
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000669 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
670 cc_gc_shader_pipe_config |=
671 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
672
Alex Deucherd03f5d52010-02-19 16:22:31 -0500673 if (rdev->family == CHIP_RV740)
674 backend_map = 0x28;
675 else
676 backend_map = r700_get_tile_pipe_to_backend_map(rdev,
677 rdev->config.rv770.max_tile_pipes,
678 (R7XX_MAX_BACKENDS -
679 r600_count_pipe_bits((cc_rb_backend_disable &
680 R7XX_MAX_BACKENDS_MASK) >> 16)),
681 (cc_rb_backend_disable >> 16));
Alex Deucherd03f5d52010-02-19 16:22:31 -0500682
Alex Deuchere7aeeba2010-06-04 13:10:12 -0400683 rdev->config.rv770.tile_config = gb_tiling_config;
684 gb_tiling_config |= BACKEND_MAP(backend_map);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000685
686 WREG32(GB_TILING_CONFIG, gb_tiling_config);
687 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
688 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
689
690 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
691 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
Alex Deucherf867c60d2010-03-05 14:50:37 -0500692 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
Alex Deucherd03f5d52010-02-19 16:22:31 -0500693 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000694
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000695 WREG32(CGTS_SYS_TCC_DISABLE, 0);
696 WREG32(CGTS_TCC_DISABLE, 0);
Alex Deucherf867c60d2010-03-05 14:50:37 -0500697 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
698 WREG32(CGTS_USER_TCC_DISABLE, 0);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000699
700 num_qd_pipes =
Alex Deucherd03f5d52010-02-19 16:22:31 -0500701 R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000702 WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
703 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
704
705 /* set HW defaults for 3D engine */
706 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
Alex Deuchere29649d2009-11-03 10:04:01 -0500707 ROQ_IB2_START(0x2b)));
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000708
709 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
710
Alex Deucherd03f5d52010-02-19 16:22:31 -0500711 ta_aux_cntl = RREG32(TA_CNTL_AUX);
712 WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000713
714 sx_debug_1 = RREG32(SX_DEBUG_1);
715 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
716 WREG32(SX_DEBUG_1, sx_debug_1);
717
718 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
719 smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
720 smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
721 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
722
Alex Deucherd03f5d52010-02-19 16:22:31 -0500723 if (rdev->family != CHIP_RV740)
724 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
725 GS_FLUSH_CTL(4) |
726 ACK_FLUSH_CTL(3) |
727 SYNC_FLUSH_CTL));
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000728
Alex Deucherd03f5d52010-02-19 16:22:31 -0500729 db_debug3 = RREG32(DB_DEBUG3);
730 db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
731 switch (rdev->family) {
732 case CHIP_RV770:
733 case CHIP_RV740:
734 db_debug3 |= DB_CLK_OFF_DELAY(0x1f);
735 break;
736 case CHIP_RV710:
737 case CHIP_RV730:
738 default:
739 db_debug3 |= DB_CLK_OFF_DELAY(2);
740 break;
741 }
742 WREG32(DB_DEBUG3, db_debug3);
743
744 if (rdev->family != CHIP_RV770) {
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000745 db_debug4 = RREG32(DB_DEBUG4);
746 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
747 WREG32(DB_DEBUG4, db_debug4);
748 }
749
750 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
Alex Deuchere29649d2009-11-03 10:04:01 -0500751 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
752 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000753
754 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
Alex Deuchere29649d2009-11-03 10:04:01 -0500755 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
756 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000757
758 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
759
760 WREG32(VGT_NUM_INSTANCES, 1);
761
762 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
763
764 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
765
766 WREG32(CP_PERFMON_CNTL, 0);
767
768 sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
769 DONE_FIFO_HIWATER(0xe0) |
770 ALU_UPDATE_FIFO_HIWATER(0x8));
771 switch (rdev->family) {
772 case CHIP_RV770:
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000773 case CHIP_RV730:
774 case CHIP_RV710:
Alex Deucherd03f5d52010-02-19 16:22:31 -0500775 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
776 break;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000777 case CHIP_RV740:
778 default:
779 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
780 break;
781 }
782 WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
783
784 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
785 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
786 */
787 sq_config = RREG32(SQ_CONFIG);
788 sq_config &= ~(PS_PRIO(3) |
789 VS_PRIO(3) |
790 GS_PRIO(3) |
791 ES_PRIO(3));
792 sq_config |= (DX9_CONSTS |
793 VC_ENABLE |
794 EXPORT_SRC_C |
795 PS_PRIO(0) |
796 VS_PRIO(1) |
797 GS_PRIO(2) |
798 ES_PRIO(3));
799 if (rdev->family == CHIP_RV710)
800 /* no vertex cache */
801 sq_config &= ~VC_ENABLE;
802
803 WREG32(SQ_CONFIG, sq_config);
804
805 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
Dave Airliefe62e1a2009-09-21 14:06:30 +1000806 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
807 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000808
809 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
Dave Airliefe62e1a2009-09-21 14:06:30 +1000810 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000811
812 sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
813 NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
814 NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
815 if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
816 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
817 else
818 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
819 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
820
821 WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
822 NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
823
824 WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
825 NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
826
827 sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
828 SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
829 SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
830 SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
831
832 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
833 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
834 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
835 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
836 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
837 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
838 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
839 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
840
841 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
Dave Airliefe62e1a2009-09-21 14:06:30 +1000842 FORCE_EOV_MAX_REZ_CNT(255)));
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000843
844 if (rdev->family == CHIP_RV710)
845 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
Dave Airliefe62e1a2009-09-21 14:06:30 +1000846 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000847 else
848 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
Dave Airliefe62e1a2009-09-21 14:06:30 +1000849 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000850
851 switch (rdev->family) {
852 case CHIP_RV770:
853 case CHIP_RV730:
854 case CHIP_RV740:
855 gs_prim_buffer_depth = 384;
856 break;
857 case CHIP_RV710:
858 gs_prim_buffer_depth = 128;
859 break;
860 default:
861 break;
862 }
863
864 num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
865 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
866 /* Max value for this is 256 */
867 if (vgt_gs_per_es > 256)
868 vgt_gs_per_es = 256;
869
870 WREG32(VGT_ES_PER_GS, 128);
871 WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
872 WREG32(VGT_GS_PER_VS, 2);
873
874 /* more default values. 2D/3D driver should adjust as needed */
875 WREG32(VGT_GS_VERTEX_REUSE, 16);
876 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
877 WREG32(VGT_STRMOUT_EN, 0);
878 WREG32(SX_MISC, 0);
879 WREG32(PA_SC_MODE_CNTL, 0);
880 WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
881 WREG32(PA_SC_AA_CONFIG, 0);
882 WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
883 WREG32(PA_SC_LINE_STIPPLE, 0);
884 WREG32(SPI_INPUT_Z, 0);
885 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
886 WREG32(CB_COLOR7_FRAG, 0);
887
888 /* clear render buffer base addresses */
889 WREG32(CB_COLOR0_BASE, 0);
890 WREG32(CB_COLOR1_BASE, 0);
891 WREG32(CB_COLOR2_BASE, 0);
892 WREG32(CB_COLOR3_BASE, 0);
893 WREG32(CB_COLOR4_BASE, 0);
894 WREG32(CB_COLOR5_BASE, 0);
895 WREG32(CB_COLOR6_BASE, 0);
896 WREG32(CB_COLOR7_BASE, 0);
897
898 WREG32(TCP_CNTL, 0);
899
900 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
901 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
902
903 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
904
905 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
906 NUM_CLIP_SEQ(3)));
907
908}
909
Alex Deucher87cbf8f2010-08-27 13:59:54 -0400910static int rv770_vram_scratch_init(struct radeon_device *rdev)
911{
912 int r;
913 u64 gpu_addr;
914
915 if (rdev->vram_scratch.robj == NULL) {
916 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE,
917 true, RADEON_GEM_DOMAIN_VRAM,
918 &rdev->vram_scratch.robj);
919 if (r) {
920 return r;
921 }
922 }
923
924 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
925 if (unlikely(r != 0))
926 return r;
927 r = radeon_bo_pin(rdev->vram_scratch.robj,
928 RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
929 if (r) {
930 radeon_bo_unreserve(rdev->vram_scratch.robj);
931 return r;
932 }
933 r = radeon_bo_kmap(rdev->vram_scratch.robj,
934 (void **)&rdev->vram_scratch.ptr);
935 if (r)
936 radeon_bo_unpin(rdev->vram_scratch.robj);
937 radeon_bo_unreserve(rdev->vram_scratch.robj);
938
939 return r;
940}
941
942static void rv770_vram_scratch_fini(struct radeon_device *rdev)
943{
944 int r;
945
946 if (rdev->vram_scratch.robj == NULL) {
947 return;
948 }
949 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
950 if (likely(r == 0)) {
951 radeon_bo_kunmap(rdev->vram_scratch.robj);
952 radeon_bo_unpin(rdev->vram_scratch.robj);
953 radeon_bo_unreserve(rdev->vram_scratch.robj);
954 }
955 radeon_bo_unref(&rdev->vram_scratch.robj);
956}
957
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000958int rv770_mc_init(struct radeon_device *rdev)
959{
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000960 u32 tmp;
Alex Deucher5885b7a2009-10-19 17:23:33 -0400961 int chansize, numchan;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000962
963 /* Get VRAM informations */
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000964 rdev->mc.vram_is_ddr = true;
Alex Deucher5885b7a2009-10-19 17:23:33 -0400965 tmp = RREG32(MC_ARB_RAMCFG);
966 if (tmp & CHANSIZE_OVERRIDE) {
967 chansize = 16;
968 } else if (tmp & CHANSIZE_MASK) {
969 chansize = 64;
970 } else {
971 chansize = 32;
972 }
973 tmp = RREG32(MC_SHARED_CHMAP);
974 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
975 case 0:
976 default:
977 numchan = 1;
978 break;
979 case 1:
980 numchan = 2;
981 break;
982 case 2:
983 numchan = 4;
984 break;
985 case 3:
986 numchan = 8;
987 break;
988 }
989 rdev->mc.vram_width = numchan * chansize;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200990 /* Could aper size report 0 ? */
Jordan Crouse01d73a62010-05-27 13:40:24 -0600991 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
992 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000993 /* Setup GPU memory space */
994 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
995 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
Jerome Glisse51e5fcd2010-02-19 14:33:54 +0000996 rdev->mc.visible_vram_size = rdev->mc.aper_size;
Jerome Glissec919b372010-08-10 17:41:31 -0400997 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
Jerome Glissed594e462010-02-17 21:54:29 +0000998 r600_vram_gtt_location(rdev, &rdev->mc);
Alex Deucherf47299c2010-03-16 20:54:38 -0400999 radeon_update_bandwidth_info(rdev);
1000
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001001 return 0;
1002}
Jerome Glissed594e462010-02-17 21:54:29 +00001003
Dave Airliefc30b8e2009-09-18 15:19:37 +10001004static int rv770_startup(struct radeon_device *rdev)
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001005{
1006 int r;
1007
Alex Deucher779720a2009-12-09 19:31:44 -05001008 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1009 r = r600_init_microcode(rdev);
1010 if (r) {
1011 DRM_ERROR("Failed to load firmware!\n");
1012 return r;
1013 }
1014 }
1015
Jerome Glissea3c19452009-10-01 18:02:13 +02001016 rv770_mc_program(rdev);
Jerome Glisse1a029b72009-10-06 19:04:30 +02001017 if (rdev->flags & RADEON_IS_AGP) {
1018 rv770_agp_enable(rdev);
1019 } else {
1020 r = rv770_pcie_gart_enable(rdev);
1021 if (r)
1022 return r;
1023 }
Alex Deucher87cbf8f2010-08-27 13:59:54 -04001024 r = rv770_vram_scratch_init(rdev);
1025 if (r)
1026 return r;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001027 rv770_gpu_init(rdev);
Jerome Glissec38c7b62010-02-04 17:27:27 +01001028 r = r600_blit_init(rdev);
1029 if (r) {
1030 r600_blit_fini(rdev);
1031 rdev->asic->copy = NULL;
1032 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1033 }
Alex Deucherb70d6bb2010-08-06 21:36:58 -04001034
Alex Deucher724c80e2010-08-27 18:25:25 -04001035 /* allocate wb buffer */
1036 r = radeon_wb_init(rdev);
1037 if (r)
1038 return r;
1039
Alex Deucherd8f60cf2009-12-01 13:43:46 -05001040 /* Enable IRQ */
Alex Deucherd8f60cf2009-12-01 13:43:46 -05001041 r = r600_irq_init(rdev);
1042 if (r) {
1043 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1044 radeon_irq_kms_fini(rdev);
1045 return r;
1046 }
1047 r600_irq_set(rdev);
1048
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001049 r = radeon_ring_init(rdev, rdev->cp.ring_size);
1050 if (r)
1051 return r;
1052 r = rv770_cp_load_microcode(rdev);
1053 if (r)
1054 return r;
1055 r = r600_cp_resume(rdev);
1056 if (r)
1057 return r;
Alex Deucher724c80e2010-08-27 18:25:25 -04001058
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001059 return 0;
1060}
1061
Dave Airliefc30b8e2009-09-18 15:19:37 +10001062int rv770_resume(struct radeon_device *rdev)
1063{
1064 int r;
1065
Jerome Glisse1a029b72009-10-06 19:04:30 +02001066 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1067 * posting will perform necessary task to bring back GPU into good
1068 * shape.
1069 */
Dave Airliefc30b8e2009-09-18 15:19:37 +10001070 /* post card */
Jerome Glissee7d40b92009-10-01 18:02:15 +02001071 atom_asic_init(rdev->mode_info.atom_context);
Dave Airliefc30b8e2009-09-18 15:19:37 +10001072
1073 r = rv770_startup(rdev);
1074 if (r) {
1075 DRM_ERROR("r600 startup failed on resume\n");
1076 return r;
1077 }
1078
Jerome Glisse62a8ea32009-10-01 18:02:11 +02001079 r = r600_ib_test(rdev);
Dave Airliefc30b8e2009-09-18 15:19:37 +10001080 if (r) {
1081 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1082 return r;
1083 }
Rafał Miłecki8a8c6e72010-03-06 13:03:36 +00001084
1085 r = r600_audio_init(rdev);
1086 if (r) {
1087 dev_err(rdev->dev, "radeon: audio init failed\n");
1088 return r;
1089 }
1090
Dave Airliefc30b8e2009-09-18 15:19:37 +10001091 return r;
1092
1093}
1094
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001095int rv770_suspend(struct radeon_device *rdev)
1096{
Jerome Glisse4c788672009-11-20 14:29:23 +01001097 int r;
1098
Rafał Miłecki8a8c6e72010-03-06 13:03:36 +00001099 r600_audio_fini(rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001100 /* FIXME: we should wait for ring to be empty */
1101 r700_cp_stop(rdev);
Dave Airlie4153e582009-09-18 18:41:24 +10001102 rdev->cp.ready = false;
Jerome Glisse0c452492010-01-15 14:44:37 +01001103 r600_irq_suspend(rdev);
Alex Deucher724c80e2010-08-27 18:25:25 -04001104 radeon_wb_disable(rdev);
Jerome Glisse4aac0472009-09-14 18:29:49 +02001105 rv770_pcie_gart_disable(rdev);
Dave Airlie4153e582009-09-18 18:41:24 +10001106 /* unpin shaders bo */
Jerome Glisse30d2d9a2010-01-13 10:29:27 +01001107 if (rdev->r600_blit.shader_obj) {
1108 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1109 if (likely(r == 0)) {
1110 radeon_bo_unpin(rdev->r600_blit.shader_obj);
1111 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1112 }
Jerome Glisse4c788672009-11-20 14:29:23 +01001113 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001114 return 0;
1115}
1116
1117/* Plan is to move initialization in that function and use
1118 * helper function so that radeon_device_init pretty much
1119 * do nothing more than calling asic specific function. This
1120 * should also allow to remove a bunch of callback function
1121 * like vram_info.
1122 */
1123int rv770_init(struct radeon_device *rdev)
1124{
1125 int r;
1126
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001127 r = radeon_dummy_page_init(rdev);
1128 if (r)
1129 return r;
1130 /* This don't do much */
1131 r = radeon_gem_init(rdev);
1132 if (r)
1133 return r;
1134 /* Read BIOS */
1135 if (!radeon_get_bios(rdev)) {
1136 if (ASIC_IS_AVIVO(rdev))
1137 return -EINVAL;
1138 }
1139 /* Must be an ATOMBIOS */
Jerome Glissee7d40b92009-10-01 18:02:15 +02001140 if (!rdev->is_atom_bios) {
1141 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001142 return -EINVAL;
Jerome Glissee7d40b92009-10-01 18:02:15 +02001143 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001144 r = radeon_atombios_init(rdev);
1145 if (r)
1146 return r;
1147 /* Post card if necessary */
Dave Airlie72542d72009-12-01 14:06:31 +10001148 if (!r600_card_posted(rdev)) {
1149 if (!rdev->bios) {
1150 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1151 return -EINVAL;
1152 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001153 DRM_INFO("GPU not posted. posting now...\n");
1154 atom_asic_init(rdev->mode_info.atom_context);
1155 }
1156 /* Initialize scratch registers */
1157 r600_scratch_init(rdev);
1158 /* Initialize surface registers */
1159 radeon_surface_init(rdev);
Rafał Miłecki74338742009-11-03 00:53:02 +01001160 /* Initialize clocks */
Michel Dänzer5e6dde72009-09-17 09:42:28 +02001161 radeon_get_clock_info(rdev->ddev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001162 /* Fence driver */
1163 r = radeon_fence_driver_init(rdev);
1164 if (r)
1165 return r;
Jerome Glissed594e462010-02-17 21:54:29 +00001166 /* initialize AGP */
Jerome Glisse700a0cc2010-01-13 15:16:38 +01001167 if (rdev->flags & RADEON_IS_AGP) {
1168 r = radeon_agp_init(rdev);
1169 if (r)
1170 radeon_agp_disable(rdev);
1171 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001172 r = rv770_mc_init(rdev);
Jerome Glisseb574f252009-10-06 19:04:29 +02001173 if (r)
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001174 return r;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001175 /* Memory manager */
Jerome Glisse4c788672009-11-20 14:29:23 +01001176 r = radeon_bo_init(rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001177 if (r)
1178 return r;
Alex Deucherd8f60cf2009-12-01 13:43:46 -05001179
1180 r = radeon_irq_kms_init(rdev);
1181 if (r)
1182 return r;
1183
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001184 rdev->cp.ring_obj = NULL;
1185 r600_ring_init(rdev, 1024 * 1024);
1186
Alex Deucherd8f60cf2009-12-01 13:43:46 -05001187 rdev->ih.ring_obj = NULL;
1188 r600_ih_ring_init(rdev, 64 * 1024);
1189
Jerome Glisse4aac0472009-09-14 18:29:49 +02001190 r = r600_pcie_gart_init(rdev);
1191 if (r)
1192 return r;
1193
Alex Deucher779720a2009-12-09 19:31:44 -05001194 rdev->accel_working = true;
Dave Airliefc30b8e2009-09-18 15:19:37 +10001195 r = rv770_startup(rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001196 if (r) {
Jerome Glisse655efd32010-02-02 11:51:45 +01001197 dev_err(rdev->dev, "disabling GPU acceleration\n");
Alex Deucherfe251e22010-03-24 13:36:43 -04001198 r700_cp_fini(rdev);
Jerome Glisse655efd32010-02-02 11:51:45 +01001199 r600_irq_fini(rdev);
Alex Deucher724c80e2010-08-27 18:25:25 -04001200 radeon_wb_fini(rdev);
Jerome Glisse655efd32010-02-02 11:51:45 +01001201 radeon_irq_kms_fini(rdev);
Jerome Glisse75c81292009-10-01 18:02:14 +02001202 rv770_pcie_gart_fini(rdev);
Jerome Glisse733289c2009-09-16 15:24:21 +02001203 rdev->accel_working = false;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001204 }
Jerome Glisse733289c2009-09-16 15:24:21 +02001205 if (rdev->accel_working) {
Jerome Glisse733289c2009-09-16 15:24:21 +02001206 r = radeon_ib_pool_init(rdev);
1207 if (r) {
Jerome Glissedb963802010-01-17 21:21:56 +01001208 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
Jerome Glisse733289c2009-09-16 15:24:21 +02001209 rdev->accel_working = false;
Jerome Glissedb963802010-01-17 21:21:56 +01001210 } else {
1211 r = r600_ib_test(rdev);
1212 if (r) {
1213 dev_err(rdev->dev, "IB test failed (%d).\n", r);
1214 rdev->accel_working = false;
1215 }
Jerome Glisse733289c2009-09-16 15:24:21 +02001216 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001217 }
Rafał Miłecki8a8c6e72010-03-06 13:03:36 +00001218
1219 r = r600_audio_init(rdev);
1220 if (r) {
1221 dev_err(rdev->dev, "radeon: audio init failed\n");
1222 return r;
1223 }
1224
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001225 return 0;
1226}
1227
1228void rv770_fini(struct radeon_device *rdev)
1229{
1230 r600_blit_fini(rdev);
Alex Deucherfe251e22010-03-24 13:36:43 -04001231 r700_cp_fini(rdev);
Alex Deucherd8f60cf2009-12-01 13:43:46 -05001232 r600_irq_fini(rdev);
Alex Deucher724c80e2010-08-27 18:25:25 -04001233 radeon_wb_fini(rdev);
Alex Deucherd8f60cf2009-12-01 13:43:46 -05001234 radeon_irq_kms_fini(rdev);
Jerome Glisse4aac0472009-09-14 18:29:49 +02001235 rv770_pcie_gart_fini(rdev);
Alex Deucher87cbf8f2010-08-27 13:59:54 -04001236 rv770_vram_scratch_fini(rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001237 radeon_gem_fini(rdev);
1238 radeon_fence_driver_fini(rdev);
Jerome Glissed0269ed2010-01-07 16:08:32 +01001239 radeon_agp_fini(rdev);
Jerome Glisse4c788672009-11-20 14:29:23 +01001240 radeon_bo_fini(rdev);
Jerome Glissee7d40b92009-10-01 18:02:15 +02001241 radeon_atombios_fini(rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001242 kfree(rdev->bios);
1243 rdev->bios = NULL;
1244 radeon_dummy_page_fini(rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001245}