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Andrew Vasquezfa90c542005-10-27 11:10:08 -07001/*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2005 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07007#ifndef __QLA_DEF_H
8#define __QLA_DEF_H
9
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/types.h>
13#include <linux/module.h>
14#include <linux/list.h>
15#include <linux/pci.h>
16#include <linux/dma-mapping.h>
17#include <linux/sched.h>
18#include <linux/slab.h>
19#include <linux/dmapool.h>
20#include <linux/mempool.h>
21#include <linux/spinlock.h>
22#include <linux/completion.h>
Andrew Vasquezabbd8872005-07-06 10:30:05 -070023#include <linux/interrupt.h>
James.Smart@Emulex.Com19a7b4a2005-10-18 12:03:35 -040024#include <linux/workqueue.h>
Andrew Vasquez54333832005-11-09 15:49:04 -080025#include <linux/firmware.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070026#include <asm/semaphore.h>
27
28#include <scsi/scsi.h>
29#include <scsi/scsi_host.h>
30#include <scsi/scsi_device.h>
31#include <scsi/scsi_cmnd.h>
andrew.vasquez@qlogic.com392e2f62006-01-31 16:05:02 -080032#include <scsi/scsi_transport_fc.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070033
Andrew Vasquezcb630672006-05-17 15:09:45 -070034#define QLA2XXX_DRIVER_NAME "qla2xxx"
35
Linus Torvalds1da177e2005-04-16 15:20:36 -070036/*
37 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
38 * but that's fine as we don't look at the last 24 ones for
39 * ISP2100 HBAs.
40 */
41#define MAILBOX_REGISTER_COUNT_2100 8
42#define MAILBOX_REGISTER_COUNT 32
43
44#define QLA2200A_RISC_ROM_VER 4
45#define FPM_2300 6
46#define FPM_2310 7
47
48#include "qla_settings.h"
49
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -070050/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070051 * Data bit definitions
52 */
53#define BIT_0 0x1
54#define BIT_1 0x2
55#define BIT_2 0x4
56#define BIT_3 0x8
57#define BIT_4 0x10
58#define BIT_5 0x20
59#define BIT_6 0x40
60#define BIT_7 0x80
61#define BIT_8 0x100
62#define BIT_9 0x200
63#define BIT_10 0x400
64#define BIT_11 0x800
65#define BIT_12 0x1000
66#define BIT_13 0x2000
67#define BIT_14 0x4000
68#define BIT_15 0x8000
69#define BIT_16 0x10000
70#define BIT_17 0x20000
71#define BIT_18 0x40000
72#define BIT_19 0x80000
73#define BIT_20 0x100000
74#define BIT_21 0x200000
75#define BIT_22 0x400000
76#define BIT_23 0x800000
77#define BIT_24 0x1000000
78#define BIT_25 0x2000000
79#define BIT_26 0x4000000
80#define BIT_27 0x8000000
81#define BIT_28 0x10000000
82#define BIT_29 0x20000000
83#define BIT_30 0x40000000
84#define BIT_31 0x80000000
85
86#define LSB(x) ((uint8_t)(x))
87#define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
88
89#define LSW(x) ((uint16_t)(x))
90#define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
91
92#define LSD(x) ((uint32_t)((uint64_t)(x)))
93#define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
94
95
96/*
97 * I/O register
98*/
99
100#define RD_REG_BYTE(addr) readb(addr)
101#define RD_REG_WORD(addr) readw(addr)
102#define RD_REG_DWORD(addr) readl(addr)
103#define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
104#define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
105#define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
106#define WRT_REG_BYTE(addr, data) writeb(data,addr)
107#define WRT_REG_WORD(addr, data) writew(data,addr)
108#define WRT_REG_DWORD(addr, data) writel(data,addr)
109
110/*
andrew.vasquez@qlogic.comf6df1442006-01-31 16:05:07 -0800111 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
112 * 133Mhz slot.
113 */
114#define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
115#define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr))
116
117/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700118 * Fibre Channel device definitions.
119 */
120#define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
121#define MAX_FIBRE_DEVICES 512
Andrew Vasquezcc4731f2005-07-06 10:32:37 -0700122#define MAX_FIBRE_LUNS 0xFFFF
Linus Torvalds1da177e2005-04-16 15:20:36 -0700123#define MAX_RSCN_COUNT 32
124#define MAX_HOST_COUNT 16
125
126/*
127 * Host adapter default definitions.
128 */
129#define MAX_BUSES 1 /* We only have one bus today */
130#define MAX_TARGETS_2100 MAX_FIBRE_DEVICES
131#define MAX_TARGETS_2200 MAX_FIBRE_DEVICES
Linus Torvalds1da177e2005-04-16 15:20:36 -0700132#define MIN_LUNS 8
133#define MAX_LUNS MAX_FIBRE_LUNS
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -0700134#define MAX_CMDS_PER_LUN 255
135
Linus Torvalds1da177e2005-04-16 15:20:36 -0700136/*
137 * Fibre Channel device definitions.
138 */
139#define SNS_LAST_LOOP_ID_2100 0xfe
140#define SNS_LAST_LOOP_ID_2300 0x7ff
141
142#define LAST_LOCAL_LOOP_ID 0x7d
143#define SNS_FL_PORT 0x7e
144#define FABRIC_CONTROLLER 0x7f
145#define SIMPLE_NAME_SERVER 0x80
146#define SNS_FIRST_LOOP_ID 0x81
147#define MANAGEMENT_SERVER 0xfe
148#define BROADCAST 0xff
149
Andrew Vasquez3d716442005-07-06 10:30:26 -0700150/*
151 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
152 * valid range of an N-PORT id is 0 through 0x7ef.
153 */
154#define NPH_LAST_HANDLE 0x7ef
Andrew Vasquezcca53352005-08-26 19:08:30 -0700155#define NPH_MGMT_SERVER 0x7fa /* FFFFFA */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700156#define NPH_SNS 0x7fc /* FFFFFC */
157#define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
158#define NPH_F_PORT 0x7fe /* FFFFFE */
159#define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
160
161#define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
162#include "qla_fw.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700163
164/*
165 * Timeout timer counts in seconds
166 */
8482e112005-04-17 15:04:54 -0500167#define PORT_RETRY_TIME 1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700168#define LOOP_DOWN_TIMEOUT 60
169#define LOOP_DOWN_TIME 255 /* 240 */
170#define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
171
172/* Maximum outstanding commands in ISP queues (1-65535) */
173#define MAX_OUTSTANDING_COMMANDS 1024
174
175/* ISP request and response entry counts (37-65535) */
176#define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
177#define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
178#define REQUEST_ENTRY_CNT_2XXX_EXT_MEM 4096 /* Number of request entries. */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700179#define REQUEST_ENTRY_CNT_24XX 4096 /* Number of request entries. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700180#define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
181#define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
182
183/*
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -0700184 * SCSI Request Block
Linus Torvalds1da177e2005-04-16 15:20:36 -0700185 */
186typedef struct srb {
187 struct list_head list;
188
189 struct scsi_qla_host *ha; /* HA the SP is queued on */
bdf79622005-04-17 15:06:53 -0500190 struct fc_port *fcport;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700191
192 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
193
Linus Torvalds1da177e2005-04-16 15:20:36 -0700194 uint16_t flags;
195
Linus Torvalds1da177e2005-04-16 15:20:36 -0700196 /* Single transfer DMA context */
197 dma_addr_t dma_handle;
198
199 uint32_t request_sense_length;
200 uint8_t *request_sense_ptr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700201} srb_t;
202
203/*
204 * SRB flag definitions
205 */
206#define SRB_TIMEOUT BIT_0 /* Command timed out */
207#define SRB_DMA_VALID BIT_1 /* Command sent to ISP */
208#define SRB_WATCHDOG BIT_2 /* Command on watchdog list */
209#define SRB_ABORT_PENDING BIT_3 /* Command abort sent to device */
210
211#define SRB_ABORTED BIT_4 /* Command aborted command already */
212#define SRB_RETRY BIT_5 /* Command needs retrying */
213#define SRB_GOT_SENSE BIT_6 /* Command has sense data */
214#define SRB_FAILOVER BIT_7 /* Command in failover state */
215
216#define SRB_BUSY BIT_8 /* Command is in busy retry state */
217#define SRB_FO_CANCEL BIT_9 /* Command don't need to do failover */
218#define SRB_IOCTL BIT_10 /* IOCTL command. */
219#define SRB_TAPE BIT_11 /* FCP2 (Tape) command. */
220
221/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700222 * ISP I/O Register Set structure definitions.
223 */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700224struct device_reg_2xxx {
225 uint16_t flash_address; /* Flash BIOS address */
226 uint16_t flash_data; /* Flash BIOS data */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700227 uint16_t unused_1[1]; /* Gap */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700228 uint16_t ctrl_status; /* Control/Status */
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -0700229#define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700230#define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
231#define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
232
Andrew Vasquez3d716442005-07-06 10:30:26 -0700233 uint16_t ictrl; /* Interrupt control */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700234#define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
235#define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
236
Andrew Vasquez3d716442005-07-06 10:30:26 -0700237 uint16_t istatus; /* Interrupt status */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700238#define ISR_RISC_INT BIT_3 /* RISC interrupt */
239
Andrew Vasquez3d716442005-07-06 10:30:26 -0700240 uint16_t semaphore; /* Semaphore */
241 uint16_t nvram; /* NVRAM register. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700242#define NVR_DESELECT 0
243#define NVR_BUSY BIT_15
244#define NVR_WRT_ENABLE BIT_14 /* Write enable */
245#define NVR_PR_ENABLE BIT_13 /* Protection register enable */
246#define NVR_DATA_IN BIT_3
247#define NVR_DATA_OUT BIT_2
248#define NVR_SELECT BIT_1
249#define NVR_CLOCK BIT_0
250
Ravi Anand45aeaf12006-05-17 15:08:49 -0700251#define NVR_WAIT_CNT 20000
252
Linus Torvalds1da177e2005-04-16 15:20:36 -0700253 union {
254 struct {
Andrew Vasquez3d716442005-07-06 10:30:26 -0700255 uint16_t mailbox0;
256 uint16_t mailbox1;
257 uint16_t mailbox2;
258 uint16_t mailbox3;
259 uint16_t mailbox4;
260 uint16_t mailbox5;
261 uint16_t mailbox6;
262 uint16_t mailbox7;
263 uint16_t unused_2[59]; /* Gap */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700264 } __attribute__((packed)) isp2100;
265 struct {
Andrew Vasquez3d716442005-07-06 10:30:26 -0700266 /* Request Queue */
267 uint16_t req_q_in; /* In-Pointer */
268 uint16_t req_q_out; /* Out-Pointer */
269 /* Response Queue */
270 uint16_t rsp_q_in; /* In-Pointer */
271 uint16_t rsp_q_out; /* Out-Pointer */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700272
273 /* RISC to Host Status */
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -0700274 uint32_t host_status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700275#define HSR_RISC_INT BIT_15 /* RISC interrupt */
276#define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
277
278 /* Host to Host Semaphore */
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -0700279 uint16_t host_semaphore;
Andrew Vasquez3d716442005-07-06 10:30:26 -0700280 uint16_t unused_3[17]; /* Gap */
281 uint16_t mailbox0;
282 uint16_t mailbox1;
283 uint16_t mailbox2;
284 uint16_t mailbox3;
285 uint16_t mailbox4;
286 uint16_t mailbox5;
287 uint16_t mailbox6;
288 uint16_t mailbox7;
289 uint16_t mailbox8;
290 uint16_t mailbox9;
291 uint16_t mailbox10;
292 uint16_t mailbox11;
293 uint16_t mailbox12;
294 uint16_t mailbox13;
295 uint16_t mailbox14;
296 uint16_t mailbox15;
297 uint16_t mailbox16;
298 uint16_t mailbox17;
299 uint16_t mailbox18;
300 uint16_t mailbox19;
301 uint16_t mailbox20;
302 uint16_t mailbox21;
303 uint16_t mailbox22;
304 uint16_t mailbox23;
305 uint16_t mailbox24;
306 uint16_t mailbox25;
307 uint16_t mailbox26;
308 uint16_t mailbox27;
309 uint16_t mailbox28;
310 uint16_t mailbox29;
311 uint16_t mailbox30;
312 uint16_t mailbox31;
313 uint16_t fb_cmd;
314 uint16_t unused_4[10]; /* Gap */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700315 } __attribute__((packed)) isp2300;
316 } u;
317
Andrew Vasquez3d716442005-07-06 10:30:26 -0700318 uint16_t fpm_diag_config;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700319 uint16_t unused_5[0x6]; /* Gap */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700320 uint16_t pcr; /* Processor Control Register. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700321 uint16_t unused_6[0x5]; /* Gap */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700322 uint16_t mctr; /* Memory Configuration and Timing. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700323 uint16_t unused_7[0x3]; /* Gap */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700324 uint16_t fb_cmd_2100; /* Unused on 23XX */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700325 uint16_t unused_8[0x3]; /* Gap */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700326 uint16_t hccr; /* Host command & control register. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700327#define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
328#define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
329 /* HCCR commands */
330#define HCCR_RESET_RISC 0x1000 /* Reset RISC */
331#define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
332#define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
333#define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
334#define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
335#define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
336#define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
337#define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
338
339 uint16_t unused_9[5]; /* Gap */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700340 uint16_t gpiod; /* GPIO Data register. */
341 uint16_t gpioe; /* GPIO Enable register. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700342#define GPIO_LED_MASK 0x00C0
343#define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
344#define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
345#define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
346#define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
andrew.vasquez@qlogic.comf6df1442006-01-31 16:05:07 -0800347#define GPIO_LED_ALL_OFF 0x0000
348#define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */
349#define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700350
351 union {
352 struct {
Andrew Vasquez3d716442005-07-06 10:30:26 -0700353 uint16_t unused_10[8]; /* Gap */
354 uint16_t mailbox8;
355 uint16_t mailbox9;
356 uint16_t mailbox10;
357 uint16_t mailbox11;
358 uint16_t mailbox12;
359 uint16_t mailbox13;
360 uint16_t mailbox14;
361 uint16_t mailbox15;
362 uint16_t mailbox16;
363 uint16_t mailbox17;
364 uint16_t mailbox18;
365 uint16_t mailbox19;
366 uint16_t mailbox20;
367 uint16_t mailbox21;
368 uint16_t mailbox22;
369 uint16_t mailbox23; /* Also probe reg. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700370 } __attribute__((packed)) isp2200;
371 } u_end;
Andrew Vasquez3d716442005-07-06 10:30:26 -0700372};
373
Andrew Morton9a168bd2005-07-26 14:11:28 -0700374typedef union {
Andrew Vasquez3d716442005-07-06 10:30:26 -0700375 struct device_reg_2xxx isp;
376 struct device_reg_24xx isp24;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700377} device_reg_t;
378
379#define ISP_REQ_Q_IN(ha, reg) \
380 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
381 &(reg)->u.isp2100.mailbox4 : \
382 &(reg)->u.isp2300.req_q_in)
383#define ISP_REQ_Q_OUT(ha, reg) \
384 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
385 &(reg)->u.isp2100.mailbox4 : \
386 &(reg)->u.isp2300.req_q_out)
387#define ISP_RSP_Q_IN(ha, reg) \
388 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
389 &(reg)->u.isp2100.mailbox5 : \
390 &(reg)->u.isp2300.rsp_q_in)
391#define ISP_RSP_Q_OUT(ha, reg) \
392 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
393 &(reg)->u.isp2100.mailbox5 : \
394 &(reg)->u.isp2300.rsp_q_out)
395
396#define MAILBOX_REG(ha, reg, num) \
397 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
398 (num < 8 ? \
399 &(reg)->u.isp2100.mailbox0 + (num) : \
400 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
401 &(reg)->u.isp2300.mailbox0 + (num))
402#define RD_MAILBOX_REG(ha, reg, num) \
403 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
404#define WRT_MAILBOX_REG(ha, reg, num, data) \
405 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
406
407#define FB_CMD_REG(ha, reg) \
408 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
409 &(reg)->fb_cmd_2100 : \
410 &(reg)->u.isp2300.fb_cmd)
411#define RD_FB_CMD_REG(ha, reg) \
412 RD_REG_WORD(FB_CMD_REG(ha, reg))
413#define WRT_FB_CMD_REG(ha, reg, data) \
414 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
415
416typedef struct {
417 uint32_t out_mb; /* outbound from driver */
418 uint32_t in_mb; /* Incoming from RISC */
419 uint16_t mb[MAILBOX_REGISTER_COUNT];
420 long buf_size;
421 void *bufp;
422 uint32_t tov;
423 uint8_t flags;
424#define MBX_DMA_IN BIT_0
425#define MBX_DMA_OUT BIT_1
426#define IOCTL_CMD BIT_2
427} mbx_cmd_t;
428
429#define MBX_TOV_SECONDS 30
430
431/*
432 * ISP product identification definitions in mailboxes after reset.
433 */
434#define PROD_ID_1 0x4953
435#define PROD_ID_2 0x0000
436#define PROD_ID_2a 0x5020
437#define PROD_ID_3 0x2020
438
439/*
440 * ISP mailbox Self-Test status codes
441 */
442#define MBS_FRM_ALIVE 0 /* Firmware Alive. */
443#define MBS_CHKSUM_ERR 1 /* Checksum Error. */
444#define MBS_BUSY 4 /* Busy. */
445
446/*
447 * ISP mailbox command complete status codes
448 */
449#define MBS_COMMAND_COMPLETE 0x4000
450#define MBS_INVALID_COMMAND 0x4001
451#define MBS_HOST_INTERFACE_ERROR 0x4002
452#define MBS_TEST_FAILED 0x4003
453#define MBS_COMMAND_ERROR 0x4005
454#define MBS_COMMAND_PARAMETER_ERROR 0x4006
455#define MBS_PORT_ID_USED 0x4007
456#define MBS_LOOP_ID_USED 0x4008
457#define MBS_ALL_IDS_IN_USE 0x4009
458#define MBS_NOT_LOGGED_IN 0x400A
Andrew Vasquez3d716442005-07-06 10:30:26 -0700459#define MBS_LINK_DOWN_ERROR 0x400B
460#define MBS_DIAG_ECHO_TEST_ERROR 0x400C
Linus Torvalds1da177e2005-04-16 15:20:36 -0700461
462/*
463 * ISP mailbox asynchronous event status codes
464 */
465#define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
466#define MBA_RESET 0x8001 /* Reset Detected. */
467#define MBA_SYSTEM_ERR 0x8002 /* System Error. */
468#define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
469#define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
470#define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
471#define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
472 /* occurred. */
473#define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
474#define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
475#define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
476#define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
477#define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
478#define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
479#define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
480#define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
481#define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
482#define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
483#define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
484#define MBA_IP_RECEIVE 0x8023 /* IP Received. */
485#define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
486#define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
487#define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
488#define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
489 /* used. */
490#define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
491#define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
492#define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
493#define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
494#define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
495#define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
496#define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
497#define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
498#define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
499#define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
500#define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
501#define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
502#define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
503
504/*
505 * Firmware options 1, 2, 3.
506 */
507#define FO1_AE_ON_LIPF8 BIT_0
508#define FO1_AE_ALL_LIP_RESET BIT_1
509#define FO1_CTIO_RETRY BIT_3
510#define FO1_DISABLE_LIP_F7_SW BIT_4
511#define FO1_DISABLE_100MS_LOS_WAIT BIT_5
Andrew Vasquez3d716442005-07-06 10:30:26 -0700512#define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700513#define FO1_AE_ON_LOOP_INIT_ERR BIT_7
514#define FO1_SET_EMPHASIS_SWING BIT_8
515#define FO1_AE_AUTO_BYPASS BIT_9
516#define FO1_ENABLE_PURE_IOCB BIT_10
517#define FO1_AE_PLOGI_RJT BIT_11
518#define FO1_ENABLE_ABORT_SEQUENCE BIT_12
519#define FO1_AE_QUEUE_FULL BIT_13
520
521#define FO2_ENABLE_ATIO_TYPE_3 BIT_0
522#define FO2_REV_LOOPBACK BIT_1
523
524#define FO3_ENABLE_EMERG_IOCB BIT_0
525#define FO3_AE_RND_ERROR BIT_1
526
Andrew Vasquez3d716442005-07-06 10:30:26 -0700527/* 24XX additional firmware options */
528#define ADD_FO_COUNT 3
529#define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
530#define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
531
532#define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
533
534#define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
535
Linus Torvalds1da177e2005-04-16 15:20:36 -0700536/*
537 * ISP mailbox commands
538 */
539#define MBC_LOAD_RAM 1 /* Load RAM. */
540#define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
541#define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */
542#define MBC_READ_RAM_WORD 5 /* Read RAM word. */
543#define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
544#define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
545#define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
546#define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
547#define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
548#define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
549#define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
550#define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
551#define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
552#define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
Andrew Vasquezf6ef3b12005-08-26 19:10:20 -0700553#define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700554#define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
555#define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
556#define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
557#define MBC_RESET 0x18 /* Reset. */
558#define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
559#define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
560#define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
561#define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
562#define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
563#define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
564#define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
565#define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
566#define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
567#define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
568#define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
569#define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
570#define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
571#define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
572#define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
573#define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
574#define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
575#define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
576#define MBC_GET_RNID_PARAMS 0x5a /* Data Rate */
577#define MBC_DATA_RATE 0x5d /* Get RNID parameters */
578#define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
579#define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
580 /* Initialization Procedure */
581#define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
582#define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
583#define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
584#define MBC_TARGET_RESET 0x66 /* Target Reset. */
585#define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
586#define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
587#define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
588#define MBC_GET_PORT_NAME 0x6a /* Get port name. */
589#define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
590#define MBC_LIP_RESET 0x6c /* LIP reset. */
591#define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
592 /* commandd. */
593#define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
594#define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
595#define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
596#define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
597#define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
598#define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
599#define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
600#define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
601#define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
602#define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
603#define MBC_LUN_RESET 0x7E /* Send LUN reset */
604
Andrew Vasquez3d716442005-07-06 10:30:26 -0700605/*
606 * ISP24xx mailbox commands
607 */
608#define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
609#define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
610#define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
Andrew Vasqueza7a167b2006-06-23 16:10:29 -0700611#define MBC_TRACE_CONTROL 0x27 /* Trace control command. */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700612#define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
Andrew Vasquez88729e52006-06-23 16:10:50 -0700613#define MBC_READ_SFP 0x31 /* Read SFP Data. */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700614#define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
615#define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
616#define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
617#define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
618#define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
619#define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
620#define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
621#define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
622
Andrew Vasqueza7a167b2006-06-23 16:10:29 -0700623#define TC_ENABLE 4
624#define TC_DISABLE 5
625
Linus Torvalds1da177e2005-04-16 15:20:36 -0700626/* Firmware return data sizes */
627#define FCAL_MAP_SIZE 128
628
629/* Mailbox bit definitions for out_mb and in_mb */
630#define MBX_31 BIT_31
631#define MBX_30 BIT_30
632#define MBX_29 BIT_29
633#define MBX_28 BIT_28
634#define MBX_27 BIT_27
635#define MBX_26 BIT_26
636#define MBX_25 BIT_25
637#define MBX_24 BIT_24
638#define MBX_23 BIT_23
639#define MBX_22 BIT_22
640#define MBX_21 BIT_21
641#define MBX_20 BIT_20
642#define MBX_19 BIT_19
643#define MBX_18 BIT_18
644#define MBX_17 BIT_17
645#define MBX_16 BIT_16
646#define MBX_15 BIT_15
647#define MBX_14 BIT_14
648#define MBX_13 BIT_13
649#define MBX_12 BIT_12
650#define MBX_11 BIT_11
651#define MBX_10 BIT_10
652#define MBX_9 BIT_9
653#define MBX_8 BIT_8
654#define MBX_7 BIT_7
655#define MBX_6 BIT_6
656#define MBX_5 BIT_5
657#define MBX_4 BIT_4
658#define MBX_3 BIT_3
659#define MBX_2 BIT_2
660#define MBX_1 BIT_1
661#define MBX_0 BIT_0
662
663/*
664 * Firmware state codes from get firmware state mailbox command
665 */
666#define FSTATE_CONFIG_WAIT 0
667#define FSTATE_WAIT_AL_PA 1
668#define FSTATE_WAIT_LOGIN 2
669#define FSTATE_READY 3
670#define FSTATE_LOSS_OF_SYNC 4
671#define FSTATE_ERROR 5
672#define FSTATE_REINIT 6
673#define FSTATE_NON_PART 7
674
675#define FSTATE_CONFIG_CORRECT 0
676#define FSTATE_P2P_RCV_LIP 1
677#define FSTATE_P2P_CHOOSE_LOOP 2
678#define FSTATE_P2P_RCV_UNIDEN_LIP 3
679#define FSTATE_FATAL_ERROR 4
680#define FSTATE_LOOP_BACK_CONN 5
681
682/*
683 * Port Database structure definition
684 * Little endian except where noted.
685 */
686#define PORT_DATABASE_SIZE 128 /* bytes */
687typedef struct {
688 uint8_t options;
689 uint8_t control;
690 uint8_t master_state;
691 uint8_t slave_state;
692 uint8_t reserved[2];
693 uint8_t hard_address;
694 uint8_t reserved_1;
695 uint8_t port_id[4];
696 uint8_t node_name[WWN_SIZE];
697 uint8_t port_name[WWN_SIZE];
698 uint16_t execution_throttle;
699 uint16_t execution_count;
700 uint8_t reset_count;
701 uint8_t reserved_2;
702 uint16_t resource_allocation;
703 uint16_t current_allocation;
704 uint16_t queue_head;
705 uint16_t queue_tail;
706 uint16_t transmit_execution_list_next;
707 uint16_t transmit_execution_list_previous;
708 uint16_t common_features;
709 uint16_t total_concurrent_sequences;
710 uint16_t RO_by_information_category;
711 uint8_t recipient;
712 uint8_t initiator;
713 uint16_t receive_data_size;
714 uint16_t concurrent_sequences;
715 uint16_t open_sequences_per_exchange;
716 uint16_t lun_abort_flags;
717 uint16_t lun_stop_flags;
718 uint16_t stop_queue_head;
719 uint16_t stop_queue_tail;
720 uint16_t port_retry_timer;
721 uint16_t next_sequence_id;
722 uint16_t frame_count;
723 uint16_t PRLI_payload_length;
724 uint8_t prli_svc_param_word_0[2]; /* Big endian */
725 /* Bits 15-0 of word 0 */
726 uint8_t prli_svc_param_word_3[2]; /* Big endian */
727 /* Bits 15-0 of word 3 */
728 uint16_t loop_id;
729 uint16_t extended_lun_info_list_pointer;
730 uint16_t extended_lun_stop_list_pointer;
731} port_database_t;
732
733/*
734 * Port database slave/master states
735 */
736#define PD_STATE_DISCOVERY 0
737#define PD_STATE_WAIT_DISCOVERY_ACK 1
738#define PD_STATE_PORT_LOGIN 2
739#define PD_STATE_WAIT_PORT_LOGIN_ACK 3
740#define PD_STATE_PROCESS_LOGIN 4
741#define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
742#define PD_STATE_PORT_LOGGED_IN 6
743#define PD_STATE_PORT_UNAVAILABLE 7
744#define PD_STATE_PROCESS_LOGOUT 8
745#define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
746#define PD_STATE_PORT_LOGOUT 10
747#define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
748
749
Andrew Vasquez4fdfefe2005-10-27 11:09:48 -0700750#define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
751#define QLA_ZIO_DISABLED 0
752#define QLA_ZIO_DEFAULT_TIMER 2
753
Linus Torvalds1da177e2005-04-16 15:20:36 -0700754/*
755 * ISP Initialization Control Block.
756 * Little endian except where noted.
757 */
758#define ICB_VERSION 1
759typedef struct {
760 uint8_t version;
761 uint8_t reserved_1;
762
763 /*
764 * LSB BIT 0 = Enable Hard Loop Id
765 * LSB BIT 1 = Enable Fairness
766 * LSB BIT 2 = Enable Full-Duplex
767 * LSB BIT 3 = Enable Fast Posting
768 * LSB BIT 4 = Enable Target Mode
769 * LSB BIT 5 = Disable Initiator Mode
770 * LSB BIT 6 = Enable ADISC
771 * LSB BIT 7 = Enable Target Inquiry Data
772 *
773 * MSB BIT 0 = Enable PDBC Notify
774 * MSB BIT 1 = Non Participating LIP
775 * MSB BIT 2 = Descending Loop ID Search
776 * MSB BIT 3 = Acquire Loop ID in LIPA
777 * MSB BIT 4 = Stop PortQ on Full Status
778 * MSB BIT 5 = Full Login after LIP
779 * MSB BIT 6 = Node Name Option
780 * MSB BIT 7 = Ext IFWCB enable bit
781 */
782 uint8_t firmware_options[2];
783
784 uint16_t frame_payload_size;
785 uint16_t max_iocb_allocation;
786 uint16_t execution_throttle;
787 uint8_t retry_count;
788 uint8_t retry_delay; /* unused */
789 uint8_t port_name[WWN_SIZE]; /* Big endian. */
790 uint16_t hard_address;
791 uint8_t inquiry_data;
792 uint8_t login_timeout;
793 uint8_t node_name[WWN_SIZE]; /* Big endian. */
794
795 uint16_t request_q_outpointer;
796 uint16_t response_q_inpointer;
797 uint16_t request_q_length;
798 uint16_t response_q_length;
799 uint32_t request_q_address[2];
800 uint32_t response_q_address[2];
801
802 uint16_t lun_enables;
803 uint8_t command_resource_count;
804 uint8_t immediate_notify_resource_count;
805 uint16_t timeout;
806 uint8_t reserved_2[2];
807
808 /*
809 * LSB BIT 0 = Timer Operation mode bit 0
810 * LSB BIT 1 = Timer Operation mode bit 1
811 * LSB BIT 2 = Timer Operation mode bit 2
812 * LSB BIT 3 = Timer Operation mode bit 3
813 * LSB BIT 4 = Init Config Mode bit 0
814 * LSB BIT 5 = Init Config Mode bit 1
815 * LSB BIT 6 = Init Config Mode bit 2
816 * LSB BIT 7 = Enable Non part on LIHA failure
817 *
818 * MSB BIT 0 = Enable class 2
819 * MSB BIT 1 = Enable ACK0
820 * MSB BIT 2 =
821 * MSB BIT 3 =
822 * MSB BIT 4 = FC Tape Enable
823 * MSB BIT 5 = Enable FC Confirm
824 * MSB BIT 6 = Enable command queuing in target mode
825 * MSB BIT 7 = No Logo On Link Down
826 */
827 uint8_t add_firmware_options[2];
828
829 uint8_t response_accumulation_timer;
830 uint8_t interrupt_delay_timer;
831
832 /*
833 * LSB BIT 0 = Enable Read xfr_rdy
834 * LSB BIT 1 = Soft ID only
835 * LSB BIT 2 =
836 * LSB BIT 3 =
837 * LSB BIT 4 = FCP RSP Payload [0]
838 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
839 * LSB BIT 6 = Enable Out-of-Order frame handling
840 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
841 *
842 * MSB BIT 0 = Sbus enable - 2300
843 * MSB BIT 1 =
844 * MSB BIT 2 =
845 * MSB BIT 3 =
Andrew Vasquez06c22bd2005-08-26 19:09:00 -0700846 * MSB BIT 4 = LED mode
Linus Torvalds1da177e2005-04-16 15:20:36 -0700847 * MSB BIT 5 = enable 50 ohm termination
848 * MSB BIT 6 = Data Rate (2300 only)
849 * MSB BIT 7 = Data Rate (2300 only)
850 */
851 uint8_t special_options[2];
852
853 uint8_t reserved_3[26];
854} init_cb_t;
855
856/*
857 * Get Link Status mailbox command return buffer.
858 */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700859#define GLSO_SEND_RPS BIT_0
860#define GLSO_USE_DID BIT_3
861
Linus Torvalds1da177e2005-04-16 15:20:36 -0700862typedef struct {
863 uint32_t link_fail_cnt;
864 uint32_t loss_sync_cnt;
865 uint32_t loss_sig_cnt;
866 uint32_t prim_seq_err_cnt;
867 uint32_t inval_xmit_word_cnt;
868 uint32_t inval_crc_cnt;
869} link_stat_t;
870
871/*
872 * NVRAM Command values.
873 */
874#define NV_START_BIT BIT_2
875#define NV_WRITE_OP (BIT_26+BIT_24)
876#define NV_READ_OP (BIT_26+BIT_25)
877#define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
878#define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
879#define NV_DELAY_COUNT 10
880
881/*
882 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
883 */
884typedef struct {
885 /*
886 * NVRAM header
887 */
888 uint8_t id[4];
889 uint8_t nvram_version;
890 uint8_t reserved_0;
891
892 /*
893 * NVRAM RISC parameter block
894 */
895 uint8_t parameter_block_version;
896 uint8_t reserved_1;
897
898 /*
899 * LSB BIT 0 = Enable Hard Loop Id
900 * LSB BIT 1 = Enable Fairness
901 * LSB BIT 2 = Enable Full-Duplex
902 * LSB BIT 3 = Enable Fast Posting
903 * LSB BIT 4 = Enable Target Mode
904 * LSB BIT 5 = Disable Initiator Mode
905 * LSB BIT 6 = Enable ADISC
906 * LSB BIT 7 = Enable Target Inquiry Data
907 *
908 * MSB BIT 0 = Enable PDBC Notify
909 * MSB BIT 1 = Non Participating LIP
910 * MSB BIT 2 = Descending Loop ID Search
911 * MSB BIT 3 = Acquire Loop ID in LIPA
912 * MSB BIT 4 = Stop PortQ on Full Status
913 * MSB BIT 5 = Full Login after LIP
914 * MSB BIT 6 = Node Name Option
915 * MSB BIT 7 = Ext IFWCB enable bit
916 */
917 uint8_t firmware_options[2];
918
919 uint16_t frame_payload_size;
920 uint16_t max_iocb_allocation;
921 uint16_t execution_throttle;
922 uint8_t retry_count;
923 uint8_t retry_delay; /* unused */
924 uint8_t port_name[WWN_SIZE]; /* Big endian. */
925 uint16_t hard_address;
926 uint8_t inquiry_data;
927 uint8_t login_timeout;
928 uint8_t node_name[WWN_SIZE]; /* Big endian. */
929
930 /*
931 * LSB BIT 0 = Timer Operation mode bit 0
932 * LSB BIT 1 = Timer Operation mode bit 1
933 * LSB BIT 2 = Timer Operation mode bit 2
934 * LSB BIT 3 = Timer Operation mode bit 3
935 * LSB BIT 4 = Init Config Mode bit 0
936 * LSB BIT 5 = Init Config Mode bit 1
937 * LSB BIT 6 = Init Config Mode bit 2
938 * LSB BIT 7 = Enable Non part on LIHA failure
939 *
940 * MSB BIT 0 = Enable class 2
941 * MSB BIT 1 = Enable ACK0
942 * MSB BIT 2 =
943 * MSB BIT 3 =
944 * MSB BIT 4 = FC Tape Enable
945 * MSB BIT 5 = Enable FC Confirm
946 * MSB BIT 6 = Enable command queuing in target mode
947 * MSB BIT 7 = No Logo On Link Down
948 */
949 uint8_t add_firmware_options[2];
950
951 uint8_t response_accumulation_timer;
952 uint8_t interrupt_delay_timer;
953
954 /*
955 * LSB BIT 0 = Enable Read xfr_rdy
956 * LSB BIT 1 = Soft ID only
957 * LSB BIT 2 =
958 * LSB BIT 3 =
959 * LSB BIT 4 = FCP RSP Payload [0]
960 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
961 * LSB BIT 6 = Enable Out-of-Order frame handling
962 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
963 *
964 * MSB BIT 0 = Sbus enable - 2300
965 * MSB BIT 1 =
966 * MSB BIT 2 =
967 * MSB BIT 3 =
Andrew Vasquez06c22bd2005-08-26 19:09:00 -0700968 * MSB BIT 4 = LED mode
Linus Torvalds1da177e2005-04-16 15:20:36 -0700969 * MSB BIT 5 = enable 50 ohm termination
970 * MSB BIT 6 = Data Rate (2300 only)
971 * MSB BIT 7 = Data Rate (2300 only)
972 */
973 uint8_t special_options[2];
974
975 /* Reserved for expanded RISC parameter block */
976 uint8_t reserved_2[22];
977
978 /*
979 * LSB BIT 0 = Tx Sensitivity 1G bit 0
980 * LSB BIT 1 = Tx Sensitivity 1G bit 1
981 * LSB BIT 2 = Tx Sensitivity 1G bit 2
982 * LSB BIT 3 = Tx Sensitivity 1G bit 3
983 * LSB BIT 4 = Rx Sensitivity 1G bit 0
984 * LSB BIT 5 = Rx Sensitivity 1G bit 1
985 * LSB BIT 6 = Rx Sensitivity 1G bit 2
986 * LSB BIT 7 = Rx Sensitivity 1G bit 3
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -0700987 *
Linus Torvalds1da177e2005-04-16 15:20:36 -0700988 * MSB BIT 0 = Tx Sensitivity 2G bit 0
989 * MSB BIT 1 = Tx Sensitivity 2G bit 1
990 * MSB BIT 2 = Tx Sensitivity 2G bit 2
991 * MSB BIT 3 = Tx Sensitivity 2G bit 3
992 * MSB BIT 4 = Rx Sensitivity 2G bit 0
993 * MSB BIT 5 = Rx Sensitivity 2G bit 1
994 * MSB BIT 6 = Rx Sensitivity 2G bit 2
995 * MSB BIT 7 = Rx Sensitivity 2G bit 3
996 *
997 * LSB BIT 0 = Output Swing 1G bit 0
998 * LSB BIT 1 = Output Swing 1G bit 1
999 * LSB BIT 2 = Output Swing 1G bit 2
1000 * LSB BIT 3 = Output Emphasis 1G bit 0
1001 * LSB BIT 4 = Output Emphasis 1G bit 1
1002 * LSB BIT 5 = Output Swing 2G bit 0
1003 * LSB BIT 6 = Output Swing 2G bit 1
1004 * LSB BIT 7 = Output Swing 2G bit 2
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07001005 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07001006 * MSB BIT 0 = Output Emphasis 2G bit 0
1007 * MSB BIT 1 = Output Emphasis 2G bit 1
1008 * MSB BIT 2 = Output Enable
1009 * MSB BIT 3 =
1010 * MSB BIT 4 =
1011 * MSB BIT 5 =
1012 * MSB BIT 6 =
1013 * MSB BIT 7 =
1014 */
1015 uint8_t seriallink_options[4];
1016
1017 /*
1018 * NVRAM host parameter block
1019 *
1020 * LSB BIT 0 = Enable spinup delay
1021 * LSB BIT 1 = Disable BIOS
1022 * LSB BIT 2 = Enable Memory Map BIOS
1023 * LSB BIT 3 = Enable Selectable Boot
1024 * LSB BIT 4 = Disable RISC code load
1025 * LSB BIT 5 = Set cache line size 1
1026 * LSB BIT 6 = PCI Parity Disable
1027 * LSB BIT 7 = Enable extended logging
1028 *
1029 * MSB BIT 0 = Enable 64bit addressing
1030 * MSB BIT 1 = Enable lip reset
1031 * MSB BIT 2 = Enable lip full login
1032 * MSB BIT 3 = Enable target reset
1033 * MSB BIT 4 = Enable database storage
1034 * MSB BIT 5 = Enable cache flush read
1035 * MSB BIT 6 = Enable database load
1036 * MSB BIT 7 = Enable alternate WWN
1037 */
1038 uint8_t host_p[2];
1039
1040 uint8_t boot_node_name[WWN_SIZE];
1041 uint8_t boot_lun_number;
1042 uint8_t reset_delay;
1043 uint8_t port_down_retry_count;
1044 uint8_t boot_id_number;
1045 uint16_t max_luns_per_target;
1046 uint8_t fcode_boot_port_name[WWN_SIZE];
1047 uint8_t alternate_port_name[WWN_SIZE];
1048 uint8_t alternate_node_name[WWN_SIZE];
1049
1050 /*
1051 * BIT 0 = Selective Login
1052 * BIT 1 = Alt-Boot Enable
1053 * BIT 2 =
1054 * BIT 3 = Boot Order List
1055 * BIT 4 =
1056 * BIT 5 = Selective LUN
1057 * BIT 6 =
1058 * BIT 7 = unused
1059 */
1060 uint8_t efi_parameters;
1061
1062 uint8_t link_down_timeout;
1063
Andrew Vasquezcca53352005-08-26 19:08:30 -07001064 uint8_t adapter_id[16];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001065
1066 uint8_t alt1_boot_node_name[WWN_SIZE];
1067 uint16_t alt1_boot_lun_number;
1068 uint8_t alt2_boot_node_name[WWN_SIZE];
1069 uint16_t alt2_boot_lun_number;
1070 uint8_t alt3_boot_node_name[WWN_SIZE];
1071 uint16_t alt3_boot_lun_number;
1072 uint8_t alt4_boot_node_name[WWN_SIZE];
1073 uint16_t alt4_boot_lun_number;
1074 uint8_t alt5_boot_node_name[WWN_SIZE];
1075 uint16_t alt5_boot_lun_number;
1076 uint8_t alt6_boot_node_name[WWN_SIZE];
1077 uint16_t alt6_boot_lun_number;
1078 uint8_t alt7_boot_node_name[WWN_SIZE];
1079 uint16_t alt7_boot_lun_number;
1080
1081 uint8_t reserved_3[2];
1082
1083 /* Offset 200-215 : Model Number */
1084 uint8_t model_number[16];
1085
1086 /* OEM related items */
1087 uint8_t oem_specific[16];
1088
1089 /*
1090 * NVRAM Adapter Features offset 232-239
1091 *
1092 * LSB BIT 0 = External GBIC
1093 * LSB BIT 1 = Risc RAM parity
1094 * LSB BIT 2 = Buffer Plus Module
1095 * LSB BIT 3 = Multi Chip Adapter
1096 * LSB BIT 4 = Internal connector
1097 * LSB BIT 5 =
1098 * LSB BIT 6 =
1099 * LSB BIT 7 =
1100 *
1101 * MSB BIT 0 =
1102 * MSB BIT 1 =
1103 * MSB BIT 2 =
1104 * MSB BIT 3 =
1105 * MSB BIT 4 =
1106 * MSB BIT 5 =
1107 * MSB BIT 6 =
1108 * MSB BIT 7 =
1109 */
1110 uint8_t adapter_features[2];
1111
1112 uint8_t reserved_4[16];
1113
1114 /* Subsystem vendor ID for ISP2200 */
1115 uint16_t subsystem_vendor_id_2200;
1116
1117 /* Subsystem device ID for ISP2200 */
1118 uint16_t subsystem_device_id_2200;
1119
1120 uint8_t reserved_5;
1121 uint8_t checksum;
1122} nvram_t;
1123
1124/*
1125 * ISP queue - response queue entry definition.
1126 */
1127typedef struct {
1128 uint8_t data[60];
1129 uint32_t signature;
1130#define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1131} response_t;
1132
1133typedef union {
1134 uint16_t extended;
1135 struct {
1136 uint8_t reserved;
1137 uint8_t standard;
1138 } id;
1139} target_id_t;
1140
1141#define SET_TARGET_ID(ha, to, from) \
1142do { \
1143 if (HAS_EXTENDED_IDS(ha)) \
1144 to.extended = cpu_to_le16(from); \
1145 else \
1146 to.id.standard = (uint8_t)from; \
1147} while (0)
1148
1149/*
1150 * ISP queue - command entry structure definition.
1151 */
1152#define COMMAND_TYPE 0x11 /* Command entry */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001153typedef struct {
1154 uint8_t entry_type; /* Entry type. */
1155 uint8_t entry_count; /* Entry count. */
1156 uint8_t sys_define; /* System defined. */
1157 uint8_t entry_status; /* Entry Status. */
1158 uint32_t handle; /* System handle. */
1159 target_id_t target; /* SCSI ID */
1160 uint16_t lun; /* SCSI LUN */
1161 uint16_t control_flags; /* Control flags. */
1162#define CF_WRITE BIT_6
1163#define CF_READ BIT_5
1164#define CF_SIMPLE_TAG BIT_3
1165#define CF_ORDERED_TAG BIT_2
1166#define CF_HEAD_TAG BIT_1
1167 uint16_t reserved_1;
1168 uint16_t timeout; /* Command timeout. */
1169 uint16_t dseg_count; /* Data segment count. */
1170 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1171 uint32_t byte_count; /* Total byte count. */
1172 uint32_t dseg_0_address; /* Data segment 0 address. */
1173 uint32_t dseg_0_length; /* Data segment 0 length. */
1174 uint32_t dseg_1_address; /* Data segment 1 address. */
1175 uint32_t dseg_1_length; /* Data segment 1 length. */
1176 uint32_t dseg_2_address; /* Data segment 2 address. */
1177 uint32_t dseg_2_length; /* Data segment 2 length. */
1178} cmd_entry_t;
1179
1180/*
1181 * ISP queue - 64-Bit addressing, command entry structure definition.
1182 */
1183#define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1184typedef struct {
1185 uint8_t entry_type; /* Entry type. */
1186 uint8_t entry_count; /* Entry count. */
1187 uint8_t sys_define; /* System defined. */
1188 uint8_t entry_status; /* Entry Status. */
1189 uint32_t handle; /* System handle. */
1190 target_id_t target; /* SCSI ID */
1191 uint16_t lun; /* SCSI LUN */
1192 uint16_t control_flags; /* Control flags. */
1193 uint16_t reserved_1;
1194 uint16_t timeout; /* Command timeout. */
1195 uint16_t dseg_count; /* Data segment count. */
1196 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1197 uint32_t byte_count; /* Total byte count. */
1198 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1199 uint32_t dseg_0_length; /* Data segment 0 length. */
1200 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1201 uint32_t dseg_1_length; /* Data segment 1 length. */
1202} cmd_a64_entry_t, request_t;
1203
1204/*
1205 * ISP queue - continuation entry structure definition.
1206 */
1207#define CONTINUE_TYPE 0x02 /* Continuation entry. */
1208typedef struct {
1209 uint8_t entry_type; /* Entry type. */
1210 uint8_t entry_count; /* Entry count. */
1211 uint8_t sys_define; /* System defined. */
1212 uint8_t entry_status; /* Entry Status. */
1213 uint32_t reserved;
1214 uint32_t dseg_0_address; /* Data segment 0 address. */
1215 uint32_t dseg_0_length; /* Data segment 0 length. */
1216 uint32_t dseg_1_address; /* Data segment 1 address. */
1217 uint32_t dseg_1_length; /* Data segment 1 length. */
1218 uint32_t dseg_2_address; /* Data segment 2 address. */
1219 uint32_t dseg_2_length; /* Data segment 2 length. */
1220 uint32_t dseg_3_address; /* Data segment 3 address. */
1221 uint32_t dseg_3_length; /* Data segment 3 length. */
1222 uint32_t dseg_4_address; /* Data segment 4 address. */
1223 uint32_t dseg_4_length; /* Data segment 4 length. */
1224 uint32_t dseg_5_address; /* Data segment 5 address. */
1225 uint32_t dseg_5_length; /* Data segment 5 length. */
1226 uint32_t dseg_6_address; /* Data segment 6 address. */
1227 uint32_t dseg_6_length; /* Data segment 6 length. */
1228} cont_entry_t;
1229
1230/*
1231 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1232 */
1233#define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1234typedef struct {
1235 uint8_t entry_type; /* Entry type. */
1236 uint8_t entry_count; /* Entry count. */
1237 uint8_t sys_define; /* System defined. */
1238 uint8_t entry_status; /* Entry Status. */
1239 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1240 uint32_t dseg_0_length; /* Data segment 0 length. */
1241 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1242 uint32_t dseg_1_length; /* Data segment 1 length. */
1243 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1244 uint32_t dseg_2_length; /* Data segment 2 length. */
1245 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1246 uint32_t dseg_3_length; /* Data segment 3 length. */
1247 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1248 uint32_t dseg_4_length; /* Data segment 4 length. */
1249} cont_a64_entry_t;
1250
1251/*
1252 * ISP queue - status entry structure definition.
1253 */
1254#define STATUS_TYPE 0x03 /* Status entry. */
1255typedef struct {
1256 uint8_t entry_type; /* Entry type. */
1257 uint8_t entry_count; /* Entry count. */
1258 uint8_t sys_define; /* System defined. */
1259 uint8_t entry_status; /* Entry Status. */
1260 uint32_t handle; /* System handle. */
1261 uint16_t scsi_status; /* SCSI status. */
1262 uint16_t comp_status; /* Completion status. */
1263 uint16_t state_flags; /* State flags. */
1264 uint16_t status_flags; /* Status flags. */
1265 uint16_t rsp_info_len; /* Response Info Length. */
1266 uint16_t req_sense_length; /* Request sense data length. */
1267 uint32_t residual_length; /* Residual transfer length. */
1268 uint8_t rsp_info[8]; /* FCP response information. */
1269 uint8_t req_sense_data[32]; /* Request sense data. */
1270} sts_entry_t;
1271
1272/*
1273 * Status entry entry status
1274 */
Andrew Vasquez3d716442005-07-06 10:30:26 -07001275#define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001276#define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1277#define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1278#define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1279#define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1280#define RF_BUSY BIT_1 /* Busy */
Andrew Vasquez3d716442005-07-06 10:30:26 -07001281#define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1282 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1283#define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1284 RF_INV_E_TYPE)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001285
1286/*
1287 * Status entry SCSI status bit definitions.
1288 */
1289#define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1290#define SS_RESIDUAL_UNDER BIT_11
1291#define SS_RESIDUAL_OVER BIT_10
1292#define SS_SENSE_LEN_VALID BIT_9
1293#define SS_RESPONSE_INFO_LEN_VALID BIT_8
1294
1295#define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1296#define SS_BUSY_CONDITION BIT_3
1297#define SS_CONDITION_MET BIT_2
1298#define SS_CHECK_CONDITION BIT_1
1299
1300/*
1301 * Status entry completion status
1302 */
1303#define CS_COMPLETE 0x0 /* No errors */
1304#define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1305#define CS_DMA 0x2 /* A DMA direction error. */
1306#define CS_TRANSPORT 0x3 /* Transport error. */
1307#define CS_RESET 0x4 /* SCSI bus reset occurred */
1308#define CS_ABORTED 0x5 /* System aborted command. */
1309#define CS_TIMEOUT 0x6 /* Timeout error. */
1310#define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1311
1312#define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1313#define CS_QUEUE_FULL 0x1C /* Queue Full. */
1314#define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1315 /* (selection timeout) */
1316#define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1317#define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1318#define CS_PORT_BUSY 0x2B /* Port Busy */
1319#define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1320#define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1321#define CS_UNKNOWN 0x81 /* Driver defined */
1322#define CS_RETRY 0x82 /* Driver defined */
1323#define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1324
1325/*
1326 * Status entry status flags
1327 */
1328#define SF_ABTS_TERMINATED BIT_10
1329#define SF_LOGOUT_SENT BIT_13
1330
1331/*
1332 * ISP queue - status continuation entry structure definition.
1333 */
1334#define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1335typedef struct {
1336 uint8_t entry_type; /* Entry type. */
1337 uint8_t entry_count; /* Entry count. */
1338 uint8_t sys_define; /* System defined. */
1339 uint8_t entry_status; /* Entry Status. */
1340 uint8_t data[60]; /* data */
1341} sts_cont_entry_t;
1342
1343/*
1344 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1345 * structure definition.
1346 */
1347#define STATUS_TYPE_21 0x21 /* Status entry. */
1348typedef struct {
1349 uint8_t entry_type; /* Entry type. */
1350 uint8_t entry_count; /* Entry count. */
1351 uint8_t handle_count; /* Handle count. */
1352 uint8_t entry_status; /* Entry Status. */
1353 uint32_t handle[15]; /* System handles. */
1354} sts21_entry_t;
1355
1356/*
1357 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1358 * structure definition.
1359 */
1360#define STATUS_TYPE_22 0x22 /* Status entry. */
1361typedef struct {
1362 uint8_t entry_type; /* Entry type. */
1363 uint8_t entry_count; /* Entry count. */
1364 uint8_t handle_count; /* Handle count. */
1365 uint8_t entry_status; /* Entry Status. */
1366 uint16_t handle[30]; /* System handles. */
1367} sts22_entry_t;
1368
1369/*
1370 * ISP queue - marker entry structure definition.
1371 */
1372#define MARKER_TYPE 0x04 /* Marker entry. */
1373typedef struct {
1374 uint8_t entry_type; /* Entry type. */
1375 uint8_t entry_count; /* Entry count. */
1376 uint8_t handle_count; /* Handle count. */
1377 uint8_t entry_status; /* Entry Status. */
1378 uint32_t sys_define_2; /* System defined. */
1379 target_id_t target; /* SCSI ID */
1380 uint8_t modifier; /* Modifier (7-0). */
1381#define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1382#define MK_SYNC_ID 1 /* Synchronize ID */
1383#define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1384#define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1385 /* clear port changed, */
1386 /* use sequence number. */
1387 uint8_t reserved_1;
1388 uint16_t sequence_number; /* Sequence number of event */
1389 uint16_t lun; /* SCSI LUN */
1390 uint8_t reserved_2[48];
1391} mrk_entry_t;
1392
1393/*
1394 * ISP queue - Management Server entry structure definition.
1395 */
1396#define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1397typedef struct {
1398 uint8_t entry_type; /* Entry type. */
1399 uint8_t entry_count; /* Entry count. */
1400 uint8_t handle_count; /* Handle count. */
1401 uint8_t entry_status; /* Entry Status. */
1402 uint32_t handle1; /* System handle. */
1403 target_id_t loop_id;
1404 uint16_t status;
1405 uint16_t control_flags; /* Control flags. */
1406 uint16_t reserved2;
1407 uint16_t timeout;
1408 uint16_t cmd_dsd_count;
1409 uint16_t total_dsd_count;
1410 uint8_t type;
1411 uint8_t r_ctl;
1412 uint16_t rx_id;
1413 uint16_t reserved3;
1414 uint32_t handle2;
1415 uint32_t rsp_bytecount;
1416 uint32_t req_bytecount;
1417 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
1418 uint32_t dseg_req_length; /* Data segment 0 length. */
1419 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
1420 uint32_t dseg_rsp_length; /* Data segment 1 length. */
1421} ms_iocb_entry_t;
1422
1423
1424/*
1425 * ISP queue - Mailbox Command entry structure definition.
1426 */
1427#define MBX_IOCB_TYPE 0x39
1428struct mbx_entry {
1429 uint8_t entry_type;
1430 uint8_t entry_count;
1431 uint8_t sys_define1;
1432 /* Use sys_define1 for source type */
1433#define SOURCE_SCSI 0x00
1434#define SOURCE_IP 0x01
1435#define SOURCE_VI 0x02
1436#define SOURCE_SCTP 0x03
1437#define SOURCE_MP 0x04
1438#define SOURCE_MPIOCTL 0x05
1439#define SOURCE_ASYNC_IOCB 0x07
1440
1441 uint8_t entry_status;
1442
1443 uint32_t handle;
1444 target_id_t loop_id;
1445
1446 uint16_t status;
1447 uint16_t state_flags;
1448 uint16_t status_flags;
1449
1450 uint32_t sys_define2[2];
1451
1452 uint16_t mb0;
1453 uint16_t mb1;
1454 uint16_t mb2;
1455 uint16_t mb3;
1456 uint16_t mb6;
1457 uint16_t mb7;
1458 uint16_t mb9;
1459 uint16_t mb10;
1460 uint32_t reserved_2[2];
1461 uint8_t node_name[WWN_SIZE];
1462 uint8_t port_name[WWN_SIZE];
1463};
1464
1465/*
1466 * ISP request and response queue entry sizes
1467 */
1468#define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1469#define REQUEST_ENTRY_SIZE (sizeof(request_t))
1470
1471
1472/*
1473 * 24 bit port ID type definition.
1474 */
1475typedef union {
1476 uint32_t b24 : 24;
1477
1478 struct {
1479 uint8_t d_id[3];
1480 uint8_t rsvd_1;
1481 } r;
1482
1483 struct {
1484 uint8_t al_pa;
1485 uint8_t area;
1486 uint8_t domain;
1487 uint8_t rsvd_1;
1488 } b;
1489} port_id_t;
1490#define INVALID_PORT_ID 0xFFFFFF
1491
1492/*
1493 * Switch info gathering structure.
1494 */
1495typedef struct {
1496 port_id_t d_id;
1497 uint8_t node_name[WWN_SIZE];
1498 uint8_t port_name[WWN_SIZE];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001499} sw_info_t;
1500
1501/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001502 * Fibre channel port type.
1503 */
1504 typedef enum {
1505 FCT_UNKNOWN,
1506 FCT_RSCN,
1507 FCT_SWITCH,
1508 FCT_BROADCAST,
1509 FCT_INITIATOR,
1510 FCT_TARGET
1511} fc_port_type_t;
1512
1513/*
1514 * Fibre channel port structure.
1515 */
1516typedef struct fc_port {
1517 struct list_head list;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001518 struct scsi_qla_host *ha;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001519
1520 uint8_t node_name[WWN_SIZE];
1521 uint8_t port_name[WWN_SIZE];
1522 port_id_t d_id;
1523 uint16_t loop_id;
1524 uint16_t old_loop_id;
1525
1526 fc_port_type_t port_type;
1527
1528 atomic_t state;
1529 uint32_t flags;
1530
bdf79622005-04-17 15:06:53 -05001531 unsigned int os_target_id;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001532
Linus Torvalds1da177e2005-04-16 15:20:36 -07001533 int port_login_retry_count;
1534 int login_retry;
1535 atomic_t port_down_timer;
1536
andrew.vasquez@qlogic.comd97994d2006-01-20 14:53:13 -08001537 spinlock_t rport_lock;
1538 struct fc_rport *rport, *drport;
Andrew Vasquezad3e0ed2005-08-26 19:08:10 -07001539 u32 supported_classes;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001540} fc_port_t;
1541
1542/*
1543 * Fibre channel port/lun states.
1544 */
1545#define FCS_UNCONFIGURED 1
1546#define FCS_DEVICE_DEAD 2
1547#define FCS_DEVICE_LOST 3
1548#define FCS_ONLINE 4
1549#define FCS_NOT_SUPPORTED 5
1550#define FCS_FAILOVER 6
1551#define FCS_FAILOVER_FAILED 7
1552
1553/*
1554 * FC port flags.
1555 */
1556#define FCF_FABRIC_DEVICE BIT_0
1557#define FCF_LOGIN_NEEDED BIT_1
1558#define FCF_FO_MASKED BIT_2
1559#define FCF_FAILOVER_NEEDED BIT_3
1560#define FCF_RESET_NEEDED BIT_4
1561#define FCF_PERSISTENT_BOUND BIT_5
1562#define FCF_TAPE_PRESENT BIT_6
1563#define FCF_FARP_DONE BIT_7
1564#define FCF_FARP_FAILED BIT_8
1565#define FCF_FARP_REPLY_NEEDED BIT_9
1566#define FCF_AUTH_REQ BIT_10
1567#define FCF_SEND_AUTH_REQ BIT_11
1568#define FCF_RECEIVE_AUTH_REQ BIT_12
1569#define FCF_AUTH_SUCCESS BIT_13
1570#define FCF_RLC_SUPPORT BIT_14
1571#define FCF_CONFIG BIT_15 /* Needed? */
1572#define FCF_RESCAN_NEEDED BIT_16
1573#define FCF_XP_DEVICE BIT_17
1574#define FCF_MSA_DEVICE BIT_18
1575#define FCF_EVA_DEVICE BIT_19
1576#define FCF_MSA_PORT_ACTIVE BIT_20
1577#define FCF_FAILBACK_DISABLE BIT_21
1578#define FCF_FAILOVER_DISABLE BIT_22
1579#define FCF_DSXXX_DEVICE BIT_23
1580#define FCF_AA_EVA_DEVICE BIT_24
Andrew Vasquez3d716442005-07-06 10:30:26 -07001581#define FCF_AA_MSA_DEVICE BIT_25
Linus Torvalds1da177e2005-04-16 15:20:36 -07001582
1583/* No loop ID flag. */
1584#define FC_NO_LOOP_ID 0x1000
1585
1586/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001587 * FC-CT interface
1588 *
1589 * NOTE: All structures are big-endian in form.
1590 */
1591
1592#define CT_REJECT_RESPONSE 0x8001
1593#define CT_ACCEPT_RESPONSE 0x8002
Andrew Vasquezcca53352005-08-26 19:08:30 -07001594#define CT_REASON_CANNOT_PERFORM 0x09
1595#define CT_EXPL_ALREADY_REGISTERED 0x10
Linus Torvalds1da177e2005-04-16 15:20:36 -07001596
1597#define NS_N_PORT_TYPE 0x01
1598#define NS_NL_PORT_TYPE 0x02
1599#define NS_NX_PORT_TYPE 0x7F
1600
1601#define GA_NXT_CMD 0x100
1602#define GA_NXT_REQ_SIZE (16 + 4)
1603#define GA_NXT_RSP_SIZE (16 + 620)
1604
1605#define GID_PT_CMD 0x1A1
1606#define GID_PT_REQ_SIZE (16 + 4)
1607#define GID_PT_RSP_SIZE (16 + (MAX_FIBRE_DEVICES * 4))
1608
1609#define GPN_ID_CMD 0x112
1610#define GPN_ID_REQ_SIZE (16 + 4)
1611#define GPN_ID_RSP_SIZE (16 + 8)
1612
1613#define GNN_ID_CMD 0x113
1614#define GNN_ID_REQ_SIZE (16 + 4)
1615#define GNN_ID_RSP_SIZE (16 + 8)
1616
1617#define GFT_ID_CMD 0x117
1618#define GFT_ID_REQ_SIZE (16 + 4)
1619#define GFT_ID_RSP_SIZE (16 + 32)
1620
1621#define RFT_ID_CMD 0x217
1622#define RFT_ID_REQ_SIZE (16 + 4 + 32)
1623#define RFT_ID_RSP_SIZE 16
1624
1625#define RFF_ID_CMD 0x21F
1626#define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
1627#define RFF_ID_RSP_SIZE 16
1628
1629#define RNN_ID_CMD 0x213
1630#define RNN_ID_REQ_SIZE (16 + 4 + 8)
1631#define RNN_ID_RSP_SIZE 16
1632
1633#define RSNN_NN_CMD 0x239
1634#define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
1635#define RSNN_NN_RSP_SIZE 16
1636
Andrew Vasquezcca53352005-08-26 19:08:30 -07001637/*
1638 * HBA attribute types.
1639 */
1640#define FDMI_HBA_ATTR_COUNT 9
1641#define FDMI_HBA_NODE_NAME 1
1642#define FDMI_HBA_MANUFACTURER 2
1643#define FDMI_HBA_SERIAL_NUMBER 3
1644#define FDMI_HBA_MODEL 4
1645#define FDMI_HBA_MODEL_DESCRIPTION 5
1646#define FDMI_HBA_HARDWARE_VERSION 6
1647#define FDMI_HBA_DRIVER_VERSION 7
1648#define FDMI_HBA_OPTION_ROM_VERSION 8
1649#define FDMI_HBA_FIRMWARE_VERSION 9
1650#define FDMI_HBA_OS_NAME_AND_VERSION 0xa
1651#define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
1652
1653struct ct_fdmi_hba_attr {
1654 uint16_t type;
1655 uint16_t len;
1656 union {
1657 uint8_t node_name[WWN_SIZE];
1658 uint8_t manufacturer[32];
1659 uint8_t serial_num[8];
1660 uint8_t model[16];
1661 uint8_t model_desc[80];
1662 uint8_t hw_version[16];
1663 uint8_t driver_version[32];
1664 uint8_t orom_version[16];
1665 uint8_t fw_version[16];
1666 uint8_t os_version[128];
1667 uint8_t max_ct_len[4];
1668 } a;
1669};
1670
1671struct ct_fdmi_hba_attributes {
1672 uint32_t count;
1673 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
1674};
1675
1676/*
1677 * Port attribute types.
1678 */
1679#define FDMI_PORT_ATTR_COUNT 5
1680#define FDMI_PORT_FC4_TYPES 1
1681#define FDMI_PORT_SUPPORT_SPEED 2
1682#define FDMI_PORT_CURRENT_SPEED 3
1683#define FDMI_PORT_MAX_FRAME_SIZE 4
1684#define FDMI_PORT_OS_DEVICE_NAME 5
1685#define FDMI_PORT_HOST_NAME 6
1686
1687struct ct_fdmi_port_attr {
1688 uint16_t type;
1689 uint16_t len;
1690 union {
1691 uint8_t fc4_types[32];
1692 uint32_t sup_speed;
1693 uint32_t cur_speed;
1694 uint32_t max_frame_size;
1695 uint8_t os_dev_name[32];
1696 uint8_t host_name[32];
1697 } a;
1698};
1699
1700/*
1701 * Port Attribute Block.
1702 */
1703struct ct_fdmi_port_attributes {
1704 uint32_t count;
1705 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
1706};
1707
1708/* FDMI definitions. */
1709#define GRHL_CMD 0x100
1710#define GHAT_CMD 0x101
1711#define GRPL_CMD 0x102
1712#define GPAT_CMD 0x110
1713
1714#define RHBA_CMD 0x200
1715#define RHBA_RSP_SIZE 16
1716
1717#define RHAT_CMD 0x201
1718#define RPRT_CMD 0x210
1719
1720#define RPA_CMD 0x211
1721#define RPA_RSP_SIZE 16
1722
1723#define DHBA_CMD 0x300
1724#define DHBA_REQ_SIZE (16 + 8)
1725#define DHBA_RSP_SIZE 16
1726
1727#define DHAT_CMD 0x301
1728#define DPRT_CMD 0x310
1729#define DPA_CMD 0x311
1730
Linus Torvalds1da177e2005-04-16 15:20:36 -07001731/* CT command header -- request/response common fields */
1732struct ct_cmd_hdr {
1733 uint8_t revision;
1734 uint8_t in_id[3];
1735 uint8_t gs_type;
1736 uint8_t gs_subtype;
1737 uint8_t options;
1738 uint8_t reserved;
1739};
1740
1741/* CT command request */
1742struct ct_sns_req {
1743 struct ct_cmd_hdr header;
1744 uint16_t command;
1745 uint16_t max_rsp_size;
1746 uint8_t fragment_id;
1747 uint8_t reserved[3];
1748
1749 union {
1750 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID */
1751 struct {
1752 uint8_t reserved;
1753 uint8_t port_id[3];
1754 } port_id;
1755
1756 struct {
1757 uint8_t port_type;
1758 uint8_t domain;
1759 uint8_t area;
1760 uint8_t reserved;
1761 } gid_pt;
1762
1763 struct {
1764 uint8_t reserved;
1765 uint8_t port_id[3];
1766 uint8_t fc4_types[32];
1767 } rft_id;
1768
1769 struct {
1770 uint8_t reserved;
1771 uint8_t port_id[3];
1772 uint16_t reserved2;
1773 uint8_t fc4_feature;
1774 uint8_t fc4_type;
1775 } rff_id;
1776
1777 struct {
1778 uint8_t reserved;
1779 uint8_t port_id[3];
1780 uint8_t node_name[8];
1781 } rnn_id;
1782
1783 struct {
1784 uint8_t node_name[8];
1785 uint8_t name_len;
1786 uint8_t sym_node_name[255];
1787 } rsnn_nn;
Andrew Vasquezcca53352005-08-26 19:08:30 -07001788
1789 struct {
1790 uint8_t hba_indentifier[8];
1791 } ghat;
1792
1793 struct {
1794 uint8_t hba_identifier[8];
1795 uint32_t entry_count;
1796 uint8_t port_name[8];
1797 struct ct_fdmi_hba_attributes attrs;
1798 } rhba;
1799
1800 struct {
1801 uint8_t hba_identifier[8];
1802 struct ct_fdmi_hba_attributes attrs;
1803 } rhat;
1804
1805 struct {
1806 uint8_t port_name[8];
1807 struct ct_fdmi_port_attributes attrs;
1808 } rpa;
1809
1810 struct {
1811 uint8_t port_name[8];
1812 } dhba;
1813
1814 struct {
1815 uint8_t port_name[8];
1816 } dhat;
1817
1818 struct {
1819 uint8_t port_name[8];
1820 } dprt;
1821
1822 struct {
1823 uint8_t port_name[8];
1824 } dpa;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001825 } req;
1826};
1827
1828/* CT command response header */
1829struct ct_rsp_hdr {
1830 struct ct_cmd_hdr header;
1831 uint16_t response;
1832 uint16_t residual;
1833 uint8_t fragment_id;
1834 uint8_t reason_code;
1835 uint8_t explanation_code;
1836 uint8_t vendor_unique;
1837};
1838
1839struct ct_sns_gid_pt_data {
1840 uint8_t control_byte;
1841 uint8_t port_id[3];
1842};
1843
1844struct ct_sns_rsp {
1845 struct ct_rsp_hdr header;
1846
1847 union {
1848 struct {
1849 uint8_t port_type;
1850 uint8_t port_id[3];
1851 uint8_t port_name[8];
1852 uint8_t sym_port_name_len;
1853 uint8_t sym_port_name[255];
1854 uint8_t node_name[8];
1855 uint8_t sym_node_name_len;
1856 uint8_t sym_node_name[255];
1857 uint8_t init_proc_assoc[8];
1858 uint8_t node_ip_addr[16];
1859 uint8_t class_of_service[4];
1860 uint8_t fc4_types[32];
1861 uint8_t ip_address[16];
1862 uint8_t fabric_port_name[8];
1863 uint8_t reserved;
1864 uint8_t hard_address[3];
1865 } ga_nxt;
1866
1867 struct {
1868 struct ct_sns_gid_pt_data entries[MAX_FIBRE_DEVICES];
1869 } gid_pt;
1870
1871 struct {
1872 uint8_t port_name[8];
1873 } gpn_id;
1874
1875 struct {
1876 uint8_t node_name[8];
1877 } gnn_id;
1878
1879 struct {
1880 uint8_t fc4_types[32];
1881 } gft_id;
Andrew Vasquezcca53352005-08-26 19:08:30 -07001882
1883 struct {
1884 uint32_t entry_count;
1885 uint8_t port_name[8];
1886 struct ct_fdmi_hba_attributes attrs;
1887 } ghat;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001888 } rsp;
1889};
1890
1891struct ct_sns_pkt {
1892 union {
1893 struct ct_sns_req req;
1894 struct ct_sns_rsp rsp;
1895 } p;
1896};
1897
1898/*
1899 * SNS command structures -- for 2200 compatability.
1900 */
1901#define RFT_ID_SNS_SCMD_LEN 22
1902#define RFT_ID_SNS_CMD_SIZE 60
1903#define RFT_ID_SNS_DATA_SIZE 16
1904
1905#define RNN_ID_SNS_SCMD_LEN 10
1906#define RNN_ID_SNS_CMD_SIZE 36
1907#define RNN_ID_SNS_DATA_SIZE 16
1908
1909#define GA_NXT_SNS_SCMD_LEN 6
1910#define GA_NXT_SNS_CMD_SIZE 28
1911#define GA_NXT_SNS_DATA_SIZE (620 + 16)
1912
1913#define GID_PT_SNS_SCMD_LEN 6
1914#define GID_PT_SNS_CMD_SIZE 28
1915#define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES * 4 + 16)
1916
1917#define GPN_ID_SNS_SCMD_LEN 6
1918#define GPN_ID_SNS_CMD_SIZE 28
1919#define GPN_ID_SNS_DATA_SIZE (8 + 16)
1920
1921#define GNN_ID_SNS_SCMD_LEN 6
1922#define GNN_ID_SNS_CMD_SIZE 28
1923#define GNN_ID_SNS_DATA_SIZE (8 + 16)
1924
1925struct sns_cmd_pkt {
1926 union {
1927 struct {
1928 uint16_t buffer_length;
1929 uint16_t reserved_1;
1930 uint32_t buffer_address[2];
1931 uint16_t subcommand_length;
1932 uint16_t reserved_2;
1933 uint16_t subcommand;
1934 uint16_t size;
1935 uint32_t reserved_3;
1936 uint8_t param[36];
1937 } cmd;
1938
1939 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
1940 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
1941 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
1942 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
1943 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
1944 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
1945 } p;
1946};
1947
Andrew Vasquez54333832005-11-09 15:49:04 -08001948struct fw_blob {
1949 char *name;
1950 uint32_t segs[4];
1951 const struct firmware *fw;
1952};
1953
Linus Torvalds1da177e2005-04-16 15:20:36 -07001954/* Return data from MBC_GET_ID_LIST call. */
1955struct gid_list_info {
1956 uint8_t al_pa;
1957 uint8_t area;
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07001958 uint8_t domain;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001959 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
1960 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
Andrew Vasquez3d716442005-07-06 10:30:26 -07001961 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001962};
1963#define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES)
1964
1965/*
Andrew Vasquezabbd8872005-07-06 10:30:05 -07001966 * ISP operations
1967 */
1968struct isp_operations {
1969
1970 int (*pci_config) (struct scsi_qla_host *);
1971 void (*reset_chip) (struct scsi_qla_host *);
1972 int (*chip_diag) (struct scsi_qla_host *);
1973 void (*config_rings) (struct scsi_qla_host *);
1974 void (*reset_adapter) (struct scsi_qla_host *);
1975 int (*nvram_config) (struct scsi_qla_host *);
1976 void (*update_fw_options) (struct scsi_qla_host *);
1977 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
1978
1979 char * (*pci_info_str) (struct scsi_qla_host *, char *);
1980 char * (*fw_version_str) (struct scsi_qla_host *, char *);
1981
1982 irqreturn_t (*intr_handler) (int, void *, struct pt_regs *);
1983 void (*enable_intrs) (struct scsi_qla_host *);
1984 void (*disable_intrs) (struct scsi_qla_host *);
1985
1986 int (*abort_command) (struct scsi_qla_host *, srb_t *);
1987 int (*abort_target) (struct fc_port *);
1988 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
1989 uint8_t, uint8_t, uint16_t *, uint8_t);
Andrew Vasquez1c7c6352005-07-06 10:30:57 -07001990 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
1991 uint8_t, uint8_t);
Andrew Vasquezabbd8872005-07-06 10:30:05 -07001992
1993 uint16_t (*calc_req_entries) (uint16_t);
1994 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
Andrew Vasquez8c958a92005-07-06 10:30:47 -07001995 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t);
Andrew Vasquezcca53352005-08-26 19:08:30 -07001996 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
1997 uint32_t);
Andrew Vasquezabbd8872005-07-06 10:30:05 -07001998
1999 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *,
2000 uint32_t, uint32_t);
2001 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
2002 uint32_t);
2003
2004 void (*fw_dump) (struct scsi_qla_host *, int);
andrew.vasquez@qlogic.comf6df1442006-01-31 16:05:07 -08002005
2006 int (*beacon_on) (struct scsi_qla_host *);
2007 int (*beacon_off) (struct scsi_qla_host *);
2008 void (*beacon_blink) (struct scsi_qla_host *);
andrew.vasquez@qlogic.com854165f2006-01-31 16:05:17 -08002009
2010 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *,
2011 uint32_t, uint32_t);
2012 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t,
2013 uint32_t);
Andrew Vasquezabbd8872005-07-06 10:30:05 -07002014};
2015
2016/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002017 * Linux Host Adapter structure
2018 */
2019typedef struct scsi_qla_host {
2020 struct list_head list;
2021
2022 /* Commonly used flags and state information. */
2023 struct Scsi_Host *host;
2024 struct pci_dev *pdev;
2025
2026 unsigned long host_no;
2027 unsigned long instance;
2028
2029 volatile struct {
2030 uint32_t init_done :1;
2031 uint32_t online :1;
2032 uint32_t mbox_int :1;
2033 uint32_t mbox_busy :1;
2034 uint32_t rscn_queue_overflow :1;
2035 uint32_t reset_active :1;
2036
2037 uint32_t management_server_logged_in :1;
2038 uint32_t process_response_queue :1;
2039
2040 uint32_t disable_risc_code_load :1;
2041 uint32_t enable_64bit_addressing :1;
2042 uint32_t enable_lip_reset :1;
2043 uint32_t enable_lip_full_login :1;
2044 uint32_t enable_target_reset :1;
2045 uint32_t enable_led_scheme :1;
Andrew Vasquez3d716442005-07-06 10:30:26 -07002046 uint32_t msi_enabled :1;
2047 uint32_t msix_enabled :1;
Andrew Vasquezd4c760c2006-06-23 16:10:39 -07002048 uint32_t disable_serdes :1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002049 } flags;
2050
2051 atomic_t loop_state;
2052#define LOOP_TIMEOUT 1
2053#define LOOP_DOWN 2
2054#define LOOP_UP 3
2055#define LOOP_UPDATE 4
2056#define LOOP_READY 5
2057#define LOOP_DEAD 6
2058
2059 unsigned long dpc_flags;
2060#define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
2061#define RESET_ACTIVE 1
2062#define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
2063#define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
2064#define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
2065#define LOOP_RESYNC_ACTIVE 5
2066#define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
2067#define RSCN_UPDATE 7 /* Perform an RSCN update. */
2068#define MAILBOX_RETRY 8
2069#define ISP_RESET_NEEDED 9 /* Initiate a ISP reset. */
2070#define FAILOVER_EVENT_NEEDED 10
2071#define FAILOVER_EVENT 11
2072#define FAILOVER_NEEDED 12
2073#define SCSI_RESTART_NEEDED 13 /* Processes SCSI retry queue. */
2074#define PORT_RESTART_NEEDED 14 /* Processes Retry queue. */
2075#define RESTART_QUEUES_NEEDED 15 /* Restarts the Lun queue. */
2076#define ABORT_QUEUES_NEEDED 16
2077#define RELOGIN_NEEDED 17
2078#define LOGIN_RETRY_NEEDED 18 /* Initiate required fabric logins. */
2079#define REGISTER_FC4_NEEDED 19 /* SNS FC4 registration required. */
2080#define ISP_ABORT_RETRY 20 /* ISP aborted. */
2081#define FCPORT_RESCAN_NEEDED 21 /* IO descriptor processing needed */
2082#define IODESC_PROCESS_NEEDED 22 /* IO descriptor processing needed */
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07002083#define IOCTL_ERROR_RECOVERY 23
Linus Torvalds1da177e2005-04-16 15:20:36 -07002084#define LOOP_RESET_NEEDED 24
Andrew Vasquez3d716442005-07-06 10:30:26 -07002085#define BEACON_BLINK_NEEDED 25
Andrew Vasquezcca53352005-08-26 19:08:30 -07002086#define REGISTER_FDMI_NEEDED 26
andrew.vasquez@qlogic.comd97994d2006-01-20 14:53:13 -08002087#define FCPORT_UPDATE_NEEDED 27
Linus Torvalds1da177e2005-04-16 15:20:36 -07002088
2089 uint32_t device_flags;
2090#define DFLG_LOCAL_DEVICES BIT_0
2091#define DFLG_RETRY_LOCAL_DEVICES BIT_1
2092#define DFLG_FABRIC_DEVICES BIT_2
2093#define SWITCH_FOUND BIT_3
2094#define DFLG_NO_CABLE BIT_4
2095
andrew.vasquez@qlogic.comea5b6382006-03-09 14:27:08 -08002096 uint32_t device_type;
2097#define DT_ISP2100 BIT_0
2098#define DT_ISP2200 BIT_1
2099#define DT_ISP2300 BIT_2
2100#define DT_ISP2312 BIT_3
2101#define DT_ISP2322 BIT_4
2102#define DT_ISP6312 BIT_5
2103#define DT_ISP6322 BIT_6
2104#define DT_ISP2422 BIT_7
2105#define DT_ISP2432 BIT_8
andrew.vasquez@qlogic.com044cc6c2006-03-09 14:27:13 -08002106#define DT_ISP5422 BIT_9
2107#define DT_ISP5432 BIT_10
2108#define DT_ISP_LAST (DT_ISP5432 << 1)
andrew.vasquez@qlogic.comea5b6382006-03-09 14:27:08 -08002109
andrew.vasquez@qlogic.com4a59f712006-03-09 14:27:39 -08002110#define DT_ZIO_SUPPORTED BIT_28
andrew.vasquez@qlogic.comea5b6382006-03-09 14:27:08 -08002111#define DT_OEM_001 BIT_29
2112#define DT_ISP2200A BIT_30
2113#define DT_EXTENDED_IDS BIT_31
2114
2115#define DT_MASK(ha) ((ha)->device_type & (DT_ISP_LAST - 1))
2116#define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
2117#define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
2118#define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
2119#define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
2120#define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
2121#define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
2122#define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
2123#define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
2124#define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
andrew.vasquez@qlogic.com044cc6c2006-03-09 14:27:13 -08002125#define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
2126#define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
andrew.vasquez@qlogic.comea5b6382006-03-09 14:27:08 -08002127
2128#define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
2129 IS_QLA6312(ha) || IS_QLA6322(ha))
2130#define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
andrew.vasquez@qlogic.com044cc6c2006-03-09 14:27:13 -08002131#define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
andrew.vasquez@qlogic.comea5b6382006-03-09 14:27:08 -08002132
andrew.vasquez@qlogic.com4a59f712006-03-09 14:27:39 -08002133#define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
andrew.vasquez@qlogic.comea5b6382006-03-09 14:27:08 -08002134#define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
2135#define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
2136
Linus Torvalds1da177e2005-04-16 15:20:36 -07002137 /* SRB cache. */
2138#define SRB_MIN_REQ 128
2139 mempool_t *srb_mempool;
2140
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07002141 /* This spinlock is used to protect "io transactions", you must
Linus Torvalds1da177e2005-04-16 15:20:36 -07002142 * aquire it before doing any IO to the card, eg with RD_REG*() and
2143 * WRT_REG*() for the duration of your entire commandtransaction.
2144 *
2145 * This spinlock is of lower priority than the io request lock.
2146 */
2147
2148 spinlock_t hardware_lock ____cacheline_aligned;
2149
2150 device_reg_t __iomem *iobase; /* Base I/O address */
2151 unsigned long pio_address;
2152 unsigned long pio_length;
2153#define MIN_IOBASE_LEN 0x100
2154
2155 /* ISP ring lock, rings, and indexes */
2156 dma_addr_t request_dma; /* Physical address. */
2157 request_t *request_ring; /* Base virtual address */
2158 request_t *request_ring_ptr; /* Current address. */
2159 uint16_t req_ring_index; /* Current index. */
2160 uint16_t req_q_cnt; /* Number of available entries. */
2161 uint16_t request_q_length;
2162
2163 dma_addr_t response_dma; /* Physical address. */
2164 response_t *response_ring; /* Base virtual address */
2165 response_t *response_ring_ptr; /* Current address. */
2166 uint16_t rsp_ring_index; /* Current index. */
2167 uint16_t response_q_length;
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07002168
Andrew Vasquezabbd8872005-07-06 10:30:05 -07002169 struct isp_operations isp_ops;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002170
2171 /* Outstandings ISP commands. */
2172 srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07002173 uint32_t current_outstanding_cmd;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002174 srb_t *status_srb; /* Status continuation entry. */
2175
Linus Torvalds1da177e2005-04-16 15:20:36 -07002176 /* ISP configuration data. */
2177 uint16_t loop_id; /* Host adapter loop id */
2178 uint16_t fb_rev;
2179
2180 port_id_t d_id; /* Host adapter port id */
2181 uint16_t max_public_loop_ids;
2182 uint16_t min_external_loopid; /* First external loop Id */
2183
2184 uint16_t link_data_rate; /* F/W operating speed */
andrew.vasquez@qlogic.com04414012006-01-31 16:04:51 -08002185#define LDR_1GB 0
2186#define LDR_2GB 1
2187#define LDR_4GB 3
2188#define LDR_UNKNOWN 0xFFFF
Linus Torvalds1da177e2005-04-16 15:20:36 -07002189
2190 uint8_t current_topology;
2191 uint8_t prev_topology;
2192#define ISP_CFG_NL 1
2193#define ISP_CFG_N 2
2194#define ISP_CFG_FL 4
2195#define ISP_CFG_F 8
2196
2197 uint8_t operating_mode; /* F/W operating mode */
2198#define LOOP 0
2199#define P2P 1
2200#define LOOP_P2P 2
2201#define P2P_LOOP 3
2202
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07002203 uint8_t marker_needed;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002204
2205 uint8_t interrupts_on;
2206
2207 /* HBA serial number */
2208 uint8_t serial0;
2209 uint8_t serial1;
2210 uint8_t serial2;
2211
2212 /* NVRAM configuration data */
Andrew Vasquez3d716442005-07-06 10:30:26 -07002213 uint16_t nvram_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002214 uint16_t nvram_base;
andrew.vasquez@qlogic.com6f641792006-03-09 14:27:34 -08002215 uint16_t vpd_size;
2216 uint16_t vpd_base;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002217
2218 uint16_t loop_reset_delay;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002219 uint8_t retry_count;
2220 uint8_t login_timeout;
2221 uint16_t r_a_tov;
2222 int port_down_retry_count;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002223 uint8_t mbx_count;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002224 uint16_t last_loop_id;
Andrew Vasquezcca53352005-08-26 19:08:30 -07002225 uint16_t mgmt_svr_loop_id;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002226
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07002227 uint32_t login_retry_count;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002228
2229 /* Fibre Channel Device List. */
2230 struct list_head fcports;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002231
Linus Torvalds1da177e2005-04-16 15:20:36 -07002232 /* RSCN queue. */
2233 uint32_t rscn_queue[MAX_RSCN_COUNT];
2234 uint8_t rscn_in_ptr;
2235 uint8_t rscn_out_ptr;
2236
2237 /* SNS command interfaces. */
2238 ms_iocb_entry_t *ms_iocb;
2239 dma_addr_t ms_iocb_dma;
2240 struct ct_sns_pkt *ct_sns;
2241 dma_addr_t ct_sns_dma;
2242 /* SNS command interfaces for 2200. */
2243 struct sns_cmd_pkt *sns_cmd;
2244 dma_addr_t sns_cmd_dma;
2245
Andrew Vasquez88729e52006-06-23 16:10:50 -07002246#define SFP_DEV_SIZE 256
2247#define SFP_BLOCK_SIZE 64
2248 void *sfp_data;
2249 dma_addr_t sfp_data_dma;
2250
Christoph Hellwig39a11242006-02-14 18:46:22 +01002251 struct task_struct *dpc_thread;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002252 uint8_t dpc_active; /* DPC routine is active */
2253
2254 /* Timeout timers. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002255 uint8_t loop_down_abort_time; /* port down timer */
2256 atomic_t loop_down_timer; /* loop down timer */
2257 uint8_t link_down_timeout; /* link down timeout */
2258
2259 uint32_t timer_active;
2260 struct timer_list timer;
2261
2262 dma_addr_t gid_list_dma;
2263 struct gid_list_info *gid_list;
Andrew Vasquezabbd8872005-07-06 10:30:05 -07002264 int gid_list_info_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002265
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07002266 /* Small DMA pool allocations -- maximum 256 bytes in length. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002267#define DMA_POOL_SIZE 256
2268 struct dma_pool *s_dma_pool;
2269
2270 dma_addr_t init_cb_dma;
Andrew Vasquez3d716442005-07-06 10:30:26 -07002271 init_cb_t *init_cb;
2272 int init_cb_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002273
Linus Torvalds1da177e2005-04-16 15:20:36 -07002274 /* These are used by mailbox operations. */
2275 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
2276
2277 mbx_cmd_t *mcp;
2278 unsigned long mbx_cmd_flags;
2279#define MBX_INTERRUPT 1
2280#define MBX_INTR_WAIT 2
2281#define MBX_UPDATE_FLASH_ACTIVE 3
2282
2283 spinlock_t mbx_reg_lock; /* Mbx Cmd Register Lock */
2284
2285 struct semaphore mbx_cmd_sem; /* Serialialize mbx access */
2286 struct semaphore mbx_intr_sem; /* Used for completion notification */
2287
2288 uint32_t mbx_flags;
2289#define MBX_IN_PROGRESS BIT_0
2290#define MBX_BUSY BIT_1 /* Got the Access */
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07002291#define MBX_SLEEPING_ON_SEM BIT_2
Linus Torvalds1da177e2005-04-16 15:20:36 -07002292#define MBX_POLLING_FOR_COMP BIT_3
2293#define MBX_COMPLETED BIT_4
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07002294#define MBX_TIMEDOUT BIT_5
Linus Torvalds1da177e2005-04-16 15:20:36 -07002295#define MBX_ACCESS_TIMEDOUT BIT_6
2296
2297 mbx_cmd_t mc;
2298
Linus Torvalds1da177e2005-04-16 15:20:36 -07002299 /* Basic firmware related information. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002300 uint16_t fw_major_version;
2301 uint16_t fw_minor_version;
2302 uint16_t fw_subminor_version;
2303 uint16_t fw_attributes;
2304 uint32_t fw_memory_size;
2305 uint32_t fw_transfer_size;
Andrew Vasquez441d1072006-05-17 15:09:34 -07002306 uint32_t fw_srisc_address;
2307#define RISC_START_ADDRESS_2100 0x1000
2308#define RISC_START_ADDRESS_2300 0x800
2309#define RISC_START_ADDRESS_2400 0x100000
Linus Torvalds1da177e2005-04-16 15:20:36 -07002310
2311 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
2312 uint8_t fw_seriallink_options[4];
Andrew Vasquez3d716442005-07-06 10:30:26 -07002313 uint16_t fw_seriallink_options24[4];
Linus Torvalds1da177e2005-04-16 15:20:36 -07002314
2315 /* Firmware dump information. */
Andrew Vasqueza7a167b2006-06-23 16:10:29 -07002316 struct qla2xxx_fw_dump *fw_dump;
2317 uint32_t fw_dump_len;
Andrew Vasquezd4e3e042006-05-17 15:09:50 -07002318 int fw_dumped;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002319 int fw_dump_reading;
Andrew Vasqueza7a167b2006-06-23 16:10:29 -07002320 dma_addr_t eft_dma;
2321 void *eft;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002322
2323 uint8_t host_str[16];
Andrew Vasquez3d716442005-07-06 10:30:26 -07002324 uint32_t pci_attr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002325
2326 uint16_t product_id[4];
2327
2328 uint8_t model_number[16+1];
2329#define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
2330 char *model_desc;
Andrew Vasquezcca53352005-08-26 19:08:30 -07002331 uint8_t adapter_id[16+1];
Linus Torvalds1da177e2005-04-16 15:20:36 -07002332
Andrew Vasquez3d716442005-07-06 10:30:26 -07002333 uint8_t *node_name;
2334 uint8_t *port_name;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002335 uint32_t isp_abort_cnt;
2336
andrew.vasquez@qlogic.com854165f2006-01-31 16:05:17 -08002337 /* Option ROM information. */
2338 char *optrom_buffer;
2339 uint32_t optrom_size;
2340 int optrom_state;
2341#define QLA_SWAITING 0
2342#define QLA_SREADING 1
2343#define QLA_SWRITING 2
2344
Linus Torvalds1da177e2005-04-16 15:20:36 -07002345 /* Needed for BEACON */
2346 uint16_t beacon_blink_led;
andrew.vasquez@qlogic.comf6df1442006-01-31 16:05:07 -08002347 uint8_t beacon_color_state;
2348#define QLA_LED_GRN_ON 0x01
2349#define QLA_LED_YLW_ON 0x02
2350#define QLA_LED_ABR_ON 0x04
2351#define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */
2352 /* ISP2322: red, green, amber. */
Andrew Vasquez4fdfefe2005-10-27 11:09:48 -07002353
2354 uint16_t zio_mode;
2355 uint16_t zio_timer;
andrew.vasquez@qlogic.com392e2f62006-01-31 16:05:02 -08002356 struct fc_host_statistics fc_host_stat;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002357} scsi_qla_host_t;
2358
2359
2360/*
2361 * Macros to help code, maintain, etc.
2362 */
2363#define LOOP_TRANSITION(ha) \
2364 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
Andrew Vasquez23443b12005-12-06 10:57:06 -08002365 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
Linus Torvalds1da177e2005-04-16 15:20:36 -07002366 atomic_read(&ha->loop_state) == LOOP_DOWN)
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07002367
Linus Torvalds1da177e2005-04-16 15:20:36 -07002368#define to_qla_host(x) ((scsi_qla_host_t *) (x)->hostdata)
2369
2370#define qla_printk(level, ha, format, arg...) \
2371 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
2372
2373/*
2374 * qla2x00 local function return status codes
2375 */
2376#define MBS_MASK 0x3fff
2377
2378#define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
2379#define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
2380#define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
2381#define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
2382#define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
2383#define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
2384#define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
2385#define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
2386#define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
2387#define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
2388
2389#define QLA_FUNCTION_TIMEOUT 0x100
2390#define QLA_FUNCTION_PARAMETER_ERROR 0x101
2391#define QLA_FUNCTION_FAILED 0x102
2392#define QLA_MEMORY_ALLOC_FAILED 0x103
2393#define QLA_LOCK_TIMEOUT 0x104
2394#define QLA_ABORTED 0x105
2395#define QLA_SUSPENDED 0x106
2396#define QLA_BUSY 0x107
2397#define QLA_RSCNS_HANDLED 0x108
Andrew Vasquezcca53352005-08-26 19:08:30 -07002398#define QLA_ALREADY_REGISTERED 0x109
Linus Torvalds1da177e2005-04-16 15:20:36 -07002399
Linus Torvalds1da177e2005-04-16 15:20:36 -07002400#define NVRAM_DELAY() udelay(10)
2401
2402#define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1)
2403
2404/*
2405 * Flash support definitions
2406 */
andrew.vasquez@qlogic.com854165f2006-01-31 16:05:17 -08002407#define OPTROM_SIZE_2300 0x20000
2408#define OPTROM_SIZE_2322 0x100000
2409#define OPTROM_SIZE_24XX 0x100000
Linus Torvalds1da177e2005-04-16 15:20:36 -07002410
2411#include "qla_gbl.h"
2412#include "qla_dbg.h"
2413#include "qla_inline.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -07002414
Linus Torvalds1da177e2005-04-16 15:20:36 -07002415#define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
2416#define CMD_COMPL_STATUS(Cmnd) ((Cmnd)->SCp.this_residual)
2417#define CMD_RESID_LEN(Cmnd) ((Cmnd)->SCp.buffers_residual)
2418#define CMD_SCSI_STATUS(Cmnd) ((Cmnd)->SCp.Status)
2419#define CMD_ACTUAL_SNSLEN(Cmnd) ((Cmnd)->SCp.Message)
2420#define CMD_ENTRY_STATUS(Cmnd) ((Cmnd)->SCp.have_data_in)
2421
2422#endif