Divy Le Ray | 4d22de3 | 2007-01-18 22:04:14 -0500 | [diff] [blame] | 1 | /* |
Divy Le Ray | 1d68e93 | 2007-01-30 19:44:35 -0800 | [diff] [blame] | 2 | * Copyright (c) 2005-2007 Chelsio, Inc. All rights reserved. |
Divy Le Ray | 4d22de3 | 2007-01-18 22:04:14 -0500 | [diff] [blame] | 3 | * |
Divy Le Ray | 1d68e93 | 2007-01-30 19:44:35 -0800 | [diff] [blame] | 4 | * This software is available to you under a choice of one of two |
| 5 | * licenses. You may choose to be licensed under the terms of the GNU |
| 6 | * General Public License (GPL) Version 2, available from the file |
| 7 | * COPYING in the main directory of this source tree, or the |
| 8 | * OpenIB.org BSD license below: |
Divy Le Ray | 4d22de3 | 2007-01-18 22:04:14 -0500 | [diff] [blame] | 9 | * |
Divy Le Ray | 1d68e93 | 2007-01-30 19:44:35 -0800 | [diff] [blame] | 10 | * Redistribution and use in source and binary forms, with or |
| 11 | * without modification, are permitted provided that the following |
| 12 | * conditions are met: |
| 13 | * |
| 14 | * - Redistributions of source code must retain the above |
| 15 | * copyright notice, this list of conditions and the following |
| 16 | * disclaimer. |
| 17 | * |
| 18 | * - Redistributions in binary form must reproduce the above |
| 19 | * copyright notice, this list of conditions and the following |
| 20 | * disclaimer in the documentation and/or other materials |
| 21 | * provided with the distribution. |
| 22 | * |
| 23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
| 27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
| 28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| 29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 30 | * SOFTWARE. |
Divy Le Ray | 4d22de3 | 2007-01-18 22:04:14 -0500 | [diff] [blame] | 31 | */ |
Divy Le Ray | 4d22de3 | 2007-01-18 22:04:14 -0500 | [diff] [blame] | 32 | #ifndef __CHELSIO_COMMON_H |
| 33 | #define __CHELSIO_COMMON_H |
| 34 | |
| 35 | #include <linux/kernel.h> |
| 36 | #include <linux/types.h> |
| 37 | #include <linux/ctype.h> |
| 38 | #include <linux/delay.h> |
| 39 | #include <linux/init.h> |
| 40 | #include <linux/netdevice.h> |
| 41 | #include <linux/ethtool.h> |
| 42 | #include <linux/mii.h> |
| 43 | #include "version.h" |
| 44 | |
| 45 | #define CH_ERR(adap, fmt, ...) dev_err(&adap->pdev->dev, fmt, ## __VA_ARGS__) |
| 46 | #define CH_WARN(adap, fmt, ...) dev_warn(&adap->pdev->dev, fmt, ## __VA_ARGS__) |
| 47 | #define CH_ALERT(adap, fmt, ...) \ |
| 48 | dev_printk(KERN_ALERT, &adap->pdev->dev, fmt, ## __VA_ARGS__) |
| 49 | |
| 50 | /* |
| 51 | * More powerful macro that selectively prints messages based on msg_enable. |
| 52 | * For info and debugging messages. |
| 53 | */ |
| 54 | #define CH_MSG(adapter, level, category, fmt, ...) do { \ |
| 55 | if ((adapter)->msg_enable & NETIF_MSG_##category) \ |
| 56 | dev_printk(KERN_##level, &adapter->pdev->dev, fmt, \ |
| 57 | ## __VA_ARGS__); \ |
| 58 | } while (0) |
| 59 | |
| 60 | #ifdef DEBUG |
| 61 | # define CH_DBG(adapter, category, fmt, ...) \ |
| 62 | CH_MSG(adapter, DEBUG, category, fmt, ## __VA_ARGS__) |
| 63 | #else |
| 64 | # define CH_DBG(adapter, category, fmt, ...) |
| 65 | #endif |
| 66 | |
| 67 | /* Additional NETIF_MSG_* categories */ |
| 68 | #define NETIF_MSG_MMIO 0x8000000 |
| 69 | |
| 70 | struct t3_rx_mode { |
| 71 | struct net_device *dev; |
| 72 | struct dev_mc_list *mclist; |
| 73 | unsigned int idx; |
| 74 | }; |
| 75 | |
| 76 | static inline void init_rx_mode(struct t3_rx_mode *p, struct net_device *dev, |
| 77 | struct dev_mc_list *mclist) |
| 78 | { |
| 79 | p->dev = dev; |
| 80 | p->mclist = mclist; |
| 81 | p->idx = 0; |
| 82 | } |
| 83 | |
| 84 | static inline u8 *t3_get_next_mcaddr(struct t3_rx_mode *rm) |
| 85 | { |
| 86 | u8 *addr = NULL; |
| 87 | |
| 88 | if (rm->mclist && rm->idx < rm->dev->mc_count) { |
| 89 | addr = rm->mclist->dmi_addr; |
| 90 | rm->mclist = rm->mclist->next; |
| 91 | rm->idx++; |
| 92 | } |
| 93 | return addr; |
| 94 | } |
| 95 | |
| 96 | enum { |
| 97 | MAX_NPORTS = 2, /* max # of ports */ |
| 98 | MAX_FRAME_SIZE = 10240, /* max MAC frame size, including header + FCS */ |
| 99 | EEPROMSIZE = 8192, /* Serial EEPROM size */ |
| 100 | RSS_TABLE_SIZE = 64, /* size of RSS lookup and mapping tables */ |
| 101 | TCB_SIZE = 128, /* TCB size */ |
| 102 | NMTUS = 16, /* size of MTU table */ |
| 103 | NCCTRL_WIN = 32, /* # of congestion control windows */ |
| 104 | }; |
| 105 | |
| 106 | #define MAX_RX_COALESCING_LEN 16224U |
| 107 | |
| 108 | enum { |
| 109 | PAUSE_RX = 1 << 0, |
| 110 | PAUSE_TX = 1 << 1, |
| 111 | PAUSE_AUTONEG = 1 << 2 |
| 112 | }; |
| 113 | |
| 114 | enum { |
| 115 | SUPPORTED_OFFLOAD = 1 << 24, |
| 116 | SUPPORTED_IRQ = 1 << 25 |
| 117 | }; |
| 118 | |
| 119 | enum { /* adapter interrupt-maintained statistics */ |
| 120 | STAT_ULP_CH0_PBL_OOB, |
| 121 | STAT_ULP_CH1_PBL_OOB, |
| 122 | STAT_PCI_CORR_ECC, |
| 123 | |
| 124 | IRQ_NUM_STATS /* keep last */ |
| 125 | }; |
| 126 | |
| 127 | enum { |
| 128 | SGE_QSETS = 8, /* # of SGE Tx/Rx/RspQ sets */ |
| 129 | SGE_RXQ_PER_SET = 2, /* # of Rx queues per set */ |
| 130 | SGE_TXQ_PER_SET = 3 /* # of Tx queues per set */ |
| 131 | }; |
| 132 | |
| 133 | enum sge_context_type { /* SGE egress context types */ |
| 134 | SGE_CNTXT_RDMA = 0, |
| 135 | SGE_CNTXT_ETH = 2, |
| 136 | SGE_CNTXT_OFLD = 4, |
| 137 | SGE_CNTXT_CTRL = 5 |
| 138 | }; |
| 139 | |
| 140 | enum { |
| 141 | AN_PKT_SIZE = 32, /* async notification packet size */ |
| 142 | IMMED_PKT_SIZE = 48 /* packet size for immediate data */ |
| 143 | }; |
| 144 | |
| 145 | struct sg_ent { /* SGE scatter/gather entry */ |
| 146 | u32 len[2]; |
| 147 | u64 addr[2]; |
| 148 | }; |
| 149 | |
| 150 | #ifndef SGE_NUM_GENBITS |
| 151 | /* Must be 1 or 2 */ |
| 152 | # define SGE_NUM_GENBITS 2 |
| 153 | #endif |
| 154 | |
| 155 | #define TX_DESC_FLITS 16U |
| 156 | #define WR_FLITS (TX_DESC_FLITS + 1 - SGE_NUM_GENBITS) |
| 157 | |
| 158 | struct cphy; |
| 159 | struct adapter; |
| 160 | |
| 161 | struct mdio_ops { |
| 162 | int (*read)(struct adapter *adapter, int phy_addr, int mmd_addr, |
| 163 | int reg_addr, unsigned int *val); |
| 164 | int (*write)(struct adapter *adapter, int phy_addr, int mmd_addr, |
| 165 | int reg_addr, unsigned int val); |
| 166 | }; |
| 167 | |
| 168 | struct adapter_info { |
| 169 | unsigned char nports; /* # of ports */ |
| 170 | unsigned char phy_base_addr; /* MDIO PHY base address */ |
| 171 | unsigned char mdien; |
| 172 | unsigned char mdiinv; |
| 173 | unsigned int gpio_out; /* GPIO output settings */ |
| 174 | unsigned int gpio_intr; /* GPIO IRQ enable mask */ |
| 175 | unsigned long caps; /* adapter capabilities */ |
| 176 | const struct mdio_ops *mdio_ops; /* MDIO operations */ |
| 177 | const char *desc; /* product description */ |
| 178 | }; |
| 179 | |
| 180 | struct port_type_info { |
| 181 | void (*phy_prep)(struct cphy *phy, struct adapter *adapter, |
| 182 | int phy_addr, const struct mdio_ops *ops); |
| 183 | unsigned int caps; |
| 184 | const char *desc; |
| 185 | }; |
| 186 | |
| 187 | struct mc5_stats { |
| 188 | unsigned long parity_err; |
| 189 | unsigned long active_rgn_full; |
| 190 | unsigned long nfa_srch_err; |
| 191 | unsigned long unknown_cmd; |
| 192 | unsigned long reqq_parity_err; |
| 193 | unsigned long dispq_parity_err; |
| 194 | unsigned long del_act_empty; |
| 195 | }; |
| 196 | |
| 197 | struct mc7_stats { |
| 198 | unsigned long corr_err; |
| 199 | unsigned long uncorr_err; |
| 200 | unsigned long parity_err; |
| 201 | unsigned long addr_err; |
| 202 | }; |
| 203 | |
| 204 | struct mac_stats { |
| 205 | u64 tx_octets; /* total # of octets in good frames */ |
| 206 | u64 tx_octets_bad; /* total # of octets in error frames */ |
| 207 | u64 tx_frames; /* all good frames */ |
| 208 | u64 tx_mcast_frames; /* good multicast frames */ |
| 209 | u64 tx_bcast_frames; /* good broadcast frames */ |
| 210 | u64 tx_pause; /* # of transmitted pause frames */ |
| 211 | u64 tx_deferred; /* frames with deferred transmissions */ |
| 212 | u64 tx_late_collisions; /* # of late collisions */ |
| 213 | u64 tx_total_collisions; /* # of total collisions */ |
| 214 | u64 tx_excess_collisions; /* frame errors from excessive collissions */ |
| 215 | u64 tx_underrun; /* # of Tx FIFO underruns */ |
| 216 | u64 tx_len_errs; /* # of Tx length errors */ |
| 217 | u64 tx_mac_internal_errs; /* # of internal MAC errors on Tx */ |
| 218 | u64 tx_excess_deferral; /* # of frames with excessive deferral */ |
| 219 | u64 tx_fcs_errs; /* # of frames with bad FCS */ |
| 220 | |
| 221 | u64 tx_frames_64; /* # of Tx frames in a particular range */ |
| 222 | u64 tx_frames_65_127; |
| 223 | u64 tx_frames_128_255; |
| 224 | u64 tx_frames_256_511; |
| 225 | u64 tx_frames_512_1023; |
| 226 | u64 tx_frames_1024_1518; |
| 227 | u64 tx_frames_1519_max; |
| 228 | |
| 229 | u64 rx_octets; /* total # of octets in good frames */ |
| 230 | u64 rx_octets_bad; /* total # of octets in error frames */ |
| 231 | u64 rx_frames; /* all good frames */ |
| 232 | u64 rx_mcast_frames; /* good multicast frames */ |
| 233 | u64 rx_bcast_frames; /* good broadcast frames */ |
| 234 | u64 rx_pause; /* # of received pause frames */ |
| 235 | u64 rx_fcs_errs; /* # of received frames with bad FCS */ |
| 236 | u64 rx_align_errs; /* alignment errors */ |
| 237 | u64 rx_symbol_errs; /* symbol errors */ |
| 238 | u64 rx_data_errs; /* data errors */ |
| 239 | u64 rx_sequence_errs; /* sequence errors */ |
| 240 | u64 rx_runt; /* # of runt frames */ |
| 241 | u64 rx_jabber; /* # of jabber frames */ |
| 242 | u64 rx_short; /* # of short frames */ |
| 243 | u64 rx_too_long; /* # of oversized frames */ |
| 244 | u64 rx_mac_internal_errs; /* # of internal MAC errors on Rx */ |
| 245 | |
| 246 | u64 rx_frames_64; /* # of Rx frames in a particular range */ |
| 247 | u64 rx_frames_65_127; |
| 248 | u64 rx_frames_128_255; |
| 249 | u64 rx_frames_256_511; |
| 250 | u64 rx_frames_512_1023; |
| 251 | u64 rx_frames_1024_1518; |
| 252 | u64 rx_frames_1519_max; |
| 253 | |
| 254 | u64 rx_cong_drops; /* # of Rx drops due to SGE congestion */ |
| 255 | |
| 256 | unsigned long tx_fifo_parity_err; |
| 257 | unsigned long rx_fifo_parity_err; |
| 258 | unsigned long tx_fifo_urun; |
| 259 | unsigned long rx_fifo_ovfl; |
| 260 | unsigned long serdes_signal_loss; |
| 261 | unsigned long xaui_pcs_ctc_err; |
| 262 | unsigned long xaui_pcs_align_change; |
Divy Le Ray | fc90664 | 2007-03-18 13:10:12 -0700 | [diff] [blame] | 263 | |
| 264 | unsigned long num_toggled; /* # times toggled TxEn due to stuck TX */ |
| 265 | unsigned long num_resets; /* # times reset due to stuck TX */ |
| 266 | |
Divy Le Ray | 4d22de3 | 2007-01-18 22:04:14 -0500 | [diff] [blame] | 267 | }; |
| 268 | |
| 269 | struct tp_mib_stats { |
| 270 | u32 ipInReceive_hi; |
| 271 | u32 ipInReceive_lo; |
| 272 | u32 ipInHdrErrors_hi; |
| 273 | u32 ipInHdrErrors_lo; |
| 274 | u32 ipInAddrErrors_hi; |
| 275 | u32 ipInAddrErrors_lo; |
| 276 | u32 ipInUnknownProtos_hi; |
| 277 | u32 ipInUnknownProtos_lo; |
| 278 | u32 ipInDiscards_hi; |
| 279 | u32 ipInDiscards_lo; |
| 280 | u32 ipInDelivers_hi; |
| 281 | u32 ipInDelivers_lo; |
| 282 | u32 ipOutRequests_hi; |
| 283 | u32 ipOutRequests_lo; |
| 284 | u32 ipOutDiscards_hi; |
| 285 | u32 ipOutDiscards_lo; |
| 286 | u32 ipOutNoRoutes_hi; |
| 287 | u32 ipOutNoRoutes_lo; |
| 288 | u32 ipReasmTimeout; |
| 289 | u32 ipReasmReqds; |
| 290 | u32 ipReasmOKs; |
| 291 | u32 ipReasmFails; |
| 292 | |
| 293 | u32 reserved[8]; |
| 294 | |
| 295 | u32 tcpActiveOpens; |
| 296 | u32 tcpPassiveOpens; |
| 297 | u32 tcpAttemptFails; |
| 298 | u32 tcpEstabResets; |
| 299 | u32 tcpOutRsts; |
| 300 | u32 tcpCurrEstab; |
| 301 | u32 tcpInSegs_hi; |
| 302 | u32 tcpInSegs_lo; |
| 303 | u32 tcpOutSegs_hi; |
| 304 | u32 tcpOutSegs_lo; |
| 305 | u32 tcpRetransSeg_hi; |
| 306 | u32 tcpRetransSeg_lo; |
| 307 | u32 tcpInErrs_hi; |
| 308 | u32 tcpInErrs_lo; |
| 309 | u32 tcpRtoMin; |
| 310 | u32 tcpRtoMax; |
| 311 | }; |
| 312 | |
| 313 | struct tp_params { |
| 314 | unsigned int nchan; /* # of channels */ |
| 315 | unsigned int pmrx_size; /* total PMRX capacity */ |
| 316 | unsigned int pmtx_size; /* total PMTX capacity */ |
| 317 | unsigned int cm_size; /* total CM capacity */ |
| 318 | unsigned int chan_rx_size; /* per channel Rx size */ |
| 319 | unsigned int chan_tx_size; /* per channel Tx size */ |
| 320 | unsigned int rx_pg_size; /* Rx page size */ |
| 321 | unsigned int tx_pg_size; /* Tx page size */ |
| 322 | unsigned int rx_num_pgs; /* # of Rx pages */ |
| 323 | unsigned int tx_num_pgs; /* # of Tx pages */ |
| 324 | unsigned int ntimer_qs; /* # of timer queues */ |
| 325 | }; |
| 326 | |
| 327 | struct qset_params { /* SGE queue set parameters */ |
| 328 | unsigned int polling; /* polling/interrupt service for rspq */ |
| 329 | unsigned int coalesce_usecs; /* irq coalescing timer */ |
| 330 | unsigned int rspq_size; /* # of entries in response queue */ |
| 331 | unsigned int fl_size; /* # of entries in regular free list */ |
| 332 | unsigned int jumbo_size; /* # of entries in jumbo free list */ |
| 333 | unsigned int txq_size[SGE_TXQ_PER_SET]; /* Tx queue sizes */ |
| 334 | unsigned int cong_thres; /* FL congestion threshold */ |
| 335 | }; |
| 336 | |
| 337 | struct sge_params { |
| 338 | unsigned int max_pkt_size; /* max offload pkt size */ |
| 339 | struct qset_params qset[SGE_QSETS]; |
| 340 | }; |
| 341 | |
| 342 | struct mc5_params { |
| 343 | unsigned int mode; /* selects MC5 width */ |
| 344 | unsigned int nservers; /* size of server region */ |
| 345 | unsigned int nfilters; /* size of filter region */ |
| 346 | unsigned int nroutes; /* size of routing region */ |
| 347 | }; |
| 348 | |
| 349 | /* Default MC5 region sizes */ |
| 350 | enum { |
| 351 | DEFAULT_NSERVERS = 512, |
| 352 | DEFAULT_NFILTERS = 128 |
| 353 | }; |
| 354 | |
| 355 | /* MC5 modes, these must be non-0 */ |
| 356 | enum { |
| 357 | MC5_MODE_144_BIT = 1, |
| 358 | MC5_MODE_72_BIT = 2 |
| 359 | }; |
| 360 | |
Divy Le Ray | 9f23848 | 2007-03-31 00:23:13 -0700 | [diff] [blame^] | 361 | /* MC5 min active region size */ |
| 362 | enum { MC5_MIN_TIDS = 16 }; |
| 363 | |
Divy Le Ray | 4d22de3 | 2007-01-18 22:04:14 -0500 | [diff] [blame] | 364 | struct vpd_params { |
| 365 | unsigned int cclk; |
| 366 | unsigned int mclk; |
| 367 | unsigned int uclk; |
| 368 | unsigned int mdc; |
| 369 | unsigned int mem_timing; |
| 370 | u8 eth_base[6]; |
| 371 | u8 port_type[MAX_NPORTS]; |
| 372 | unsigned short xauicfg[2]; |
| 373 | }; |
| 374 | |
| 375 | struct pci_params { |
| 376 | unsigned int vpd_cap_addr; |
| 377 | unsigned int pcie_cap_addr; |
| 378 | unsigned short speed; |
| 379 | unsigned char width; |
| 380 | unsigned char variant; |
| 381 | }; |
| 382 | |
| 383 | enum { |
| 384 | PCI_VARIANT_PCI, |
| 385 | PCI_VARIANT_PCIX_MODE1_PARITY, |
| 386 | PCI_VARIANT_PCIX_MODE1_ECC, |
| 387 | PCI_VARIANT_PCIX_266_MODE2, |
| 388 | PCI_VARIANT_PCIE |
| 389 | }; |
| 390 | |
| 391 | struct adapter_params { |
| 392 | struct sge_params sge; |
| 393 | struct mc5_params mc5; |
| 394 | struct tp_params tp; |
| 395 | struct vpd_params vpd; |
| 396 | struct pci_params pci; |
| 397 | |
| 398 | const struct adapter_info *info; |
| 399 | |
| 400 | unsigned short mtus[NMTUS]; |
| 401 | unsigned short a_wnd[NCCTRL_WIN]; |
| 402 | unsigned short b_wnd[NCCTRL_WIN]; |
| 403 | |
| 404 | unsigned int nports; /* # of ethernet ports */ |
| 405 | unsigned int stats_update_period; /* MAC stats accumulation period */ |
| 406 | unsigned int linkpoll_period; /* link poll period in 0.1s */ |
| 407 | unsigned int rev; /* chip revision */ |
| 408 | }; |
| 409 | |
Divy Le Ray | fc90664 | 2007-03-18 13:10:12 -0700 | [diff] [blame] | 410 | enum { /* chip revisions */ |
| 411 | T3_REV_A = 0, |
| 412 | T3_REV_B = 2, |
| 413 | T3_REV_B2 = 3, |
| 414 | }; |
| 415 | |
Divy Le Ray | 4d22de3 | 2007-01-18 22:04:14 -0500 | [diff] [blame] | 416 | struct trace_params { |
| 417 | u32 sip; |
| 418 | u32 sip_mask; |
| 419 | u32 dip; |
| 420 | u32 dip_mask; |
| 421 | u16 sport; |
| 422 | u16 sport_mask; |
| 423 | u16 dport; |
| 424 | u16 dport_mask; |
| 425 | u32 vlan:12; |
| 426 | u32 vlan_mask:12; |
| 427 | u32 intf:4; |
| 428 | u32 intf_mask:4; |
| 429 | u8 proto; |
| 430 | u8 proto_mask; |
| 431 | }; |
| 432 | |
| 433 | struct link_config { |
| 434 | unsigned int supported; /* link capabilities */ |
| 435 | unsigned int advertising; /* advertised capabilities */ |
| 436 | unsigned short requested_speed; /* speed user has requested */ |
| 437 | unsigned short speed; /* actual link speed */ |
| 438 | unsigned char requested_duplex; /* duplex user has requested */ |
| 439 | unsigned char duplex; /* actual link duplex */ |
| 440 | unsigned char requested_fc; /* flow control user has requested */ |
| 441 | unsigned char fc; /* actual link flow control */ |
| 442 | unsigned char autoneg; /* autonegotiating? */ |
| 443 | unsigned int link_ok; /* link up? */ |
| 444 | }; |
| 445 | |
| 446 | #define SPEED_INVALID 0xffff |
| 447 | #define DUPLEX_INVALID 0xff |
| 448 | |
| 449 | struct mc5 { |
| 450 | struct adapter *adapter; |
| 451 | unsigned int tcam_size; |
| 452 | unsigned char part_type; |
| 453 | unsigned char parity_enabled; |
| 454 | unsigned char mode; |
| 455 | struct mc5_stats stats; |
| 456 | }; |
| 457 | |
| 458 | static inline unsigned int t3_mc5_size(const struct mc5 *p) |
| 459 | { |
| 460 | return p->tcam_size; |
| 461 | } |
| 462 | |
| 463 | struct mc7 { |
| 464 | struct adapter *adapter; /* backpointer to adapter */ |
| 465 | unsigned int size; /* memory size in bytes */ |
| 466 | unsigned int width; /* MC7 interface width */ |
| 467 | unsigned int offset; /* register address offset for MC7 instance */ |
| 468 | const char *name; /* name of MC7 instance */ |
| 469 | struct mc7_stats stats; /* MC7 statistics */ |
| 470 | }; |
| 471 | |
| 472 | static inline unsigned int t3_mc7_size(const struct mc7 *p) |
| 473 | { |
| 474 | return p->size; |
| 475 | } |
| 476 | |
| 477 | struct cmac { |
| 478 | struct adapter *adapter; |
| 479 | unsigned int offset; |
| 480 | unsigned int nucast; /* # of address filters for unicast MACs */ |
Divy Le Ray | fc90664 | 2007-03-18 13:10:12 -0700 | [diff] [blame] | 481 | unsigned int tcnt; |
| 482 | unsigned int xcnt; |
| 483 | unsigned int toggle_cnt; |
| 484 | unsigned int txen; |
Divy Le Ray | 4d22de3 | 2007-01-18 22:04:14 -0500 | [diff] [blame] | 485 | struct mac_stats stats; |
| 486 | }; |
| 487 | |
| 488 | enum { |
| 489 | MAC_DIRECTION_RX = 1, |
| 490 | MAC_DIRECTION_TX = 2, |
| 491 | MAC_RXFIFO_SIZE = 32768 |
| 492 | }; |
| 493 | |
| 494 | /* IEEE 802.3ae specified MDIO devices */ |
| 495 | enum { |
| 496 | MDIO_DEV_PMA_PMD = 1, |
| 497 | MDIO_DEV_WIS = 2, |
| 498 | MDIO_DEV_PCS = 3, |
| 499 | MDIO_DEV_XGXS = 4 |
| 500 | }; |
| 501 | |
| 502 | /* PHY loopback direction */ |
| 503 | enum { |
| 504 | PHY_LOOPBACK_TX = 1, |
| 505 | PHY_LOOPBACK_RX = 2 |
| 506 | }; |
| 507 | |
| 508 | /* PHY interrupt types */ |
| 509 | enum { |
| 510 | cphy_cause_link_change = 1, |
| 511 | cphy_cause_fifo_error = 2 |
| 512 | }; |
| 513 | |
| 514 | /* PHY operations */ |
| 515 | struct cphy_ops { |
| 516 | void (*destroy)(struct cphy *phy); |
| 517 | int (*reset)(struct cphy *phy, int wait); |
| 518 | |
| 519 | int (*intr_enable)(struct cphy *phy); |
| 520 | int (*intr_disable)(struct cphy *phy); |
| 521 | int (*intr_clear)(struct cphy *phy); |
| 522 | int (*intr_handler)(struct cphy *phy); |
| 523 | |
| 524 | int (*autoneg_enable)(struct cphy *phy); |
| 525 | int (*autoneg_restart)(struct cphy *phy); |
| 526 | |
| 527 | int (*advertise)(struct cphy *phy, unsigned int advertise_map); |
| 528 | int (*set_loopback)(struct cphy *phy, int mmd, int dir, int enable); |
| 529 | int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex); |
| 530 | int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed, |
| 531 | int *duplex, int *fc); |
| 532 | int (*power_down)(struct cphy *phy, int enable); |
| 533 | }; |
| 534 | |
| 535 | /* A PHY instance */ |
| 536 | struct cphy { |
| 537 | int addr; /* PHY address */ |
| 538 | struct adapter *adapter; /* associated adapter */ |
| 539 | unsigned long fifo_errors; /* FIFO over/under-flows */ |
| 540 | const struct cphy_ops *ops; /* PHY operations */ |
| 541 | int (*mdio_read)(struct adapter *adapter, int phy_addr, int mmd_addr, |
| 542 | int reg_addr, unsigned int *val); |
| 543 | int (*mdio_write)(struct adapter *adapter, int phy_addr, int mmd_addr, |
| 544 | int reg_addr, unsigned int val); |
| 545 | }; |
| 546 | |
| 547 | /* Convenience MDIO read/write wrappers */ |
| 548 | static inline int mdio_read(struct cphy *phy, int mmd, int reg, |
| 549 | unsigned int *valp) |
| 550 | { |
| 551 | return phy->mdio_read(phy->adapter, phy->addr, mmd, reg, valp); |
| 552 | } |
| 553 | |
| 554 | static inline int mdio_write(struct cphy *phy, int mmd, int reg, |
| 555 | unsigned int val) |
| 556 | { |
| 557 | return phy->mdio_write(phy->adapter, phy->addr, mmd, reg, val); |
| 558 | } |
| 559 | |
| 560 | /* Convenience initializer */ |
| 561 | static inline void cphy_init(struct cphy *phy, struct adapter *adapter, |
| 562 | int phy_addr, struct cphy_ops *phy_ops, |
| 563 | const struct mdio_ops *mdio_ops) |
| 564 | { |
| 565 | phy->adapter = adapter; |
| 566 | phy->addr = phy_addr; |
| 567 | phy->ops = phy_ops; |
| 568 | if (mdio_ops) { |
| 569 | phy->mdio_read = mdio_ops->read; |
| 570 | phy->mdio_write = mdio_ops->write; |
| 571 | } |
| 572 | } |
| 573 | |
| 574 | /* Accumulate MAC statistics every 180 seconds. For 1G we multiply by 10. */ |
| 575 | #define MAC_STATS_ACCUM_SECS 180 |
| 576 | |
| 577 | #define XGM_REG(reg_addr, idx) \ |
| 578 | ((reg_addr) + (idx) * (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR)) |
| 579 | |
| 580 | struct addr_val_pair { |
| 581 | unsigned int reg_addr; |
| 582 | unsigned int val; |
| 583 | }; |
| 584 | |
| 585 | #include "adapter.h" |
| 586 | |
| 587 | #ifndef PCI_VENDOR_ID_CHELSIO |
| 588 | # define PCI_VENDOR_ID_CHELSIO 0x1425 |
| 589 | #endif |
| 590 | |
| 591 | #define for_each_port(adapter, iter) \ |
| 592 | for (iter = 0; iter < (adapter)->params.nports; ++iter) |
| 593 | |
| 594 | #define adapter_info(adap) ((adap)->params.info) |
| 595 | |
| 596 | static inline int uses_xaui(const struct adapter *adap) |
| 597 | { |
| 598 | return adapter_info(adap)->caps & SUPPORTED_AUI; |
| 599 | } |
| 600 | |
| 601 | static inline int is_10G(const struct adapter *adap) |
| 602 | { |
| 603 | return adapter_info(adap)->caps & SUPPORTED_10000baseT_Full; |
| 604 | } |
| 605 | |
| 606 | static inline int is_offload(const struct adapter *adap) |
| 607 | { |
| 608 | return adapter_info(adap)->caps & SUPPORTED_OFFLOAD; |
| 609 | } |
| 610 | |
| 611 | static inline unsigned int core_ticks_per_usec(const struct adapter *adap) |
| 612 | { |
| 613 | return adap->params.vpd.cclk / 1000; |
| 614 | } |
| 615 | |
| 616 | static inline unsigned int is_pcie(const struct adapter *adap) |
| 617 | { |
| 618 | return adap->params.pci.variant == PCI_VARIANT_PCIE; |
| 619 | } |
| 620 | |
| 621 | void t3_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, |
| 622 | u32 val); |
| 623 | void t3_write_regs(struct adapter *adapter, const struct addr_val_pair *p, |
| 624 | int n, unsigned int offset); |
| 625 | int t3_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, |
| 626 | int polarity, int attempts, int delay, u32 *valp); |
| 627 | static inline int t3_wait_op_done(struct adapter *adapter, int reg, u32 mask, |
| 628 | int polarity, int attempts, int delay) |
| 629 | { |
| 630 | return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts, |
| 631 | delay, NULL); |
| 632 | } |
| 633 | int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear, |
| 634 | unsigned int set); |
| 635 | int t3_phy_reset(struct cphy *phy, int mmd, int wait); |
| 636 | int t3_phy_advertise(struct cphy *phy, unsigned int advert); |
| 637 | int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex); |
| 638 | |
| 639 | void t3_intr_enable(struct adapter *adapter); |
| 640 | void t3_intr_disable(struct adapter *adapter); |
| 641 | void t3_intr_clear(struct adapter *adapter); |
| 642 | void t3_port_intr_enable(struct adapter *adapter, int idx); |
| 643 | void t3_port_intr_disable(struct adapter *adapter, int idx); |
| 644 | void t3_port_intr_clear(struct adapter *adapter, int idx); |
| 645 | int t3_slow_intr_handler(struct adapter *adapter); |
| 646 | int t3_phy_intr_handler(struct adapter *adapter); |
| 647 | |
| 648 | void t3_link_changed(struct adapter *adapter, int port_id); |
| 649 | int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc); |
| 650 | const struct adapter_info *t3_get_adapter_info(unsigned int board_id); |
| 651 | int t3_seeprom_read(struct adapter *adapter, u32 addr, u32 *data); |
| 652 | int t3_seeprom_write(struct adapter *adapter, u32 addr, u32 data); |
| 653 | int t3_seeprom_wp(struct adapter *adapter, int enable); |
| 654 | int t3_read_flash(struct adapter *adapter, unsigned int addr, |
| 655 | unsigned int nwords, u32 *data, int byte_oriented); |
| 656 | int t3_load_fw(struct adapter *adapter, const u8 * fw_data, unsigned int size); |
| 657 | int t3_get_fw_version(struct adapter *adapter, u32 *vers); |
| 658 | int t3_check_fw_version(struct adapter *adapter); |
| 659 | int t3_init_hw(struct adapter *adapter, u32 fw_params); |
| 660 | void mac_prep(struct cmac *mac, struct adapter *adapter, int index); |
| 661 | void early_hw_init(struct adapter *adapter, const struct adapter_info *ai); |
| 662 | int t3_prep_adapter(struct adapter *adapter, const struct adapter_info *ai, |
| 663 | int reset); |
| 664 | void t3_led_ready(struct adapter *adapter); |
| 665 | void t3_fatal_err(struct adapter *adapter); |
| 666 | void t3_set_vlan_accel(struct adapter *adapter, unsigned int ports, int on); |
| 667 | void t3_config_rss(struct adapter *adapter, unsigned int rss_config, |
| 668 | const u8 * cpus, const u16 *rspq); |
| 669 | int t3_read_rss(struct adapter *adapter, u8 * lkup, u16 *map); |
| 670 | int t3_mps_set_active_ports(struct adapter *adap, unsigned int port_mask); |
| 671 | int t3_cim_ctl_blk_read(struct adapter *adap, unsigned int addr, |
| 672 | unsigned int n, unsigned int *valp); |
| 673 | int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n, |
| 674 | u64 *buf); |
| 675 | |
| 676 | int t3_mac_reset(struct cmac *mac); |
| 677 | void t3b_pcs_reset(struct cmac *mac); |
| 678 | int t3_mac_enable(struct cmac *mac, int which); |
| 679 | int t3_mac_disable(struct cmac *mac, int which); |
| 680 | int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu); |
| 681 | int t3_mac_set_rx_mode(struct cmac *mac, struct t3_rx_mode *rm); |
| 682 | int t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6]); |
| 683 | int t3_mac_set_num_ucast(struct cmac *mac, int n); |
| 684 | const struct mac_stats *t3_mac_update_stats(struct cmac *mac); |
| 685 | int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, int fc); |
Divy Le Ray | fc90664 | 2007-03-18 13:10:12 -0700 | [diff] [blame] | 686 | int t3b2_mac_watchdog_task(struct cmac *mac); |
Divy Le Ray | 4d22de3 | 2007-01-18 22:04:14 -0500 | [diff] [blame] | 687 | |
| 688 | void t3_mc5_prep(struct adapter *adapter, struct mc5 *mc5, int mode); |
| 689 | int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters, |
| 690 | unsigned int nroutes); |
| 691 | void t3_mc5_intr_handler(struct mc5 *mc5); |
| 692 | int t3_read_mc5_range(const struct mc5 *mc5, unsigned int start, unsigned int n, |
| 693 | u32 *buf); |
| 694 | |
| 695 | int t3_tp_set_coalescing_size(struct adapter *adap, unsigned int size, int psh); |
| 696 | void t3_tp_set_max_rxsize(struct adapter *adap, unsigned int size); |
| 697 | void t3_tp_set_offload_mode(struct adapter *adap, int enable); |
| 698 | void t3_tp_get_mib_stats(struct adapter *adap, struct tp_mib_stats *tps); |
| 699 | void t3_load_mtus(struct adapter *adap, unsigned short mtus[NMTUS], |
| 700 | unsigned short alpha[NCCTRL_WIN], |
| 701 | unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap); |
| 702 | void t3_read_hw_mtus(struct adapter *adap, unsigned short mtus[NMTUS]); |
| 703 | void t3_get_cong_cntl_tab(struct adapter *adap, |
| 704 | unsigned short incr[NMTUS][NCCTRL_WIN]); |
| 705 | void t3_config_trace_filter(struct adapter *adapter, |
| 706 | const struct trace_params *tp, int filter_index, |
| 707 | int invert, int enable); |
| 708 | int t3_config_sched(struct adapter *adap, unsigned int kbps, int sched); |
| 709 | |
| 710 | void t3_sge_prep(struct adapter *adap, struct sge_params *p); |
| 711 | void t3_sge_init(struct adapter *adap, struct sge_params *p); |
| 712 | int t3_sge_init_ecntxt(struct adapter *adapter, unsigned int id, int gts_enable, |
| 713 | enum sge_context_type type, int respq, u64 base_addr, |
| 714 | unsigned int size, unsigned int token, int gen, |
| 715 | unsigned int cidx); |
| 716 | int t3_sge_init_flcntxt(struct adapter *adapter, unsigned int id, |
| 717 | int gts_enable, u64 base_addr, unsigned int size, |
| 718 | unsigned int esize, unsigned int cong_thres, int gen, |
| 719 | unsigned int cidx); |
| 720 | int t3_sge_init_rspcntxt(struct adapter *adapter, unsigned int id, |
| 721 | int irq_vec_idx, u64 base_addr, unsigned int size, |
| 722 | unsigned int fl_thres, int gen, unsigned int cidx); |
| 723 | int t3_sge_init_cqcntxt(struct adapter *adapter, unsigned int id, u64 base_addr, |
| 724 | unsigned int size, int rspq, int ovfl_mode, |
| 725 | unsigned int credits, unsigned int credit_thres); |
| 726 | int t3_sge_enable_ecntxt(struct adapter *adapter, unsigned int id, int enable); |
| 727 | int t3_sge_disable_fl(struct adapter *adapter, unsigned int id); |
| 728 | int t3_sge_disable_rspcntxt(struct adapter *adapter, unsigned int id); |
| 729 | int t3_sge_disable_cqcntxt(struct adapter *adapter, unsigned int id); |
| 730 | int t3_sge_read_ecntxt(struct adapter *adapter, unsigned int id, u32 data[4]); |
| 731 | int t3_sge_read_fl(struct adapter *adapter, unsigned int id, u32 data[4]); |
| 732 | int t3_sge_read_cq(struct adapter *adapter, unsigned int id, u32 data[4]); |
| 733 | int t3_sge_read_rspq(struct adapter *adapter, unsigned int id, u32 data[4]); |
| 734 | int t3_sge_cqcntxt_op(struct adapter *adapter, unsigned int id, unsigned int op, |
| 735 | unsigned int credits); |
| 736 | |
| 737 | void t3_vsc8211_phy_prep(struct cphy *phy, struct adapter *adapter, |
| 738 | int phy_addr, const struct mdio_ops *mdio_ops); |
| 739 | void t3_ael1002_phy_prep(struct cphy *phy, struct adapter *adapter, |
| 740 | int phy_addr, const struct mdio_ops *mdio_ops); |
| 741 | void t3_ael1006_phy_prep(struct cphy *phy, struct adapter *adapter, |
| 742 | int phy_addr, const struct mdio_ops *mdio_ops); |
| 743 | void t3_qt2045_phy_prep(struct cphy *phy, struct adapter *adapter, int phy_addr, |
| 744 | const struct mdio_ops *mdio_ops); |
| 745 | void t3_xaui_direct_phy_prep(struct cphy *phy, struct adapter *adapter, |
| 746 | int phy_addr, const struct mdio_ops *mdio_ops); |
| 747 | #endif /* __CHELSIO_COMMON_H */ |