| Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 1 | # |
| 2 | # DMA engine configuration |
| 3 | # |
| 4 | |
| Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 5 | menuconfig DMADEVICES |
| Haavard Skinnemoen | 6d4f587 | 2007-11-28 16:21:43 -0800 | [diff] [blame] | 6 | bool "DMA Engine support" |
| Dan Williams | 9c402f4 | 2008-06-27 01:21:11 -0700 | [diff] [blame^] | 7 | depends on !HIGHMEM64G && HAS_DMA |
| Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 8 | help |
| Haavard Skinnemoen | 6d4f587 | 2007-11-28 16:21:43 -0800 | [diff] [blame] | 9 | DMA engines can do asynchronous data transfers without |
| 10 | involving the host CPU. Currently, this framework can be |
| 11 | used to offload memory copies in the network stack and |
| Dan Williams | 9c402f4 | 2008-06-27 01:21:11 -0700 | [diff] [blame^] | 12 | RAID operations in the MD driver. This menu only presents |
| 13 | DMA Device drivers supported by the configured arch, it may |
| 14 | be empty in some cases. |
| Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 15 | |
| Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 16 | if DMADEVICES |
| Chris Leech | db21733 | 2006-06-17 21:24:58 -0700 | [diff] [blame] | 17 | |
| Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 18 | comment "DMA Devices" |
| 19 | |
| 20 | config INTEL_IOATDMA |
| 21 | tristate "Intel I/OAT DMA support" |
| Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 22 | depends on PCI && X86 |
| 23 | select DMA_ENGINE |
| 24 | select DCA |
| 25 | help |
| 26 | Enable support for the Intel(R) I/OAT DMA engine present |
| 27 | in recent Intel Xeon chipsets. |
| 28 | |
| 29 | Say Y here if you have such a chipset. |
| 30 | |
| 31 | If unsure, say N. |
| Dan Williams | c211092 | 2007-01-02 13:52:26 -0700 | [diff] [blame] | 32 | |
| 33 | config INTEL_IOP_ADMA |
| Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 34 | tristate "Intel IOP ADMA support" |
| 35 | depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX |
| Dan Williams | c211092 | 2007-01-02 13:52:26 -0700 | [diff] [blame] | 36 | select ASYNC_CORE |
| Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 37 | select DMA_ENGINE |
| 38 | help |
| 39 | Enable support for the Intel(R) IOP Series RAID engines. |
| Dan Williams | c211092 | 2007-01-02 13:52:26 -0700 | [diff] [blame] | 40 | |
| Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 41 | config FSL_DMA |
| 42 | bool "Freescale MPC85xx/MPC83xx DMA support" |
| 43 | depends on PPC |
| 44 | select DMA_ENGINE |
| 45 | ---help--- |
| 46 | Enable support for the Freescale DMA engine. Now, it support |
| 47 | MPC8560/40, MPC8555, MPC8548 and MPC8641 processors. |
| 48 | The MPC8349, MPC8360 is also supported. |
| 49 | |
| Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 50 | config DMA_ENGINE |
| 51 | bool |
| 52 | |
| 53 | comment "DMA Clients" |
| 54 | depends on DMA_ENGINE |
| 55 | |
| 56 | config NET_DMA |
| 57 | bool "Network: TCP receive copy offload" |
| 58 | depends on DMA_ENGINE && NET |
| Dan Williams | 9c402f4 | 2008-06-27 01:21:11 -0700 | [diff] [blame^] | 59 | default (INTEL_IOATDMA || FSL_DMA) |
| Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 60 | help |
| 61 | This enables the use of DMA engines in the network stack to |
| 62 | offload receive copy-to-user operations, freeing CPU cycles. |
| Dan Williams | 9c402f4 | 2008-06-27 01:21:11 -0700 | [diff] [blame^] | 63 | |
| 64 | Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise |
| 65 | say N. |
| Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 66 | |
| 67 | endif |