Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
| 2 | */ |
| 3 | /************************************************************************** |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 4 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 6 | * All Rights Reserved. |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 7 | * |
| 8 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 9 | * copy of this software and associated documentation files (the |
| 10 | * "Software"), to deal in the Software without restriction, including |
| 11 | * without limitation the rights to use, copy, modify, merge, publish, |
| 12 | * distribute, sub license, and/or sell copies of the Software, and to |
| 13 | * permit persons to whom the Software is furnished to do so, subject to |
| 14 | * the following conditions: |
| 15 | * |
| 16 | * The above copyright notice and this permission notice (including the |
| 17 | * next paragraph) shall be included in all copies or substantial portions |
| 18 | * of the Software. |
| 19 | * |
| 20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 27 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | **************************************************************************/ |
| 29 | |
| 30 | #ifndef _I915_DRV_H_ |
| 31 | #define _I915_DRV_H_ |
| 32 | |
| 33 | /* General customization: |
| 34 | */ |
| 35 | |
| 36 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." |
| 37 | |
| 38 | #define DRIVER_NAME "i915" |
| 39 | #define DRIVER_DESC "Intel Graphics" |
| 40 | #define DRIVER_DATE "20040405" |
| 41 | |
| 42 | /* Interface history: |
| 43 | * |
| 44 | * 1.1: Original. |
| 45 | */ |
| 46 | #define DRIVER_MAJOR 1 |
| 47 | #define DRIVER_MINOR 1 |
| 48 | #define DRIVER_PATCHLEVEL 0 |
| 49 | |
| 50 | /* We use our own dma mechanisms, not the drm template code. However, |
| 51 | * the shared IRQ code is useful to us: |
| 52 | */ |
| 53 | #define __HAVE_PM 1 |
| 54 | |
| 55 | typedef struct _drm_i915_ring_buffer { |
| 56 | int tail_mask; |
| 57 | unsigned long Start; |
| 58 | unsigned long End; |
| 59 | unsigned long Size; |
| 60 | u8 *virtual_start; |
| 61 | int head; |
| 62 | int tail; |
| 63 | int space; |
| 64 | drm_local_map_t map; |
| 65 | } drm_i915_ring_buffer_t; |
| 66 | |
| 67 | struct mem_block { |
| 68 | struct mem_block *next; |
| 69 | struct mem_block *prev; |
| 70 | int start; |
| 71 | int size; |
| 72 | DRMFILE filp; /* 0: free, -1: heap, other: real files */ |
| 73 | }; |
| 74 | |
| 75 | typedef struct drm_i915_private { |
| 76 | drm_local_map_t *sarea; |
| 77 | drm_local_map_t *mmio_map; |
| 78 | |
| 79 | drm_i915_sarea_t *sarea_priv; |
| 80 | drm_i915_ring_buffer_t ring; |
| 81 | |
Dave Airlie | 9c8da5e | 2005-07-10 15:38:56 +1000 | [diff] [blame^] | 82 | drm_dma_handle_t *status_page_dmah; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 83 | void *hw_status_page; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 84 | dma_addr_t dma_status_page; |
Dave Airlie | 9c8da5e | 2005-07-10 15:38:56 +1000 | [diff] [blame^] | 85 | unsigned long counter; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 86 | |
| 87 | int back_offset; |
| 88 | int front_offset; |
| 89 | int current_page; |
| 90 | int page_flipping; |
| 91 | int use_mi_batchbuffer_start; |
| 92 | |
| 93 | wait_queue_head_t irq_queue; |
| 94 | atomic_t irq_received; |
| 95 | atomic_t irq_emitted; |
| 96 | |
| 97 | int tex_lru_log_granularity; |
| 98 | int allow_batchbuffer; |
| 99 | struct mem_block *agp_heap; |
| 100 | } drm_i915_private_t; |
| 101 | |
| 102 | /* i915_dma.c */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 103 | extern void i915_kernel_lost_context(drm_device_t * dev); |
| 104 | extern void i915_driver_pretakedown(drm_device_t *dev); |
| 105 | extern void i915_driver_prerelease(drm_device_t *dev, DRMFILE filp); |
| 106 | |
| 107 | /* i915_irq.c */ |
| 108 | extern int i915_irq_emit(DRM_IOCTL_ARGS); |
| 109 | extern int i915_irq_wait(DRM_IOCTL_ARGS); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 110 | |
| 111 | extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); |
| 112 | extern void i915_driver_irq_preinstall(drm_device_t *dev); |
| 113 | extern void i915_driver_irq_postinstall(drm_device_t *dev); |
| 114 | extern void i915_driver_irq_uninstall(drm_device_t *dev); |
| 115 | |
| 116 | /* i915_mem.c */ |
| 117 | extern int i915_mem_alloc(DRM_IOCTL_ARGS); |
| 118 | extern int i915_mem_free(DRM_IOCTL_ARGS); |
| 119 | extern int i915_mem_init_heap(DRM_IOCTL_ARGS); |
| 120 | extern void i915_mem_takedown(struct mem_block **heap); |
| 121 | extern void i915_mem_release(drm_device_t * dev, |
| 122 | DRMFILE filp, struct mem_block *heap); |
| 123 | |
Dave Airlie | 8ca7c1d | 2005-07-07 21:51:26 +1000 | [diff] [blame] | 124 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
Dave Airlie | f179bc7 | 2005-07-10 12:46:19 +1000 | [diff] [blame] | 125 | unsigned long arg); |
Dave Airlie | 8ca7c1d | 2005-07-07 21:51:26 +1000 | [diff] [blame] | 126 | |
| 127 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 128 | #define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, reg) |
| 129 | #define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, reg, val) |
| 130 | #define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, reg) |
| 131 | #define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, reg, val) |
| 132 | |
| 133 | #define I915_VERBOSE 0 |
| 134 | |
| 135 | #define RING_LOCALS unsigned int outring, ringmask, outcount; \ |
| 136 | volatile char *virt; |
| 137 | |
| 138 | #define BEGIN_LP_RING(n) do { \ |
| 139 | if (I915_VERBOSE) \ |
| 140 | DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n", \ |
| 141 | n, __FUNCTION__); \ |
| 142 | if (dev_priv->ring.space < n*4) \ |
| 143 | i915_wait_ring(dev, n*4, __FUNCTION__); \ |
| 144 | outcount = 0; \ |
| 145 | outring = dev_priv->ring.tail; \ |
| 146 | ringmask = dev_priv->ring.tail_mask; \ |
| 147 | virt = dev_priv->ring.virtual_start; \ |
| 148 | } while (0) |
| 149 | |
| 150 | #define OUT_RING(n) do { \ |
| 151 | if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ |
| 152 | *(volatile unsigned int *)(virt + outring) = n; \ |
| 153 | outcount++; \ |
| 154 | outring += 4; \ |
| 155 | outring &= ringmask; \ |
| 156 | } while (0) |
| 157 | |
| 158 | #define ADVANCE_LP_RING() do { \ |
| 159 | if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \ |
| 160 | dev_priv->ring.tail = outring; \ |
| 161 | dev_priv->ring.space -= outcount * 4; \ |
| 162 | I915_WRITE(LP_RING + RING_TAIL, outring); \ |
| 163 | } while(0) |
| 164 | |
| 165 | extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller); |
| 166 | |
| 167 | #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23)) |
| 168 | #define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23)) |
| 169 | #define CMD_REPORT_HEAD (7<<23) |
| 170 | #define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1) |
| 171 | #define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1) |
| 172 | |
| 173 | #define INST_PARSER_CLIENT 0x00000000 |
| 174 | #define INST_OP_FLUSH 0x02000000 |
| 175 | #define INST_FLUSH_MAP_CACHE 0x00000001 |
| 176 | |
| 177 | #define BB1_START_ADDR_MASK (~0x7) |
| 178 | #define BB1_PROTECTED (1<<0) |
| 179 | #define BB1_UNPROTECTED (0<<0) |
| 180 | #define BB2_END_ADDR_MASK (~0x7) |
| 181 | |
| 182 | #define I915REG_HWSTAM 0x02098 |
| 183 | #define I915REG_INT_IDENTITY_R 0x020a4 |
| 184 | #define I915REG_INT_MASK_R 0x020a8 |
| 185 | #define I915REG_INT_ENABLE_R 0x020a0 |
| 186 | |
| 187 | #define SRX_INDEX 0x3c4 |
| 188 | #define SRX_DATA 0x3c5 |
| 189 | #define SR01 1 |
| 190 | #define SR01_SCREEN_OFF (1<<5) |
| 191 | |
| 192 | #define PPCR 0x61204 |
| 193 | #define PPCR_ON (1<<0) |
| 194 | |
| 195 | #define ADPA 0x61100 |
| 196 | #define ADPA_DPMS_MASK (~(3<<10)) |
| 197 | #define ADPA_DPMS_ON (0<<10) |
| 198 | #define ADPA_DPMS_SUSPEND (1<<10) |
| 199 | #define ADPA_DPMS_STANDBY (2<<10) |
| 200 | #define ADPA_DPMS_OFF (3<<10) |
| 201 | |
| 202 | #define NOPID 0x2094 |
| 203 | #define LP_RING 0x2030 |
| 204 | #define HP_RING 0x2040 |
| 205 | #define RING_TAIL 0x00 |
| 206 | #define TAIL_ADDR 0x001FFFF8 |
| 207 | #define RING_HEAD 0x04 |
| 208 | #define HEAD_WRAP_COUNT 0xFFE00000 |
| 209 | #define HEAD_WRAP_ONE 0x00200000 |
| 210 | #define HEAD_ADDR 0x001FFFFC |
| 211 | #define RING_START 0x08 |
| 212 | #define START_ADDR 0x0xFFFFF000 |
| 213 | #define RING_LEN 0x0C |
| 214 | #define RING_NR_PAGES 0x001FF000 |
| 215 | #define RING_REPORT_MASK 0x00000006 |
| 216 | #define RING_REPORT_64K 0x00000002 |
| 217 | #define RING_REPORT_128K 0x00000004 |
| 218 | #define RING_NO_REPORT 0x00000000 |
| 219 | #define RING_VALID_MASK 0x00000001 |
| 220 | #define RING_VALID 0x00000001 |
| 221 | #define RING_INVALID 0x00000000 |
| 222 | |
| 223 | #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) |
| 224 | #define SC_UPDATE_SCISSOR (0x1<<1) |
| 225 | #define SC_ENABLE_MASK (0x1<<0) |
| 226 | #define SC_ENABLE (0x1<<0) |
| 227 | |
| 228 | #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) |
| 229 | #define SCI_YMIN_MASK (0xffff<<16) |
| 230 | #define SCI_XMIN_MASK (0xffff<<0) |
| 231 | #define SCI_YMAX_MASK (0xffff<<16) |
| 232 | #define SCI_XMAX_MASK (0xffff<<0) |
| 233 | |
| 234 | #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) |
| 235 | #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) |
| 236 | #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) |
| 237 | #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) |
| 238 | #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) |
| 239 | #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) |
| 240 | #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) |
| 241 | |
| 242 | #define MI_BATCH_BUFFER ((0x30<<23)|1) |
| 243 | #define MI_BATCH_BUFFER_START (0x31<<23) |
| 244 | #define MI_BATCH_BUFFER_END (0xA<<23) |
| 245 | #define MI_BATCH_NON_SECURE (1) |
| 246 | |
| 247 | #define MI_WAIT_FOR_EVENT ((0x3<<23)) |
| 248 | #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) |
| 249 | #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) |
| 250 | |
| 251 | #define MI_LOAD_SCAN_LINES_INCL ((0x12<<23)) |
| 252 | |
| 253 | #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) |
| 254 | #define ASYNC_FLIP (1<<22) |
| 255 | |
| 256 | #define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) |
| 257 | |
| 258 | #endif |