| Paul Mackerras | d662ed2 | 2009-01-09 17:01:53 +1100 | [diff] [blame] | 1 | /* |
| 2 | * Performance counter support - PowerPC-specific definitions. |
| 3 | * |
| 4 | * Copyright 2008-2009 Paul Mackerras, IBM Corporation. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License |
| 8 | * as published by the Free Software Foundation; either version |
| 9 | * 2 of the License, or (at your option) any later version. |
| 10 | */ |
| Paul Mackerras | 4574910 | 2009-01-09 20:21:55 +1100 | [diff] [blame] | 11 | #include <linux/types.h> |
| 12 | |
| 13 | #define MAX_HWCOUNTERS 8 |
| 14 | #define MAX_EVENT_ALTERNATIVES 8 |
| 15 | |
| 16 | /* |
| 17 | * This struct provides the constants and functions needed to |
| 18 | * describe the PMU on a particular POWER-family CPU. |
| 19 | */ |
| 20 | struct power_pmu { |
| 21 | int n_counter; |
| 22 | int max_alternatives; |
| 23 | u64 add_fields; |
| 24 | u64 test_adder; |
| 25 | int (*compute_mmcr)(unsigned int events[], int n_ev, |
| 26 | unsigned int hwc[], u64 mmcr[]); |
| 27 | int (*get_constraint)(unsigned int event, u64 *mskp, u64 *valp); |
| 28 | int (*get_alternatives)(unsigned int event, unsigned int alt[]); |
| 29 | void (*disable_pmc)(unsigned int pmc, u64 mmcr[]); |
| 30 | int n_generic; |
| 31 | int *generic_events; |
| 32 | }; |
| 33 | |
| 34 | extern struct power_pmu *ppmu; |
| 35 | |
| 36 | /* |
| 37 | * The power_pmu.get_constraint function returns a 64-bit value and |
| 38 | * a 64-bit mask that express the constraints between this event and |
| 39 | * other events. |
| 40 | * |
| 41 | * The value and mask are divided up into (non-overlapping) bitfields |
| 42 | * of three different types: |
| 43 | * |
| 44 | * Select field: this expresses the constraint that some set of bits |
| 45 | * in MMCR* needs to be set to a specific value for this event. For a |
| 46 | * select field, the mask contains 1s in every bit of the field, and |
| 47 | * the value contains a unique value for each possible setting of the |
| 48 | * MMCR* bits. The constraint checking code will ensure that two events |
| 49 | * that set the same field in their masks have the same value in their |
| 50 | * value dwords. |
| 51 | * |
| 52 | * Add field: this expresses the constraint that there can be at most |
| 53 | * N events in a particular class. A field of k bits can be used for |
| 54 | * N <= 2^(k-1) - 1. The mask has the most significant bit of the field |
| 55 | * set (and the other bits 0), and the value has only the least significant |
| 56 | * bit of the field set. In addition, the 'add_fields' and 'test_adder' |
| 57 | * in the struct power_pmu for this processor come into play. The |
| 58 | * add_fields value contains 1 in the LSB of the field, and the |
| 59 | * test_adder contains 2^(k-1) - 1 - N in the field. |
| 60 | * |
| 61 | * NAND field: this expresses the constraint that you may not have events |
| 62 | * in all of a set of classes. (For example, on PPC970, you can't select |
| 63 | * events from the FPU, ISU and IDU simultaneously, although any two are |
| 64 | * possible.) For N classes, the field is N+1 bits wide, and each class |
| 65 | * is assigned one bit from the least-significant N bits. The mask has |
| 66 | * only the most-significant bit set, and the value has only the bit |
| 67 | * for the event's class set. The test_adder has the least significant |
| 68 | * bit set in the field. |
| 69 | * |
| 70 | * If an event is not subject to the constraint expressed by a particular |
| 71 | * field, then it will have 0 in both the mask and value for that field. |
| 72 | */ |