| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* | 
| Maciej W. Rozycki | 9399575 | 2006-12-06 20:38:59 -0800 | [diff] [blame] | 2 | * dz.h: Serial port driver for DECstations equipped | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3 | *       with the DZ chipset. | 
|  | 4 | * | 
|  | 5 | * Copyright (C) 1998 Olivier A. D. Lebaillif | 
|  | 6 | * | 
|  | 7 | * Email: olivier.lebaillif@ifrsys.com | 
|  | 8 | * | 
| Maciej W. Rozycki | 9399575 | 2006-12-06 20:38:59 -0800 | [diff] [blame] | 9 | * Copyright (C) 2004, 2006  Maciej W. Rozycki | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10 | */ | 
|  | 11 | #ifndef DZ_SERIAL_H | 
|  | 12 | #define DZ_SERIAL_H | 
|  | 13 |  | 
|  | 14 | /* | 
| Maciej W. Rozycki | 9399575 | 2006-12-06 20:38:59 -0800 | [diff] [blame] | 15 | * Definitions for the Control and Status Register. | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 16 | */ | 
|  | 17 | #define DZ_TRDY        0x8000                 /* Transmitter empty */ | 
| Maciej W. Rozycki | 9399575 | 2006-12-06 20:38:59 -0800 | [diff] [blame] | 18 | #define DZ_TIE         0x4000                 /* Transmitter Interrupt Enbl */ | 
|  | 19 | #define DZ_TLINE       0x0300                 /* Transmitter Line Number */ | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 20 | #define DZ_RDONE       0x0080                 /* Receiver data ready */ | 
|  | 21 | #define DZ_RIE         0x0040                 /* Receive Interrupt Enable */ | 
|  | 22 | #define DZ_MSE         0x0020                 /* Master Scan Enable */ | 
|  | 23 | #define DZ_CLR         0x0010                 /* Master reset */ | 
|  | 24 | #define DZ_MAINT       0x0008                 /* Loop Back Mode */ | 
|  | 25 |  | 
|  | 26 | /* | 
| Maciej W. Rozycki | 9399575 | 2006-12-06 20:38:59 -0800 | [diff] [blame] | 27 | * Definitions for the Receiver Buffer Register. | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | */ | 
| Maciej W. Rozycki | 9399575 | 2006-12-06 20:38:59 -0800 | [diff] [blame] | 29 | #define DZ_RBUF_MASK   0x00FF                 /* Data Mask */ | 
|  | 30 | #define DZ_LINE_MASK   0x0300                 /* Line Mask */ | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 31 | #define DZ_DVAL        0x8000                 /* Valid Data indicator */ | 
|  | 32 | #define DZ_OERR        0x4000                 /* Overrun error indicator */ | 
|  | 33 | #define DZ_FERR        0x2000                 /* Frame error indicator */ | 
|  | 34 | #define DZ_PERR        0x1000                 /* Parity error indicator */ | 
|  | 35 |  | 
| Maciej W. Rozycki | 9399575 | 2006-12-06 20:38:59 -0800 | [diff] [blame] | 36 | #define LINE(x) ((x & DZ_LINE_MASK) >> 8)     /* Get the line number | 
|  | 37 | from the input buffer */ | 
|  | 38 | #define UCHAR(x) ((unsigned char)(x & DZ_RBUF_MASK)) | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 39 |  | 
|  | 40 | /* | 
| Maciej W. Rozycki | 9399575 | 2006-12-06 20:38:59 -0800 | [diff] [blame] | 41 | * Definitions for the Transmit Control Register. | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 42 | */ | 
|  | 43 | #define DZ_LINE_KEYBOARD 0x0001 | 
|  | 44 | #define DZ_LINE_MOUSE    0x0002 | 
|  | 45 | #define DZ_LINE_MODEM    0x0004 | 
|  | 46 | #define DZ_LINE_PRINTER  0x0008 | 
|  | 47 |  | 
| Maciej W. Rozycki | 9399575 | 2006-12-06 20:38:59 -0800 | [diff] [blame] | 48 | #define DZ_MODEM_RTS     0x0800               /* RTS for the modem line (2) */ | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 49 | #define DZ_MODEM_DTR     0x0400               /* DTR for the modem line (2) */ | 
| Maciej W. Rozycki | 9399575 | 2006-12-06 20:38:59 -0800 | [diff] [blame] | 50 | #define DZ_PRINT_RTS     0x0200               /* RTS for the prntr line (3) */ | 
|  | 51 | #define DZ_PRINT_DTR     0x0100               /* DTR for the prntr line (3) */ | 
|  | 52 | #define DZ_LNENB         0x000f               /* Transmitter Line Enable */ | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 53 |  | 
|  | 54 | /* | 
|  | 55 | * Definitions for the Modem Status Register. | 
|  | 56 | */ | 
| Maciej W. Rozycki | 9399575 | 2006-12-06 20:38:59 -0800 | [diff] [blame] | 57 | #define DZ_MODEM_RI      0x0800               /* RI for the modem line (2) */ | 
|  | 58 | #define DZ_MODEM_CD      0x0400               /* CD for the modem line (2) */ | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 59 | #define DZ_MODEM_DSR     0x0200               /* DSR for the modem line (2) */ | 
| Maciej W. Rozycki | 9399575 | 2006-12-06 20:38:59 -0800 | [diff] [blame] | 60 | #define DZ_MODEM_CTS     0x0100               /* CTS for the modem line (2) */ | 
|  | 61 | #define DZ_PRINT_RI      0x0008               /* RI for the printer line (3) */ | 
|  | 62 | #define DZ_PRINT_CD      0x0004               /* CD for the printer line (3) */ | 
|  | 63 | #define DZ_PRINT_DSR     0x0002               /* DSR for the prntr line (3) */ | 
|  | 64 | #define DZ_PRINT_CTS     0x0001               /* CTS for the prntr line (3) */ | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 65 |  | 
|  | 66 | /* | 
|  | 67 | * Definitions for the Transmit Data Register. | 
|  | 68 | */ | 
|  | 69 | #define DZ_BRK0          0x0100               /* Break assertion for line 0 */ | 
|  | 70 | #define DZ_BRK1          0x0200               /* Break assertion for line 1 */ | 
|  | 71 | #define DZ_BRK2          0x0400               /* Break assertion for line 2 */ | 
|  | 72 | #define DZ_BRK3          0x0800               /* Break assertion for line 3 */ | 
|  | 73 |  | 
|  | 74 | /* | 
|  | 75 | * Definitions for the Line Parameter Register. | 
|  | 76 | */ | 
|  | 77 | #define DZ_KEYBOARD      0x0000               /* line 0 = keyboard */ | 
|  | 78 | #define DZ_MOUSE         0x0001               /* line 1 = mouse */ | 
|  | 79 | #define DZ_MODEM         0x0002               /* line 2 = modem */ | 
|  | 80 | #define DZ_PRINTER       0x0003               /* line 3 = printer */ | 
|  | 81 |  | 
|  | 82 | #define DZ_CSIZE         0x0018               /* Number of bits per byte (mask) */ | 
|  | 83 | #define DZ_CS5           0x0000               /* 5 bits per byte */ | 
|  | 84 | #define DZ_CS6           0x0008               /* 6 bits per byte */ | 
|  | 85 | #define DZ_CS7           0x0010               /* 7 bits per byte */ | 
|  | 86 | #define DZ_CS8           0x0018               /* 8 bits per byte */ | 
|  | 87 |  | 
|  | 88 | #define DZ_CSTOPB        0x0020               /* 2 stop bits instead of one */ | 
|  | 89 |  | 
|  | 90 | #define DZ_PARENB        0x0040               /* Parity enable */ | 
|  | 91 | #define DZ_PARODD        0x0080               /* Odd parity instead of even */ | 
|  | 92 |  | 
|  | 93 | #define DZ_CBAUD         0x0E00               /* Baud Rate (mask) */ | 
|  | 94 | #define DZ_B50           0x0000 | 
|  | 95 | #define DZ_B75           0x0100 | 
|  | 96 | #define DZ_B110          0x0200 | 
|  | 97 | #define DZ_B134          0x0300 | 
|  | 98 | #define DZ_B150          0x0400 | 
|  | 99 | #define DZ_B300          0x0500 | 
|  | 100 | #define DZ_B600          0x0600 | 
|  | 101 | #define DZ_B1200         0x0700 | 
|  | 102 | #define DZ_B1800         0x0800 | 
|  | 103 | #define DZ_B2000         0x0900 | 
|  | 104 | #define DZ_B2400         0x0A00 | 
|  | 105 | #define DZ_B3600         0x0B00 | 
|  | 106 | #define DZ_B4800         0x0C00 | 
|  | 107 | #define DZ_B7200         0x0D00 | 
|  | 108 | #define DZ_B9600         0x0E00 | 
|  | 109 |  | 
|  | 110 | #define DZ_CREAD         0x1000               /* Enable receiver */ | 
|  | 111 | #define DZ_RXENAB        0x1000               /* enable receive char */ | 
|  | 112 | /* | 
|  | 113 | * Addresses for the DZ registers | 
|  | 114 | */ | 
|  | 115 | #define DZ_CSR       0x00            /* Control and Status Register */ | 
|  | 116 | #define DZ_RBUF      0x08            /* Receive Buffer */ | 
|  | 117 | #define DZ_LPR       0x08            /* Line Parameters Register */ | 
|  | 118 | #define DZ_TCR       0x10            /* Transmitter Control Register */ | 
|  | 119 | #define DZ_MSR       0x18            /* Modem Status Register */ | 
|  | 120 | #define DZ_TDR       0x18            /* Transmit Data Register */ | 
|  | 121 |  | 
|  | 122 | #define DZ_NB_PORT 4 | 
|  | 123 |  | 
|  | 124 | #define DZ_XMIT_SIZE   4096                 /* buffer size */ | 
|  | 125 | #define DZ_WAKEUP_CHARS   DZ_XMIT_SIZE/4 | 
|  | 126 |  | 
|  | 127 | #ifdef MODULE | 
|  | 128 | int init_module (void) | 
|  | 129 | void cleanup_module (void) | 
|  | 130 | #endif | 
|  | 131 |  | 
|  | 132 | #endif /* DZ_SERIAL_H */ |