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Arnd Bergmannae209cf2005-06-23 09:43:54 +10001/*
Arnd Bergmannf3f66f52005-10-31 20:08:37 -05002 * IOMMU implementation for Cell Broadband Processor Architecture
Arnd Bergmannae209cf2005-06-23 09:43:54 +10003 * We just establish a linear mapping at boot by setting all the
4 * IOPT cache entries in the CPU.
5 * The mapping functions should be identical to pci_direct_iommu,
6 * except for the handling of the high order bit that is required
7 * by the Spider bridge. These should be split into a separate
8 * file at the point where we get a different bridge chip.
9 *
10 * Copyright (C) 2005 IBM Deutschland Entwicklung GmbH,
11 * Arnd Bergmann <arndb@de.ibm.com>
12 *
13 * Based on linear mapping
14 * Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
15 *
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License
18 * as published by the Free Software Foundation; either version
19 * 2 of the License, or (at your option) any later version.
20 */
21
22#undef DEBUG
23
24#include <linux/kernel.h>
25#include <linux/pci.h>
26#include <linux/delay.h>
27#include <linux/string.h>
28#include <linux/init.h>
29#include <linux/bootmem.h>
30#include <linux/mm.h>
31#include <linux/dma-mapping.h>
Jens.Osterkamp@de.ibm.com49d65b32005-12-09 19:04:20 +010032#include <linux/kernel.h>
33#include <linux/compiler.h>
Arnd Bergmannae209cf2005-06-23 09:43:54 +100034
35#include <asm/sections.h>
36#include <asm/iommu.h>
37#include <asm/io.h>
38#include <asm/prom.h>
39#include <asm/pci-bridge.h>
40#include <asm/machdep.h>
41#include <asm/pmac_feature.h>
42#include <asm/abs_addr.h>
43#include <asm/system.h>
Stephen Rothwelld3878992005-09-28 02:50:25 +100044#include <asm/ppc-pci.h>
Jens.Osterkamp@de.ibm.com49d65b32005-12-09 19:04:20 +010045#include <asm/udbg.h>
Arnd Bergmannae209cf2005-06-23 09:43:54 +100046
Arnd Bergmannf3f66f52005-10-31 20:08:37 -050047#include "iommu.h"
Arnd Bergmannae209cf2005-06-23 09:43:54 +100048
Benjamin Herrenschmidtd03f3872006-11-11 17:25:09 +110049static dma_addr_t cell_dma_valid = SPIDER_DMA_VALID;
50
Arnd Bergmannae209cf2005-06-23 09:43:54 +100051static inline unsigned long
52get_iopt_entry(unsigned long real_address, unsigned long ioid,
53 unsigned long prot)
54{
55 return (prot & IOPT_PROT_MASK)
56 | (IOPT_COHERENT)
57 | (IOPT_ORDER_VC)
58 | (real_address & IOPT_RPN_MASK)
59 | (ioid & IOPT_IOID_MASK);
60}
61
62typedef struct {
63 unsigned long val;
64} ioste;
65
66static inline ioste
67mk_ioste(unsigned long val)
68{
69 ioste ioste = { .val = val, };
70 return ioste;
71}
72
73static inline ioste
74get_iost_entry(unsigned long iopt_base, unsigned long io_address, unsigned page_size)
75{
76 unsigned long ps;
77 unsigned long iostep;
78 unsigned long nnpt;
79 unsigned long shift;
80
81 switch (page_size) {
82 case 0x1000000:
83 ps = IOST_PS_16M;
84 nnpt = 0; /* one page per segment */
85 shift = 5; /* segment has 16 iopt entries */
86 break;
87
88 case 0x100000:
89 ps = IOST_PS_1M;
90 nnpt = 0; /* one page per segment */
91 shift = 1; /* segment has 256 iopt entries */
92 break;
93
94 case 0x10000:
95 ps = IOST_PS_64K;
96 nnpt = 0x07; /* 8 pages per io page table */
97 shift = 0; /* all entries are used */
98 break;
99
100 case 0x1000:
101 ps = IOST_PS_4K;
102 nnpt = 0x7f; /* 128 pages per io page table */
103 shift = 0; /* all entries are used */
104 break;
105
106 default: /* not a known compile time constant */
Al Viroc215a162005-09-30 03:36:50 +0100107 {
108 /* BUILD_BUG_ON() is not usable here */
109 extern void __get_iost_entry_bad_page_size(void);
110 __get_iost_entry_bad_page_size();
111 }
Arnd Bergmannae209cf2005-06-23 09:43:54 +1000112 break;
113 }
114
115 iostep = iopt_base +
116 /* need 8 bytes per iopte */
117 (((io_address / page_size * 8)
118 /* align io page tables on 4k page boundaries */
119 << shift)
120 /* nnpt+1 pages go into each iopt */
121 & ~(nnpt << 12));
122
123 nnpt++; /* this seems to work, but the documentation is not clear
124 about wether we put nnpt or nnpt-1 into the ioste bits.
125 In theory, this can't work for 4k pages. */
126 return mk_ioste(IOST_VALID_MASK
127 | (iostep & IOST_PT_BASE_MASK)
128 | ((nnpt << 5) & IOST_NNPT_MASK)
129 | (ps & IOST_PS_MASK));
130}
131
132/* compute the address of an io pte */
133static inline unsigned long
134get_ioptep(ioste iost_entry, unsigned long io_address)
135{
136 unsigned long iopt_base;
137 unsigned long page_size;
138 unsigned long page_number;
139 unsigned long iopt_offset;
140
141 iopt_base = iost_entry.val & IOST_PT_BASE_MASK;
142 page_size = iost_entry.val & IOST_PS_MASK;
143
144 /* decode page size to compute page number */
145 page_number = (io_address & 0x0fffffff) >> (10 + 2 * page_size);
146 /* page number is an offset into the io page table */
147 iopt_offset = (page_number << 3) & 0x7fff8ul;
148 return iopt_base + iopt_offset;
149}
150
151/* compute the tag field of the iopt cache entry */
152static inline unsigned long
153get_ioc_tag(ioste iost_entry, unsigned long io_address)
154{
155 unsigned long iopte = get_ioptep(iost_entry, io_address);
156
157 return IOPT_VALID_MASK
158 | ((iopte & 0x00000000000000ff8ul) >> 3)
159 | ((iopte & 0x0000003fffffc0000ul) >> 9);
160}
161
162/* compute the hashed 6 bit index for the 4-way associative pte cache */
163static inline unsigned long
164get_ioc_hash(ioste iost_entry, unsigned long io_address)
165{
166 unsigned long iopte = get_ioptep(iost_entry, io_address);
167
168 return ((iopte & 0x000000000000001f8ul) >> 3)
169 ^ ((iopte & 0x00000000000020000ul) >> 17)
170 ^ ((iopte & 0x00000000000010000ul) >> 15)
171 ^ ((iopte & 0x00000000000008000ul) >> 13)
172 ^ ((iopte & 0x00000000000004000ul) >> 11)
173 ^ ((iopte & 0x00000000000002000ul) >> 9)
174 ^ ((iopte & 0x00000000000001000ul) >> 7);
175}
176
177/* same as above, but pretend that we have a simpler 1-way associative
178 pte cache with an 8 bit index */
179static inline unsigned long
180get_ioc_hash_1way(ioste iost_entry, unsigned long io_address)
181{
182 unsigned long iopte = get_ioptep(iost_entry, io_address);
183
184 return ((iopte & 0x000000000000001f8ul) >> 3)
185 ^ ((iopte & 0x00000000000020000ul) >> 17)
186 ^ ((iopte & 0x00000000000010000ul) >> 15)
187 ^ ((iopte & 0x00000000000008000ul) >> 13)
188 ^ ((iopte & 0x00000000000004000ul) >> 11)
189 ^ ((iopte & 0x00000000000002000ul) >> 9)
190 ^ ((iopte & 0x00000000000001000ul) >> 7)
191 ^ ((iopte & 0x0000000000000c000ul) >> 8);
192}
193
194static inline ioste
195get_iost_cache(void __iomem *base, unsigned long index)
196{
197 unsigned long __iomem *p = (base + IOC_ST_CACHE_DIR);
198 return mk_ioste(in_be64(&p[index]));
199}
200
201static inline void
202set_iost_cache(void __iomem *base, unsigned long index, ioste ste)
203{
204 unsigned long __iomem *p = (base + IOC_ST_CACHE_DIR);
205 pr_debug("ioste %02lx was %016lx, store %016lx", index,
206 get_iost_cache(base, index).val, ste.val);
207 out_be64(&p[index], ste.val);
208 pr_debug(" now %016lx\n", get_iost_cache(base, index).val);
209}
210
211static inline unsigned long
212get_iopt_cache(void __iomem *base, unsigned long index, unsigned long *tag)
213{
214 unsigned long __iomem *tags = (void *)(base + IOC_PT_CACHE_DIR);
215 unsigned long __iomem *p = (void *)(base + IOC_PT_CACHE_REG);
216
217 *tag = tags[index];
218 rmb();
219 return *p;
220}
221
222static inline void
223set_iopt_cache(void __iomem *base, unsigned long index,
224 unsigned long tag, unsigned long val)
225{
226 unsigned long __iomem *tags = base + IOC_PT_CACHE_DIR;
227 unsigned long __iomem *p = base + IOC_PT_CACHE_REG;
Arnd Bergmannae209cf2005-06-23 09:43:54 +1000228
229 out_be64(p, val);
230 out_be64(&tags[index], tag);
231}
232
233static inline void
234set_iost_origin(void __iomem *base)
235{
236 unsigned long __iomem *p = base + IOC_ST_ORIGIN;
237 unsigned long origin = IOSTO_ENABLE | IOSTO_SW;
238
239 pr_debug("iost_origin %016lx, now %016lx\n", in_be64(p), origin);
240 out_be64(p, origin);
241}
242
243static inline void
244set_iocmd_config(void __iomem *base)
245{
246 unsigned long __iomem *p = base + 0xc00;
247 unsigned long conf;
248
249 conf = in_be64(p);
250 pr_debug("iost_conf %016lx, now %016lx\n", conf, conf | IOCMD_CONF_TE);
251 out_be64(p, conf | IOCMD_CONF_TE);
252}
253
Jens.Osterkamp@de.ibm.com49d65b32005-12-09 19:04:20 +0100254static void enable_mapping(void __iomem *base, void __iomem *mmio_base)
Arnd Bergmannae209cf2005-06-23 09:43:54 +1000255{
Jens.Osterkamp@de.ibm.com49d65b32005-12-09 19:04:20 +0100256 set_iocmd_config(base);
257 set_iost_origin(mmio_base);
Arnd Bergmannae209cf2005-06-23 09:43:54 +1000258}
259
Jens.Osterkamp@de.ibm.com49d65b32005-12-09 19:04:20 +0100260struct cell_iommu {
261 unsigned long base;
262 unsigned long mmio_base;
263 void __iomem *mapped_base;
264 void __iomem *mapped_mmio_base;
265};
266
267static struct cell_iommu cell_iommus[NR_CPUS];
Arnd Bergmannae209cf2005-06-23 09:43:54 +1000268
269/* initialize the iommu to support a simple linear mapping
270 * for each DMA window used by any device. For now, we
271 * happen to know that there is only one DMA window in use,
272 * starting at iopt_phys_offset. */
Jens.Osterkamp@de.ibm.com49d65b32005-12-09 19:04:20 +0100273static void cell_do_map_iommu(struct cell_iommu *iommu,
274 unsigned int ioid,
275 unsigned long map_start,
276 unsigned long map_size)
Arnd Bergmannae209cf2005-06-23 09:43:54 +1000277{
Jens.Osterkamp@de.ibm.com49d65b32005-12-09 19:04:20 +0100278 unsigned long io_address, real_address;
279 void __iomem *ioc_base, *ioc_mmio_base;
Arnd Bergmannae209cf2005-06-23 09:43:54 +1000280 ioste ioste;
281 unsigned long index;
282
Jens.Osterkamp@de.ibm.com49d65b32005-12-09 19:04:20 +0100283 /* we pretend the io page table was at a very high address */
284 const unsigned long fake_iopt = 0x10000000000ul;
285 const unsigned long io_page_size = 0x1000000; /* use 16M pages */
286 const unsigned long io_segment_size = 0x10000000; /* 256M */
Arnd Bergmannae209cf2005-06-23 09:43:54 +1000287
Jens.Osterkamp@de.ibm.com49d65b32005-12-09 19:04:20 +0100288 ioc_base = iommu->mapped_base;
289 ioc_mmio_base = iommu->mapped_mmio_base;
Arnd Bergmannae209cf2005-06-23 09:43:54 +1000290
Arnd Bergmann5fa500b2006-03-23 00:00:04 +0100291 for (real_address = 0, io_address = map_start;
Jens.Osterkamp@de.ibm.com49d65b32005-12-09 19:04:20 +0100292 io_address <= map_start + map_size;
293 real_address += io_page_size, io_address += io_page_size) {
294 ioste = get_iost_entry(fake_iopt, io_address, io_page_size);
295 if ((real_address % io_segment_size) == 0) /* segment start */
296 set_iost_cache(ioc_mmio_base,
297 io_address >> 28, ioste);
298 index = get_ioc_hash_1way(ioste, io_address);
Arnd Bergmannae209cf2005-06-23 09:43:54 +1000299 pr_debug("addr %08lx, index %02lx, ioste %016lx\n",
Jens.Osterkamp@de.ibm.com49d65b32005-12-09 19:04:20 +0100300 io_address, index, ioste.val);
301 set_iopt_cache(ioc_mmio_base,
302 get_ioc_hash_1way(ioste, io_address),
303 get_ioc_tag(ioste, io_address),
Arnd Bergmann5fa500b2006-03-23 00:00:04 +0100304 get_iopt_entry(real_address, ioid, IOPT_PROT_RW));
Arnd Bergmannae209cf2005-06-23 09:43:54 +1000305 }
Arnd Bergmannae209cf2005-06-23 09:43:54 +1000306}
307
Benjamin Herrenschmidt12d04ee2006-11-11 17:25:02 +1100308static void pci_dma_cell_bus_setup(struct pci_bus *b)
Jens.Osterkamp@de.ibm.com49d65b32005-12-09 19:04:20 +0100309{
Jeremy Kerrc61c27d2006-07-12 15:39:54 +1000310 const unsigned int *ioid;
311 unsigned long map_start, map_size, token;
312 const unsigned long *dma_window;
Jens.Osterkamp@de.ibm.com49d65b32005-12-09 19:04:20 +0100313 struct cell_iommu *iommu;
Benjamin Herrenschmidt12d04ee2006-11-11 17:25:02 +1100314 struct device_node *d;
315
316 d = pci_bus_to_OF_node(b);
Jens.Osterkamp@de.ibm.com49d65b32005-12-09 19:04:20 +0100317
Jeremy Kerrc61c27d2006-07-12 15:39:54 +1000318 ioid = get_property(d, "ioid", NULL);
Jens.Osterkamp@de.ibm.com49d65b32005-12-09 19:04:20 +0100319 if (!ioid)
320 pr_debug("No ioid entry found !\n");
321
Jeremy Kerrc61c27d2006-07-12 15:39:54 +1000322 dma_window = get_property(d, "ibm,dma-window", NULL);
Jens.Osterkamp@de.ibm.com49d65b32005-12-09 19:04:20 +0100323 if (!dma_window)
324 pr_debug("No ibm,dma-window entry found !\n");
325
326 map_start = dma_window[1];
327 map_size = dma_window[2];
328 token = dma_window[0] >> 32;
329
330 iommu = &cell_iommus[token];
331
332 cell_do_map_iommu(iommu, *ioid, map_start, map_size);
333}
334
Jens.Osterkamp@de.ibm.com49d65b32005-12-09 19:04:20 +0100335
336static int cell_map_iommu_hardcoded(int num_nodes)
337{
338 struct cell_iommu *iommu = NULL;
339
340 pr_debug("%s(%d): Using hardcoded defaults\n", __FUNCTION__, __LINE__);
341
342 /* node 0 */
343 iommu = &cell_iommus[0];
Arnd Bergmann43b4f402006-10-04 17:26:24 +0200344 iommu->mapped_base = ioremap(0x20000511000ul, 0x1000);
345 iommu->mapped_mmio_base = ioremap(0x20000510000ul, 0x1000);
Jens.Osterkamp@de.ibm.com49d65b32005-12-09 19:04:20 +0100346
347 enable_mapping(iommu->mapped_base, iommu->mapped_mmio_base);
348
349 cell_do_map_iommu(iommu, 0x048a,
350 0x20000000ul,0x20000000ul);
351
352 if (num_nodes < 2)
353 return 0;
354
355 /* node 1 */
356 iommu = &cell_iommus[1];
Arnd Bergmann43b4f402006-10-04 17:26:24 +0200357 iommu->mapped_base = ioremap(0x30000511000ul, 0x1000);
358 iommu->mapped_mmio_base = ioremap(0x30000510000ul, 0x1000);
Jens.Osterkamp@de.ibm.com49d65b32005-12-09 19:04:20 +0100359
360 enable_mapping(iommu->mapped_base, iommu->mapped_mmio_base);
361
362 cell_do_map_iommu(iommu, 0x048a,
363 0x20000000,0x20000000ul);
364
365 return 0;
366}
367
368
369static int cell_map_iommu(void)
370{
Jeremy Kerrc61c27d2006-07-12 15:39:54 +1000371 unsigned int num_nodes = 0;
372 const unsigned int *node_id;
373 const unsigned long *base, *mmio_base;
Jens.Osterkamp@de.ibm.com49d65b32005-12-09 19:04:20 +0100374 struct device_node *dn;
375 struct cell_iommu *iommu = NULL;
376
377 /* determine number of nodes (=iommus) */
378 pr_debug("%s(%d): determining number of nodes...", __FUNCTION__, __LINE__);
379 for(dn = of_find_node_by_type(NULL, "cpu");
380 dn;
381 dn = of_find_node_by_type(dn, "cpu")) {
Jeremy Kerrc61c27d2006-07-12 15:39:54 +1000382 node_id = get_property(dn, "node-id", NULL);
Jens.Osterkamp@de.ibm.com49d65b32005-12-09 19:04:20 +0100383
384 if (num_nodes < *node_id)
385 num_nodes = *node_id;
386 }
387
388 num_nodes++;
389 pr_debug("%i found.\n", num_nodes);
390
391 /* map the iommu registers for each node */
392 pr_debug("%s(%d): Looping through nodes\n", __FUNCTION__, __LINE__);
393 for(dn = of_find_node_by_type(NULL, "cpu");
394 dn;
395 dn = of_find_node_by_type(dn, "cpu")) {
396
Jeremy Kerrc61c27d2006-07-12 15:39:54 +1000397 node_id = get_property(dn, "node-id", NULL);
398 base = get_property(dn, "ioc-cache", NULL);
399 mmio_base = get_property(dn, "ioc-translation", NULL);
Jens.Osterkamp@de.ibm.com49d65b32005-12-09 19:04:20 +0100400
401 if (!base || !mmio_base || !node_id)
402 return cell_map_iommu_hardcoded(num_nodes);
403
404 iommu = &cell_iommus[*node_id];
405 iommu->base = *base;
406 iommu->mmio_base = *mmio_base;
407
Arnd Bergmann47952d52006-03-24 19:47:52 +0100408 iommu->mapped_base = ioremap(*base, 0x1000);
409 iommu->mapped_mmio_base = ioremap(*mmio_base, 0x1000);
Jens.Osterkamp@de.ibm.com49d65b32005-12-09 19:04:20 +0100410
411 enable_mapping(iommu->mapped_base,
412 iommu->mapped_mmio_base);
413
414 /* everything else will be done in iommu_bus_setup */
415 }
416
417 return 1;
418}
Arnd Bergmannae209cf2005-06-23 09:43:54 +1000419
Arnd Bergmannf3f66f52005-10-31 20:08:37 -0500420static void *cell_alloc_coherent(struct device *hwdev, size_t size,
Al Virodd0fc662005-10-07 07:46:04 +0100421 dma_addr_t *dma_handle, gfp_t flag)
Arnd Bergmannae209cf2005-06-23 09:43:54 +1000422{
423 void *ret;
424
425 ret = (void *)__get_free_pages(flag, get_order(size));
426 if (ret != NULL) {
427 memset(ret, 0, size);
Benjamin Herrenschmidtd03f3872006-11-11 17:25:09 +1100428 *dma_handle = virt_to_abs(ret) | cell_dma_valid;
Arnd Bergmannae209cf2005-06-23 09:43:54 +1000429 }
430 return ret;
431}
432
Arnd Bergmannf3f66f52005-10-31 20:08:37 -0500433static void cell_free_coherent(struct device *hwdev, size_t size,
Arnd Bergmannae209cf2005-06-23 09:43:54 +1000434 void *vaddr, dma_addr_t dma_handle)
435{
436 free_pages((unsigned long)vaddr, get_order(size));
437}
438
Arnd Bergmannf3f66f52005-10-31 20:08:37 -0500439static dma_addr_t cell_map_single(struct device *hwdev, void *ptr,
Arnd Bergmannae209cf2005-06-23 09:43:54 +1000440 size_t size, enum dma_data_direction direction)
441{
Benjamin Herrenschmidtd03f3872006-11-11 17:25:09 +1100442 return virt_to_abs(ptr) | cell_dma_valid;
Arnd Bergmannae209cf2005-06-23 09:43:54 +1000443}
444
Arnd Bergmannf3f66f52005-10-31 20:08:37 -0500445static void cell_unmap_single(struct device *hwdev, dma_addr_t dma_addr,
Arnd Bergmannae209cf2005-06-23 09:43:54 +1000446 size_t size, enum dma_data_direction direction)
447{
448}
449
Arnd Bergmannf3f66f52005-10-31 20:08:37 -0500450static int cell_map_sg(struct device *hwdev, struct scatterlist *sg,
Arnd Bergmannae209cf2005-06-23 09:43:54 +1000451 int nents, enum dma_data_direction direction)
452{
453 int i;
454
455 for (i = 0; i < nents; i++, sg++) {
456 sg->dma_address = (page_to_phys(sg->page) + sg->offset)
Benjamin Herrenschmidtd03f3872006-11-11 17:25:09 +1100457 | cell_dma_valid;
Arnd Bergmannae209cf2005-06-23 09:43:54 +1000458 sg->dma_length = sg->length;
459 }
460
461 return nents;
462}
463
Arnd Bergmannf3f66f52005-10-31 20:08:37 -0500464static void cell_unmap_sg(struct device *hwdev, struct scatterlist *sg,
Arnd Bergmannae209cf2005-06-23 09:43:54 +1000465 int nents, enum dma_data_direction direction)
466{
467}
468
Arnd Bergmannf3f66f52005-10-31 20:08:37 -0500469static int cell_dma_supported(struct device *dev, u64 mask)
Arnd Bergmannae209cf2005-06-23 09:43:54 +1000470{
471 return mask < 0x100000000ull;
472}
473
Anton Blancharddf310652006-06-10 23:04:39 +1000474static struct dma_mapping_ops cell_iommu_ops = {
475 .alloc_coherent = cell_alloc_coherent,
476 .free_coherent = cell_free_coherent,
477 .map_single = cell_map_single,
478 .unmap_single = cell_unmap_single,
479 .map_sg = cell_map_sg,
480 .unmap_sg = cell_unmap_sg,
481 .dma_supported = cell_dma_supported,
482};
483
Arnd Bergmannf3f66f52005-10-31 20:08:37 -0500484void cell_init_iommu(void)
Arnd Bergmannae209cf2005-06-23 09:43:54 +1000485{
Jens.Osterkamp@de.ibm.com49d65b32005-12-09 19:04:20 +0100486 int setup_bus = 0;
Arnd Bergmannae209cf2005-06-23 09:43:54 +1000487
Benjamin Herrenschmidtd03f3872006-11-11 17:25:09 +1100488 /* If we have an Axon bridge, clear the DMA valid mask. This is fairly
489 * hackish but will work well enough until we have proper iommu code.
490 */
491 if (of_find_node_by_name(NULL, "axon"))
492 cell_dma_valid = 0;
493
Jens.Osterkamp@de.ibm.com49d65b32005-12-09 19:04:20 +0100494 if (of_find_node_by_path("/mambo")) {
495 pr_info("Not using iommu on systemsim\n");
496 } else {
497
498 if (!(of_chosen &&
499 get_property(of_chosen, "linux,iommu-off", NULL)))
500 setup_bus = cell_map_iommu();
501
502 if (setup_bus) {
503 pr_debug("%s: IOMMU mapping activated\n", __FUNCTION__);
Benjamin Herrenschmidt12d04ee2006-11-11 17:25:02 +1100504 ppc_md.pci_dma_bus_setup = pci_dma_cell_bus_setup;
Jens.Osterkamp@de.ibm.com49d65b32005-12-09 19:04:20 +0100505 } else {
506 pr_debug("%s: IOMMU mapping activated, "
507 "no device action necessary\n", __FUNCTION__);
508 /* Direct I/O, IOMMU off */
Jens.Osterkamp@de.ibm.com49d65b32005-12-09 19:04:20 +0100509 }
510 }
Arnd Bergmannae209cf2005-06-23 09:43:54 +1000511
Benjamin Herrenschmidt12d04ee2006-11-11 17:25:02 +1100512 pci_dma_ops = &cell_iommu_ops;
Arnd Bergmannae209cf2005-06-23 09:43:54 +1000513}