blob: a2a3fa5999236c70f5c14ec91456fb52f644e044 [file] [log] [blame]
Eric Anholt673a3942008-07-30 12:06:12 -07001/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include "drmP.h"
29#include "drm.h"
30#include "i915_drm.h"
31#include "i915_drv.h"
Chris Wilson1c5d22f2009-08-25 11:15:50 +010032#include "i915_trace.h"
Jesse Barnes652c3932009-08-17 13:31:43 -070033#include "intel_drv.h"
Eric Anholt673a3942008-07-30 12:06:12 -070034#include <linux/swap.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080035#include <linux/pci.h>
Eric Anholt673a3942008-07-30 12:06:12 -070036
Eric Anholt28dfe522008-11-13 15:00:55 -080037#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
38
Eric Anholte47c68e2008-11-14 13:35:19 -080039static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
40static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
41static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
Eric Anholte47c68e2008-11-14 13:35:19 -080042static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
43 int write);
44static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
45 uint64_t offset,
46 uint64_t size);
47static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
Eric Anholt673a3942008-07-30 12:06:12 -070048static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
Jesse Barnesde151cf2008-11-12 10:03:55 -080049static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
50 unsigned alignment);
Jesse Barnesde151cf2008-11-12 10:03:55 -080051static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
Chris Wilson07f73f62009-09-14 16:50:30 +010052static int i915_gem_evict_something(struct drm_device *dev, int min_size);
Chris Wilsonab5ee572009-09-20 19:25:47 +010053static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
Dave Airlie71acb5e2008-12-30 20:31:46 +100054static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
55 struct drm_i915_gem_pwrite *args,
56 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -070057
Chris Wilson31169712009-09-14 16:50:28 +010058static LIST_HEAD(shrink_list);
59static DEFINE_SPINLOCK(shrink_list_lock);
60
Jesse Barnes79e53942008-11-07 14:24:08 -080061int i915_gem_do_init(struct drm_device *dev, unsigned long start,
62 unsigned long end)
63{
64 drm_i915_private_t *dev_priv = dev->dev_private;
65
66 if (start >= end ||
67 (start & (PAGE_SIZE - 1)) != 0 ||
68 (end & (PAGE_SIZE - 1)) != 0) {
69 return -EINVAL;
70 }
71
72 drm_mm_init(&dev_priv->mm.gtt_space, start,
73 end - start);
74
75 dev->gtt_total = (uint32_t) (end - start);
76
77 return 0;
78}
Keith Packard6dbe2772008-10-14 21:41:13 -070079
Eric Anholt673a3942008-07-30 12:06:12 -070080int
81i915_gem_init_ioctl(struct drm_device *dev, void *data,
82 struct drm_file *file_priv)
83{
Eric Anholt673a3942008-07-30 12:06:12 -070084 struct drm_i915_gem_init *args = data;
Jesse Barnes79e53942008-11-07 14:24:08 -080085 int ret;
Eric Anholt673a3942008-07-30 12:06:12 -070086
87 mutex_lock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -080088 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
Eric Anholt673a3942008-07-30 12:06:12 -070089 mutex_unlock(&dev->struct_mutex);
90
Jesse Barnes79e53942008-11-07 14:24:08 -080091 return ret;
Eric Anholt673a3942008-07-30 12:06:12 -070092}
93
Eric Anholt5a125c32008-10-22 21:40:13 -070094int
95i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
96 struct drm_file *file_priv)
97{
Eric Anholt5a125c32008-10-22 21:40:13 -070098 struct drm_i915_gem_get_aperture *args = data;
Eric Anholt5a125c32008-10-22 21:40:13 -070099
100 if (!(dev->driver->driver_features & DRIVER_GEM))
101 return -ENODEV;
102
103 args->aper_size = dev->gtt_total;
Keith Packard2678d9d2008-11-20 22:54:54 -0800104 args->aper_available_size = (args->aper_size -
105 atomic_read(&dev->pin_memory));
Eric Anholt5a125c32008-10-22 21:40:13 -0700106
107 return 0;
108}
109
Eric Anholt673a3942008-07-30 12:06:12 -0700110
111/**
112 * Creates a new mm object and returns a handle to it.
113 */
114int
115i915_gem_create_ioctl(struct drm_device *dev, void *data,
116 struct drm_file *file_priv)
117{
118 struct drm_i915_gem_create *args = data;
119 struct drm_gem_object *obj;
Pekka Paalanena1a2d1d2009-08-23 12:40:55 +0300120 int ret;
121 u32 handle;
Eric Anholt673a3942008-07-30 12:06:12 -0700122
123 args->size = roundup(args->size, PAGE_SIZE);
124
125 /* Allocate the new object */
126 obj = drm_gem_object_alloc(dev, args->size);
127 if (obj == NULL)
128 return -ENOMEM;
129
130 ret = drm_gem_handle_create(file_priv, obj, &handle);
131 mutex_lock(&dev->struct_mutex);
132 drm_gem_object_handle_unreference(obj);
133 mutex_unlock(&dev->struct_mutex);
134
135 if (ret)
136 return ret;
137
138 args->handle = handle;
139
140 return 0;
141}
142
Eric Anholt40123c12009-03-09 13:42:30 -0700143static inline int
Eric Anholteb014592009-03-10 11:44:52 -0700144fast_shmem_read(struct page **pages,
145 loff_t page_base, int page_offset,
146 char __user *data,
147 int length)
148{
149 char __iomem *vaddr;
Florian Mickler2bc43b52009-04-06 22:55:41 +0200150 int unwritten;
Eric Anholteb014592009-03-10 11:44:52 -0700151
152 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
153 if (vaddr == NULL)
154 return -ENOMEM;
Florian Mickler2bc43b52009-04-06 22:55:41 +0200155 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
Eric Anholteb014592009-03-10 11:44:52 -0700156 kunmap_atomic(vaddr, KM_USER0);
157
Florian Mickler2bc43b52009-04-06 22:55:41 +0200158 if (unwritten)
159 return -EFAULT;
160
161 return 0;
Eric Anholteb014592009-03-10 11:44:52 -0700162}
163
Eric Anholt280b7132009-03-12 16:56:27 -0700164static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
165{
166 drm_i915_private_t *dev_priv = obj->dev->dev_private;
167 struct drm_i915_gem_object *obj_priv = obj->driver_private;
168
169 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
170 obj_priv->tiling_mode != I915_TILING_NONE;
171}
172
Eric Anholteb014592009-03-10 11:44:52 -0700173static inline int
Eric Anholt40123c12009-03-09 13:42:30 -0700174slow_shmem_copy(struct page *dst_page,
175 int dst_offset,
176 struct page *src_page,
177 int src_offset,
178 int length)
179{
180 char *dst_vaddr, *src_vaddr;
181
182 dst_vaddr = kmap_atomic(dst_page, KM_USER0);
183 if (dst_vaddr == NULL)
184 return -ENOMEM;
185
186 src_vaddr = kmap_atomic(src_page, KM_USER1);
187 if (src_vaddr == NULL) {
188 kunmap_atomic(dst_vaddr, KM_USER0);
189 return -ENOMEM;
190 }
191
192 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
193
194 kunmap_atomic(src_vaddr, KM_USER1);
195 kunmap_atomic(dst_vaddr, KM_USER0);
196
197 return 0;
198}
199
Eric Anholt280b7132009-03-12 16:56:27 -0700200static inline int
201slow_shmem_bit17_copy(struct page *gpu_page,
202 int gpu_offset,
203 struct page *cpu_page,
204 int cpu_offset,
205 int length,
206 int is_read)
207{
208 char *gpu_vaddr, *cpu_vaddr;
209
210 /* Use the unswizzled path if this page isn't affected. */
211 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
212 if (is_read)
213 return slow_shmem_copy(cpu_page, cpu_offset,
214 gpu_page, gpu_offset, length);
215 else
216 return slow_shmem_copy(gpu_page, gpu_offset,
217 cpu_page, cpu_offset, length);
218 }
219
220 gpu_vaddr = kmap_atomic(gpu_page, KM_USER0);
221 if (gpu_vaddr == NULL)
222 return -ENOMEM;
223
224 cpu_vaddr = kmap_atomic(cpu_page, KM_USER1);
225 if (cpu_vaddr == NULL) {
226 kunmap_atomic(gpu_vaddr, KM_USER0);
227 return -ENOMEM;
228 }
229
230 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
231 * XORing with the other bits (A9 for Y, A9 and A10 for X)
232 */
233 while (length > 0) {
234 int cacheline_end = ALIGN(gpu_offset + 1, 64);
235 int this_length = min(cacheline_end - gpu_offset, length);
236 int swizzled_gpu_offset = gpu_offset ^ 64;
237
238 if (is_read) {
239 memcpy(cpu_vaddr + cpu_offset,
240 gpu_vaddr + swizzled_gpu_offset,
241 this_length);
242 } else {
243 memcpy(gpu_vaddr + swizzled_gpu_offset,
244 cpu_vaddr + cpu_offset,
245 this_length);
246 }
247 cpu_offset += this_length;
248 gpu_offset += this_length;
249 length -= this_length;
250 }
251
252 kunmap_atomic(cpu_vaddr, KM_USER1);
253 kunmap_atomic(gpu_vaddr, KM_USER0);
254
255 return 0;
256}
257
Eric Anholt673a3942008-07-30 12:06:12 -0700258/**
Eric Anholteb014592009-03-10 11:44:52 -0700259 * This is the fast shmem pread path, which attempts to copy_from_user directly
260 * from the backing pages of the object to the user's address space. On a
261 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
262 */
263static int
264i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
265 struct drm_i915_gem_pread *args,
266 struct drm_file *file_priv)
267{
268 struct drm_i915_gem_object *obj_priv = obj->driver_private;
269 ssize_t remain;
270 loff_t offset, page_base;
271 char __user *user_data;
272 int page_offset, page_length;
273 int ret;
274
275 user_data = (char __user *) (uintptr_t) args->data_ptr;
276 remain = args->size;
277
278 mutex_lock(&dev->struct_mutex);
279
280 ret = i915_gem_object_get_pages(obj);
281 if (ret != 0)
282 goto fail_unlock;
283
284 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
285 args->size);
286 if (ret != 0)
287 goto fail_put_pages;
288
289 obj_priv = obj->driver_private;
290 offset = args->offset;
291
292 while (remain > 0) {
293 /* Operation in this page
294 *
295 * page_base = page offset within aperture
296 * page_offset = offset within page
297 * page_length = bytes to copy for this page
298 */
299 page_base = (offset & ~(PAGE_SIZE-1));
300 page_offset = offset & (PAGE_SIZE-1);
301 page_length = remain;
302 if ((page_offset + remain) > PAGE_SIZE)
303 page_length = PAGE_SIZE - page_offset;
304
305 ret = fast_shmem_read(obj_priv->pages,
306 page_base, page_offset,
307 user_data, page_length);
308 if (ret)
309 goto fail_put_pages;
310
311 remain -= page_length;
312 user_data += page_length;
313 offset += page_length;
314 }
315
316fail_put_pages:
317 i915_gem_object_put_pages(obj);
318fail_unlock:
319 mutex_unlock(&dev->struct_mutex);
320
321 return ret;
322}
323
Chris Wilson07f73f62009-09-14 16:50:30 +0100324static inline gfp_t
325i915_gem_object_get_page_gfp_mask (struct drm_gem_object *obj)
326{
327 return mapping_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping);
328}
329
330static inline void
331i915_gem_object_set_page_gfp_mask (struct drm_gem_object *obj, gfp_t gfp)
332{
333 mapping_set_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping, gfp);
334}
335
336static int
337i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
338{
339 int ret;
340
341 ret = i915_gem_object_get_pages(obj);
342
343 /* If we've insufficient memory to map in the pages, attempt
344 * to make some space by throwing out some old buffers.
345 */
346 if (ret == -ENOMEM) {
347 struct drm_device *dev = obj->dev;
348 gfp_t gfp;
349
350 ret = i915_gem_evict_something(dev, obj->size);
351 if (ret)
352 return ret;
353
354 gfp = i915_gem_object_get_page_gfp_mask(obj);
355 i915_gem_object_set_page_gfp_mask(obj, gfp & ~__GFP_NORETRY);
356 ret = i915_gem_object_get_pages(obj);
357 i915_gem_object_set_page_gfp_mask (obj, gfp);
358 }
359
360 return ret;
361}
362
Eric Anholteb014592009-03-10 11:44:52 -0700363/**
364 * This is the fallback shmem pread path, which allocates temporary storage
365 * in kernel space to copy_to_user into outside of the struct_mutex, so we
366 * can copy out of the object's backing pages while holding the struct mutex
367 * and not take page faults.
368 */
369static int
370i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
371 struct drm_i915_gem_pread *args,
372 struct drm_file *file_priv)
373{
374 struct drm_i915_gem_object *obj_priv = obj->driver_private;
375 struct mm_struct *mm = current->mm;
376 struct page **user_pages;
377 ssize_t remain;
378 loff_t offset, pinned_pages, i;
379 loff_t first_data_page, last_data_page, num_pages;
380 int shmem_page_index, shmem_page_offset;
381 int data_page_index, data_page_offset;
382 int page_length;
383 int ret;
384 uint64_t data_ptr = args->data_ptr;
Eric Anholt280b7132009-03-12 16:56:27 -0700385 int do_bit17_swizzling;
Eric Anholteb014592009-03-10 11:44:52 -0700386
387 remain = args->size;
388
389 /* Pin the user pages containing the data. We can't fault while
390 * holding the struct mutex, yet we want to hold it while
391 * dereferencing the user data.
392 */
393 first_data_page = data_ptr / PAGE_SIZE;
394 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
395 num_pages = last_data_page - first_data_page + 1;
396
Jesse Barnes8e7d2b22009-05-08 16:13:25 -0700397 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
Eric Anholteb014592009-03-10 11:44:52 -0700398 if (user_pages == NULL)
399 return -ENOMEM;
400
401 down_read(&mm->mmap_sem);
402 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
Eric Anholte5e9ecd2009-04-07 16:01:22 -0700403 num_pages, 1, 0, user_pages, NULL);
Eric Anholteb014592009-03-10 11:44:52 -0700404 up_read(&mm->mmap_sem);
405 if (pinned_pages < num_pages) {
406 ret = -EFAULT;
407 goto fail_put_user_pages;
408 }
409
Eric Anholt280b7132009-03-12 16:56:27 -0700410 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
411
Eric Anholteb014592009-03-10 11:44:52 -0700412 mutex_lock(&dev->struct_mutex);
413
Chris Wilson07f73f62009-09-14 16:50:30 +0100414 ret = i915_gem_object_get_pages_or_evict(obj);
415 if (ret)
Eric Anholteb014592009-03-10 11:44:52 -0700416 goto fail_unlock;
417
418 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
419 args->size);
420 if (ret != 0)
421 goto fail_put_pages;
422
423 obj_priv = obj->driver_private;
424 offset = args->offset;
425
426 while (remain > 0) {
427 /* Operation in this page
428 *
429 * shmem_page_index = page number within shmem file
430 * shmem_page_offset = offset within page in shmem file
431 * data_page_index = page number in get_user_pages return
432 * data_page_offset = offset with data_page_index page.
433 * page_length = bytes to copy for this page
434 */
435 shmem_page_index = offset / PAGE_SIZE;
436 shmem_page_offset = offset & ~PAGE_MASK;
437 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
438 data_page_offset = data_ptr & ~PAGE_MASK;
439
440 page_length = remain;
441 if ((shmem_page_offset + page_length) > PAGE_SIZE)
442 page_length = PAGE_SIZE - shmem_page_offset;
443 if ((data_page_offset + page_length) > PAGE_SIZE)
444 page_length = PAGE_SIZE - data_page_offset;
445
Eric Anholt280b7132009-03-12 16:56:27 -0700446 if (do_bit17_swizzling) {
447 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
448 shmem_page_offset,
449 user_pages[data_page_index],
450 data_page_offset,
451 page_length,
452 1);
453 } else {
454 ret = slow_shmem_copy(user_pages[data_page_index],
455 data_page_offset,
456 obj_priv->pages[shmem_page_index],
457 shmem_page_offset,
458 page_length);
459 }
Eric Anholteb014592009-03-10 11:44:52 -0700460 if (ret)
461 goto fail_put_pages;
462
463 remain -= page_length;
464 data_ptr += page_length;
465 offset += page_length;
466 }
467
468fail_put_pages:
469 i915_gem_object_put_pages(obj);
470fail_unlock:
471 mutex_unlock(&dev->struct_mutex);
472fail_put_user_pages:
473 for (i = 0; i < pinned_pages; i++) {
474 SetPageDirty(user_pages[i]);
475 page_cache_release(user_pages[i]);
476 }
Jesse Barnes8e7d2b22009-05-08 16:13:25 -0700477 drm_free_large(user_pages);
Eric Anholteb014592009-03-10 11:44:52 -0700478
479 return ret;
480}
481
Eric Anholt673a3942008-07-30 12:06:12 -0700482/**
483 * Reads data from the object referenced by handle.
484 *
485 * On error, the contents of *data are undefined.
486 */
487int
488i915_gem_pread_ioctl(struct drm_device *dev, void *data,
489 struct drm_file *file_priv)
490{
491 struct drm_i915_gem_pread *args = data;
492 struct drm_gem_object *obj;
493 struct drm_i915_gem_object *obj_priv;
Eric Anholt673a3942008-07-30 12:06:12 -0700494 int ret;
495
496 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
497 if (obj == NULL)
498 return -EBADF;
499 obj_priv = obj->driver_private;
500
501 /* Bounds check source.
502 *
503 * XXX: This could use review for overflow issues...
504 */
505 if (args->offset > obj->size || args->size > obj->size ||
506 args->offset + args->size > obj->size) {
507 drm_gem_object_unreference(obj);
508 return -EINVAL;
509 }
510
Eric Anholt280b7132009-03-12 16:56:27 -0700511 if (i915_gem_object_needs_bit17_swizzle(obj)) {
Eric Anholteb014592009-03-10 11:44:52 -0700512 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
Eric Anholt280b7132009-03-12 16:56:27 -0700513 } else {
514 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
515 if (ret != 0)
516 ret = i915_gem_shmem_pread_slow(dev, obj, args,
517 file_priv);
518 }
Eric Anholt673a3942008-07-30 12:06:12 -0700519
520 drm_gem_object_unreference(obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700521
Eric Anholteb014592009-03-10 11:44:52 -0700522 return ret;
Eric Anholt673a3942008-07-30 12:06:12 -0700523}
524
Keith Packard0839ccb2008-10-30 19:38:48 -0700525/* This is the fast write path which cannot handle
526 * page faults in the source data
Linus Torvalds9b7530cc2008-10-20 14:16:43 -0700527 */
Linus Torvalds9b7530cc2008-10-20 14:16:43 -0700528
Keith Packard0839ccb2008-10-30 19:38:48 -0700529static inline int
530fast_user_write(struct io_mapping *mapping,
531 loff_t page_base, int page_offset,
532 char __user *user_data,
533 int length)
534{
535 char *vaddr_atomic;
536 unsigned long unwritten;
537
538 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
539 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
540 user_data, length);
541 io_mapping_unmap_atomic(vaddr_atomic);
542 if (unwritten)
543 return -EFAULT;
Linus Torvalds9b7530cc2008-10-20 14:16:43 -0700544 return 0;
Keith Packard0839ccb2008-10-30 19:38:48 -0700545}
546
547/* Here's the write path which can sleep for
548 * page faults
549 */
550
551static inline int
Eric Anholt3de09aa2009-03-09 09:42:23 -0700552slow_kernel_write(struct io_mapping *mapping,
553 loff_t gtt_base, int gtt_offset,
554 struct page *user_page, int user_offset,
555 int length)
Keith Packard0839ccb2008-10-30 19:38:48 -0700556{
Eric Anholt3de09aa2009-03-09 09:42:23 -0700557 char *src_vaddr, *dst_vaddr;
Keith Packard0839ccb2008-10-30 19:38:48 -0700558 unsigned long unwritten;
559
Eric Anholt3de09aa2009-03-09 09:42:23 -0700560 dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
561 src_vaddr = kmap_atomic(user_page, KM_USER1);
562 unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
563 src_vaddr + user_offset,
564 length);
565 kunmap_atomic(src_vaddr, KM_USER1);
566 io_mapping_unmap_atomic(dst_vaddr);
Keith Packard0839ccb2008-10-30 19:38:48 -0700567 if (unwritten)
568 return -EFAULT;
569 return 0;
Linus Torvalds9b7530cc2008-10-20 14:16:43 -0700570}
571
Eric Anholt40123c12009-03-09 13:42:30 -0700572static inline int
573fast_shmem_write(struct page **pages,
574 loff_t page_base, int page_offset,
575 char __user *data,
576 int length)
577{
578 char __iomem *vaddr;
Dave Airlied0088772009-03-28 20:29:48 -0400579 unsigned long unwritten;
Eric Anholt40123c12009-03-09 13:42:30 -0700580
581 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
582 if (vaddr == NULL)
583 return -ENOMEM;
Dave Airlied0088772009-03-28 20:29:48 -0400584 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
Eric Anholt40123c12009-03-09 13:42:30 -0700585 kunmap_atomic(vaddr, KM_USER0);
586
Dave Airlied0088772009-03-28 20:29:48 -0400587 if (unwritten)
588 return -EFAULT;
Eric Anholt40123c12009-03-09 13:42:30 -0700589 return 0;
590}
591
Eric Anholt3de09aa2009-03-09 09:42:23 -0700592/**
593 * This is the fast pwrite path, where we copy the data directly from the
594 * user into the GTT, uncached.
595 */
Eric Anholt673a3942008-07-30 12:06:12 -0700596static int
Eric Anholt3de09aa2009-03-09 09:42:23 -0700597i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
598 struct drm_i915_gem_pwrite *args,
599 struct drm_file *file_priv)
Eric Anholt673a3942008-07-30 12:06:12 -0700600{
601 struct drm_i915_gem_object *obj_priv = obj->driver_private;
Keith Packard0839ccb2008-10-30 19:38:48 -0700602 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholt673a3942008-07-30 12:06:12 -0700603 ssize_t remain;
Keith Packard0839ccb2008-10-30 19:38:48 -0700604 loff_t offset, page_base;
Eric Anholt673a3942008-07-30 12:06:12 -0700605 char __user *user_data;
Keith Packard0839ccb2008-10-30 19:38:48 -0700606 int page_offset, page_length;
607 int ret;
Eric Anholt673a3942008-07-30 12:06:12 -0700608
609 user_data = (char __user *) (uintptr_t) args->data_ptr;
610 remain = args->size;
611 if (!access_ok(VERIFY_READ, user_data, remain))
612 return -EFAULT;
613
614
615 mutex_lock(&dev->struct_mutex);
616 ret = i915_gem_object_pin(obj, 0);
617 if (ret) {
618 mutex_unlock(&dev->struct_mutex);
619 return ret;
620 }
Eric Anholt2ef7eea2008-11-10 10:53:25 -0800621 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
Eric Anholt673a3942008-07-30 12:06:12 -0700622 if (ret)
623 goto fail;
624
625 obj_priv = obj->driver_private;
626 offset = obj_priv->gtt_offset + args->offset;
Eric Anholt673a3942008-07-30 12:06:12 -0700627
628 while (remain > 0) {
629 /* Operation in this page
630 *
Keith Packard0839ccb2008-10-30 19:38:48 -0700631 * page_base = page offset within aperture
632 * page_offset = offset within page
633 * page_length = bytes to copy for this page
Eric Anholt673a3942008-07-30 12:06:12 -0700634 */
Keith Packard0839ccb2008-10-30 19:38:48 -0700635 page_base = (offset & ~(PAGE_SIZE-1));
636 page_offset = offset & (PAGE_SIZE-1);
637 page_length = remain;
638 if ((page_offset + remain) > PAGE_SIZE)
639 page_length = PAGE_SIZE - page_offset;
Eric Anholt673a3942008-07-30 12:06:12 -0700640
Keith Packard0839ccb2008-10-30 19:38:48 -0700641 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
642 page_offset, user_data, page_length);
Eric Anholt673a3942008-07-30 12:06:12 -0700643
Keith Packard0839ccb2008-10-30 19:38:48 -0700644 /* If we get a fault while copying data, then (presumably) our
Eric Anholt3de09aa2009-03-09 09:42:23 -0700645 * source page isn't available. Return the error and we'll
646 * retry in the slow path.
Keith Packard0839ccb2008-10-30 19:38:48 -0700647 */
Eric Anholt3de09aa2009-03-09 09:42:23 -0700648 if (ret)
649 goto fail;
Eric Anholt673a3942008-07-30 12:06:12 -0700650
Keith Packard0839ccb2008-10-30 19:38:48 -0700651 remain -= page_length;
652 user_data += page_length;
653 offset += page_length;
Eric Anholt673a3942008-07-30 12:06:12 -0700654 }
Eric Anholt673a3942008-07-30 12:06:12 -0700655
656fail:
657 i915_gem_object_unpin(obj);
658 mutex_unlock(&dev->struct_mutex);
659
660 return ret;
661}
662
Eric Anholt3de09aa2009-03-09 09:42:23 -0700663/**
664 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
665 * the memory and maps it using kmap_atomic for copying.
666 *
667 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
668 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
669 */
Eric Anholt3043c602008-10-02 12:24:47 -0700670static int
Eric Anholt3de09aa2009-03-09 09:42:23 -0700671i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
672 struct drm_i915_gem_pwrite *args,
673 struct drm_file *file_priv)
Eric Anholt673a3942008-07-30 12:06:12 -0700674{
Eric Anholt3de09aa2009-03-09 09:42:23 -0700675 struct drm_i915_gem_object *obj_priv = obj->driver_private;
676 drm_i915_private_t *dev_priv = dev->dev_private;
677 ssize_t remain;
678 loff_t gtt_page_base, offset;
679 loff_t first_data_page, last_data_page, num_pages;
680 loff_t pinned_pages, i;
681 struct page **user_pages;
682 struct mm_struct *mm = current->mm;
683 int gtt_page_offset, data_page_offset, data_page_index, page_length;
Eric Anholt673a3942008-07-30 12:06:12 -0700684 int ret;
Eric Anholt3de09aa2009-03-09 09:42:23 -0700685 uint64_t data_ptr = args->data_ptr;
686
687 remain = args->size;
688
689 /* Pin the user pages containing the data. We can't fault while
690 * holding the struct mutex, and all of the pwrite implementations
691 * want to hold it while dereferencing the user data.
692 */
693 first_data_page = data_ptr / PAGE_SIZE;
694 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
695 num_pages = last_data_page - first_data_page + 1;
696
Jesse Barnes8e7d2b22009-05-08 16:13:25 -0700697 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
Eric Anholt3de09aa2009-03-09 09:42:23 -0700698 if (user_pages == NULL)
699 return -ENOMEM;
700
701 down_read(&mm->mmap_sem);
702 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
703 num_pages, 0, 0, user_pages, NULL);
704 up_read(&mm->mmap_sem);
705 if (pinned_pages < num_pages) {
706 ret = -EFAULT;
707 goto out_unpin_pages;
708 }
709
710 mutex_lock(&dev->struct_mutex);
711 ret = i915_gem_object_pin(obj, 0);
712 if (ret)
713 goto out_unlock;
714
715 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
716 if (ret)
717 goto out_unpin_object;
718
719 obj_priv = obj->driver_private;
720 offset = obj_priv->gtt_offset + args->offset;
721
722 while (remain > 0) {
723 /* Operation in this page
724 *
725 * gtt_page_base = page offset within aperture
726 * gtt_page_offset = offset within page in aperture
727 * data_page_index = page number in get_user_pages return
728 * data_page_offset = offset with data_page_index page.
729 * page_length = bytes to copy for this page
730 */
731 gtt_page_base = offset & PAGE_MASK;
732 gtt_page_offset = offset & ~PAGE_MASK;
733 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
734 data_page_offset = data_ptr & ~PAGE_MASK;
735
736 page_length = remain;
737 if ((gtt_page_offset + page_length) > PAGE_SIZE)
738 page_length = PAGE_SIZE - gtt_page_offset;
739 if ((data_page_offset + page_length) > PAGE_SIZE)
740 page_length = PAGE_SIZE - data_page_offset;
741
742 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
743 gtt_page_base, gtt_page_offset,
744 user_pages[data_page_index],
745 data_page_offset,
746 page_length);
747
748 /* If we get a fault while copying data, then (presumably) our
749 * source page isn't available. Return the error and we'll
750 * retry in the slow path.
751 */
752 if (ret)
753 goto out_unpin_object;
754
755 remain -= page_length;
756 offset += page_length;
757 data_ptr += page_length;
758 }
759
760out_unpin_object:
761 i915_gem_object_unpin(obj);
762out_unlock:
763 mutex_unlock(&dev->struct_mutex);
764out_unpin_pages:
765 for (i = 0; i < pinned_pages; i++)
766 page_cache_release(user_pages[i]);
Jesse Barnes8e7d2b22009-05-08 16:13:25 -0700767 drm_free_large(user_pages);
Eric Anholt3de09aa2009-03-09 09:42:23 -0700768
769 return ret;
770}
771
Eric Anholt40123c12009-03-09 13:42:30 -0700772/**
773 * This is the fast shmem pwrite path, which attempts to directly
774 * copy_from_user into the kmapped pages backing the object.
775 */
Eric Anholt673a3942008-07-30 12:06:12 -0700776static int
Eric Anholt40123c12009-03-09 13:42:30 -0700777i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
778 struct drm_i915_gem_pwrite *args,
779 struct drm_file *file_priv)
Eric Anholt673a3942008-07-30 12:06:12 -0700780{
Eric Anholt40123c12009-03-09 13:42:30 -0700781 struct drm_i915_gem_object *obj_priv = obj->driver_private;
782 ssize_t remain;
783 loff_t offset, page_base;
784 char __user *user_data;
785 int page_offset, page_length;
Eric Anholt673a3942008-07-30 12:06:12 -0700786 int ret;
Eric Anholt40123c12009-03-09 13:42:30 -0700787
788 user_data = (char __user *) (uintptr_t) args->data_ptr;
789 remain = args->size;
Eric Anholt673a3942008-07-30 12:06:12 -0700790
791 mutex_lock(&dev->struct_mutex);
792
Eric Anholt40123c12009-03-09 13:42:30 -0700793 ret = i915_gem_object_get_pages(obj);
794 if (ret != 0)
795 goto fail_unlock;
796
Eric Anholte47c68e2008-11-14 13:35:19 -0800797 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
Eric Anholt40123c12009-03-09 13:42:30 -0700798 if (ret != 0)
799 goto fail_put_pages;
Eric Anholt673a3942008-07-30 12:06:12 -0700800
Eric Anholt40123c12009-03-09 13:42:30 -0700801 obj_priv = obj->driver_private;
Eric Anholt673a3942008-07-30 12:06:12 -0700802 offset = args->offset;
Eric Anholt40123c12009-03-09 13:42:30 -0700803 obj_priv->dirty = 1;
Eric Anholt673a3942008-07-30 12:06:12 -0700804
Eric Anholt40123c12009-03-09 13:42:30 -0700805 while (remain > 0) {
806 /* Operation in this page
807 *
808 * page_base = page offset within aperture
809 * page_offset = offset within page
810 * page_length = bytes to copy for this page
811 */
812 page_base = (offset & ~(PAGE_SIZE-1));
813 page_offset = offset & (PAGE_SIZE-1);
814 page_length = remain;
815 if ((page_offset + remain) > PAGE_SIZE)
816 page_length = PAGE_SIZE - page_offset;
817
818 ret = fast_shmem_write(obj_priv->pages,
819 page_base, page_offset,
820 user_data, page_length);
821 if (ret)
822 goto fail_put_pages;
823
824 remain -= page_length;
825 user_data += page_length;
826 offset += page_length;
Eric Anholt673a3942008-07-30 12:06:12 -0700827 }
828
Eric Anholt40123c12009-03-09 13:42:30 -0700829fail_put_pages:
830 i915_gem_object_put_pages(obj);
831fail_unlock:
Eric Anholt673a3942008-07-30 12:06:12 -0700832 mutex_unlock(&dev->struct_mutex);
833
Eric Anholt40123c12009-03-09 13:42:30 -0700834 return ret;
835}
836
837/**
838 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
839 * the memory and maps it using kmap_atomic for copying.
840 *
841 * This avoids taking mmap_sem for faulting on the user's address while the
842 * struct_mutex is held.
843 */
844static int
845i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
846 struct drm_i915_gem_pwrite *args,
847 struct drm_file *file_priv)
848{
849 struct drm_i915_gem_object *obj_priv = obj->driver_private;
850 struct mm_struct *mm = current->mm;
851 struct page **user_pages;
852 ssize_t remain;
853 loff_t offset, pinned_pages, i;
854 loff_t first_data_page, last_data_page, num_pages;
855 int shmem_page_index, shmem_page_offset;
856 int data_page_index, data_page_offset;
857 int page_length;
858 int ret;
859 uint64_t data_ptr = args->data_ptr;
Eric Anholt280b7132009-03-12 16:56:27 -0700860 int do_bit17_swizzling;
Eric Anholt40123c12009-03-09 13:42:30 -0700861
862 remain = args->size;
863
864 /* Pin the user pages containing the data. We can't fault while
865 * holding the struct mutex, and all of the pwrite implementations
866 * want to hold it while dereferencing the user data.
867 */
868 first_data_page = data_ptr / PAGE_SIZE;
869 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
870 num_pages = last_data_page - first_data_page + 1;
871
Jesse Barnes8e7d2b22009-05-08 16:13:25 -0700872 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
Eric Anholt40123c12009-03-09 13:42:30 -0700873 if (user_pages == NULL)
874 return -ENOMEM;
875
876 down_read(&mm->mmap_sem);
877 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
878 num_pages, 0, 0, user_pages, NULL);
879 up_read(&mm->mmap_sem);
880 if (pinned_pages < num_pages) {
881 ret = -EFAULT;
882 goto fail_put_user_pages;
883 }
884
Eric Anholt280b7132009-03-12 16:56:27 -0700885 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
886
Eric Anholt40123c12009-03-09 13:42:30 -0700887 mutex_lock(&dev->struct_mutex);
888
Chris Wilson07f73f62009-09-14 16:50:30 +0100889 ret = i915_gem_object_get_pages_or_evict(obj);
890 if (ret)
Eric Anholt40123c12009-03-09 13:42:30 -0700891 goto fail_unlock;
892
893 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
894 if (ret != 0)
895 goto fail_put_pages;
896
897 obj_priv = obj->driver_private;
898 offset = args->offset;
899 obj_priv->dirty = 1;
900
901 while (remain > 0) {
902 /* Operation in this page
903 *
904 * shmem_page_index = page number within shmem file
905 * shmem_page_offset = offset within page in shmem file
906 * data_page_index = page number in get_user_pages return
907 * data_page_offset = offset with data_page_index page.
908 * page_length = bytes to copy for this page
909 */
910 shmem_page_index = offset / PAGE_SIZE;
911 shmem_page_offset = offset & ~PAGE_MASK;
912 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
913 data_page_offset = data_ptr & ~PAGE_MASK;
914
915 page_length = remain;
916 if ((shmem_page_offset + page_length) > PAGE_SIZE)
917 page_length = PAGE_SIZE - shmem_page_offset;
918 if ((data_page_offset + page_length) > PAGE_SIZE)
919 page_length = PAGE_SIZE - data_page_offset;
920
Eric Anholt280b7132009-03-12 16:56:27 -0700921 if (do_bit17_swizzling) {
922 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
923 shmem_page_offset,
924 user_pages[data_page_index],
925 data_page_offset,
926 page_length,
927 0);
928 } else {
929 ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
930 shmem_page_offset,
931 user_pages[data_page_index],
932 data_page_offset,
933 page_length);
934 }
Eric Anholt40123c12009-03-09 13:42:30 -0700935 if (ret)
936 goto fail_put_pages;
937
938 remain -= page_length;
939 data_ptr += page_length;
940 offset += page_length;
941 }
942
943fail_put_pages:
944 i915_gem_object_put_pages(obj);
945fail_unlock:
946 mutex_unlock(&dev->struct_mutex);
947fail_put_user_pages:
948 for (i = 0; i < pinned_pages; i++)
949 page_cache_release(user_pages[i]);
Jesse Barnes8e7d2b22009-05-08 16:13:25 -0700950 drm_free_large(user_pages);
Eric Anholt40123c12009-03-09 13:42:30 -0700951
952 return ret;
Eric Anholt673a3942008-07-30 12:06:12 -0700953}
954
955/**
956 * Writes data to the object referenced by handle.
957 *
958 * On error, the contents of the buffer that were to be modified are undefined.
959 */
960int
961i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
962 struct drm_file *file_priv)
963{
964 struct drm_i915_gem_pwrite *args = data;
965 struct drm_gem_object *obj;
966 struct drm_i915_gem_object *obj_priv;
967 int ret = 0;
968
969 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
970 if (obj == NULL)
971 return -EBADF;
972 obj_priv = obj->driver_private;
973
974 /* Bounds check destination.
975 *
976 * XXX: This could use review for overflow issues...
977 */
978 if (args->offset > obj->size || args->size > obj->size ||
979 args->offset + args->size > obj->size) {
980 drm_gem_object_unreference(obj);
981 return -EINVAL;
982 }
983
984 /* We can only do the GTT pwrite on untiled buffers, as otherwise
985 * it would end up going through the fenced access, and we'll get
986 * different detiling behavior between reading and writing.
987 * pread/pwrite currently are reading and writing from the CPU
988 * perspective, requiring manual detiling by the client.
989 */
Dave Airlie71acb5e2008-12-30 20:31:46 +1000990 if (obj_priv->phys_obj)
991 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
992 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
Eric Anholt3de09aa2009-03-09 09:42:23 -0700993 dev->gtt_total != 0) {
994 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
995 if (ret == -EFAULT) {
996 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
997 file_priv);
998 }
Eric Anholt280b7132009-03-12 16:56:27 -0700999 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
1000 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
Eric Anholt40123c12009-03-09 13:42:30 -07001001 } else {
1002 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
1003 if (ret == -EFAULT) {
1004 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
1005 file_priv);
1006 }
1007 }
Eric Anholt673a3942008-07-30 12:06:12 -07001008
1009#if WATCH_PWRITE
1010 if (ret)
1011 DRM_INFO("pwrite failed %d\n", ret);
1012#endif
1013
1014 drm_gem_object_unreference(obj);
1015
1016 return ret;
1017}
1018
1019/**
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001020 * Called when user space prepares to use an object with the CPU, either
1021 * through the mmap ioctl's mapping or a GTT mapping.
Eric Anholt673a3942008-07-30 12:06:12 -07001022 */
1023int
1024i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1025 struct drm_file *file_priv)
1026{
Eric Anholta09ba7f2009-08-29 12:49:51 -07001027 struct drm_i915_private *dev_priv = dev->dev_private;
Eric Anholt673a3942008-07-30 12:06:12 -07001028 struct drm_i915_gem_set_domain *args = data;
1029 struct drm_gem_object *obj;
Jesse Barnes652c3932009-08-17 13:31:43 -07001030 struct drm_i915_gem_object *obj_priv;
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001031 uint32_t read_domains = args->read_domains;
1032 uint32_t write_domain = args->write_domain;
Eric Anholt673a3942008-07-30 12:06:12 -07001033 int ret;
1034
1035 if (!(dev->driver->driver_features & DRIVER_GEM))
1036 return -ENODEV;
1037
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001038 /* Only handle setting domains to types used by the CPU. */
Chris Wilson21d509e2009-06-06 09:46:02 +01001039 if (write_domain & I915_GEM_GPU_DOMAINS)
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001040 return -EINVAL;
1041
Chris Wilson21d509e2009-06-06 09:46:02 +01001042 if (read_domains & I915_GEM_GPU_DOMAINS)
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001043 return -EINVAL;
1044
1045 /* Having something in the write domain implies it's in the read
1046 * domain, and only that read domain. Enforce that in the request.
1047 */
1048 if (write_domain != 0 && read_domains != write_domain)
1049 return -EINVAL;
1050
Eric Anholt673a3942008-07-30 12:06:12 -07001051 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1052 if (obj == NULL)
1053 return -EBADF;
Jesse Barnes652c3932009-08-17 13:31:43 -07001054 obj_priv = obj->driver_private;
Eric Anholt673a3942008-07-30 12:06:12 -07001055
1056 mutex_lock(&dev->struct_mutex);
Jesse Barnes652c3932009-08-17 13:31:43 -07001057
1058 intel_mark_busy(dev, obj);
1059
Eric Anholt673a3942008-07-30 12:06:12 -07001060#if WATCH_BUF
Krzysztof Halasacfd43c02009-06-20 00:31:28 +02001061 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001062 obj, obj->size, read_domains, write_domain);
Eric Anholt673a3942008-07-30 12:06:12 -07001063#endif
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001064 if (read_domains & I915_GEM_DOMAIN_GTT) {
1065 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
Eric Anholt02354392008-11-26 13:58:13 -08001066
Eric Anholta09ba7f2009-08-29 12:49:51 -07001067 /* Update the LRU on the fence for the CPU access that's
1068 * about to occur.
1069 */
1070 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1071 list_move_tail(&obj_priv->fence_list,
1072 &dev_priv->mm.fence_list);
1073 }
1074
Eric Anholt02354392008-11-26 13:58:13 -08001075 /* Silently promote "you're not bound, there was nothing to do"
1076 * to success, since the client was just asking us to
1077 * make sure everything was done.
1078 */
1079 if (ret == -EINVAL)
1080 ret = 0;
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001081 } else {
Eric Anholte47c68e2008-11-14 13:35:19 -08001082 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001083 }
1084
Eric Anholt673a3942008-07-30 12:06:12 -07001085 drm_gem_object_unreference(obj);
1086 mutex_unlock(&dev->struct_mutex);
1087 return ret;
1088}
1089
1090/**
1091 * Called when user space has done writes to this buffer
1092 */
1093int
1094i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1095 struct drm_file *file_priv)
1096{
1097 struct drm_i915_gem_sw_finish *args = data;
1098 struct drm_gem_object *obj;
1099 struct drm_i915_gem_object *obj_priv;
1100 int ret = 0;
1101
1102 if (!(dev->driver->driver_features & DRIVER_GEM))
1103 return -ENODEV;
1104
1105 mutex_lock(&dev->struct_mutex);
1106 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1107 if (obj == NULL) {
1108 mutex_unlock(&dev->struct_mutex);
1109 return -EBADF;
1110 }
1111
1112#if WATCH_BUF
Krzysztof Halasacfd43c02009-06-20 00:31:28 +02001113 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
Eric Anholt673a3942008-07-30 12:06:12 -07001114 __func__, args->handle, obj, obj->size);
1115#endif
1116 obj_priv = obj->driver_private;
1117
1118 /* Pinned buffers may be scanout, so flush the cache */
Eric Anholte47c68e2008-11-14 13:35:19 -08001119 if (obj_priv->pin_count)
1120 i915_gem_object_flush_cpu_write_domain(obj);
1121
Eric Anholt673a3942008-07-30 12:06:12 -07001122 drm_gem_object_unreference(obj);
1123 mutex_unlock(&dev->struct_mutex);
1124 return ret;
1125}
1126
1127/**
1128 * Maps the contents of an object, returning the address it is mapped
1129 * into.
1130 *
1131 * While the mapping holds a reference on the contents of the object, it doesn't
1132 * imply a ref on the object itself.
1133 */
1134int
1135i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1136 struct drm_file *file_priv)
1137{
1138 struct drm_i915_gem_mmap *args = data;
1139 struct drm_gem_object *obj;
1140 loff_t offset;
1141 unsigned long addr;
1142
1143 if (!(dev->driver->driver_features & DRIVER_GEM))
1144 return -ENODEV;
1145
1146 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1147 if (obj == NULL)
1148 return -EBADF;
1149
1150 offset = args->offset;
1151
1152 down_write(&current->mm->mmap_sem);
1153 addr = do_mmap(obj->filp, 0, args->size,
1154 PROT_READ | PROT_WRITE, MAP_SHARED,
1155 args->offset);
1156 up_write(&current->mm->mmap_sem);
1157 mutex_lock(&dev->struct_mutex);
1158 drm_gem_object_unreference(obj);
1159 mutex_unlock(&dev->struct_mutex);
1160 if (IS_ERR((void *)addr))
1161 return addr;
1162
1163 args->addr_ptr = (uint64_t) addr;
1164
1165 return 0;
1166}
1167
Jesse Barnesde151cf2008-11-12 10:03:55 -08001168/**
1169 * i915_gem_fault - fault a page into the GTT
1170 * vma: VMA in question
1171 * vmf: fault info
1172 *
1173 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1174 * from userspace. The fault handler takes care of binding the object to
1175 * the GTT (if needed), allocating and programming a fence register (again,
1176 * only if needed based on whether the old reg is still valid or the object
1177 * is tiled) and inserting a new PTE into the faulting process.
1178 *
1179 * Note that the faulting process may involve evicting existing objects
1180 * from the GTT and/or fence registers to make room. So performance may
1181 * suffer if the GTT working set is large or there are few fence registers
1182 * left.
1183 */
1184int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1185{
1186 struct drm_gem_object *obj = vma->vm_private_data;
1187 struct drm_device *dev = obj->dev;
1188 struct drm_i915_private *dev_priv = dev->dev_private;
1189 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1190 pgoff_t page_offset;
1191 unsigned long pfn;
1192 int ret = 0;
Jesse Barnes0f973f22009-01-26 17:10:45 -08001193 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001194
1195 /* We don't use vmf->pgoff since that has the fake offset */
1196 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1197 PAGE_SHIFT;
1198
1199 /* Now bind it into the GTT if needed */
1200 mutex_lock(&dev->struct_mutex);
1201 if (!obj_priv->gtt_space) {
Chris Wilsone67b8ce2009-09-14 16:50:26 +01001202 ret = i915_gem_object_bind_to_gtt(obj, 0);
Chris Wilsonc7150892009-09-23 00:43:56 +01001203 if (ret)
1204 goto unlock;
Kristian Høgsberg07f4f3e2009-05-27 14:37:28 -04001205
Jesse Barnes14b60392009-05-20 16:47:08 -04001206 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001207
1208 ret = i915_gem_object_set_to_gtt_domain(obj, write);
Chris Wilsonc7150892009-09-23 00:43:56 +01001209 if (ret)
1210 goto unlock;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001211 }
1212
1213 /* Need a new fence register? */
Eric Anholta09ba7f2009-08-29 12:49:51 -07001214 if (obj_priv->tiling_mode != I915_TILING_NONE) {
Chris Wilson8c4b8c32009-06-17 22:08:52 +01001215 ret = i915_gem_object_get_fence_reg(obj);
Chris Wilsonc7150892009-09-23 00:43:56 +01001216 if (ret)
1217 goto unlock;
Eric Anholtd9ddcb92009-01-27 10:33:49 -08001218 }
Jesse Barnesde151cf2008-11-12 10:03:55 -08001219
1220 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1221 page_offset;
1222
1223 /* Finally, remap it using the new GTT offset */
1224 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
Chris Wilsonc7150892009-09-23 00:43:56 +01001225unlock:
Jesse Barnesde151cf2008-11-12 10:03:55 -08001226 mutex_unlock(&dev->struct_mutex);
1227
1228 switch (ret) {
Chris Wilsonc7150892009-09-23 00:43:56 +01001229 case 0:
1230 case -ERESTARTSYS:
1231 return VM_FAULT_NOPAGE;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001232 case -ENOMEM:
1233 case -EAGAIN:
1234 return VM_FAULT_OOM;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001235 default:
Chris Wilsonc7150892009-09-23 00:43:56 +01001236 return VM_FAULT_SIGBUS;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001237 }
1238}
1239
1240/**
1241 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1242 * @obj: obj in question
1243 *
1244 * GEM memory mapping works by handing back to userspace a fake mmap offset
1245 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1246 * up the object based on the offset and sets up the various memory mapping
1247 * structures.
1248 *
1249 * This routine allocates and attaches a fake offset for @obj.
1250 */
1251static int
1252i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1253{
1254 struct drm_device *dev = obj->dev;
1255 struct drm_gem_mm *mm = dev->mm_private;
1256 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1257 struct drm_map_list *list;
Benjamin Herrenschmidtf77d3902009-02-02 16:55:46 +11001258 struct drm_local_map *map;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001259 int ret = 0;
1260
1261 /* Set the object up for mmap'ing */
1262 list = &obj->map_list;
Eric Anholt9a298b22009-03-24 12:23:04 -07001263 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001264 if (!list->map)
1265 return -ENOMEM;
1266
1267 map = list->map;
1268 map->type = _DRM_GEM;
1269 map->size = obj->size;
1270 map->handle = obj;
1271
1272 /* Get a DRM GEM mmap offset allocated... */
1273 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1274 obj->size / PAGE_SIZE, 0, 0);
1275 if (!list->file_offset_node) {
1276 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1277 ret = -ENOMEM;
1278 goto out_free_list;
1279 }
1280
1281 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1282 obj->size / PAGE_SIZE, 0);
1283 if (!list->file_offset_node) {
1284 ret = -ENOMEM;
1285 goto out_free_list;
1286 }
1287
1288 list->hash.key = list->file_offset_node->start;
1289 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1290 DRM_ERROR("failed to add to map hash\n");
1291 goto out_free_mm;
1292 }
1293
1294 /* By now we should be all set, any drm_mmap request on the offset
1295 * below will get to our mmap & fault handler */
1296 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1297
1298 return 0;
1299
1300out_free_mm:
1301 drm_mm_put_block(list->file_offset_node);
1302out_free_list:
Eric Anholt9a298b22009-03-24 12:23:04 -07001303 kfree(list->map);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001304
1305 return ret;
1306}
1307
Chris Wilson901782b2009-07-10 08:18:50 +01001308/**
1309 * i915_gem_release_mmap - remove physical page mappings
1310 * @obj: obj in question
1311 *
André Goddard Rosaaf901ca2009-11-14 13:09:05 -02001312 * Preserve the reservation of the mmapping with the DRM core code, but
Chris Wilson901782b2009-07-10 08:18:50 +01001313 * relinquish ownership of the pages back to the system.
1314 *
1315 * It is vital that we remove the page mapping if we have mapped a tiled
1316 * object through the GTT and then lose the fence register due to
1317 * resource pressure. Similarly if the object has been moved out of the
1318 * aperture, than pages mapped into userspace must be revoked. Removing the
1319 * mapping will then trigger a page fault on the next user access, allowing
1320 * fixup by i915_gem_fault().
1321 */
Eric Anholtd05ca302009-07-10 13:02:26 -07001322void
Chris Wilson901782b2009-07-10 08:18:50 +01001323i915_gem_release_mmap(struct drm_gem_object *obj)
1324{
1325 struct drm_device *dev = obj->dev;
1326 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1327
1328 if (dev->dev_mapping)
1329 unmap_mapping_range(dev->dev_mapping,
1330 obj_priv->mmap_offset, obj->size, 1);
1331}
1332
Jesse Barnesab00b3e2009-02-11 14:01:46 -08001333static void
1334i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1335{
1336 struct drm_device *dev = obj->dev;
1337 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1338 struct drm_gem_mm *mm = dev->mm_private;
1339 struct drm_map_list *list;
1340
1341 list = &obj->map_list;
1342 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1343
1344 if (list->file_offset_node) {
1345 drm_mm_put_block(list->file_offset_node);
1346 list->file_offset_node = NULL;
1347 }
1348
1349 if (list->map) {
Eric Anholt9a298b22009-03-24 12:23:04 -07001350 kfree(list->map);
Jesse Barnesab00b3e2009-02-11 14:01:46 -08001351 list->map = NULL;
1352 }
1353
1354 obj_priv->mmap_offset = 0;
1355}
1356
Jesse Barnesde151cf2008-11-12 10:03:55 -08001357/**
1358 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1359 * @obj: object to check
1360 *
1361 * Return the required GTT alignment for an object, taking into account
1362 * potential fence register mapping if needed.
1363 */
1364static uint32_t
1365i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1366{
1367 struct drm_device *dev = obj->dev;
1368 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1369 int start, i;
1370
1371 /*
1372 * Minimum alignment is 4k (GTT page size), but might be greater
1373 * if a fence register is needed for the object.
1374 */
1375 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1376 return 4096;
1377
1378 /*
1379 * Previous chips need to be aligned to the size of the smallest
1380 * fence register that can contain the object.
1381 */
1382 if (IS_I9XX(dev))
1383 start = 1024*1024;
1384 else
1385 start = 512*1024;
1386
1387 for (i = start; i < obj->size; i <<= 1)
1388 ;
1389
1390 return i;
1391}
1392
1393/**
1394 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1395 * @dev: DRM device
1396 * @data: GTT mapping ioctl data
1397 * @file_priv: GEM object info
1398 *
1399 * Simply returns the fake offset to userspace so it can mmap it.
1400 * The mmap call will end up in drm_gem_mmap(), which will set things
1401 * up so we can get faults in the handler above.
1402 *
1403 * The fault handler will take care of binding the object into the GTT
1404 * (since it may have been evicted to make room for something), allocating
1405 * a fence register, and mapping the appropriate aperture address into
1406 * userspace.
1407 */
1408int
1409i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1410 struct drm_file *file_priv)
1411{
1412 struct drm_i915_gem_mmap_gtt *args = data;
1413 struct drm_i915_private *dev_priv = dev->dev_private;
1414 struct drm_gem_object *obj;
1415 struct drm_i915_gem_object *obj_priv;
1416 int ret;
1417
1418 if (!(dev->driver->driver_features & DRIVER_GEM))
1419 return -ENODEV;
1420
1421 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1422 if (obj == NULL)
1423 return -EBADF;
1424
1425 mutex_lock(&dev->struct_mutex);
1426
1427 obj_priv = obj->driver_private;
1428
Chris Wilsonab182822009-09-22 18:46:17 +01001429 if (obj_priv->madv != I915_MADV_WILLNEED) {
1430 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1431 drm_gem_object_unreference(obj);
1432 mutex_unlock(&dev->struct_mutex);
1433 return -EINVAL;
1434 }
1435
1436
Jesse Barnesde151cf2008-11-12 10:03:55 -08001437 if (!obj_priv->mmap_offset) {
1438 ret = i915_gem_create_mmap_offset(obj);
Chris Wilson13af1062009-02-11 14:26:31 +00001439 if (ret) {
1440 drm_gem_object_unreference(obj);
1441 mutex_unlock(&dev->struct_mutex);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001442 return ret;
Chris Wilson13af1062009-02-11 14:26:31 +00001443 }
Jesse Barnesde151cf2008-11-12 10:03:55 -08001444 }
1445
1446 args->offset = obj_priv->mmap_offset;
1447
Jesse Barnesde151cf2008-11-12 10:03:55 -08001448 /*
1449 * Pull it into the GTT so that we have a page list (makes the
1450 * initial fault faster and any subsequent flushing possible).
1451 */
1452 if (!obj_priv->agp_mem) {
Chris Wilsone67b8ce2009-09-14 16:50:26 +01001453 ret = i915_gem_object_bind_to_gtt(obj, 0);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001454 if (ret) {
1455 drm_gem_object_unreference(obj);
1456 mutex_unlock(&dev->struct_mutex);
1457 return ret;
1458 }
Jesse Barnes14b60392009-05-20 16:47:08 -04001459 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001460 }
1461
1462 drm_gem_object_unreference(obj);
1463 mutex_unlock(&dev->struct_mutex);
1464
1465 return 0;
1466}
1467
Ben Gamari6911a9b2009-04-02 11:24:54 -07001468void
Eric Anholt856fa192009-03-19 14:10:50 -07001469i915_gem_object_put_pages(struct drm_gem_object *obj)
Eric Anholt673a3942008-07-30 12:06:12 -07001470{
1471 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1472 int page_count = obj->size / PAGE_SIZE;
1473 int i;
1474
Eric Anholt856fa192009-03-19 14:10:50 -07001475 BUG_ON(obj_priv->pages_refcount == 0);
Chris Wilsonbb6baf72009-09-22 14:24:13 +01001476 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
Eric Anholt856fa192009-03-19 14:10:50 -07001477
1478 if (--obj_priv->pages_refcount != 0)
Eric Anholt673a3942008-07-30 12:06:12 -07001479 return;
1480
Eric Anholt280b7132009-03-12 16:56:27 -07001481 if (obj_priv->tiling_mode != I915_TILING_NONE)
1482 i915_gem_object_save_bit_17_swizzle(obj);
1483
Chris Wilson3ef94da2009-09-14 16:50:29 +01001484 if (obj_priv->madv == I915_MADV_DONTNEED)
Chris Wilson13a05fd2009-09-20 23:03:19 +01001485 obj_priv->dirty = 0;
Chris Wilson3ef94da2009-09-14 16:50:29 +01001486
1487 for (i = 0; i < page_count; i++) {
1488 if (obj_priv->pages[i] == NULL)
1489 break;
1490
1491 if (obj_priv->dirty)
1492 set_page_dirty(obj_priv->pages[i]);
1493
1494 if (obj_priv->madv == I915_MADV_WILLNEED)
Eric Anholt856fa192009-03-19 14:10:50 -07001495 mark_page_accessed(obj_priv->pages[i]);
Chris Wilson3ef94da2009-09-14 16:50:29 +01001496
1497 page_cache_release(obj_priv->pages[i]);
1498 }
Eric Anholt673a3942008-07-30 12:06:12 -07001499 obj_priv->dirty = 0;
1500
Jesse Barnes8e7d2b22009-05-08 16:13:25 -07001501 drm_free_large(obj_priv->pages);
Eric Anholt856fa192009-03-19 14:10:50 -07001502 obj_priv->pages = NULL;
Eric Anholt673a3942008-07-30 12:06:12 -07001503}
1504
1505static void
Eric Anholtce44b0e2008-11-06 16:00:31 -08001506i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
Eric Anholt673a3942008-07-30 12:06:12 -07001507{
1508 struct drm_device *dev = obj->dev;
1509 drm_i915_private_t *dev_priv = dev->dev_private;
1510 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1511
1512 /* Add a reference if we're newly entering the active list. */
1513 if (!obj_priv->active) {
1514 drm_gem_object_reference(obj);
1515 obj_priv->active = 1;
1516 }
1517 /* Move from whatever list we were on to the tail of execution. */
Carl Worth5e118f42009-03-20 11:54:25 -07001518 spin_lock(&dev_priv->mm.active_list_lock);
Eric Anholt673a3942008-07-30 12:06:12 -07001519 list_move_tail(&obj_priv->list,
1520 &dev_priv->mm.active_list);
Carl Worth5e118f42009-03-20 11:54:25 -07001521 spin_unlock(&dev_priv->mm.active_list_lock);
Eric Anholtce44b0e2008-11-06 16:00:31 -08001522 obj_priv->last_rendering_seqno = seqno;
Eric Anholt673a3942008-07-30 12:06:12 -07001523}
1524
Eric Anholtce44b0e2008-11-06 16:00:31 -08001525static void
1526i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1527{
1528 struct drm_device *dev = obj->dev;
1529 drm_i915_private_t *dev_priv = dev->dev_private;
1530 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1531
1532 BUG_ON(!obj_priv->active);
1533 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1534 obj_priv->last_rendering_seqno = 0;
1535}
Eric Anholt673a3942008-07-30 12:06:12 -07001536
Chris Wilson963b4832009-09-20 23:03:54 +01001537/* Immediately discard the backing storage */
1538static void
1539i915_gem_object_truncate(struct drm_gem_object *obj)
1540{
Chris Wilsonbb6baf72009-09-22 14:24:13 +01001541 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1542 struct inode *inode;
Chris Wilson963b4832009-09-20 23:03:54 +01001543
Chris Wilsonbb6baf72009-09-22 14:24:13 +01001544 inode = obj->filp->f_path.dentry->d_inode;
1545 if (inode->i_op->truncate)
1546 inode->i_op->truncate (inode);
1547
1548 obj_priv->madv = __I915_MADV_PURGED;
Chris Wilson963b4832009-09-20 23:03:54 +01001549}
1550
1551static inline int
1552i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1553{
1554 return obj_priv->madv == I915_MADV_DONTNEED;
1555}
1556
Eric Anholt673a3942008-07-30 12:06:12 -07001557static void
1558i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1559{
1560 struct drm_device *dev = obj->dev;
1561 drm_i915_private_t *dev_priv = dev->dev_private;
1562 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1563
1564 i915_verify_inactive(dev, __FILE__, __LINE__);
1565 if (obj_priv->pin_count != 0)
1566 list_del_init(&obj_priv->list);
1567 else
1568 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1569
Eric Anholtce44b0e2008-11-06 16:00:31 -08001570 obj_priv->last_rendering_seqno = 0;
Eric Anholt673a3942008-07-30 12:06:12 -07001571 if (obj_priv->active) {
1572 obj_priv->active = 0;
1573 drm_gem_object_unreference(obj);
1574 }
1575 i915_verify_inactive(dev, __FILE__, __LINE__);
1576}
1577
1578/**
1579 * Creates a new sequence number, emitting a write of it to the status page
1580 * plus an interrupt, which will trigger i915_user_interrupt_handler.
1581 *
1582 * Must be called with struct_lock held.
1583 *
1584 * Returned sequence numbers are nonzero on success.
1585 */
1586static uint32_t
Eric Anholtb9624422009-06-03 07:27:35 +00001587i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1588 uint32_t flush_domains)
Eric Anholt673a3942008-07-30 12:06:12 -07001589{
1590 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholtb9624422009-06-03 07:27:35 +00001591 struct drm_i915_file_private *i915_file_priv = NULL;
Eric Anholt673a3942008-07-30 12:06:12 -07001592 struct drm_i915_gem_request *request;
1593 uint32_t seqno;
1594 int was_empty;
1595 RING_LOCALS;
1596
Eric Anholtb9624422009-06-03 07:27:35 +00001597 if (file_priv != NULL)
1598 i915_file_priv = file_priv->driver_priv;
1599
Eric Anholt9a298b22009-03-24 12:23:04 -07001600 request = kzalloc(sizeof(*request), GFP_KERNEL);
Eric Anholt673a3942008-07-30 12:06:12 -07001601 if (request == NULL)
1602 return 0;
1603
1604 /* Grab the seqno we're going to make this request be, and bump the
1605 * next (skipping 0 so it can be the reserved no-seqno value).
1606 */
1607 seqno = dev_priv->mm.next_gem_seqno;
1608 dev_priv->mm.next_gem_seqno++;
1609 if (dev_priv->mm.next_gem_seqno == 0)
1610 dev_priv->mm.next_gem_seqno++;
1611
1612 BEGIN_LP_RING(4);
1613 OUT_RING(MI_STORE_DWORD_INDEX);
1614 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1615 OUT_RING(seqno);
1616
1617 OUT_RING(MI_USER_INTERRUPT);
1618 ADVANCE_LP_RING();
1619
1620 DRM_DEBUG("%d\n", seqno);
1621
1622 request->seqno = seqno;
1623 request->emitted_jiffies = jiffies;
Eric Anholt673a3942008-07-30 12:06:12 -07001624 was_empty = list_empty(&dev_priv->mm.request_list);
1625 list_add_tail(&request->list, &dev_priv->mm.request_list);
Eric Anholtb9624422009-06-03 07:27:35 +00001626 if (i915_file_priv) {
1627 list_add_tail(&request->client_list,
1628 &i915_file_priv->mm.request_list);
1629 } else {
1630 INIT_LIST_HEAD(&request->client_list);
1631 }
Eric Anholt673a3942008-07-30 12:06:12 -07001632
Eric Anholtce44b0e2008-11-06 16:00:31 -08001633 /* Associate any objects on the flushing list matching the write
1634 * domain we're flushing with our flush.
1635 */
1636 if (flush_domains != 0) {
1637 struct drm_i915_gem_object *obj_priv, *next;
1638
1639 list_for_each_entry_safe(obj_priv, next,
1640 &dev_priv->mm.flushing_list, list) {
1641 struct drm_gem_object *obj = obj_priv->obj;
1642
1643 if ((obj->write_domain & flush_domains) ==
1644 obj->write_domain) {
Chris Wilson1c5d22f2009-08-25 11:15:50 +01001645 uint32_t old_write_domain = obj->write_domain;
1646
Eric Anholtce44b0e2008-11-06 16:00:31 -08001647 obj->write_domain = 0;
1648 i915_gem_object_move_to_active(obj, seqno);
Chris Wilson1c5d22f2009-08-25 11:15:50 +01001649
1650 trace_i915_gem_object_change_domain(obj,
1651 obj->read_domains,
1652 old_write_domain);
Eric Anholtce44b0e2008-11-06 16:00:31 -08001653 }
1654 }
1655
1656 }
1657
Ben Gamarif65d9422009-09-14 17:48:44 -04001658 if (!dev_priv->mm.suspended) {
1659 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1660 if (was_empty)
1661 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1662 }
Eric Anholt673a3942008-07-30 12:06:12 -07001663 return seqno;
1664}
1665
1666/**
1667 * Command execution barrier
1668 *
1669 * Ensures that all commands in the ring are finished
1670 * before signalling the CPU
1671 */
Eric Anholt3043c602008-10-02 12:24:47 -07001672static uint32_t
Eric Anholt673a3942008-07-30 12:06:12 -07001673i915_retire_commands(struct drm_device *dev)
1674{
1675 drm_i915_private_t *dev_priv = dev->dev_private;
1676 uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1677 uint32_t flush_domains = 0;
1678 RING_LOCALS;
1679
1680 /* The sampler always gets flushed on i965 (sigh) */
1681 if (IS_I965G(dev))
1682 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1683 BEGIN_LP_RING(2);
1684 OUT_RING(cmd);
1685 OUT_RING(0); /* noop */
1686 ADVANCE_LP_RING();
1687 return flush_domains;
1688}
1689
1690/**
1691 * Moves buffers associated only with the given active seqno from the active
1692 * to inactive list, potentially freeing them.
1693 */
1694static void
1695i915_gem_retire_request(struct drm_device *dev,
1696 struct drm_i915_gem_request *request)
1697{
1698 drm_i915_private_t *dev_priv = dev->dev_private;
1699
Chris Wilson1c5d22f2009-08-25 11:15:50 +01001700 trace_i915_gem_request_retire(dev, request->seqno);
1701
Eric Anholt673a3942008-07-30 12:06:12 -07001702 /* Move any buffers on the active list that are no longer referenced
1703 * by the ringbuffer to the flushing/inactive lists as appropriate.
1704 */
Carl Worth5e118f42009-03-20 11:54:25 -07001705 spin_lock(&dev_priv->mm.active_list_lock);
Eric Anholt673a3942008-07-30 12:06:12 -07001706 while (!list_empty(&dev_priv->mm.active_list)) {
1707 struct drm_gem_object *obj;
1708 struct drm_i915_gem_object *obj_priv;
1709
1710 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1711 struct drm_i915_gem_object,
1712 list);
1713 obj = obj_priv->obj;
1714
1715 /* If the seqno being retired doesn't match the oldest in the
1716 * list, then the oldest in the list must still be newer than
1717 * this seqno.
1718 */
1719 if (obj_priv->last_rendering_seqno != request->seqno)
Carl Worth5e118f42009-03-20 11:54:25 -07001720 goto out;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001721
Eric Anholt673a3942008-07-30 12:06:12 -07001722#if WATCH_LRU
1723 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1724 __func__, request->seqno, obj);
1725#endif
1726
Eric Anholtce44b0e2008-11-06 16:00:31 -08001727 if (obj->write_domain != 0)
1728 i915_gem_object_move_to_flushing(obj);
Shaohua Li68c84342009-04-08 10:58:23 +08001729 else {
1730 /* Take a reference on the object so it won't be
1731 * freed while the spinlock is held. The list
1732 * protection for this spinlock is safe when breaking
1733 * the lock like this since the next thing we do
1734 * is just get the head of the list again.
1735 */
1736 drm_gem_object_reference(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001737 i915_gem_object_move_to_inactive(obj);
Shaohua Li68c84342009-04-08 10:58:23 +08001738 spin_unlock(&dev_priv->mm.active_list_lock);
1739 drm_gem_object_unreference(obj);
1740 spin_lock(&dev_priv->mm.active_list_lock);
1741 }
Eric Anholt673a3942008-07-30 12:06:12 -07001742 }
Carl Worth5e118f42009-03-20 11:54:25 -07001743out:
1744 spin_unlock(&dev_priv->mm.active_list_lock);
Eric Anholt673a3942008-07-30 12:06:12 -07001745}
1746
1747/**
1748 * Returns true if seq1 is later than seq2.
1749 */
Ben Gamari22be1722009-09-14 17:48:43 -04001750bool
Eric Anholt673a3942008-07-30 12:06:12 -07001751i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1752{
1753 return (int32_t)(seq1 - seq2) >= 0;
1754}
1755
1756uint32_t
1757i915_get_gem_seqno(struct drm_device *dev)
1758{
1759 drm_i915_private_t *dev_priv = dev->dev_private;
1760
1761 return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1762}
1763
1764/**
1765 * This function clears the request list as sequence numbers are passed.
1766 */
1767void
1768i915_gem_retire_requests(struct drm_device *dev)
1769{
1770 drm_i915_private_t *dev_priv = dev->dev_private;
1771 uint32_t seqno;
1772
Chris Wilson9d34e5d2009-09-24 05:26:06 +01001773 if (!dev_priv->hw_status_page || list_empty(&dev_priv->mm.request_list))
Karsten Wiese6c0594a2009-02-23 15:07:57 +01001774 return;
1775
Eric Anholt673a3942008-07-30 12:06:12 -07001776 seqno = i915_get_gem_seqno(dev);
1777
1778 while (!list_empty(&dev_priv->mm.request_list)) {
1779 struct drm_i915_gem_request *request;
1780 uint32_t retiring_seqno;
1781
1782 request = list_first_entry(&dev_priv->mm.request_list,
1783 struct drm_i915_gem_request,
1784 list);
1785 retiring_seqno = request->seqno;
1786
1787 if (i915_seqno_passed(seqno, retiring_seqno) ||
Ben Gamariba1234d2009-09-14 17:48:47 -04001788 atomic_read(&dev_priv->mm.wedged)) {
Eric Anholt673a3942008-07-30 12:06:12 -07001789 i915_gem_retire_request(dev, request);
1790
1791 list_del(&request->list);
Eric Anholtb9624422009-06-03 07:27:35 +00001792 list_del(&request->client_list);
Eric Anholt9a298b22009-03-24 12:23:04 -07001793 kfree(request);
Eric Anholt673a3942008-07-30 12:06:12 -07001794 } else
1795 break;
1796 }
Chris Wilson9d34e5d2009-09-24 05:26:06 +01001797
1798 if (unlikely (dev_priv->trace_irq_seqno &&
1799 i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1800 i915_user_irq_put(dev);
1801 dev_priv->trace_irq_seqno = 0;
1802 }
Eric Anholt673a3942008-07-30 12:06:12 -07001803}
1804
1805void
1806i915_gem_retire_work_handler(struct work_struct *work)
1807{
1808 drm_i915_private_t *dev_priv;
1809 struct drm_device *dev;
1810
1811 dev_priv = container_of(work, drm_i915_private_t,
1812 mm.retire_work.work);
1813 dev = dev_priv->dev;
1814
1815 mutex_lock(&dev->struct_mutex);
1816 i915_gem_retire_requests(dev);
Keith Packard6dbe2772008-10-14 21:41:13 -07001817 if (!dev_priv->mm.suspended &&
1818 !list_empty(&dev_priv->mm.request_list))
Eric Anholt9c9fe1f2009-08-03 16:09:16 -07001819 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
Eric Anholt673a3942008-07-30 12:06:12 -07001820 mutex_unlock(&dev->struct_mutex);
1821}
1822
1823/**
1824 * Waits for a sequence number to be signaled, and cleans up the
1825 * request and object lists appropriately for that event.
1826 */
Eric Anholt3043c602008-10-02 12:24:47 -07001827static int
Eric Anholt673a3942008-07-30 12:06:12 -07001828i915_wait_request(struct drm_device *dev, uint32_t seqno)
1829{
1830 drm_i915_private_t *dev_priv = dev->dev_private;
Jesse Barnes802c7eb2009-05-05 16:03:48 -07001831 u32 ier;
Eric Anholt673a3942008-07-30 12:06:12 -07001832 int ret = 0;
1833
1834 BUG_ON(seqno == 0);
1835
Ben Gamariba1234d2009-09-14 17:48:47 -04001836 if (atomic_read(&dev_priv->mm.wedged))
Ben Gamariffed1d02009-09-14 17:48:41 -04001837 return -EIO;
1838
Eric Anholt673a3942008-07-30 12:06:12 -07001839 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001840 if (IS_IGDNG(dev))
1841 ier = I915_READ(DEIER) | I915_READ(GTIER);
1842 else
1843 ier = I915_READ(IER);
Jesse Barnes802c7eb2009-05-05 16:03:48 -07001844 if (!ier) {
1845 DRM_ERROR("something (likely vbetool) disabled "
1846 "interrupts, re-enabling\n");
1847 i915_driver_irq_preinstall(dev);
1848 i915_driver_irq_postinstall(dev);
1849 }
1850
Chris Wilson1c5d22f2009-08-25 11:15:50 +01001851 trace_i915_gem_request_wait_begin(dev, seqno);
1852
Eric Anholt673a3942008-07-30 12:06:12 -07001853 dev_priv->mm.waiting_gem_seqno = seqno;
1854 i915_user_irq_get(dev);
1855 ret = wait_event_interruptible(dev_priv->irq_queue,
1856 i915_seqno_passed(i915_get_gem_seqno(dev),
1857 seqno) ||
Ben Gamariba1234d2009-09-14 17:48:47 -04001858 atomic_read(&dev_priv->mm.wedged));
Eric Anholt673a3942008-07-30 12:06:12 -07001859 i915_user_irq_put(dev);
1860 dev_priv->mm.waiting_gem_seqno = 0;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01001861
1862 trace_i915_gem_request_wait_end(dev, seqno);
Eric Anholt673a3942008-07-30 12:06:12 -07001863 }
Ben Gamariba1234d2009-09-14 17:48:47 -04001864 if (atomic_read(&dev_priv->mm.wedged))
Eric Anholt673a3942008-07-30 12:06:12 -07001865 ret = -EIO;
1866
1867 if (ret && ret != -ERESTARTSYS)
1868 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1869 __func__, ret, seqno, i915_get_gem_seqno(dev));
1870
1871 /* Directly dispatch request retiring. While we have the work queue
1872 * to handle this, the waiter on a request often wants an associated
1873 * buffer to have made it to the inactive list, and we would need
1874 * a separate wait queue to handle that.
1875 */
1876 if (ret == 0)
1877 i915_gem_retire_requests(dev);
1878
1879 return ret;
1880}
1881
1882static void
1883i915_gem_flush(struct drm_device *dev,
1884 uint32_t invalidate_domains,
1885 uint32_t flush_domains)
1886{
1887 drm_i915_private_t *dev_priv = dev->dev_private;
1888 uint32_t cmd;
1889 RING_LOCALS;
1890
1891#if WATCH_EXEC
1892 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1893 invalidate_domains, flush_domains);
1894#endif
Chris Wilson1c5d22f2009-08-25 11:15:50 +01001895 trace_i915_gem_request_flush(dev, dev_priv->mm.next_gem_seqno,
1896 invalidate_domains, flush_domains);
Eric Anholt673a3942008-07-30 12:06:12 -07001897
1898 if (flush_domains & I915_GEM_DOMAIN_CPU)
1899 drm_agp_chipset_flush(dev);
1900
Chris Wilson21d509e2009-06-06 09:46:02 +01001901 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
Eric Anholt673a3942008-07-30 12:06:12 -07001902 /*
1903 * read/write caches:
1904 *
1905 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1906 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1907 * also flushed at 2d versus 3d pipeline switches.
1908 *
1909 * read-only caches:
1910 *
1911 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1912 * MI_READ_FLUSH is set, and is always flushed on 965.
1913 *
1914 * I915_GEM_DOMAIN_COMMAND may not exist?
1915 *
1916 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1917 * invalidated when MI_EXE_FLUSH is set.
1918 *
1919 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1920 * invalidated with every MI_FLUSH.
1921 *
1922 * TLBs:
1923 *
1924 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1925 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1926 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1927 * are flushed at any MI_FLUSH.
1928 */
1929
1930 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1931 if ((invalidate_domains|flush_domains) &
1932 I915_GEM_DOMAIN_RENDER)
1933 cmd &= ~MI_NO_WRITE_FLUSH;
1934 if (!IS_I965G(dev)) {
1935 /*
1936 * On the 965, the sampler cache always gets flushed
1937 * and this bit is reserved.
1938 */
1939 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1940 cmd |= MI_READ_FLUSH;
1941 }
1942 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1943 cmd |= MI_EXE_FLUSH;
1944
1945#if WATCH_EXEC
1946 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1947#endif
1948 BEGIN_LP_RING(2);
1949 OUT_RING(cmd);
1950 OUT_RING(0); /* noop */
1951 ADVANCE_LP_RING();
1952 }
1953}
1954
1955/**
1956 * Ensures that all rendering to the object has completed and the object is
1957 * safe to unbind from the GTT or access from the CPU.
1958 */
1959static int
1960i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1961{
1962 struct drm_device *dev = obj->dev;
1963 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1964 int ret;
1965
Eric Anholte47c68e2008-11-14 13:35:19 -08001966 /* This function only exists to support waiting for existing rendering,
1967 * not for emitting required flushes.
Eric Anholt673a3942008-07-30 12:06:12 -07001968 */
Eric Anholte47c68e2008-11-14 13:35:19 -08001969 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
Eric Anholt673a3942008-07-30 12:06:12 -07001970
1971 /* If there is rendering queued on the buffer being evicted, wait for
1972 * it.
1973 */
1974 if (obj_priv->active) {
1975#if WATCH_BUF
1976 DRM_INFO("%s: object %p wait for seqno %08x\n",
1977 __func__, obj, obj_priv->last_rendering_seqno);
1978#endif
1979 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1980 if (ret != 0)
1981 return ret;
1982 }
1983
1984 return 0;
1985}
1986
1987/**
1988 * Unbinds an object from the GTT aperture.
1989 */
Jesse Barnes0f973f22009-01-26 17:10:45 -08001990int
Eric Anholt673a3942008-07-30 12:06:12 -07001991i915_gem_object_unbind(struct drm_gem_object *obj)
1992{
1993 struct drm_device *dev = obj->dev;
1994 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1995 int ret = 0;
1996
1997#if WATCH_BUF
1998 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1999 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
2000#endif
2001 if (obj_priv->gtt_space == NULL)
2002 return 0;
2003
2004 if (obj_priv->pin_count != 0) {
2005 DRM_ERROR("Attempting to unbind pinned buffer\n");
2006 return -EINVAL;
2007 }
2008
Eric Anholt5323fd02009-09-09 11:50:45 -07002009 /* blow away mappings if mapped through GTT */
2010 i915_gem_release_mmap(obj);
2011
2012 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2013 i915_gem_clear_fence_reg(obj);
2014
Eric Anholt673a3942008-07-30 12:06:12 -07002015 /* Move the object to the CPU domain to ensure that
2016 * any possible CPU writes while it's not in the GTT
2017 * are flushed when we go to remap it. This will
2018 * also ensure that all pending GPU writes are finished
2019 * before we unbind.
2020 */
Eric Anholte47c68e2008-11-14 13:35:19 -08002021 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
Eric Anholt673a3942008-07-30 12:06:12 -07002022 if (ret) {
Eric Anholte47c68e2008-11-14 13:35:19 -08002023 if (ret != -ERESTARTSYS)
2024 DRM_ERROR("set_domain failed: %d\n", ret);
Eric Anholt673a3942008-07-30 12:06:12 -07002025 return ret;
2026 }
2027
Eric Anholt5323fd02009-09-09 11:50:45 -07002028 BUG_ON(obj_priv->active);
2029
Eric Anholt673a3942008-07-30 12:06:12 -07002030 if (obj_priv->agp_mem != NULL) {
2031 drm_unbind_agp(obj_priv->agp_mem);
2032 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
2033 obj_priv->agp_mem = NULL;
2034 }
2035
Eric Anholt856fa192009-03-19 14:10:50 -07002036 i915_gem_object_put_pages(obj);
Chris Wilsona32808c2009-09-20 21:29:47 +01002037 BUG_ON(obj_priv->pages_refcount);
Eric Anholt673a3942008-07-30 12:06:12 -07002038
2039 if (obj_priv->gtt_space) {
2040 atomic_dec(&dev->gtt_count);
2041 atomic_sub(obj->size, &dev->gtt_memory);
2042
2043 drm_mm_put_block(obj_priv->gtt_space);
2044 obj_priv->gtt_space = NULL;
2045 }
2046
2047 /* Remove ourselves from the LRU list if present. */
2048 if (!list_empty(&obj_priv->list))
2049 list_del_init(&obj_priv->list);
2050
Chris Wilson963b4832009-09-20 23:03:54 +01002051 if (i915_gem_object_is_purgeable(obj_priv))
2052 i915_gem_object_truncate(obj);
2053
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002054 trace_i915_gem_object_unbind(obj);
2055
Eric Anholt673a3942008-07-30 12:06:12 -07002056 return 0;
2057}
2058
Chris Wilson07f73f62009-09-14 16:50:30 +01002059static struct drm_gem_object *
2060i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
2061{
2062 drm_i915_private_t *dev_priv = dev->dev_private;
2063 struct drm_i915_gem_object *obj_priv;
2064 struct drm_gem_object *best = NULL;
2065 struct drm_gem_object *first = NULL;
2066
2067 /* Try to find the smallest clean object */
2068 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
2069 struct drm_gem_object *obj = obj_priv->obj;
2070 if (obj->size >= min_size) {
Chris Wilson963b4832009-09-20 23:03:54 +01002071 if ((!obj_priv->dirty ||
2072 i915_gem_object_is_purgeable(obj_priv)) &&
Chris Wilson07f73f62009-09-14 16:50:30 +01002073 (!best || obj->size < best->size)) {
2074 best = obj;
2075 if (best->size == min_size)
2076 return best;
2077 }
2078 if (!first)
2079 first = obj;
2080 }
2081 }
2082
2083 return best ? best : first;
2084}
2085
Eric Anholt673a3942008-07-30 12:06:12 -07002086static int
Chris Wilson07f73f62009-09-14 16:50:30 +01002087i915_gem_evict_everything(struct drm_device *dev)
2088{
2089 drm_i915_private_t *dev_priv = dev->dev_private;
2090 uint32_t seqno;
2091 int ret;
2092 bool lists_empty;
2093
Chris Wilson07f73f62009-09-14 16:50:30 +01002094 spin_lock(&dev_priv->mm.active_list_lock);
2095 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2096 list_empty(&dev_priv->mm.flushing_list) &&
2097 list_empty(&dev_priv->mm.active_list));
2098 spin_unlock(&dev_priv->mm.active_list_lock);
2099
Chris Wilson97311292009-09-21 00:22:34 +01002100 if (lists_empty)
Chris Wilson07f73f62009-09-14 16:50:30 +01002101 return -ENOSPC;
Chris Wilson07f73f62009-09-14 16:50:30 +01002102
2103 /* Flush everything (on to the inactive lists) and evict */
2104 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2105 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
2106 if (seqno == 0)
2107 return -ENOMEM;
2108
2109 ret = i915_wait_request(dev, seqno);
2110 if (ret)
2111 return ret;
2112
Chris Wilsonab5ee572009-09-20 19:25:47 +01002113 ret = i915_gem_evict_from_inactive_list(dev);
Chris Wilson07f73f62009-09-14 16:50:30 +01002114 if (ret)
2115 return ret;
2116
2117 spin_lock(&dev_priv->mm.active_list_lock);
2118 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2119 list_empty(&dev_priv->mm.flushing_list) &&
2120 list_empty(&dev_priv->mm.active_list));
2121 spin_unlock(&dev_priv->mm.active_list_lock);
2122 BUG_ON(!lists_empty);
2123
Eric Anholt673a3942008-07-30 12:06:12 -07002124 return 0;
2125}
2126
2127static int
Chris Wilson07f73f62009-09-14 16:50:30 +01002128i915_gem_evict_something(struct drm_device *dev, int min_size)
Eric Anholt673a3942008-07-30 12:06:12 -07002129{
2130 drm_i915_private_t *dev_priv = dev->dev_private;
2131 struct drm_gem_object *obj;
Chris Wilson07f73f62009-09-14 16:50:30 +01002132 int ret;
Eric Anholt673a3942008-07-30 12:06:12 -07002133
2134 for (;;) {
Chris Wilson07f73f62009-09-14 16:50:30 +01002135 i915_gem_retire_requests(dev);
2136
Eric Anholt673a3942008-07-30 12:06:12 -07002137 /* If there's an inactive buffer available now, grab it
2138 * and be done.
2139 */
Chris Wilson07f73f62009-09-14 16:50:30 +01002140 obj = i915_gem_find_inactive_object(dev, min_size);
2141 if (obj) {
2142 struct drm_i915_gem_object *obj_priv;
2143
Eric Anholt673a3942008-07-30 12:06:12 -07002144#if WATCH_LRU
2145 DRM_INFO("%s: evicting %p\n", __func__, obj);
2146#endif
Chris Wilson07f73f62009-09-14 16:50:30 +01002147 obj_priv = obj->driver_private;
2148 BUG_ON(obj_priv->pin_count != 0);
Eric Anholt673a3942008-07-30 12:06:12 -07002149 BUG_ON(obj_priv->active);
2150
2151 /* Wait on the rendering and unbind the buffer. */
Chris Wilson07f73f62009-09-14 16:50:30 +01002152 return i915_gem_object_unbind(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07002153 }
2154
2155 /* If we didn't get anything, but the ring is still processing
Chris Wilson07f73f62009-09-14 16:50:30 +01002156 * things, wait for the next to finish and hopefully leave us
2157 * a buffer to evict.
Eric Anholt673a3942008-07-30 12:06:12 -07002158 */
2159 if (!list_empty(&dev_priv->mm.request_list)) {
2160 struct drm_i915_gem_request *request;
2161
2162 request = list_first_entry(&dev_priv->mm.request_list,
2163 struct drm_i915_gem_request,
2164 list);
2165
2166 ret = i915_wait_request(dev, request->seqno);
2167 if (ret)
Chris Wilson07f73f62009-09-14 16:50:30 +01002168 return ret;
Eric Anholt673a3942008-07-30 12:06:12 -07002169
Chris Wilson07f73f62009-09-14 16:50:30 +01002170 continue;
Eric Anholt673a3942008-07-30 12:06:12 -07002171 }
2172
2173 /* If we didn't have anything on the request list but there
2174 * are buffers awaiting a flush, emit one and try again.
2175 * When we wait on it, those buffers waiting for that flush
2176 * will get moved to inactive.
2177 */
2178 if (!list_empty(&dev_priv->mm.flushing_list)) {
Chris Wilson07f73f62009-09-14 16:50:30 +01002179 struct drm_i915_gem_object *obj_priv;
Eric Anholt673a3942008-07-30 12:06:12 -07002180
Chris Wilson9a1e2582009-09-20 20:16:50 +01002181 /* Find an object that we can immediately reuse */
2182 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
2183 obj = obj_priv->obj;
2184 if (obj->size >= min_size)
2185 break;
Eric Anholt673a3942008-07-30 12:06:12 -07002186
Chris Wilson9a1e2582009-09-20 20:16:50 +01002187 obj = NULL;
2188 }
Eric Anholt673a3942008-07-30 12:06:12 -07002189
Chris Wilson9a1e2582009-09-20 20:16:50 +01002190 if (obj != NULL) {
2191 uint32_t seqno;
Chris Wilson07f73f62009-09-14 16:50:30 +01002192
Chris Wilson9a1e2582009-09-20 20:16:50 +01002193 i915_gem_flush(dev,
2194 obj->write_domain,
2195 obj->write_domain);
2196 seqno = i915_add_request(dev, NULL, obj->write_domain);
2197 if (seqno == 0)
2198 return -ENOMEM;
2199
2200 ret = i915_wait_request(dev, seqno);
2201 if (ret)
2202 return ret;
2203
2204 continue;
2205 }
Eric Anholt673a3942008-07-30 12:06:12 -07002206 }
2207
Chris Wilson07f73f62009-09-14 16:50:30 +01002208 /* If we didn't do any of the above, there's no single buffer
2209 * large enough to swap out for the new one, so just evict
2210 * everything and start again. (This should be rare.)
Eric Anholt673a3942008-07-30 12:06:12 -07002211 */
Chris Wilson97311292009-09-21 00:22:34 +01002212 if (!list_empty (&dev_priv->mm.inactive_list))
Chris Wilsonab5ee572009-09-20 19:25:47 +01002213 return i915_gem_evict_from_inactive_list(dev);
Chris Wilson97311292009-09-21 00:22:34 +01002214 else
Chris Wilson07f73f62009-09-14 16:50:30 +01002215 return i915_gem_evict_everything(dev);
Eric Anholt673a3942008-07-30 12:06:12 -07002216 }
Keith Packardac94a962008-11-20 23:30:27 -08002217}
2218
Ben Gamari6911a9b2009-04-02 11:24:54 -07002219int
Eric Anholt856fa192009-03-19 14:10:50 -07002220i915_gem_object_get_pages(struct drm_gem_object *obj)
Eric Anholt673a3942008-07-30 12:06:12 -07002221{
2222 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2223 int page_count, i;
2224 struct address_space *mapping;
2225 struct inode *inode;
2226 struct page *page;
2227 int ret;
2228
Eric Anholt856fa192009-03-19 14:10:50 -07002229 if (obj_priv->pages_refcount++ != 0)
Eric Anholt673a3942008-07-30 12:06:12 -07002230 return 0;
2231
2232 /* Get the list of pages out of our struct file. They'll be pinned
2233 * at this point until we release them.
2234 */
2235 page_count = obj->size / PAGE_SIZE;
Eric Anholt856fa192009-03-19 14:10:50 -07002236 BUG_ON(obj_priv->pages != NULL);
Jesse Barnes8e7d2b22009-05-08 16:13:25 -07002237 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
Eric Anholt856fa192009-03-19 14:10:50 -07002238 if (obj_priv->pages == NULL) {
Eric Anholt856fa192009-03-19 14:10:50 -07002239 obj_priv->pages_refcount--;
Eric Anholt673a3942008-07-30 12:06:12 -07002240 return -ENOMEM;
2241 }
2242
2243 inode = obj->filp->f_path.dentry->d_inode;
2244 mapping = inode->i_mapping;
2245 for (i = 0; i < page_count; i++) {
2246 page = read_mapping_page(mapping, i, NULL);
2247 if (IS_ERR(page)) {
2248 ret = PTR_ERR(page);
Eric Anholt856fa192009-03-19 14:10:50 -07002249 i915_gem_object_put_pages(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07002250 return ret;
2251 }
Eric Anholt856fa192009-03-19 14:10:50 -07002252 obj_priv->pages[i] = page;
Eric Anholt673a3942008-07-30 12:06:12 -07002253 }
Eric Anholt280b7132009-03-12 16:56:27 -07002254
2255 if (obj_priv->tiling_mode != I915_TILING_NONE)
2256 i915_gem_object_do_bit_17_swizzle(obj);
2257
Eric Anholt673a3942008-07-30 12:06:12 -07002258 return 0;
2259}
2260
Jesse Barnesde151cf2008-11-12 10:03:55 -08002261static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2262{
2263 struct drm_gem_object *obj = reg->obj;
2264 struct drm_device *dev = obj->dev;
2265 drm_i915_private_t *dev_priv = dev->dev_private;
2266 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2267 int regnum = obj_priv->fence_reg;
2268 uint64_t val;
2269
2270 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2271 0xfffff000) << 32;
2272 val |= obj_priv->gtt_offset & 0xfffff000;
2273 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2274 if (obj_priv->tiling_mode == I915_TILING_Y)
2275 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2276 val |= I965_FENCE_REG_VALID;
2277
2278 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2279}
2280
2281static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2282{
2283 struct drm_gem_object *obj = reg->obj;
2284 struct drm_device *dev = obj->dev;
2285 drm_i915_private_t *dev_priv = dev->dev_private;
2286 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2287 int regnum = obj_priv->fence_reg;
Jesse Barnes0f973f22009-01-26 17:10:45 -08002288 int tile_width;
Eric Anholtdc529a42009-03-10 22:34:49 -07002289 uint32_t fence_reg, val;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002290 uint32_t pitch_val;
2291
2292 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2293 (obj_priv->gtt_offset & (obj->size - 1))) {
Linus Torvaldsf06da262009-02-09 08:57:29 -08002294 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
Jesse Barnes0f973f22009-01-26 17:10:45 -08002295 __func__, obj_priv->gtt_offset, obj->size);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002296 return;
2297 }
2298
Jesse Barnes0f973f22009-01-26 17:10:45 -08002299 if (obj_priv->tiling_mode == I915_TILING_Y &&
2300 HAS_128_BYTE_Y_TILING(dev))
2301 tile_width = 128;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002302 else
Jesse Barnes0f973f22009-01-26 17:10:45 -08002303 tile_width = 512;
2304
2305 /* Note: pitch better be a power of two tile widths */
2306 pitch_val = obj_priv->stride / tile_width;
2307 pitch_val = ffs(pitch_val) - 1;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002308
2309 val = obj_priv->gtt_offset;
2310 if (obj_priv->tiling_mode == I915_TILING_Y)
2311 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2312 val |= I915_FENCE_SIZE_BITS(obj->size);
2313 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2314 val |= I830_FENCE_REG_VALID;
2315
Eric Anholtdc529a42009-03-10 22:34:49 -07002316 if (regnum < 8)
2317 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2318 else
2319 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2320 I915_WRITE(fence_reg, val);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002321}
2322
2323static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2324{
2325 struct drm_gem_object *obj = reg->obj;
2326 struct drm_device *dev = obj->dev;
2327 drm_i915_private_t *dev_priv = dev->dev_private;
2328 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2329 int regnum = obj_priv->fence_reg;
2330 uint32_t val;
2331 uint32_t pitch_val;
Daniel Vetter8d7773a2009-03-29 14:09:41 +02002332 uint32_t fence_size_bits;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002333
Daniel Vetter8d7773a2009-03-29 14:09:41 +02002334 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
Jesse Barnesde151cf2008-11-12 10:03:55 -08002335 (obj_priv->gtt_offset & (obj->size - 1))) {
Daniel Vetter8d7773a2009-03-29 14:09:41 +02002336 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
Jesse Barnes0f973f22009-01-26 17:10:45 -08002337 __func__, obj_priv->gtt_offset);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002338 return;
2339 }
2340
Eric Anholte76a16d2009-05-26 17:44:56 -07002341 pitch_val = obj_priv->stride / 128;
2342 pitch_val = ffs(pitch_val) - 1;
2343 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2344
Jesse Barnesde151cf2008-11-12 10:03:55 -08002345 val = obj_priv->gtt_offset;
2346 if (obj_priv->tiling_mode == I915_TILING_Y)
2347 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
Daniel Vetter8d7773a2009-03-29 14:09:41 +02002348 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2349 WARN_ON(fence_size_bits & ~0x00000f00);
2350 val |= fence_size_bits;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002351 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2352 val |= I830_FENCE_REG_VALID;
2353
2354 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002355}
2356
2357/**
2358 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2359 * @obj: object to map through a fence reg
2360 *
2361 * When mapping objects through the GTT, userspace wants to be able to write
2362 * to them without having to worry about swizzling if the object is tiled.
2363 *
2364 * This function walks the fence regs looking for a free one for @obj,
2365 * stealing one if it can't find any.
2366 *
2367 * It then sets up the reg based on the object's properties: address, pitch
2368 * and tiling format.
2369 */
Chris Wilson8c4b8c32009-06-17 22:08:52 +01002370int
2371i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
Jesse Barnesde151cf2008-11-12 10:03:55 -08002372{
2373 struct drm_device *dev = obj->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08002374 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002375 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2376 struct drm_i915_fence_reg *reg = NULL;
Chris Wilsonfc7170b2009-02-11 14:26:46 +00002377 struct drm_i915_gem_object *old_obj_priv = NULL;
2378 int i, ret, avail;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002379
Eric Anholta09ba7f2009-08-29 12:49:51 -07002380 /* Just update our place in the LRU if our fence is getting used. */
2381 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2382 list_move_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2383 return 0;
2384 }
2385
Jesse Barnesde151cf2008-11-12 10:03:55 -08002386 switch (obj_priv->tiling_mode) {
2387 case I915_TILING_NONE:
2388 WARN(1, "allocating a fence for non-tiled object?\n");
2389 break;
2390 case I915_TILING_X:
Jesse Barnes0f973f22009-01-26 17:10:45 -08002391 if (!obj_priv->stride)
2392 return -EINVAL;
2393 WARN((obj_priv->stride & (512 - 1)),
2394 "object 0x%08x is X tiled but has non-512B pitch\n",
2395 obj_priv->gtt_offset);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002396 break;
2397 case I915_TILING_Y:
Jesse Barnes0f973f22009-01-26 17:10:45 -08002398 if (!obj_priv->stride)
2399 return -EINVAL;
2400 WARN((obj_priv->stride & (128 - 1)),
2401 "object 0x%08x is Y tiled but has non-128B pitch\n",
2402 obj_priv->gtt_offset);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002403 break;
2404 }
2405
2406 /* First try to find a free reg */
Chris Wilsonfc7170b2009-02-11 14:26:46 +00002407 avail = 0;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002408 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2409 reg = &dev_priv->fence_regs[i];
2410 if (!reg->obj)
2411 break;
Chris Wilsonfc7170b2009-02-11 14:26:46 +00002412
2413 old_obj_priv = reg->obj->driver_private;
2414 if (!old_obj_priv->pin_count)
2415 avail++;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002416 }
2417
2418 /* None available, try to steal one or wait for a user to finish */
2419 if (i == dev_priv->num_fence_regs) {
Eric Anholta09ba7f2009-08-29 12:49:51 -07002420 struct drm_gem_object *old_obj = NULL;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002421
Chris Wilsonfc7170b2009-02-11 14:26:46 +00002422 if (avail == 0)
Chris Wilson2939e1f2009-06-06 09:46:03 +01002423 return -ENOSPC;
Chris Wilsonfc7170b2009-02-11 14:26:46 +00002424
Eric Anholta09ba7f2009-08-29 12:49:51 -07002425 list_for_each_entry(old_obj_priv, &dev_priv->mm.fence_list,
2426 fence_list) {
2427 old_obj = old_obj_priv->obj;
Chris Wilsond7619c42009-02-11 14:26:47 +00002428
Chris Wilsond7619c42009-02-11 14:26:47 +00002429 if (old_obj_priv->pin_count)
2430 continue;
2431
Eric Anholta09ba7f2009-08-29 12:49:51 -07002432 /* Take a reference, as otherwise the wait_rendering
2433 * below may cause the object to get freed out from
2434 * under us.
2435 */
2436 drm_gem_object_reference(old_obj);
2437
Chris Wilsond7619c42009-02-11 14:26:47 +00002438 /* i915 uses fences for GPU access to tiled buffers */
2439 if (IS_I965G(dev) || !old_obj_priv->active)
Jesse Barnesde151cf2008-11-12 10:03:55 -08002440 break;
Chris Wilsond7619c42009-02-11 14:26:47 +00002441
Eric Anholta09ba7f2009-08-29 12:49:51 -07002442 /* This brings the object to the head of the LRU if it
2443 * had been written to. The only way this should
2444 * result in us waiting longer than the expected
2445 * optimal amount of time is if there was a
2446 * fence-using buffer later that was read-only.
2447 */
2448 i915_gem_object_flush_gpu_write_domain(old_obj);
2449 ret = i915_gem_object_wait_rendering(old_obj);
Chris Wilson58c2fb62009-09-01 12:02:39 +01002450 if (ret != 0) {
2451 drm_gem_object_unreference(old_obj);
Chris Wilsond7619c42009-02-11 14:26:47 +00002452 return ret;
Chris Wilson58c2fb62009-09-01 12:02:39 +01002453 }
2454
Eric Anholta09ba7f2009-08-29 12:49:51 -07002455 break;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002456 }
2457
2458 /*
2459 * Zap this virtual mapping so we can set up a fence again
2460 * for this object next time we need it.
2461 */
Chris Wilson58c2fb62009-09-01 12:02:39 +01002462 i915_gem_release_mmap(old_obj);
2463
Eric Anholta09ba7f2009-08-29 12:49:51 -07002464 i = old_obj_priv->fence_reg;
Chris Wilson58c2fb62009-09-01 12:02:39 +01002465 reg = &dev_priv->fence_regs[i];
2466
Jesse Barnesde151cf2008-11-12 10:03:55 -08002467 old_obj_priv->fence_reg = I915_FENCE_REG_NONE;
Eric Anholta09ba7f2009-08-29 12:49:51 -07002468 list_del_init(&old_obj_priv->fence_list);
Chris Wilson58c2fb62009-09-01 12:02:39 +01002469
Eric Anholta09ba7f2009-08-29 12:49:51 -07002470 drm_gem_object_unreference(old_obj);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002471 }
2472
2473 obj_priv->fence_reg = i;
Eric Anholta09ba7f2009-08-29 12:49:51 -07002474 list_add_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2475
Jesse Barnesde151cf2008-11-12 10:03:55 -08002476 reg->obj = obj;
2477
2478 if (IS_I965G(dev))
2479 i965_write_fence_reg(reg);
2480 else if (IS_I9XX(dev))
2481 i915_write_fence_reg(reg);
2482 else
2483 i830_write_fence_reg(reg);
Eric Anholtd9ddcb92009-01-27 10:33:49 -08002484
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002485 trace_i915_gem_object_get_fence(obj, i, obj_priv->tiling_mode);
2486
Eric Anholtd9ddcb92009-01-27 10:33:49 -08002487 return 0;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002488}
2489
2490/**
2491 * i915_gem_clear_fence_reg - clear out fence register info
2492 * @obj: object to clear
2493 *
2494 * Zeroes out the fence register itself and clears out the associated
2495 * data structures in dev_priv and obj_priv.
2496 */
2497static void
2498i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2499{
2500 struct drm_device *dev = obj->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08002501 drm_i915_private_t *dev_priv = dev->dev_private;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002502 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2503
2504 if (IS_I965G(dev))
2505 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
Eric Anholtdc529a42009-03-10 22:34:49 -07002506 else {
2507 uint32_t fence_reg;
2508
2509 if (obj_priv->fence_reg < 8)
2510 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2511 else
2512 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2513 8) * 4;
2514
2515 I915_WRITE(fence_reg, 0);
2516 }
Jesse Barnesde151cf2008-11-12 10:03:55 -08002517
2518 dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
2519 obj_priv->fence_reg = I915_FENCE_REG_NONE;
Eric Anholta09ba7f2009-08-29 12:49:51 -07002520 list_del_init(&obj_priv->fence_list);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002521}
2522
Eric Anholt673a3942008-07-30 12:06:12 -07002523/**
Chris Wilson52dc7d32009-06-06 09:46:01 +01002524 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2525 * to the buffer to finish, and then resets the fence register.
2526 * @obj: tiled object holding a fence register.
2527 *
2528 * Zeroes out the fence register itself and clears out the associated
2529 * data structures in dev_priv and obj_priv.
2530 */
2531int
2532i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2533{
2534 struct drm_device *dev = obj->dev;
2535 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2536
2537 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2538 return 0;
2539
2540 /* On the i915, GPU access to tiled buffers is via a fence,
2541 * therefore we must wait for any outstanding access to complete
2542 * before clearing the fence.
2543 */
2544 if (!IS_I965G(dev)) {
2545 int ret;
2546
2547 i915_gem_object_flush_gpu_write_domain(obj);
2548 i915_gem_object_flush_gtt_write_domain(obj);
2549 ret = i915_gem_object_wait_rendering(obj);
2550 if (ret != 0)
2551 return ret;
2552 }
2553
2554 i915_gem_clear_fence_reg (obj);
2555
2556 return 0;
2557}
2558
2559/**
Eric Anholt673a3942008-07-30 12:06:12 -07002560 * Finds free space in the GTT aperture and binds the object there.
2561 */
2562static int
2563i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2564{
2565 struct drm_device *dev = obj->dev;
2566 drm_i915_private_t *dev_priv = dev->dev_private;
2567 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2568 struct drm_mm_node *free_space;
Chris Wilson07f73f62009-09-14 16:50:30 +01002569 bool retry_alloc = false;
2570 int ret;
Eric Anholt673a3942008-07-30 12:06:12 -07002571
Eric Anholt9bb2d6f2008-12-23 18:42:32 -08002572 if (dev_priv->mm.suspended)
2573 return -EBUSY;
Chris Wilson3ef94da2009-09-14 16:50:29 +01002574
Chris Wilsonbb6baf72009-09-22 14:24:13 +01002575 if (obj_priv->madv != I915_MADV_WILLNEED) {
Chris Wilson3ef94da2009-09-14 16:50:29 +01002576 DRM_ERROR("Attempting to bind a purgeable object\n");
2577 return -EINVAL;
2578 }
2579
Eric Anholt673a3942008-07-30 12:06:12 -07002580 if (alignment == 0)
Jesse Barnes0f973f22009-01-26 17:10:45 -08002581 alignment = i915_gem_get_gtt_alignment(obj);
Daniel Vetter8d7773a2009-03-29 14:09:41 +02002582 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
Eric Anholt673a3942008-07-30 12:06:12 -07002583 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2584 return -EINVAL;
2585 }
2586
2587 search_free:
2588 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2589 obj->size, alignment, 0);
2590 if (free_space != NULL) {
2591 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2592 alignment);
2593 if (obj_priv->gtt_space != NULL) {
2594 obj_priv->gtt_space->private = obj;
2595 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2596 }
2597 }
2598 if (obj_priv->gtt_space == NULL) {
2599 /* If the gtt is empty and we're still having trouble
2600 * fitting our object in, we're out of memory.
2601 */
2602#if WATCH_LRU
2603 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2604#endif
Chris Wilson07f73f62009-09-14 16:50:30 +01002605 ret = i915_gem_evict_something(dev, obj->size);
Chris Wilson97311292009-09-21 00:22:34 +01002606 if (ret)
Eric Anholt673a3942008-07-30 12:06:12 -07002607 return ret;
Chris Wilson97311292009-09-21 00:22:34 +01002608
Eric Anholt673a3942008-07-30 12:06:12 -07002609 goto search_free;
2610 }
2611
2612#if WATCH_BUF
Krzysztof Halasacfd43c02009-06-20 00:31:28 +02002613 DRM_INFO("Binding object of size %zd at 0x%08x\n",
Eric Anholt673a3942008-07-30 12:06:12 -07002614 obj->size, obj_priv->gtt_offset);
2615#endif
Chris Wilson07f73f62009-09-14 16:50:30 +01002616 if (retry_alloc) {
2617 i915_gem_object_set_page_gfp_mask (obj,
2618 i915_gem_object_get_page_gfp_mask (obj) & ~__GFP_NORETRY);
2619 }
Eric Anholt856fa192009-03-19 14:10:50 -07002620 ret = i915_gem_object_get_pages(obj);
Chris Wilson07f73f62009-09-14 16:50:30 +01002621 if (retry_alloc) {
2622 i915_gem_object_set_page_gfp_mask (obj,
2623 i915_gem_object_get_page_gfp_mask (obj) | __GFP_NORETRY);
2624 }
Eric Anholt673a3942008-07-30 12:06:12 -07002625 if (ret) {
2626 drm_mm_put_block(obj_priv->gtt_space);
2627 obj_priv->gtt_space = NULL;
Chris Wilson07f73f62009-09-14 16:50:30 +01002628
2629 if (ret == -ENOMEM) {
2630 /* first try to clear up some space from the GTT */
2631 ret = i915_gem_evict_something(dev, obj->size);
2632 if (ret) {
Chris Wilson07f73f62009-09-14 16:50:30 +01002633 /* now try to shrink everyone else */
2634 if (! retry_alloc) {
2635 retry_alloc = true;
2636 goto search_free;
2637 }
2638
2639 return ret;
2640 }
2641
2642 goto search_free;
2643 }
2644
Eric Anholt673a3942008-07-30 12:06:12 -07002645 return ret;
2646 }
2647
Eric Anholt673a3942008-07-30 12:06:12 -07002648 /* Create an AGP memory structure pointing at our pages, and bind it
2649 * into the GTT.
2650 */
2651 obj_priv->agp_mem = drm_agp_bind_pages(dev,
Eric Anholt856fa192009-03-19 14:10:50 -07002652 obj_priv->pages,
Chris Wilson07f73f62009-09-14 16:50:30 +01002653 obj->size >> PAGE_SHIFT,
Keith Packardba1eb1d2008-10-14 19:55:10 -07002654 obj_priv->gtt_offset,
2655 obj_priv->agp_type);
Eric Anholt673a3942008-07-30 12:06:12 -07002656 if (obj_priv->agp_mem == NULL) {
Eric Anholt856fa192009-03-19 14:10:50 -07002657 i915_gem_object_put_pages(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07002658 drm_mm_put_block(obj_priv->gtt_space);
2659 obj_priv->gtt_space = NULL;
Chris Wilson07f73f62009-09-14 16:50:30 +01002660
2661 ret = i915_gem_evict_something(dev, obj->size);
Chris Wilson97311292009-09-21 00:22:34 +01002662 if (ret)
Chris Wilson07f73f62009-09-14 16:50:30 +01002663 return ret;
Chris Wilson07f73f62009-09-14 16:50:30 +01002664
2665 goto search_free;
Eric Anholt673a3942008-07-30 12:06:12 -07002666 }
2667 atomic_inc(&dev->gtt_count);
2668 atomic_add(obj->size, &dev->gtt_memory);
2669
2670 /* Assert that the object is not currently in any GPU domain. As it
2671 * wasn't in the GTT, there shouldn't be any way it could have been in
2672 * a GPU cache
2673 */
Chris Wilson21d509e2009-06-06 09:46:02 +01002674 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2675 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
Eric Anholt673a3942008-07-30 12:06:12 -07002676
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002677 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2678
Eric Anholt673a3942008-07-30 12:06:12 -07002679 return 0;
2680}
2681
2682void
2683i915_gem_clflush_object(struct drm_gem_object *obj)
2684{
2685 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2686
2687 /* If we don't have a page list set up, then we're not pinned
2688 * to GPU, and we can ignore the cache flush because it'll happen
2689 * again at bind time.
2690 */
Eric Anholt856fa192009-03-19 14:10:50 -07002691 if (obj_priv->pages == NULL)
Eric Anholt673a3942008-07-30 12:06:12 -07002692 return;
2693
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002694 trace_i915_gem_object_clflush(obj);
Eric Anholtcfa16a02009-05-26 18:46:16 -07002695
Eric Anholt856fa192009-03-19 14:10:50 -07002696 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
Eric Anholt673a3942008-07-30 12:06:12 -07002697}
2698
Eric Anholte47c68e2008-11-14 13:35:19 -08002699/** Flushes any GPU write domain for the object if it's dirty. */
2700static void
2701i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2702{
2703 struct drm_device *dev = obj->dev;
2704 uint32_t seqno;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002705 uint32_t old_write_domain;
Eric Anholte47c68e2008-11-14 13:35:19 -08002706
2707 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2708 return;
2709
2710 /* Queue the GPU write cache flushing we need. */
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002711 old_write_domain = obj->write_domain;
Eric Anholte47c68e2008-11-14 13:35:19 -08002712 i915_gem_flush(dev, 0, obj->write_domain);
Eric Anholtb9624422009-06-03 07:27:35 +00002713 seqno = i915_add_request(dev, NULL, obj->write_domain);
Eric Anholte47c68e2008-11-14 13:35:19 -08002714 obj->write_domain = 0;
2715 i915_gem_object_move_to_active(obj, seqno);
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002716
2717 trace_i915_gem_object_change_domain(obj,
2718 obj->read_domains,
2719 old_write_domain);
Eric Anholte47c68e2008-11-14 13:35:19 -08002720}
2721
2722/** Flushes the GTT write domain for the object if it's dirty. */
2723static void
2724i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2725{
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002726 uint32_t old_write_domain;
2727
Eric Anholte47c68e2008-11-14 13:35:19 -08002728 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2729 return;
2730
2731 /* No actual flushing is required for the GTT write domain. Writes
2732 * to it immediately go to main memory as far as we know, so there's
2733 * no chipset flush. It also doesn't land in render cache.
2734 */
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002735 old_write_domain = obj->write_domain;
Eric Anholte47c68e2008-11-14 13:35:19 -08002736 obj->write_domain = 0;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002737
2738 trace_i915_gem_object_change_domain(obj,
2739 obj->read_domains,
2740 old_write_domain);
Eric Anholte47c68e2008-11-14 13:35:19 -08002741}
2742
2743/** Flushes the CPU write domain for the object if it's dirty. */
2744static void
2745i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2746{
2747 struct drm_device *dev = obj->dev;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002748 uint32_t old_write_domain;
Eric Anholte47c68e2008-11-14 13:35:19 -08002749
2750 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2751 return;
2752
2753 i915_gem_clflush_object(obj);
2754 drm_agp_chipset_flush(dev);
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002755 old_write_domain = obj->write_domain;
Eric Anholte47c68e2008-11-14 13:35:19 -08002756 obj->write_domain = 0;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002757
2758 trace_i915_gem_object_change_domain(obj,
2759 obj->read_domains,
2760 old_write_domain);
Eric Anholte47c68e2008-11-14 13:35:19 -08002761}
2762
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002763/**
2764 * Moves a single object to the GTT read, and possibly write domain.
2765 *
2766 * This function returns when the move is complete, including waiting on
2767 * flushes to occur.
2768 */
Jesse Barnes79e53942008-11-07 14:24:08 -08002769int
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002770i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2771{
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002772 struct drm_i915_gem_object *obj_priv = obj->driver_private;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002773 uint32_t old_write_domain, old_read_domains;
Eric Anholte47c68e2008-11-14 13:35:19 -08002774 int ret;
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002775
Eric Anholt02354392008-11-26 13:58:13 -08002776 /* Not valid to be called on unbound objects. */
2777 if (obj_priv->gtt_space == NULL)
2778 return -EINVAL;
2779
Eric Anholte47c68e2008-11-14 13:35:19 -08002780 i915_gem_object_flush_gpu_write_domain(obj);
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002781 /* Wait on any GPU rendering and flushing to occur. */
Eric Anholte47c68e2008-11-14 13:35:19 -08002782 ret = i915_gem_object_wait_rendering(obj);
2783 if (ret != 0)
2784 return ret;
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002785
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002786 old_write_domain = obj->write_domain;
2787 old_read_domains = obj->read_domains;
2788
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002789 /* If we're writing through the GTT domain, then CPU and GPU caches
2790 * will need to be invalidated at next use.
2791 */
2792 if (write)
Eric Anholte47c68e2008-11-14 13:35:19 -08002793 obj->read_domains &= I915_GEM_DOMAIN_GTT;
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002794
Eric Anholte47c68e2008-11-14 13:35:19 -08002795 i915_gem_object_flush_cpu_write_domain(obj);
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002796
2797 /* It should now be out of any other write domains, and we can update
2798 * the domain values for our changes.
2799 */
2800 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2801 obj->read_domains |= I915_GEM_DOMAIN_GTT;
Eric Anholte47c68e2008-11-14 13:35:19 -08002802 if (write) {
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002803 obj->write_domain = I915_GEM_DOMAIN_GTT;
Eric Anholte47c68e2008-11-14 13:35:19 -08002804 obj_priv->dirty = 1;
2805 }
2806
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002807 trace_i915_gem_object_change_domain(obj,
2808 old_read_domains,
2809 old_write_domain);
2810
Eric Anholte47c68e2008-11-14 13:35:19 -08002811 return 0;
2812}
2813
2814/**
2815 * Moves a single object to the CPU read, and possibly write domain.
2816 *
2817 * This function returns when the move is complete, including waiting on
2818 * flushes to occur.
2819 */
2820static int
2821i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2822{
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002823 uint32_t old_write_domain, old_read_domains;
Eric Anholte47c68e2008-11-14 13:35:19 -08002824 int ret;
2825
2826 i915_gem_object_flush_gpu_write_domain(obj);
2827 /* Wait on any GPU rendering and flushing to occur. */
2828 ret = i915_gem_object_wait_rendering(obj);
2829 if (ret != 0)
2830 return ret;
2831
2832 i915_gem_object_flush_gtt_write_domain(obj);
2833
2834 /* If we have a partially-valid cache of the object in the CPU,
2835 * finish invalidating it and free the per-page flags.
2836 */
2837 i915_gem_object_set_to_full_cpu_read_domain(obj);
2838
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002839 old_write_domain = obj->write_domain;
2840 old_read_domains = obj->read_domains;
2841
Eric Anholte47c68e2008-11-14 13:35:19 -08002842 /* Flush the CPU cache if it's still invalid. */
2843 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2844 i915_gem_clflush_object(obj);
Eric Anholte47c68e2008-11-14 13:35:19 -08002845
2846 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2847 }
2848
2849 /* It should now be out of any other write domains, and we can update
2850 * the domain values for our changes.
2851 */
2852 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2853
2854 /* If we're writing through the CPU, then the GPU read domains will
2855 * need to be invalidated at next use.
2856 */
2857 if (write) {
2858 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2859 obj->write_domain = I915_GEM_DOMAIN_CPU;
2860 }
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002861
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002862 trace_i915_gem_object_change_domain(obj,
2863 old_read_domains,
2864 old_write_domain);
2865
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002866 return 0;
2867}
2868
Eric Anholt673a3942008-07-30 12:06:12 -07002869/*
2870 * Set the next domain for the specified object. This
2871 * may not actually perform the necessary flushing/invaliding though,
2872 * as that may want to be batched with other set_domain operations
2873 *
2874 * This is (we hope) the only really tricky part of gem. The goal
2875 * is fairly simple -- track which caches hold bits of the object
2876 * and make sure they remain coherent. A few concrete examples may
2877 * help to explain how it works. For shorthand, we use the notation
2878 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2879 * a pair of read and write domain masks.
2880 *
2881 * Case 1: the batch buffer
2882 *
2883 * 1. Allocated
2884 * 2. Written by CPU
2885 * 3. Mapped to GTT
2886 * 4. Read by GPU
2887 * 5. Unmapped from GTT
2888 * 6. Freed
2889 *
2890 * Let's take these a step at a time
2891 *
2892 * 1. Allocated
2893 * Pages allocated from the kernel may still have
2894 * cache contents, so we set them to (CPU, CPU) always.
2895 * 2. Written by CPU (using pwrite)
2896 * The pwrite function calls set_domain (CPU, CPU) and
2897 * this function does nothing (as nothing changes)
2898 * 3. Mapped by GTT
2899 * This function asserts that the object is not
2900 * currently in any GPU-based read or write domains
2901 * 4. Read by GPU
2902 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2903 * As write_domain is zero, this function adds in the
2904 * current read domains (CPU+COMMAND, 0).
2905 * flush_domains is set to CPU.
2906 * invalidate_domains is set to COMMAND
2907 * clflush is run to get data out of the CPU caches
2908 * then i915_dev_set_domain calls i915_gem_flush to
2909 * emit an MI_FLUSH and drm_agp_chipset_flush
2910 * 5. Unmapped from GTT
2911 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2912 * flush_domains and invalidate_domains end up both zero
2913 * so no flushing/invalidating happens
2914 * 6. Freed
2915 * yay, done
2916 *
2917 * Case 2: The shared render buffer
2918 *
2919 * 1. Allocated
2920 * 2. Mapped to GTT
2921 * 3. Read/written by GPU
2922 * 4. set_domain to (CPU,CPU)
2923 * 5. Read/written by CPU
2924 * 6. Read/written by GPU
2925 *
2926 * 1. Allocated
2927 * Same as last example, (CPU, CPU)
2928 * 2. Mapped to GTT
2929 * Nothing changes (assertions find that it is not in the GPU)
2930 * 3. Read/written by GPU
2931 * execbuffer calls set_domain (RENDER, RENDER)
2932 * flush_domains gets CPU
2933 * invalidate_domains gets GPU
2934 * clflush (obj)
2935 * MI_FLUSH and drm_agp_chipset_flush
2936 * 4. set_domain (CPU, CPU)
2937 * flush_domains gets GPU
2938 * invalidate_domains gets CPU
2939 * wait_rendering (obj) to make sure all drawing is complete.
2940 * This will include an MI_FLUSH to get the data from GPU
2941 * to memory
2942 * clflush (obj) to invalidate the CPU cache
2943 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2944 * 5. Read/written by CPU
2945 * cache lines are loaded and dirtied
2946 * 6. Read written by GPU
2947 * Same as last GPU access
2948 *
2949 * Case 3: The constant buffer
2950 *
2951 * 1. Allocated
2952 * 2. Written by CPU
2953 * 3. Read by GPU
2954 * 4. Updated (written) by CPU again
2955 * 5. Read by GPU
2956 *
2957 * 1. Allocated
2958 * (CPU, CPU)
2959 * 2. Written by CPU
2960 * (CPU, CPU)
2961 * 3. Read by GPU
2962 * (CPU+RENDER, 0)
2963 * flush_domains = CPU
2964 * invalidate_domains = RENDER
2965 * clflush (obj)
2966 * MI_FLUSH
2967 * drm_agp_chipset_flush
2968 * 4. Updated (written) by CPU again
2969 * (CPU, CPU)
2970 * flush_domains = 0 (no previous write domain)
2971 * invalidate_domains = 0 (no new read domains)
2972 * 5. Read by GPU
2973 * (CPU+RENDER, 0)
2974 * flush_domains = CPU
2975 * invalidate_domains = RENDER
2976 * clflush (obj)
2977 * MI_FLUSH
2978 * drm_agp_chipset_flush
2979 */
Keith Packardc0d90822008-11-20 23:11:08 -08002980static void
Eric Anholt8b0e3782009-02-19 14:40:50 -08002981i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
Eric Anholt673a3942008-07-30 12:06:12 -07002982{
2983 struct drm_device *dev = obj->dev;
2984 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2985 uint32_t invalidate_domains = 0;
2986 uint32_t flush_domains = 0;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002987 uint32_t old_read_domains;
Eric Anholte47c68e2008-11-14 13:35:19 -08002988
Eric Anholt8b0e3782009-02-19 14:40:50 -08002989 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
2990 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
Eric Anholt673a3942008-07-30 12:06:12 -07002991
Jesse Barnes652c3932009-08-17 13:31:43 -07002992 intel_mark_busy(dev, obj);
2993
Eric Anholt673a3942008-07-30 12:06:12 -07002994#if WATCH_BUF
2995 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2996 __func__, obj,
Eric Anholt8b0e3782009-02-19 14:40:50 -08002997 obj->read_domains, obj->pending_read_domains,
2998 obj->write_domain, obj->pending_write_domain);
Eric Anholt673a3942008-07-30 12:06:12 -07002999#endif
3000 /*
3001 * If the object isn't moving to a new write domain,
3002 * let the object stay in multiple read domains
3003 */
Eric Anholt8b0e3782009-02-19 14:40:50 -08003004 if (obj->pending_write_domain == 0)
3005 obj->pending_read_domains |= obj->read_domains;
Eric Anholt673a3942008-07-30 12:06:12 -07003006 else
3007 obj_priv->dirty = 1;
3008
3009 /*
3010 * Flush the current write domain if
3011 * the new read domains don't match. Invalidate
3012 * any read domains which differ from the old
3013 * write domain
3014 */
Eric Anholt8b0e3782009-02-19 14:40:50 -08003015 if (obj->write_domain &&
3016 obj->write_domain != obj->pending_read_domains) {
Eric Anholt673a3942008-07-30 12:06:12 -07003017 flush_domains |= obj->write_domain;
Eric Anholt8b0e3782009-02-19 14:40:50 -08003018 invalidate_domains |=
3019 obj->pending_read_domains & ~obj->write_domain;
Eric Anholt673a3942008-07-30 12:06:12 -07003020 }
3021 /*
3022 * Invalidate any read caches which may have
3023 * stale data. That is, any new read domains.
3024 */
Eric Anholt8b0e3782009-02-19 14:40:50 -08003025 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
Eric Anholt673a3942008-07-30 12:06:12 -07003026 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3027#if WATCH_BUF
3028 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3029 __func__, flush_domains, invalidate_domains);
3030#endif
Eric Anholt673a3942008-07-30 12:06:12 -07003031 i915_gem_clflush_object(obj);
3032 }
3033
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003034 old_read_domains = obj->read_domains;
3035
Eric Anholtefbeed92009-02-19 14:54:51 -08003036 /* The actual obj->write_domain will be updated with
3037 * pending_write_domain after we emit the accumulated flush for all
3038 * of our domain changes in execbuffers (which clears objects'
3039 * write_domains). So if we have a current write domain that we
3040 * aren't changing, set pending_write_domain to that.
3041 */
3042 if (flush_domains == 0 && obj->pending_write_domain == 0)
3043 obj->pending_write_domain = obj->write_domain;
Eric Anholt8b0e3782009-02-19 14:40:50 -08003044 obj->read_domains = obj->pending_read_domains;
Eric Anholt673a3942008-07-30 12:06:12 -07003045
3046 dev->invalidate_domains |= invalidate_domains;
3047 dev->flush_domains |= flush_domains;
3048#if WATCH_BUF
3049 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3050 __func__,
3051 obj->read_domains, obj->write_domain,
3052 dev->invalidate_domains, dev->flush_domains);
3053#endif
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003054
3055 trace_i915_gem_object_change_domain(obj,
3056 old_read_domains,
3057 obj->write_domain);
Eric Anholt673a3942008-07-30 12:06:12 -07003058}
3059
3060/**
Eric Anholte47c68e2008-11-14 13:35:19 -08003061 * Moves the object from a partially CPU read to a full one.
Eric Anholt673a3942008-07-30 12:06:12 -07003062 *
Eric Anholte47c68e2008-11-14 13:35:19 -08003063 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3064 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3065 */
3066static void
3067i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3068{
Eric Anholte47c68e2008-11-14 13:35:19 -08003069 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3070
3071 if (!obj_priv->page_cpu_valid)
3072 return;
3073
3074 /* If we're partially in the CPU read domain, finish moving it in.
3075 */
3076 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3077 int i;
3078
3079 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3080 if (obj_priv->page_cpu_valid[i])
3081 continue;
Eric Anholt856fa192009-03-19 14:10:50 -07003082 drm_clflush_pages(obj_priv->pages + i, 1);
Eric Anholte47c68e2008-11-14 13:35:19 -08003083 }
Eric Anholte47c68e2008-11-14 13:35:19 -08003084 }
3085
3086 /* Free the page_cpu_valid mappings which are now stale, whether
3087 * or not we've got I915_GEM_DOMAIN_CPU.
3088 */
Eric Anholt9a298b22009-03-24 12:23:04 -07003089 kfree(obj_priv->page_cpu_valid);
Eric Anholte47c68e2008-11-14 13:35:19 -08003090 obj_priv->page_cpu_valid = NULL;
3091}
3092
3093/**
3094 * Set the CPU read domain on a range of the object.
3095 *
3096 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3097 * not entirely valid. The page_cpu_valid member of the object flags which
3098 * pages have been flushed, and will be respected by
3099 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3100 * of the whole object.
3101 *
3102 * This function returns when the move is complete, including waiting on
3103 * flushes to occur.
Eric Anholt673a3942008-07-30 12:06:12 -07003104 */
3105static int
Eric Anholte47c68e2008-11-14 13:35:19 -08003106i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3107 uint64_t offset, uint64_t size)
Eric Anholt673a3942008-07-30 12:06:12 -07003108{
3109 struct drm_i915_gem_object *obj_priv = obj->driver_private;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003110 uint32_t old_read_domains;
Eric Anholte47c68e2008-11-14 13:35:19 -08003111 int i, ret;
Eric Anholt673a3942008-07-30 12:06:12 -07003112
Eric Anholte47c68e2008-11-14 13:35:19 -08003113 if (offset == 0 && size == obj->size)
3114 return i915_gem_object_set_to_cpu_domain(obj, 0);
3115
3116 i915_gem_object_flush_gpu_write_domain(obj);
3117 /* Wait on any GPU rendering and flushing to occur. */
3118 ret = i915_gem_object_wait_rendering(obj);
3119 if (ret != 0)
3120 return ret;
3121 i915_gem_object_flush_gtt_write_domain(obj);
3122
3123 /* If we're already fully in the CPU read domain, we're done. */
3124 if (obj_priv->page_cpu_valid == NULL &&
3125 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
Eric Anholt673a3942008-07-30 12:06:12 -07003126 return 0;
3127
Eric Anholte47c68e2008-11-14 13:35:19 -08003128 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3129 * newly adding I915_GEM_DOMAIN_CPU
3130 */
Eric Anholt673a3942008-07-30 12:06:12 -07003131 if (obj_priv->page_cpu_valid == NULL) {
Eric Anholt9a298b22009-03-24 12:23:04 -07003132 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3133 GFP_KERNEL);
Eric Anholte47c68e2008-11-14 13:35:19 -08003134 if (obj_priv->page_cpu_valid == NULL)
3135 return -ENOMEM;
3136 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3137 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
Eric Anholt673a3942008-07-30 12:06:12 -07003138
3139 /* Flush the cache on any pages that are still invalid from the CPU's
3140 * perspective.
3141 */
Eric Anholte47c68e2008-11-14 13:35:19 -08003142 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3143 i++) {
Eric Anholt673a3942008-07-30 12:06:12 -07003144 if (obj_priv->page_cpu_valid[i])
3145 continue;
3146
Eric Anholt856fa192009-03-19 14:10:50 -07003147 drm_clflush_pages(obj_priv->pages + i, 1);
Eric Anholt673a3942008-07-30 12:06:12 -07003148
3149 obj_priv->page_cpu_valid[i] = 1;
3150 }
3151
Eric Anholte47c68e2008-11-14 13:35:19 -08003152 /* It should now be out of any other write domains, and we can update
3153 * the domain values for our changes.
3154 */
3155 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3156
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003157 old_read_domains = obj->read_domains;
Eric Anholte47c68e2008-11-14 13:35:19 -08003158 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3159
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003160 trace_i915_gem_object_change_domain(obj,
3161 old_read_domains,
3162 obj->write_domain);
3163
Eric Anholt673a3942008-07-30 12:06:12 -07003164 return 0;
3165}
3166
3167/**
Eric Anholt673a3942008-07-30 12:06:12 -07003168 * Pin an object to the GTT and evaluate the relocations landing in it.
3169 */
3170static int
3171i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3172 struct drm_file *file_priv,
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003173 struct drm_i915_gem_exec_object *entry,
3174 struct drm_i915_gem_relocation_entry *relocs)
Eric Anholt673a3942008-07-30 12:06:12 -07003175{
3176 struct drm_device *dev = obj->dev;
Keith Packard0839ccb2008-10-30 19:38:48 -07003177 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholt673a3942008-07-30 12:06:12 -07003178 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3179 int i, ret;
Keith Packard0839ccb2008-10-30 19:38:48 -07003180 void __iomem *reloc_page;
Eric Anholt673a3942008-07-30 12:06:12 -07003181
3182 /* Choose the GTT offset for our buffer and put it there. */
3183 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3184 if (ret)
3185 return ret;
3186
3187 entry->offset = obj_priv->gtt_offset;
3188
Eric Anholt673a3942008-07-30 12:06:12 -07003189 /* Apply the relocations, using the GTT aperture to avoid cache
3190 * flushing requirements.
3191 */
3192 for (i = 0; i < entry->relocation_count; i++) {
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003193 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
Eric Anholt673a3942008-07-30 12:06:12 -07003194 struct drm_gem_object *target_obj;
3195 struct drm_i915_gem_object *target_obj_priv;
Eric Anholt3043c602008-10-02 12:24:47 -07003196 uint32_t reloc_val, reloc_offset;
3197 uint32_t __iomem *reloc_entry;
Eric Anholt673a3942008-07-30 12:06:12 -07003198
Eric Anholt673a3942008-07-30 12:06:12 -07003199 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003200 reloc->target_handle);
Eric Anholt673a3942008-07-30 12:06:12 -07003201 if (target_obj == NULL) {
3202 i915_gem_object_unpin(obj);
3203 return -EBADF;
3204 }
3205 target_obj_priv = target_obj->driver_private;
3206
Chris Wilson8542a0b2009-09-09 21:15:15 +01003207#if WATCH_RELOC
3208 DRM_INFO("%s: obj %p offset %08x target %d "
3209 "read %08x write %08x gtt %08x "
3210 "presumed %08x delta %08x\n",
3211 __func__,
3212 obj,
3213 (int) reloc->offset,
3214 (int) reloc->target_handle,
3215 (int) reloc->read_domains,
3216 (int) reloc->write_domain,
3217 (int) target_obj_priv->gtt_offset,
3218 (int) reloc->presumed_offset,
3219 reloc->delta);
3220#endif
3221
Eric Anholt673a3942008-07-30 12:06:12 -07003222 /* The target buffer should have appeared before us in the
3223 * exec_object list, so it should have a GTT space bound by now.
3224 */
3225 if (target_obj_priv->gtt_space == NULL) {
3226 DRM_ERROR("No GTT space found for object %d\n",
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003227 reloc->target_handle);
Eric Anholt673a3942008-07-30 12:06:12 -07003228 drm_gem_object_unreference(target_obj);
3229 i915_gem_object_unpin(obj);
3230 return -EINVAL;
3231 }
3232
Chris Wilson8542a0b2009-09-09 21:15:15 +01003233 /* Validate that the target is in a valid r/w GPU domain */
3234 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3235 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3236 DRM_ERROR("reloc with read/write CPU domains: "
3237 "obj %p target %d offset %d "
3238 "read %08x write %08x",
3239 obj, reloc->target_handle,
3240 (int) reloc->offset,
3241 reloc->read_domains,
3242 reloc->write_domain);
3243 drm_gem_object_unreference(target_obj);
3244 i915_gem_object_unpin(obj);
3245 return -EINVAL;
3246 }
3247 if (reloc->write_domain && target_obj->pending_write_domain &&
3248 reloc->write_domain != target_obj->pending_write_domain) {
3249 DRM_ERROR("Write domain conflict: "
3250 "obj %p target %d offset %d "
3251 "new %08x old %08x\n",
3252 obj, reloc->target_handle,
3253 (int) reloc->offset,
3254 reloc->write_domain,
3255 target_obj->pending_write_domain);
3256 drm_gem_object_unreference(target_obj);
3257 i915_gem_object_unpin(obj);
3258 return -EINVAL;
3259 }
3260
3261 target_obj->pending_read_domains |= reloc->read_domains;
3262 target_obj->pending_write_domain |= reloc->write_domain;
3263
3264 /* If the relocation already has the right value in it, no
3265 * more work needs to be done.
3266 */
3267 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
3268 drm_gem_object_unreference(target_obj);
3269 continue;
3270 }
3271
3272 /* Check that the relocation address is valid... */
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003273 if (reloc->offset > obj->size - 4) {
Eric Anholt673a3942008-07-30 12:06:12 -07003274 DRM_ERROR("Relocation beyond object bounds: "
3275 "obj %p target %d offset %d size %d.\n",
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003276 obj, reloc->target_handle,
3277 (int) reloc->offset, (int) obj->size);
Eric Anholt673a3942008-07-30 12:06:12 -07003278 drm_gem_object_unreference(target_obj);
3279 i915_gem_object_unpin(obj);
3280 return -EINVAL;
3281 }
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003282 if (reloc->offset & 3) {
Eric Anholt673a3942008-07-30 12:06:12 -07003283 DRM_ERROR("Relocation not 4-byte aligned: "
3284 "obj %p target %d offset %d.\n",
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003285 obj, reloc->target_handle,
3286 (int) reloc->offset);
Eric Anholt673a3942008-07-30 12:06:12 -07003287 drm_gem_object_unreference(target_obj);
3288 i915_gem_object_unpin(obj);
3289 return -EINVAL;
3290 }
3291
Chris Wilson8542a0b2009-09-09 21:15:15 +01003292 /* and points to somewhere within the target object. */
Chris Wilsoncd0b9fb2009-09-15 23:23:18 +01003293 if (reloc->delta >= target_obj->size) {
3294 DRM_ERROR("Relocation beyond target object bounds: "
3295 "obj %p target %d delta %d size %d.\n",
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003296 obj, reloc->target_handle,
Chris Wilsoncd0b9fb2009-09-15 23:23:18 +01003297 (int) reloc->delta, (int) target_obj->size);
Chris Wilson491152b2009-02-11 14:26:32 +00003298 drm_gem_object_unreference(target_obj);
3299 i915_gem_object_unpin(obj);
Eric Anholte47c68e2008-11-14 13:35:19 -08003300 return -EINVAL;
3301 }
3302
Eric Anholt2ef7eea2008-11-10 10:53:25 -08003303 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3304 if (ret != 0) {
3305 drm_gem_object_unreference(target_obj);
3306 i915_gem_object_unpin(obj);
3307 return -EINVAL;
Eric Anholt673a3942008-07-30 12:06:12 -07003308 }
3309
3310 /* Map the page containing the relocation we're going to
3311 * perform.
3312 */
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003313 reloc_offset = obj_priv->gtt_offset + reloc->offset;
Keith Packard0839ccb2008-10-30 19:38:48 -07003314 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3315 (reloc_offset &
3316 ~(PAGE_SIZE - 1)));
Eric Anholt3043c602008-10-02 12:24:47 -07003317 reloc_entry = (uint32_t __iomem *)(reloc_page +
Keith Packard0839ccb2008-10-30 19:38:48 -07003318 (reloc_offset & (PAGE_SIZE - 1)));
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003319 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
Eric Anholt673a3942008-07-30 12:06:12 -07003320
3321#if WATCH_BUF
3322 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003323 obj, (unsigned int) reloc->offset,
Eric Anholt673a3942008-07-30 12:06:12 -07003324 readl(reloc_entry), reloc_val);
3325#endif
3326 writel(reloc_val, reloc_entry);
Keith Packard0839ccb2008-10-30 19:38:48 -07003327 io_mapping_unmap_atomic(reloc_page);
Eric Anholt673a3942008-07-30 12:06:12 -07003328
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003329 /* The updated presumed offset for this entry will be
3330 * copied back out to the user.
Eric Anholt673a3942008-07-30 12:06:12 -07003331 */
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003332 reloc->presumed_offset = target_obj_priv->gtt_offset;
Eric Anholt673a3942008-07-30 12:06:12 -07003333
3334 drm_gem_object_unreference(target_obj);
3335 }
3336
Eric Anholt673a3942008-07-30 12:06:12 -07003337#if WATCH_BUF
3338 if (0)
3339 i915_gem_dump_object(obj, 128, __func__, ~0);
3340#endif
3341 return 0;
3342}
3343
3344/** Dispatch a batchbuffer to the ring
3345 */
3346static int
3347i915_dispatch_gem_execbuffer(struct drm_device *dev,
3348 struct drm_i915_gem_execbuffer *exec,
Eric Anholt201361a2009-03-11 12:30:04 -07003349 struct drm_clip_rect *cliprects,
Eric Anholt673a3942008-07-30 12:06:12 -07003350 uint64_t exec_offset)
3351{
3352 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholt673a3942008-07-30 12:06:12 -07003353 int nbox = exec->num_cliprects;
3354 int i = 0, count;
Chris Wilson83d60792009-06-06 09:45:57 +01003355 uint32_t exec_start, exec_len;
Eric Anholt673a3942008-07-30 12:06:12 -07003356 RING_LOCALS;
3357
3358 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3359 exec_len = (uint32_t) exec->batch_len;
3360
Chris Wilson8f0dc5b2009-09-24 00:43:17 +01003361 trace_i915_gem_request_submit(dev, dev_priv->mm.next_gem_seqno + 1);
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003362
Eric Anholt673a3942008-07-30 12:06:12 -07003363 count = nbox ? nbox : 1;
3364
3365 for (i = 0; i < count; i++) {
3366 if (i < nbox) {
Eric Anholt201361a2009-03-11 12:30:04 -07003367 int ret = i915_emit_box(dev, cliprects, i,
Eric Anholt673a3942008-07-30 12:06:12 -07003368 exec->DR1, exec->DR4);
3369 if (ret)
3370 return ret;
3371 }
3372
3373 if (IS_I830(dev) || IS_845G(dev)) {
3374 BEGIN_LP_RING(4);
3375 OUT_RING(MI_BATCH_BUFFER);
3376 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3377 OUT_RING(exec_start + exec_len - 4);
3378 OUT_RING(0);
3379 ADVANCE_LP_RING();
3380 } else {
3381 BEGIN_LP_RING(2);
3382 if (IS_I965G(dev)) {
3383 OUT_RING(MI_BATCH_BUFFER_START |
3384 (2 << 6) |
3385 MI_BATCH_NON_SECURE_I965);
3386 OUT_RING(exec_start);
3387 } else {
3388 OUT_RING(MI_BATCH_BUFFER_START |
3389 (2 << 6));
3390 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3391 }
3392 ADVANCE_LP_RING();
3393 }
3394 }
3395
3396 /* XXX breadcrumb */
3397 return 0;
3398}
3399
3400/* Throttle our rendering by waiting until the ring has completed our requests
3401 * emitted over 20 msec ago.
3402 *
Eric Anholtb9624422009-06-03 07:27:35 +00003403 * Note that if we were to use the current jiffies each time around the loop,
3404 * we wouldn't escape the function with any frames outstanding if the time to
3405 * render a frame was over 20ms.
3406 *
Eric Anholt673a3942008-07-30 12:06:12 -07003407 * This should get us reasonable parallelism between CPU and GPU but also
3408 * relatively low latency when blocking on a particular request to finish.
3409 */
3410static int
3411i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3412{
3413 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3414 int ret = 0;
Eric Anholtb9624422009-06-03 07:27:35 +00003415 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
Eric Anholt673a3942008-07-30 12:06:12 -07003416
3417 mutex_lock(&dev->struct_mutex);
Eric Anholtb9624422009-06-03 07:27:35 +00003418 while (!list_empty(&i915_file_priv->mm.request_list)) {
3419 struct drm_i915_gem_request *request;
3420
3421 request = list_first_entry(&i915_file_priv->mm.request_list,
3422 struct drm_i915_gem_request,
3423 client_list);
3424
3425 if (time_after_eq(request->emitted_jiffies, recent_enough))
3426 break;
3427
3428 ret = i915_wait_request(dev, request->seqno);
3429 if (ret != 0)
3430 break;
3431 }
Eric Anholt673a3942008-07-30 12:06:12 -07003432 mutex_unlock(&dev->struct_mutex);
Eric Anholtb9624422009-06-03 07:27:35 +00003433
Eric Anholt673a3942008-07-30 12:06:12 -07003434 return ret;
3435}
3436
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003437static int
3438i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object *exec_list,
3439 uint32_t buffer_count,
3440 struct drm_i915_gem_relocation_entry **relocs)
3441{
3442 uint32_t reloc_count = 0, reloc_index = 0, i;
3443 int ret;
3444
3445 *relocs = NULL;
3446 for (i = 0; i < buffer_count; i++) {
3447 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3448 return -EINVAL;
3449 reloc_count += exec_list[i].relocation_count;
3450 }
3451
Jesse Barnes8e7d2b22009-05-08 16:13:25 -07003452 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003453 if (*relocs == NULL)
3454 return -ENOMEM;
3455
3456 for (i = 0; i < buffer_count; i++) {
3457 struct drm_i915_gem_relocation_entry __user *user_relocs;
3458
3459 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3460
3461 ret = copy_from_user(&(*relocs)[reloc_index],
3462 user_relocs,
3463 exec_list[i].relocation_count *
3464 sizeof(**relocs));
3465 if (ret != 0) {
Jesse Barnes8e7d2b22009-05-08 16:13:25 -07003466 drm_free_large(*relocs);
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003467 *relocs = NULL;
Florian Mickler2bc43b52009-04-06 22:55:41 +02003468 return -EFAULT;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003469 }
3470
3471 reloc_index += exec_list[i].relocation_count;
3472 }
3473
Florian Mickler2bc43b52009-04-06 22:55:41 +02003474 return 0;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003475}
3476
3477static int
3478i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object *exec_list,
3479 uint32_t buffer_count,
3480 struct drm_i915_gem_relocation_entry *relocs)
3481{
3482 uint32_t reloc_count = 0, i;
Florian Mickler2bc43b52009-04-06 22:55:41 +02003483 int ret = 0;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003484
3485 for (i = 0; i < buffer_count; i++) {
3486 struct drm_i915_gem_relocation_entry __user *user_relocs;
Florian Mickler2bc43b52009-04-06 22:55:41 +02003487 int unwritten;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003488
3489 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3490
Florian Mickler2bc43b52009-04-06 22:55:41 +02003491 unwritten = copy_to_user(user_relocs,
3492 &relocs[reloc_count],
3493 exec_list[i].relocation_count *
3494 sizeof(*relocs));
3495
3496 if (unwritten) {
3497 ret = -EFAULT;
3498 goto err;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003499 }
3500
3501 reloc_count += exec_list[i].relocation_count;
3502 }
3503
Florian Mickler2bc43b52009-04-06 22:55:41 +02003504err:
Jesse Barnes8e7d2b22009-05-08 16:13:25 -07003505 drm_free_large(relocs);
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003506
3507 return ret;
3508}
3509
Chris Wilson83d60792009-06-06 09:45:57 +01003510static int
3511i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer *exec,
3512 uint64_t exec_offset)
3513{
3514 uint32_t exec_start, exec_len;
3515
3516 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3517 exec_len = (uint32_t) exec->batch_len;
3518
3519 if ((exec_start | exec_len) & 0x7)
3520 return -EINVAL;
3521
3522 if (!exec_start)
3523 return -EINVAL;
3524
3525 return 0;
3526}
3527
Eric Anholt673a3942008-07-30 12:06:12 -07003528int
3529i915_gem_execbuffer(struct drm_device *dev, void *data,
3530 struct drm_file *file_priv)
3531{
3532 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholt673a3942008-07-30 12:06:12 -07003533 struct drm_i915_gem_execbuffer *args = data;
3534 struct drm_i915_gem_exec_object *exec_list = NULL;
3535 struct drm_gem_object **object_list = NULL;
3536 struct drm_gem_object *batch_obj;
Kristian Høgsbergb70d11d2009-03-03 14:45:57 -05003537 struct drm_i915_gem_object *obj_priv;
Eric Anholt201361a2009-03-11 12:30:04 -07003538 struct drm_clip_rect *cliprects = NULL;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003539 struct drm_i915_gem_relocation_entry *relocs;
3540 int ret, ret2, i, pinned = 0;
Eric Anholt673a3942008-07-30 12:06:12 -07003541 uint64_t exec_offset;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003542 uint32_t seqno, flush_domains, reloc_index;
Keith Packardac94a962008-11-20 23:30:27 -08003543 int pin_tries;
Eric Anholt673a3942008-07-30 12:06:12 -07003544
3545#if WATCH_EXEC
3546 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3547 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3548#endif
3549
Eric Anholt4f481ed2008-09-10 14:22:49 -07003550 if (args->buffer_count < 1) {
3551 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3552 return -EINVAL;
3553 }
Eric Anholt673a3942008-07-30 12:06:12 -07003554 /* Copy in the exec list from userland */
Jesse Barnes8e7d2b22009-05-08 16:13:25 -07003555 exec_list = drm_calloc_large(sizeof(*exec_list), args->buffer_count);
3556 object_list = drm_calloc_large(sizeof(*object_list), args->buffer_count);
Eric Anholt673a3942008-07-30 12:06:12 -07003557 if (exec_list == NULL || object_list == NULL) {
3558 DRM_ERROR("Failed to allocate exec or object list "
3559 "for %d buffers\n",
3560 args->buffer_count);
3561 ret = -ENOMEM;
3562 goto pre_mutex_err;
3563 }
3564 ret = copy_from_user(exec_list,
3565 (struct drm_i915_relocation_entry __user *)
3566 (uintptr_t) args->buffers_ptr,
3567 sizeof(*exec_list) * args->buffer_count);
3568 if (ret != 0) {
3569 DRM_ERROR("copy %d exec entries failed %d\n",
3570 args->buffer_count, ret);
3571 goto pre_mutex_err;
3572 }
3573
Eric Anholt201361a2009-03-11 12:30:04 -07003574 if (args->num_cliprects != 0) {
Eric Anholt9a298b22009-03-24 12:23:04 -07003575 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3576 GFP_KERNEL);
Eric Anholt201361a2009-03-11 12:30:04 -07003577 if (cliprects == NULL)
3578 goto pre_mutex_err;
3579
3580 ret = copy_from_user(cliprects,
3581 (struct drm_clip_rect __user *)
3582 (uintptr_t) args->cliprects_ptr,
3583 sizeof(*cliprects) * args->num_cliprects);
3584 if (ret != 0) {
3585 DRM_ERROR("copy %d cliprects failed: %d\n",
3586 args->num_cliprects, ret);
3587 goto pre_mutex_err;
3588 }
3589 }
3590
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003591 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3592 &relocs);
3593 if (ret != 0)
3594 goto pre_mutex_err;
3595
Eric Anholt673a3942008-07-30 12:06:12 -07003596 mutex_lock(&dev->struct_mutex);
3597
3598 i915_verify_inactive(dev, __FILE__, __LINE__);
3599
Ben Gamariba1234d2009-09-14 17:48:47 -04003600 if (atomic_read(&dev_priv->mm.wedged)) {
Eric Anholt673a3942008-07-30 12:06:12 -07003601 DRM_ERROR("Execbuf while wedged\n");
3602 mutex_unlock(&dev->struct_mutex);
Chris Wilsona198bc82009-02-06 16:55:20 +00003603 ret = -EIO;
3604 goto pre_mutex_err;
Eric Anholt673a3942008-07-30 12:06:12 -07003605 }
3606
3607 if (dev_priv->mm.suspended) {
3608 DRM_ERROR("Execbuf while VT-switched.\n");
3609 mutex_unlock(&dev->struct_mutex);
Chris Wilsona198bc82009-02-06 16:55:20 +00003610 ret = -EBUSY;
3611 goto pre_mutex_err;
Eric Anholt673a3942008-07-30 12:06:12 -07003612 }
3613
Keith Packardac94a962008-11-20 23:30:27 -08003614 /* Look up object handles */
Eric Anholt673a3942008-07-30 12:06:12 -07003615 for (i = 0; i < args->buffer_count; i++) {
3616 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3617 exec_list[i].handle);
3618 if (object_list[i] == NULL) {
3619 DRM_ERROR("Invalid object handle %d at index %d\n",
3620 exec_list[i].handle, i);
3621 ret = -EBADF;
3622 goto err;
3623 }
Kristian Høgsbergb70d11d2009-03-03 14:45:57 -05003624
3625 obj_priv = object_list[i]->driver_private;
3626 if (obj_priv->in_execbuffer) {
3627 DRM_ERROR("Object %p appears more than once in object list\n",
3628 object_list[i]);
3629 ret = -EBADF;
3630 goto err;
3631 }
3632 obj_priv->in_execbuffer = true;
Keith Packardac94a962008-11-20 23:30:27 -08003633 }
Eric Anholt673a3942008-07-30 12:06:12 -07003634
Keith Packardac94a962008-11-20 23:30:27 -08003635 /* Pin and relocate */
3636 for (pin_tries = 0; ; pin_tries++) {
3637 ret = 0;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003638 reloc_index = 0;
3639
Keith Packardac94a962008-11-20 23:30:27 -08003640 for (i = 0; i < args->buffer_count; i++) {
3641 object_list[i]->pending_read_domains = 0;
3642 object_list[i]->pending_write_domain = 0;
3643 ret = i915_gem_object_pin_and_relocate(object_list[i],
3644 file_priv,
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003645 &exec_list[i],
3646 &relocs[reloc_index]);
Keith Packardac94a962008-11-20 23:30:27 -08003647 if (ret)
3648 break;
3649 pinned = i + 1;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003650 reloc_index += exec_list[i].relocation_count;
Keith Packardac94a962008-11-20 23:30:27 -08003651 }
3652 /* success */
3653 if (ret == 0)
3654 break;
3655
3656 /* error other than GTT full, or we've already tried again */
Chris Wilson2939e1f2009-06-06 09:46:03 +01003657 if (ret != -ENOSPC || pin_tries >= 1) {
Chris Wilson07f73f62009-09-14 16:50:30 +01003658 if (ret != -ERESTARTSYS) {
3659 unsigned long long total_size = 0;
3660 for (i = 0; i < args->buffer_count; i++)
3661 total_size += object_list[i]->size;
3662 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n",
3663 pinned+1, args->buffer_count,
3664 total_size, ret);
3665 DRM_ERROR("%d objects [%d pinned], "
3666 "%d object bytes [%d pinned], "
3667 "%d/%d gtt bytes\n",
3668 atomic_read(&dev->object_count),
3669 atomic_read(&dev->pin_count),
3670 atomic_read(&dev->object_memory),
3671 atomic_read(&dev->pin_memory),
3672 atomic_read(&dev->gtt_memory),
3673 dev->gtt_total);
3674 }
Eric Anholt673a3942008-07-30 12:06:12 -07003675 goto err;
3676 }
Keith Packardac94a962008-11-20 23:30:27 -08003677
3678 /* unpin all of our buffers */
3679 for (i = 0; i < pinned; i++)
3680 i915_gem_object_unpin(object_list[i]);
Eric Anholtb1177632008-12-10 10:09:41 -08003681 pinned = 0;
Keith Packardac94a962008-11-20 23:30:27 -08003682
3683 /* evict everyone we can from the aperture */
3684 ret = i915_gem_evict_everything(dev);
Chris Wilson07f73f62009-09-14 16:50:30 +01003685 if (ret && ret != -ENOSPC)
Keith Packardac94a962008-11-20 23:30:27 -08003686 goto err;
Eric Anholt673a3942008-07-30 12:06:12 -07003687 }
3688
3689 /* Set the pending read domains for the batch buffer to COMMAND */
3690 batch_obj = object_list[args->buffer_count-1];
Chris Wilson5f26a2c2009-06-06 09:45:58 +01003691 if (batch_obj->pending_write_domain) {
3692 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3693 ret = -EINVAL;
3694 goto err;
3695 }
3696 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
Eric Anholt673a3942008-07-30 12:06:12 -07003697
Chris Wilson83d60792009-06-06 09:45:57 +01003698 /* Sanity check the batch buffer, prior to moving objects */
3699 exec_offset = exec_list[args->buffer_count - 1].offset;
3700 ret = i915_gem_check_execbuffer (args, exec_offset);
3701 if (ret != 0) {
3702 DRM_ERROR("execbuf with invalid offset/length\n");
3703 goto err;
3704 }
3705
Eric Anholt673a3942008-07-30 12:06:12 -07003706 i915_verify_inactive(dev, __FILE__, __LINE__);
3707
Keith Packard646f0f62008-11-20 23:23:03 -08003708 /* Zero the global flush/invalidate flags. These
3709 * will be modified as new domains are computed
3710 * for each object
3711 */
3712 dev->invalidate_domains = 0;
3713 dev->flush_domains = 0;
3714
Eric Anholt673a3942008-07-30 12:06:12 -07003715 for (i = 0; i < args->buffer_count; i++) {
3716 struct drm_gem_object *obj = object_list[i];
Eric Anholt673a3942008-07-30 12:06:12 -07003717
Keith Packard646f0f62008-11-20 23:23:03 -08003718 /* Compute new gpu domains and update invalidate/flush */
Eric Anholt8b0e3782009-02-19 14:40:50 -08003719 i915_gem_object_set_to_gpu_domain(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07003720 }
3721
3722 i915_verify_inactive(dev, __FILE__, __LINE__);
3723
Keith Packard646f0f62008-11-20 23:23:03 -08003724 if (dev->invalidate_domains | dev->flush_domains) {
3725#if WATCH_EXEC
3726 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3727 __func__,
3728 dev->invalidate_domains,
3729 dev->flush_domains);
3730#endif
3731 i915_gem_flush(dev,
3732 dev->invalidate_domains,
3733 dev->flush_domains);
3734 if (dev->flush_domains)
Eric Anholtb9624422009-06-03 07:27:35 +00003735 (void)i915_add_request(dev, file_priv,
3736 dev->flush_domains);
Keith Packard646f0f62008-11-20 23:23:03 -08003737 }
Eric Anholt673a3942008-07-30 12:06:12 -07003738
Eric Anholtefbeed92009-02-19 14:54:51 -08003739 for (i = 0; i < args->buffer_count; i++) {
3740 struct drm_gem_object *obj = object_list[i];
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003741 uint32_t old_write_domain = obj->write_domain;
Eric Anholtefbeed92009-02-19 14:54:51 -08003742
3743 obj->write_domain = obj->pending_write_domain;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003744 trace_i915_gem_object_change_domain(obj,
3745 obj->read_domains,
3746 old_write_domain);
Eric Anholtefbeed92009-02-19 14:54:51 -08003747 }
3748
Eric Anholt673a3942008-07-30 12:06:12 -07003749 i915_verify_inactive(dev, __FILE__, __LINE__);
3750
3751#if WATCH_COHERENCY
3752 for (i = 0; i < args->buffer_count; i++) {
3753 i915_gem_object_check_coherency(object_list[i],
3754 exec_list[i].handle);
3755 }
3756#endif
3757
Eric Anholt673a3942008-07-30 12:06:12 -07003758#if WATCH_EXEC
Ben Gamari6911a9b2009-04-02 11:24:54 -07003759 i915_gem_dump_object(batch_obj,
Eric Anholt673a3942008-07-30 12:06:12 -07003760 args->batch_len,
3761 __func__,
3762 ~0);
3763#endif
3764
Eric Anholt673a3942008-07-30 12:06:12 -07003765 /* Exec the batchbuffer */
Eric Anholt201361a2009-03-11 12:30:04 -07003766 ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset);
Eric Anholt673a3942008-07-30 12:06:12 -07003767 if (ret) {
3768 DRM_ERROR("dispatch failed %d\n", ret);
3769 goto err;
3770 }
3771
3772 /*
3773 * Ensure that the commands in the batch buffer are
3774 * finished before the interrupt fires
3775 */
3776 flush_domains = i915_retire_commands(dev);
3777
3778 i915_verify_inactive(dev, __FILE__, __LINE__);
3779
3780 /*
3781 * Get a seqno representing the execution of the current buffer,
3782 * which we can wait on. We would like to mitigate these interrupts,
3783 * likely by only creating seqnos occasionally (so that we have
3784 * *some* interrupts representing completion of buffers that we can
3785 * wait on when trying to clear up gtt space).
3786 */
Eric Anholtb9624422009-06-03 07:27:35 +00003787 seqno = i915_add_request(dev, file_priv, flush_domains);
Eric Anholt673a3942008-07-30 12:06:12 -07003788 BUG_ON(seqno == 0);
Eric Anholt673a3942008-07-30 12:06:12 -07003789 for (i = 0; i < args->buffer_count; i++) {
3790 struct drm_gem_object *obj = object_list[i];
Eric Anholt673a3942008-07-30 12:06:12 -07003791
Eric Anholtce44b0e2008-11-06 16:00:31 -08003792 i915_gem_object_move_to_active(obj, seqno);
Eric Anholt673a3942008-07-30 12:06:12 -07003793#if WATCH_LRU
3794 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3795#endif
3796 }
3797#if WATCH_LRU
3798 i915_dump_lru(dev, __func__);
3799#endif
3800
3801 i915_verify_inactive(dev, __FILE__, __LINE__);
3802
Eric Anholt673a3942008-07-30 12:06:12 -07003803err:
Julia Lawallaad87df2008-12-21 16:28:47 +01003804 for (i = 0; i < pinned; i++)
3805 i915_gem_object_unpin(object_list[i]);
Eric Anholt673a3942008-07-30 12:06:12 -07003806
Kristian Høgsbergb70d11d2009-03-03 14:45:57 -05003807 for (i = 0; i < args->buffer_count; i++) {
3808 if (object_list[i]) {
3809 obj_priv = object_list[i]->driver_private;
3810 obj_priv->in_execbuffer = false;
3811 }
Julia Lawallaad87df2008-12-21 16:28:47 +01003812 drm_gem_object_unreference(object_list[i]);
Kristian Høgsbergb70d11d2009-03-03 14:45:57 -05003813 }
Julia Lawallaad87df2008-12-21 16:28:47 +01003814
Eric Anholt673a3942008-07-30 12:06:12 -07003815 mutex_unlock(&dev->struct_mutex);
3816
Roland Dreiera35f2e22009-02-06 17:48:09 -08003817 if (!ret) {
3818 /* Copy the new buffer offsets back to the user's exec list. */
3819 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3820 (uintptr_t) args->buffers_ptr,
3821 exec_list,
3822 sizeof(*exec_list) * args->buffer_count);
Florian Mickler2bc43b52009-04-06 22:55:41 +02003823 if (ret) {
3824 ret = -EFAULT;
Roland Dreiera35f2e22009-02-06 17:48:09 -08003825 DRM_ERROR("failed to copy %d exec entries "
3826 "back to user (%d)\n",
3827 args->buffer_count, ret);
Florian Mickler2bc43b52009-04-06 22:55:41 +02003828 }
Roland Dreiera35f2e22009-02-06 17:48:09 -08003829 }
3830
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003831 /* Copy the updated relocations out regardless of current error
3832 * state. Failure to update the relocs would mean that the next
3833 * time userland calls execbuf, it would do so with presumed offset
3834 * state that didn't match the actual object state.
3835 */
3836 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3837 relocs);
3838 if (ret2 != 0) {
3839 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3840
3841 if (ret == 0)
3842 ret = ret2;
3843 }
3844
Eric Anholt673a3942008-07-30 12:06:12 -07003845pre_mutex_err:
Jesse Barnes8e7d2b22009-05-08 16:13:25 -07003846 drm_free_large(object_list);
3847 drm_free_large(exec_list);
Eric Anholt9a298b22009-03-24 12:23:04 -07003848 kfree(cliprects);
Eric Anholt673a3942008-07-30 12:06:12 -07003849
3850 return ret;
3851}
3852
3853int
3854i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
3855{
3856 struct drm_device *dev = obj->dev;
3857 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3858 int ret;
3859
3860 i915_verify_inactive(dev, __FILE__, __LINE__);
3861 if (obj_priv->gtt_space == NULL) {
3862 ret = i915_gem_object_bind_to_gtt(obj, alignment);
Chris Wilson97311292009-09-21 00:22:34 +01003863 if (ret)
Eric Anholt673a3942008-07-30 12:06:12 -07003864 return ret;
Chris Wilson22c344e2009-02-11 14:26:45 +00003865 }
3866 /*
3867 * Pre-965 chips need a fence register set up in order to
3868 * properly handle tiled surfaces.
3869 */
Eric Anholta09ba7f2009-08-29 12:49:51 -07003870 if (!IS_I965G(dev) && obj_priv->tiling_mode != I915_TILING_NONE) {
Chris Wilson8c4b8c32009-06-17 22:08:52 +01003871 ret = i915_gem_object_get_fence_reg(obj);
Chris Wilson22c344e2009-02-11 14:26:45 +00003872 if (ret != 0) {
3873 if (ret != -EBUSY && ret != -ERESTARTSYS)
3874 DRM_ERROR("Failure to install fence: %d\n",
3875 ret);
3876 return ret;
3877 }
Eric Anholt673a3942008-07-30 12:06:12 -07003878 }
3879 obj_priv->pin_count++;
3880
3881 /* If the object is not active and not pending a flush,
3882 * remove it from the inactive list
3883 */
3884 if (obj_priv->pin_count == 1) {
3885 atomic_inc(&dev->pin_count);
3886 atomic_add(obj->size, &dev->pin_memory);
3887 if (!obj_priv->active &&
Chris Wilson21d509e2009-06-06 09:46:02 +01003888 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
Eric Anholt673a3942008-07-30 12:06:12 -07003889 !list_empty(&obj_priv->list))
3890 list_del_init(&obj_priv->list);
3891 }
3892 i915_verify_inactive(dev, __FILE__, __LINE__);
3893
3894 return 0;
3895}
3896
3897void
3898i915_gem_object_unpin(struct drm_gem_object *obj)
3899{
3900 struct drm_device *dev = obj->dev;
3901 drm_i915_private_t *dev_priv = dev->dev_private;
3902 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3903
3904 i915_verify_inactive(dev, __FILE__, __LINE__);
3905 obj_priv->pin_count--;
3906 BUG_ON(obj_priv->pin_count < 0);
3907 BUG_ON(obj_priv->gtt_space == NULL);
3908
3909 /* If the object is no longer pinned, and is
3910 * neither active nor being flushed, then stick it on
3911 * the inactive list
3912 */
3913 if (obj_priv->pin_count == 0) {
3914 if (!obj_priv->active &&
Chris Wilson21d509e2009-06-06 09:46:02 +01003915 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
Eric Anholt673a3942008-07-30 12:06:12 -07003916 list_move_tail(&obj_priv->list,
3917 &dev_priv->mm.inactive_list);
3918 atomic_dec(&dev->pin_count);
3919 atomic_sub(obj->size, &dev->pin_memory);
3920 }
3921 i915_verify_inactive(dev, __FILE__, __LINE__);
3922}
3923
3924int
3925i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3926 struct drm_file *file_priv)
3927{
3928 struct drm_i915_gem_pin *args = data;
3929 struct drm_gem_object *obj;
3930 struct drm_i915_gem_object *obj_priv;
3931 int ret;
3932
3933 mutex_lock(&dev->struct_mutex);
3934
3935 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3936 if (obj == NULL) {
3937 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
3938 args->handle);
3939 mutex_unlock(&dev->struct_mutex);
3940 return -EBADF;
3941 }
3942 obj_priv = obj->driver_private;
3943
Chris Wilsonbb6baf72009-09-22 14:24:13 +01003944 if (obj_priv->madv != I915_MADV_WILLNEED) {
3945 DRM_ERROR("Attempting to pin a purgeable buffer\n");
Chris Wilson3ef94da2009-09-14 16:50:29 +01003946 drm_gem_object_unreference(obj);
3947 mutex_unlock(&dev->struct_mutex);
3948 return -EINVAL;
3949 }
3950
Jesse Barnes79e53942008-11-07 14:24:08 -08003951 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
3952 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3953 args->handle);
Chris Wilson96dec612009-02-08 19:08:04 +00003954 drm_gem_object_unreference(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07003955 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08003956 return -EINVAL;
3957 }
3958
3959 obj_priv->user_pin_count++;
3960 obj_priv->pin_filp = file_priv;
3961 if (obj_priv->user_pin_count == 1) {
3962 ret = i915_gem_object_pin(obj, args->alignment);
3963 if (ret != 0) {
3964 drm_gem_object_unreference(obj);
3965 mutex_unlock(&dev->struct_mutex);
3966 return ret;
3967 }
Eric Anholt673a3942008-07-30 12:06:12 -07003968 }
3969
3970 /* XXX - flush the CPU caches for pinned objects
3971 * as the X server doesn't manage domains yet
3972 */
Eric Anholte47c68e2008-11-14 13:35:19 -08003973 i915_gem_object_flush_cpu_write_domain(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07003974 args->offset = obj_priv->gtt_offset;
3975 drm_gem_object_unreference(obj);
3976 mutex_unlock(&dev->struct_mutex);
3977
3978 return 0;
3979}
3980
3981int
3982i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3983 struct drm_file *file_priv)
3984{
3985 struct drm_i915_gem_pin *args = data;
3986 struct drm_gem_object *obj;
Jesse Barnes79e53942008-11-07 14:24:08 -08003987 struct drm_i915_gem_object *obj_priv;
Eric Anholt673a3942008-07-30 12:06:12 -07003988
3989 mutex_lock(&dev->struct_mutex);
3990
3991 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3992 if (obj == NULL) {
3993 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
3994 args->handle);
3995 mutex_unlock(&dev->struct_mutex);
3996 return -EBADF;
3997 }
3998
Jesse Barnes79e53942008-11-07 14:24:08 -08003999 obj_priv = obj->driver_private;
4000 if (obj_priv->pin_filp != file_priv) {
4001 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4002 args->handle);
4003 drm_gem_object_unreference(obj);
4004 mutex_unlock(&dev->struct_mutex);
4005 return -EINVAL;
4006 }
4007 obj_priv->user_pin_count--;
4008 if (obj_priv->user_pin_count == 0) {
4009 obj_priv->pin_filp = NULL;
4010 i915_gem_object_unpin(obj);
4011 }
Eric Anholt673a3942008-07-30 12:06:12 -07004012
4013 drm_gem_object_unreference(obj);
4014 mutex_unlock(&dev->struct_mutex);
4015 return 0;
4016}
4017
4018int
4019i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4020 struct drm_file *file_priv)
4021{
4022 struct drm_i915_gem_busy *args = data;
4023 struct drm_gem_object *obj;
4024 struct drm_i915_gem_object *obj_priv;
4025
Eric Anholt673a3942008-07-30 12:06:12 -07004026 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4027 if (obj == NULL) {
4028 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4029 args->handle);
Eric Anholt673a3942008-07-30 12:06:12 -07004030 return -EBADF;
4031 }
4032
Chris Wilsonb1ce7862009-06-06 09:46:00 +01004033 mutex_lock(&dev->struct_mutex);
Eric Anholtf21289b2009-02-18 09:44:56 -08004034 /* Update the active list for the hardware's current position.
4035 * Otherwise this only updates on a delayed timer or when irqs are
4036 * actually unmasked, and our working set ends up being larger than
4037 * required.
4038 */
4039 i915_gem_retire_requests(dev);
4040
Eric Anholt673a3942008-07-30 12:06:12 -07004041 obj_priv = obj->driver_private;
Eric Anholtc4de0a52008-12-14 19:05:04 -08004042 /* Don't count being on the flushing list against the object being
4043 * done. Otherwise, a buffer left on the flushing list but not getting
4044 * flushed (because nobody's flushing that domain) won't ever return
4045 * unbusy and get reused by libdrm's bo cache. The other expected
4046 * consumer of this interface, OpenGL's occlusion queries, also specs
4047 * that the objects get unbusy "eventually" without any interference.
4048 */
4049 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
Eric Anholt673a3942008-07-30 12:06:12 -07004050
4051 drm_gem_object_unreference(obj);
4052 mutex_unlock(&dev->struct_mutex);
4053 return 0;
4054}
4055
4056int
4057i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4058 struct drm_file *file_priv)
4059{
4060 return i915_gem_ring_throttle(dev, file_priv);
4061}
4062
Chris Wilson3ef94da2009-09-14 16:50:29 +01004063int
4064i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4065 struct drm_file *file_priv)
4066{
4067 struct drm_i915_gem_madvise *args = data;
4068 struct drm_gem_object *obj;
4069 struct drm_i915_gem_object *obj_priv;
4070
4071 switch (args->madv) {
4072 case I915_MADV_DONTNEED:
4073 case I915_MADV_WILLNEED:
4074 break;
4075 default:
4076 return -EINVAL;
4077 }
4078
4079 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4080 if (obj == NULL) {
4081 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4082 args->handle);
4083 return -EBADF;
4084 }
4085
4086 mutex_lock(&dev->struct_mutex);
4087 obj_priv = obj->driver_private;
4088
4089 if (obj_priv->pin_count) {
4090 drm_gem_object_unreference(obj);
4091 mutex_unlock(&dev->struct_mutex);
4092
4093 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4094 return -EINVAL;
4095 }
4096
Chris Wilsonbb6baf72009-09-22 14:24:13 +01004097 if (obj_priv->madv != __I915_MADV_PURGED)
4098 obj_priv->madv = args->madv;
Chris Wilson3ef94da2009-09-14 16:50:29 +01004099
Chris Wilson2d7ef392009-09-20 23:13:10 +01004100 /* if the object is no longer bound, discard its backing storage */
4101 if (i915_gem_object_is_purgeable(obj_priv) &&
4102 obj_priv->gtt_space == NULL)
4103 i915_gem_object_truncate(obj);
4104
Chris Wilsonbb6baf72009-09-22 14:24:13 +01004105 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4106
Chris Wilson3ef94da2009-09-14 16:50:29 +01004107 drm_gem_object_unreference(obj);
4108 mutex_unlock(&dev->struct_mutex);
4109
4110 return 0;
4111}
4112
Eric Anholt673a3942008-07-30 12:06:12 -07004113int i915_gem_init_object(struct drm_gem_object *obj)
4114{
4115 struct drm_i915_gem_object *obj_priv;
4116
Eric Anholt9a298b22009-03-24 12:23:04 -07004117 obj_priv = kzalloc(sizeof(*obj_priv), GFP_KERNEL);
Eric Anholt673a3942008-07-30 12:06:12 -07004118 if (obj_priv == NULL)
4119 return -ENOMEM;
4120
4121 /*
4122 * We've just allocated pages from the kernel,
4123 * so they've just been written by the CPU with
4124 * zeros. They'll need to be clflushed before we
4125 * use them with the GPU.
4126 */
4127 obj->write_domain = I915_GEM_DOMAIN_CPU;
4128 obj->read_domains = I915_GEM_DOMAIN_CPU;
4129
Keith Packardba1eb1d2008-10-14 19:55:10 -07004130 obj_priv->agp_type = AGP_USER_MEMORY;
4131
Eric Anholt673a3942008-07-30 12:06:12 -07004132 obj->driver_private = obj_priv;
4133 obj_priv->obj = obj;
Jesse Barnesde151cf2008-11-12 10:03:55 -08004134 obj_priv->fence_reg = I915_FENCE_REG_NONE;
Eric Anholt673a3942008-07-30 12:06:12 -07004135 INIT_LIST_HEAD(&obj_priv->list);
Eric Anholta09ba7f2009-08-29 12:49:51 -07004136 INIT_LIST_HEAD(&obj_priv->fence_list);
Chris Wilson3ef94da2009-09-14 16:50:29 +01004137 obj_priv->madv = I915_MADV_WILLNEED;
Jesse Barnesde151cf2008-11-12 10:03:55 -08004138
Chris Wilson1c5d22f2009-08-25 11:15:50 +01004139 trace_i915_gem_object_create(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07004140
4141 return 0;
4142}
4143
4144void i915_gem_free_object(struct drm_gem_object *obj)
4145{
Jesse Barnesde151cf2008-11-12 10:03:55 -08004146 struct drm_device *dev = obj->dev;
Eric Anholt673a3942008-07-30 12:06:12 -07004147 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4148
Chris Wilson1c5d22f2009-08-25 11:15:50 +01004149 trace_i915_gem_object_destroy(obj);
4150
Eric Anholt673a3942008-07-30 12:06:12 -07004151 while (obj_priv->pin_count > 0)
4152 i915_gem_object_unpin(obj);
4153
Dave Airlie71acb5e2008-12-30 20:31:46 +10004154 if (obj_priv->phys_obj)
4155 i915_gem_detach_phys_object(dev, obj);
4156
Eric Anholt673a3942008-07-30 12:06:12 -07004157 i915_gem_object_unbind(obj);
4158
Chris Wilson7e616152009-09-10 08:53:04 +01004159 if (obj_priv->mmap_offset)
4160 i915_gem_free_mmap_offset(obj);
Jesse Barnesde151cf2008-11-12 10:03:55 -08004161
Eric Anholt9a298b22009-03-24 12:23:04 -07004162 kfree(obj_priv->page_cpu_valid);
Eric Anholt280b7132009-03-12 16:56:27 -07004163 kfree(obj_priv->bit_17);
Eric Anholt9a298b22009-03-24 12:23:04 -07004164 kfree(obj->driver_private);
Eric Anholt673a3942008-07-30 12:06:12 -07004165}
4166
Chris Wilsonab5ee572009-09-20 19:25:47 +01004167/** Unbinds all inactive objects. */
Eric Anholt673a3942008-07-30 12:06:12 -07004168static int
Chris Wilsonab5ee572009-09-20 19:25:47 +01004169i915_gem_evict_from_inactive_list(struct drm_device *dev)
Eric Anholt673a3942008-07-30 12:06:12 -07004170{
Chris Wilsonab5ee572009-09-20 19:25:47 +01004171 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholt673a3942008-07-30 12:06:12 -07004172
Chris Wilsonab5ee572009-09-20 19:25:47 +01004173 while (!list_empty(&dev_priv->mm.inactive_list)) {
4174 struct drm_gem_object *obj;
4175 int ret;
Eric Anholt673a3942008-07-30 12:06:12 -07004176
Chris Wilsonab5ee572009-09-20 19:25:47 +01004177 obj = list_first_entry(&dev_priv->mm.inactive_list,
4178 struct drm_i915_gem_object,
4179 list)->obj;
Eric Anholt673a3942008-07-30 12:06:12 -07004180
4181 ret = i915_gem_object_unbind(obj);
4182 if (ret != 0) {
Chris Wilsonab5ee572009-09-20 19:25:47 +01004183 DRM_ERROR("Error unbinding object: %d\n", ret);
Eric Anholt673a3942008-07-30 12:06:12 -07004184 return ret;
4185 }
4186 }
4187
Eric Anholt673a3942008-07-30 12:06:12 -07004188 return 0;
4189}
4190
Jesse Barnes5669fca2009-02-17 15:13:31 -08004191int
Eric Anholt673a3942008-07-30 12:06:12 -07004192i915_gem_idle(struct drm_device *dev)
4193{
4194 drm_i915_private_t *dev_priv = dev->dev_private;
4195 uint32_t seqno, cur_seqno, last_seqno;
4196 int stuck, ret;
4197
Keith Packard6dbe2772008-10-14 21:41:13 -07004198 mutex_lock(&dev->struct_mutex);
4199
4200 if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
4201 mutex_unlock(&dev->struct_mutex);
Eric Anholt673a3942008-07-30 12:06:12 -07004202 return 0;
Keith Packard6dbe2772008-10-14 21:41:13 -07004203 }
Eric Anholt673a3942008-07-30 12:06:12 -07004204
4205 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4206 * We need to replace this with a semaphore, or something.
4207 */
4208 dev_priv->mm.suspended = 1;
Ben Gamarif65d9422009-09-14 17:48:44 -04004209 del_timer(&dev_priv->hangcheck_timer);
Eric Anholt673a3942008-07-30 12:06:12 -07004210
Keith Packard6dbe2772008-10-14 21:41:13 -07004211 /* Cancel the retire work handler, wait for it to finish if running
4212 */
4213 mutex_unlock(&dev->struct_mutex);
4214 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4215 mutex_lock(&dev->struct_mutex);
4216
Eric Anholt673a3942008-07-30 12:06:12 -07004217 i915_kernel_lost_context(dev);
4218
4219 /* Flush the GPU along with all non-CPU write domains
4220 */
Chris Wilson21d509e2009-06-06 09:46:02 +01004221 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
4222 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
Eric Anholt673a3942008-07-30 12:06:12 -07004223
4224 if (seqno == 0) {
4225 mutex_unlock(&dev->struct_mutex);
4226 return -ENOMEM;
4227 }
4228
4229 dev_priv->mm.waiting_gem_seqno = seqno;
4230 last_seqno = 0;
4231 stuck = 0;
4232 for (;;) {
4233 cur_seqno = i915_get_gem_seqno(dev);
4234 if (i915_seqno_passed(cur_seqno, seqno))
4235 break;
4236 if (last_seqno == cur_seqno) {
4237 if (stuck++ > 100) {
4238 DRM_ERROR("hardware wedged\n");
Ben Gamariba1234d2009-09-14 17:48:47 -04004239 atomic_set(&dev_priv->mm.wedged, 1);
Eric Anholt673a3942008-07-30 12:06:12 -07004240 DRM_WAKEUP(&dev_priv->irq_queue);
4241 break;
4242 }
4243 }
4244 msleep(10);
4245 last_seqno = cur_seqno;
4246 }
4247 dev_priv->mm.waiting_gem_seqno = 0;
4248
4249 i915_gem_retire_requests(dev);
4250
Carl Worth5e118f42009-03-20 11:54:25 -07004251 spin_lock(&dev_priv->mm.active_list_lock);
Ben Gamariba1234d2009-09-14 17:48:47 -04004252 if (!atomic_read(&dev_priv->mm.wedged)) {
Eric Anholt28dfe522008-11-13 15:00:55 -08004253 /* Active and flushing should now be empty as we've
4254 * waited for a sequence higher than any pending execbuffer
4255 */
4256 WARN_ON(!list_empty(&dev_priv->mm.active_list));
4257 WARN_ON(!list_empty(&dev_priv->mm.flushing_list));
4258 /* Request should now be empty as we've also waited
4259 * for the last request in the list
4260 */
4261 WARN_ON(!list_empty(&dev_priv->mm.request_list));
4262 }
Eric Anholt673a3942008-07-30 12:06:12 -07004263
Eric Anholt28dfe522008-11-13 15:00:55 -08004264 /* Empty the active and flushing lists to inactive. If there's
4265 * anything left at this point, it means that we're wedged and
4266 * nothing good's going to happen by leaving them there. So strip
4267 * the GPU domains and just stuff them onto inactive.
Eric Anholt673a3942008-07-30 12:06:12 -07004268 */
Eric Anholt28dfe522008-11-13 15:00:55 -08004269 while (!list_empty(&dev_priv->mm.active_list)) {
Chris Wilson1c5d22f2009-08-25 11:15:50 +01004270 struct drm_gem_object *obj;
4271 uint32_t old_write_domain;
Eric Anholt673a3942008-07-30 12:06:12 -07004272
Chris Wilson1c5d22f2009-08-25 11:15:50 +01004273 obj = list_first_entry(&dev_priv->mm.active_list,
4274 struct drm_i915_gem_object,
4275 list)->obj;
4276 old_write_domain = obj->write_domain;
4277 obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
4278 i915_gem_object_move_to_inactive(obj);
4279
4280 trace_i915_gem_object_change_domain(obj,
4281 obj->read_domains,
4282 old_write_domain);
Eric Anholt28dfe522008-11-13 15:00:55 -08004283 }
Carl Worth5e118f42009-03-20 11:54:25 -07004284 spin_unlock(&dev_priv->mm.active_list_lock);
Eric Anholt28dfe522008-11-13 15:00:55 -08004285
4286 while (!list_empty(&dev_priv->mm.flushing_list)) {
Chris Wilson1c5d22f2009-08-25 11:15:50 +01004287 struct drm_gem_object *obj;
4288 uint32_t old_write_domain;
Eric Anholt28dfe522008-11-13 15:00:55 -08004289
Chris Wilson1c5d22f2009-08-25 11:15:50 +01004290 obj = list_first_entry(&dev_priv->mm.flushing_list,
4291 struct drm_i915_gem_object,
4292 list)->obj;
4293 old_write_domain = obj->write_domain;
4294 obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
4295 i915_gem_object_move_to_inactive(obj);
4296
4297 trace_i915_gem_object_change_domain(obj,
4298 obj->read_domains,
4299 old_write_domain);
Eric Anholt28dfe522008-11-13 15:00:55 -08004300 }
4301
4302
4303 /* Move all inactive buffers out of the GTT. */
Chris Wilsonab5ee572009-09-20 19:25:47 +01004304 ret = i915_gem_evict_from_inactive_list(dev);
Eric Anholt28dfe522008-11-13 15:00:55 -08004305 WARN_ON(!list_empty(&dev_priv->mm.inactive_list));
Keith Packard6dbe2772008-10-14 21:41:13 -07004306 if (ret) {
4307 mutex_unlock(&dev->struct_mutex);
Eric Anholt673a3942008-07-30 12:06:12 -07004308 return ret;
Keith Packard6dbe2772008-10-14 21:41:13 -07004309 }
Eric Anholt673a3942008-07-30 12:06:12 -07004310
Keith Packard6dbe2772008-10-14 21:41:13 -07004311 i915_gem_cleanup_ringbuffer(dev);
4312 mutex_unlock(&dev->struct_mutex);
4313
Eric Anholt673a3942008-07-30 12:06:12 -07004314 return 0;
4315}
4316
4317static int
4318i915_gem_init_hws(struct drm_device *dev)
4319{
4320 drm_i915_private_t *dev_priv = dev->dev_private;
4321 struct drm_gem_object *obj;
4322 struct drm_i915_gem_object *obj_priv;
4323 int ret;
4324
4325 /* If we need a physical address for the status page, it's already
4326 * initialized at driver load time.
4327 */
4328 if (!I915_NEED_GFX_HWS(dev))
4329 return 0;
4330
4331 obj = drm_gem_object_alloc(dev, 4096);
4332 if (obj == NULL) {
4333 DRM_ERROR("Failed to allocate status page\n");
4334 return -ENOMEM;
4335 }
4336 obj_priv = obj->driver_private;
Keith Packardba1eb1d2008-10-14 19:55:10 -07004337 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
Eric Anholt673a3942008-07-30 12:06:12 -07004338
4339 ret = i915_gem_object_pin(obj, 4096);
4340 if (ret != 0) {
4341 drm_gem_object_unreference(obj);
4342 return ret;
4343 }
4344
4345 dev_priv->status_gfx_addr = obj_priv->gtt_offset;
Eric Anholt673a3942008-07-30 12:06:12 -07004346
Eric Anholt856fa192009-03-19 14:10:50 -07004347 dev_priv->hw_status_page = kmap(obj_priv->pages[0]);
Keith Packardba1eb1d2008-10-14 19:55:10 -07004348 if (dev_priv->hw_status_page == NULL) {
Eric Anholt673a3942008-07-30 12:06:12 -07004349 DRM_ERROR("Failed to map status page.\n");
4350 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
Chris Wilson3eb2ee72009-02-11 14:26:34 +00004351 i915_gem_object_unpin(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07004352 drm_gem_object_unreference(obj);
4353 return -EINVAL;
4354 }
4355 dev_priv->hws_obj = obj;
Eric Anholt673a3942008-07-30 12:06:12 -07004356 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
4357 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
Keith Packardba1eb1d2008-10-14 19:55:10 -07004358 I915_READ(HWS_PGA); /* posting read */
Eric Anholt673a3942008-07-30 12:06:12 -07004359 DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
4360
4361 return 0;
4362}
4363
Chris Wilson85a7bb92009-02-11 14:52:44 +00004364static void
4365i915_gem_cleanup_hws(struct drm_device *dev)
4366{
4367 drm_i915_private_t *dev_priv = dev->dev_private;
Chris Wilsonbab2d1f2009-02-20 17:52:20 +00004368 struct drm_gem_object *obj;
4369 struct drm_i915_gem_object *obj_priv;
Chris Wilson85a7bb92009-02-11 14:52:44 +00004370
4371 if (dev_priv->hws_obj == NULL)
4372 return;
4373
Chris Wilsonbab2d1f2009-02-20 17:52:20 +00004374 obj = dev_priv->hws_obj;
4375 obj_priv = obj->driver_private;
4376
Eric Anholt856fa192009-03-19 14:10:50 -07004377 kunmap(obj_priv->pages[0]);
Chris Wilson85a7bb92009-02-11 14:52:44 +00004378 i915_gem_object_unpin(obj);
4379 drm_gem_object_unreference(obj);
4380 dev_priv->hws_obj = NULL;
Chris Wilsonbab2d1f2009-02-20 17:52:20 +00004381
Chris Wilson85a7bb92009-02-11 14:52:44 +00004382 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4383 dev_priv->hw_status_page = NULL;
4384
4385 /* Write high address into HWS_PGA when disabling. */
4386 I915_WRITE(HWS_PGA, 0x1ffff000);
4387}
4388
Jesse Barnes79e53942008-11-07 14:24:08 -08004389int
Eric Anholt673a3942008-07-30 12:06:12 -07004390i915_gem_init_ringbuffer(struct drm_device *dev)
4391{
4392 drm_i915_private_t *dev_priv = dev->dev_private;
4393 struct drm_gem_object *obj;
4394 struct drm_i915_gem_object *obj_priv;
Jesse Barnes79e53942008-11-07 14:24:08 -08004395 drm_i915_ring_buffer_t *ring = &dev_priv->ring;
Eric Anholt673a3942008-07-30 12:06:12 -07004396 int ret;
Keith Packard50aa2532008-10-14 17:20:35 -07004397 u32 head;
Eric Anholt673a3942008-07-30 12:06:12 -07004398
4399 ret = i915_gem_init_hws(dev);
4400 if (ret != 0)
4401 return ret;
4402
4403 obj = drm_gem_object_alloc(dev, 128 * 1024);
4404 if (obj == NULL) {
4405 DRM_ERROR("Failed to allocate ringbuffer\n");
Chris Wilson85a7bb92009-02-11 14:52:44 +00004406 i915_gem_cleanup_hws(dev);
Eric Anholt673a3942008-07-30 12:06:12 -07004407 return -ENOMEM;
4408 }
4409 obj_priv = obj->driver_private;
4410
4411 ret = i915_gem_object_pin(obj, 4096);
4412 if (ret != 0) {
4413 drm_gem_object_unreference(obj);
Chris Wilson85a7bb92009-02-11 14:52:44 +00004414 i915_gem_cleanup_hws(dev);
Eric Anholt673a3942008-07-30 12:06:12 -07004415 return ret;
4416 }
4417
4418 /* Set up the kernel mapping for the ring. */
Jesse Barnes79e53942008-11-07 14:24:08 -08004419 ring->Size = obj->size;
Eric Anholt673a3942008-07-30 12:06:12 -07004420
Jesse Barnes79e53942008-11-07 14:24:08 -08004421 ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
4422 ring->map.size = obj->size;
4423 ring->map.type = 0;
4424 ring->map.flags = 0;
4425 ring->map.mtrr = 0;
Eric Anholt673a3942008-07-30 12:06:12 -07004426
Jesse Barnes79e53942008-11-07 14:24:08 -08004427 drm_core_ioremap_wc(&ring->map, dev);
4428 if (ring->map.handle == NULL) {
Eric Anholt673a3942008-07-30 12:06:12 -07004429 DRM_ERROR("Failed to map ringbuffer.\n");
4430 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
Chris Wilson47ed1852009-02-11 14:26:33 +00004431 i915_gem_object_unpin(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07004432 drm_gem_object_unreference(obj);
Chris Wilson85a7bb92009-02-11 14:52:44 +00004433 i915_gem_cleanup_hws(dev);
Eric Anholt673a3942008-07-30 12:06:12 -07004434 return -EINVAL;
4435 }
Jesse Barnes79e53942008-11-07 14:24:08 -08004436 ring->ring_obj = obj;
4437 ring->virtual_start = ring->map.handle;
Eric Anholt673a3942008-07-30 12:06:12 -07004438
4439 /* Stop the ring if it's running. */
4440 I915_WRITE(PRB0_CTL, 0);
Eric Anholt673a3942008-07-30 12:06:12 -07004441 I915_WRITE(PRB0_TAIL, 0);
Keith Packard50aa2532008-10-14 17:20:35 -07004442 I915_WRITE(PRB0_HEAD, 0);
Eric Anholt673a3942008-07-30 12:06:12 -07004443
4444 /* Initialize the ring. */
4445 I915_WRITE(PRB0_START, obj_priv->gtt_offset);
Keith Packard50aa2532008-10-14 17:20:35 -07004446 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4447
4448 /* G45 ring initialization fails to reset head to zero */
4449 if (head != 0) {
4450 DRM_ERROR("Ring head not reset to zero "
4451 "ctl %08x head %08x tail %08x start %08x\n",
4452 I915_READ(PRB0_CTL),
4453 I915_READ(PRB0_HEAD),
4454 I915_READ(PRB0_TAIL),
4455 I915_READ(PRB0_START));
4456 I915_WRITE(PRB0_HEAD, 0);
4457
4458 DRM_ERROR("Ring head forced to zero "
4459 "ctl %08x head %08x tail %08x start %08x\n",
4460 I915_READ(PRB0_CTL),
4461 I915_READ(PRB0_HEAD),
4462 I915_READ(PRB0_TAIL),
4463 I915_READ(PRB0_START));
4464 }
4465
Eric Anholt673a3942008-07-30 12:06:12 -07004466 I915_WRITE(PRB0_CTL,
4467 ((obj->size - 4096) & RING_NR_PAGES) |
4468 RING_NO_REPORT |
4469 RING_VALID);
4470
Keith Packard50aa2532008-10-14 17:20:35 -07004471 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4472
4473 /* If the head is still not zero, the ring is dead */
4474 if (head != 0) {
4475 DRM_ERROR("Ring initialization failed "
4476 "ctl %08x head %08x tail %08x start %08x\n",
4477 I915_READ(PRB0_CTL),
4478 I915_READ(PRB0_HEAD),
4479 I915_READ(PRB0_TAIL),
4480 I915_READ(PRB0_START));
4481 return -EIO;
4482 }
4483
Eric Anholt673a3942008-07-30 12:06:12 -07004484 /* Update our cache of the ring state */
Jesse Barnes79e53942008-11-07 14:24:08 -08004485 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4486 i915_kernel_lost_context(dev);
4487 else {
4488 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4489 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
4490 ring->space = ring->head - (ring->tail + 8);
4491 if (ring->space < 0)
4492 ring->space += ring->Size;
4493 }
Eric Anholt673a3942008-07-30 12:06:12 -07004494
4495 return 0;
4496}
4497
Jesse Barnes79e53942008-11-07 14:24:08 -08004498void
Eric Anholt673a3942008-07-30 12:06:12 -07004499i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4500{
4501 drm_i915_private_t *dev_priv = dev->dev_private;
4502
4503 if (dev_priv->ring.ring_obj == NULL)
4504 return;
4505
4506 drm_core_ioremapfree(&dev_priv->ring.map, dev);
4507
4508 i915_gem_object_unpin(dev_priv->ring.ring_obj);
4509 drm_gem_object_unreference(dev_priv->ring.ring_obj);
4510 dev_priv->ring.ring_obj = NULL;
4511 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4512
Chris Wilson85a7bb92009-02-11 14:52:44 +00004513 i915_gem_cleanup_hws(dev);
Eric Anholt673a3942008-07-30 12:06:12 -07004514}
4515
4516int
4517i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4518 struct drm_file *file_priv)
4519{
4520 drm_i915_private_t *dev_priv = dev->dev_private;
4521 int ret;
4522
Jesse Barnes79e53942008-11-07 14:24:08 -08004523 if (drm_core_check_feature(dev, DRIVER_MODESET))
4524 return 0;
4525
Ben Gamariba1234d2009-09-14 17:48:47 -04004526 if (atomic_read(&dev_priv->mm.wedged)) {
Eric Anholt673a3942008-07-30 12:06:12 -07004527 DRM_ERROR("Reenabling wedged hardware, good luck\n");
Ben Gamariba1234d2009-09-14 17:48:47 -04004528 atomic_set(&dev_priv->mm.wedged, 0);
Eric Anholt673a3942008-07-30 12:06:12 -07004529 }
4530
Eric Anholt673a3942008-07-30 12:06:12 -07004531 mutex_lock(&dev->struct_mutex);
Eric Anholt9bb2d6f2008-12-23 18:42:32 -08004532 dev_priv->mm.suspended = 0;
4533
4534 ret = i915_gem_init_ringbuffer(dev);
Wu Fengguangd816f6a2009-04-18 10:43:32 +08004535 if (ret != 0) {
4536 mutex_unlock(&dev->struct_mutex);
Eric Anholt9bb2d6f2008-12-23 18:42:32 -08004537 return ret;
Wu Fengguangd816f6a2009-04-18 10:43:32 +08004538 }
Eric Anholt9bb2d6f2008-12-23 18:42:32 -08004539
Carl Worth5e118f42009-03-20 11:54:25 -07004540 spin_lock(&dev_priv->mm.active_list_lock);
Eric Anholt673a3942008-07-30 12:06:12 -07004541 BUG_ON(!list_empty(&dev_priv->mm.active_list));
Carl Worth5e118f42009-03-20 11:54:25 -07004542 spin_unlock(&dev_priv->mm.active_list_lock);
4543
Eric Anholt673a3942008-07-30 12:06:12 -07004544 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4545 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4546 BUG_ON(!list_empty(&dev_priv->mm.request_list));
Eric Anholt673a3942008-07-30 12:06:12 -07004547 mutex_unlock(&dev->struct_mutex);
Kristian Høgsbergdbb19d32008-08-20 11:04:27 -04004548
4549 drm_irq_install(dev);
4550
Eric Anholt673a3942008-07-30 12:06:12 -07004551 return 0;
4552}
4553
4554int
4555i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4556 struct drm_file *file_priv)
4557{
Jesse Barnes79e53942008-11-07 14:24:08 -08004558 if (drm_core_check_feature(dev, DRIVER_MODESET))
4559 return 0;
4560
Kristian Høgsbergdbb19d32008-08-20 11:04:27 -04004561 drm_irq_uninstall(dev);
Linus Torvaldse6890f62009-09-08 17:09:24 -07004562 return i915_gem_idle(dev);
Eric Anholt673a3942008-07-30 12:06:12 -07004563}
4564
4565void
4566i915_gem_lastclose(struct drm_device *dev)
4567{
4568 int ret;
Eric Anholt673a3942008-07-30 12:06:12 -07004569
Eric Anholte806b492009-01-22 09:56:58 -08004570 if (drm_core_check_feature(dev, DRIVER_MODESET))
4571 return;
4572
Keith Packard6dbe2772008-10-14 21:41:13 -07004573 ret = i915_gem_idle(dev);
4574 if (ret)
4575 DRM_ERROR("failed to idle hardware: %d\n", ret);
Eric Anholt673a3942008-07-30 12:06:12 -07004576}
4577
4578void
4579i915_gem_load(struct drm_device *dev)
4580{
Grégoire Henryb5aa8a02009-06-23 15:41:02 +02004581 int i;
Eric Anholt673a3942008-07-30 12:06:12 -07004582 drm_i915_private_t *dev_priv = dev->dev_private;
4583
Carl Worth5e118f42009-03-20 11:54:25 -07004584 spin_lock_init(&dev_priv->mm.active_list_lock);
Eric Anholt673a3942008-07-30 12:06:12 -07004585 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4586 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4587 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4588 INIT_LIST_HEAD(&dev_priv->mm.request_list);
Eric Anholta09ba7f2009-08-29 12:49:51 -07004589 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
Eric Anholt673a3942008-07-30 12:06:12 -07004590 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4591 i915_gem_retire_work_handler);
Eric Anholt673a3942008-07-30 12:06:12 -07004592 dev_priv->mm.next_gem_seqno = 1;
4593
Chris Wilson31169712009-09-14 16:50:28 +01004594 spin_lock(&shrink_list_lock);
4595 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4596 spin_unlock(&shrink_list_lock);
4597
Jesse Barnesde151cf2008-11-12 10:03:55 -08004598 /* Old X drivers will take 0-2 for front, back, depth buffers */
4599 dev_priv->fence_reg_start = 3;
4600
Jesse Barnes0f973f22009-01-26 17:10:45 -08004601 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
Jesse Barnesde151cf2008-11-12 10:03:55 -08004602 dev_priv->num_fence_regs = 16;
4603 else
4604 dev_priv->num_fence_regs = 8;
4605
Grégoire Henryb5aa8a02009-06-23 15:41:02 +02004606 /* Initialize fence registers to zero */
4607 if (IS_I965G(dev)) {
4608 for (i = 0; i < 16; i++)
4609 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4610 } else {
4611 for (i = 0; i < 8; i++)
4612 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4613 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4614 for (i = 0; i < 8; i++)
4615 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4616 }
4617
Eric Anholt673a3942008-07-30 12:06:12 -07004618 i915_gem_detect_bit_6_swizzle(dev);
4619}
Dave Airlie71acb5e2008-12-30 20:31:46 +10004620
4621/*
4622 * Create a physically contiguous memory object for this object
4623 * e.g. for cursor + overlay regs
4624 */
4625int i915_gem_init_phys_object(struct drm_device *dev,
4626 int id, int size)
4627{
4628 drm_i915_private_t *dev_priv = dev->dev_private;
4629 struct drm_i915_gem_phys_object *phys_obj;
4630 int ret;
4631
4632 if (dev_priv->mm.phys_objs[id - 1] || !size)
4633 return 0;
4634
Eric Anholt9a298b22009-03-24 12:23:04 -07004635 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004636 if (!phys_obj)
4637 return -ENOMEM;
4638
4639 phys_obj->id = id;
4640
4641 phys_obj->handle = drm_pci_alloc(dev, size, 0, 0xffffffff);
4642 if (!phys_obj->handle) {
4643 ret = -ENOMEM;
4644 goto kfree_obj;
4645 }
4646#ifdef CONFIG_X86
4647 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4648#endif
4649
4650 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4651
4652 return 0;
4653kfree_obj:
Eric Anholt9a298b22009-03-24 12:23:04 -07004654 kfree(phys_obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004655 return ret;
4656}
4657
4658void i915_gem_free_phys_object(struct drm_device *dev, int id)
4659{
4660 drm_i915_private_t *dev_priv = dev->dev_private;
4661 struct drm_i915_gem_phys_object *phys_obj;
4662
4663 if (!dev_priv->mm.phys_objs[id - 1])
4664 return;
4665
4666 phys_obj = dev_priv->mm.phys_objs[id - 1];
4667 if (phys_obj->cur_obj) {
4668 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4669 }
4670
4671#ifdef CONFIG_X86
4672 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4673#endif
4674 drm_pci_free(dev, phys_obj->handle);
4675 kfree(phys_obj);
4676 dev_priv->mm.phys_objs[id - 1] = NULL;
4677}
4678
4679void i915_gem_free_all_phys_object(struct drm_device *dev)
4680{
4681 int i;
4682
Dave Airlie260883c2009-01-22 17:58:49 +10004683 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
Dave Airlie71acb5e2008-12-30 20:31:46 +10004684 i915_gem_free_phys_object(dev, i);
4685}
4686
4687void i915_gem_detach_phys_object(struct drm_device *dev,
4688 struct drm_gem_object *obj)
4689{
4690 struct drm_i915_gem_object *obj_priv;
4691 int i;
4692 int ret;
4693 int page_count;
4694
4695 obj_priv = obj->driver_private;
4696 if (!obj_priv->phys_obj)
4697 return;
4698
Eric Anholt856fa192009-03-19 14:10:50 -07004699 ret = i915_gem_object_get_pages(obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004700 if (ret)
4701 goto out;
4702
4703 page_count = obj->size / PAGE_SIZE;
4704
4705 for (i = 0; i < page_count; i++) {
Eric Anholt856fa192009-03-19 14:10:50 -07004706 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004707 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4708
4709 memcpy(dst, src, PAGE_SIZE);
4710 kunmap_atomic(dst, KM_USER0);
4711 }
Eric Anholt856fa192009-03-19 14:10:50 -07004712 drm_clflush_pages(obj_priv->pages, page_count);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004713 drm_agp_chipset_flush(dev);
Chris Wilsond78b47b2009-06-17 21:52:49 +01004714
4715 i915_gem_object_put_pages(obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004716out:
4717 obj_priv->phys_obj->cur_obj = NULL;
4718 obj_priv->phys_obj = NULL;
4719}
4720
4721int
4722i915_gem_attach_phys_object(struct drm_device *dev,
4723 struct drm_gem_object *obj, int id)
4724{
4725 drm_i915_private_t *dev_priv = dev->dev_private;
4726 struct drm_i915_gem_object *obj_priv;
4727 int ret = 0;
4728 int page_count;
4729 int i;
4730
4731 if (id > I915_MAX_PHYS_OBJECT)
4732 return -EINVAL;
4733
4734 obj_priv = obj->driver_private;
4735
4736 if (obj_priv->phys_obj) {
4737 if (obj_priv->phys_obj->id == id)
4738 return 0;
4739 i915_gem_detach_phys_object(dev, obj);
4740 }
4741
4742
4743 /* create a new object */
4744 if (!dev_priv->mm.phys_objs[id - 1]) {
4745 ret = i915_gem_init_phys_object(dev, id,
4746 obj->size);
4747 if (ret) {
Linus Torvaldsaeb565d2009-01-26 10:01:53 -08004748 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004749 goto out;
4750 }
4751 }
4752
4753 /* bind to the object */
4754 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4755 obj_priv->phys_obj->cur_obj = obj;
4756
Eric Anholt856fa192009-03-19 14:10:50 -07004757 ret = i915_gem_object_get_pages(obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004758 if (ret) {
4759 DRM_ERROR("failed to get page list\n");
4760 goto out;
4761 }
4762
4763 page_count = obj->size / PAGE_SIZE;
4764
4765 for (i = 0; i < page_count; i++) {
Eric Anholt856fa192009-03-19 14:10:50 -07004766 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004767 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4768
4769 memcpy(dst, src, PAGE_SIZE);
4770 kunmap_atomic(src, KM_USER0);
4771 }
4772
Chris Wilsond78b47b2009-06-17 21:52:49 +01004773 i915_gem_object_put_pages(obj);
4774
Dave Airlie71acb5e2008-12-30 20:31:46 +10004775 return 0;
4776out:
4777 return ret;
4778}
4779
4780static int
4781i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4782 struct drm_i915_gem_pwrite *args,
4783 struct drm_file *file_priv)
4784{
4785 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4786 void *obj_addr;
4787 int ret;
4788 char __user *user_data;
4789
4790 user_data = (char __user *) (uintptr_t) args->data_ptr;
4791 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4792
Dave Airliee08fb4f2009-02-25 14:52:30 +10004793 DRM_DEBUG("obj_addr %p, %lld\n", obj_addr, args->size);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004794 ret = copy_from_user(obj_addr, user_data, args->size);
4795 if (ret)
4796 return -EFAULT;
4797
4798 drm_agp_chipset_flush(dev);
4799 return 0;
4800}
Eric Anholtb9624422009-06-03 07:27:35 +00004801
4802void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
4803{
4804 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
4805
4806 /* Clean up our request list when the client is going away, so that
4807 * later retire_requests won't dereference our soon-to-be-gone
4808 * file_priv.
4809 */
4810 mutex_lock(&dev->struct_mutex);
4811 while (!list_empty(&i915_file_priv->mm.request_list))
4812 list_del_init(i915_file_priv->mm.request_list.next);
4813 mutex_unlock(&dev->struct_mutex);
4814}
Chris Wilson31169712009-09-14 16:50:28 +01004815
Chris Wilson31169712009-09-14 16:50:28 +01004816static int
4817i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask)
4818{
4819 drm_i915_private_t *dev_priv, *next_dev;
4820 struct drm_i915_gem_object *obj_priv, *next_obj;
4821 int cnt = 0;
4822 int would_deadlock = 1;
4823
4824 /* "fast-path" to count number of available objects */
4825 if (nr_to_scan == 0) {
4826 spin_lock(&shrink_list_lock);
4827 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4828 struct drm_device *dev = dev_priv->dev;
4829
4830 if (mutex_trylock(&dev->struct_mutex)) {
4831 list_for_each_entry(obj_priv,
4832 &dev_priv->mm.inactive_list,
4833 list)
4834 cnt++;
4835 mutex_unlock(&dev->struct_mutex);
4836 }
4837 }
4838 spin_unlock(&shrink_list_lock);
4839
4840 return (cnt / 100) * sysctl_vfs_cache_pressure;
4841 }
4842
4843 spin_lock(&shrink_list_lock);
4844
4845 /* first scan for clean buffers */
4846 list_for_each_entry_safe(dev_priv, next_dev,
4847 &shrink_list, mm.shrink_list) {
4848 struct drm_device *dev = dev_priv->dev;
4849
4850 if (! mutex_trylock(&dev->struct_mutex))
4851 continue;
4852
4853 spin_unlock(&shrink_list_lock);
4854
4855 i915_gem_retire_requests(dev);
4856
4857 list_for_each_entry_safe(obj_priv, next_obj,
4858 &dev_priv->mm.inactive_list,
4859 list) {
4860 if (i915_gem_object_is_purgeable(obj_priv)) {
Chris Wilson963b4832009-09-20 23:03:54 +01004861 i915_gem_object_unbind(obj_priv->obj);
Chris Wilson31169712009-09-14 16:50:28 +01004862 if (--nr_to_scan <= 0)
4863 break;
4864 }
4865 }
4866
4867 spin_lock(&shrink_list_lock);
4868 mutex_unlock(&dev->struct_mutex);
4869
Chris Wilson963b4832009-09-20 23:03:54 +01004870 would_deadlock = 0;
4871
Chris Wilson31169712009-09-14 16:50:28 +01004872 if (nr_to_scan <= 0)
4873 break;
4874 }
4875
4876 /* second pass, evict/count anything still on the inactive list */
4877 list_for_each_entry_safe(dev_priv, next_dev,
4878 &shrink_list, mm.shrink_list) {
4879 struct drm_device *dev = dev_priv->dev;
4880
4881 if (! mutex_trylock(&dev->struct_mutex))
4882 continue;
4883
4884 spin_unlock(&shrink_list_lock);
4885
4886 list_for_each_entry_safe(obj_priv, next_obj,
4887 &dev_priv->mm.inactive_list,
4888 list) {
4889 if (nr_to_scan > 0) {
Chris Wilson963b4832009-09-20 23:03:54 +01004890 i915_gem_object_unbind(obj_priv->obj);
Chris Wilson31169712009-09-14 16:50:28 +01004891 nr_to_scan--;
4892 } else
4893 cnt++;
4894 }
4895
4896 spin_lock(&shrink_list_lock);
4897 mutex_unlock(&dev->struct_mutex);
4898
4899 would_deadlock = 0;
4900 }
4901
4902 spin_unlock(&shrink_list_lock);
4903
4904 if (would_deadlock)
4905 return -1;
4906 else if (cnt > 0)
4907 return (cnt / 100) * sysctl_vfs_cache_pressure;
4908 else
4909 return 0;
4910}
4911
4912static struct shrinker shrinker = {
4913 .shrink = i915_gem_shrink,
4914 .seeks = DEFAULT_SEEKS,
4915};
4916
4917__init void
4918i915_gem_shrinker_init(void)
4919{
4920 register_shrinker(&shrinker);
4921}
4922
4923__exit void
4924i915_gem_shrinker_exit(void)
4925{
4926 unregister_shrinker(&shrinker);
4927}