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gerrit-public.fairphone.software / fp2-dev / kernel / msm / b445e26cbf784cdba10f2b6c3e2cd3ee7bab360a / . / arch / sparc64 / lib / VISsave.S
blob: 4e18989bd60299e67b693f7e2d9070b52d0cb190 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/* $Id: VISsave.S,v 1.6 2002/02/09 19:49:30 davem Exp $
2 * VISsave.S: Code for saving FPU register state for
3 * VIS routines. One should not call this directly,
4 * but use macros provided in <asm/visasm.h>.
5 *
6 * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
7 */
8
9#include <asm/asi.h>
10#include <asm/page.h>
11#include <asm/ptrace.h>
12#include <asm/visasm.h>
13#include <asm/thread_info.h>
14
15 .text
16 .globl VISenter, VISenterhalf
17
18 /* On entry: %o5=current FPRS value, %g7 is callers address */
19 /* May clobber %o5, %g1, %g2, %g3, %g7, %icc, %xcc */
20
21 /* Nothing special need be done here to handle pre-emption, this
22 * FPU save/restore mechanism is already preemption safe.
23 */
24
25 .align 32
26VISenter:
27 ldub [%g6 + TI_FPDEPTH], %g1
28 brnz,a,pn %g1, 1f
29 cmp %g1, 1
30 stb %g0, [%g6 + TI_FPSAVED]
31 stx %fsr, [%g6 + TI_XFSR]
329: jmpl %g7 + %g0, %g0
33 nop
341: bne,pn %icc, 2f
35
36 srl %g1, 1, %g1
37vis1: ldub [%g6 + TI_FPSAVED], %g3
38 stx %fsr, [%g6 + TI_XFSR]
39 or %g3, %o5, %g3
40 stb %g3, [%g6 + TI_FPSAVED]
41 rd %gsr, %g3
42 clr %g1
43 ba,pt %xcc, 3f
44
45 stx %g3, [%g6 + TI_GSR]
462: add %g6, %g1, %g3
47 cmp %o5, FPRS_DU
48 be,pn %icc, 6f
49 sll %g1, 3, %g1
50 stb %o5, [%g3 + TI_FPSAVED]
51 rd %gsr, %g2
52 add %g6, %g1, %g3
53 stx %g2, [%g3 + TI_GSR]
54
55 add %g6, %g1, %g2
56 stx %fsr, [%g2 + TI_XFSR]
57 sll %g1, 5, %g1
583: andcc %o5, FPRS_DL|FPRS_DU, %g0
59 be,pn %icc, 9b
60 add %g6, TI_FPREGS, %g2
61 andcc %o5, FPRS_DL, %g0
62 membar #StoreStore | #LoadStore
63
64 be,pn %icc, 4f
65 add %g6, TI_FPREGS+0x40, %g3
66 stda %f0, [%g2 + %g1] ASI_BLK_P
67 stda %f16, [%g3 + %g1] ASI_BLK_P
68 andcc %o5, FPRS_DU, %g0
69 be,pn %icc, 5f
704: add %g1, 128, %g1
71 stda %f32, [%g2 + %g1] ASI_BLK_P
72
73 stda %f48, [%g3 + %g1] ASI_BLK_P
745: membar #Sync
David S. Millerb445e262005-06-27 15:42:04 -0700[diff] [blame^]75 ba,pt %xcc, 80f
76 nop
77
78 .align 32
7980: jmpl %g7 + %g0, %g0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]80 nop
81
826: ldub [%g3 + TI_FPSAVED], %o5
83 or %o5, FPRS_DU, %o5
84 add %g6, TI_FPREGS+0x80, %g2
85 stb %o5, [%g3 + TI_FPSAVED]
86
87 sll %g1, 5, %g1
88 add %g6, TI_FPREGS+0xc0, %g3
89 wr %g0, FPRS_FEF, %fprs
90 membar #StoreStore | #LoadStore
91 stda %f32, [%g2 + %g1] ASI_BLK_P
92 stda %f48, [%g3 + %g1] ASI_BLK_P
93 membar #Sync
David S. Millerb445e262005-06-27 15:42:04 -0700[diff] [blame^]94 ba,pt %xcc, 80f
95 nop
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]96
David S. Millerb445e262005-06-27 15:42:04 -0700[diff] [blame^]97 .align 32
9880: jmpl %g7 + %g0, %g0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]99 nop
100
101 .align 32
102VISenterhalf:
103 ldub [%g6 + TI_FPDEPTH], %g1
104 brnz,a,pn %g1, 1f
105 cmp %g1, 1
106 stb %g0, [%g6 + TI_FPSAVED]
107 stx %fsr, [%g6 + TI_XFSR]
108 clr %o5
109 jmpl %g7 + %g0, %g0
110 wr %g0, FPRS_FEF, %fprs
111
1121: bne,pn %icc, 2f
113 srl %g1, 1, %g1
114 ba,pt %xcc, vis1
115 sub %g7, 8, %g7
1162: addcc %g6, %g1, %g3
117 sll %g1, 3, %g1
118 andn %o5, FPRS_DU, %g2
119 stb %g2, [%g3 + TI_FPSAVED]
120
121 rd %gsr, %g2
122 add %g6, %g1, %g3
123 stx %g2, [%g3 + TI_GSR]
124 add %g6, %g1, %g2
125 stx %fsr, [%g2 + TI_XFSR]
126 sll %g1, 5, %g1
1273: andcc %o5, FPRS_DL, %g0
128 be,pn %icc, 4f
129 add %g6, TI_FPREGS, %g2
130
131 membar #StoreStore | #LoadStore
132 add %g6, TI_FPREGS+0x40, %g3
133 stda %f0, [%g2 + %g1] ASI_BLK_P
134 stda %f16, [%g3 + %g1] ASI_BLK_P
135 membar #Sync
David S. Millerb445e262005-06-27 15:42:04 -0700[diff] [blame^]136 ba,pt %xcc, 4f
137 nop
138
139 .align 32
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1404: and %o5, FPRS_DU, %o5
141 jmpl %g7 + %g0, %g0
142 wr %o5, FPRS_FEF, %fprs