Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * drivers/pci/setup-bus.c |
| 3 | * |
| 4 | * Extruded from code written by |
| 5 | * Dave Rusling (david.rusling@reo.mts.dec.com) |
| 6 | * David Mosberger (davidm@cs.arizona.edu) |
| 7 | * David Miller (davem@redhat.com) |
| 8 | * |
| 9 | * Support routines for initializing a PCI subsystem. |
| 10 | */ |
| 11 | |
| 12 | /* |
| 13 | * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> |
| 14 | * PCI-PCI bridges cleanup, sorted resource allocation. |
| 15 | * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru> |
| 16 | * Converted to allocation in 3 passes, which gives |
| 17 | * tighter packing. Prefetchable range support. |
| 18 | */ |
| 19 | |
| 20 | #include <linux/init.h> |
| 21 | #include <linux/kernel.h> |
| 22 | #include <linux/module.h> |
| 23 | #include <linux/pci.h> |
| 24 | #include <linux/errno.h> |
| 25 | #include <linux/ioport.h> |
| 26 | #include <linux/cache.h> |
| 27 | #include <linux/slab.h> |
Chris Wright | 6faf17f | 2009-08-28 13:00:06 -0700 | [diff] [blame] | 28 | #include "pci.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 29 | |
Yinghai Lu | 568ddef | 2010-01-22 01:02:21 -0800 | [diff] [blame] | 30 | struct resource_list_x { |
| 31 | struct resource_list_x *next; |
| 32 | struct resource *res; |
| 33 | struct pci_dev *dev; |
| 34 | resource_size_t start; |
| 35 | resource_size_t end; |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 36 | resource_size_t add_size; |
Yinghai Lu | 568ddef | 2010-01-22 01:02:21 -0800 | [diff] [blame] | 37 | unsigned long flags; |
| 38 | }; |
| 39 | |
Ram Pai | 094732a | 2011-02-14 17:43:18 -0800 | [diff] [blame] | 40 | #define free_list(type, head) do { \ |
| 41 | struct type *list, *tmp; \ |
| 42 | for (list = (head)->next; list;) { \ |
| 43 | tmp = list; \ |
| 44 | list = list->next; \ |
| 45 | kfree(tmp); \ |
| 46 | } \ |
| 47 | (head)->next = NULL; \ |
| 48 | } while (0) |
| 49 | |
Ram Pai | f483d39 | 2011-07-07 11:19:10 -0700 | [diff] [blame] | 50 | int pci_realloc_enable = 0; |
| 51 | #define pci_realloc_enabled() pci_realloc_enable |
| 52 | void pci_realloc(void) |
| 53 | { |
| 54 | pci_realloc_enable = 1; |
| 55 | } |
| 56 | |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 57 | /** |
| 58 | * add_to_list() - add a new resource tracker to the list |
| 59 | * @head: Head of the list |
| 60 | * @dev: device corresponding to which the resource |
| 61 | * belongs |
| 62 | * @res: The resource to be tracked |
| 63 | * @add_size: additional size to be optionally added |
| 64 | * to the resource |
| 65 | */ |
| 66 | static void add_to_list(struct resource_list_x *head, |
| 67 | struct pci_dev *dev, struct resource *res, |
| 68 | resource_size_t add_size) |
Yinghai Lu | 568ddef | 2010-01-22 01:02:21 -0800 | [diff] [blame] | 69 | { |
| 70 | struct resource_list_x *list = head; |
| 71 | struct resource_list_x *ln = list->next; |
| 72 | struct resource_list_x *tmp; |
| 73 | |
| 74 | tmp = kmalloc(sizeof(*tmp), GFP_KERNEL); |
| 75 | if (!tmp) { |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 76 | pr_warning("add_to_list: kmalloc() failed!\n"); |
Yinghai Lu | 568ddef | 2010-01-22 01:02:21 -0800 | [diff] [blame] | 77 | return; |
| 78 | } |
| 79 | |
| 80 | tmp->next = ln; |
| 81 | tmp->res = res; |
| 82 | tmp->dev = dev; |
| 83 | tmp->start = res->start; |
| 84 | tmp->end = res->end; |
| 85 | tmp->flags = res->flags; |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 86 | tmp->add_size = add_size; |
Yinghai Lu | 568ddef | 2010-01-22 01:02:21 -0800 | [diff] [blame] | 87 | list->next = tmp; |
| 88 | } |
| 89 | |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 90 | static void add_to_failed_list(struct resource_list_x *head, |
| 91 | struct pci_dev *dev, struct resource *res) |
| 92 | { |
| 93 | add_to_list(head, dev, res, 0); |
| 94 | } |
| 95 | |
Yinghai Lu | 6841ec6 | 2010-01-22 01:02:25 -0800 | [diff] [blame] | 96 | static void __dev_sort_resources(struct pci_dev *dev, |
| 97 | struct resource_list *head) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 98 | { |
Yinghai Lu | 6841ec6 | 2010-01-22 01:02:25 -0800 | [diff] [blame] | 99 | u16 class = dev->class >> 8; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 100 | |
Yinghai Lu | 6841ec6 | 2010-01-22 01:02:25 -0800 | [diff] [blame] | 101 | /* Don't touch classless devices or host bridges or ioapics. */ |
| 102 | if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST) |
| 103 | return; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 104 | |
Yinghai Lu | 6841ec6 | 2010-01-22 01:02:25 -0800 | [diff] [blame] | 105 | /* Don't touch ioapic devices already enabled by firmware */ |
| 106 | if (class == PCI_CLASS_SYSTEM_PIC) { |
| 107 | u16 command; |
| 108 | pci_read_config_word(dev, PCI_COMMAND, &command); |
| 109 | if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) |
| 110 | return; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 111 | } |
| 112 | |
Yinghai Lu | 6841ec6 | 2010-01-22 01:02:25 -0800 | [diff] [blame] | 113 | pdev_sort_resources(dev, head); |
| 114 | } |
| 115 | |
Ram Pai | fc075e1 | 2011-02-14 17:43:19 -0800 | [diff] [blame] | 116 | static inline void reset_resource(struct resource *res) |
| 117 | { |
| 118 | res->start = 0; |
| 119 | res->end = 0; |
| 120 | res->flags = 0; |
| 121 | } |
| 122 | |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 123 | /** |
| 124 | * adjust_resources_sorted() - satisfy any additional resource requests |
| 125 | * |
| 126 | * @add_head : head of the list tracking requests requiring additional |
| 127 | * resources |
| 128 | * @head : head of the list tracking requests with allocated |
| 129 | * resources |
| 130 | * |
| 131 | * Walk through each element of the add_head and try to procure |
| 132 | * additional resources for the element, provided the element |
| 133 | * is in the head list. |
| 134 | */ |
| 135 | static void adjust_resources_sorted(struct resource_list_x *add_head, |
| 136 | struct resource_list *head) |
| 137 | { |
| 138 | struct resource *res; |
| 139 | struct resource_list_x *list, *tmp, *prev; |
| 140 | struct resource_list *hlist; |
| 141 | resource_size_t add_size; |
| 142 | int idx; |
| 143 | |
| 144 | prev = add_head; |
| 145 | for (list = add_head->next; list;) { |
| 146 | res = list->res; |
| 147 | /* skip resource that has been reset */ |
| 148 | if (!res->flags) |
| 149 | goto out; |
| 150 | |
| 151 | /* skip this resource if not found in head list */ |
| 152 | for (hlist = head->next; hlist && hlist->res != res; |
| 153 | hlist = hlist->next); |
| 154 | if (!hlist) { /* just skip */ |
| 155 | prev = list; |
| 156 | list = list->next; |
| 157 | continue; |
| 158 | } |
| 159 | |
| 160 | idx = res - &list->dev->resource[0]; |
| 161 | add_size=list->add_size; |
| 162 | if (!resource_size(res) && add_size) { |
| 163 | res->end = res->start + add_size - 1; |
| 164 | if(pci_assign_resource(list->dev, idx)) |
| 165 | reset_resource(res); |
| 166 | } else if (add_size) { |
| 167 | adjust_resource(res, res->start, |
| 168 | resource_size(res) + add_size); |
| 169 | } |
| 170 | out: |
| 171 | tmp = list; |
| 172 | prev->next = list = list->next; |
| 173 | kfree(tmp); |
| 174 | } |
| 175 | } |
| 176 | |
| 177 | /** |
| 178 | * assign_requested_resources_sorted() - satisfy resource requests |
| 179 | * |
| 180 | * @head : head of the list tracking requests for resources |
| 181 | * @failed_list : head of the list tracking requests that could |
| 182 | * not be allocated |
| 183 | * |
| 184 | * Satisfy resource requests of each element in the list. Add |
| 185 | * requests that could not satisfied to the failed_list. |
| 186 | */ |
| 187 | static void assign_requested_resources_sorted(struct resource_list *head, |
Yinghai Lu | 6841ec6 | 2010-01-22 01:02:25 -0800 | [diff] [blame] | 188 | struct resource_list_x *fail_head) |
| 189 | { |
| 190 | struct resource *res; |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 191 | struct resource_list *list; |
Yinghai Lu | 6841ec6 | 2010-01-22 01:02:25 -0800 | [diff] [blame] | 192 | int idx; |
| 193 | |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 194 | for (list = head->next; list; list = list->next) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 195 | res = list->res; |
| 196 | idx = res - &list->dev->resource[0]; |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 197 | if (resource_size(res) && pci_assign_resource(list->dev, idx)) { |
Yinghai Lu | 9a92866 | 2010-02-28 15:49:39 -0800 | [diff] [blame] | 198 | if (fail_head && !pci_is_root_bus(list->dev->bus)) { |
| 199 | /* |
| 200 | * if the failed res is for ROM BAR, and it will |
| 201 | * be enabled later, don't add it to the list |
| 202 | */ |
| 203 | if (!((idx == PCI_ROM_RESOURCE) && |
| 204 | (!(res->flags & IORESOURCE_ROM_ENABLE)))) |
| 205 | add_to_failed_list(fail_head, list->dev, res); |
| 206 | } |
Ram Pai | fc075e1 | 2011-02-14 17:43:19 -0800 | [diff] [blame] | 207 | reset_resource(res); |
Rajesh Shah | 542df5d | 2005-04-28 00:25:50 -0700 | [diff] [blame] | 208 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 209 | } |
| 210 | } |
| 211 | |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 212 | static void __assign_resources_sorted(struct resource_list *head, |
| 213 | struct resource_list_x *add_head, |
| 214 | struct resource_list_x *fail_head) |
| 215 | { |
| 216 | /* Satisfy the must-have resource requests */ |
| 217 | assign_requested_resources_sorted(head, fail_head); |
| 218 | |
| 219 | /* Try to satisfy any additional nice-to-have resource |
| 220 | requests */ |
| 221 | if (add_head) |
| 222 | adjust_resources_sorted(add_head, head); |
| 223 | free_list(resource_list, head); |
| 224 | } |
| 225 | |
Yinghai Lu | 6841ec6 | 2010-01-22 01:02:25 -0800 | [diff] [blame] | 226 | static void pdev_assign_resources_sorted(struct pci_dev *dev, |
| 227 | struct resource_list_x *fail_head) |
| 228 | { |
| 229 | struct resource_list head; |
| 230 | |
| 231 | head.next = NULL; |
| 232 | __dev_sort_resources(dev, &head); |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 233 | __assign_resources_sorted(&head, NULL, fail_head); |
Yinghai Lu | 6841ec6 | 2010-01-22 01:02:25 -0800 | [diff] [blame] | 234 | |
| 235 | } |
| 236 | |
| 237 | static void pbus_assign_resources_sorted(const struct pci_bus *bus, |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 238 | struct resource_list_x *add_head, |
Yinghai Lu | 6841ec6 | 2010-01-22 01:02:25 -0800 | [diff] [blame] | 239 | struct resource_list_x *fail_head) |
| 240 | { |
| 241 | struct pci_dev *dev; |
| 242 | struct resource_list head; |
| 243 | |
| 244 | head.next = NULL; |
| 245 | list_for_each_entry(dev, &bus->devices, bus_list) |
| 246 | __dev_sort_resources(dev, &head); |
| 247 | |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 248 | __assign_resources_sorted(&head, add_head, fail_head); |
Yinghai Lu | 6841ec6 | 2010-01-22 01:02:25 -0800 | [diff] [blame] | 249 | } |
| 250 | |
Dominik Brodowski | b3743fa | 2005-09-09 13:03:23 -0700 | [diff] [blame] | 251 | void pci_setup_cardbus(struct pci_bus *bus) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 252 | { |
| 253 | struct pci_dev *bridge = bus->self; |
Bjorn Helgaas | c7dabef | 2009-10-27 13:26:47 -0600 | [diff] [blame] | 254 | struct resource *res; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 255 | struct pci_bus_region region; |
| 256 | |
Bjorn Helgaas | 865df57 | 2009-11-04 10:32:57 -0700 | [diff] [blame] | 257 | dev_info(&bridge->dev, "CardBus bridge to [bus %02x-%02x]\n", |
| 258 | bus->secondary, bus->subordinate); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 259 | |
Bjorn Helgaas | c7dabef | 2009-10-27 13:26:47 -0600 | [diff] [blame] | 260 | res = bus->resource[0]; |
| 261 | pcibios_resource_to_bus(bridge, ®ion, res); |
| 262 | if (res->flags & IORESOURCE_IO) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 263 | /* |
| 264 | * The IO resource is allocated a range twice as large as it |
| 265 | * would normally need. This allows us to set both IO regs. |
| 266 | */ |
Bjorn Helgaas | c7dabef | 2009-10-27 13:26:47 -0600 | [diff] [blame] | 267 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 268 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, |
| 269 | region.start); |
| 270 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, |
| 271 | region.end); |
| 272 | } |
| 273 | |
Bjorn Helgaas | c7dabef | 2009-10-27 13:26:47 -0600 | [diff] [blame] | 274 | res = bus->resource[1]; |
| 275 | pcibios_resource_to_bus(bridge, ®ion, res); |
| 276 | if (res->flags & IORESOURCE_IO) { |
| 277 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 278 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, |
| 279 | region.start); |
| 280 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, |
| 281 | region.end); |
| 282 | } |
| 283 | |
Bjorn Helgaas | c7dabef | 2009-10-27 13:26:47 -0600 | [diff] [blame] | 284 | res = bus->resource[2]; |
| 285 | pcibios_resource_to_bus(bridge, ®ion, res); |
| 286 | if (res->flags & IORESOURCE_MEM) { |
| 287 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 288 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, |
| 289 | region.start); |
| 290 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, |
| 291 | region.end); |
| 292 | } |
| 293 | |
Bjorn Helgaas | c7dabef | 2009-10-27 13:26:47 -0600 | [diff] [blame] | 294 | res = bus->resource[3]; |
| 295 | pcibios_resource_to_bus(bridge, ®ion, res); |
| 296 | if (res->flags & IORESOURCE_MEM) { |
| 297 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 298 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, |
| 299 | region.start); |
| 300 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, |
| 301 | region.end); |
| 302 | } |
| 303 | } |
Dominik Brodowski | b3743fa | 2005-09-09 13:03:23 -0700 | [diff] [blame] | 304 | EXPORT_SYMBOL(pci_setup_cardbus); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 305 | |
| 306 | /* Initialize bridges with base/limit values we have collected. |
| 307 | PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998) |
| 308 | requires that if there is no I/O ports or memory behind the |
| 309 | bridge, corresponding range must be turned off by writing base |
| 310 | value greater than limit to the bridge's base/limit registers. |
| 311 | |
| 312 | Note: care must be taken when updating I/O base/limit registers |
| 313 | of bridges which support 32-bit I/O. This update requires two |
| 314 | config space writes, so it's quite possible that an I/O window of |
| 315 | the bridge will have some undesirable address (e.g. 0) after the |
| 316 | first write. Ditto 64-bit prefetchable MMIO. */ |
Yinghai Lu | 7cc5997 | 2009-12-22 15:02:21 -0800 | [diff] [blame] | 317 | static void pci_setup_bridge_io(struct pci_bus *bus) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 318 | { |
| 319 | struct pci_dev *bridge = bus->self; |
Bjorn Helgaas | c7dabef | 2009-10-27 13:26:47 -0600 | [diff] [blame] | 320 | struct resource *res; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 321 | struct pci_bus_region region; |
Yinghai Lu | 7cc5997 | 2009-12-22 15:02:21 -0800 | [diff] [blame] | 322 | u32 l, io_upper16; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 323 | |
| 324 | /* Set up the top and bottom of the PCI I/O segment for this bus. */ |
Bjorn Helgaas | c7dabef | 2009-10-27 13:26:47 -0600 | [diff] [blame] | 325 | res = bus->resource[0]; |
| 326 | pcibios_resource_to_bus(bridge, ®ion, res); |
| 327 | if (res->flags & IORESOURCE_IO) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 328 | pci_read_config_dword(bridge, PCI_IO_BASE, &l); |
| 329 | l &= 0xffff0000; |
| 330 | l |= (region.start >> 8) & 0x00f0; |
| 331 | l |= region.end & 0xf000; |
| 332 | /* Set up upper 16 bits of I/O base/limit. */ |
| 333 | io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); |
Bjorn Helgaas | c7dabef | 2009-10-27 13:26:47 -0600 | [diff] [blame] | 334 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
Yinghai Lu | 7cc5997 | 2009-12-22 15:02:21 -0800 | [diff] [blame] | 335 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 336 | /* Clear upper 16 bits of I/O base/limit. */ |
| 337 | io_upper16 = 0; |
| 338 | l = 0x00f0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 339 | } |
| 340 | /* Temporarily disable the I/O range before updating PCI_IO_BASE. */ |
| 341 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); |
| 342 | /* Update lower 16 bits of I/O base/limit. */ |
| 343 | pci_write_config_dword(bridge, PCI_IO_BASE, l); |
| 344 | /* Update upper 16 bits of I/O base/limit. */ |
| 345 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16); |
Yinghai Lu | 7cc5997 | 2009-12-22 15:02:21 -0800 | [diff] [blame] | 346 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 347 | |
Yinghai Lu | 7cc5997 | 2009-12-22 15:02:21 -0800 | [diff] [blame] | 348 | static void pci_setup_bridge_mmio(struct pci_bus *bus) |
| 349 | { |
| 350 | struct pci_dev *bridge = bus->self; |
| 351 | struct resource *res; |
| 352 | struct pci_bus_region region; |
| 353 | u32 l; |
| 354 | |
| 355 | /* Set up the top and bottom of the PCI Memory segment for this bus. */ |
Bjorn Helgaas | c7dabef | 2009-10-27 13:26:47 -0600 | [diff] [blame] | 356 | res = bus->resource[1]; |
| 357 | pcibios_resource_to_bus(bridge, ®ion, res); |
| 358 | if (res->flags & IORESOURCE_MEM) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 359 | l = (region.start >> 16) & 0xfff0; |
| 360 | l |= region.end & 0xfff00000; |
Bjorn Helgaas | c7dabef | 2009-10-27 13:26:47 -0600 | [diff] [blame] | 361 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
Yinghai Lu | 7cc5997 | 2009-12-22 15:02:21 -0800 | [diff] [blame] | 362 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 363 | l = 0x0000fff0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 364 | } |
| 365 | pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); |
Yinghai Lu | 7cc5997 | 2009-12-22 15:02:21 -0800 | [diff] [blame] | 366 | } |
| 367 | |
| 368 | static void pci_setup_bridge_mmio_pref(struct pci_bus *bus) |
| 369 | { |
| 370 | struct pci_dev *bridge = bus->self; |
| 371 | struct resource *res; |
| 372 | struct pci_bus_region region; |
| 373 | u32 l, bu, lu; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 374 | |
| 375 | /* Clear out the upper 32 bits of PREF limit. |
| 376 | If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily |
| 377 | disables PREF range, which is ok. */ |
| 378 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); |
| 379 | |
| 380 | /* Set up PREF base/limit. */ |
Benjamin Herrenschmidt | c40a22e | 2007-12-10 17:32:15 +1100 | [diff] [blame] | 381 | bu = lu = 0; |
Bjorn Helgaas | c7dabef | 2009-10-27 13:26:47 -0600 | [diff] [blame] | 382 | res = bus->resource[2]; |
| 383 | pcibios_resource_to_bus(bridge, ®ion, res); |
| 384 | if (res->flags & IORESOURCE_PREFETCH) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 385 | l = (region.start >> 16) & 0xfff0; |
| 386 | l |= region.end & 0xfff00000; |
Bjorn Helgaas | c7dabef | 2009-10-27 13:26:47 -0600 | [diff] [blame] | 387 | if (res->flags & IORESOURCE_MEM_64) { |
Yinghai Lu | 1f82de1 | 2009-04-23 20:48:32 -0700 | [diff] [blame] | 388 | bu = upper_32_bits(region.start); |
| 389 | lu = upper_32_bits(region.end); |
Yinghai Lu | 1f82de1 | 2009-04-23 20:48:32 -0700 | [diff] [blame] | 390 | } |
Bjorn Helgaas | c7dabef | 2009-10-27 13:26:47 -0600 | [diff] [blame] | 391 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
Yinghai Lu | 7cc5997 | 2009-12-22 15:02:21 -0800 | [diff] [blame] | 392 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 393 | l = 0x0000fff0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 394 | } |
| 395 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); |
| 396 | |
Alex Williamson | 59353ea | 2009-11-30 14:51:44 -0700 | [diff] [blame] | 397 | /* Set the upper 32 bits of PREF base & limit. */ |
| 398 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu); |
| 399 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu); |
Yinghai Lu | 7cc5997 | 2009-12-22 15:02:21 -0800 | [diff] [blame] | 400 | } |
| 401 | |
| 402 | static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type) |
| 403 | { |
| 404 | struct pci_dev *bridge = bus->self; |
| 405 | |
Yinghai Lu | 7cc5997 | 2009-12-22 15:02:21 -0800 | [diff] [blame] | 406 | dev_info(&bridge->dev, "PCI bridge to [bus %02x-%02x]\n", |
| 407 | bus->secondary, bus->subordinate); |
| 408 | |
| 409 | if (type & IORESOURCE_IO) |
| 410 | pci_setup_bridge_io(bus); |
| 411 | |
| 412 | if (type & IORESOURCE_MEM) |
| 413 | pci_setup_bridge_mmio(bus); |
| 414 | |
| 415 | if (type & IORESOURCE_PREFETCH) |
| 416 | pci_setup_bridge_mmio_pref(bus); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 417 | |
| 418 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl); |
| 419 | } |
| 420 | |
Yinghai Lu | 7cc5997 | 2009-12-22 15:02:21 -0800 | [diff] [blame] | 421 | static void pci_setup_bridge(struct pci_bus *bus) |
| 422 | { |
| 423 | unsigned long type = IORESOURCE_IO | IORESOURCE_MEM | |
| 424 | IORESOURCE_PREFETCH; |
| 425 | |
| 426 | __pci_setup_bridge(bus, type); |
| 427 | } |
| 428 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 429 | /* Check whether the bridge supports optional I/O and |
| 430 | prefetchable memory ranges. If not, the respective |
| 431 | base/limit registers must be read-only and read as 0. */ |
Sam Ravnborg | 96bde06 | 2007-03-26 21:53:30 -0800 | [diff] [blame] | 432 | static void pci_bridge_check_ranges(struct pci_bus *bus) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 433 | { |
| 434 | u16 io; |
| 435 | u32 pmem; |
| 436 | struct pci_dev *bridge = bus->self; |
| 437 | struct resource *b_res; |
| 438 | |
| 439 | b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; |
| 440 | b_res[1].flags |= IORESOURCE_MEM; |
| 441 | |
| 442 | pci_read_config_word(bridge, PCI_IO_BASE, &io); |
| 443 | if (!io) { |
| 444 | pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0); |
| 445 | pci_read_config_word(bridge, PCI_IO_BASE, &io); |
| 446 | pci_write_config_word(bridge, PCI_IO_BASE, 0x0); |
| 447 | } |
| 448 | if (io) |
| 449 | b_res[0].flags |= IORESOURCE_IO; |
| 450 | /* DECchip 21050 pass 2 errata: the bridge may miss an address |
| 451 | disconnect boundary by one PCI data phase. |
| 452 | Workaround: do not use prefetching on this device. */ |
| 453 | if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) |
| 454 | return; |
| 455 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); |
| 456 | if (!pmem) { |
| 457 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, |
| 458 | 0xfff0fff0); |
| 459 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); |
| 460 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); |
| 461 | } |
Yinghai Lu | 1f82de1 | 2009-04-23 20:48:32 -0700 | [diff] [blame] | 462 | if (pmem) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 463 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; |
Yinghai Lu | 9958610 | 2010-01-22 01:02:28 -0800 | [diff] [blame] | 464 | if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == |
| 465 | PCI_PREF_RANGE_TYPE_64) { |
Yinghai Lu | 1f82de1 | 2009-04-23 20:48:32 -0700 | [diff] [blame] | 466 | b_res[2].flags |= IORESOURCE_MEM_64; |
Yinghai Lu | 9958610 | 2010-01-22 01:02:28 -0800 | [diff] [blame] | 467 | b_res[2].flags |= PCI_PREF_RANGE_TYPE_64; |
| 468 | } |
Yinghai Lu | 1f82de1 | 2009-04-23 20:48:32 -0700 | [diff] [blame] | 469 | } |
| 470 | |
| 471 | /* double check if bridge does support 64 bit pref */ |
| 472 | if (b_res[2].flags & IORESOURCE_MEM_64) { |
| 473 | u32 mem_base_hi, tmp; |
| 474 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, |
| 475 | &mem_base_hi); |
| 476 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, |
| 477 | 0xffffffff); |
| 478 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); |
| 479 | if (!tmp) |
| 480 | b_res[2].flags &= ~IORESOURCE_MEM_64; |
| 481 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, |
| 482 | mem_base_hi); |
| 483 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 484 | } |
| 485 | |
| 486 | /* Helper function for sizing routines: find first available |
| 487 | bus resource of a given type. Note: we intentionally skip |
| 488 | the bus resources which have already been assigned (that is, |
| 489 | have non-NULL parent resource). */ |
Sam Ravnborg | 96bde06 | 2007-03-26 21:53:30 -0800 | [diff] [blame] | 490 | static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 491 | { |
| 492 | int i; |
| 493 | struct resource *r; |
| 494 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | |
| 495 | IORESOURCE_PREFETCH; |
| 496 | |
Bjorn Helgaas | 89a74ec | 2010-02-23 10:24:31 -0700 | [diff] [blame] | 497 | pci_bus_for_each_resource(bus, r, i) { |
Ivan Kokshaysky | 299de03 | 2005-06-15 18:59:27 +0400 | [diff] [blame] | 498 | if (r == &ioport_resource || r == &iomem_resource) |
| 499 | continue; |
Jesse Barnes | 55a1098 | 2009-10-27 09:39:18 -0700 | [diff] [blame] | 500 | if (r && (r->flags & type_mask) == type && !r->parent) |
| 501 | return r; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 502 | } |
| 503 | return NULL; |
| 504 | } |
| 505 | |
Ram Pai | 13583b1 | 2011-02-14 17:43:17 -0800 | [diff] [blame] | 506 | static resource_size_t calculate_iosize(resource_size_t size, |
| 507 | resource_size_t min_size, |
| 508 | resource_size_t size1, |
| 509 | resource_size_t old_size, |
| 510 | resource_size_t align) |
| 511 | { |
| 512 | if (size < min_size) |
| 513 | size = min_size; |
| 514 | if (old_size == 1 ) |
| 515 | old_size = 0; |
| 516 | /* To be fixed in 2.5: we should have sort of HAVE_ISA |
| 517 | flag in the struct pci_bus. */ |
| 518 | #if defined(CONFIG_ISA) || defined(CONFIG_EISA) |
| 519 | size = (size & 0xff) + ((size & ~0xffUL) << 2); |
| 520 | #endif |
| 521 | size = ALIGN(size + size1, align); |
| 522 | if (size < old_size) |
| 523 | size = old_size; |
| 524 | return size; |
| 525 | } |
| 526 | |
| 527 | static resource_size_t calculate_memsize(resource_size_t size, |
| 528 | resource_size_t min_size, |
| 529 | resource_size_t size1, |
| 530 | resource_size_t old_size, |
| 531 | resource_size_t align) |
| 532 | { |
| 533 | if (size < min_size) |
| 534 | size = min_size; |
| 535 | if (old_size == 1 ) |
| 536 | old_size = 0; |
| 537 | if (size < old_size) |
| 538 | size = old_size; |
| 539 | size = ALIGN(size + size1, align); |
| 540 | return size; |
| 541 | } |
| 542 | |
Yinghai Lu | be76891 | 2011-07-25 13:08:38 -0700 | [diff] [blame^] | 543 | static resource_size_t get_res_add_size(struct resource_list_x *add_head, |
| 544 | struct resource *res) |
| 545 | { |
| 546 | struct resource_list_x *list; |
| 547 | |
| 548 | /* check if it is in add_head list */ |
| 549 | for (list = add_head->next; list && list->res != res; |
| 550 | list = list->next); |
| 551 | if (list) |
| 552 | return list->add_size; |
| 553 | |
| 554 | return 0; |
| 555 | } |
| 556 | |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 557 | /** |
| 558 | * pbus_size_io() - size the io window of a given bus |
| 559 | * |
| 560 | * @bus : the bus |
| 561 | * @min_size : the minimum io window that must to be allocated |
| 562 | * @add_size : additional optional io window |
| 563 | * @add_head : track the additional io window on this list |
| 564 | * |
| 565 | * Sizing the IO windows of the PCI-PCI bridge is trivial, |
| 566 | * since these windows have 4K granularity and the IO ranges |
| 567 | * of non-bridge PCI devices are limited to 256 bytes. |
| 568 | * We must be careful with the ISA aliasing though. |
| 569 | */ |
| 570 | static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size, |
| 571 | resource_size_t add_size, struct resource_list_x *add_head) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 572 | { |
| 573 | struct pci_dev *dev; |
| 574 | struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO); |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 575 | unsigned long size = 0, size0 = 0, size1 = 0; |
Yinghai Lu | be76891 | 2011-07-25 13:08:38 -0700 | [diff] [blame^] | 576 | resource_size_t children_add_size = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 577 | |
| 578 | if (!b_res) |
| 579 | return; |
| 580 | |
| 581 | list_for_each_entry(dev, &bus->devices, bus_list) { |
| 582 | int i; |
| 583 | |
| 584 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { |
| 585 | struct resource *r = &dev->resource[i]; |
| 586 | unsigned long r_size; |
| 587 | |
| 588 | if (r->parent || !(r->flags & IORESOURCE_IO)) |
| 589 | continue; |
Zhao, Yu | 022edd8 | 2008-10-13 19:24:28 +0800 | [diff] [blame] | 590 | r_size = resource_size(r); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 591 | |
| 592 | if (r_size < 0x400) |
| 593 | /* Might be re-aligned for ISA */ |
| 594 | size += r_size; |
| 595 | else |
| 596 | size1 += r_size; |
Yinghai Lu | be76891 | 2011-07-25 13:08:38 -0700 | [diff] [blame^] | 597 | |
| 598 | if (add_head) |
| 599 | children_add_size += get_res_add_size(add_head, r); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 600 | } |
| 601 | } |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 602 | size0 = calculate_iosize(size, min_size, size1, |
Ram Pai | 13583b1 | 2011-02-14 17:43:17 -0800 | [diff] [blame] | 603 | resource_size(b_res), 4096); |
Yinghai Lu | be76891 | 2011-07-25 13:08:38 -0700 | [diff] [blame^] | 604 | if (children_add_size > add_size) |
| 605 | add_size = children_add_size; |
Yinghai Lu | 93d2175 | 2011-05-13 18:06:17 -0700 | [diff] [blame] | 606 | size1 = (!add_head || (add_head && !add_size)) ? size0 : |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 607 | calculate_iosize(size, min_size+add_size, size1, |
| 608 | resource_size(b_res), 4096); |
| 609 | if (!size0 && !size1) { |
Bjorn Helgaas | 865df57 | 2009-11-04 10:32:57 -0700 | [diff] [blame] | 610 | if (b_res->start || b_res->end) |
| 611 | dev_info(&bus->self->dev, "disabling bridge window " |
| 612 | "%pR to [bus %02x-%02x] (unused)\n", b_res, |
| 613 | bus->secondary, bus->subordinate); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 614 | b_res->flags = 0; |
| 615 | return; |
| 616 | } |
| 617 | /* Alignment of the IO window is always 4K */ |
| 618 | b_res->start = 4096; |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 619 | b_res->end = b_res->start + size0 - 1; |
Ivan Kokshaysky | 8845256 | 2008-03-30 19:50:14 +0400 | [diff] [blame] | 620 | b_res->flags |= IORESOURCE_STARTALIGN; |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 621 | if (size1 > size0 && add_head) |
| 622 | add_to_list(add_head, bus->self, b_res, size1-size0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 623 | } |
| 624 | |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 625 | /** |
| 626 | * pbus_size_mem() - size the memory window of a given bus |
| 627 | * |
| 628 | * @bus : the bus |
| 629 | * @min_size : the minimum memory window that must to be allocated |
| 630 | * @add_size : additional optional memory window |
| 631 | * @add_head : track the additional memory window on this list |
| 632 | * |
| 633 | * Calculate the size of the bus and minimal alignment which |
| 634 | * guarantees that all child resources fit in this size. |
| 635 | */ |
Eric W. Biederman | 2876048 | 2009-09-09 14:09:24 -0700 | [diff] [blame] | 636 | static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 637 | unsigned long type, resource_size_t min_size, |
| 638 | resource_size_t add_size, |
| 639 | struct resource_list_x *add_head) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 640 | { |
| 641 | struct pci_dev *dev; |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 642 | resource_size_t min_align, align, size, size0, size1; |
Benjamin Herrenschmidt | c40a22e | 2007-12-10 17:32:15 +1100 | [diff] [blame] | 643 | resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 644 | int order, max_order; |
| 645 | struct resource *b_res = find_free_bus_resource(bus, type); |
Yinghai Lu | 1f82de1 | 2009-04-23 20:48:32 -0700 | [diff] [blame] | 646 | unsigned int mem64_mask = 0; |
Yinghai Lu | be76891 | 2011-07-25 13:08:38 -0700 | [diff] [blame^] | 647 | resource_size_t children_add_size = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 648 | |
| 649 | if (!b_res) |
| 650 | return 0; |
| 651 | |
| 652 | memset(aligns, 0, sizeof(aligns)); |
| 653 | max_order = 0; |
| 654 | size = 0; |
| 655 | |
Yinghai Lu | 1f82de1 | 2009-04-23 20:48:32 -0700 | [diff] [blame] | 656 | mem64_mask = b_res->flags & IORESOURCE_MEM_64; |
| 657 | b_res->flags &= ~IORESOURCE_MEM_64; |
| 658 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 659 | list_for_each_entry(dev, &bus->devices, bus_list) { |
| 660 | int i; |
Yinghai Lu | 1f82de1 | 2009-04-23 20:48:32 -0700 | [diff] [blame] | 661 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 662 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { |
| 663 | struct resource *r = &dev->resource[i]; |
Benjamin Herrenschmidt | c40a22e | 2007-12-10 17:32:15 +1100 | [diff] [blame] | 664 | resource_size_t r_size; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 665 | |
| 666 | if (r->parent || (r->flags & mask) != type) |
| 667 | continue; |
Zhao, Yu | 022edd8 | 2008-10-13 19:24:28 +0800 | [diff] [blame] | 668 | r_size = resource_size(r); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 669 | /* For bridges size != alignment */ |
Chris Wright | 6faf17f | 2009-08-28 13:00:06 -0700 | [diff] [blame] | 670 | align = pci_resource_alignment(dev, r); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 671 | order = __ffs(align) - 20; |
| 672 | if (order > 11) { |
Bjorn Helgaas | 865df57 | 2009-11-04 10:32:57 -0700 | [diff] [blame] | 673 | dev_warn(&dev->dev, "disabling BAR %d: %pR " |
| 674 | "(bad alignment %#llx)\n", i, r, |
| 675 | (unsigned long long) align); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 676 | r->flags = 0; |
| 677 | continue; |
| 678 | } |
| 679 | size += r_size; |
| 680 | if (order < 0) |
| 681 | order = 0; |
| 682 | /* Exclude ranges with size > align from |
| 683 | calculation of the alignment. */ |
| 684 | if (r_size == align) |
| 685 | aligns[order] += align; |
| 686 | if (order > max_order) |
| 687 | max_order = order; |
Yinghai Lu | 1f82de1 | 2009-04-23 20:48:32 -0700 | [diff] [blame] | 688 | mem64_mask &= r->flags & IORESOURCE_MEM_64; |
Yinghai Lu | be76891 | 2011-07-25 13:08:38 -0700 | [diff] [blame^] | 689 | |
| 690 | if (add_head) |
| 691 | children_add_size += get_res_add_size(add_head, r); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 692 | } |
| 693 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 694 | align = 0; |
| 695 | min_align = 0; |
| 696 | for (order = 0; order <= max_order; order++) { |
Jeremy Fitzhardinge | 8308c54 | 2008-09-11 01:31:50 -0700 | [diff] [blame] | 697 | resource_size_t align1 = 1; |
| 698 | |
| 699 | align1 <<= (order + 20); |
| 700 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 701 | if (!align) |
| 702 | min_align = align1; |
Milind Arun Choudhary | 6f6f8c2 | 2007-07-09 11:55:51 -0700 | [diff] [blame] | 703 | else if (ALIGN(align + min_align, min_align) < align1) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 704 | min_align = align1 >> 1; |
| 705 | align += aligns[order]; |
| 706 | } |
Linus Torvalds | b42282e | 2011-04-11 10:53:11 -0700 | [diff] [blame] | 707 | size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align); |
Yinghai Lu | be76891 | 2011-07-25 13:08:38 -0700 | [diff] [blame^] | 708 | if (children_add_size > add_size) |
| 709 | add_size = children_add_size; |
Yinghai Lu | 93d2175 | 2011-05-13 18:06:17 -0700 | [diff] [blame] | 710 | size1 = (!add_head || (add_head && !add_size)) ? size0 : |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 711 | calculate_memsize(size, min_size+add_size, 0, |
Linus Torvalds | b42282e | 2011-04-11 10:53:11 -0700 | [diff] [blame] | 712 | resource_size(b_res), min_align); |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 713 | if (!size0 && !size1) { |
Bjorn Helgaas | 865df57 | 2009-11-04 10:32:57 -0700 | [diff] [blame] | 714 | if (b_res->start || b_res->end) |
| 715 | dev_info(&bus->self->dev, "disabling bridge window " |
| 716 | "%pR to [bus %02x-%02x] (unused)\n", b_res, |
| 717 | bus->secondary, bus->subordinate); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 718 | b_res->flags = 0; |
| 719 | return 1; |
| 720 | } |
| 721 | b_res->start = min_align; |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 722 | b_res->end = size0 + min_align - 1; |
| 723 | b_res->flags |= IORESOURCE_STARTALIGN | mem64_mask; |
| 724 | if (size1 > size0 && add_head) |
| 725 | add_to_list(add_head, bus->self, b_res, size1-size0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 726 | return 1; |
| 727 | } |
| 728 | |
Adrian Bunk | 5468ae6 | 2008-04-18 13:53:56 -0700 | [diff] [blame] | 729 | static void pci_bus_size_cardbus(struct pci_bus *bus) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 730 | { |
| 731 | struct pci_dev *bridge = bus->self; |
| 732 | struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; |
| 733 | u16 ctrl; |
| 734 | |
| 735 | /* |
| 736 | * Reserve some resources for CardBus. We reserve |
| 737 | * a fixed amount of bus space for CardBus bridges. |
| 738 | */ |
Linus Torvalds | 934b702 | 2008-04-22 18:16:30 -0700 | [diff] [blame] | 739 | b_res[0].start = 0; |
| 740 | b_res[0].end = pci_cardbus_io_size - 1; |
| 741 | b_res[0].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 742 | |
Linus Torvalds | 934b702 | 2008-04-22 18:16:30 -0700 | [diff] [blame] | 743 | b_res[1].start = 0; |
| 744 | b_res[1].end = pci_cardbus_io_size - 1; |
| 745 | b_res[1].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 746 | |
| 747 | /* |
| 748 | * Check whether prefetchable memory is supported |
| 749 | * by this bridge. |
| 750 | */ |
| 751 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); |
| 752 | if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { |
| 753 | ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; |
| 754 | pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); |
| 755 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); |
| 756 | } |
| 757 | |
| 758 | /* |
| 759 | * If we have prefetchable memory support, allocate |
| 760 | * two regions. Otherwise, allocate one region of |
| 761 | * twice the size. |
| 762 | */ |
| 763 | if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { |
Linus Torvalds | 934b702 | 2008-04-22 18:16:30 -0700 | [diff] [blame] | 764 | b_res[2].start = 0; |
| 765 | b_res[2].end = pci_cardbus_mem_size - 1; |
| 766 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_SIZEALIGN; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 767 | |
Linus Torvalds | 934b702 | 2008-04-22 18:16:30 -0700 | [diff] [blame] | 768 | b_res[3].start = 0; |
| 769 | b_res[3].end = pci_cardbus_mem_size - 1; |
| 770 | b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 771 | } else { |
Linus Torvalds | 934b702 | 2008-04-22 18:16:30 -0700 | [diff] [blame] | 772 | b_res[3].start = 0; |
| 773 | b_res[3].end = pci_cardbus_mem_size * 2 - 1; |
| 774 | b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 775 | } |
| 776 | } |
| 777 | |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 778 | void __ref __pci_bus_size_bridges(struct pci_bus *bus, |
| 779 | struct resource_list_x *add_head) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 780 | { |
| 781 | struct pci_dev *dev; |
| 782 | unsigned long mask, prefmask; |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 783 | resource_size_t additional_mem_size = 0, additional_io_size = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 784 | |
| 785 | list_for_each_entry(dev, &bus->devices, bus_list) { |
| 786 | struct pci_bus *b = dev->subordinate; |
| 787 | if (!b) |
| 788 | continue; |
| 789 | |
| 790 | switch (dev->class >> 8) { |
| 791 | case PCI_CLASS_BRIDGE_CARDBUS: |
| 792 | pci_bus_size_cardbus(b); |
| 793 | break; |
| 794 | |
| 795 | case PCI_CLASS_BRIDGE_PCI: |
| 796 | default: |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 797 | __pci_bus_size_bridges(b, add_head); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 798 | break; |
| 799 | } |
| 800 | } |
| 801 | |
| 802 | /* The root bus? */ |
| 803 | if (!bus->self) |
| 804 | return; |
| 805 | |
| 806 | switch (bus->self->class >> 8) { |
| 807 | case PCI_CLASS_BRIDGE_CARDBUS: |
| 808 | /* don't size cardbuses yet. */ |
| 809 | break; |
| 810 | |
| 811 | case PCI_CLASS_BRIDGE_PCI: |
| 812 | pci_bridge_check_ranges(bus); |
Eric W. Biederman | 2876048 | 2009-09-09 14:09:24 -0700 | [diff] [blame] | 813 | if (bus->self->is_hotplug_bridge) { |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 814 | additional_io_size = pci_hotplug_io_size; |
| 815 | additional_mem_size = pci_hotplug_mem_size; |
Eric W. Biederman | 2876048 | 2009-09-09 14:09:24 -0700 | [diff] [blame] | 816 | } |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 817 | /* |
| 818 | * Follow thru |
| 819 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 820 | default: |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 821 | pbus_size_io(bus, 0, additional_io_size, add_head); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 822 | /* If the bridge supports prefetchable range, size it |
| 823 | separately. If it doesn't, or its prefetchable window |
| 824 | has already been allocated by arch code, try |
| 825 | non-prefetchable range for both types of PCI memory |
| 826 | resources. */ |
| 827 | mask = IORESOURCE_MEM; |
| 828 | prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH; |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 829 | if (pbus_size_mem(bus, prefmask, prefmask, 0, additional_mem_size, add_head)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 830 | mask = prefmask; /* Success, size non-prefetch only. */ |
Eric W. Biederman | 2876048 | 2009-09-09 14:09:24 -0700 | [diff] [blame] | 831 | else |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 832 | additional_mem_size += additional_mem_size; |
| 833 | pbus_size_mem(bus, mask, IORESOURCE_MEM, 0, additional_mem_size, add_head); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 834 | break; |
| 835 | } |
| 836 | } |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 837 | |
| 838 | void __ref pci_bus_size_bridges(struct pci_bus *bus) |
| 839 | { |
| 840 | __pci_bus_size_bridges(bus, NULL); |
| 841 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 842 | EXPORT_SYMBOL(pci_bus_size_bridges); |
| 843 | |
Yinghai Lu | 568ddef | 2010-01-22 01:02:21 -0800 | [diff] [blame] | 844 | static void __ref __pci_bus_assign_resources(const struct pci_bus *bus, |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 845 | struct resource_list_x *add_head, |
Yinghai Lu | 568ddef | 2010-01-22 01:02:21 -0800 | [diff] [blame] | 846 | struct resource_list_x *fail_head) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 847 | { |
| 848 | struct pci_bus *b; |
| 849 | struct pci_dev *dev; |
| 850 | |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 851 | pbus_assign_resources_sorted(bus, add_head, fail_head); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 852 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 853 | list_for_each_entry(dev, &bus->devices, bus_list) { |
| 854 | b = dev->subordinate; |
| 855 | if (!b) |
| 856 | continue; |
| 857 | |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 858 | __pci_bus_assign_resources(b, add_head, fail_head); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 859 | |
| 860 | switch (dev->class >> 8) { |
| 861 | case PCI_CLASS_BRIDGE_PCI: |
Yinghai Lu | 6841ec6 | 2010-01-22 01:02:25 -0800 | [diff] [blame] | 862 | if (!pci_is_enabled(dev)) |
| 863 | pci_setup_bridge(b); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 864 | break; |
| 865 | |
| 866 | case PCI_CLASS_BRIDGE_CARDBUS: |
| 867 | pci_setup_cardbus(b); |
| 868 | break; |
| 869 | |
| 870 | default: |
Bjorn Helgaas | 80ccba1 | 2008-06-13 10:52:11 -0600 | [diff] [blame] | 871 | dev_info(&dev->dev, "not setting up bridge for bus " |
| 872 | "%04x:%02x\n", pci_domain_nr(b), b->number); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 873 | break; |
| 874 | } |
| 875 | } |
| 876 | } |
Yinghai Lu | 568ddef | 2010-01-22 01:02:21 -0800 | [diff] [blame] | 877 | |
| 878 | void __ref pci_bus_assign_resources(const struct pci_bus *bus) |
| 879 | { |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 880 | __pci_bus_assign_resources(bus, NULL, NULL); |
Yinghai Lu | 568ddef | 2010-01-22 01:02:21 -0800 | [diff] [blame] | 881 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 882 | EXPORT_SYMBOL(pci_bus_assign_resources); |
| 883 | |
Yinghai Lu | 6841ec6 | 2010-01-22 01:02:25 -0800 | [diff] [blame] | 884 | static void __ref __pci_bridge_assign_resources(const struct pci_dev *bridge, |
| 885 | struct resource_list_x *fail_head) |
| 886 | { |
| 887 | struct pci_bus *b; |
| 888 | |
| 889 | pdev_assign_resources_sorted((struct pci_dev *)bridge, fail_head); |
| 890 | |
| 891 | b = bridge->subordinate; |
| 892 | if (!b) |
| 893 | return; |
| 894 | |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 895 | __pci_bus_assign_resources(b, NULL, fail_head); |
Yinghai Lu | 6841ec6 | 2010-01-22 01:02:25 -0800 | [diff] [blame] | 896 | |
| 897 | switch (bridge->class >> 8) { |
| 898 | case PCI_CLASS_BRIDGE_PCI: |
| 899 | pci_setup_bridge(b); |
| 900 | break; |
| 901 | |
| 902 | case PCI_CLASS_BRIDGE_CARDBUS: |
| 903 | pci_setup_cardbus(b); |
| 904 | break; |
| 905 | |
| 906 | default: |
| 907 | dev_info(&bridge->dev, "not setting up bridge for bus " |
| 908 | "%04x:%02x\n", pci_domain_nr(b), b->number); |
| 909 | break; |
| 910 | } |
| 911 | } |
Yinghai Lu | 5009b46 | 2010-01-22 01:02:20 -0800 | [diff] [blame] | 912 | static void pci_bridge_release_resources(struct pci_bus *bus, |
| 913 | unsigned long type) |
| 914 | { |
| 915 | int idx; |
| 916 | bool changed = false; |
| 917 | struct pci_dev *dev; |
| 918 | struct resource *r; |
| 919 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | |
| 920 | IORESOURCE_PREFETCH; |
| 921 | |
| 922 | dev = bus->self; |
| 923 | for (idx = PCI_BRIDGE_RESOURCES; idx <= PCI_BRIDGE_RESOURCE_END; |
| 924 | idx++) { |
| 925 | r = &dev->resource[idx]; |
| 926 | if ((r->flags & type_mask) != type) |
| 927 | continue; |
| 928 | if (!r->parent) |
| 929 | continue; |
| 930 | /* |
| 931 | * if there are children under that, we should release them |
| 932 | * all |
| 933 | */ |
| 934 | release_child_resources(r); |
| 935 | if (!release_resource(r)) { |
| 936 | dev_printk(KERN_DEBUG, &dev->dev, |
| 937 | "resource %d %pR released\n", idx, r); |
| 938 | /* keep the old size */ |
| 939 | r->end = resource_size(r) - 1; |
| 940 | r->start = 0; |
| 941 | r->flags = 0; |
| 942 | changed = true; |
| 943 | } |
| 944 | } |
| 945 | |
| 946 | if (changed) { |
| 947 | /* avoiding touch the one without PREF */ |
| 948 | if (type & IORESOURCE_PREFETCH) |
| 949 | type = IORESOURCE_PREFETCH; |
| 950 | __pci_setup_bridge(bus, type); |
| 951 | } |
| 952 | } |
| 953 | |
| 954 | enum release_type { |
| 955 | leaf_only, |
| 956 | whole_subtree, |
| 957 | }; |
| 958 | /* |
| 959 | * try to release pci bridge resources that is from leaf bridge, |
| 960 | * so we can allocate big new one later |
| 961 | */ |
| 962 | static void __ref pci_bus_release_bridge_resources(struct pci_bus *bus, |
| 963 | unsigned long type, |
| 964 | enum release_type rel_type) |
| 965 | { |
| 966 | struct pci_dev *dev; |
| 967 | bool is_leaf_bridge = true; |
| 968 | |
| 969 | list_for_each_entry(dev, &bus->devices, bus_list) { |
| 970 | struct pci_bus *b = dev->subordinate; |
| 971 | if (!b) |
| 972 | continue; |
| 973 | |
| 974 | is_leaf_bridge = false; |
| 975 | |
| 976 | if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) |
| 977 | continue; |
| 978 | |
| 979 | if (rel_type == whole_subtree) |
| 980 | pci_bus_release_bridge_resources(b, type, |
| 981 | whole_subtree); |
| 982 | } |
| 983 | |
| 984 | if (pci_is_root_bus(bus)) |
| 985 | return; |
| 986 | |
| 987 | if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI) |
| 988 | return; |
| 989 | |
| 990 | if ((rel_type == whole_subtree) || is_leaf_bridge) |
| 991 | pci_bridge_release_resources(bus, type); |
| 992 | } |
| 993 | |
Yinghai Lu | 76fbc26 | 2008-06-23 20:33:06 +0200 | [diff] [blame] | 994 | static void pci_bus_dump_res(struct pci_bus *bus) |
| 995 | { |
Bjorn Helgaas | 89a74ec | 2010-02-23 10:24:31 -0700 | [diff] [blame] | 996 | struct resource *res; |
| 997 | int i; |
Yinghai Lu | 76fbc26 | 2008-06-23 20:33:06 +0200 | [diff] [blame] | 998 | |
Bjorn Helgaas | 89a74ec | 2010-02-23 10:24:31 -0700 | [diff] [blame] | 999 | pci_bus_for_each_resource(bus, res, i) { |
Yinghai Lu | 7c9342b | 2009-12-22 15:02:24 -0800 | [diff] [blame] | 1000 | if (!res || !res->end || !res->flags) |
Yinghai Lu | 76fbc26 | 2008-06-23 20:33:06 +0200 | [diff] [blame] | 1001 | continue; |
| 1002 | |
Bjorn Helgaas | c7dabef | 2009-10-27 13:26:47 -0600 | [diff] [blame] | 1003 | dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res); |
Yinghai Lu | 76fbc26 | 2008-06-23 20:33:06 +0200 | [diff] [blame] | 1004 | } |
| 1005 | } |
| 1006 | |
| 1007 | static void pci_bus_dump_resources(struct pci_bus *bus) |
| 1008 | { |
| 1009 | struct pci_bus *b; |
| 1010 | struct pci_dev *dev; |
| 1011 | |
| 1012 | |
| 1013 | pci_bus_dump_res(bus); |
| 1014 | |
| 1015 | list_for_each_entry(dev, &bus->devices, bus_list) { |
| 1016 | b = dev->subordinate; |
| 1017 | if (!b) |
| 1018 | continue; |
| 1019 | |
| 1020 | pci_bus_dump_resources(b); |
| 1021 | } |
| 1022 | } |
| 1023 | |
Yinghai Lu | da7822e | 2011-05-12 17:11:37 -0700 | [diff] [blame] | 1024 | static int __init pci_bus_get_depth(struct pci_bus *bus) |
| 1025 | { |
| 1026 | int depth = 0; |
| 1027 | struct pci_dev *dev; |
| 1028 | |
| 1029 | list_for_each_entry(dev, &bus->devices, bus_list) { |
| 1030 | int ret; |
| 1031 | struct pci_bus *b = dev->subordinate; |
| 1032 | if (!b) |
| 1033 | continue; |
| 1034 | |
| 1035 | ret = pci_bus_get_depth(b); |
| 1036 | if (ret + 1 > depth) |
| 1037 | depth = ret + 1; |
| 1038 | } |
| 1039 | |
| 1040 | return depth; |
| 1041 | } |
| 1042 | static int __init pci_get_max_depth(void) |
| 1043 | { |
| 1044 | int depth = 0; |
| 1045 | struct pci_bus *bus; |
| 1046 | |
| 1047 | list_for_each_entry(bus, &pci_root_buses, node) { |
| 1048 | int ret; |
| 1049 | |
| 1050 | ret = pci_bus_get_depth(bus); |
| 1051 | if (ret > depth) |
| 1052 | depth = ret; |
| 1053 | } |
| 1054 | |
| 1055 | return depth; |
| 1056 | } |
| 1057 | |
Ram Pai | f483d39 | 2011-07-07 11:19:10 -0700 | [diff] [blame] | 1058 | |
Yinghai Lu | da7822e | 2011-05-12 17:11:37 -0700 | [diff] [blame] | 1059 | /* |
| 1060 | * first try will not touch pci bridge res |
| 1061 | * second and later try will clear small leaf bridge res |
| 1062 | * will stop till to the max deepth if can not find good one |
| 1063 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1064 | void __init |
| 1065 | pci_assign_unassigned_resources(void) |
| 1066 | { |
| 1067 | struct pci_bus *bus; |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 1068 | struct resource_list_x add_list; /* list of resources that |
| 1069 | want additional resources */ |
Yinghai Lu | da7822e | 2011-05-12 17:11:37 -0700 | [diff] [blame] | 1070 | int tried_times = 0; |
| 1071 | enum release_type rel_type = leaf_only; |
| 1072 | struct resource_list_x head, *list; |
| 1073 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | |
| 1074 | IORESOURCE_PREFETCH; |
| 1075 | unsigned long failed_type; |
| 1076 | int max_depth = pci_get_max_depth(); |
| 1077 | int pci_try_num; |
| 1078 | |
| 1079 | |
| 1080 | head.next = NULL; |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 1081 | add_list.next = NULL; |
Yinghai Lu | da7822e | 2011-05-12 17:11:37 -0700 | [diff] [blame] | 1082 | |
| 1083 | pci_try_num = max_depth + 1; |
| 1084 | printk(KERN_DEBUG "PCI: max bus depth: %d pci_try_num: %d\n", |
| 1085 | max_depth, pci_try_num); |
| 1086 | |
| 1087 | again: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1088 | /* Depth first, calculate sizes and alignments of all |
| 1089 | subordinate buses. */ |
Yinghai Lu | da7822e | 2011-05-12 17:11:37 -0700 | [diff] [blame] | 1090 | list_for_each_entry(bus, &pci_root_buses, node) |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 1091 | __pci_bus_size_bridges(bus, &add_list); |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 1092 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1093 | /* Depth last, allocate resources and update the hardware. */ |
Yinghai Lu | da7822e | 2011-05-12 17:11:37 -0700 | [diff] [blame] | 1094 | list_for_each_entry(bus, &pci_root_buses, node) |
| 1095 | __pci_bus_assign_resources(bus, &add_list, &head); |
Ram Pai | c8adf9a | 2011-02-14 17:43:20 -0800 | [diff] [blame] | 1096 | BUG_ON(add_list.next); |
Yinghai Lu | da7822e | 2011-05-12 17:11:37 -0700 | [diff] [blame] | 1097 | tried_times++; |
| 1098 | |
| 1099 | /* any device complain? */ |
| 1100 | if (!head.next) |
| 1101 | goto enable_and_dump; |
Ram Pai | f483d39 | 2011-07-07 11:19:10 -0700 | [diff] [blame] | 1102 | |
| 1103 | /* don't realloc if asked to do so */ |
| 1104 | if (!pci_realloc_enabled()) { |
| 1105 | free_list(resource_list_x, &head); |
| 1106 | goto enable_and_dump; |
| 1107 | } |
| 1108 | |
Yinghai Lu | da7822e | 2011-05-12 17:11:37 -0700 | [diff] [blame] | 1109 | failed_type = 0; |
| 1110 | for (list = head.next; list;) { |
| 1111 | failed_type |= list->flags; |
| 1112 | list = list->next; |
| 1113 | } |
| 1114 | /* |
| 1115 | * io port are tight, don't try extra |
| 1116 | * or if reach the limit, don't want to try more |
| 1117 | */ |
| 1118 | failed_type &= type_mask; |
| 1119 | if ((failed_type == IORESOURCE_IO) || (tried_times >= pci_try_num)) { |
| 1120 | free_list(resource_list_x, &head); |
| 1121 | goto enable_and_dump; |
| 1122 | } |
| 1123 | |
| 1124 | printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n", |
| 1125 | tried_times + 1); |
| 1126 | |
| 1127 | /* third times and later will not check if it is leaf */ |
| 1128 | if ((tried_times + 1) > 2) |
| 1129 | rel_type = whole_subtree; |
| 1130 | |
| 1131 | /* |
| 1132 | * Try to release leaf bridge's resources that doesn't fit resource of |
| 1133 | * child device under that bridge |
| 1134 | */ |
| 1135 | for (list = head.next; list;) { |
| 1136 | bus = list->dev->bus; |
| 1137 | pci_bus_release_bridge_resources(bus, list->flags & type_mask, |
| 1138 | rel_type); |
| 1139 | list = list->next; |
| 1140 | } |
| 1141 | /* restore size and flags */ |
| 1142 | for (list = head.next; list;) { |
| 1143 | struct resource *res = list->res; |
| 1144 | |
| 1145 | res->start = list->start; |
| 1146 | res->end = list->end; |
| 1147 | res->flags = list->flags; |
| 1148 | if (list->dev->subordinate) |
| 1149 | res->flags = 0; |
| 1150 | |
| 1151 | list = list->next; |
| 1152 | } |
| 1153 | free_list(resource_list_x, &head); |
| 1154 | |
| 1155 | goto again; |
| 1156 | |
| 1157 | enable_and_dump: |
| 1158 | /* Depth last, update the hardware. */ |
| 1159 | list_for_each_entry(bus, &pci_root_buses, node) |
| 1160 | pci_enable_bridges(bus); |
Yinghai Lu | 76fbc26 | 2008-06-23 20:33:06 +0200 | [diff] [blame] | 1161 | |
| 1162 | /* dump the resource on buses */ |
Yinghai Lu | da7822e | 2011-05-12 17:11:37 -0700 | [diff] [blame] | 1163 | list_for_each_entry(bus, &pci_root_buses, node) |
Yinghai Lu | 76fbc26 | 2008-06-23 20:33:06 +0200 | [diff] [blame] | 1164 | pci_bus_dump_resources(bus); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1165 | } |
Yinghai Lu | 6841ec6 | 2010-01-22 01:02:25 -0800 | [diff] [blame] | 1166 | |
| 1167 | void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge) |
| 1168 | { |
| 1169 | struct pci_bus *parent = bridge->subordinate; |
Yinghai Lu | 32180e4 | 2010-01-22 01:02:27 -0800 | [diff] [blame] | 1170 | int tried_times = 0; |
| 1171 | struct resource_list_x head, *list; |
Yinghai Lu | 6841ec6 | 2010-01-22 01:02:25 -0800 | [diff] [blame] | 1172 | int retval; |
Yinghai Lu | 32180e4 | 2010-01-22 01:02:27 -0800 | [diff] [blame] | 1173 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | |
| 1174 | IORESOURCE_PREFETCH; |
Yinghai Lu | 6841ec6 | 2010-01-22 01:02:25 -0800 | [diff] [blame] | 1175 | |
Yinghai Lu | 32180e4 | 2010-01-22 01:02:27 -0800 | [diff] [blame] | 1176 | head.next = NULL; |
| 1177 | |
| 1178 | again: |
Yinghai Lu | 6841ec6 | 2010-01-22 01:02:25 -0800 | [diff] [blame] | 1179 | pci_bus_size_bridges(parent); |
Yinghai Lu | 32180e4 | 2010-01-22 01:02:27 -0800 | [diff] [blame] | 1180 | __pci_bridge_assign_resources(bridge, &head); |
Yinghai Lu | 32180e4 | 2010-01-22 01:02:27 -0800 | [diff] [blame] | 1181 | |
| 1182 | tried_times++; |
| 1183 | |
| 1184 | if (!head.next) |
Yinghai Lu | 3f579c3 | 2010-05-21 14:35:06 -0700 | [diff] [blame] | 1185 | goto enable_all; |
Yinghai Lu | 32180e4 | 2010-01-22 01:02:27 -0800 | [diff] [blame] | 1186 | |
| 1187 | if (tried_times >= 2) { |
| 1188 | /* still fail, don't need to try more */ |
Ram Pai | 094732a | 2011-02-14 17:43:18 -0800 | [diff] [blame] | 1189 | free_list(resource_list_x, &head); |
Yinghai Lu | 3f579c3 | 2010-05-21 14:35:06 -0700 | [diff] [blame] | 1190 | goto enable_all; |
Yinghai Lu | 32180e4 | 2010-01-22 01:02:27 -0800 | [diff] [blame] | 1191 | } |
| 1192 | |
| 1193 | printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n", |
| 1194 | tried_times + 1); |
| 1195 | |
| 1196 | /* |
| 1197 | * Try to release leaf bridge's resources that doesn't fit resource of |
| 1198 | * child device under that bridge |
| 1199 | */ |
| 1200 | for (list = head.next; list;) { |
| 1201 | struct pci_bus *bus = list->dev->bus; |
| 1202 | unsigned long flags = list->flags; |
| 1203 | |
| 1204 | pci_bus_release_bridge_resources(bus, flags & type_mask, |
| 1205 | whole_subtree); |
| 1206 | list = list->next; |
| 1207 | } |
| 1208 | /* restore size and flags */ |
| 1209 | for (list = head.next; list;) { |
| 1210 | struct resource *res = list->res; |
| 1211 | |
| 1212 | res->start = list->start; |
| 1213 | res->end = list->end; |
| 1214 | res->flags = list->flags; |
| 1215 | if (list->dev->subordinate) |
| 1216 | res->flags = 0; |
| 1217 | |
| 1218 | list = list->next; |
| 1219 | } |
Ram Pai | 094732a | 2011-02-14 17:43:18 -0800 | [diff] [blame] | 1220 | free_list(resource_list_x, &head); |
Yinghai Lu | 32180e4 | 2010-01-22 01:02:27 -0800 | [diff] [blame] | 1221 | |
| 1222 | goto again; |
Yinghai Lu | 3f579c3 | 2010-05-21 14:35:06 -0700 | [diff] [blame] | 1223 | |
| 1224 | enable_all: |
| 1225 | retval = pci_reenable_device(bridge); |
| 1226 | pci_set_master(bridge); |
| 1227 | pci_enable_bridges(parent); |
Yinghai Lu | 6841ec6 | 2010-01-22 01:02:25 -0800 | [diff] [blame] | 1228 | } |
| 1229 | EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources); |