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gerrit-public.fairphone.software / fp2-dev / kernel / msm / acd4b715ec83e451990bb82bdbf28ecaeab1b67d / . / arch / powerpc / boot / dts / mpc8544ds.dts
blob: 921f9f6848ea0b0530863e5e09aa55e24f4d91ba [file] [log] [blame]
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]1/*
2 * MPC8544 DS Device Tree Source
3 *
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]12/dts-v1/;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]13/ {
14 model = "MPC8544DS";
15 compatible = "MPC8544DS", "MPC85xxDS";
16 #address-cells = <1>;
17 #size-cells = <1>;
18
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]19 aliases {
20 ethernet0 = &enet0;
21 ethernet1 = &enet1;
22 serial0 = &serial0;
23 serial1 = &serial1;
24 pci0 = &pci0;
25 pci1 = &pci1;
26 pci2 = &pci2;
27 pci3 = &pci3;
28 };
29
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]30 cpus {
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]31 #address-cells = <1>;
32 #size-cells = <0>;
33
34 PowerPC,8544@0 {
35 device_type = "cpu";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]36 reg = <0x0>;
37 d-cache-line-size = <32>; // 32 bytes
38 i-cache-line-size = <32>; // 32 bytes
39 d-cache-size = <0x8000>; // L1, 32K
40 i-cache-size = <0x8000>; // L1, 32K
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]41 timebase-frequency = <0>;
42 bus-frequency = <0>;
43 clock-frequency = <0>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]44 };
45 };
46
47 memory {
48 device_type = "memory";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]49 reg = <0x0 0x0>; // Filled by U-Boot
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]50 };
51
52 soc8544@e0000000 {
53 #address-cells = <1>;
54 #size-cells = <1>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]55 device_type = "soc";
Kumar Galab66510c2007-08-16 23:55:55 -0500[diff] [blame]56
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]57 ranges = <0x0 0xe0000000 0x100000>;
58 reg = <0xe0000000 0x1000>; // CCSRBAR 1M
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]59 bus-frequency = <0>; // Filled out by uboot.
60
Kumar Gala4da421d2007-05-15 13:20:05 -0500[diff] [blame]61 memory-controller@2000 {
62 compatible = "fsl,8544-memory-controller";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]63 reg = <0x2000 0x1000>;
Kumar Gala4da421d2007-05-15 13:20:05 -0500[diff] [blame]64 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]65 interrupts = <18 2>;
Kumar Gala4da421d2007-05-15 13:20:05 -0500[diff] [blame]66 };
67
68 l2-cache-controller@20000 {
69 compatible = "fsl,8544-l2-cache-controller";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]70 reg = <0x20000 0x1000>;
71 cache-line-size = <32>; // 32 bytes
72 cache-size = <0x40000>; // L2, 256K
Kumar Gala4da421d2007-05-15 13:20:05 -0500[diff] [blame]73 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]74 interrupts = <16 2>;
Kumar Gala4da421d2007-05-15 13:20:05 -0500[diff] [blame]75 };
76
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]77 i2c@3000 {
Kumar Galaec9686c2007-12-11 23:17:24 -0600[diff] [blame]78 #address-cells = <1>;
79 #size-cells = <0>;
80 cell-index = <0>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]81 compatible = "fsl-i2c";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]82 reg = <0x3000 0x100>;
83 interrupts = <43 2>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]84 interrupt-parent = <&mpic>;
85 dfsrr;
86 };
87
Kumar Galaec9686c2007-12-11 23:17:24 -0600[diff] [blame]88 i2c@3100 {
89 #address-cells = <1>;
90 #size-cells = <0>;
91 cell-index = <1>;
92 compatible = "fsl-i2c";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]93 reg = <0x3100 0x100>;
94 interrupts = <43 2>;
Kumar Galaec9686c2007-12-11 23:17:24 -0600[diff] [blame]95 interrupt-parent = <&mpic>;
96 dfsrr;
97 };
98
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]99 mdio@24520 {
100 #address-cells = <1>;
101 #size-cells = <0>;
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]102 compatible = "fsl,gianfar-mdio";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]103 reg = <0x24520 0x20>;
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]104
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]105 phy0: ethernet-phy@0 {
106 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]107 interrupts = <10 1>;
108 reg = <0x0>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]109 device_type = "ethernet-phy";
110 };
111 phy1: ethernet-phy@1 {
112 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]113 interrupts = <10 1>;
114 reg = <0x1>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]115 device_type = "ethernet-phy";
116 };
117 };
118
Sebastian Siewior1028d4f2008-03-15 00:01:30 +0100[diff] [blame]119 dma@21300 {
120 #address-cells = <1>;
121 #size-cells = <1>;
122 compatible = "fsl,mpc8544-dma", "fsl,eloplus-dma";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]123 reg = <0x21300 0x4>;
124 ranges = <0x0 0x21100 0x200>;
Sebastian Siewior1028d4f2008-03-15 00:01:30 +0100[diff] [blame]125 cell-index = <0>;
126 dma-channel@0 {
127 compatible = "fsl,mpc8544-dma-channel",
128 "fsl,eloplus-dma-channel";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]129 reg = <0x0 0x80>;
Sebastian Siewior1028d4f2008-03-15 00:01:30 +0100[diff] [blame]130 cell-index = <0>;
131 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]132 interrupts = <20 2>;
Sebastian Siewior1028d4f2008-03-15 00:01:30 +0100[diff] [blame]133 };
134 dma-channel@80 {
135 compatible = "fsl,mpc8544-dma-channel",
136 "fsl,eloplus-dma-channel";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]137 reg = <0x80 0x80>;
Sebastian Siewior1028d4f2008-03-15 00:01:30 +0100[diff] [blame]138 cell-index = <1>;
139 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]140 interrupts = <21 2>;
Sebastian Siewior1028d4f2008-03-15 00:01:30 +0100[diff] [blame]141 };
142 dma-channel@100 {
143 compatible = "fsl,mpc8544-dma-channel",
144 "fsl,eloplus-dma-channel";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]145 reg = <0x100 0x80>;
Sebastian Siewior1028d4f2008-03-15 00:01:30 +0100[diff] [blame]146 cell-index = <2>;
147 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]148 interrupts = <22 2>;
Sebastian Siewior1028d4f2008-03-15 00:01:30 +0100[diff] [blame]149 };
150 dma-channel@180 {
151 compatible = "fsl,mpc8544-dma-channel",
152 "fsl,eloplus-dma-channel";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]153 reg = <0x180 0x80>;
Sebastian Siewior1028d4f2008-03-15 00:01:30 +0100[diff] [blame]154 cell-index = <3>;
155 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]156 interrupts = <23 2>;
Sebastian Siewior1028d4f2008-03-15 00:01:30 +0100[diff] [blame]157 };
158 };
159
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]160 enet0: ethernet@24000 {
161 cell-index = <0>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]162 device_type = "network";
163 model = "TSEC";
164 compatible = "gianfar";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]165 reg = <0x24000 0x1000>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]166 local-mac-address = [ 00 00 00 00 00 00 ];
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]167 interrupts = <29 2 30 2 34 2>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]168 interrupt-parent = <&mpic>;
169 phy-handle = <&phy0>;
Kumar Gala9a9bcf42007-07-26 00:07:36 -0500[diff] [blame]170 phy-connection-type = "rgmii-id";
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]171 };
172
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]173 enet1: ethernet@26000 {
174 cell-index = <1>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]175 device_type = "network";
176 model = "TSEC";
177 compatible = "gianfar";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]178 reg = <0x26000 0x1000>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]179 local-mac-address = [ 00 00 00 00 00 00 ];
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]180 interrupts = <31 2 32 2 33 2>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]181 interrupt-parent = <&mpic>;
182 phy-handle = <&phy1>;
Kumar Gala9a9bcf42007-07-26 00:07:36 -0500[diff] [blame]183 phy-connection-type = "rgmii-id";
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]184 };
185
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]186 serial0: serial@4500 {
187 cell-index = <0>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]188 device_type = "serial";
189 compatible = "ns16550";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]190 reg = <0x4500 0x100>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]191 clock-frequency = <0>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]192 interrupts = <42 2>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]193 interrupt-parent = <&mpic>;
194 };
195
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]196 serial1: serial@4600 {
197 cell-index = <1>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]198 device_type = "serial";
199 compatible = "ns16550";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]200 reg = <0x4600 0x100>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]201 clock-frequency = <0>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]202 interrupts = <42 2>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]203 interrupt-parent = <&mpic>;
204 };
205
Roy Zang10ce8c62007-07-13 17:35:33 +0800[diff] [blame]206 global-utilities@e0000 { //global utilities block
207 compatible = "fsl,mpc8548-guts";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]208 reg = <0xe0000 0x1000>;
Roy Zang10ce8c62007-07-13 17:35:33 +0800[diff] [blame]209 fsl,has-rstcr;
210 };
211
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]212 mpic: pic@40000 {
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]213 interrupt-controller;
214 #address-cells = <0>;
215 #interrupt-cells = <2>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]216 reg = <0x40000 0x40000>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]217 compatible = "chrp,open-pic";
218 device_type = "open-pic";
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]219 };
Jason Jin741edc42008-05-23 16:32:48 +0800[diff] [blame]220
221 msi@41600 {
222 compatible = "fsl,mpc8544-msi", "fsl,mpic-msi";
223 reg = <0x41600 0x80>;
224 msi-available-ranges = <0 0x100>;
225 interrupts = <
226 0xe0 0
227 0xe1 0
228 0xe2 0
229 0xe3 0
230 0xe4 0
231 0xe5 0
232 0xe6 0
233 0xe7 0>;
234 interrupt-parent = <&mpic>;
235 };
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]236 };
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]237
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]238 pci0: pci@e0008000 {
239 cell-index = <0>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]240 compatible = "fsl,mpc8540-pci";
241 device_type = "pci";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]242 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]243 interrupt-map = <
244
245 /* IDSEL 0x11 J17 Slot 1 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]246 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
247 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
248 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
249 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]250
251 /* IDSEL 0x12 J16 Slot 2 */
252
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]253 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
254 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
255 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
256 0x9000 0x0 0x0 0x4 &mpic 0x1 0x1>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]257
258 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]259 interrupts = <24 2>;
260 bus-range = <0 255>;
261 ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
262 0x1000000 0x0 0x0 0xe1000000 0x0 0x10000>;
263 clock-frequency = <66666666>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]264 #interrupt-cells = <1>;
265 #size-cells = <2>;
266 #address-cells = <3>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]267 reg = <0xe0008000 0x1000>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]268 };
269
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]270 pci1: pcie@e0009000 {
271 cell-index = <1>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]272 compatible = "fsl,mpc8548-pcie";
273 device_type = "pci";
274 #interrupt-cells = <1>;
275 #size-cells = <2>;
276 #address-cells = <3>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]277 reg = <0xe0009000 0x1000>;
278 bus-range = <0 255>;
279 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
280 0x1000000 0x0 0x0 0xe1010000 0x0 0x10000>;
281 clock-frequency = <33333333>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]282 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]283 interrupts = <26 2>;
284 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]285 interrupt-map = <
286 /* IDSEL 0x0 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]287 0000 0x0 0x0 0x1 &mpic 0x4 0x1
288 0000 0x0 0x0 0x2 &mpic 0x5 0x1
289 0000 0x0 0x0 0x3 &mpic 0x6 0x1
290 0000 0x0 0x0 0x4 &mpic 0x7 0x1
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]291 >;
292 pcie@0 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]293 reg = <0x0 0x0 0x0 0x0 0x0>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]294 #size-cells = <2>;
295 #address-cells = <3>;
296 device_type = "pci";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]297 ranges = <0x2000000 0x0 0x80000000
298 0x2000000 0x0 0x80000000
299 0x0 0x20000000
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]300
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]301 0x1000000 0x0 0x0
302 0x1000000 0x0 0x0
303 0x0 0x10000>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]304 };
305 };
306
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]307 pci2: pcie@e000a000 {
308 cell-index = <2>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]309 compatible = "fsl,mpc8548-pcie";
310 device_type = "pci";
311 #interrupt-cells = <1>;
312 #size-cells = <2>;
313 #address-cells = <3>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]314 reg = <0xe000a000 0x1000>;
315 bus-range = <0 255>;
316 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
317 0x1000000 0x0 0x0 0xe1020000 0x0 0x10000>;
318 clock-frequency = <33333333>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]319 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]320 interrupts = <25 2>;
321 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]322 interrupt-map = <
323 /* IDSEL 0x0 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]324 0000 0x0 0x0 0x1 &mpic 0x0 0x1
325 0000 0x0 0x0 0x2 &mpic 0x1 0x1
326 0000 0x0 0x0 0x3 &mpic 0x2 0x1
327 0000 0x0 0x0 0x4 &mpic 0x3 0x1
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]328 >;
329 pcie@0 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]330 reg = <0x0 0x0 0x0 0x0 0x0>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]331 #size-cells = <2>;
332 #address-cells = <3>;
333 device_type = "pci";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]334 ranges = <0x2000000 0x0 0xa0000000
335 0x2000000 0x0 0xa0000000
336 0x0 0x10000000
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]337
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]338 0x1000000 0x0 0x0
339 0x1000000 0x0 0x0
340 0x0 0x10000>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]341 };
342 };
343
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]344 pci3: pcie@e000b000 {
345 cell-index = <3>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]346 compatible = "fsl,mpc8548-pcie";
347 device_type = "pci";
348 #interrupt-cells = <1>;
349 #size-cells = <2>;
350 #address-cells = <3>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]351 reg = <0xe000b000 0x1000>;
352 bus-range = <0 255>;
353 ranges = <0x2000000 0x0 0xb0000000 0xb0000000 0x0 0x100000
354 0x1000000 0x0 0x0 0xb0100000 0x0 0x100000>;
355 clock-frequency = <33333333>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]356 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]357 interrupts = <27 2>;
358 interrupt-map-mask = <0xff00 0x0 0x0 0x1>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]359 interrupt-map = <
360 // IDSEL 0x1c USB
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]361 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
362 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
363 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
364 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]365
366 // IDSEL 0x1d Audio
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]367 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]368
369 // IDSEL 0x1e Legacy
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]370 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
371 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]372
373 // IDSEL 0x1f IDE/SATA
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]374 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
375 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]376 >;
377
378 pcie@0 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]379 reg = <0x0 0x0 0x0 0x0 0x0>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]380 #size-cells = <2>;
381 #address-cells = <3>;
382 device_type = "pci";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]383 ranges = <0x2000000 0x0 0xb0000000
384 0x2000000 0x0 0xb0000000
385 0x0 0x100000
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]386
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]387 0x1000000 0x0 0x0
388 0x1000000 0x0 0x0
389 0x0 0x100000>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]390
391 uli1575@0 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]392 reg = <0x0 0x0 0x0 0x0 0x0>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]393 #size-cells = <2>;
394 #address-cells = <3>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]395 ranges = <0x2000000 0x0 0xb0000000
396 0x2000000 0x0 0xb0000000
397 0x0 0x100000
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]398
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]399 0x1000000 0x0 0x0
400 0x1000000 0x0 0x0
401 0x0 0x100000>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]402 isa@1e {
403 device_type = "isa";
404 #interrupt-cells = <2>;
405 #size-cells = <1>;
406 #address-cells = <2>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]407 reg = <0xf000 0x0 0x0 0x0 0x0>;
408 ranges = <0x1 0x0
409 0x1000000 0x0 0x0
410 0x1000>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]411 interrupt-parent = <&i8259>;
412
413 i8259: interrupt-controller@20 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]414 reg = <0x1 0x20 0x2
415 0x1 0xa0 0x2
416 0x1 0x4d0 0x2>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]417 interrupt-controller;
418 device_type = "interrupt-controller";
419 #address-cells = <0>;
420 #interrupt-cells = <2>;
421 compatible = "chrp,iic";
422 interrupts = <9 2>;
423 interrupt-parent = <&mpic>;
424 };
425
426 i8042@60 {
427 #size-cells = <0>;
428 #address-cells = <1>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]429 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
430 interrupts = <1 3 12 3>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]431 interrupt-parent = <&i8259>;
432
433 keyboard@0 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]434 reg = <0x0>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]435 compatible = "pnpPNP,303";
436 };
437
438 mouse@1 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]439 reg = <0x1>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]440 compatible = "pnpPNP,f03";
441 };
442 };
443
444 rtc@70 {
445 compatible = "pnpPNP,b00";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]446 reg = <0x1 0x70 0x2>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]447 };
448
449 gpio@400 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]450 reg = <0x1 0x400 0x80>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]451 };
452 };
453 };
454 };
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]455 };
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]456};