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gerrit-public.fairphone.software / fp2-dev / kernel / msm / acd4b715ec83e451990bb82bdbf28ecaeab1b67d / . / arch / powerpc / boot / dts / mpc8548cds.dts
blob: 213c88e5aee801c7483ef76c092b651c59f3d5ed [file] [log] [blame]
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]1/*
Roy Zang02edff52007-07-10 18:46:47 +0800[diff] [blame]2 * MPC8548 CDS Device Tree Source
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]3 *
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]4 * Copyright 2006, 2008 Freescale Semiconductor Inc.
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]12/dts-v1/;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]13
14/ {
15 model = "MPC8548CDS";
Kumar Gala52094872007-02-17 16:04:23 -0600[diff] [blame]16 compatible = "MPC8548CDS", "MPC85xxCDS";
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]17 #address-cells = <1>;
18 #size-cells = <1>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]19
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23/*
24 ethernet2 = &enet2;
25 ethernet3 = &enet3;
26*/
27 serial0 = &serial0;
28 serial1 = &serial1;
29 pci0 = &pci0;
30 pci1 = &pci1;
31 pci2 = &pci2;
32 };
33
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]34 cpus {
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]35 #address-cells = <1>;
36 #size-cells = <0>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]37
38 PowerPC,8548@0 {
39 device_type = "cpu";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]40 reg = <0x0>;
41 d-cache-line-size = <32>; // 32 bytes
42 i-cache-line-size = <32>; // 32 bytes
43 d-cache-size = <0x8000>; // L1, 32K
44 i-cache-size = <0x8000>; // L1, 32K
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]45 timebase-frequency = <0>; // 33 MHz, from uboot
46 bus-frequency = <0>; // 166 MHz
47 clock-frequency = <0>; // 825 MHz, from uboot
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]48 };
49 };
50
51 memory {
52 device_type = "memory";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]53 reg = <0x0 0x8000000>; // 128M at 0x0
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]54 };
55
56 soc8548@e0000000 {
57 #address-cells = <1>;
58 #size-cells = <1>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]59 device_type = "soc";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]60 ranges = <0x0 0xe0000000 0x100000>;
61 reg = <0xe0000000 0x1000>; // CCSRBAR
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]62 bus-frequency = <0>;
63
Dave Jiang50cf6702007-05-10 10:03:05 -0700[diff] [blame]64 memory-controller@2000 {
65 compatible = "fsl,8548-memory-controller";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]66 reg = <0x2000 0x1000>;
Dave Jiang50cf6702007-05-10 10:03:05 -0700[diff] [blame]67 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]68 interrupts = <18 2>;
Dave Jiang50cf6702007-05-10 10:03:05 -0700[diff] [blame]69 };
70
71 l2-cache-controller@20000 {
72 compatible = "fsl,8548-l2-cache-controller";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]73 reg = <0x20000 0x1000>;
74 cache-line-size = <32>; // 32 bytes
75 cache-size = <0x80000>; // L2, 512K
Dave Jiang50cf6702007-05-10 10:03:05 -0700[diff] [blame]76 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]77 interrupts = <16 2>;
Dave Jiang50cf6702007-05-10 10:03:05 -0700[diff] [blame]78 };
79
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]80 i2c@3000 {
Kumar Galaec9686c2007-12-11 23:17:24 -0600[diff] [blame]81 #address-cells = <1>;
82 #size-cells = <0>;
83 cell-index = <0>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]84 compatible = "fsl-i2c";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]85 reg = <0x3000 0x100>;
86 interrupts = <43 2>;
Kumar Gala52094872007-02-17 16:04:23 -0600[diff] [blame]87 interrupt-parent = <&mpic>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]88 dfsrr;
89 };
90
Kumar Galaec9686c2007-12-11 23:17:24 -0600[diff] [blame]91 i2c@3100 {
92 #address-cells = <1>;
93 #size-cells = <0>;
94 cell-index = <1>;
95 compatible = "fsl-i2c";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]96 reg = <0x3100 0x100>;
97 interrupts = <43 2>;
Kumar Galaec9686c2007-12-11 23:17:24 -0600[diff] [blame]98 interrupt-parent = <&mpic>;
99 dfsrr;
100 };
101
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]102 mdio@24520 {
103 #address-cells = <1>;
104 #size-cells = <0>;
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]105 compatible = "fsl,gianfar-mdio";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]106 reg = <0x24520 0x20>;
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]107
Kumar Gala52094872007-02-17 16:04:23 -0600[diff] [blame]108 phy0: ethernet-phy@0 {
109 interrupt-parent = <&mpic>;
Kumar Gala58fe2552007-07-03 03:05:58 -0500[diff] [blame]110 interrupts = <5 1>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]111 reg = <0x0>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]112 device_type = "ethernet-phy";
113 };
Kumar Gala52094872007-02-17 16:04:23 -0600[diff] [blame]114 phy1: ethernet-phy@1 {
115 interrupt-parent = <&mpic>;
Kumar Gala58fe2552007-07-03 03:05:58 -0500[diff] [blame]116 interrupts = <5 1>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]117 reg = <0x1>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]118 device_type = "ethernet-phy";
119 };
Kumar Gala52094872007-02-17 16:04:23 -0600[diff] [blame]120 phy2: ethernet-phy@2 {
121 interrupt-parent = <&mpic>;
Kumar Gala58fe2552007-07-03 03:05:58 -0500[diff] [blame]122 interrupts = <5 1>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]123 reg = <0x2>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]124 device_type = "ethernet-phy";
125 };
Kumar Gala52094872007-02-17 16:04:23 -0600[diff] [blame]126 phy3: ethernet-phy@3 {
127 interrupt-parent = <&mpic>;
Kumar Gala58fe2552007-07-03 03:05:58 -0500[diff] [blame]128 interrupts = <5 1>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]129 reg = <0x3>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]130 device_type = "ethernet-phy";
131 };
132 };
133
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]134 enet0: ethernet@24000 {
135 cell-index = <0>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]136 device_type = "network";
137 model = "eTSEC";
138 compatible = "gianfar";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]139 reg = <0x24000 0x1000>;
Timur Tabieae98262007-06-22 14:33:15 -0500[diff] [blame]140 local-mac-address = [ 00 00 00 00 00 00 ];
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]141 interrupts = <29 2 30 2 34 2>;
Kumar Gala52094872007-02-17 16:04:23 -0600[diff] [blame]142 interrupt-parent = <&mpic>;
143 phy-handle = <&phy0>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]144 };
145
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]146 enet1: ethernet@25000 {
147 cell-index = <1>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]148 device_type = "network";
149 model = "eTSEC";
150 compatible = "gianfar";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]151 reg = <0x25000 0x1000>;
Timur Tabieae98262007-06-22 14:33:15 -0500[diff] [blame]152 local-mac-address = [ 00 00 00 00 00 00 ];
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]153 interrupts = <35 2 36 2 40 2>;
Kumar Gala52094872007-02-17 16:04:23 -0600[diff] [blame]154 interrupt-parent = <&mpic>;
155 phy-handle = <&phy1>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]156 };
157
Kumar Gala52094872007-02-17 16:04:23 -0600[diff] [blame]158/* eTSEC 3/4 are currently broken
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]159 enet2: ethernet@26000 {
160 cell-index = <2>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]161 device_type = "network";
162 model = "eTSEC";
163 compatible = "gianfar";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]164 reg = <0x26000 0x1000>;
Timur Tabieae98262007-06-22 14:33:15 -0500[diff] [blame]165 local-mac-address = [ 00 00 00 00 00 00 ];
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]166 interrupts = <31 2 32 2 33 2>;
Kumar Gala52094872007-02-17 16:04:23 -0600[diff] [blame]167 interrupt-parent = <&mpic>;
168 phy-handle = <&phy2>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]169 };
170
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]171 enet3: ethernet@27000 {
172 cell-index = <3>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]173 device_type = "network";
174 model = "eTSEC";
175 compatible = "gianfar";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]176 reg = <0x27000 0x1000>;
Timur Tabieae98262007-06-22 14:33:15 -0500[diff] [blame]177 local-mac-address = [ 00 00 00 00 00 00 ];
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]178 interrupts = <37 2 38 2 39 2>;
Kumar Gala52094872007-02-17 16:04:23 -0600[diff] [blame]179 interrupt-parent = <&mpic>;
180 phy-handle = <&phy3>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]181 };
182 */
183
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]184 serial0: serial@4500 {
185 cell-index = <0>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]186 device_type = "serial";
187 compatible = "ns16550";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]188 reg = <0x4500 0x100>; // reg base, size
Randy Vinson6af01252007-07-17 16:37:12 -0700[diff] [blame]189 clock-frequency = <0>; // should we fill in in uboot?
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]190 interrupts = <42 2>;
Kumar Gala52094872007-02-17 16:04:23 -0600[diff] [blame]191 interrupt-parent = <&mpic>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]192 };
193
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]194 serial1: serial@4600 {
195 cell-index = <1>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]196 device_type = "serial";
197 compatible = "ns16550";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]198 reg = <0x4600 0x100>; // reg base, size
Randy Vinson6af01252007-07-17 16:37:12 -0700[diff] [blame]199 clock-frequency = <0>; // should we fill in in uboot?
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]200 interrupts = <42 2>;
Kumar Gala52094872007-02-17 16:04:23 -0600[diff] [blame]201 interrupt-parent = <&mpic>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]202 };
203
Roy Zang68fb0d22007-06-13 17:13:42 +0800[diff] [blame]204 global-utilities@e0000 { //global utilities reg
205 compatible = "fsl,mpc8548-guts";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]206 reg = <0xe0000 0x1000>;
Roy Zang68fb0d22007-06-13 17:13:42 +0800[diff] [blame]207 fsl,has-rstcr;
208 };
209
Kumar Gala52094872007-02-17 16:04:23 -0600[diff] [blame]210 mpic: pic@40000 {
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]211 interrupt-controller;
212 #address-cells = <0>;
213 #interrupt-cells = <2>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]214 reg = <0x40000 0x40000>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]215 compatible = "chrp,open-pic";
216 device_type = "open-pic";
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]217 };
218 };
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]219
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]220 pci0: pci@e0008000 {
221 cell-index = <0>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]222 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]223 interrupt-map = <
224 /* IDSEL 0x4 (PCIX Slot 2) */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]225 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
226 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
227 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
228 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]229
230 /* IDSEL 0x5 (PCIX Slot 3) */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]231 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
232 0x2800 0x0 0x0 0x2 &mpic 0x2 0x1
233 0x2800 0x0 0x0 0x3 &mpic 0x3 0x1
234 0x2800 0x0 0x0 0x4 &mpic 0x0 0x1
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]235
236 /* IDSEL 0x6 (PCIX Slot 4) */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]237 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
238 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
239 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
240 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]241
242 /* IDSEL 0x8 (PCIX Slot 5) */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]243 0x4000 0x0 0x0 0x1 &mpic 0x0 0x1
244 0x4000 0x0 0x0 0x2 &mpic 0x1 0x1
245 0x4000 0x0 0x0 0x3 &mpic 0x2 0x1
246 0x4000 0x0 0x0 0x4 &mpic 0x3 0x1
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]247
248 /* IDSEL 0xC (Tsi310 bridge) */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]249 0x6000 0x0 0x0 0x1 &mpic 0x0 0x1
250 0x6000 0x0 0x0 0x2 &mpic 0x1 0x1
251 0x6000 0x0 0x0 0x3 &mpic 0x2 0x1
252 0x6000 0x0 0x0 0x4 &mpic 0x3 0x1
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]253
254 /* IDSEL 0x14 (Slot 2) */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]255 0xa000 0x0 0x0 0x1 &mpic 0x0 0x1
256 0xa000 0x0 0x0 0x2 &mpic 0x1 0x1
257 0xa000 0x0 0x0 0x3 &mpic 0x2 0x1
258 0xa000 0x0 0x0 0x4 &mpic 0x3 0x1
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]259
260 /* IDSEL 0x15 (Slot 3) */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]261 0xa800 0x0 0x0 0x1 &mpic 0x1 0x1
262 0xa800 0x0 0x0 0x2 &mpic 0x2 0x1
263 0xa800 0x0 0x0 0x3 &mpic 0x3 0x1
264 0xa800 0x0 0x0 0x4 &mpic 0x0 0x1
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]265
266 /* IDSEL 0x16 (Slot 4) */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]267 0xb000 0x0 0x0 0x1 &mpic 0x2 0x1
268 0xb000 0x0 0x0 0x2 &mpic 0x3 0x1
269 0xb000 0x0 0x0 0x3 &mpic 0x0 0x1
270 0xb000 0x0 0x0 0x4 &mpic 0x1 0x1
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]271
272 /* IDSEL 0x18 (Slot 5) */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]273 0xc000 0x0 0x0 0x1 &mpic 0x0 0x1
274 0xc000 0x0 0x0 0x2 &mpic 0x1 0x1
275 0xc000 0x0 0x0 0x3 &mpic 0x2 0x1
276 0xc000 0x0 0x0 0x4 &mpic 0x3 0x1
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]277
278 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]279 0xe000 0x0 0x0 0x1 &mpic 0x0 0x1
280 0xe000 0x0 0x0 0x2 &mpic 0x1 0x1
281 0xe000 0x0 0x0 0x3 &mpic 0x2 0x1
282 0xe000 0x0 0x0 0x4 &mpic 0x3 0x1>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]283
284 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]285 interrupts = <24 2>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]286 bus-range = <0 0>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]287 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
288 0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
289 clock-frequency = <66666666>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]290 #interrupt-cells = <1>;
291 #size-cells = <2>;
292 #address-cells = <3>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]293 reg = <0xe0008000 0x1000>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]294 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
295 device_type = "pci";
296
297 pci_bridge@1c {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]298 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]299 interrupt-map = <
300
301 /* IDSEL 0x00 (PrPMC Site) */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]302 0000 0x0 0x0 0x1 &mpic 0x0 0x1
303 0000 0x0 0x0 0x2 &mpic 0x1 0x1
304 0000 0x0 0x0 0x3 &mpic 0x2 0x1
305 0000 0x0 0x0 0x4 &mpic 0x3 0x1
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]306
307 /* IDSEL 0x04 (VIA chip) */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]308 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
309 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
310 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
311 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]312
313 /* IDSEL 0x05 (8139) */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]314 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]315
316 /* IDSEL 0x06 (Slot 6) */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]317 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
318 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
319 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
320 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]321
322 /* IDESL 0x07 (Slot 7) */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]323 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1
324 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1
325 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1
326 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]327
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]328 reg = <0xe000 0x0 0x0 0x0 0x0>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]329 #interrupt-cells = <1>;
330 #size-cells = <2>;
331 #address-cells = <3>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]332 ranges = <0x2000000 0x0 0x80000000
333 0x2000000 0x0 0x80000000
334 0x0 0x20000000
335 0x1000000 0x0 0x0
336 0x1000000 0x0 0x0
337 0x0 0x80000>;
338 clock-frequency = <33333333>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]339
340 isa@4 {
341 device_type = "isa";
342 #interrupt-cells = <2>;
343 #size-cells = <1>;
344 #address-cells = <2>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]345 reg = <0x2000 0x0 0x0 0x0 0x0>;
346 ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]347 interrupt-parent = <&i8259>;
348
349 i8259: interrupt-controller@20 {
350 interrupt-controller;
351 device_type = "interrupt-controller";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]352 reg = <0x1 0x20 0x2
353 0x1 0xa0 0x2
354 0x1 0x4d0 0x2>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]355 #address-cells = <0>;
356 #interrupt-cells = <2>;
357 compatible = "chrp,iic";
358 interrupts = <0 1>;
359 interrupt-parent = <&mpic>;
360 };
361
362 rtc@70 {
363 compatible = "pnpPNP,b00";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]364 reg = <0x1 0x70 0x2>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]365 };
366 };
367 };
368 };
369
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]370 pci1: pci@e0009000 {
371 cell-index = <1>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]372 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]373 interrupt-map = <
374
375 /* IDSEL 0x15 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]376 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
377 0xa800 0x0 0x0 0x2 &mpic 0x1 0x1
378 0xa800 0x0 0x0 0x3 &mpic 0x2 0x1
379 0xa800 0x0 0x0 0x4 &mpic 0x3 0x1>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]380
381 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]382 interrupts = <25 2>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]383 bus-range = <0 0>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]384 ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
385 0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
386 clock-frequency = <66666666>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]387 #interrupt-cells = <1>;
388 #size-cells = <2>;
389 #address-cells = <3>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]390 reg = <0xe0009000 0x1000>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]391 compatible = "fsl,mpc8540-pci";
392 device_type = "pci";
393 };
394
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]395 pci2: pcie@e000a000 {
396 cell-index = <2>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]397 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]398 interrupt-map = <
399
400 /* IDSEL 0x0 (PEX) */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]401 00000 0x0 0x0 0x1 &mpic 0x0 0x1
402 00000 0x0 0x0 0x2 &mpic 0x1 0x1
403 00000 0x0 0x0 0x3 &mpic 0x2 0x1
404 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]405
406 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]407 interrupts = <26 2>;
408 bus-range = <0 255>;
409 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
410 0x1000000 0x0 0x0 0xe3000000 0x0 0x8000000>;
411 clock-frequency = <33333333>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]412 #interrupt-cells = <1>;
413 #size-cells = <2>;
414 #address-cells = <3>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]415 reg = <0xe000a000 0x1000>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]416 compatible = "fsl,mpc8548-pcie";
417 device_type = "pci";
418 pcie@0 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]419 reg = <0x0 0x0 0x0 0x0 0x0>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]420 #size-cells = <2>;
421 #address-cells = <3>;
422 device_type = "pci";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]423 ranges = <0x2000000 0x0 0xa0000000
424 0x2000000 0x0 0xa0000000
425 0x0 0x20000000
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]426
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]427 0x1000000 0x0 0x0
428 0x1000000 0x0 0x0
429 0x0 0x8000000>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]430 };
431 };
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]432};