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gerrit-public.fairphone.software / fp2-dev / kernel / msm / c13e9e9544bd88da4f1a38fcedf416e0fab871e4 / . / arch / arm / boot / dts / msm8974-gpu.dtsi
blob: 2751d765d3a56ee0912c6972d52bd79cc9ed78a8 [file] [log] [blame]
Vladimir Razgulin20df89c2012-12-19 15:16:47 -0700[diff] [blame]1/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
Pu Chen1335e872012-08-01 08:45:25 -0600[diff] [blame]2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12/ {
Jordan Crousec13e9e92013-01-29 10:13:36 -0700[diff] [blame^]13 msm_gpu: qcom,kgsl-3d0@fdb00000 {
Pu Chen1335e872012-08-01 08:45:25 -0600[diff] [blame]14 label = "kgsl-3d0";
15 compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
Harsh Vardhan Dwivedi623b9a22012-10-28 20:54:17 -0600[diff] [blame]16 reg = <0xfdb00000 0x10000
17 0xfdb20000 0x10000>;
18 reg-names = "kgsl_3d0_reg_memory" , "kgsl_3d0_shader_memory";
Pu Chen1335e872012-08-01 08:45:25 -0600[diff] [blame]19 interrupts = <0 33 0>;
20 interrupt-names = "kgsl_3d0_irq";
21 qcom,id = <0>;
22
23 qcom,chipid = <0x03030000>;
24
25 qcom,initial-pwrlevel = <1>;
26
Vladimir Razgulin20df89c2012-12-19 15:16:47 -0700[diff] [blame]27 qcom,idle-timeout = <8>; //<HZ/12>
Pu Chen1335e872012-08-01 08:45:25 -0600[diff] [blame]28 qcom,nap-allowed = <1>;
Harsh Vardhan Dwivedi41588242012-08-29 18:49:57 -0600[diff] [blame]29 qcom,strtstp-sleepwake;
Harsh Vardhan Dwivedicb067ec2012-10-08 16:41:10 -0600[diff] [blame]30 qcom,clk-map = <0x0000006>; //KGSL_CLK_CORE | KGSL_CLK_IFACE
Pu Chen1335e872012-08-01 08:45:25 -0600[diff] [blame]31
32 /* Bus Scale Settings */
Gagan Macb2372ae2012-08-20 19:24:32 -0600[diff] [blame]33 qcom,msm-bus,name = "grp3d";
34 qcom,msm-bus,num-cases = <4>;
35 qcom,msm-bus,active-only = <0>;
36 qcom,msm-bus,num-paths = <2>;
37 qcom,msm-bus,vectors-KBps =
38 <26 512 0 0>, <89 604 0 0>,
Lucille Sylvesterfa9bbae2012-12-05 16:04:59 -0700[diff] [blame]39 <26 512 0 1600000>, <89 604 0 3000000>,
40 <26 512 0 4000000>, <89 604 0 4500000>,
Gagan Macb2372ae2012-08-20 19:24:32 -0600[diff] [blame]41 <26 512 0 6400000>, <89 604 0 7600000>;
Pu Chen1335e872012-08-01 08:45:25 -0600[diff] [blame]42
43 /* GDSC oxili regulators */
44 vddcx-supply = <&gdsc_oxili_cx>;
45 vdd-supply = <&gdsc_oxili_gx>;
46
47 /* Power levels */
48
49 /* IOMMU Data */
50 iommu = <&kgsl_iommu>;
51
52 qcom,gpu-pwrlevels {
53 #address-cells = <1>;
54 #size-cells = <0>;
55
56 compatible = "qcom,gpu-pwrlevels";
57
58 qcom,gpu-pwrlevel@0 {
59 reg = <0>;
Alex Wongcadb9e42012-09-07 21:50:07 -0700[diff] [blame]60 qcom,gpu-freq = <450000000>;
Pu Chen1335e872012-08-01 08:45:25 -0600[diff] [blame]61 qcom,bus-freq = <3>;
62 qcom,io-fraction = <0>;
63 };
64
65 qcom,gpu-pwrlevel@1 {
66 reg = <1>;
Alex Wongcadb9e42012-09-07 21:50:07 -0700[diff] [blame]67 qcom,gpu-freq = <300000000>;
Pu Chen1335e872012-08-01 08:45:25 -0600[diff] [blame]68 qcom,bus-freq = <2>;
69 qcom,io-fraction = <33>;
70 };
71
72 qcom,gpu-pwrlevel@2 {
73 reg = <2>;
74 qcom,gpu-freq = <200000000>;
75 qcom,bus-freq = <1>;
76 qcom,io-fraction = <100>;
77 };
78
79 qcom,gpu-pwrlevel@3 {
80 reg = <3>;
81 qcom,gpu-freq = <27000000>;
82 qcom,bus-freq = <0>;
83 qcom,io-fraction = <0>;
84 };
85 };
86
87 qcom,dcvs-core-info {
88 #address-cells = <1>;
89 #size-cells = <0>;
90
91 compatible = "qcom,dcvs-core-info";
92
Abhijeet Dharmapurikarfc7dca42012-08-26 18:27:53 -0700[diff] [blame]93 qcom,num-cores = <1>;
94 qcom,sensors = <0>;
95
Abhijeet Dharmapurikar44451662012-08-23 18:58:44 -0700[diff] [blame]96 qcom,core-core-type = <1>;
97
98 qcom,algo-disable-pc-threshold = <0>;
99 qcom,algo-em-win-size-min-us = <100000>;
100 qcom,algo-em-win-size-max-us = <300000>;
Pu Chen1335e872012-08-01 08:45:25 -0600[diff] [blame]101 qcom,algo-em-max-util-pct = <97>;
Abhijeet Dharmapurikar44451662012-08-23 18:58:44 -0700[diff] [blame]102 qcom,algo-group-id = <95>;
103 qcom,algo-max-freq-chg-time-us = <100000>;
104 qcom,algo-slack-mode-dynamic = <100000>;
105 qcom,algo-slack-weight-thresh-pct = <0>;
106 qcom,algo-slack-time-min-us = <39000>;
107 qcom,algo-slack-time-max-us = <39000>;
108 qcom,algo-ss-win-size-min-us = <1000000>;
109 qcom,algo-ss-win-size-max-us = <1000000>;
110 qcom,algo-ss-util-pct = <95>;
Steve Mucklee8c6d612012-12-06 14:31:00 -0800[diff] [blame]111 qcom,algo-ss-no-corr-below-freq = <0>;
Pu Chen1335e872012-08-01 08:45:25 -0600[diff] [blame]112
Abhijeet Dharmapurikar44451662012-08-23 18:58:44 -0700[diff] [blame]113 qcom,energy-active-coeff-a = <2492>;
114 qcom,energy-active-coeff-b = <0>;
115 qcom,energy-active-coeff-c = <0>;
116 qcom,energy-leakage-coeff-a = <11>;
117 qcom,energy-leakage-coeff-b = <157150>;
118 qcom,energy-leakage-coeff-c = <0>;
119 qcom,energy-leakage-coeff-d = <0>;
120
121 qcom,power-current-temp = <25>;
122 qcom,power-num-freq = <4>;
123
Pu Chen1335e872012-08-01 08:45:25 -0600[diff] [blame]124 qcom,dcvs-freq@0 {
125 reg = <0>;
126 qcom,freq = <0>;
Abhijeet Dharmapurikar44451662012-08-23 18:58:44 -0700[diff] [blame]127 qcom,voltage = <0>;
128 qcom,is_trans_level = <0>;
129 qcom,active-energy-offset = <100>;
130 qcom,leakage-energy-offset = <0>;
Pu Chen1335e872012-08-01 08:45:25 -0600[diff] [blame]131 };
132
133 qcom,dcvs-freq@1 {
134 reg = <1>;
135 qcom,freq = <0>;
Abhijeet Dharmapurikar44451662012-08-23 18:58:44 -0700[diff] [blame]136 qcom,voltage = <0>;
137 qcom,is_trans_level = <0>;
138 qcom,active-energy-offset = <100>;
139 qcom,leakage-energy-offset = <0>;
Pu Chen1335e872012-08-01 08:45:25 -0600[diff] [blame]140 };
141
142 qcom,dcvs-freq@2 {
143 reg = <2>;
144 qcom,freq = <0>;
Abhijeet Dharmapurikar44451662012-08-23 18:58:44 -0700[diff] [blame]145 qcom,voltage = <0>;
146 qcom,is_trans_level = <0>;
147 qcom,active-energy-offset = <100>;
148 qcom,leakage-energy-offset = <0>;
Pu Chen1335e872012-08-01 08:45:25 -0600[diff] [blame]149 };
150
151 qcom,dcvs-freq@3 {
152 reg = <3>;
153 qcom,freq = <0>;
Abhijeet Dharmapurikar44451662012-08-23 18:58:44 -0700[diff] [blame]154 qcom,voltage = <0>;
155 qcom,is_trans_level = <0>;
156 qcom,active-energy-offset = <844545>;
157 qcom,leakage-energy-offset = <0>;
Pu Chen1335e872012-08-01 08:45:25 -0600[diff] [blame]158 };
159 };
160
161 };
162};