blob: 135a3a5931a4eedf60a56fafb95ffbbc7ff30b71 [file] [log] [blame]
Andrei Konovalovae918c02007-07-17 04:04:11 -07001/*
2 * xilinx_spi.c
3 *
4 * Xilinx SPI controller driver (master mode only)
5 *
6 * Author: MontaVista Software, Inc.
7 * source@mvista.com
8 *
9 * 2002-2007 (c) MontaVista Software, Inc. This file is licensed under the
10 * terms of the GNU General Public License version 2. This program is licensed
11 * "as is" without any warranty of any kind, whether express or implied.
12 */
13
14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/interrupt.h>
John Linnff82c582009-01-09 16:01:53 -070017
Andrei Konovalovae918c02007-07-17 04:04:11 -070018#include <linux/spi/spi.h>
19#include <linux/spi/spi_bitbang.h>
20#include <linux/io.h>
21
Richard Röjforsd5af91a2009-11-13 12:28:39 +010022#include "xilinx_spi.h"
23#include <linux/spi/xilinx_spi.h>
24
David Brownellfc3ba952007-08-30 23:56:24 -070025#define XILINX_SPI_NAME "xilinx_spi"
Andrei Konovalovae918c02007-07-17 04:04:11 -070026
27/* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e)
28 * Product Specification", DS464
29 */
Richard Röjfors86fc5932009-11-13 12:28:49 +010030#define XSPI_CR_OFFSET 0x60 /* 16-bit Control Register */
Andrei Konovalovae918c02007-07-17 04:04:11 -070031
32#define XSPI_CR_ENABLE 0x02
33#define XSPI_CR_MASTER_MODE 0x04
34#define XSPI_CR_CPOL 0x08
35#define XSPI_CR_CPHA 0x10
36#define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL)
37#define XSPI_CR_TXFIFO_RESET 0x20
38#define XSPI_CR_RXFIFO_RESET 0x40
39#define XSPI_CR_MANUAL_SSELECT 0x80
40#define XSPI_CR_TRANS_INHIBIT 0x100
41
Richard Röjfors86fc5932009-11-13 12:28:49 +010042#define XSPI_SR_OFFSET 0x64 /* 8-bit Status Register */
Andrei Konovalovae918c02007-07-17 04:04:11 -070043
44#define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */
45#define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */
46#define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */
47#define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */
48#define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */
49
Richard Röjfors86fc5932009-11-13 12:28:49 +010050#define XSPI_TXD_OFFSET 0x68 /* 8-bit Data Transmit Register */
51#define XSPI_RXD_OFFSET 0x6c /* 8-bit Data Receive Register */
Andrei Konovalovae918c02007-07-17 04:04:11 -070052
53#define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */
54
55/* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414
56 * IPIF registers are 32 bit
57 */
58#define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */
59#define XIPIF_V123B_GINTR_ENABLE 0x80000000
60
61#define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */
62#define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */
63
64#define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */
65#define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while
66 * disabled */
67#define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */
68#define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */
69#define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */
70#define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */
71
72#define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */
73#define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */
74
75struct xilinx_spi {
76 /* bitbang has to be first */
77 struct spi_bitbang bitbang;
78 struct completion done;
Richard Röjforsd5af91a2009-11-13 12:28:39 +010079 struct resource mem; /* phys mem */
Andrei Konovalovae918c02007-07-17 04:04:11 -070080 void __iomem *regs; /* virt. address of the control registers */
81
82 u32 irq;
83
84 u32 speed_hz; /* SCK has a fixed frequency of speed_hz Hz */
85
86 u8 *rx_ptr; /* pointer in the Tx buffer */
87 const u8 *tx_ptr; /* pointer in the Rx buffer */
88 int remaining_bytes; /* the number of bytes left to transfer */
Richard Röjfors86fc5932009-11-13 12:28:49 +010089 unsigned int (*read_fn) (void __iomem *);
90 void (*write_fn) (u32, void __iomem *);
Andrei Konovalovae918c02007-07-17 04:04:11 -070091};
92
Richard Röjfors86fc5932009-11-13 12:28:49 +010093static void xspi_init_hw(struct xilinx_spi *xspi)
Andrei Konovalovae918c02007-07-17 04:04:11 -070094{
Richard Röjfors86fc5932009-11-13 12:28:49 +010095 void __iomem *regs_base = xspi->regs;
96
Andrei Konovalovae918c02007-07-17 04:04:11 -070097 /* Reset the SPI device */
Richard Röjfors86fc5932009-11-13 12:28:49 +010098 xspi->write_fn(XIPIF_V123B_RESET_MASK,
99 regs_base + XIPIF_V123B_RESETR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700100 /* Disable all the interrupts just in case */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100101 xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700102 /* Enable the global IPIF interrupt */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100103 xspi->write_fn(XIPIF_V123B_GINTR_ENABLE,
104 regs_base + XIPIF_V123B_DGIER_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700105 /* Deselect the slave on the SPI bus */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100106 xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700107 /* Disable the transmitter, enable Manual Slave Select Assertion,
108 * put SPI controller into master mode, and enable it */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100109 xspi->write_fn(XSPI_CR_TRANS_INHIBIT | XSPI_CR_MANUAL_SSELECT |
110 XSPI_CR_MASTER_MODE | XSPI_CR_ENABLE,
111 regs_base + XSPI_CR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700112}
113
114static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
115{
116 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
117
118 if (is_on == BITBANG_CS_INACTIVE) {
119 /* Deselect the slave on the SPI bus */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100120 xspi->write_fn(0xffff, xspi->regs + XSPI_SSR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700121 } else if (is_on == BITBANG_CS_ACTIVE) {
122 /* Set the SPI clock phase and polarity */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100123 u16 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET)
Andrei Konovalovae918c02007-07-17 04:04:11 -0700124 & ~XSPI_CR_MODE_MASK;
125 if (spi->mode & SPI_CPHA)
126 cr |= XSPI_CR_CPHA;
127 if (spi->mode & SPI_CPOL)
128 cr |= XSPI_CR_CPOL;
Richard Röjfors86fc5932009-11-13 12:28:49 +0100129 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700130
131 /* We do not check spi->max_speed_hz here as the SPI clock
132 * frequency is not software programmable (the IP block design
133 * parameter)
134 */
135
136 /* Activate the chip select */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100137 xspi->write_fn(~(0x0001 << spi->chip_select),
138 xspi->regs + XSPI_SSR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700139 }
140}
141
142/* spi_bitbang requires custom setup_transfer() to be defined if there is a
143 * custom txrx_bufs(). We have nothing to setup here as the SPI IP block
144 * supports just 8 bits per word, and SPI clock can't be changed in software.
145 * Check for 8 bits per word. Chip select delay calculations could be
146 * added here as soon as bitbang_work() can be made aware of the delay value.
147 */
148static int xilinx_spi_setup_transfer(struct spi_device *spi,
149 struct spi_transfer *t)
150{
151 u8 bits_per_word;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700152
John Linn1a8d3b72009-09-14 08:17:05 +0000153 bits_per_word = (t && t->bits_per_word)
154 ? t->bits_per_word : spi->bits_per_word;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700155 if (bits_per_word != 8) {
156 dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
Harvey Harrisonb687d2a2008-04-28 02:14:19 -0700157 __func__, bits_per_word);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700158 return -EINVAL;
159 }
160
Andrei Konovalovae918c02007-07-17 04:04:11 -0700161 return 0;
162}
163
Andrei Konovalovae918c02007-07-17 04:04:11 -0700164static int xilinx_spi_setup(struct spi_device *spi)
165{
166 struct spi_bitbang *bitbang;
167 struct xilinx_spi *xspi;
168 int retval;
169
170 xspi = spi_master_get_devdata(spi->master);
171 bitbang = &xspi->bitbang;
172
Andrei Konovalovae918c02007-07-17 04:04:11 -0700173 retval = xilinx_spi_setup_transfer(spi, NULL);
174 if (retval < 0)
175 return retval;
176
Andrei Konovalovae918c02007-07-17 04:04:11 -0700177 return 0;
178}
179
180static void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi)
181{
182 u8 sr;
183
184 /* Fill the Tx FIFO with as many bytes as possible */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100185 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700186 while ((sr & XSPI_SR_TX_FULL_MASK) == 0 && xspi->remaining_bytes > 0) {
Richard Röjfors86fc5932009-11-13 12:28:49 +0100187 if (xspi->tx_ptr)
188 xspi->write_fn(*xspi->tx_ptr++,
189 xspi->regs + XSPI_TXD_OFFSET);
190 else
191 xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700192 xspi->remaining_bytes--;
Richard Röjfors86fc5932009-11-13 12:28:49 +0100193 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700194 }
195}
196
197static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
198{
199 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
200 u32 ipif_ier;
201 u16 cr;
202
203 /* We get here with transmitter inhibited */
204
205 xspi->tx_ptr = t->tx_buf;
206 xspi->rx_ptr = t->rx_buf;
207 xspi->remaining_bytes = t->len;
208 INIT_COMPLETION(xspi->done);
209
210 xilinx_spi_fill_tx_fifo(xspi);
211
212 /* Enable the transmit empty interrupt, which we use to determine
213 * progress on the transmission.
214 */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100215 ipif_ier = xspi->read_fn(xspi->regs + XIPIF_V123B_IIER_OFFSET);
216 xspi->write_fn(ipif_ier | XSPI_INTR_TX_EMPTY,
217 xspi->regs + XIPIF_V123B_IIER_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700218
219 /* Start the transfer by not inhibiting the transmitter any longer */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100220 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) &
221 ~XSPI_CR_TRANS_INHIBIT;
222 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700223
224 wait_for_completion(&xspi->done);
225
226 /* Disable the transmit empty interrupt */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100227 xspi->write_fn(ipif_ier, xspi->regs + XIPIF_V123B_IIER_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700228
229 return t->len - xspi->remaining_bytes;
230}
231
232
233/* This driver supports single master mode only. Hence Tx FIFO Empty
234 * is the only interrupt we care about.
235 * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode
236 * Fault are not to happen.
237 */
238static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
239{
240 struct xilinx_spi *xspi = dev_id;
241 u32 ipif_isr;
242
243 /* Get the IPIF interrupts, and clear them immediately */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100244 ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
245 xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700246
247 if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */
248 u16 cr;
249 u8 sr;
250
251 /* A transmit has just completed. Process received data and
252 * check for more data to transmit. Always inhibit the
253 * transmitter while the Isr refills the transmit register/FIFO,
254 * or make sure it is stopped if we're done.
255 */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100256 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
257 xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
258 xspi->regs + XSPI_CR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700259
260 /* Read out all the data from the Rx FIFO */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100261 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700262 while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) {
263 u8 data;
264
Richard Röjfors86fc5932009-11-13 12:28:49 +0100265 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700266 if (xspi->rx_ptr) {
267 *xspi->rx_ptr++ = data;
268 }
Richard Röjfors86fc5932009-11-13 12:28:49 +0100269 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700270 }
271
272 /* See if there is more data to send */
273 if (xspi->remaining_bytes > 0) {
274 xilinx_spi_fill_tx_fifo(xspi);
275 /* Start the transfer by not inhibiting the
276 * transmitter any longer
277 */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100278 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700279 } else {
280 /* No more data to send.
281 * Indicate the transfer is completed.
282 */
283 complete(&xspi->done);
284 }
285 }
286
287 return IRQ_HANDLED;
288}
289
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100290struct spi_master *xilinx_spi_init(struct device *dev, struct resource *mem,
291 u32 irq, s16 bus_num)
Andrei Konovalovae918c02007-07-17 04:04:11 -0700292{
Andrei Konovalovae918c02007-07-17 04:04:11 -0700293 struct spi_master *master;
294 struct xilinx_spi *xspi;
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100295 struct xspi_platform_data *pdata = dev->platform_data;
296 int ret;
John Linnff82c582009-01-09 16:01:53 -0700297
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100298 if (!pdata) {
299 dev_err(dev, "No platform data attached\n");
300 return NULL;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700301 }
302
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100303 master = spi_alloc_master(dev, sizeof(struct xilinx_spi));
304 if (!master)
305 return NULL;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700306
David Brownelle7db06b2009-06-17 16:26:04 -0700307 /* the spi->mode bits understood by this driver: */
308 master->mode_bits = SPI_CPOL | SPI_CPHA;
309
Andrei Konovalovae918c02007-07-17 04:04:11 -0700310 xspi = spi_master_get_devdata(master);
311 xspi->bitbang.master = spi_master_get(master);
312 xspi->bitbang.chipselect = xilinx_spi_chipselect;
313 xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
314 xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
315 xspi->bitbang.master->setup = xilinx_spi_setup;
316 init_completion(&xspi->done);
317
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100318 if (!request_mem_region(mem->start, resource_size(mem),
319 XILINX_SPI_NAME))
Andrei Konovalovae918c02007-07-17 04:04:11 -0700320 goto put_master;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700321
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100322 xspi->regs = ioremap(mem->start, resource_size(mem));
Andrei Konovalovae918c02007-07-17 04:04:11 -0700323 if (xspi->regs == NULL) {
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100324 dev_warn(dev, "ioremap failure\n");
325 goto map_failed;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700326 }
327
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100328 master->bus_num = bus_num;
329 master->num_chipselect = pdata->num_chipselect;
John Linnff82c582009-01-09 16:01:53 -0700330
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100331 xspi->mem = *mem;
332 xspi->irq = irq;
Richard Röjfors86fc5932009-11-13 12:28:49 +0100333 if (pdata->little_endian) {
334 xspi->read_fn = ioread32;
335 xspi->write_fn = iowrite32;
336 } else {
337 xspi->read_fn = ioread32be;
338 xspi->write_fn = iowrite32be;
339 }
Andrei Konovalovae918c02007-07-17 04:04:11 -0700340
341 /* SPI controller initializations */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100342 xspi_init_hw(xspi);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700343
344 /* Register for SPI Interrupt */
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100345 ret = request_irq(xspi->irq, xilinx_spi_irq, 0, XILINX_SPI_NAME, xspi);
346 if (ret)
Andrei Konovalovae918c02007-07-17 04:04:11 -0700347 goto unmap_io;
348
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100349 ret = spi_bitbang_start(&xspi->bitbang);
350 if (ret) {
351 dev_err(dev, "spi_bitbang_start FAILED\n");
Andrei Konovalovae918c02007-07-17 04:04:11 -0700352 goto free_irq;
353 }
354
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100355 dev_info(dev, "at 0x%08X mapped to 0x%08X, irq=%d\n",
356 (u32)mem->start, (u32)xspi->regs, xspi->irq);
357 return master;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700358
359free_irq:
360 free_irq(xspi->irq, xspi);
361unmap_io:
362 iounmap(xspi->regs);
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100363map_failed:
364 release_mem_region(mem->start, resource_size(mem));
Andrei Konovalovae918c02007-07-17 04:04:11 -0700365put_master:
366 spi_master_put(master);
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100367 return NULL;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700368}
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100369EXPORT_SYMBOL(xilinx_spi_init);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700370
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100371void xilinx_spi_deinit(struct spi_master *master)
Andrei Konovalovae918c02007-07-17 04:04:11 -0700372{
373 struct xilinx_spi *xspi;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700374
Andrei Konovalovae918c02007-07-17 04:04:11 -0700375 xspi = spi_master_get_devdata(master);
376
377 spi_bitbang_stop(&xspi->bitbang);
378 free_irq(xspi->irq, xspi);
379 iounmap(xspi->regs);
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100380
381 release_mem_region(xspi->mem.start, resource_size(&xspi->mem));
Andrei Konovalovae918c02007-07-17 04:04:11 -0700382 spi_master_put(xspi->bitbang.master);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700383}
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100384EXPORT_SYMBOL(xilinx_spi_deinit);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700385
Andrei Konovalovae918c02007-07-17 04:04:11 -0700386MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
387MODULE_DESCRIPTION("Xilinx SPI driver");
388MODULE_LICENSE("GPL");