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Pete Popove3ad1c22005-03-01 06:33:16 +00001/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Alchemy Pb1200/Db1200 board setup.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
Pete Popove3ad1c22005-03-01 06:33:16 +000026#include <linux/init.h>
27#include <linux/sched.h>
28#include <linux/ioport.h>
29#include <linux/mm.h>
30#include <linux/console.h>
31#include <linux/mc146818rtc.h>
32#include <linux/delay.h>
33
34#if defined(CONFIG_BLK_DEV_IDE_AU1XXX)
35#include <linux/ide.h>
36#endif
37
38#include <asm/cpu.h>
39#include <asm/bootinfo.h>
40#include <asm/irq.h>
41#include <asm/mipsregs.h>
42#include <asm/reboot.h>
43#include <asm/pgtable.h>
Yoichi Yuasa25b31cb2007-10-15 19:11:24 +090044
45#include <au1000.h>
46#include <au1xxx_dbdma.h>
47#include <prom.h>
Pete Popove3ad1c22005-03-01 06:33:16 +000048
49#ifdef CONFIG_MIPS_PB1200
50#include <asm/mach-pb1x00/pb1200.h>
51#endif
52
53#ifdef CONFIG_MIPS_DB1200
54#include <asm/mach-db1x00/db1200.h>
55#define PB1200_ETH_INT DB1200_ETH_INT
56#define PB1200_IDE_INT DB1200_IDE_INT
57#endif
58
59extern void _board_init_irq(void);
Yoichi Yuasa0d02f072006-11-01 18:40:15 +090060extern void (*board_init_irq)(void);
Pete Popove3ad1c22005-03-01 06:33:16 +000061
Ralf Baechle49a89ef2007-10-11 23:46:15 +010062void board_reset(void)
Pete Popove3ad1c22005-03-01 06:33:16 +000063{
64 bcsr->resets = 0;
Pete Popov64abf642005-09-14 16:17:59 +000065 bcsr->system = 0;
Pete Popove3ad1c22005-03-01 06:33:16 +000066}
67
68void __init board_setup(void)
69{
70 char *argptr = NULL;
Pete Popove3ad1c22005-03-01 06:33:16 +000071
72#if 0
Ralf Baechlef5cd9f12007-11-01 12:22:53 +000073 {
74 u32 pin_func;
75
Pete Popove3ad1c22005-03-01 06:33:16 +000076 /* Enable PSC1 SYNC for AC97. Normaly done in audio driver,
77 * but it is board specific code, so put it here.
78 */
79 pin_func = au_readl(SYS_PINFUNC);
80 au_sync();
81 pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1;
82 au_writel(pin_func, SYS_PINFUNC);
83
84 au_writel(0, (u32)bcsr|0x10); /* turn off pcmcia power */
85 au_sync();
Ralf Baechlef5cd9f12007-11-01 12:22:53 +000086 }
Pete Popove3ad1c22005-03-01 06:33:16 +000087#endif
88
Pete Popov64abf642005-09-14 16:17:59 +000089#if defined(CONFIG_I2C_AU1550)
Pete Popove3ad1c22005-03-01 06:33:16 +000090 {
91 u32 freq0, clksrc;
Ralf Baechlef5cd9f12007-11-01 12:22:53 +000092 u32 pin_func;
Pete Popove3ad1c22005-03-01 06:33:16 +000093
94 /* Select SMBUS in CPLD */
95 bcsr->resets &= ~(BCSR_RESETS_PCS0MUX);
96
97 pin_func = au_readl(SYS_PINFUNC);
98 au_sync();
99 pin_func &= ~(3<<17 | 1<<4);
100 /* Set GPIOs correctly */
101 pin_func |= 2<<17;
102 au_writel(pin_func, SYS_PINFUNC);
103 au_sync();
104
105 /* The i2c driver depends on 50Mhz clock */
106 freq0 = au_readl(SYS_FREQCTRL0);
107 au_sync();
108 freq0 &= ~(SYS_FC_FRDIV1_MASK | SYS_FC_FS1 | SYS_FC_FE1);
109 freq0 |= (3<<SYS_FC_FRDIV1_BIT);
110 /* 396Mhz / (3+1)*2 == 49.5Mhz */
111 au_writel(freq0, SYS_FREQCTRL0);
112 au_sync();
113 freq0 |= SYS_FC_FE1;
114 au_writel(freq0, SYS_FREQCTRL0);
115 au_sync();
116
117 clksrc = au_readl(SYS_CLKSRC);
118 au_sync();
119 clksrc &= ~0x01f00000;
120 /* bit 22 is EXTCLK0 for PSC0 */
121 clksrc |= (0x3 << 22);
122 au_writel(clksrc, SYS_CLKSRC);
123 au_sync();
124 }
125#endif
126
127#ifdef CONFIG_FB_AU1200
128 argptr = prom_getcmdline();
129#ifdef CONFIG_MIPS_PB1200
Pete Popov64abf642005-09-14 16:17:59 +0000130 strcat(argptr, " video=au1200fb:panel:bs");
Pete Popove3ad1c22005-03-01 06:33:16 +0000131#endif
132#ifdef CONFIG_MIPS_DB1200
Pete Popov64abf642005-09-14 16:17:59 +0000133 strcat(argptr, " video=au1200fb:panel:bs");
Pete Popove3ad1c22005-03-01 06:33:16 +0000134#endif
135#endif
136
Pete Popove3ad1c22005-03-01 06:33:16 +0000137 /* The Pb1200 development board uses external MUX for PSC0 to
138 support SMB/SPI. bcsr->resets bit 12: 0=SMB 1=SPI
139 */
Ralf Baechle6fec2e12007-07-13 06:33:09 +0100140#ifdef CONFIG_I2C_AU1550
Pete Popove3ad1c22005-03-01 06:33:16 +0000141 bcsr->resets &= (~BCSR_RESETS_PCS0MUX);
142#endif
143 au_sync();
144
145#ifdef CONFIG_MIPS_PB1200
146 printk("AMD Alchemy Pb1200 Board\n");
147#endif
148#ifdef CONFIG_MIPS_DB1200
149 printk("AMD Alchemy Db1200 Board\n");
150#endif
Pete Popovebc7f122005-03-04 08:31:06 +0000151
Pete Popove3ad1c22005-03-01 06:33:16 +0000152 /* Setup Pb1200 External Interrupt Controller */
Yoichi Yuasa0d02f072006-11-01 18:40:15 +0900153 board_init_irq = _board_init_irq;
Pete Popove3ad1c22005-03-01 06:33:16 +0000154}
Pete Popov64abf642005-09-14 16:17:59 +0000155
156int
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100157board_au1200fb_panel(void)
Pete Popov64abf642005-09-14 16:17:59 +0000158{
159 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
160 int p;
161
162 p = bcsr->switches;
163 p >>= 8;
164 p &= 0x0F;
165 return p;
166}
167
168int
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100169board_au1200fb_panel_init(void)
Pete Popov64abf642005-09-14 16:17:59 +0000170{
171 /* Apply power */
172 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
173 bcsr->board |= (BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | BCSR_BOARD_LCDBL);
174 /*printk("board_au1200fb_panel_init()\n"); */
175 return 0;
176}
177
178int
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100179board_au1200fb_panel_shutdown(void)
Pete Popov64abf642005-09-14 16:17:59 +0000180{
181 /* Remove power */
182 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
183 bcsr->board &= ~(BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | BCSR_BOARD_LCDBL);
184 /*printk("board_au1200fb_panel_shutdown()\n"); */
185 return 0;
186}
187