Ben Dooks | cf18acf | 2008-10-21 14:07:02 +0100 | [diff] [blame] | 1 | /* linux/arch/arm/plat-s3c64xx/s3c6400-clock.c |
| 2 | * |
| 3 | * Copyright 2008 Openmoko, Inc. |
| 4 | * Copyright 2008 Simtec Electronics |
| 5 | * Ben Dooks <ben@simtec.co.uk> |
| 6 | * http://armlinux.simtec.co.uk/ |
| 7 | * |
| 8 | * S3C6400 based common clock support |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License version 2 as |
| 12 | * published by the Free Software Foundation. |
| 13 | */ |
| 14 | |
| 15 | #include <linux/init.h> |
| 16 | #include <linux/module.h> |
| 17 | #include <linux/kernel.h> |
| 18 | #include <linux/list.h> |
| 19 | #include <linux/errno.h> |
| 20 | #include <linux/err.h> |
| 21 | #include <linux/clk.h> |
| 22 | #include <linux/sysdev.h> |
| 23 | #include <linux/io.h> |
| 24 | |
| 25 | #include <mach/hardware.h> |
| 26 | #include <mach/map.h> |
| 27 | |
| 28 | #include <plat/cpu-freq.h> |
| 29 | |
| 30 | #include <plat/regs-clock.h> |
| 31 | #include <plat/clock.h> |
| 32 | #include <plat/cpu.h> |
| 33 | #include <plat/pll.h> |
| 34 | |
| 35 | /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call |
| 36 | * ext_xtal_mux for want of an actual name from the manual. |
| 37 | */ |
| 38 | |
Ben Dooks | 3782d36 | 2009-02-27 11:25:37 +0000 | [diff] [blame] | 39 | static struct clk clk_ext_xtal_mux = { |
Ben Dooks | cf18acf | 2008-10-21 14:07:02 +0100 | [diff] [blame] | 40 | .name = "ext_xtal", |
| 41 | .id = -1, |
| 42 | }; |
| 43 | |
| 44 | #define clk_fin_apll clk_ext_xtal_mux |
| 45 | #define clk_fin_mpll clk_ext_xtal_mux |
| 46 | #define clk_fin_epll clk_ext_xtal_mux |
| 47 | |
| 48 | #define clk_fout_mpll clk_mpll |
| 49 | |
| 50 | struct clk_sources { |
| 51 | unsigned int nr_sources; |
| 52 | struct clk **sources; |
| 53 | }; |
| 54 | |
| 55 | struct clksrc_clk { |
| 56 | struct clk clk; |
| 57 | unsigned int mask; |
| 58 | unsigned int shift; |
| 59 | |
| 60 | struct clk_sources *sources; |
| 61 | |
| 62 | unsigned int divider_shift; |
| 63 | void __iomem *reg_divider; |
| 64 | }; |
| 65 | |
Ben Dooks | 3782d36 | 2009-02-27 11:25:37 +0000 | [diff] [blame] | 66 | static struct clk clk_fout_apll = { |
Ben Dooks | cf18acf | 2008-10-21 14:07:02 +0100 | [diff] [blame] | 67 | .name = "fout_apll", |
| 68 | .id = -1, |
| 69 | }; |
| 70 | |
| 71 | static struct clk *clk_src_apll_list[] = { |
| 72 | [0] = &clk_fin_apll, |
| 73 | [1] = &clk_fout_apll, |
| 74 | }; |
| 75 | |
| 76 | static struct clk_sources clk_src_apll = { |
| 77 | .sources = clk_src_apll_list, |
| 78 | .nr_sources = ARRAY_SIZE(clk_src_apll_list), |
| 79 | }; |
| 80 | |
Ben Dooks | 3782d36 | 2009-02-27 11:25:37 +0000 | [diff] [blame] | 81 | static struct clksrc_clk clk_mout_apll = { |
Ben Dooks | cf18acf | 2008-10-21 14:07:02 +0100 | [diff] [blame] | 82 | .clk = { |
| 83 | .name = "mout_apll", |
| 84 | .id = -1, |
| 85 | }, |
| 86 | .shift = S3C6400_CLKSRC_APLL_MOUT_SHIFT, |
| 87 | .mask = S3C6400_CLKSRC_APLL_MOUT, |
| 88 | .sources = &clk_src_apll, |
| 89 | }; |
| 90 | |
Ben Dooks | 3782d36 | 2009-02-27 11:25:37 +0000 | [diff] [blame] | 91 | static struct clk clk_fout_epll = { |
Ben Dooks | cf18acf | 2008-10-21 14:07:02 +0100 | [diff] [blame] | 92 | .name = "fout_epll", |
| 93 | .id = -1, |
| 94 | }; |
| 95 | |
| 96 | static struct clk *clk_src_epll_list[] = { |
| 97 | [0] = &clk_fin_epll, |
| 98 | [1] = &clk_fout_epll, |
| 99 | }; |
| 100 | |
| 101 | static struct clk_sources clk_src_epll = { |
| 102 | .sources = clk_src_epll_list, |
| 103 | .nr_sources = ARRAY_SIZE(clk_src_epll_list), |
| 104 | }; |
| 105 | |
Ben Dooks | 3782d36 | 2009-02-27 11:25:37 +0000 | [diff] [blame] | 106 | static struct clksrc_clk clk_mout_epll = { |
Ben Dooks | cf18acf | 2008-10-21 14:07:02 +0100 | [diff] [blame] | 107 | .clk = { |
| 108 | .name = "mout_epll", |
| 109 | .id = -1, |
| 110 | }, |
| 111 | .shift = S3C6400_CLKSRC_EPLL_MOUT_SHIFT, |
| 112 | .mask = S3C6400_CLKSRC_EPLL_MOUT, |
| 113 | .sources = &clk_src_epll, |
| 114 | }; |
| 115 | |
| 116 | static struct clk *clk_src_mpll_list[] = { |
| 117 | [0] = &clk_fin_mpll, |
| 118 | [1] = &clk_fout_mpll, |
| 119 | }; |
| 120 | |
| 121 | static struct clk_sources clk_src_mpll = { |
| 122 | .sources = clk_src_mpll_list, |
| 123 | .nr_sources = ARRAY_SIZE(clk_src_mpll_list), |
| 124 | }; |
| 125 | |
Ben Dooks | 3782d36 | 2009-02-27 11:25:37 +0000 | [diff] [blame] | 126 | static struct clksrc_clk clk_mout_mpll = { |
Ben Dooks | cf18acf | 2008-10-21 14:07:02 +0100 | [diff] [blame] | 127 | .clk = { |
| 128 | .name = "mout_mpll", |
| 129 | .id = -1, |
| 130 | }, |
| 131 | .shift = S3C6400_CLKSRC_MPLL_MOUT_SHIFT, |
| 132 | .mask = S3C6400_CLKSRC_MPLL_MOUT, |
| 133 | .sources = &clk_src_mpll, |
| 134 | }; |
| 135 | |
Ben Dooks | 496a3f0 | 2009-05-02 13:48:53 +0100 | [diff] [blame] | 136 | static unsigned int armclk_mask; |
| 137 | |
| 138 | static unsigned long s3c64xx_clk_arm_get_rate(struct clk *clk) |
| 139 | { |
| 140 | unsigned long rate = clk_get_rate(clk->parent); |
| 141 | u32 clkdiv; |
| 142 | |
| 143 | /* divisor mask starts at bit0, so no need to shift */ |
| 144 | clkdiv = __raw_readl(S3C_CLK_DIV0) & armclk_mask; |
| 145 | |
| 146 | return rate / (clkdiv + 1); |
| 147 | } |
| 148 | |
| 149 | static unsigned long s3c64xx_clk_arm_round_rate(struct clk *clk, |
| 150 | unsigned long rate) |
| 151 | { |
| 152 | unsigned long parent = clk_get_rate(clk->parent); |
| 153 | u32 div; |
| 154 | |
| 155 | if (parent < rate) |
| 156 | return rate; |
| 157 | |
| 158 | div = (parent / rate) - 1; |
| 159 | if (div > armclk_mask) |
| 160 | div = armclk_mask; |
| 161 | |
| 162 | return parent / (div + 1); |
| 163 | } |
| 164 | |
| 165 | static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate) |
| 166 | { |
| 167 | unsigned long parent = clk_get_rate(clk->parent); |
| 168 | u32 div; |
| 169 | u32 val; |
| 170 | |
| 171 | if (rate < parent / (armclk_mask + 1)) |
| 172 | return -EINVAL; |
| 173 | |
| 174 | rate = clk_round_rate(clk, rate); |
| 175 | div = clk_get_rate(clk->parent) / rate; |
| 176 | |
| 177 | val = __raw_readl(S3C_CLK_DIV0); |
| 178 | val &= armclk_mask; |
| 179 | val |= (div - 1); |
| 180 | __raw_writel(val, S3C_CLK_DIV0); |
| 181 | |
| 182 | return 0; |
| 183 | |
| 184 | } |
| 185 | |
| 186 | static struct clk clk_arm = { |
| 187 | .name = "armclk", |
| 188 | .id = -1, |
| 189 | .parent = &clk_mout_apll.clk, |
| 190 | .get_rate = s3c64xx_clk_arm_get_rate, |
| 191 | .set_rate = s3c64xx_clk_arm_set_rate, |
| 192 | .round_rate = s3c64xx_clk_arm_round_rate, |
| 193 | }; |
| 194 | |
Ben Dooks | cf18acf | 2008-10-21 14:07:02 +0100 | [diff] [blame] | 195 | static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk) |
| 196 | { |
| 197 | unsigned long rate = clk_get_rate(clk->parent); |
| 198 | |
Ben Dooks | 39669f5 | 2008-10-21 14:07:12 +0100 | [diff] [blame] | 199 | printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); |
Ben Dooks | cf18acf | 2008-10-21 14:07:02 +0100 | [diff] [blame] | 200 | |
| 201 | if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK) |
| 202 | rate /= 2; |
| 203 | |
| 204 | return rate; |
| 205 | } |
| 206 | |
Ben Dooks | 3782d36 | 2009-02-27 11:25:37 +0000 | [diff] [blame] | 207 | static struct clk clk_dout_mpll = { |
Ben Dooks | cf18acf | 2008-10-21 14:07:02 +0100 | [diff] [blame] | 208 | .name = "dout_mpll", |
| 209 | .id = -1, |
| 210 | .parent = &clk_mout_mpll.clk, |
| 211 | .get_rate = s3c64xx_clk_doutmpll_get_rate, |
| 212 | }; |
| 213 | |
| 214 | static struct clk *clkset_spi_mmc_list[] = { |
| 215 | &clk_mout_epll.clk, |
| 216 | &clk_dout_mpll, |
| 217 | &clk_fin_epll, |
| 218 | &clk_27m, |
| 219 | }; |
| 220 | |
| 221 | static struct clk_sources clkset_spi_mmc = { |
| 222 | .sources = clkset_spi_mmc_list, |
| 223 | .nr_sources = ARRAY_SIZE(clkset_spi_mmc_list), |
| 224 | }; |
| 225 | |
| 226 | static struct clk *clkset_irda_list[] = { |
| 227 | &clk_mout_epll.clk, |
| 228 | &clk_dout_mpll, |
| 229 | NULL, |
| 230 | &clk_27m, |
| 231 | }; |
| 232 | |
| 233 | static struct clk_sources clkset_irda = { |
| 234 | .sources = clkset_irda_list, |
| 235 | .nr_sources = ARRAY_SIZE(clkset_irda_list), |
| 236 | }; |
| 237 | |
| 238 | static struct clk *clkset_uart_list[] = { |
| 239 | &clk_mout_epll.clk, |
| 240 | &clk_dout_mpll, |
| 241 | NULL, |
| 242 | NULL |
| 243 | }; |
| 244 | |
| 245 | static struct clk_sources clkset_uart = { |
| 246 | .sources = clkset_uart_list, |
| 247 | .nr_sources = ARRAY_SIZE(clkset_uart_list), |
| 248 | }; |
| 249 | |
| 250 | static struct clk *clkset_uhost_list[] = { |
Ben Dooks | 41ba41d | 2009-02-26 23:00:34 +0000 | [diff] [blame] | 251 | &clk_48m, |
Ben Dooks | cf18acf | 2008-10-21 14:07:02 +0100 | [diff] [blame] | 252 | &clk_mout_epll.clk, |
| 253 | &clk_dout_mpll, |
| 254 | &clk_fin_epll, |
Ben Dooks | cf18acf | 2008-10-21 14:07:02 +0100 | [diff] [blame] | 255 | }; |
| 256 | |
| 257 | static struct clk_sources clkset_uhost = { |
| 258 | .sources = clkset_uhost_list, |
| 259 | .nr_sources = ARRAY_SIZE(clkset_uhost_list), |
| 260 | }; |
| 261 | |
| 262 | |
| 263 | /* The peripheral clocks are all controlled via clocksource followed |
| 264 | * by an optional divider and gate stage. We currently roll this into |
| 265 | * one clock which hides the intermediate clock from the mux. |
| 266 | * |
| 267 | * Note, the JPEG clock can only be an even divider... |
| 268 | * |
| 269 | * The scaler and LCD clocks depend on the S3C64XX version, and also |
| 270 | * have a common parent divisor so are not included here. |
| 271 | */ |
| 272 | |
| 273 | static inline struct clksrc_clk *to_clksrc(struct clk *clk) |
| 274 | { |
| 275 | return container_of(clk, struct clksrc_clk, clk); |
| 276 | } |
| 277 | |
| 278 | static unsigned long s3c64xx_getrate_clksrc(struct clk *clk) |
| 279 | { |
| 280 | struct clksrc_clk *sclk = to_clksrc(clk); |
| 281 | unsigned long rate = clk_get_rate(clk->parent); |
| 282 | u32 clkdiv = __raw_readl(sclk->reg_divider); |
| 283 | |
| 284 | clkdiv >>= sclk->divider_shift; |
| 285 | clkdiv &= 0xf; |
| 286 | clkdiv++; |
| 287 | |
| 288 | rate /= clkdiv; |
| 289 | return rate; |
| 290 | } |
| 291 | |
| 292 | static int s3c64xx_setrate_clksrc(struct clk *clk, unsigned long rate) |
| 293 | { |
| 294 | struct clksrc_clk *sclk = to_clksrc(clk); |
| 295 | void __iomem *reg = sclk->reg_divider; |
| 296 | unsigned int div; |
| 297 | u32 val; |
| 298 | |
| 299 | rate = clk_round_rate(clk, rate); |
| 300 | div = clk_get_rate(clk->parent) / rate; |
Werner Almesberger | efeff56 | 2009-02-27 08:03:07 -0300 | [diff] [blame] | 301 | if (div > 16) |
| 302 | return -EINVAL; |
Ben Dooks | cf18acf | 2008-10-21 14:07:02 +0100 | [diff] [blame] | 303 | |
| 304 | val = __raw_readl(reg); |
Werner Almesberger | efeff56 | 2009-02-27 08:03:07 -0300 | [diff] [blame] | 305 | val &= ~(0xf << sclk->shift); |
| 306 | val |= (div - 1) << sclk->shift; |
Ben Dooks | cf18acf | 2008-10-21 14:07:02 +0100 | [diff] [blame] | 307 | __raw_writel(val, reg); |
| 308 | |
| 309 | return 0; |
| 310 | } |
| 311 | |
| 312 | static int s3c64xx_setparent_clksrc(struct clk *clk, struct clk *parent) |
| 313 | { |
| 314 | struct clksrc_clk *sclk = to_clksrc(clk); |
| 315 | struct clk_sources *srcs = sclk->sources; |
| 316 | u32 clksrc = __raw_readl(S3C_CLK_SRC); |
| 317 | int src_nr = -1; |
| 318 | int ptr; |
| 319 | |
| 320 | for (ptr = 0; ptr < srcs->nr_sources; ptr++) |
| 321 | if (srcs->sources[ptr] == parent) { |
| 322 | src_nr = ptr; |
| 323 | break; |
| 324 | } |
| 325 | |
| 326 | if (src_nr >= 0) { |
| 327 | clksrc &= ~sclk->mask; |
| 328 | clksrc |= src_nr << sclk->shift; |
| 329 | |
| 330 | __raw_writel(clksrc, S3C_CLK_SRC); |
| 331 | return 0; |
| 332 | } |
| 333 | |
| 334 | return -EINVAL; |
| 335 | } |
| 336 | |
| 337 | static unsigned long s3c64xx_roundrate_clksrc(struct clk *clk, |
| 338 | unsigned long rate) |
| 339 | { |
| 340 | unsigned long parent_rate = clk_get_rate(clk->parent); |
| 341 | int div; |
| 342 | |
| 343 | if (rate > parent_rate) |
| 344 | rate = parent_rate; |
| 345 | else { |
| 346 | div = rate / parent_rate; |
| 347 | |
| 348 | if (div == 0) |
| 349 | div = 1; |
| 350 | if (div > 16) |
| 351 | div = 16; |
| 352 | |
| 353 | rate = parent_rate / div; |
| 354 | } |
| 355 | |
| 356 | return rate; |
| 357 | } |
| 358 | |
| 359 | static struct clksrc_clk clk_mmc0 = { |
| 360 | .clk = { |
| 361 | .name = "mmc_bus", |
| 362 | .id = 0, |
| 363 | .ctrlbit = S3C_CLKCON_SCLK_MMC0, |
| 364 | .enable = s3c64xx_sclk_ctrl, |
| 365 | .set_parent = s3c64xx_setparent_clksrc, |
| 366 | .get_rate = s3c64xx_getrate_clksrc, |
| 367 | .set_rate = s3c64xx_setrate_clksrc, |
| 368 | .round_rate = s3c64xx_roundrate_clksrc, |
| 369 | }, |
| 370 | .shift = S3C6400_CLKSRC_MMC0_SHIFT, |
| 371 | .mask = S3C6400_CLKSRC_MMC0_MASK, |
| 372 | .sources = &clkset_spi_mmc, |
| 373 | .divider_shift = S3C6400_CLKDIV1_MMC0_SHIFT, |
| 374 | .reg_divider = S3C_CLK_DIV1, |
| 375 | }; |
| 376 | |
| 377 | static struct clksrc_clk clk_mmc1 = { |
| 378 | .clk = { |
| 379 | .name = "mmc_bus", |
| 380 | .id = 1, |
| 381 | .ctrlbit = S3C_CLKCON_SCLK_MMC1, |
| 382 | .enable = s3c64xx_sclk_ctrl, |
| 383 | .get_rate = s3c64xx_getrate_clksrc, |
| 384 | .set_rate = s3c64xx_setrate_clksrc, |
| 385 | .set_parent = s3c64xx_setparent_clksrc, |
| 386 | .round_rate = s3c64xx_roundrate_clksrc, |
| 387 | }, |
| 388 | .shift = S3C6400_CLKSRC_MMC1_SHIFT, |
| 389 | .mask = S3C6400_CLKSRC_MMC1_MASK, |
| 390 | .sources = &clkset_spi_mmc, |
| 391 | .divider_shift = S3C6400_CLKDIV1_MMC1_SHIFT, |
| 392 | .reg_divider = S3C_CLK_DIV1, |
| 393 | }; |
| 394 | |
| 395 | static struct clksrc_clk clk_mmc2 = { |
| 396 | .clk = { |
| 397 | .name = "mmc_bus", |
| 398 | .id = 2, |
| 399 | .ctrlbit = S3C_CLKCON_SCLK_MMC2, |
| 400 | .enable = s3c64xx_sclk_ctrl, |
| 401 | .get_rate = s3c64xx_getrate_clksrc, |
| 402 | .set_rate = s3c64xx_setrate_clksrc, |
| 403 | .set_parent = s3c64xx_setparent_clksrc, |
| 404 | .round_rate = s3c64xx_roundrate_clksrc, |
| 405 | }, |
| 406 | .shift = S3C6400_CLKSRC_MMC2_SHIFT, |
| 407 | .mask = S3C6400_CLKSRC_MMC2_MASK, |
| 408 | .sources = &clkset_spi_mmc, |
| 409 | .divider_shift = S3C6400_CLKDIV1_MMC2_SHIFT, |
| 410 | .reg_divider = S3C_CLK_DIV1, |
| 411 | }; |
| 412 | |
| 413 | static struct clksrc_clk clk_usbhost = { |
| 414 | .clk = { |
Ben Dooks | 19c5957 | 2009-02-26 23:00:33 +0000 | [diff] [blame] | 415 | .name = "usb-bus-host", |
Ben Dooks | cf18acf | 2008-10-21 14:07:02 +0100 | [diff] [blame] | 416 | .id = -1, |
| 417 | .ctrlbit = S3C_CLKCON_SCLK_UHOST, |
| 418 | .enable = s3c64xx_sclk_ctrl, |
| 419 | .set_parent = s3c64xx_setparent_clksrc, |
| 420 | .get_rate = s3c64xx_getrate_clksrc, |
| 421 | .set_rate = s3c64xx_setrate_clksrc, |
| 422 | .round_rate = s3c64xx_roundrate_clksrc, |
| 423 | }, |
| 424 | .shift = S3C6400_CLKSRC_UHOST_SHIFT, |
| 425 | .mask = S3C6400_CLKSRC_UHOST_MASK, |
| 426 | .sources = &clkset_uhost, |
| 427 | .divider_shift = S3C6400_CLKDIV1_UHOST_SHIFT, |
| 428 | .reg_divider = S3C_CLK_DIV1, |
| 429 | }; |
| 430 | |
| 431 | static struct clksrc_clk clk_uart_uclk1 = { |
| 432 | .clk = { |
| 433 | .name = "uclk1", |
| 434 | .id = -1, |
| 435 | .ctrlbit = S3C_CLKCON_SCLK_UART, |
| 436 | .enable = s3c64xx_sclk_ctrl, |
| 437 | .set_parent = s3c64xx_setparent_clksrc, |
| 438 | .get_rate = s3c64xx_getrate_clksrc, |
| 439 | .set_rate = s3c64xx_setrate_clksrc, |
| 440 | .round_rate = s3c64xx_roundrate_clksrc, |
| 441 | }, |
| 442 | .shift = S3C6400_CLKSRC_UART_SHIFT, |
| 443 | .mask = S3C6400_CLKSRC_UART_MASK, |
| 444 | .sources = &clkset_uart, |
| 445 | .divider_shift = S3C6400_CLKDIV2_UART_SHIFT, |
| 446 | .reg_divider = S3C_CLK_DIV2, |
| 447 | }; |
| 448 | |
| 449 | /* Where does UCLK0 come from? */ |
| 450 | |
| 451 | static struct clksrc_clk clk_spi0 = { |
| 452 | .clk = { |
| 453 | .name = "spi-bus", |
| 454 | .id = 0, |
| 455 | .ctrlbit = S3C_CLKCON_SCLK_SPI0, |
| 456 | .enable = s3c64xx_sclk_ctrl, |
| 457 | .set_parent = s3c64xx_setparent_clksrc, |
| 458 | .get_rate = s3c64xx_getrate_clksrc, |
| 459 | .set_rate = s3c64xx_setrate_clksrc, |
| 460 | .round_rate = s3c64xx_roundrate_clksrc, |
| 461 | }, |
| 462 | .shift = S3C6400_CLKSRC_SPI0_SHIFT, |
| 463 | .mask = S3C6400_CLKSRC_SPI0_MASK, |
| 464 | .sources = &clkset_spi_mmc, |
| 465 | .divider_shift = S3C6400_CLKDIV2_SPI0_SHIFT, |
| 466 | .reg_divider = S3C_CLK_DIV2, |
| 467 | }; |
| 468 | |
| 469 | static struct clksrc_clk clk_spi1 = { |
| 470 | .clk = { |
| 471 | .name = "spi-bus", |
| 472 | .id = 1, |
| 473 | .ctrlbit = S3C_CLKCON_SCLK_SPI1, |
| 474 | .enable = s3c64xx_sclk_ctrl, |
| 475 | .set_parent = s3c64xx_setparent_clksrc, |
| 476 | .get_rate = s3c64xx_getrate_clksrc, |
| 477 | .set_rate = s3c64xx_setrate_clksrc, |
| 478 | .round_rate = s3c64xx_roundrate_clksrc, |
| 479 | }, |
| 480 | .shift = S3C6400_CLKSRC_SPI1_SHIFT, |
| 481 | .mask = S3C6400_CLKSRC_SPI1_MASK, |
| 482 | .sources = &clkset_spi_mmc, |
| 483 | .divider_shift = S3C6400_CLKDIV2_SPI1_SHIFT, |
| 484 | .reg_divider = S3C_CLK_DIV2, |
| 485 | }; |
| 486 | |
| 487 | static struct clk clk_iis_cd0 = { |
| 488 | .name = "iis_cdclk0", |
| 489 | .id = -1, |
| 490 | }; |
| 491 | |
| 492 | static struct clk clk_iis_cd1 = { |
| 493 | .name = "iis_cdclk1", |
| 494 | .id = -1, |
| 495 | }; |
| 496 | |
| 497 | static struct clk clk_pcm_cd = { |
| 498 | .name = "pcm_cdclk", |
| 499 | .id = -1, |
| 500 | }; |
| 501 | |
| 502 | static struct clk *clkset_audio0_list[] = { |
| 503 | [0] = &clk_mout_epll.clk, |
| 504 | [1] = &clk_dout_mpll, |
| 505 | [2] = &clk_fin_epll, |
| 506 | [3] = &clk_iis_cd0, |
| 507 | [4] = &clk_pcm_cd, |
| 508 | }; |
| 509 | |
| 510 | static struct clk_sources clkset_audio0 = { |
| 511 | .sources = clkset_audio0_list, |
| 512 | .nr_sources = ARRAY_SIZE(clkset_audio0_list), |
| 513 | }; |
| 514 | |
| 515 | static struct clksrc_clk clk_audio0 = { |
| 516 | .clk = { |
| 517 | .name = "audio-bus", |
| 518 | .id = 0, |
| 519 | .ctrlbit = S3C_CLKCON_SCLK_AUDIO0, |
| 520 | .enable = s3c64xx_sclk_ctrl, |
| 521 | .set_parent = s3c64xx_setparent_clksrc, |
| 522 | .get_rate = s3c64xx_getrate_clksrc, |
| 523 | .set_rate = s3c64xx_setrate_clksrc, |
| 524 | .round_rate = s3c64xx_roundrate_clksrc, |
| 525 | }, |
| 526 | .shift = S3C6400_CLKSRC_AUDIO0_SHIFT, |
| 527 | .mask = S3C6400_CLKSRC_AUDIO0_MASK, |
| 528 | .sources = &clkset_audio0, |
| 529 | .divider_shift = S3C6400_CLKDIV2_AUDIO0_SHIFT, |
| 530 | .reg_divider = S3C_CLK_DIV2, |
| 531 | }; |
| 532 | |
| 533 | static struct clk *clkset_audio1_list[] = { |
| 534 | [0] = &clk_mout_epll.clk, |
| 535 | [1] = &clk_dout_mpll, |
| 536 | [2] = &clk_fin_epll, |
| 537 | [3] = &clk_iis_cd1, |
| 538 | [4] = &clk_pcm_cd, |
| 539 | }; |
| 540 | |
| 541 | static struct clk_sources clkset_audio1 = { |
| 542 | .sources = clkset_audio1_list, |
| 543 | .nr_sources = ARRAY_SIZE(clkset_audio1_list), |
| 544 | }; |
| 545 | |
| 546 | static struct clksrc_clk clk_audio1 = { |
| 547 | .clk = { |
| 548 | .name = "audio-bus", |
| 549 | .id = 1, |
| 550 | .ctrlbit = S3C_CLKCON_SCLK_AUDIO1, |
| 551 | .enable = s3c64xx_sclk_ctrl, |
| 552 | .set_parent = s3c64xx_setparent_clksrc, |
| 553 | .get_rate = s3c64xx_getrate_clksrc, |
| 554 | .set_rate = s3c64xx_setrate_clksrc, |
| 555 | .round_rate = s3c64xx_roundrate_clksrc, |
| 556 | }, |
| 557 | .shift = S3C6400_CLKSRC_AUDIO1_SHIFT, |
| 558 | .mask = S3C6400_CLKSRC_AUDIO1_MASK, |
| 559 | .sources = &clkset_audio1, |
| 560 | .divider_shift = S3C6400_CLKDIV2_AUDIO1_SHIFT, |
| 561 | .reg_divider = S3C_CLK_DIV2, |
| 562 | }; |
| 563 | |
| 564 | static struct clksrc_clk clk_irda = { |
| 565 | .clk = { |
| 566 | .name = "irda-bus", |
| 567 | .id = 0, |
| 568 | .ctrlbit = S3C_CLKCON_SCLK_IRDA, |
| 569 | .enable = s3c64xx_sclk_ctrl, |
| 570 | .set_parent = s3c64xx_setparent_clksrc, |
| 571 | .get_rate = s3c64xx_getrate_clksrc, |
| 572 | .set_rate = s3c64xx_setrate_clksrc, |
| 573 | .round_rate = s3c64xx_roundrate_clksrc, |
| 574 | }, |
| 575 | .shift = S3C6400_CLKSRC_IRDA_SHIFT, |
| 576 | .mask = S3C6400_CLKSRC_IRDA_MASK, |
| 577 | .sources = &clkset_irda, |
| 578 | .divider_shift = S3C6400_CLKDIV2_IRDA_SHIFT, |
| 579 | .reg_divider = S3C_CLK_DIV2, |
| 580 | }; |
| 581 | |
Werner Almesberger | e2c977d | 2009-03-05 11:43:14 +0800 | [diff] [blame] | 582 | static struct clk *clkset_camif_list[] = { |
| 583 | &clk_h2, |
| 584 | }; |
| 585 | |
| 586 | static struct clk_sources clkset_camif = { |
| 587 | .sources = clkset_camif_list, |
| 588 | .nr_sources = ARRAY_SIZE(clkset_camif_list), |
| 589 | }; |
| 590 | |
| 591 | static struct clksrc_clk clk_camif = { |
| 592 | .clk = { |
| 593 | .name = "camera", |
| 594 | .id = -1, |
| 595 | .ctrlbit = S3C_CLKCON_SCLK_CAM, |
| 596 | .enable = s3c64xx_sclk_ctrl, |
| 597 | .set_parent = s3c64xx_setparent_clksrc, |
| 598 | .get_rate = s3c64xx_getrate_clksrc, |
| 599 | .set_rate = s3c64xx_setrate_clksrc, |
| 600 | .round_rate = s3c64xx_roundrate_clksrc, |
| 601 | }, |
| 602 | .shift = 0, |
| 603 | .mask = 0, |
| 604 | .sources = &clkset_camif, |
| 605 | .divider_shift = S3C6400_CLKDIV0_CAM_SHIFT, |
| 606 | .reg_divider = S3C_CLK_DIV0, |
| 607 | }; |
| 608 | |
Ben Dooks | cf18acf | 2008-10-21 14:07:02 +0100 | [diff] [blame] | 609 | /* Clock initialisation code */ |
| 610 | |
| 611 | static struct clksrc_clk *init_parents[] = { |
| 612 | &clk_mout_apll, |
| 613 | &clk_mout_epll, |
| 614 | &clk_mout_mpll, |
| 615 | &clk_mmc0, |
| 616 | &clk_mmc1, |
| 617 | &clk_mmc2, |
| 618 | &clk_usbhost, |
| 619 | &clk_uart_uclk1, |
| 620 | &clk_spi0, |
| 621 | &clk_spi1, |
| 622 | &clk_audio0, |
| 623 | &clk_audio1, |
| 624 | &clk_irda, |
Werner Almesberger | e2c977d | 2009-03-05 11:43:14 +0800 | [diff] [blame] | 625 | &clk_camif, |
Ben Dooks | cf18acf | 2008-10-21 14:07:02 +0100 | [diff] [blame] | 626 | }; |
| 627 | |
| 628 | static void __init_or_cpufreq s3c6400_set_clksrc(struct clksrc_clk *clk) |
| 629 | { |
| 630 | struct clk_sources *srcs = clk->sources; |
| 631 | u32 clksrc = __raw_readl(S3C_CLK_SRC); |
| 632 | |
| 633 | clksrc &= clk->mask; |
| 634 | clksrc >>= clk->shift; |
| 635 | |
| 636 | if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) { |
| 637 | printk(KERN_ERR "%s: bad source %d\n", |
| 638 | clk->clk.name, clksrc); |
| 639 | return; |
| 640 | } |
| 641 | |
| 642 | clk->clk.parent = srcs->sources[clksrc]; |
| 643 | |
| 644 | printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n", |
| 645 | clk->clk.name, clk->clk.parent->name, clksrc, |
| 646 | clk_get_rate(&clk->clk)); |
| 647 | } |
| 648 | |
| 649 | #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) |
| 650 | |
| 651 | void __init_or_cpufreq s3c6400_setup_clocks(void) |
| 652 | { |
| 653 | struct clk *xtal_clk; |
| 654 | unsigned long xtal; |
| 655 | unsigned long fclk; |
| 656 | unsigned long hclk; |
| 657 | unsigned long hclk2; |
| 658 | unsigned long pclk; |
| 659 | unsigned long epll; |
| 660 | unsigned long apll; |
| 661 | unsigned long mpll; |
| 662 | unsigned int ptr; |
| 663 | u32 clkdiv0; |
| 664 | |
Ben Dooks | 39669f5 | 2008-10-21 14:07:12 +0100 | [diff] [blame] | 665 | printk(KERN_DEBUG "%s: registering clocks\n", __func__); |
Ben Dooks | cf18acf | 2008-10-21 14:07:02 +0100 | [diff] [blame] | 666 | |
| 667 | clkdiv0 = __raw_readl(S3C_CLK_DIV0); |
Ben Dooks | 39669f5 | 2008-10-21 14:07:12 +0100 | [diff] [blame] | 668 | printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0); |
Ben Dooks | cf18acf | 2008-10-21 14:07:02 +0100 | [diff] [blame] | 669 | |
| 670 | xtal_clk = clk_get(NULL, "xtal"); |
| 671 | BUG_ON(IS_ERR(xtal_clk)); |
| 672 | |
| 673 | xtal = clk_get_rate(xtal_clk); |
| 674 | clk_put(xtal_clk); |
| 675 | |
Ben Dooks | 39669f5 | 2008-10-21 14:07:12 +0100 | [diff] [blame] | 676 | printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); |
Ben Dooks | cf18acf | 2008-10-21 14:07:02 +0100 | [diff] [blame] | 677 | |
| 678 | epll = s3c6400_get_epll(xtal); |
| 679 | mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON)); |
| 680 | apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON)); |
| 681 | |
| 682 | fclk = mpll; |
| 683 | |
| 684 | printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n", |
| 685 | apll, mpll, epll); |
| 686 | |
| 687 | hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2); |
| 688 | hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK); |
| 689 | pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK); |
| 690 | |
| 691 | printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n", |
| 692 | hclk2, hclk, pclk); |
| 693 | |
| 694 | clk_fout_mpll.rate = mpll; |
| 695 | clk_fout_epll.rate = epll; |
| 696 | clk_fout_apll.rate = apll; |
| 697 | |
Werner Almesberger | a03f7da | 2009-03-05 11:43:13 +0800 | [diff] [blame] | 698 | clk_h2.rate = hclk2; |
Ben Dooks | cf18acf | 2008-10-21 14:07:02 +0100 | [diff] [blame] | 699 | clk_h.rate = hclk; |
| 700 | clk_p.rate = pclk; |
| 701 | clk_f.rate = fclk; |
| 702 | |
| 703 | for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) |
| 704 | s3c6400_set_clksrc(init_parents[ptr]); |
| 705 | } |
| 706 | |
| 707 | static struct clk *clks[] __initdata = { |
| 708 | &clk_ext_xtal_mux, |
| 709 | &clk_iis_cd0, |
| 710 | &clk_iis_cd1, |
| 711 | &clk_pcm_cd, |
| 712 | &clk_mout_epll.clk, |
Ben Dooks | 1451325 | 2008-10-31 16:14:35 +0000 | [diff] [blame] | 713 | &clk_fout_epll, |
Ben Dooks | cf18acf | 2008-10-21 14:07:02 +0100 | [diff] [blame] | 714 | &clk_mout_mpll.clk, |
| 715 | &clk_dout_mpll, |
| 716 | &clk_mmc0.clk, |
| 717 | &clk_mmc1.clk, |
| 718 | &clk_mmc2.clk, |
| 719 | &clk_usbhost.clk, |
| 720 | &clk_uart_uclk1.clk, |
| 721 | &clk_spi0.clk, |
| 722 | &clk_spi1.clk, |
| 723 | &clk_audio0.clk, |
| 724 | &clk_audio1.clk, |
| 725 | &clk_irda.clk, |
Werner Almesberger | e2c977d | 2009-03-05 11:43:14 +0800 | [diff] [blame] | 726 | &clk_camif.clk, |
Ben Dooks | 496a3f0 | 2009-05-02 13:48:53 +0100 | [diff] [blame] | 727 | &clk_arm, |
Ben Dooks | cf18acf | 2008-10-21 14:07:02 +0100 | [diff] [blame] | 728 | }; |
| 729 | |
Ben Dooks | 496a3f0 | 2009-05-02 13:48:53 +0100 | [diff] [blame] | 730 | /** |
| 731 | * s3c6400_register_clocks - register clocks for s3c6400 and above |
| 732 | * @armclk_divlimit: Divisor mask for ARMCLK |
| 733 | * |
| 734 | * Register the clocks for the S3C6400 and above SoC range, such |
| 735 | * as ARMCLK and the clocks which have divider chains attached. |
| 736 | * |
| 737 | * This call does not setup the clocks, which is left to the |
| 738 | * s3c6400_setup_clocks() call which may be needed by the cpufreq |
| 739 | * or resume code to re-set the clocks if the bootloader has changed |
| 740 | * them. |
| 741 | */ |
| 742 | void __init s3c6400_register_clocks(unsigned armclk_divlimit) |
Ben Dooks | cf18acf | 2008-10-21 14:07:02 +0100 | [diff] [blame] | 743 | { |
| 744 | struct clk *clkp; |
| 745 | int ret; |
| 746 | int ptr; |
| 747 | |
Ben Dooks | 496a3f0 | 2009-05-02 13:48:53 +0100 | [diff] [blame] | 748 | armclk_mask = armclk_divlimit; |
| 749 | |
Ben Dooks | cf18acf | 2008-10-21 14:07:02 +0100 | [diff] [blame] | 750 | for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) { |
| 751 | clkp = clks[ptr]; |
| 752 | ret = s3c24xx_register_clock(clkp); |
| 753 | if (ret < 0) { |
| 754 | printk(KERN_ERR "Failed to register clock %s (%d)\n", |
| 755 | clkp->name, ret); |
| 756 | } |
| 757 | } |
| 758 | |
| 759 | clk_mpll.parent = &clk_mout_mpll.clk; |
| 760 | clk_epll.parent = &clk_mout_epll.clk; |
| 761 | } |