Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 1 | /* |
| 2 | * |
| 3 | * Support for a cx23417 mpeg encoder via cx23885 host port. |
| 4 | * |
Jelle Foks | f8de18d | 2008-11-20 07:07:45 -0300 | [diff] [blame] | 5 | * (c) 2004 Jelle Foks <jelle@foks.us> |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 6 | * (c) 2004 Gerd Knorr <kraxel@bytesex.org> |
Steven Toth | 6d89761 | 2008-09-03 17:12:12 -0300 | [diff] [blame] | 7 | * (c) 2008 Steven Toth <stoth@linuxtv.org> |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 8 | * - CX23885/7/8 support |
| 9 | * |
| 10 | * Includes parts from the ivtv driver( http://ivtv.sourceforge.net/), |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or modify |
| 13 | * it under the terms of the GNU General Public License as published by |
| 14 | * the Free Software Foundation; either version 2 of the License, or |
| 15 | * (at your option) any later version. |
| 16 | * |
| 17 | * This program is distributed in the hope that it will be useful, |
| 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 20 | * GNU General Public License for more details. |
| 21 | * |
| 22 | * You should have received a copy of the GNU General Public License |
| 23 | * along with this program; if not, write to the Free Software |
| 24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 25 | */ |
| 26 | |
| 27 | #include <linux/module.h> |
| 28 | #include <linux/moduleparam.h> |
| 29 | #include <linux/init.h> |
| 30 | #include <linux/fs.h> |
| 31 | #include <linux/delay.h> |
| 32 | #include <linux/device.h> |
| 33 | #include <linux/firmware.h> |
| 34 | #include <media/v4l2-common.h> |
Hans Verkuil | 35ea11f | 2008-07-20 08:12:02 -0300 | [diff] [blame] | 35 | #include <media/v4l2-ioctl.h> |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 36 | #include <media/cx2341x.h> |
| 37 | |
| 38 | #include "cx23885.h" |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 39 | |
| 40 | #define CX23885_FIRM_IMAGE_SIZE 376836 |
| 41 | #define CX23885_FIRM_IMAGE_NAME "v4l-cx23885-enc.fw" |
| 42 | |
| 43 | static unsigned int mpegbufs = 32; |
| 44 | module_param(mpegbufs, int, 0644); |
| 45 | MODULE_PARM_DESC(mpegbufs, "number of mpeg buffers, range 2-32"); |
| 46 | static unsigned int mpeglines = 32; |
| 47 | module_param(mpeglines, int, 0644); |
| 48 | MODULE_PARM_DESC(mpeglines, "number of lines in an MPEG buffer, range 2-32"); |
| 49 | static unsigned int mpeglinesize = 512; |
| 50 | module_param(mpeglinesize, int, 0644); |
| 51 | MODULE_PARM_DESC(mpeglinesize, |
| 52 | "number of bytes in each line of an MPEG buffer, range 512-1024"); |
| 53 | |
| 54 | static unsigned int v4l_debug; |
| 55 | module_param(v4l_debug, int, 0644); |
| 56 | MODULE_PARM_DESC(v4l_debug, "enable V4L debug messages"); |
| 57 | |
| 58 | #define dprintk(level, fmt, arg...)\ |
| 59 | do { if (v4l_debug >= level) \ |
| 60 | printk(KERN_DEBUG "%s: " fmt, dev->name , ## arg);\ |
| 61 | } while (0) |
| 62 | |
| 63 | static struct cx23885_tvnorm cx23885_tvnorms[] = { |
| 64 | { |
| 65 | .name = "NTSC-M", |
| 66 | .id = V4L2_STD_NTSC_M, |
| 67 | }, { |
| 68 | .name = "NTSC-JP", |
| 69 | .id = V4L2_STD_NTSC_M_JP, |
| 70 | }, { |
| 71 | .name = "PAL-BG", |
| 72 | .id = V4L2_STD_PAL_BG, |
| 73 | }, { |
| 74 | .name = "PAL-DK", |
| 75 | .id = V4L2_STD_PAL_DK, |
| 76 | }, { |
| 77 | .name = "PAL-I", |
| 78 | .id = V4L2_STD_PAL_I, |
| 79 | }, { |
| 80 | .name = "PAL-M", |
| 81 | .id = V4L2_STD_PAL_M, |
| 82 | }, { |
| 83 | .name = "PAL-N", |
| 84 | .id = V4L2_STD_PAL_N, |
| 85 | }, { |
| 86 | .name = "PAL-Nc", |
| 87 | .id = V4L2_STD_PAL_Nc, |
| 88 | }, { |
| 89 | .name = "PAL-60", |
| 90 | .id = V4L2_STD_PAL_60, |
| 91 | }, { |
| 92 | .name = "SECAM-L", |
| 93 | .id = V4L2_STD_SECAM_L, |
| 94 | }, { |
| 95 | .name = "SECAM-DK", |
| 96 | .id = V4L2_STD_SECAM_DK, |
| 97 | } |
| 98 | }; |
| 99 | |
| 100 | /* ------------------------------------------------------------------ */ |
| 101 | enum cx23885_capture_type { |
| 102 | CX23885_MPEG_CAPTURE, |
| 103 | CX23885_RAW_CAPTURE, |
| 104 | CX23885_RAW_PASSTHRU_CAPTURE |
| 105 | }; |
| 106 | enum cx23885_capture_bits { |
| 107 | CX23885_RAW_BITS_NONE = 0x00, |
| 108 | CX23885_RAW_BITS_YUV_CAPTURE = 0x01, |
| 109 | CX23885_RAW_BITS_PCM_CAPTURE = 0x02, |
| 110 | CX23885_RAW_BITS_VBI_CAPTURE = 0x04, |
| 111 | CX23885_RAW_BITS_PASSTHRU_CAPTURE = 0x08, |
| 112 | CX23885_RAW_BITS_TO_HOST_CAPTURE = 0x10 |
| 113 | }; |
| 114 | enum cx23885_capture_end { |
| 115 | CX23885_END_AT_GOP, /* stop at the end of gop, generate irq */ |
| 116 | CX23885_END_NOW, /* stop immediately, no irq */ |
| 117 | }; |
| 118 | enum cx23885_framerate { |
| 119 | CX23885_FRAMERATE_NTSC_30, /* NTSC: 30fps */ |
| 120 | CX23885_FRAMERATE_PAL_25 /* PAL: 25fps */ |
| 121 | }; |
| 122 | enum cx23885_stream_port { |
| 123 | CX23885_OUTPUT_PORT_MEMORY, |
| 124 | CX23885_OUTPUT_PORT_STREAMING, |
| 125 | CX23885_OUTPUT_PORT_SERIAL |
| 126 | }; |
| 127 | enum cx23885_data_xfer_status { |
| 128 | CX23885_MORE_BUFFERS_FOLLOW, |
| 129 | CX23885_LAST_BUFFER, |
| 130 | }; |
| 131 | enum cx23885_picture_mask { |
| 132 | CX23885_PICTURE_MASK_NONE, |
| 133 | CX23885_PICTURE_MASK_I_FRAMES, |
| 134 | CX23885_PICTURE_MASK_I_P_FRAMES = 0x3, |
| 135 | CX23885_PICTURE_MASK_ALL_FRAMES = 0x7, |
| 136 | }; |
| 137 | enum cx23885_vbi_mode_bits { |
| 138 | CX23885_VBI_BITS_SLICED, |
| 139 | CX23885_VBI_BITS_RAW, |
| 140 | }; |
| 141 | enum cx23885_vbi_insertion_bits { |
| 142 | CX23885_VBI_BITS_INSERT_IN_XTENSION_USR_DATA, |
| 143 | CX23885_VBI_BITS_INSERT_IN_PRIVATE_PACKETS = 0x1 << 1, |
| 144 | CX23885_VBI_BITS_SEPARATE_STREAM = 0x2 << 1, |
| 145 | CX23885_VBI_BITS_SEPARATE_STREAM_USR_DATA = 0x4 << 1, |
| 146 | CX23885_VBI_BITS_SEPARATE_STREAM_PRV_DATA = 0x5 << 1, |
| 147 | }; |
| 148 | enum cx23885_dma_unit { |
| 149 | CX23885_DMA_BYTES, |
| 150 | CX23885_DMA_FRAMES, |
| 151 | }; |
| 152 | enum cx23885_dma_transfer_status_bits { |
| 153 | CX23885_DMA_TRANSFER_BITS_DONE = 0x01, |
| 154 | CX23885_DMA_TRANSFER_BITS_ERROR = 0x04, |
| 155 | CX23885_DMA_TRANSFER_BITS_LL_ERROR = 0x10, |
| 156 | }; |
| 157 | enum cx23885_pause { |
| 158 | CX23885_PAUSE_ENCODING, |
| 159 | CX23885_RESUME_ENCODING, |
| 160 | }; |
| 161 | enum cx23885_copyright { |
| 162 | CX23885_COPYRIGHT_OFF, |
| 163 | CX23885_COPYRIGHT_ON, |
| 164 | }; |
| 165 | enum cx23885_notification_type { |
| 166 | CX23885_NOTIFICATION_REFRESH, |
| 167 | }; |
| 168 | enum cx23885_notification_status { |
| 169 | CX23885_NOTIFICATION_OFF, |
| 170 | CX23885_NOTIFICATION_ON, |
| 171 | }; |
| 172 | enum cx23885_notification_mailbox { |
| 173 | CX23885_NOTIFICATION_NO_MAILBOX = -1, |
| 174 | }; |
| 175 | enum cx23885_field1_lines { |
| 176 | CX23885_FIELD1_SAA7114 = 0x00EF, /* 239 */ |
| 177 | CX23885_FIELD1_SAA7115 = 0x00F0, /* 240 */ |
| 178 | CX23885_FIELD1_MICRONAS = 0x0105, /* 261 */ |
| 179 | }; |
| 180 | enum cx23885_field2_lines { |
| 181 | CX23885_FIELD2_SAA7114 = 0x00EF, /* 239 */ |
| 182 | CX23885_FIELD2_SAA7115 = 0x00F0, /* 240 */ |
| 183 | CX23885_FIELD2_MICRONAS = 0x0106, /* 262 */ |
| 184 | }; |
| 185 | enum cx23885_custom_data_type { |
| 186 | CX23885_CUSTOM_EXTENSION_USR_DATA, |
| 187 | CX23885_CUSTOM_PRIVATE_PACKET, |
| 188 | }; |
| 189 | enum cx23885_mute { |
| 190 | CX23885_UNMUTE, |
| 191 | CX23885_MUTE, |
| 192 | }; |
| 193 | enum cx23885_mute_video_mask { |
| 194 | CX23885_MUTE_VIDEO_V_MASK = 0x0000FF00, |
| 195 | CX23885_MUTE_VIDEO_U_MASK = 0x00FF0000, |
| 196 | CX23885_MUTE_VIDEO_Y_MASK = 0xFF000000, |
| 197 | }; |
| 198 | enum cx23885_mute_video_shift { |
| 199 | CX23885_MUTE_VIDEO_V_SHIFT = 8, |
| 200 | CX23885_MUTE_VIDEO_U_SHIFT = 16, |
| 201 | CX23885_MUTE_VIDEO_Y_SHIFT = 24, |
| 202 | }; |
| 203 | |
| 204 | /* defines below are from ivtv-driver.h */ |
| 205 | #define IVTV_CMD_HW_BLOCKS_RST 0xFFFFFFFF |
| 206 | |
| 207 | /* Firmware API commands */ |
| 208 | #define IVTV_API_STD_TIMEOUT 500 |
| 209 | |
| 210 | /* Registers */ |
| 211 | /* IVTV_REG_OFFSET */ |
| 212 | #define IVTV_REG_ENC_SDRAM_REFRESH (0x07F8) |
| 213 | #define IVTV_REG_ENC_SDRAM_PRECHARGE (0x07FC) |
| 214 | #define IVTV_REG_SPU (0x9050) |
| 215 | #define IVTV_REG_HW_BLOCKS (0x9054) |
| 216 | #define IVTV_REG_VPU (0x9058) |
| 217 | #define IVTV_REG_APU (0xA064) |
| 218 | |
| 219 | /**** Bit definitions for MC417_RWD and MC417_OEN registers *** |
| 220 | bits 31-16 |
| 221 | +-----------+ |
| 222 | | Reserved | |
| 223 | +-----------+ |
| 224 | bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 |
| 225 | +-------+-------+-------+-------+-------+-------+-------+-------+ |
| 226 | | MIWR# | MIRD# | MICS# |MIRDY# |MIADDR3|MIADDR2|MIADDR1|MIADDR0| |
| 227 | +-------+-------+-------+-------+-------+-------+-------+-------+ |
| 228 | bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 |
| 229 | +-------+-------+-------+-------+-------+-------+-------+-------+ |
| 230 | |MIDATA7|MIDATA6|MIDATA5|MIDATA4|MIDATA3|MIDATA2|MIDATA1|MIDATA0| |
| 231 | +-------+-------+-------+-------+-------+-------+-------+-------+ |
| 232 | ***/ |
| 233 | #define MC417_MIWR 0x8000 |
| 234 | #define MC417_MIRD 0x4000 |
| 235 | #define MC417_MICS 0x2000 |
| 236 | #define MC417_MIRDY 0x1000 |
| 237 | #define MC417_MIADDR 0x0F00 |
| 238 | #define MC417_MIDATA 0x00FF |
| 239 | |
| 240 | /* MIADDR* nibble definitions */ |
| 241 | #define MCI_MEMORY_DATA_BYTE0 0x000 |
| 242 | #define MCI_MEMORY_DATA_BYTE1 0x100 |
| 243 | #define MCI_MEMORY_DATA_BYTE2 0x200 |
| 244 | #define MCI_MEMORY_DATA_BYTE3 0x300 |
| 245 | #define MCI_MEMORY_ADDRESS_BYTE2 0x400 |
| 246 | #define MCI_MEMORY_ADDRESS_BYTE1 0x500 |
| 247 | #define MCI_MEMORY_ADDRESS_BYTE0 0x600 |
| 248 | #define MCI_REGISTER_DATA_BYTE0 0x800 |
| 249 | #define MCI_REGISTER_DATA_BYTE1 0x900 |
| 250 | #define MCI_REGISTER_DATA_BYTE2 0xA00 |
| 251 | #define MCI_REGISTER_DATA_BYTE3 0xB00 |
| 252 | #define MCI_REGISTER_ADDRESS_BYTE0 0xC00 |
| 253 | #define MCI_REGISTER_ADDRESS_BYTE1 0xD00 |
| 254 | #define MCI_REGISTER_MODE 0xE00 |
| 255 | |
| 256 | /* Read and write modes */ |
| 257 | #define MCI_MODE_REGISTER_READ 0 |
| 258 | #define MCI_MODE_REGISTER_WRITE 1 |
| 259 | #define MCI_MODE_MEMORY_READ 0 |
| 260 | #define MCI_MODE_MEMORY_WRITE 0x40 |
| 261 | |
| 262 | /*** Bit definitions for MC417_CTL register **** |
| 263 | bits 31-6 bits 5-4 bit 3 bits 2-1 Bit 0 |
| 264 | +--------+-------------+--------+--------------+------------+ |
| 265 | |Reserved|MC417_SPD_CTL|Reserved|MC417_GPIO_SEL|UART_GPIO_EN| |
| 266 | +--------+-------------+--------+--------------+------------+ |
| 267 | ***/ |
| 268 | #define MC417_SPD_CTL(x) (((x) << 4) & 0x00000030) |
| 269 | #define MC417_GPIO_SEL(x) (((x) << 1) & 0x00000006) |
| 270 | #define MC417_UART_GPIO_EN 0x00000001 |
| 271 | |
| 272 | /* Values for speed control */ |
| 273 | #define MC417_SPD_CTL_SLOW 0x1 |
| 274 | #define MC417_SPD_CTL_MEDIUM 0x0 |
| 275 | #define MC417_SPD_CTL_FAST 0x3 /* b'1x, but we use b'11 */ |
| 276 | |
| 277 | /* Values for GPIO select */ |
| 278 | #define MC417_GPIO_SEL_GPIO3 0x3 |
| 279 | #define MC417_GPIO_SEL_GPIO2 0x2 |
| 280 | #define MC417_GPIO_SEL_GPIO1 0x1 |
| 281 | #define MC417_GPIO_SEL_GPIO0 0x0 |
| 282 | |
| 283 | void cx23885_mc417_init(struct cx23885_dev *dev) |
| 284 | { |
| 285 | u32 regval; |
| 286 | |
| 287 | dprintk(2, "%s()\n", __func__); |
| 288 | |
| 289 | /* Configure MC417_CTL register to defaults. */ |
| 290 | regval = MC417_SPD_CTL(MC417_SPD_CTL_FAST) | |
| 291 | MC417_GPIO_SEL(MC417_GPIO_SEL_GPIO3) | |
| 292 | MC417_UART_GPIO_EN; |
| 293 | cx_write(MC417_CTL, regval); |
| 294 | |
| 295 | /* Configure MC417_OEN to defaults. */ |
| 296 | regval = MC417_MIRDY; |
| 297 | cx_write(MC417_OEN, regval); |
| 298 | |
| 299 | /* Configure MC417_RWD to defaults. */ |
| 300 | regval = MC417_MIWR | MC417_MIRD | MC417_MICS; |
| 301 | cx_write(MC417_RWD, regval); |
| 302 | } |
| 303 | |
| 304 | static int mc417_wait_ready(struct cx23885_dev *dev) |
| 305 | { |
| 306 | u32 mi_ready; |
| 307 | unsigned long timeout = jiffies + msecs_to_jiffies(1); |
| 308 | |
| 309 | for (;;) { |
| 310 | mi_ready = cx_read(MC417_RWD) & MC417_MIRDY; |
| 311 | if (mi_ready != 0) |
| 312 | return 0; |
| 313 | if (time_after(jiffies, timeout)) |
| 314 | return -1; |
| 315 | udelay(1); |
| 316 | } |
| 317 | } |
| 318 | |
| 319 | static int mc417_register_write(struct cx23885_dev *dev, u16 address, u32 value) |
| 320 | { |
| 321 | u32 regval; |
| 322 | |
| 323 | /* Enable MC417 GPIO outputs except for MC417_MIRDY, |
| 324 | * which is an input. |
| 325 | */ |
| 326 | cx_write(MC417_OEN, MC417_MIRDY); |
| 327 | |
| 328 | /* Write data byte 0 */ |
| 329 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0 | |
| 330 | (value & 0x000000FF); |
| 331 | cx_write(MC417_RWD, regval); |
| 332 | |
| 333 | /* Transition CS/WR to effect write transaction across bus. */ |
| 334 | regval |= MC417_MICS | MC417_MIWR; |
| 335 | cx_write(MC417_RWD, regval); |
| 336 | |
| 337 | /* Write data byte 1 */ |
| 338 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1 | |
| 339 | ((value >> 8) & 0x000000FF); |
| 340 | cx_write(MC417_RWD, regval); |
| 341 | regval |= MC417_MICS | MC417_MIWR; |
| 342 | cx_write(MC417_RWD, regval); |
| 343 | |
| 344 | /* Write data byte 2 */ |
| 345 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2 | |
| 346 | ((value >> 16) & 0x000000FF); |
| 347 | cx_write(MC417_RWD, regval); |
| 348 | regval |= MC417_MICS | MC417_MIWR; |
| 349 | cx_write(MC417_RWD, regval); |
| 350 | |
| 351 | /* Write data byte 3 */ |
| 352 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3 | |
| 353 | ((value >> 24) & 0x000000FF); |
| 354 | cx_write(MC417_RWD, regval); |
| 355 | regval |= MC417_MICS | MC417_MIWR; |
| 356 | cx_write(MC417_RWD, regval); |
| 357 | |
| 358 | /* Write address byte 0 */ |
| 359 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE0 | |
| 360 | (address & 0xFF); |
| 361 | cx_write(MC417_RWD, regval); |
| 362 | regval |= MC417_MICS | MC417_MIWR; |
| 363 | cx_write(MC417_RWD, regval); |
| 364 | |
| 365 | /* Write address byte 1 */ |
| 366 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE1 | |
| 367 | ((address >> 8) & 0xFF); |
| 368 | cx_write(MC417_RWD, regval); |
| 369 | regval |= MC417_MICS | MC417_MIWR; |
| 370 | cx_write(MC417_RWD, regval); |
| 371 | |
| 372 | /* Indicate that this is a write. */ |
| 373 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_MODE | |
| 374 | MCI_MODE_REGISTER_WRITE; |
| 375 | cx_write(MC417_RWD, regval); |
| 376 | regval |= MC417_MICS | MC417_MIWR; |
| 377 | cx_write(MC417_RWD, regval); |
| 378 | |
| 379 | /* Wait for the trans to complete (MC417_MIRDY asserted). */ |
| 380 | return mc417_wait_ready(dev); |
| 381 | } |
| 382 | |
| 383 | static int mc417_register_read(struct cx23885_dev *dev, u16 address, u32 *value) |
| 384 | { |
| 385 | int retval; |
| 386 | u32 regval; |
| 387 | u32 tempval; |
| 388 | u32 dataval; |
| 389 | |
| 390 | /* Enable MC417 GPIO outputs except for MC417_MIRDY, |
| 391 | * which is an input. |
| 392 | */ |
| 393 | cx_write(MC417_OEN, MC417_MIRDY); |
| 394 | |
| 395 | /* Write address byte 0 */ |
| 396 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE0 | |
| 397 | ((address & 0x00FF)); |
| 398 | cx_write(MC417_RWD, regval); |
| 399 | regval |= MC417_MICS | MC417_MIWR; |
| 400 | cx_write(MC417_RWD, regval); |
| 401 | |
| 402 | /* Write address byte 1 */ |
| 403 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE1 | |
| 404 | ((address >> 8) & 0xFF); |
| 405 | cx_write(MC417_RWD, regval); |
| 406 | regval |= MC417_MICS | MC417_MIWR; |
| 407 | cx_write(MC417_RWD, regval); |
| 408 | |
| 409 | /* Indicate that this is a register read. */ |
| 410 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_MODE | |
| 411 | MCI_MODE_REGISTER_READ; |
| 412 | cx_write(MC417_RWD, regval); |
| 413 | regval |= MC417_MICS | MC417_MIWR; |
| 414 | cx_write(MC417_RWD, regval); |
| 415 | |
| 416 | /* Wait for the trans to complete (MC417_MIRDY asserted). */ |
| 417 | retval = mc417_wait_ready(dev); |
| 418 | |
| 419 | /* switch the DAT0-7 GPIO[10:3] to input mode */ |
| 420 | cx_write(MC417_OEN, MC417_MIRDY | MC417_MIDATA); |
| 421 | |
| 422 | /* Read data byte 0 */ |
| 423 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0; |
| 424 | cx_write(MC417_RWD, regval); |
| 425 | |
| 426 | /* Transition RD to effect read transaction across bus. |
| 427 | * Transtion 0x5000 -> 0x9000 correct (RD/RDY -> WR/RDY)? |
| 428 | * Should it be 0x9000 -> 0xF000 (also why is RDY being set, its |
| 429 | * input only...) |
| 430 | */ |
| 431 | regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0; |
| 432 | cx_write(MC417_RWD, regval); |
| 433 | |
| 434 | /* Collect byte */ |
| 435 | tempval = cx_read(MC417_RWD); |
| 436 | dataval = tempval & 0x000000FF; |
| 437 | |
| 438 | /* Bring CS and RD high. */ |
| 439 | regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; |
| 440 | cx_write(MC417_RWD, regval); |
| 441 | |
| 442 | /* Read data byte 1 */ |
| 443 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1; |
| 444 | cx_write(MC417_RWD, regval); |
| 445 | regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1; |
| 446 | cx_write(MC417_RWD, regval); |
| 447 | tempval = cx_read(MC417_RWD); |
| 448 | dataval |= ((tempval & 0x000000FF) << 8); |
| 449 | regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; |
| 450 | cx_write(MC417_RWD, regval); |
| 451 | |
| 452 | /* Read data byte 2 */ |
| 453 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2; |
| 454 | cx_write(MC417_RWD, regval); |
| 455 | regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2; |
| 456 | cx_write(MC417_RWD, regval); |
| 457 | tempval = cx_read(MC417_RWD); |
| 458 | dataval |= ((tempval & 0x000000FF) << 16); |
| 459 | regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; |
| 460 | cx_write(MC417_RWD, regval); |
| 461 | |
| 462 | /* Read data byte 3 */ |
| 463 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3; |
| 464 | cx_write(MC417_RWD, regval); |
| 465 | regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3; |
| 466 | cx_write(MC417_RWD, regval); |
| 467 | tempval = cx_read(MC417_RWD); |
| 468 | dataval |= ((tempval & 0x000000FF) << 24); |
| 469 | regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; |
| 470 | cx_write(MC417_RWD, regval); |
| 471 | |
| 472 | *value = dataval; |
| 473 | |
| 474 | return retval; |
| 475 | } |
| 476 | |
| 477 | int mc417_memory_write(struct cx23885_dev *dev, u32 address, u32 value) |
| 478 | { |
| 479 | u32 regval; |
| 480 | |
| 481 | /* Enable MC417 GPIO outputs except for MC417_MIRDY, |
| 482 | * which is an input. |
| 483 | */ |
| 484 | cx_write(MC417_OEN, MC417_MIRDY); |
| 485 | |
| 486 | /* Write data byte 0 */ |
| 487 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0 | |
| 488 | (value & 0x000000FF); |
| 489 | cx_write(MC417_RWD, regval); |
| 490 | |
| 491 | /* Transition CS/WR to effect write transaction across bus. */ |
| 492 | regval |= MC417_MICS | MC417_MIWR; |
| 493 | cx_write(MC417_RWD, regval); |
| 494 | |
| 495 | /* Write data byte 1 */ |
| 496 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1 | |
| 497 | ((value >> 8) & 0x000000FF); |
| 498 | cx_write(MC417_RWD, regval); |
| 499 | regval |= MC417_MICS | MC417_MIWR; |
| 500 | cx_write(MC417_RWD, regval); |
| 501 | |
| 502 | /* Write data byte 2 */ |
| 503 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2 | |
| 504 | ((value >> 16) & 0x000000FF); |
| 505 | cx_write(MC417_RWD, regval); |
| 506 | regval |= MC417_MICS | MC417_MIWR; |
| 507 | cx_write(MC417_RWD, regval); |
| 508 | |
| 509 | /* Write data byte 3 */ |
| 510 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3 | |
| 511 | ((value >> 24) & 0x000000FF); |
| 512 | cx_write(MC417_RWD, regval); |
| 513 | regval |= MC417_MICS | MC417_MIWR; |
| 514 | cx_write(MC417_RWD, regval); |
| 515 | |
| 516 | /* Write address byte 2 */ |
| 517 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE2 | |
| 518 | MCI_MODE_MEMORY_WRITE | ((address >> 16) & 0x3F); |
| 519 | cx_write(MC417_RWD, regval); |
| 520 | regval |= MC417_MICS | MC417_MIWR; |
| 521 | cx_write(MC417_RWD, regval); |
| 522 | |
| 523 | /* Write address byte 1 */ |
| 524 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE1 | |
| 525 | ((address >> 8) & 0xFF); |
| 526 | cx_write(MC417_RWD, regval); |
| 527 | regval |= MC417_MICS | MC417_MIWR; |
| 528 | cx_write(MC417_RWD, regval); |
| 529 | |
| 530 | /* Write address byte 0 */ |
| 531 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE0 | |
| 532 | (address & 0xFF); |
| 533 | cx_write(MC417_RWD, regval); |
| 534 | regval |= MC417_MICS | MC417_MIWR; |
| 535 | cx_write(MC417_RWD, regval); |
| 536 | |
| 537 | /* Wait for the trans to complete (MC417_MIRDY asserted). */ |
| 538 | return mc417_wait_ready(dev); |
| 539 | } |
| 540 | |
| 541 | int mc417_memory_read(struct cx23885_dev *dev, u32 address, u32 *value) |
| 542 | { |
| 543 | int retval; |
| 544 | u32 regval; |
| 545 | u32 tempval; |
| 546 | u32 dataval; |
| 547 | |
| 548 | /* Enable MC417 GPIO outputs except for MC417_MIRDY, |
| 549 | * which is an input. |
| 550 | */ |
| 551 | cx_write(MC417_OEN, MC417_MIRDY); |
| 552 | |
| 553 | /* Write address byte 2 */ |
| 554 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE2 | |
| 555 | MCI_MODE_MEMORY_READ | ((address >> 16) & 0x3F); |
| 556 | cx_write(MC417_RWD, regval); |
| 557 | regval |= MC417_MICS | MC417_MIWR; |
| 558 | cx_write(MC417_RWD, regval); |
| 559 | |
| 560 | /* Write address byte 1 */ |
| 561 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE1 | |
| 562 | ((address >> 8) & 0xFF); |
| 563 | cx_write(MC417_RWD, regval); |
| 564 | regval |= MC417_MICS | MC417_MIWR; |
| 565 | cx_write(MC417_RWD, regval); |
| 566 | |
| 567 | /* Write address byte 0 */ |
| 568 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE0 | |
| 569 | (address & 0xFF); |
| 570 | cx_write(MC417_RWD, regval); |
| 571 | regval |= MC417_MICS | MC417_MIWR; |
| 572 | cx_write(MC417_RWD, regval); |
| 573 | |
| 574 | /* Wait for the trans to complete (MC417_MIRDY asserted). */ |
| 575 | retval = mc417_wait_ready(dev); |
| 576 | |
| 577 | /* switch the DAT0-7 GPIO[10:3] to input mode */ |
| 578 | cx_write(MC417_OEN, MC417_MIRDY | MC417_MIDATA); |
| 579 | |
| 580 | /* Read data byte 3 */ |
| 581 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3; |
| 582 | cx_write(MC417_RWD, regval); |
| 583 | |
| 584 | /* Transition RD to effect read transaction across bus. */ |
| 585 | regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3; |
| 586 | cx_write(MC417_RWD, regval); |
| 587 | |
| 588 | /* Collect byte */ |
| 589 | tempval = cx_read(MC417_RWD); |
| 590 | dataval = ((tempval & 0x000000FF) << 24); |
| 591 | |
| 592 | /* Bring CS and RD high. */ |
| 593 | regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; |
| 594 | cx_write(MC417_RWD, regval); |
| 595 | |
| 596 | /* Read data byte 2 */ |
| 597 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2; |
| 598 | cx_write(MC417_RWD, regval); |
| 599 | regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2; |
| 600 | cx_write(MC417_RWD, regval); |
| 601 | tempval = cx_read(MC417_RWD); |
| 602 | dataval |= ((tempval & 0x000000FF) << 16); |
| 603 | regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; |
| 604 | cx_write(MC417_RWD, regval); |
| 605 | |
| 606 | /* Read data byte 1 */ |
| 607 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1; |
| 608 | cx_write(MC417_RWD, regval); |
| 609 | regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1; |
| 610 | cx_write(MC417_RWD, regval); |
| 611 | tempval = cx_read(MC417_RWD); |
| 612 | dataval |= ((tempval & 0x000000FF) << 8); |
| 613 | regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; |
| 614 | cx_write(MC417_RWD, regval); |
| 615 | |
| 616 | /* Read data byte 0 */ |
| 617 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0; |
| 618 | cx_write(MC417_RWD, regval); |
| 619 | regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0; |
| 620 | cx_write(MC417_RWD, regval); |
| 621 | tempval = cx_read(MC417_RWD); |
| 622 | dataval |= (tempval & 0x000000FF); |
| 623 | regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; |
| 624 | cx_write(MC417_RWD, regval); |
| 625 | |
| 626 | *value = dataval; |
| 627 | |
| 628 | return retval; |
| 629 | } |
| 630 | |
| 631 | /* ------------------------------------------------------------------ */ |
| 632 | |
| 633 | /* MPEG encoder API */ |
Hans Verkuil | d45b9b8 | 2008-09-04 03:33:43 -0300 | [diff] [blame] | 634 | static char *cmd_to_str(int cmd) |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 635 | { |
| 636 | switch (cmd) { |
| 637 | case CX2341X_ENC_PING_FW: |
| 638 | return "PING_FW"; |
| 639 | case CX2341X_ENC_START_CAPTURE: |
| 640 | return "START_CAPTURE"; |
| 641 | case CX2341X_ENC_STOP_CAPTURE: |
| 642 | return "STOP_CAPTURE"; |
| 643 | case CX2341X_ENC_SET_AUDIO_ID: |
| 644 | return "SET_AUDIO_ID"; |
| 645 | case CX2341X_ENC_SET_VIDEO_ID: |
| 646 | return "SET_VIDEO_ID"; |
| 647 | case CX2341X_ENC_SET_PCR_ID: |
| 648 | return "SET_PCR_PID"; |
| 649 | case CX2341X_ENC_SET_FRAME_RATE: |
| 650 | return "SET_FRAME_RATE"; |
| 651 | case CX2341X_ENC_SET_FRAME_SIZE: |
| 652 | return "SET_FRAME_SIZE"; |
| 653 | case CX2341X_ENC_SET_BIT_RATE: |
| 654 | return "SET_BIT_RATE"; |
| 655 | case CX2341X_ENC_SET_GOP_PROPERTIES: |
| 656 | return "SET_GOP_PROPERTIES"; |
| 657 | case CX2341X_ENC_SET_ASPECT_RATIO: |
| 658 | return "SET_ASPECT_RATIO"; |
| 659 | case CX2341X_ENC_SET_DNR_FILTER_MODE: |
| 660 | return "SET_DNR_FILTER_PROPS"; |
| 661 | case CX2341X_ENC_SET_DNR_FILTER_PROPS: |
| 662 | return "SET_DNR_FILTER_PROPS"; |
| 663 | case CX2341X_ENC_SET_CORING_LEVELS: |
| 664 | return "SET_CORING_LEVELS"; |
| 665 | case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE: |
| 666 | return "SET_SPATIAL_FILTER_TYPE"; |
| 667 | case CX2341X_ENC_SET_VBI_LINE: |
| 668 | return "SET_VBI_LINE"; |
| 669 | case CX2341X_ENC_SET_STREAM_TYPE: |
| 670 | return "SET_STREAM_TYPE"; |
| 671 | case CX2341X_ENC_SET_OUTPUT_PORT: |
| 672 | return "SET_OUTPUT_PORT"; |
| 673 | case CX2341X_ENC_SET_AUDIO_PROPERTIES: |
| 674 | return "SET_AUDIO_PROPERTIES"; |
| 675 | case CX2341X_ENC_HALT_FW: |
| 676 | return "HALT_FW"; |
| 677 | case CX2341X_ENC_GET_VERSION: |
| 678 | return "GET_VERSION"; |
| 679 | case CX2341X_ENC_SET_GOP_CLOSURE: |
| 680 | return "SET_GOP_CLOSURE"; |
| 681 | case CX2341X_ENC_GET_SEQ_END: |
| 682 | return "GET_SEQ_END"; |
| 683 | case CX2341X_ENC_SET_PGM_INDEX_INFO: |
| 684 | return "SET_PGM_INDEX_INFO"; |
| 685 | case CX2341X_ENC_SET_VBI_CONFIG: |
| 686 | return "SET_VBI_CONFIG"; |
| 687 | case CX2341X_ENC_SET_DMA_BLOCK_SIZE: |
| 688 | return "SET_DMA_BLOCK_SIZE"; |
| 689 | case CX2341X_ENC_GET_PREV_DMA_INFO_MB_10: |
| 690 | return "GET_PREV_DMA_INFO_MB_10"; |
| 691 | case CX2341X_ENC_GET_PREV_DMA_INFO_MB_9: |
| 692 | return "GET_PREV_DMA_INFO_MB_9"; |
| 693 | case CX2341X_ENC_SCHED_DMA_TO_HOST: |
| 694 | return "SCHED_DMA_TO_HOST"; |
| 695 | case CX2341X_ENC_INITIALIZE_INPUT: |
| 696 | return "INITIALIZE_INPUT"; |
| 697 | case CX2341X_ENC_SET_FRAME_DROP_RATE: |
| 698 | return "SET_FRAME_DROP_RATE"; |
| 699 | case CX2341X_ENC_PAUSE_ENCODER: |
| 700 | return "PAUSE_ENCODER"; |
| 701 | case CX2341X_ENC_REFRESH_INPUT: |
| 702 | return "REFRESH_INPUT"; |
| 703 | case CX2341X_ENC_SET_COPYRIGHT: |
| 704 | return "SET_COPYRIGHT"; |
| 705 | case CX2341X_ENC_SET_EVENT_NOTIFICATION: |
| 706 | return "SET_EVENT_NOTIFICATION"; |
| 707 | case CX2341X_ENC_SET_NUM_VSYNC_LINES: |
| 708 | return "SET_NUM_VSYNC_LINES"; |
| 709 | case CX2341X_ENC_SET_PLACEHOLDER: |
| 710 | return "SET_PLACEHOLDER"; |
| 711 | case CX2341X_ENC_MUTE_VIDEO: |
| 712 | return "MUTE_VIDEO"; |
| 713 | case CX2341X_ENC_MUTE_AUDIO: |
| 714 | return "MUTE_AUDIO"; |
| 715 | case CX2341X_ENC_MISC: |
| 716 | return "MISC"; |
| 717 | default: |
| 718 | return "UNKNOWN"; |
| 719 | } |
| 720 | } |
| 721 | |
| 722 | static int cx23885_mbox_func(void *priv, |
| 723 | u32 command, |
| 724 | int in, |
| 725 | int out, |
| 726 | u32 data[CX2341X_MBOX_MAX_DATA]) |
| 727 | { |
| 728 | struct cx23885_dev *dev = priv; |
| 729 | unsigned long timeout; |
| 730 | u32 value, flag, retval = 0; |
| 731 | int i; |
| 732 | |
| 733 | dprintk(3, "%s: command(0x%X) = %s\n", __func__, command, |
| 734 | cmd_to_str(command)); |
| 735 | |
| 736 | /* this may not be 100% safe if we can't read any memory location |
| 737 | without side effects */ |
| 738 | mc417_memory_read(dev, dev->cx23417_mailbox - 4, &value); |
| 739 | if (value != 0x12345678) { |
| 740 | printk(KERN_ERR |
| 741 | "Firmware and/or mailbox pointer not initialized " |
| 742 | "or corrupted, signature = 0x%x, cmd = %s\n", value, |
| 743 | cmd_to_str(command)); |
| 744 | return -1; |
| 745 | } |
| 746 | |
| 747 | /* This read looks at 32 bits, but flag is only 8 bits. |
| 748 | * Seems we also bail if CMD or TIMEOUT bytes are set??? |
| 749 | */ |
| 750 | mc417_memory_read(dev, dev->cx23417_mailbox, &flag); |
| 751 | if (flag) { |
| 752 | printk(KERN_ERR "ERROR: Mailbox appears to be in use " |
| 753 | "(%x), cmd = %s\n", flag, cmd_to_str(command)); |
| 754 | return -1; |
| 755 | } |
| 756 | |
| 757 | flag |= 1; /* tell 'em we're working on it */ |
| 758 | mc417_memory_write(dev, dev->cx23417_mailbox, flag); |
| 759 | |
| 760 | /* write command + args + fill remaining with zeros */ |
| 761 | /* command code */ |
| 762 | mc417_memory_write(dev, dev->cx23417_mailbox + 1, command); |
| 763 | mc417_memory_write(dev, dev->cx23417_mailbox + 3, |
| 764 | IVTV_API_STD_TIMEOUT); /* timeout */ |
| 765 | for (i = 0; i < in; i++) { |
| 766 | mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, data[i]); |
| 767 | dprintk(3, "API Input %d = %d\n", i, data[i]); |
| 768 | } |
| 769 | for (; i < CX2341X_MBOX_MAX_DATA; i++) |
| 770 | mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, 0); |
| 771 | |
| 772 | flag |= 3; /* tell 'em we're done writing */ |
| 773 | mc417_memory_write(dev, dev->cx23417_mailbox, flag); |
| 774 | |
| 775 | /* wait for firmware to handle the API command */ |
| 776 | timeout = jiffies + msecs_to_jiffies(10); |
| 777 | for (;;) { |
| 778 | mc417_memory_read(dev, dev->cx23417_mailbox, &flag); |
| 779 | if (0 != (flag & 4)) |
| 780 | break; |
| 781 | if (time_after(jiffies, timeout)) { |
| 782 | printk(KERN_ERR "ERROR: API Mailbox timeout\n"); |
| 783 | return -1; |
| 784 | } |
| 785 | udelay(10); |
| 786 | } |
| 787 | |
| 788 | /* read output values */ |
| 789 | for (i = 0; i < out; i++) { |
| 790 | mc417_memory_read(dev, dev->cx23417_mailbox + 4 + i, data + i); |
| 791 | dprintk(3, "API Output %d = %d\n", i, data[i]); |
| 792 | } |
| 793 | |
| 794 | mc417_memory_read(dev, dev->cx23417_mailbox + 2, &retval); |
| 795 | dprintk(3, "API result = %d\n", retval); |
| 796 | |
| 797 | flag = 0; |
| 798 | mc417_memory_write(dev, dev->cx23417_mailbox, flag); |
| 799 | |
| 800 | return retval; |
| 801 | } |
| 802 | |
| 803 | /* We don't need to call the API often, so using just one |
| 804 | * mailbox will probably suffice |
| 805 | */ |
| 806 | static int cx23885_api_cmd(struct cx23885_dev *dev, |
| 807 | u32 command, |
| 808 | u32 inputcnt, |
| 809 | u32 outputcnt, |
| 810 | ...) |
| 811 | { |
| 812 | u32 data[CX2341X_MBOX_MAX_DATA]; |
| 813 | va_list vargs; |
| 814 | int i, err; |
| 815 | |
| 816 | dprintk(3, "%s() cmds = 0x%08x\n", __func__, command); |
| 817 | |
| 818 | va_start(vargs, outputcnt); |
| 819 | for (i = 0; i < inputcnt; i++) |
| 820 | data[i] = va_arg(vargs, int); |
| 821 | |
| 822 | err = cx23885_mbox_func(dev, command, inputcnt, outputcnt, data); |
| 823 | for (i = 0; i < outputcnt; i++) { |
| 824 | int *vptr = va_arg(vargs, int *); |
| 825 | *vptr = data[i]; |
| 826 | } |
| 827 | va_end(vargs); |
| 828 | |
| 829 | return err; |
| 830 | } |
| 831 | |
| 832 | static int cx23885_find_mailbox(struct cx23885_dev *dev) |
| 833 | { |
| 834 | u32 signature[4] = { |
| 835 | 0x12345678, 0x34567812, 0x56781234, 0x78123456 |
| 836 | }; |
| 837 | int signaturecnt = 0; |
| 838 | u32 value; |
| 839 | int i; |
| 840 | |
| 841 | dprintk(2, "%s()\n", __func__); |
| 842 | |
| 843 | for (i = 0; i < CX23885_FIRM_IMAGE_SIZE; i++) { |
| 844 | mc417_memory_read(dev, i, &value); |
| 845 | if (value == signature[signaturecnt]) |
| 846 | signaturecnt++; |
| 847 | else |
| 848 | signaturecnt = 0; |
| 849 | if (4 == signaturecnt) { |
| 850 | dprintk(1, "Mailbox signature found at 0x%x\n", i+1); |
| 851 | return i+1; |
| 852 | } |
| 853 | } |
| 854 | printk(KERN_ERR "Mailbox signature values not found!\n"); |
| 855 | return -1; |
| 856 | } |
| 857 | |
| 858 | static int cx23885_load_firmware(struct cx23885_dev *dev) |
| 859 | { |
| 860 | static const unsigned char magic[8] = { |
| 861 | 0xa7, 0x0d, 0x00, 0x00, 0x66, 0xbb, 0x55, 0xaa |
| 862 | }; |
| 863 | const struct firmware *firmware; |
| 864 | int i, retval = 0; |
| 865 | u32 value = 0; |
| 866 | u32 gpio_output = 0; |
| 867 | u32 checksum = 0; |
| 868 | u32 *dataptr; |
| 869 | |
| 870 | dprintk(2, "%s()\n", __func__); |
| 871 | |
| 872 | /* Save GPIO settings before reset of APU */ |
| 873 | retval |= mc417_memory_read(dev, 0x9020, &gpio_output); |
| 874 | retval |= mc417_memory_read(dev, 0x900C, &value); |
| 875 | |
| 876 | retval = mc417_register_write(dev, |
| 877 | IVTV_REG_VPU, 0xFFFFFFED); |
| 878 | retval |= mc417_register_write(dev, |
| 879 | IVTV_REG_HW_BLOCKS, IVTV_CMD_HW_BLOCKS_RST); |
| 880 | retval |= mc417_register_write(dev, |
| 881 | IVTV_REG_ENC_SDRAM_REFRESH, 0x80000800); |
| 882 | retval |= mc417_register_write(dev, |
| 883 | IVTV_REG_ENC_SDRAM_PRECHARGE, 0x1A); |
| 884 | retval |= mc417_register_write(dev, |
| 885 | IVTV_REG_APU, 0); |
| 886 | |
| 887 | if (retval != 0) { |
| 888 | printk(KERN_ERR "%s: Error with mc417_register_write\n", |
| 889 | __func__); |
| 890 | return -1; |
| 891 | } |
| 892 | |
| 893 | retval = request_firmware(&firmware, CX23885_FIRM_IMAGE_NAME, |
| 894 | &dev->pci->dev); |
| 895 | |
| 896 | if (retval != 0) { |
| 897 | printk(KERN_ERR |
| 898 | "ERROR: Hotplug firmware request failed (%s).\n", |
Steven Toth | d35ed62 | 2009-03-28 13:58:28 -0300 | [diff] [blame] | 899 | CX23885_FIRM_IMAGE_NAME); |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 900 | printk(KERN_ERR "Please fix your hotplug setup, the board will " |
| 901 | "not work without firmware loaded!\n"); |
| 902 | return -1; |
| 903 | } |
| 904 | |
| 905 | if (firmware->size != CX23885_FIRM_IMAGE_SIZE) { |
| 906 | printk(KERN_ERR "ERROR: Firmware size mismatch " |
| 907 | "(have %zd, expected %d)\n", |
| 908 | firmware->size, CX23885_FIRM_IMAGE_SIZE); |
| 909 | release_firmware(firmware); |
| 910 | return -1; |
| 911 | } |
| 912 | |
| 913 | if (0 != memcmp(firmware->data, magic, 8)) { |
| 914 | printk(KERN_ERR |
| 915 | "ERROR: Firmware magic mismatch, wrong file?\n"); |
| 916 | release_firmware(firmware); |
| 917 | return -1; |
| 918 | } |
| 919 | |
| 920 | /* transfer to the chip */ |
| 921 | dprintk(2, "Loading firmware ...\n"); |
| 922 | dataptr = (u32 *)firmware->data; |
| 923 | for (i = 0; i < (firmware->size >> 2); i++) { |
| 924 | value = *dataptr; |
| 925 | checksum += ~value; |
| 926 | if (mc417_memory_write(dev, i, value) != 0) { |
| 927 | printk(KERN_ERR "ERROR: Loading firmware failed!\n"); |
| 928 | release_firmware(firmware); |
| 929 | return -1; |
| 930 | } |
| 931 | dataptr++; |
| 932 | } |
| 933 | |
| 934 | /* read back to verify with the checksum */ |
| 935 | dprintk(1, "Verifying firmware ...\n"); |
| 936 | for (i--; i >= 0; i--) { |
| 937 | if (mc417_memory_read(dev, i, &value) != 0) { |
| 938 | printk(KERN_ERR "ERROR: Reading firmware failed!\n"); |
| 939 | release_firmware(firmware); |
| 940 | return -1; |
| 941 | } |
| 942 | checksum -= ~value; |
| 943 | } |
| 944 | if (checksum) { |
| 945 | printk(KERN_ERR |
| 946 | "ERROR: Firmware load failed (checksum mismatch).\n"); |
| 947 | release_firmware(firmware); |
| 948 | return -1; |
| 949 | } |
| 950 | release_firmware(firmware); |
| 951 | dprintk(1, "Firmware upload successful.\n"); |
| 952 | |
| 953 | retval |= mc417_register_write(dev, IVTV_REG_HW_BLOCKS, |
| 954 | IVTV_CMD_HW_BLOCKS_RST); |
| 955 | |
| 956 | /* Restore GPIO settings, make sure EIO14 is enabled as an output. */ |
| 957 | dprintk(2, "%s: GPIO output EIO 0-15 was = 0x%x\n", |
| 958 | __func__, gpio_output); |
| 959 | /* Power-up seems to have GPIOs AFU. This was causing digital side |
| 960 | * to fail at power-up. Seems GPIOs should be set to 0x10ff0411 at |
| 961 | * power-up. |
| 962 | * gpio_output |= (1<<14); |
| 963 | */ |
| 964 | /* Note: GPIO14 is specific to the HVR1800 here */ |
| 965 | gpio_output = 0x10ff0411 | (1<<14); |
| 966 | retval |= mc417_register_write(dev, 0x9020, gpio_output | (1<<14)); |
| 967 | dprintk(2, "%s: GPIO output EIO 0-15 now = 0x%x\n", |
| 968 | __func__, gpio_output); |
| 969 | |
| 970 | dprintk(1, "%s: GPIO value EIO 0-15 was = 0x%x\n", |
| 971 | __func__, value); |
| 972 | value |= (1<<14); |
| 973 | dprintk(1, "%s: GPIO value EIO 0-15 now = 0x%x\n", |
| 974 | __func__, value); |
| 975 | retval |= mc417_register_write(dev, 0x900C, value); |
| 976 | |
| 977 | retval |= mc417_register_read(dev, IVTV_REG_VPU, &value); |
| 978 | retval |= mc417_register_write(dev, IVTV_REG_VPU, value & 0xFFFFFFE8); |
| 979 | |
| 980 | if (retval < 0) |
| 981 | printk(KERN_ERR "%s: Error with mc417_register_write\n", |
| 982 | __func__); |
| 983 | return 0; |
| 984 | } |
| 985 | |
| 986 | void cx23885_417_check_encoder(struct cx23885_dev *dev) |
| 987 | { |
| 988 | u32 status, seq; |
| 989 | |
| 990 | status = seq = 0; |
| 991 | cx23885_api_cmd(dev, CX2341X_ENC_GET_SEQ_END, 0, 2, &status, &seq); |
| 992 | dprintk(1, "%s() status = %d, seq = %d\n", __func__, status, seq); |
| 993 | } |
| 994 | |
| 995 | static void cx23885_codec_settings(struct cx23885_dev *dev) |
| 996 | { |
| 997 | dprintk(1, "%s()\n", __func__); |
| 998 | |
| 999 | /* assign frame size */ |
| 1000 | cx23885_api_cmd(dev, CX2341X_ENC_SET_FRAME_SIZE, 2, 0, |
| 1001 | dev->ts1.height, dev->ts1.width); |
| 1002 | |
| 1003 | dev->mpeg_params.width = dev->ts1.width; |
| 1004 | dev->mpeg_params.height = dev->ts1.height; |
| 1005 | dev->mpeg_params.is_50hz = |
| 1006 | (dev->encodernorm.id & V4L2_STD_625_50) != 0; |
| 1007 | |
| 1008 | cx2341x_update(dev, cx23885_mbox_func, NULL, &dev->mpeg_params); |
| 1009 | |
| 1010 | cx23885_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 3, 1); |
| 1011 | cx23885_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 4, 1); |
| 1012 | } |
| 1013 | |
| 1014 | static int cx23885_initialize_codec(struct cx23885_dev *dev) |
| 1015 | { |
| 1016 | int version; |
| 1017 | int retval; |
| 1018 | u32 i, data[7]; |
| 1019 | |
| 1020 | dprintk(1, "%s()\n", __func__); |
| 1021 | |
| 1022 | retval = cx23885_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0); /* ping */ |
| 1023 | if (retval < 0) { |
| 1024 | dprintk(2, "%s() PING OK\n", __func__); |
| 1025 | retval = cx23885_load_firmware(dev); |
| 1026 | if (retval < 0) { |
| 1027 | printk(KERN_ERR "%s() f/w load failed\n", __func__); |
| 1028 | return retval; |
| 1029 | } |
roel kluin | f347535 | 2008-11-26 22:03:18 -0300 | [diff] [blame] | 1030 | retval = cx23885_find_mailbox(dev); |
| 1031 | if (retval < 0) { |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 1032 | printk(KERN_ERR "%s() mailbox < 0, error\n", |
| 1033 | __func__); |
| 1034 | return -1; |
| 1035 | } |
roel kluin | f347535 | 2008-11-26 22:03:18 -0300 | [diff] [blame] | 1036 | dev->cx23417_mailbox = retval; |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 1037 | retval = cx23885_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0); |
| 1038 | if (retval < 0) { |
| 1039 | printk(KERN_ERR |
| 1040 | "ERROR: cx23417 firmware ping failed!\n"); |
| 1041 | return -1; |
| 1042 | } |
| 1043 | retval = cx23885_api_cmd(dev, CX2341X_ENC_GET_VERSION, 0, 1, |
| 1044 | &version); |
| 1045 | if (retval < 0) { |
| 1046 | printk(KERN_ERR "ERROR: cx23417 firmware get encoder :" |
| 1047 | "version failed!\n"); |
| 1048 | return -1; |
| 1049 | } |
| 1050 | dprintk(1, "cx23417 firmware version is 0x%08x\n", version); |
| 1051 | msleep(200); |
| 1052 | } |
| 1053 | |
| 1054 | cx23885_codec_settings(dev); |
| 1055 | msleep(60); |
| 1056 | |
| 1057 | cx23885_api_cmd(dev, CX2341X_ENC_SET_NUM_VSYNC_LINES, 2, 0, |
| 1058 | CX23885_FIELD1_SAA7115, CX23885_FIELD2_SAA7115); |
| 1059 | cx23885_api_cmd(dev, CX2341X_ENC_SET_PLACEHOLDER, 12, 0, |
| 1060 | CX23885_CUSTOM_EXTENSION_USR_DATA, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 1061 | 0, 0); |
| 1062 | |
| 1063 | /* Setup to capture VBI */ |
| 1064 | data[0] = 0x0001BD00; |
| 1065 | data[1] = 1; /* frames per interrupt */ |
| 1066 | data[2] = 4; /* total bufs */ |
| 1067 | data[3] = 0x91559155; /* start codes */ |
| 1068 | data[4] = 0x206080C0; /* stop codes */ |
| 1069 | data[5] = 6; /* lines */ |
| 1070 | data[6] = 64; /* BPL */ |
| 1071 | |
| 1072 | cx23885_api_cmd(dev, CX2341X_ENC_SET_VBI_CONFIG, 7, 0, data[0], data[1], |
| 1073 | data[2], data[3], data[4], data[5], data[6]); |
| 1074 | |
| 1075 | for (i = 2; i <= 24; i++) { |
| 1076 | int valid; |
| 1077 | |
| 1078 | valid = ((i >= 19) && (i <= 21)); |
| 1079 | cx23885_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0, i, |
| 1080 | valid, 0 , 0, 0); |
| 1081 | cx23885_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0, |
| 1082 | i | 0x80000000, valid, 0, 0, 0); |
| 1083 | } |
| 1084 | |
| 1085 | cx23885_api_cmd(dev, CX2341X_ENC_MUTE_AUDIO, 1, 0, CX23885_UNMUTE); |
| 1086 | msleep(60); |
| 1087 | |
| 1088 | /* initialize the video input */ |
| 1089 | cx23885_api_cmd(dev, CX2341X_ENC_INITIALIZE_INPUT, 0, 0); |
| 1090 | msleep(60); |
| 1091 | |
| 1092 | /* Enable VIP style pixel invalidation so we work with scaled mode */ |
| 1093 | mc417_memory_write(dev, 2120, 0x00000080); |
| 1094 | |
| 1095 | /* start capturing to the host interface */ |
| 1096 | cx23885_api_cmd(dev, CX2341X_ENC_START_CAPTURE, 2, 0, |
| 1097 | CX23885_MPEG_CAPTURE, CX23885_RAW_BITS_NONE); |
| 1098 | msleep(10); |
| 1099 | |
| 1100 | return 0; |
| 1101 | } |
| 1102 | |
| 1103 | /* ------------------------------------------------------------------ */ |
| 1104 | |
| 1105 | static int bb_buf_setup(struct videobuf_queue *q, |
| 1106 | unsigned int *count, unsigned int *size) |
| 1107 | { |
| 1108 | struct cx23885_fh *fh = q->priv_data; |
| 1109 | |
| 1110 | fh->dev->ts1.ts_packet_size = mpeglinesize; |
| 1111 | fh->dev->ts1.ts_packet_count = mpeglines; |
| 1112 | |
| 1113 | *size = fh->dev->ts1.ts_packet_size * fh->dev->ts1.ts_packet_count; |
| 1114 | *count = mpegbufs; |
| 1115 | |
| 1116 | return 0; |
| 1117 | } |
| 1118 | |
| 1119 | static int bb_buf_prepare(struct videobuf_queue *q, |
| 1120 | struct videobuf_buffer *vb, enum v4l2_field field) |
| 1121 | { |
| 1122 | struct cx23885_fh *fh = q->priv_data; |
| 1123 | return cx23885_buf_prepare(q, &fh->dev->ts1, |
| 1124 | (struct cx23885_buffer *)vb, |
| 1125 | field); |
| 1126 | } |
| 1127 | |
| 1128 | static void bb_buf_queue(struct videobuf_queue *q, |
| 1129 | struct videobuf_buffer *vb) |
| 1130 | { |
| 1131 | struct cx23885_fh *fh = q->priv_data; |
| 1132 | cx23885_buf_queue(&fh->dev->ts1, (struct cx23885_buffer *)vb); |
| 1133 | } |
| 1134 | |
| 1135 | static void bb_buf_release(struct videobuf_queue *q, |
| 1136 | struct videobuf_buffer *vb) |
| 1137 | { |
| 1138 | cx23885_free_buffer(q, (struct cx23885_buffer *)vb); |
| 1139 | } |
| 1140 | |
| 1141 | static struct videobuf_queue_ops cx23885_qops = { |
| 1142 | .buf_setup = bb_buf_setup, |
| 1143 | .buf_prepare = bb_buf_prepare, |
| 1144 | .buf_queue = bb_buf_queue, |
| 1145 | .buf_release = bb_buf_release, |
| 1146 | }; |
| 1147 | |
| 1148 | /* ------------------------------------------------------------------ */ |
| 1149 | |
| 1150 | static const u32 *ctrl_classes[] = { |
| 1151 | cx2341x_mpeg_ctrls, |
| 1152 | NULL |
| 1153 | }; |
| 1154 | |
| 1155 | static int cx23885_queryctrl(struct cx23885_dev *dev, |
| 1156 | struct v4l2_queryctrl *qctrl) |
| 1157 | { |
| 1158 | qctrl->id = v4l2_ctrl_next(ctrl_classes, qctrl->id); |
| 1159 | if (qctrl->id == 0) |
| 1160 | return -EINVAL; |
| 1161 | |
| 1162 | /* MPEG V4L2 controls */ |
| 1163 | if (cx2341x_ctrl_query(&dev->mpeg_params, qctrl)) |
| 1164 | qctrl->flags |= V4L2_CTRL_FLAG_DISABLED; |
| 1165 | |
| 1166 | return 0; |
| 1167 | } |
| 1168 | |
| 1169 | static int cx23885_querymenu(struct cx23885_dev *dev, |
| 1170 | struct v4l2_querymenu *qmenu) |
| 1171 | { |
| 1172 | struct v4l2_queryctrl qctrl; |
| 1173 | |
| 1174 | qctrl.id = qmenu->id; |
| 1175 | cx23885_queryctrl(dev, &qctrl); |
| 1176 | return v4l2_ctrl_query_menu(qmenu, &qctrl, |
Hans Verkuil | e0e31cd | 2008-06-22 12:03:28 -0300 | [diff] [blame] | 1177 | cx2341x_ctrl_get_menu(&dev->mpeg_params, qmenu->id)); |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 1178 | } |
| 1179 | |
Douglas Schilling Landgraf | 305519c | 2008-06-27 04:15:38 -0300 | [diff] [blame] | 1180 | static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id *id) |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 1181 | { |
Douglas Schilling Landgraf | 305519c | 2008-06-27 04:15:38 -0300 | [diff] [blame] | 1182 | struct cx23885_fh *fh = file->private_data; |
| 1183 | struct cx23885_dev *dev = fh->dev; |
| 1184 | unsigned int i; |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 1185 | |
Douglas Schilling Landgraf | 305519c | 2008-06-27 04:15:38 -0300 | [diff] [blame] | 1186 | for (i = 0; i < ARRAY_SIZE(cx23885_tvnorms); i++) |
| 1187 | if (*id & cx23885_tvnorms[i].id) |
| 1188 | break; |
| 1189 | if (i == ARRAY_SIZE(cx23885_tvnorms)) |
| 1190 | return -EINVAL; |
| 1191 | dev->encodernorm = cx23885_tvnorms[i]; |
| 1192 | return 0; |
| 1193 | } |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 1194 | |
Douglas Schilling Landgraf | 305519c | 2008-06-27 04:15:38 -0300 | [diff] [blame] | 1195 | static int vidioc_enum_input(struct file *file, void *priv, |
| 1196 | struct v4l2_input *i) |
| 1197 | { |
| 1198 | struct cx23885_fh *fh = file->private_data; |
| 1199 | struct cx23885_dev *dev = fh->dev; |
| 1200 | struct cx23885_input *input; |
Trent Piepho | f29816b | 2009-03-28 22:25:36 -0300 | [diff] [blame] | 1201 | int n; |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 1202 | |
Trent Piepho | f29816b | 2009-03-28 22:25:36 -0300 | [diff] [blame] | 1203 | if (i->index >= 4) |
Douglas Schilling Landgraf | 305519c | 2008-06-27 04:15:38 -0300 | [diff] [blame] | 1204 | return -EINVAL; |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 1205 | |
Trent Piepho | f29816b | 2009-03-28 22:25:36 -0300 | [diff] [blame] | 1206 | input = &cx23885_boards[dev->board].input[i->index]; |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 1207 | |
Douglas Schilling Landgraf | 305519c | 2008-06-27 04:15:38 -0300 | [diff] [blame] | 1208 | if (input->type == 0) |
| 1209 | return -EINVAL; |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 1210 | |
Douglas Schilling Landgraf | 305519c | 2008-06-27 04:15:38 -0300 | [diff] [blame] | 1211 | /* FIXME |
| 1212 | * strcpy(i->name, input->name); */ |
| 1213 | strcpy(i->name, "unset"); |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 1214 | |
Douglas Schilling Landgraf | 305519c | 2008-06-27 04:15:38 -0300 | [diff] [blame] | 1215 | if (input->type == CX23885_VMUX_TELEVISION || |
| 1216 | input->type == CX23885_VMUX_CABLE) |
| 1217 | i->type = V4L2_INPUT_TYPE_TUNER; |
| 1218 | else |
| 1219 | i->type = V4L2_INPUT_TYPE_CAMERA; |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 1220 | |
Douglas Schilling Landgraf | 305519c | 2008-06-27 04:15:38 -0300 | [diff] [blame] | 1221 | for (n = 0; n < ARRAY_SIZE(cx23885_tvnorms); n++) |
| 1222 | i->std |= cx23885_tvnorms[n].id; |
| 1223 | return 0; |
| 1224 | } |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 1225 | |
Douglas Schilling Landgraf | 305519c | 2008-06-27 04:15:38 -0300 | [diff] [blame] | 1226 | static int vidioc_g_input(struct file *file, void *priv, unsigned int *i) |
| 1227 | { |
| 1228 | struct cx23885_fh *fh = file->private_data; |
| 1229 | struct cx23885_dev *dev = fh->dev; |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 1230 | |
Douglas Schilling Landgraf | 305519c | 2008-06-27 04:15:38 -0300 | [diff] [blame] | 1231 | *i = dev->input; |
| 1232 | return 0; |
| 1233 | } |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 1234 | |
Douglas Schilling Landgraf | 305519c | 2008-06-27 04:15:38 -0300 | [diff] [blame] | 1235 | static int vidioc_s_input(struct file *file, void *priv, unsigned int i) |
| 1236 | { |
| 1237 | if (i >= 4) |
| 1238 | return -EINVAL; |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 1239 | |
| 1240 | return 0; |
| 1241 | } |
| 1242 | |
Douglas Schilling Landgraf | 305519c | 2008-06-27 04:15:38 -0300 | [diff] [blame] | 1243 | static int vidioc_g_tuner(struct file *file, void *priv, |
| 1244 | struct v4l2_tuner *t) |
| 1245 | { |
| 1246 | struct cx23885_fh *fh = file->private_data; |
| 1247 | struct cx23885_dev *dev = fh->dev; |
| 1248 | |
| 1249 | if (UNSET == dev->tuner_type) |
| 1250 | return -EINVAL; |
| 1251 | if (0 != t->index) |
| 1252 | return -EINVAL; |
Douglas Schilling Landgraf | 305519c | 2008-06-27 04:15:38 -0300 | [diff] [blame] | 1253 | strcpy(t->name, "Television"); |
Hans Verkuil | 0d5a19f | 2009-03-29 06:53:29 -0300 | [diff] [blame] | 1254 | call_all(dev, tuner, g_tuner, t); |
Douglas Schilling Landgraf | 305519c | 2008-06-27 04:15:38 -0300 | [diff] [blame] | 1255 | |
| 1256 | dprintk(1, "VIDIOC_G_TUNER: tuner type %d\n", t->type); |
| 1257 | |
| 1258 | return 0; |
| 1259 | } |
| 1260 | |
| 1261 | static int vidioc_s_tuner(struct file *file, void *priv, |
| 1262 | struct v4l2_tuner *t) |
| 1263 | { |
| 1264 | struct cx23885_fh *fh = file->private_data; |
| 1265 | struct cx23885_dev *dev = fh->dev; |
| 1266 | |
| 1267 | if (UNSET == dev->tuner_type) |
| 1268 | return -EINVAL; |
| 1269 | |
| 1270 | /* Update the A/V core */ |
Hans Verkuil | 0d5a19f | 2009-03-29 06:53:29 -0300 | [diff] [blame] | 1271 | call_all(dev, tuner, s_tuner, t); |
Douglas Schilling Landgraf | 305519c | 2008-06-27 04:15:38 -0300 | [diff] [blame] | 1272 | |
| 1273 | return 0; |
| 1274 | } |
| 1275 | |
| 1276 | static int vidioc_g_frequency(struct file *file, void *priv, |
| 1277 | struct v4l2_frequency *f) |
| 1278 | { |
| 1279 | struct cx23885_fh *fh = file->private_data; |
| 1280 | struct cx23885_dev *dev = fh->dev; |
| 1281 | |
Douglas Schilling Landgraf | 305519c | 2008-06-27 04:15:38 -0300 | [diff] [blame] | 1282 | if (UNSET == dev->tuner_type) |
| 1283 | return -EINVAL; |
| 1284 | f->type = V4L2_TUNER_ANALOG_TV; |
| 1285 | f->frequency = dev->freq; |
| 1286 | |
Hans Verkuil | 0d5a19f | 2009-03-29 06:53:29 -0300 | [diff] [blame] | 1287 | call_all(dev, tuner, g_frequency, f); |
Douglas Schilling Landgraf | 305519c | 2008-06-27 04:15:38 -0300 | [diff] [blame] | 1288 | |
| 1289 | return 0; |
| 1290 | } |
| 1291 | |
| 1292 | static int vidioc_s_frequency(struct file *file, void *priv, |
| 1293 | struct v4l2_frequency *f) |
| 1294 | { |
| 1295 | struct cx23885_fh *fh = file->private_data; |
| 1296 | struct cx23885_dev *dev = fh->dev; |
| 1297 | |
| 1298 | cx23885_api_cmd(fh->dev, CX2341X_ENC_STOP_CAPTURE, 3, 0, |
| 1299 | CX23885_END_NOW, CX23885_MPEG_CAPTURE, |
| 1300 | CX23885_RAW_BITS_NONE); |
| 1301 | |
| 1302 | dprintk(1, "VIDIOC_S_FREQUENCY: dev type %d, f\n", |
| 1303 | dev->tuner_type); |
| 1304 | dprintk(1, "VIDIOC_S_FREQUENCY: f tuner %d, f type %d\n", |
| 1305 | f->tuner, f->type); |
| 1306 | if (UNSET == dev->tuner_type) |
| 1307 | return -EINVAL; |
| 1308 | if (f->tuner != 0) |
| 1309 | return -EINVAL; |
| 1310 | if (f->type != V4L2_TUNER_ANALOG_TV) |
| 1311 | return -EINVAL; |
| 1312 | dev->freq = f->frequency; |
| 1313 | |
Hans Verkuil | 0d5a19f | 2009-03-29 06:53:29 -0300 | [diff] [blame] | 1314 | call_all(dev, tuner, s_frequency, f); |
Douglas Schilling Landgraf | 305519c | 2008-06-27 04:15:38 -0300 | [diff] [blame] | 1315 | |
| 1316 | cx23885_initialize_codec(dev); |
| 1317 | |
| 1318 | return 0; |
| 1319 | } |
| 1320 | |
| 1321 | static int vidioc_s_ctrl(struct file *file, void *priv, |
| 1322 | struct v4l2_control *ctl) |
| 1323 | { |
| 1324 | struct cx23885_fh *fh = file->private_data; |
| 1325 | struct cx23885_dev *dev = fh->dev; |
| 1326 | |
| 1327 | /* Update the A/V core */ |
Hans Verkuil | 0d5a19f | 2009-03-29 06:53:29 -0300 | [diff] [blame] | 1328 | call_all(dev, core, s_ctrl, ctl); |
Douglas Schilling Landgraf | 305519c | 2008-06-27 04:15:38 -0300 | [diff] [blame] | 1329 | return 0; |
| 1330 | } |
| 1331 | |
| 1332 | static int vidioc_querycap(struct file *file, void *priv, |
| 1333 | struct v4l2_capability *cap) |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 1334 | { |
| 1335 | struct cx23885_fh *fh = file->private_data; |
| 1336 | struct cx23885_dev *dev = fh->dev; |
| 1337 | struct cx23885_tsport *tsport = &dev->ts1; |
| 1338 | |
Douglas Schilling Landgraf | 305519c | 2008-06-27 04:15:38 -0300 | [diff] [blame] | 1339 | strcpy(cap->driver, dev->name); |
| 1340 | strlcpy(cap->card, cx23885_boards[tsport->dev->board].name, |
| 1341 | sizeof(cap->card)); |
| 1342 | sprintf(cap->bus_info, "PCI:%s", pci_name(dev->pci)); |
| 1343 | cap->version = CX23885_VERSION_CODE; |
| 1344 | cap->capabilities = |
| 1345 | V4L2_CAP_VIDEO_CAPTURE | |
| 1346 | V4L2_CAP_READWRITE | |
| 1347 | V4L2_CAP_STREAMING | |
| 1348 | 0; |
| 1349 | if (UNSET != dev->tuner_type) |
| 1350 | cap->capabilities |= V4L2_CAP_TUNER; |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 1351 | |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 1352 | return 0; |
| 1353 | } |
| 1354 | |
Douglas Schilling Landgraf | 305519c | 2008-06-27 04:15:38 -0300 | [diff] [blame] | 1355 | static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv, |
| 1356 | struct v4l2_fmtdesc *f) |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 1357 | { |
Trent Piepho | f29816b | 2009-03-28 22:25:36 -0300 | [diff] [blame] | 1358 | if (f->index != 0) |
Douglas Schilling Landgraf | 305519c | 2008-06-27 04:15:38 -0300 | [diff] [blame] | 1359 | return -EINVAL; |
| 1360 | |
Douglas Schilling Landgraf | 305519c | 2008-06-27 04:15:38 -0300 | [diff] [blame] | 1361 | strlcpy(f->description, "MPEG", sizeof(f->description)); |
Douglas Schilling Landgraf | 305519c | 2008-06-27 04:15:38 -0300 | [diff] [blame] | 1362 | f->pixelformat = V4L2_PIX_FMT_MPEG; |
| 1363 | |
| 1364 | return 0; |
| 1365 | } |
| 1366 | |
| 1367 | static int vidioc_g_fmt_vid_cap(struct file *file, void *priv, |
| 1368 | struct v4l2_format *f) |
| 1369 | { |
| 1370 | struct cx23885_fh *fh = file->private_data; |
| 1371 | struct cx23885_dev *dev = fh->dev; |
| 1372 | |
Douglas Schilling Landgraf | 305519c | 2008-06-27 04:15:38 -0300 | [diff] [blame] | 1373 | f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG; |
| 1374 | f->fmt.pix.bytesperline = 0; |
| 1375 | f->fmt.pix.sizeimage = |
| 1376 | dev->ts1.ts_packet_size * dev->ts1.ts_packet_count; |
| 1377 | f->fmt.pix.colorspace = 0; |
| 1378 | f->fmt.pix.width = dev->ts1.width; |
| 1379 | f->fmt.pix.height = dev->ts1.height; |
| 1380 | f->fmt.pix.field = fh->mpegq.field; |
| 1381 | dprintk(1, "VIDIOC_G_FMT: w: %d, h: %d, f: %d\n", |
| 1382 | dev->ts1.width, dev->ts1.height, fh->mpegq.field); |
| 1383 | return 0; |
| 1384 | } |
| 1385 | |
| 1386 | static int vidioc_try_fmt_vid_cap(struct file *file, void *priv, |
| 1387 | struct v4l2_format *f) |
| 1388 | { |
| 1389 | struct cx23885_fh *fh = file->private_data; |
| 1390 | struct cx23885_dev *dev = fh->dev; |
| 1391 | |
Douglas Schilling Landgraf | 305519c | 2008-06-27 04:15:38 -0300 | [diff] [blame] | 1392 | f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG; |
| 1393 | f->fmt.pix.bytesperline = 0; |
| 1394 | f->fmt.pix.sizeimage = |
| 1395 | dev->ts1.ts_packet_size * dev->ts1.ts_packet_count; |
Douglas Schilling Landgraf | 305519c | 2008-06-27 04:15:38 -0300 | [diff] [blame] | 1396 | f->fmt.pix.colorspace = 0; |
| 1397 | dprintk(1, "VIDIOC_TRY_FMT: w: %d, h: %d, f: %d\n", |
| 1398 | dev->ts1.width, dev->ts1.height, fh->mpegq.field); |
| 1399 | return 0; |
| 1400 | } |
| 1401 | |
| 1402 | static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, |
| 1403 | struct v4l2_format *f) |
| 1404 | { |
| 1405 | struct cx23885_fh *fh = file->private_data; |
| 1406 | struct cx23885_dev *dev = fh->dev; |
| 1407 | |
Douglas Schilling Landgraf | 305519c | 2008-06-27 04:15:38 -0300 | [diff] [blame] | 1408 | f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG; |
| 1409 | f->fmt.pix.bytesperline = 0; |
| 1410 | f->fmt.pix.sizeimage = |
| 1411 | dev->ts1.ts_packet_size * dev->ts1.ts_packet_count; |
| 1412 | f->fmt.pix.colorspace = 0; |
| 1413 | dprintk(1, "VIDIOC_S_FMT: w: %d, h: %d, f: %d\n", |
| 1414 | f->fmt.pix.width, f->fmt.pix.height, f->fmt.pix.field); |
| 1415 | return 0; |
| 1416 | } |
| 1417 | |
| 1418 | static int vidioc_reqbufs(struct file *file, void *priv, |
| 1419 | struct v4l2_requestbuffers *p) |
| 1420 | { |
| 1421 | struct cx23885_fh *fh = file->private_data; |
| 1422 | |
| 1423 | return videobuf_reqbufs(&fh->mpegq, p); |
| 1424 | } |
| 1425 | |
| 1426 | static int vidioc_querybuf(struct file *file, void *priv, |
| 1427 | struct v4l2_buffer *p) |
| 1428 | { |
| 1429 | struct cx23885_fh *fh = file->private_data; |
| 1430 | |
| 1431 | return videobuf_querybuf(&fh->mpegq, p); |
| 1432 | } |
| 1433 | |
| 1434 | static int vidioc_qbuf(struct file *file, void *priv, |
| 1435 | struct v4l2_buffer *p) |
| 1436 | { |
| 1437 | struct cx23885_fh *fh = file->private_data; |
| 1438 | |
| 1439 | return videobuf_qbuf(&fh->mpegq, p); |
| 1440 | } |
| 1441 | |
| 1442 | static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *b) |
| 1443 | { |
| 1444 | struct cx23885_fh *fh = priv; |
| 1445 | |
| 1446 | return videobuf_dqbuf(&fh->mpegq, b, file->f_flags & O_NONBLOCK); |
| 1447 | } |
| 1448 | |
| 1449 | |
| 1450 | static int vidioc_streamon(struct file *file, void *priv, |
| 1451 | enum v4l2_buf_type i) |
| 1452 | { |
| 1453 | struct cx23885_fh *fh = file->private_data; |
| 1454 | |
| 1455 | return videobuf_streamon(&fh->mpegq); |
| 1456 | } |
| 1457 | |
| 1458 | static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) |
| 1459 | { |
| 1460 | struct cx23885_fh *fh = file->private_data; |
| 1461 | |
| 1462 | return videobuf_streamoff(&fh->mpegq); |
| 1463 | } |
| 1464 | |
| 1465 | static int vidioc_g_ext_ctrls(struct file *file, void *priv, |
| 1466 | struct v4l2_ext_controls *f) |
| 1467 | { |
| 1468 | struct cx23885_fh *fh = priv; |
| 1469 | struct cx23885_dev *dev = fh->dev; |
| 1470 | |
| 1471 | if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG) |
| 1472 | return -EINVAL; |
| 1473 | return cx2341x_ext_ctrls(&dev->mpeg_params, 0, f, VIDIOC_G_EXT_CTRLS); |
| 1474 | } |
| 1475 | |
| 1476 | static int vidioc_s_ext_ctrls(struct file *file, void *priv, |
| 1477 | struct v4l2_ext_controls *f) |
| 1478 | { |
| 1479 | struct cx23885_fh *fh = priv; |
| 1480 | struct cx23885_dev *dev = fh->dev; |
| 1481 | struct cx2341x_mpeg_params p; |
| 1482 | int err; |
| 1483 | |
| 1484 | if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG) |
| 1485 | return -EINVAL; |
| 1486 | |
| 1487 | p = dev->mpeg_params; |
| 1488 | err = cx2341x_ext_ctrls(&p, 0, f, VIDIOC_S_EXT_CTRLS); |
| 1489 | |
| 1490 | if (err == 0) { |
| 1491 | err = cx2341x_update(dev, cx23885_mbox_func, |
| 1492 | &dev->mpeg_params, &p); |
| 1493 | dev->mpeg_params = p; |
| 1494 | } |
| 1495 | return err; |
| 1496 | } |
| 1497 | |
| 1498 | static int vidioc_try_ext_ctrls(struct file *file, void *priv, |
| 1499 | struct v4l2_ext_controls *f) |
| 1500 | { |
| 1501 | struct cx23885_fh *fh = priv; |
| 1502 | struct cx23885_dev *dev = fh->dev; |
| 1503 | struct cx2341x_mpeg_params p; |
| 1504 | int err; |
| 1505 | |
| 1506 | if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG) |
| 1507 | return -EINVAL; |
| 1508 | |
| 1509 | p = dev->mpeg_params; |
| 1510 | err = cx2341x_ext_ctrls(&p, 0, f, VIDIOC_TRY_EXT_CTRLS); |
| 1511 | return err; |
| 1512 | } |
| 1513 | |
| 1514 | static int vidioc_log_status(struct file *file, void *priv) |
| 1515 | { |
| 1516 | struct cx23885_fh *fh = priv; |
| 1517 | struct cx23885_dev *dev = fh->dev; |
| 1518 | char name[32 + 2]; |
| 1519 | |
| 1520 | snprintf(name, sizeof(name), "%s/2", dev->name); |
| 1521 | printk(KERN_INFO |
| 1522 | "%s/2: ============ START LOG STATUS ============\n", |
| 1523 | dev->name); |
Hans Verkuil | 0d5a19f | 2009-03-29 06:53:29 -0300 | [diff] [blame] | 1524 | call_all(dev, core, log_status); |
Douglas Schilling Landgraf | 305519c | 2008-06-27 04:15:38 -0300 | [diff] [blame] | 1525 | cx2341x_log_status(&dev->mpeg_params, name); |
| 1526 | printk(KERN_INFO |
| 1527 | "%s/2: ============= END LOG STATUS =============\n", |
| 1528 | dev->name); |
| 1529 | return 0; |
| 1530 | } |
| 1531 | |
| 1532 | static int vidioc_querymenu(struct file *file, void *priv, |
| 1533 | struct v4l2_querymenu *a) |
| 1534 | { |
| 1535 | struct cx23885_fh *fh = priv; |
| 1536 | struct cx23885_dev *dev = fh->dev; |
| 1537 | |
| 1538 | return cx23885_querymenu(dev, a); |
| 1539 | } |
| 1540 | |
| 1541 | static int vidioc_queryctrl(struct file *file, void *priv, |
| 1542 | struct v4l2_queryctrl *c) |
| 1543 | { |
| 1544 | struct cx23885_fh *fh = priv; |
| 1545 | struct cx23885_dev *dev = fh->dev; |
| 1546 | |
| 1547 | return cx23885_queryctrl(dev, c); |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 1548 | } |
| 1549 | |
Hans Verkuil | bec4366 | 2008-12-30 06:58:20 -0300 | [diff] [blame] | 1550 | static int mpeg_open(struct file *file) |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 1551 | { |
Hans Verkuil | bec4366 | 2008-12-30 06:58:20 -0300 | [diff] [blame] | 1552 | int minor = video_devdata(file)->minor; |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 1553 | struct cx23885_dev *h, *dev = NULL; |
| 1554 | struct list_head *list; |
| 1555 | struct cx23885_fh *fh; |
| 1556 | |
| 1557 | dprintk(2, "%s()\n", __func__); |
| 1558 | |
Hans Verkuil | d56dc61 | 2008-07-30 08:43:36 -0300 | [diff] [blame] | 1559 | lock_kernel(); |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 1560 | list_for_each(list, &cx23885_devlist) { |
| 1561 | h = list_entry(list, struct cx23885_dev, devlist); |
Andy Walls | cd8f894 | 2009-01-09 22:59:27 -0300 | [diff] [blame] | 1562 | if (h->v4l_device && |
| 1563 | h->v4l_device->minor == minor) { |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 1564 | dev = h; |
| 1565 | break; |
| 1566 | } |
| 1567 | } |
| 1568 | |
Hans Verkuil | d56dc61 | 2008-07-30 08:43:36 -0300 | [diff] [blame] | 1569 | if (dev == NULL) { |
| 1570 | unlock_kernel(); |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 1571 | return -ENODEV; |
Hans Verkuil | d56dc61 | 2008-07-30 08:43:36 -0300 | [diff] [blame] | 1572 | } |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 1573 | |
| 1574 | /* allocate + initialize per filehandle data */ |
| 1575 | fh = kzalloc(sizeof(*fh), GFP_KERNEL); |
Hans Verkuil | d56dc61 | 2008-07-30 08:43:36 -0300 | [diff] [blame] | 1576 | if (NULL == fh) { |
| 1577 | unlock_kernel(); |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 1578 | return -ENOMEM; |
Hans Verkuil | d56dc61 | 2008-07-30 08:43:36 -0300 | [diff] [blame] | 1579 | } |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 1580 | |
| 1581 | file->private_data = fh; |
| 1582 | fh->dev = dev; |
| 1583 | |
| 1584 | videobuf_queue_sg_init(&fh->mpegq, &cx23885_qops, |
| 1585 | &dev->pci->dev, &dev->ts1.slock, |
| 1586 | V4L2_BUF_TYPE_VIDEO_CAPTURE, |
| 1587 | V4L2_FIELD_INTERLACED, |
| 1588 | sizeof(struct cx23885_buffer), |
| 1589 | fh); |
Hans Verkuil | d56dc61 | 2008-07-30 08:43:36 -0300 | [diff] [blame] | 1590 | unlock_kernel(); |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 1591 | |
| 1592 | return 0; |
| 1593 | } |
| 1594 | |
Hans Verkuil | bec4366 | 2008-12-30 06:58:20 -0300 | [diff] [blame] | 1595 | static int mpeg_release(struct file *file) |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 1596 | { |
| 1597 | struct cx23885_fh *fh = file->private_data; |
| 1598 | struct cx23885_dev *dev = fh->dev; |
| 1599 | |
| 1600 | dprintk(2, "%s()\n", __func__); |
| 1601 | |
| 1602 | /* FIXME: Review this crap */ |
| 1603 | /* Shut device down on last close */ |
| 1604 | if (atomic_cmpxchg(&fh->v4l_reading, 1, 0) == 1) { |
| 1605 | if (atomic_dec_return(&dev->v4l_reader_count) == 0) { |
| 1606 | /* stop mpeg capture */ |
| 1607 | cx23885_api_cmd(fh->dev, CX2341X_ENC_STOP_CAPTURE, 3, 0, |
| 1608 | CX23885_END_NOW, CX23885_MPEG_CAPTURE, |
| 1609 | CX23885_RAW_BITS_NONE); |
| 1610 | |
| 1611 | msleep(500); |
| 1612 | cx23885_417_check_encoder(dev); |
| 1613 | |
| 1614 | cx23885_cancel_buffers(&fh->dev->ts1); |
| 1615 | } |
| 1616 | } |
| 1617 | |
| 1618 | if (fh->mpegq.streaming) |
| 1619 | videobuf_streamoff(&fh->mpegq); |
| 1620 | if (fh->mpegq.reading) |
| 1621 | videobuf_read_stop(&fh->mpegq); |
| 1622 | |
| 1623 | videobuf_mmap_free(&fh->mpegq); |
| 1624 | file->private_data = NULL; |
| 1625 | kfree(fh); |
| 1626 | |
| 1627 | return 0; |
| 1628 | } |
| 1629 | |
| 1630 | static ssize_t mpeg_read(struct file *file, char __user *data, |
| 1631 | size_t count, loff_t *ppos) |
| 1632 | { |
| 1633 | struct cx23885_fh *fh = file->private_data; |
| 1634 | struct cx23885_dev *dev = fh->dev; |
| 1635 | |
| 1636 | dprintk(2, "%s()\n", __func__); |
| 1637 | |
| 1638 | /* Deal w/ A/V decoder * and mpeg encoder sync issues. */ |
| 1639 | /* Start mpeg encoder on first read. */ |
| 1640 | if (atomic_cmpxchg(&fh->v4l_reading, 0, 1) == 0) { |
| 1641 | if (atomic_inc_return(&dev->v4l_reader_count) == 1) { |
| 1642 | if (cx23885_initialize_codec(dev) < 0) |
| 1643 | return -EINVAL; |
| 1644 | } |
| 1645 | } |
| 1646 | |
| 1647 | return videobuf_read_stream(&fh->mpegq, data, count, ppos, 0, |
| 1648 | file->f_flags & O_NONBLOCK); |
| 1649 | } |
| 1650 | |
| 1651 | static unsigned int mpeg_poll(struct file *file, |
| 1652 | struct poll_table_struct *wait) |
| 1653 | { |
| 1654 | struct cx23885_fh *fh = file->private_data; |
| 1655 | struct cx23885_dev *dev = fh->dev; |
| 1656 | |
| 1657 | dprintk(2, "%s\n", __func__); |
| 1658 | |
| 1659 | return videobuf_poll_stream(file, &fh->mpegq, wait); |
| 1660 | } |
| 1661 | |
| 1662 | static int mpeg_mmap(struct file *file, struct vm_area_struct *vma) |
| 1663 | { |
| 1664 | struct cx23885_fh *fh = file->private_data; |
| 1665 | struct cx23885_dev *dev = fh->dev; |
| 1666 | |
| 1667 | dprintk(2, "%s()\n", __func__); |
| 1668 | |
| 1669 | return videobuf_mmap_mapper(&fh->mpegq, vma); |
| 1670 | } |
| 1671 | |
Hans Verkuil | bec4366 | 2008-12-30 06:58:20 -0300 | [diff] [blame] | 1672 | static struct v4l2_file_operations mpeg_fops = { |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 1673 | .owner = THIS_MODULE, |
| 1674 | .open = mpeg_open, |
| 1675 | .release = mpeg_release, |
| 1676 | .read = mpeg_read, |
| 1677 | .poll = mpeg_poll, |
| 1678 | .mmap = mpeg_mmap, |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 1679 | }; |
| 1680 | |
Hans Verkuil | a399810 | 2008-07-21 02:57:38 -0300 | [diff] [blame] | 1681 | static const struct v4l2_ioctl_ops mpeg_ioctl_ops = { |
Douglas Schilling Landgraf | 305519c | 2008-06-27 04:15:38 -0300 | [diff] [blame] | 1682 | .vidioc_s_std = vidioc_s_std, |
| 1683 | .vidioc_enum_input = vidioc_enum_input, |
| 1684 | .vidioc_g_input = vidioc_g_input, |
| 1685 | .vidioc_s_input = vidioc_s_input, |
| 1686 | .vidioc_g_tuner = vidioc_g_tuner, |
| 1687 | .vidioc_s_tuner = vidioc_s_tuner, |
| 1688 | .vidioc_g_frequency = vidioc_g_frequency, |
| 1689 | .vidioc_s_frequency = vidioc_s_frequency, |
| 1690 | .vidioc_s_ctrl = vidioc_s_ctrl, |
| 1691 | .vidioc_querycap = vidioc_querycap, |
| 1692 | .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, |
| 1693 | .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, |
| 1694 | .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, |
| 1695 | .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, |
| 1696 | .vidioc_reqbufs = vidioc_reqbufs, |
| 1697 | .vidioc_querybuf = vidioc_querybuf, |
| 1698 | .vidioc_qbuf = vidioc_qbuf, |
| 1699 | .vidioc_dqbuf = vidioc_dqbuf, |
| 1700 | .vidioc_streamon = vidioc_streamon, |
| 1701 | .vidioc_streamoff = vidioc_streamoff, |
| 1702 | .vidioc_g_ext_ctrls = vidioc_g_ext_ctrls, |
| 1703 | .vidioc_s_ext_ctrls = vidioc_s_ext_ctrls, |
| 1704 | .vidioc_try_ext_ctrls = vidioc_try_ext_ctrls, |
| 1705 | .vidioc_log_status = vidioc_log_status, |
| 1706 | .vidioc_querymenu = vidioc_querymenu, |
| 1707 | .vidioc_queryctrl = vidioc_queryctrl, |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 1708 | }; |
| 1709 | |
Hans Verkuil | a399810 | 2008-07-21 02:57:38 -0300 | [diff] [blame] | 1710 | static struct video_device cx23885_mpeg_template = { |
| 1711 | .name = "cx23885", |
Hans Verkuil | a399810 | 2008-07-21 02:57:38 -0300 | [diff] [blame] | 1712 | .fops = &mpeg_fops, |
| 1713 | .ioctl_ops = &mpeg_ioctl_ops, |
| 1714 | .minor = -1, |
| 1715 | }; |
| 1716 | |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 1717 | void cx23885_417_unregister(struct cx23885_dev *dev) |
| 1718 | { |
| 1719 | dprintk(1, "%s()\n", __func__); |
| 1720 | |
| 1721 | if (dev->v4l_device) { |
| 1722 | if (-1 != dev->v4l_device->minor) |
| 1723 | video_unregister_device(dev->v4l_device); |
| 1724 | else |
| 1725 | video_device_release(dev->v4l_device); |
| 1726 | dev->v4l_device = NULL; |
| 1727 | } |
| 1728 | } |
| 1729 | |
| 1730 | static struct video_device *cx23885_video_dev_alloc( |
| 1731 | struct cx23885_tsport *tsport, |
| 1732 | struct pci_dev *pci, |
| 1733 | struct video_device *template, |
| 1734 | char *type) |
| 1735 | { |
| 1736 | struct video_device *vfd; |
| 1737 | struct cx23885_dev *dev = tsport->dev; |
| 1738 | |
| 1739 | dprintk(1, "%s()\n", __func__); |
| 1740 | |
| 1741 | vfd = video_device_alloc(); |
| 1742 | if (NULL == vfd) |
| 1743 | return NULL; |
| 1744 | *vfd = *template; |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 1745 | snprintf(vfd->name, sizeof(vfd->name), "%s %s (%s)", dev->name, |
| 1746 | type, cx23885_boards[tsport->dev->board].name); |
Hans Verkuil | 5e85e73 | 2008-07-20 06:31:39 -0300 | [diff] [blame] | 1747 | vfd->parent = &pci->dev; |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 1748 | vfd->release = video_device_release; |
| 1749 | return vfd; |
| 1750 | } |
| 1751 | |
| 1752 | int cx23885_417_register(struct cx23885_dev *dev) |
| 1753 | { |
| 1754 | /* FIXME: Port1 hardcoded here */ |
| 1755 | int err = -ENODEV; |
| 1756 | struct cx23885_tsport *tsport = &dev->ts1; |
| 1757 | |
| 1758 | dprintk(1, "%s()\n", __func__); |
| 1759 | |
| 1760 | if (cx23885_boards[dev->board].portb != CX23885_MPEG_ENCODER) |
| 1761 | return err; |
| 1762 | |
| 1763 | /* Set default TV standard */ |
| 1764 | dev->encodernorm = cx23885_tvnorms[0]; |
| 1765 | |
| 1766 | if (dev->encodernorm.id & V4L2_STD_525_60) |
| 1767 | tsport->height = 480; |
| 1768 | else |
| 1769 | tsport->height = 576; |
| 1770 | |
| 1771 | tsport->width = 720; |
| 1772 | cx2341x_fill_defaults(&dev->mpeg_params); |
| 1773 | |
| 1774 | dev->mpeg_params.port = CX2341X_PORT_SERIAL; |
| 1775 | |
| 1776 | /* Allocate and initialize V4L video device */ |
| 1777 | dev->v4l_device = cx23885_video_dev_alloc(tsport, |
| 1778 | dev->pci, &cx23885_mpeg_template, "mpeg"); |
| 1779 | err = video_register_device(dev->v4l_device, |
| 1780 | VFL_TYPE_GRABBER, -1); |
| 1781 | if (err < 0) { |
| 1782 | printk(KERN_INFO "%s: can't register mpeg device\n", dev->name); |
| 1783 | return err; |
| 1784 | } |
| 1785 | |
| 1786 | /* Initialize MC417 registers */ |
| 1787 | cx23885_mc417_init(dev); |
| 1788 | |
| 1789 | printk(KERN_INFO "%s: registered device video%d [mpeg]\n", |
Hans Verkuil | c6330fb | 2008-10-19 18:54:26 -0300 | [diff] [blame] | 1790 | dev->name, dev->v4l_device->num); |
Steven Toth | b1b81f1 | 2008-01-13 23:42:44 -0300 | [diff] [blame] | 1791 | |
| 1792 | return 0; |
| 1793 | } |