Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1 | /* |
Dhananjay Phadke | 5d242f1 | 2009-02-25 15:57:56 +0000 | [diff] [blame] | 2 | * Copyright (C) 2003 - 2009 NetXen, Inc. |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 3 | * All rights reserved. |
Amit S. Kale | 80922fb | 2006-12-04 09:18:00 -0800 | [diff] [blame] | 4 | * |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 5 | * This program is free software; you can redistribute it and/or |
| 6 | * modify it under the terms of the GNU General Public License |
| 7 | * as published by the Free Software Foundation; either version 2 |
| 8 | * of the License, or (at your option) any later version. |
Amit S. Kale | 80922fb | 2006-12-04 09:18:00 -0800 | [diff] [blame] | 9 | * |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 10 | * This program is distributed in the hope that it will be useful, but |
| 11 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Amit S. Kale | 80922fb | 2006-12-04 09:18:00 -0800 | [diff] [blame] | 14 | * |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, |
| 18 | * MA 02111-1307, USA. |
Amit S. Kale | 80922fb | 2006-12-04 09:18:00 -0800 | [diff] [blame] | 19 | * |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 20 | * The full GNU General Public License is included in this distribution |
| 21 | * in the file called LICENSE. |
Amit S. Kale | 80922fb | 2006-12-04 09:18:00 -0800 | [diff] [blame] | 22 | * |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 23 | * Contact Information: |
| 24 | * info@netxen.com |
Dhananjay Phadke | 5d242f1 | 2009-02-25 15:57:56 +0000 | [diff] [blame] | 25 | * NetXen Inc, |
| 26 | * 18922 Forge Drive |
| 27 | * Cupertino, CA 95014-0701 |
| 28 | * |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 29 | */ |
| 30 | |
| 31 | #ifndef _NETXEN_NIC_H_ |
| 32 | #define _NETXEN_NIC_H_ |
| 33 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 34 | #include <linux/module.h> |
| 35 | #include <linux/kernel.h> |
| 36 | #include <linux/types.h> |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 37 | #include <linux/ioport.h> |
| 38 | #include <linux/pci.h> |
| 39 | #include <linux/netdevice.h> |
| 40 | #include <linux/etherdevice.h> |
| 41 | #include <linux/ip.h> |
| 42 | #include <linux/in.h> |
| 43 | #include <linux/tcp.h> |
| 44 | #include <linux/skbuff.h> |
Dhananjay Phadke | f7185c7 | 2009-04-28 15:29:11 +0000 | [diff] [blame] | 45 | #include <linux/firmware.h> |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 46 | |
| 47 | #include <linux/ethtool.h> |
| 48 | #include <linux/mii.h> |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 49 | #include <linux/timer.h> |
| 50 | |
David S. Miller | 4255589 | 2008-07-22 18:29:10 -0700 | [diff] [blame] | 51 | #include <linux/vmalloc.h> |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 52 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 53 | #include <asm/io.h> |
| 54 | #include <asm/byteorder.h> |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 55 | |
| 56 | #include "netxen_nic_hw.h" |
| 57 | |
Dhananjay Phadke | 5873556 | 2008-07-21 19:44:10 -0700 | [diff] [blame] | 58 | #define _NETXEN_NIC_LINUX_MAJOR 4 |
| 59 | #define _NETXEN_NIC_LINUX_MINOR 0 |
Dhananjay Phadke | ff4fbd4 | 2009-03-13 14:52:06 +0000 | [diff] [blame] | 60 | #define _NETXEN_NIC_LINUX_SUBVERSION 30 |
| 61 | #define NETXEN_NIC_LINUX_VERSIONID "4.0.30" |
Dhananjay Phadke | 5873556 | 2008-07-21 19:44:10 -0700 | [diff] [blame] | 62 | |
Dhananjay Phadke | 98e31bb | 2009-07-01 11:41:42 +0000 | [diff] [blame] | 63 | #define NETXEN_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c)) |
| 64 | #define _major(v) (((v) >> 24) & 0xff) |
| 65 | #define _minor(v) (((v) >> 16) & 0xff) |
| 66 | #define _build(v) ((v) & 0xffff) |
| 67 | |
| 68 | /* version in image has weird encoding: |
| 69 | * 7:0 - major |
| 70 | * 15:8 - minor |
| 71 | * 31:16 - build (little endian) |
| 72 | */ |
| 73 | #define NETXEN_DECODE_VERSION(v) \ |
| 74 | NETXEN_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16)) |
Amit S. Kale | 27d2ab5 | 2007-02-05 07:40:49 -0800 | [diff] [blame] | 75 | |
Mithlesh Thukral | 0d04761 | 2007-06-07 04:36:36 -0700 | [diff] [blame] | 76 | #define NETXEN_NUM_FLASH_SECTORS (64) |
| 77 | #define NETXEN_FLASH_SECTOR_SIZE (64 * 1024) |
| 78 | #define NETXEN_FLASH_TOTAL_SIZE (NETXEN_NUM_FLASH_SECTORS \ |
| 79 | * NETXEN_FLASH_SECTOR_SIZE) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 80 | |
Linsys Contractor Mithlesh Thukral | 0c25cfe | 2007-02-28 05:14:07 -0800 | [diff] [blame] | 81 | #define PHAN_VENDOR_ID 0x4040 |
| 82 | |
Dhananjay Phadke | d8b100c | 2009-03-13 14:52:05 +0000 | [diff] [blame] | 83 | #define RCV_DESC_RINGSIZE(rds_ring) \ |
| 84 | (sizeof(struct rcv_desc) * (rds_ring)->num_desc) |
| 85 | #define RCV_BUFF_RINGSIZE(rds_ring) \ |
Dhananjay Phadke | 438627c | 2009-03-13 14:52:03 +0000 | [diff] [blame] | 86 | (sizeof(struct netxen_rx_buffer) * rds_ring->num_desc) |
Dhananjay Phadke | d8b100c | 2009-03-13 14:52:05 +0000 | [diff] [blame] | 87 | #define STATUS_DESC_RINGSIZE(sds_ring) \ |
| 88 | (sizeof(struct status_desc) * (sds_ring)->num_desc) |
Dhananjay Phadke | d877f1e | 2009-04-07 22:50:40 +0000 | [diff] [blame] | 89 | #define TX_BUFF_RINGSIZE(tx_ring) \ |
| 90 | (sizeof(struct netxen_cmd_buffer) * tx_ring->num_desc) |
| 91 | #define TX_DESC_RINGSIZE(tx_ring) \ |
| 92 | (sizeof(struct cmd_desc_type0) * tx_ring->num_desc) |
Dhananjay Phadke | d8b100c | 2009-03-13 14:52:05 +0000 | [diff] [blame] | 93 | |
Dhananjay Phadke | ba53e6b | 2008-03-17 19:59:50 -0700 | [diff] [blame] | 94 | #define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a))) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 95 | |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 96 | #define NETXEN_RCV_PRODUCER_OFFSET 0 |
| 97 | #define NETXEN_RCV_PEG_DB_ID 2 |
| 98 | #define NETXEN_HOST_DUMMY_DMA_SIZE 1024 |
Amit S. Kale | 27d2ab5 | 2007-02-05 07:40:49 -0800 | [diff] [blame] | 99 | #define FLASH_SUCCESS 0 |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 100 | |
| 101 | #define ADDR_IN_WINDOW1(off) \ |
| 102 | ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0 |
| 103 | |
Jeff Garzik | 4790654 | 2007-11-23 21:23:36 -0500 | [diff] [blame] | 104 | /* |
| 105 | * normalize a 64MB crb address to 32MB PCI window |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 106 | * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1 |
| 107 | */ |
Amit S. Kale | 80922fb | 2006-12-04 09:18:00 -0800 | [diff] [blame] | 108 | #define NETXEN_CRB_NORMAL(reg) \ |
| 109 | ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST) |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 110 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 111 | #define NETXEN_CRB_NORMALIZE(adapter, reg) \ |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 112 | pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg)) |
| 113 | |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 114 | #define DB_NORMALIZE(adapter, off) \ |
| 115 | (adapter->ahw.db_base + (off)) |
| 116 | |
| 117 | #define NX_P2_C0 0x24 |
| 118 | #define NX_P2_C1 0x25 |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 119 | #define NX_P3_A0 0x30 |
| 120 | #define NX_P3_A2 0x30 |
| 121 | #define NX_P3_B0 0x40 |
| 122 | #define NX_P3_B1 0x41 |
Dhananjay Phadke | e98e335 | 2009-04-07 22:50:38 +0000 | [diff] [blame] | 123 | #define NX_P3_B2 0x42 |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 124 | |
| 125 | #define NX_IS_REVISION_P2(REVISION) (REVISION <= NX_P2_C1) |
| 126 | #define NX_IS_REVISION_P3(REVISION) (REVISION >= NX_P3_A0) |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 127 | |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 128 | #define FIRST_PAGE_GROUP_START 0 |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 129 | #define FIRST_PAGE_GROUP_END 0x100000 |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 130 | |
Mithlesh Thukral | 78403a9 | 2007-04-20 07:57:26 -0700 | [diff] [blame] | 131 | #define SECOND_PAGE_GROUP_START 0x6000000 |
| 132 | #define SECOND_PAGE_GROUP_END 0x68BC000 |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 133 | |
| 134 | #define THIRD_PAGE_GROUP_START 0x70E4000 |
| 135 | #define THIRD_PAGE_GROUP_END 0x8000000 |
| 136 | |
| 137 | #define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START |
| 138 | #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START |
| 139 | #define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 140 | |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 141 | #define P2_MAX_MTU (8000) |
| 142 | #define P3_MAX_MTU (9600) |
| 143 | #define NX_ETHERMTU 1500 |
| 144 | #define NX_MAX_ETHERHDR 32 /* This contains some padding */ |
| 145 | |
| 146 | #define NX_RX_NORMAL_BUF_MAX_LEN (NX_MAX_ETHERHDR + NX_ETHERMTU) |
| 147 | #define NX_P2_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P2_MAX_MTU) |
| 148 | #define NX_P3_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P3_MAX_MTU) |
Dhananjay Phadke | d9e651b | 2008-07-21 19:44:08 -0700 | [diff] [blame] | 149 | #define NX_CT_DEFAULT_RX_BUF_LEN 2048 |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 150 | |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 151 | #define MAX_RX_BUFFER_LENGTH 1760 |
Amit S. Kale | bd56c6b | 2006-12-18 05:54:36 -0800 | [diff] [blame] | 152 | #define MAX_RX_JUMBO_BUFFER_LENGTH 8062 |
Dhananjay Phadke | 32ec803 | 2009-01-26 12:35:19 -0800 | [diff] [blame] | 153 | #define MAX_RX_LRO_BUFFER_LENGTH (8062) |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 154 | #define RX_DMA_MAP_LEN (MAX_RX_BUFFER_LENGTH - 2) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 155 | #define RX_JUMBO_DMA_MAP_LEN \ |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 156 | (MAX_RX_JUMBO_BUFFER_LENGTH - 2) |
| 157 | #define RX_LRO_DMA_MAP_LEN (MAX_RX_LRO_BUFFER_LENGTH - 2) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 158 | |
| 159 | /* |
| 160 | * Maximum number of ring contexts |
| 161 | */ |
| 162 | #define MAX_RING_CTX 1 |
| 163 | |
| 164 | /* Opcodes to be used with the commands */ |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 165 | #define TX_ETHER_PKT 0x01 |
| 166 | #define TX_TCP_PKT 0x02 |
| 167 | #define TX_UDP_PKT 0x03 |
| 168 | #define TX_IP_PKT 0x04 |
| 169 | #define TX_TCP_LSO 0x05 |
| 170 | #define TX_TCP_LSO6 0x06 |
| 171 | #define TX_IPSEC 0x07 |
| 172 | #define TX_IPSEC_CMD 0x0a |
| 173 | #define TX_TCPV6_PKT 0x0b |
| 174 | #define TX_UDPV6_PKT 0x0c |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 175 | |
| 176 | /* The following opcodes are for internal consumption. */ |
| 177 | #define NETXEN_CONTROL_OP 0x10 |
| 178 | #define PEGNET_REQUEST 0x11 |
| 179 | |
| 180 | #define MAX_NUM_CARDS 4 |
| 181 | |
| 182 | #define MAX_BUFFERS_PER_CMD 32 |
Dhananjay Phadke | cb2107b | 2009-06-17 17:27:25 +0000 | [diff] [blame] | 183 | #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + 4) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 184 | |
| 185 | /* |
| 186 | * Following are the states of the Phantom. Phantom will set them and |
| 187 | * Host will read to check if the fields are correct. |
| 188 | */ |
| 189 | #define PHAN_INITIALIZE_START 0xff00 |
| 190 | #define PHAN_INITIALIZE_FAILED 0xffff |
| 191 | #define PHAN_INITIALIZE_COMPLETE 0xff01 |
| 192 | |
| 193 | /* Host writes the following to notify that it has done the init-handshake */ |
| 194 | #define PHAN_INITIALIZE_ACK 0xf00f |
| 195 | |
Dhananjay Phadke | d8b100c | 2009-03-13 14:52:05 +0000 | [diff] [blame] | 196 | #define NUM_RCV_DESC_RINGS 3 |
| 197 | #define NUM_STS_DESC_RINGS 4 |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 198 | |
Dhananjay Phadke | 438627c | 2009-03-13 14:52:03 +0000 | [diff] [blame] | 199 | #define RCV_RING_NORMAL 0 |
| 200 | #define RCV_RING_JUMBO 1 |
| 201 | #define RCV_RING_LRO 2 |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 202 | |
Dhananjay Phadke | ba53e6b | 2008-03-17 19:59:50 -0700 | [diff] [blame] | 203 | #define MAX_CMD_DESCRIPTORS 4096 |
Amit S. Kale | bd56c6b | 2006-12-18 05:54:36 -0800 | [diff] [blame] | 204 | #define MAX_RCV_DESCRIPTORS 16384 |
Dhananjay Phadke | 32ec803 | 2009-01-26 12:35:19 -0800 | [diff] [blame] | 205 | #define MAX_CMD_DESCRIPTORS_HOST 1024 |
| 206 | #define MAX_RCV_DESCRIPTORS_1G 2048 |
| 207 | #define MAX_RCV_DESCRIPTORS_10G 4096 |
Dhananjay Phadke | e125646 | 2009-01-29 16:05:19 -0800 | [diff] [blame] | 208 | #define MAX_JUMBO_RCV_DESCRIPTORS 1024 |
Dhananjay Phadke | 32ec803 | 2009-01-26 12:35:19 -0800 | [diff] [blame] | 209 | #define MAX_LRO_RCV_DESCRIPTORS 8 |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 210 | #define NETXEN_CTX_SIGNATURE 0xdee0 |
Dhananjay Phadke | f6d21f4 | 2009-04-07 22:50:46 +0000 | [diff] [blame] | 211 | #define NETXEN_CTX_SIGNATURE_V2 0x0002dee0 |
| 212 | #define NETXEN_CTX_RESET 0xbad0 |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 213 | #define NETXEN_RCV_PRODUCER(ringid) (ringid) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 214 | |
| 215 | #define PHAN_PEG_RCV_INITIALIZED 0xff01 |
| 216 | #define PHAN_PEG_RCV_START_INITIALIZE 0xff00 |
| 217 | |
| 218 | #define get_next_index(index, length) \ |
| 219 | (((index) + 1) & ((length) - 1)) |
| 220 | |
| 221 | #define get_index_range(index,length,count) \ |
| 222 | (((index) + (count)) & ((length) - 1)) |
| 223 | |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 224 | #define MPORT_SINGLE_FUNCTION_MODE 0x1111 |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 225 | #define MPORT_MULTI_FUNCTION_MODE 0x2222 |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 226 | |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 227 | #include "netxen_nic_phan_reg.h" |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 228 | |
| 229 | /* |
| 230 | * NetXen host-peg signal message structure |
| 231 | * |
| 232 | * Bit 0-1 : peg_id => 0x2 for tx and 01 for rx |
| 233 | * Bit 2 : priv_id => must be 1 |
| 234 | * Bit 3-17 : count => for doorbell |
| 235 | * Bit 18-27 : ctx_id => Context id |
| 236 | * Bit 28-31 : opcode |
| 237 | */ |
| 238 | |
| 239 | typedef u32 netxen_ctx_msg; |
| 240 | |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 241 | #define netxen_set_msg_peg_id(config_word, val) \ |
Al Viro | a608ab9 | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 242 | ((config_word) &= ~3, (config_word) |= val & 3) |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 243 | #define netxen_set_msg_privid(config_word) \ |
Al Viro | a608ab9 | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 244 | ((config_word) |= 1 << 2) |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 245 | #define netxen_set_msg_count(config_word, val) \ |
Al Viro | a608ab9 | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 246 | ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3) |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 247 | #define netxen_set_msg_ctxid(config_word, val) \ |
Al Viro | a608ab9 | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 248 | ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18) |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 249 | #define netxen_set_msg_opcode(config_word, val) \ |
Amit S. Kale | 8258117 | 2007-02-12 04:33:38 -0800 | [diff] [blame] | 250 | ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28) |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 251 | |
Dhananjay Phadke | f6d21f4 | 2009-04-07 22:50:46 +0000 | [diff] [blame] | 252 | struct netxen_rcv_ring { |
| 253 | __le64 addr; |
| 254 | __le32 size; |
Al Viro | a608ab9 | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 255 | __le32 rsrvd; |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 256 | }; |
| 257 | |
Dhananjay Phadke | f6d21f4 | 2009-04-07 22:50:46 +0000 | [diff] [blame] | 258 | struct netxen_sts_ring { |
| 259 | __le64 addr; |
| 260 | __le32 size; |
| 261 | __le16 msi_index; |
| 262 | __le16 rsvd; |
| 263 | } ; |
| 264 | |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 265 | struct netxen_ring_ctx { |
| 266 | |
| 267 | /* one command ring */ |
Al Viro | a608ab9 | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 268 | __le64 cmd_consumer_offset; |
| 269 | __le64 cmd_ring_addr; |
| 270 | __le32 cmd_ring_size; |
| 271 | __le32 rsrvd; |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 272 | |
| 273 | /* three receive rings */ |
Dhananjay Phadke | f6d21f4 | 2009-04-07 22:50:46 +0000 | [diff] [blame] | 274 | struct netxen_rcv_ring rcv_rings[NUM_RCV_DESC_RINGS]; |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 275 | |
Al Viro | a608ab9 | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 276 | __le64 sts_ring_addr; |
| 277 | __le32 sts_ring_size; |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 278 | |
Al Viro | a608ab9 | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 279 | __le32 ctx_id; |
Dhananjay Phadke | f6d21f4 | 2009-04-07 22:50:46 +0000 | [diff] [blame] | 280 | |
| 281 | __le64 rsrvd_2[3]; |
| 282 | __le32 sts_ring_count; |
| 283 | __le32 rsrvd_3; |
| 284 | struct netxen_sts_ring sts_rings[NUM_STS_DESC_RINGS]; |
| 285 | |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 286 | } __attribute__ ((aligned(64))); |
| 287 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 288 | /* |
| 289 | * Following data structures describe the descriptors that will be used. |
| 290 | * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when |
| 291 | * we are doing LSO (above the 1500 size packet) only. |
| 292 | */ |
| 293 | |
| 294 | /* |
| 295 | * The size of reference handle been changed to 16 bits to pass the MSS fields |
| 296 | * for the LSO packet |
| 297 | */ |
| 298 | |
| 299 | #define FLAGS_CHECKSUM_ENABLED 0x01 |
| 300 | #define FLAGS_LSO_ENABLED 0x02 |
| 301 | #define FLAGS_IPSEC_SA_ADD 0x04 |
| 302 | #define FLAGS_IPSEC_SA_DELETE 0x08 |
| 303 | #define FLAGS_VLAN_TAGGED 0x10 |
| 304 | |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 305 | #define netxen_set_cmd_desc_port(cmd_desc, var) \ |
| 306 | ((cmd_desc)->port_ctxid |= ((var) & 0x0F)) |
Mithlesh Thukral | 6c80b18 | 2007-04-20 07:55:26 -0700 | [diff] [blame] | 307 | #define netxen_set_cmd_desc_ctxid(cmd_desc, var) \ |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 308 | ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0)) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 309 | |
Dhananjay Phadke | 391587c | 2009-01-14 20:48:11 -0800 | [diff] [blame] | 310 | #define netxen_set_tx_port(_desc, _port) \ |
| 311 | (_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0) |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 312 | |
Dhananjay Phadke | 391587c | 2009-01-14 20:48:11 -0800 | [diff] [blame] | 313 | #define netxen_set_tx_flags_opcode(_desc, _flags, _opcode) \ |
| 314 | (_desc)->flags_opcode = \ |
| 315 | cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7)) |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 316 | |
Dhananjay Phadke | 391587c | 2009-01-14 20:48:11 -0800 | [diff] [blame] | 317 | #define netxen_set_tx_frags_len(_desc, _frags, _len) \ |
| 318 | (_desc)->num_of_buffers_total_length = \ |
| 319 | cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8)) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 320 | |
| 321 | struct cmd_desc_type0 { |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 322 | u8 tcp_hdr_offset; /* For LSO only */ |
| 323 | u8 ip_hdr_offset; /* For LSO only */ |
| 324 | /* Bit pattern: 0-6 flags, 7-12 opcode, 13-15 unused */ |
Al Viro | a608ab9 | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 325 | __le16 flags_opcode; |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 326 | /* Bit pattern: 0-7 total number of segments, |
| 327 | 8-31 Total size of the packet */ |
Al Viro | a608ab9 | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 328 | __le32 num_of_buffers_total_length; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 329 | union { |
| 330 | struct { |
Al Viro | a608ab9 | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 331 | __le32 addr_low_part2; |
| 332 | __le32 addr_high_part2; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 333 | }; |
Al Viro | a608ab9 | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 334 | __le64 addr_buffer2; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 335 | }; |
| 336 | |
Al Viro | a608ab9 | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 337 | __le16 reference_handle; /* changed to u16 to add mss */ |
| 338 | __le16 mss; /* passed by NDIS_PACKET for LSO */ |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 339 | /* Bit pattern 0-3 port, 0-3 ctx id */ |
| 340 | u8 port_ctxid; |
| 341 | u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */ |
Al Viro | a608ab9 | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 342 | __le16 conn_id; /* IPSec offoad only */ |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 343 | |
| 344 | union { |
| 345 | struct { |
Al Viro | a608ab9 | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 346 | __le32 addr_low_part3; |
| 347 | __le32 addr_high_part3; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 348 | }; |
Al Viro | a608ab9 | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 349 | __le64 addr_buffer3; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 350 | }; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 351 | union { |
| 352 | struct { |
Al Viro | a608ab9 | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 353 | __le32 addr_low_part1; |
| 354 | __le32 addr_high_part1; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 355 | }; |
Al Viro | a608ab9 | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 356 | __le64 addr_buffer1; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 357 | }; |
| 358 | |
Dhananjay Phadke | d32cc3d | 2009-03-09 08:50:53 +0000 | [diff] [blame] | 359 | __le16 buffer_length[4]; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 360 | |
| 361 | union { |
| 362 | struct { |
Al Viro | a608ab9 | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 363 | __le32 addr_low_part4; |
| 364 | __le32 addr_high_part4; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 365 | }; |
Al Viro | a608ab9 | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 366 | __le64 addr_buffer4; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 367 | }; |
| 368 | |
Al Viro | a608ab9 | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 369 | __le64 unused; |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 370 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 371 | } __attribute__ ((aligned(64))); |
| 372 | |
| 373 | /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */ |
| 374 | struct rcv_desc { |
Al Viro | a608ab9 | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 375 | __le16 reference_handle; |
| 376 | __le16 reserved; |
| 377 | __le32 buffer_length; /* allocated buffer length (usually 2K) */ |
| 378 | __le64 addr_buffer; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 379 | }; |
| 380 | |
| 381 | /* opcode field in status_desc */ |
Dhananjay Phadke | d9e651b | 2008-07-21 19:44:08 -0700 | [diff] [blame] | 382 | #define NETXEN_NIC_RXPKT_DESC 0x04 |
| 383 | #define NETXEN_OLD_RXPKT_DESC 0x3f |
Dhananjay Phadke | 3bf26ce | 2009-04-07 22:50:42 +0000 | [diff] [blame] | 384 | #define NETXEN_NIC_RESPONSE_DESC 0x05 |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 385 | |
| 386 | /* for status field in status_desc */ |
| 387 | #define STATUS_NEED_CKSUM (1) |
| 388 | #define STATUS_CKSUM_OK (2) |
| 389 | |
| 390 | /* owner bits of status_desc */ |
Dhananjay Phadke | 0ddc110 | 2009-03-09 08:50:52 +0000 | [diff] [blame] | 391 | #define STATUS_OWNER_HOST (0x1ULL << 56) |
| 392 | #define STATUS_OWNER_PHANTOM (0x2ULL << 56) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 393 | |
Dhananjay Phadke | 3bf26ce | 2009-04-07 22:50:42 +0000 | [diff] [blame] | 394 | /* Status descriptor: |
| 395 | 0-3 port, 4-7 status, 8-11 type, 12-27 total_length |
| 396 | 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset |
| 397 | 53-55 desc_cnt, 56-57 owner, 58-63 opcode |
| 398 | */ |
Dhananjay Phadke | 5dc1626 | 2007-12-31 10:08:57 -0800 | [diff] [blame] | 399 | #define netxen_get_sts_port(sts_data) \ |
| 400 | ((sts_data) & 0x0F) |
| 401 | #define netxen_get_sts_status(sts_data) \ |
| 402 | (((sts_data) >> 4) & 0x0F) |
| 403 | #define netxen_get_sts_type(sts_data) \ |
| 404 | (((sts_data) >> 8) & 0x0F) |
| 405 | #define netxen_get_sts_totallength(sts_data) \ |
| 406 | (((sts_data) >> 12) & 0xFFFF) |
| 407 | #define netxen_get_sts_refhandle(sts_data) \ |
| 408 | (((sts_data) >> 28) & 0xFFFF) |
| 409 | #define netxen_get_sts_prot(sts_data) \ |
| 410 | (((sts_data) >> 44) & 0x0F) |
Dhananjay Phadke | d9e651b | 2008-07-21 19:44:08 -0700 | [diff] [blame] | 411 | #define netxen_get_sts_pkt_offset(sts_data) \ |
| 412 | (((sts_data) >> 48) & 0x1F) |
Dhananjay Phadke | 3bf26ce | 2009-04-07 22:50:42 +0000 | [diff] [blame] | 413 | #define netxen_get_sts_desc_cnt(sts_data) \ |
| 414 | (((sts_data) >> 53) & 0x7) |
Dhananjay Phadke | 5dc1626 | 2007-12-31 10:08:57 -0800 | [diff] [blame] | 415 | #define netxen_get_sts_opcode(sts_data) \ |
| 416 | (((sts_data) >> 58) & 0x03F) |
| 417 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 418 | struct status_desc { |
Dhananjay Phadke | 3bf26ce | 2009-04-07 22:50:42 +0000 | [diff] [blame] | 419 | __le64 status_desc_data[2]; |
Mithlesh Thukral | 6c80b18 | 2007-04-20 07:55:26 -0700 | [diff] [blame] | 420 | } __attribute__ ((aligned(16))); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 421 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 422 | /* The version of the main data structure */ |
| 423 | #define NETXEN_BDINFO_VERSION 1 |
| 424 | |
| 425 | /* Magic number to let user know flash is programmed */ |
| 426 | #define NETXEN_BDINFO_MAGIC 0x12345678 |
| 427 | |
| 428 | /* Max number of Gig ports on a Phantom board */ |
| 429 | #define NETXEN_MAX_PORTS 4 |
| 430 | |
Dhananjay Phadke | e98e335 | 2009-04-07 22:50:38 +0000 | [diff] [blame] | 431 | #define NETXEN_BRDTYPE_P1_BD 0x0000 |
| 432 | #define NETXEN_BRDTYPE_P1_SB 0x0001 |
| 433 | #define NETXEN_BRDTYPE_P1_SMAX 0x0002 |
| 434 | #define NETXEN_BRDTYPE_P1_SOCK 0x0003 |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 435 | |
Dhananjay Phadke | e98e335 | 2009-04-07 22:50:38 +0000 | [diff] [blame] | 436 | #define NETXEN_BRDTYPE_P2_SOCK_31 0x0008 |
| 437 | #define NETXEN_BRDTYPE_P2_SOCK_35 0x0009 |
| 438 | #define NETXEN_BRDTYPE_P2_SB35_4G 0x000a |
| 439 | #define NETXEN_BRDTYPE_P2_SB31_10G 0x000b |
| 440 | #define NETXEN_BRDTYPE_P2_SB31_2G 0x000c |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 441 | |
Dhananjay Phadke | e98e335 | 2009-04-07 22:50:38 +0000 | [diff] [blame] | 442 | #define NETXEN_BRDTYPE_P2_SB31_10G_IMEZ 0x000d |
| 443 | #define NETXEN_BRDTYPE_P2_SB31_10G_HMEZ 0x000e |
| 444 | #define NETXEN_BRDTYPE_P2_SB31_10G_CX4 0x000f |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 445 | |
Dhananjay Phadke | e98e335 | 2009-04-07 22:50:38 +0000 | [diff] [blame] | 446 | #define NETXEN_BRDTYPE_P3_REF_QG 0x0021 |
| 447 | #define NETXEN_BRDTYPE_P3_HMEZ 0x0022 |
| 448 | #define NETXEN_BRDTYPE_P3_10G_CX4_LP 0x0023 |
| 449 | #define NETXEN_BRDTYPE_P3_4_GB 0x0024 |
| 450 | #define NETXEN_BRDTYPE_P3_IMEZ 0x0025 |
| 451 | #define NETXEN_BRDTYPE_P3_10G_SFP_PLUS 0x0026 |
| 452 | #define NETXEN_BRDTYPE_P3_10000_BASE_T 0x0027 |
| 453 | #define NETXEN_BRDTYPE_P3_XG_LOM 0x0028 |
| 454 | #define NETXEN_BRDTYPE_P3_4_GB_MM 0x0029 |
| 455 | #define NETXEN_BRDTYPE_P3_10G_SFP_CT 0x002a |
| 456 | #define NETXEN_BRDTYPE_P3_10G_SFP_QT 0x002b |
| 457 | #define NETXEN_BRDTYPE_P3_10G_CX4 0x0031 |
| 458 | #define NETXEN_BRDTYPE_P3_10G_XFP 0x0032 |
| 459 | #define NETXEN_BRDTYPE_P3_10G_TP 0x0080 |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 460 | |
| 461 | struct netxen_board_info { |
| 462 | u32 header_version; |
| 463 | |
| 464 | u32 board_mfg; |
| 465 | u32 board_type; |
| 466 | u32 board_num; |
| 467 | u32 chip_id; |
| 468 | u32 chip_minor; |
| 469 | u32 chip_major; |
| 470 | u32 chip_pkg; |
| 471 | u32 chip_lot; |
| 472 | |
| 473 | u32 port_mask; /* available niu ports */ |
| 474 | u32 peg_mask; /* available pegs */ |
| 475 | u32 icache_ok; /* can we run with icache? */ |
| 476 | u32 dcache_ok; /* can we run with dcache? */ |
| 477 | u32 casper_ok; |
| 478 | |
| 479 | u32 mac_addr_lo_0; |
| 480 | u32 mac_addr_lo_1; |
| 481 | u32 mac_addr_lo_2; |
| 482 | u32 mac_addr_lo_3; |
| 483 | |
| 484 | /* MN-related config */ |
| 485 | u32 mn_sync_mode; /* enable/ sync shift cclk/ sync shift mclk */ |
| 486 | u32 mn_sync_shift_cclk; |
| 487 | u32 mn_sync_shift_mclk; |
| 488 | u32 mn_wb_en; |
| 489 | u32 mn_crystal_freq; /* in MHz */ |
| 490 | u32 mn_speed; /* in MHz */ |
| 491 | u32 mn_org; |
| 492 | u32 mn_depth; |
| 493 | u32 mn_ranks_0; /* ranks per slot */ |
| 494 | u32 mn_ranks_1; /* ranks per slot */ |
| 495 | u32 mn_rd_latency_0; |
| 496 | u32 mn_rd_latency_1; |
| 497 | u32 mn_rd_latency_2; |
| 498 | u32 mn_rd_latency_3; |
| 499 | u32 mn_rd_latency_4; |
| 500 | u32 mn_rd_latency_5; |
| 501 | u32 mn_rd_latency_6; |
| 502 | u32 mn_rd_latency_7; |
| 503 | u32 mn_rd_latency_8; |
| 504 | u32 mn_dll_val[18]; |
| 505 | u32 mn_mode_reg; /* MIU DDR Mode Register */ |
| 506 | u32 mn_ext_mode_reg; /* MIU DDR Extended Mode Register */ |
| 507 | u32 mn_timing_0; /* MIU Memory Control Timing Rgister */ |
| 508 | u32 mn_timing_1; /* MIU Extended Memory Ctrl Timing Register */ |
| 509 | u32 mn_timing_2; /* MIU Extended Memory Ctrl Timing2 Register */ |
| 510 | |
| 511 | /* SN-related config */ |
| 512 | u32 sn_sync_mode; /* enable/ sync shift cclk / sync shift mclk */ |
| 513 | u32 sn_pt_mode; /* pass through mode */ |
| 514 | u32 sn_ecc_en; |
| 515 | u32 sn_wb_en; |
| 516 | u32 sn_crystal_freq; |
| 517 | u32 sn_speed; |
| 518 | u32 sn_org; |
| 519 | u32 sn_depth; |
| 520 | u32 sn_dll_tap; |
| 521 | u32 sn_rd_latency; |
| 522 | |
| 523 | u32 mac_addr_hi_0; |
| 524 | u32 mac_addr_hi_1; |
| 525 | u32 mac_addr_hi_2; |
| 526 | u32 mac_addr_hi_3; |
| 527 | |
| 528 | u32 magic; /* indicates flash has been initialized */ |
| 529 | |
| 530 | u32 mn_rdimm; |
| 531 | u32 mn_dll_override; |
| 532 | |
| 533 | }; |
| 534 | |
| 535 | #define FLASH_NUM_PORTS (4) |
| 536 | |
| 537 | struct netxen_flash_mac_addr { |
| 538 | u32 flash_addr[32]; |
| 539 | }; |
| 540 | |
| 541 | struct netxen_user_old_info { |
| 542 | u8 flash_md5[16]; |
| 543 | u8 crbinit_md5[16]; |
| 544 | u8 brdcfg_md5[16]; |
| 545 | /* bootloader */ |
| 546 | u32 bootld_version; |
| 547 | u32 bootld_size; |
| 548 | u8 bootld_md5[16]; |
| 549 | /* image */ |
| 550 | u32 image_version; |
| 551 | u32 image_size; |
| 552 | u8 image_md5[16]; |
| 553 | /* primary image status */ |
| 554 | u32 primary_status; |
| 555 | u32 secondary_present; |
| 556 | |
| 557 | /* MAC address , 4 ports */ |
| 558 | struct netxen_flash_mac_addr mac_addr[FLASH_NUM_PORTS]; |
| 559 | }; |
| 560 | #define FLASH_NUM_MAC_PER_PORT 32 |
| 561 | struct netxen_user_info { |
| 562 | u8 flash_md5[16 * 64]; |
| 563 | /* bootloader */ |
| 564 | u32 bootld_version; |
| 565 | u32 bootld_size; |
| 566 | /* image */ |
| 567 | u32 image_version; |
| 568 | u32 image_size; |
| 569 | /* primary image status */ |
| 570 | u32 primary_status; |
| 571 | u32 secondary_present; |
| 572 | |
| 573 | /* MAC address , 4 ports, 32 address per port */ |
| 574 | u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT]; |
| 575 | u32 sub_sys_id; |
| 576 | u8 serial_num[32]; |
| 577 | |
| 578 | /* Any user defined data */ |
| 579 | }; |
| 580 | |
| 581 | /* |
| 582 | * Flash Layout - new format. |
| 583 | */ |
| 584 | struct netxen_new_user_info { |
| 585 | u8 flash_md5[16 * 64]; |
| 586 | /* bootloader */ |
| 587 | u32 bootld_version; |
| 588 | u32 bootld_size; |
| 589 | /* image */ |
| 590 | u32 image_version; |
| 591 | u32 image_size; |
| 592 | /* primary image status */ |
| 593 | u32 primary_status; |
| 594 | u32 secondary_present; |
| 595 | |
| 596 | /* MAC address , 4 ports, 32 address per port */ |
| 597 | u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT]; |
| 598 | u32 sub_sys_id; |
| 599 | u8 serial_num[32]; |
| 600 | |
| 601 | /* Any user defined data */ |
| 602 | }; |
| 603 | |
| 604 | #define SECONDARY_IMAGE_PRESENT 0xb3b4b5b6 |
| 605 | #define SECONDARY_IMAGE_ABSENT 0xffffffff |
| 606 | #define PRIMARY_IMAGE_GOOD 0x5a5a5a5a |
| 607 | #define PRIMARY_IMAGE_BAD 0xffffffff |
| 608 | |
| 609 | /* Flash memory map */ |
Dhananjay Phadke | e98e335 | 2009-04-07 22:50:38 +0000 | [diff] [blame] | 610 | #define NETXEN_CRBINIT_START 0 /* crbinit section */ |
| 611 | #define NETXEN_BRDCFG_START 0x4000 /* board config */ |
| 612 | #define NETXEN_INITCODE_START 0x6000 /* pegtune code */ |
| 613 | #define NETXEN_BOOTLD_START 0x10000 /* bootld */ |
| 614 | #define NETXEN_IMAGE_START 0x43000 /* compressed image */ |
| 615 | #define NETXEN_SECONDARY_START 0x200000 /* backup images */ |
| 616 | #define NETXEN_PXE_START 0x3E0000 /* PXE boot rom */ |
| 617 | #define NETXEN_USER_START 0x3E8000 /* Firmare info */ |
| 618 | #define NETXEN_FIXED_START 0x3F0000 /* backup of crbinit */ |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 619 | |
Dhananjay Phadke | ba599d4 | 2009-02-24 16:38:22 -0800 | [diff] [blame] | 620 | #define NX_FW_VERSION_OFFSET (NETXEN_USER_START+0x408) |
| 621 | #define NX_FW_SIZE_OFFSET (NETXEN_USER_START+0x40c) |
| 622 | #define NX_BIOS_VERSION_OFFSET (NETXEN_USER_START+0x83c) |
| 623 | #define NX_FW_MAGIC_OFFSET (NETXEN_BRDCFG_START+0x128) |
| 624 | #define NX_FW_MIN_SIZE (0x3fffff) |
Dhananjay Phadke | bd257ed | 2009-03-17 13:14:22 -0700 | [diff] [blame] | 625 | #define NX_P2_MN_ROMIMAGE 0 |
| 626 | #define NX_P3_CT_ROMIMAGE 1 |
| 627 | #define NX_P3_MN_ROMIMAGE 2 |
Dhananjay Phadke | 67c38fc | 2009-07-01 11:41:43 +0000 | [diff] [blame] | 628 | #define NX_FLASH_ROMIMAGE 3 |
Dhananjay Phadke | ba599d4 | 2009-02-24 16:38:22 -0800 | [diff] [blame] | 629 | |
Mithlesh Thukral | 0d04761 | 2007-06-07 04:36:36 -0700 | [diff] [blame] | 630 | #define NETXEN_USER_START_OLD NETXEN_PXE_START /* for backward compatibility */ |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 631 | |
Mithlesh Thukral | 0d04761 | 2007-06-07 04:36:36 -0700 | [diff] [blame] | 632 | #define NETXEN_FLASH_START (NETXEN_CRBINIT_START) |
| 633 | #define NETXEN_INIT_SECTOR (0) |
| 634 | #define NETXEN_PRIMARY_START (NETXEN_BOOTLD_START) |
| 635 | #define NETXEN_FLASH_CRBINIT_SIZE (0x4000) |
| 636 | #define NETXEN_FLASH_BRDCFG_SIZE (sizeof(struct netxen_board_info)) |
| 637 | #define NETXEN_FLASH_USER_SIZE (sizeof(struct netxen_user_info)/sizeof(u32)) |
| 638 | #define NETXEN_FLASH_SECONDARY_SIZE (NETXEN_USER_START-NETXEN_SECONDARY_START) |
| 639 | #define NETXEN_NUM_PRIMARY_SECTORS (0x20) |
| 640 | #define NETXEN_NUM_CONFIG_SECTORS (1) |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 641 | extern char netxen_nic_driver_name[]; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 642 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 643 | /* Number of status descriptors to handle per interrupt */ |
Dhananjay Phadke | d8b100c | 2009-03-13 14:52:05 +0000 | [diff] [blame] | 644 | #define MAX_STATUS_HANDLE (64) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 645 | |
| 646 | /* |
| 647 | * netxen_skb_frag{} is to contain mapping info for each SG list. This |
| 648 | * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}. |
| 649 | */ |
| 650 | struct netxen_skb_frag { |
| 651 | u64 dma; |
Dhananjay Phadke | d877f1e | 2009-04-07 22:50:40 +0000 | [diff] [blame] | 652 | u64 length; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 653 | }; |
| 654 | |
Mithlesh Thukral | 6c80b18 | 2007-04-20 07:55:26 -0700 | [diff] [blame] | 655 | #define _netxen_set_bits(config_word, start, bits, val) {\ |
| 656 | unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start));\ |
| 657 | unsigned long long __tvalue = (val); \ |
| 658 | (config_word) &= ~__tmask; \ |
| 659 | (config_word) |= (((__tvalue) << (start)) & __tmask); \ |
| 660 | } |
Jeff Garzik | 4790654 | 2007-11-23 21:23:36 -0500 | [diff] [blame] | 661 | |
Mithlesh Thukral | 6c80b18 | 2007-04-20 07:55:26 -0700 | [diff] [blame] | 662 | #define _netxen_clear_bits(config_word, start, bits) {\ |
| 663 | unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start)); \ |
| 664 | (config_word) &= ~__tmask; \ |
Jeff Garzik | 4790654 | 2007-11-23 21:23:36 -0500 | [diff] [blame] | 665 | } |
Mithlesh Thukral | 6c80b18 | 2007-04-20 07:55:26 -0700 | [diff] [blame] | 666 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 667 | /* Following defines are for the state of the buffers */ |
| 668 | #define NETXEN_BUFFER_FREE 0 |
| 669 | #define NETXEN_BUFFER_BUSY 1 |
| 670 | |
| 671 | /* |
| 672 | * There will be one netxen_buffer per skb packet. These will be |
| 673 | * used to save the dma info for pci_unmap_page() |
| 674 | */ |
| 675 | struct netxen_cmd_buffer { |
| 676 | struct sk_buff *skb; |
| 677 | struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1]; |
Dhananjay Phadke | 391587c | 2009-01-14 20:48:11 -0800 | [diff] [blame] | 678 | u32 frag_count; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 679 | }; |
| 680 | |
| 681 | /* In rx_buffer, we do not need multiple fragments as is a single buffer */ |
| 682 | struct netxen_rx_buffer { |
Dhananjay Phadke | d9e651b | 2008-07-21 19:44:08 -0700 | [diff] [blame] | 683 | struct list_head list; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 684 | struct sk_buff *skb; |
| 685 | u64 dma; |
| 686 | u16 ref_handle; |
| 687 | u16 state; |
| 688 | }; |
| 689 | |
| 690 | /* Board types */ |
| 691 | #define NETXEN_NIC_GBE 0x01 |
| 692 | #define NETXEN_NIC_XGBE 0x02 |
| 693 | |
| 694 | /* |
| 695 | * One hardware_context{} per adapter |
| 696 | * contains interrupt info as well shared hardware info. |
| 697 | */ |
| 698 | struct netxen_hardware_context { |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 699 | void __iomem *pci_base0; |
| 700 | void __iomem *pci_base1; |
| 701 | void __iomem *pci_base2; |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 702 | void __iomem *db_base; |
| 703 | unsigned long db_len; |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 704 | unsigned long pci_len0; |
| 705 | |
| 706 | int qdr_sn_window; |
| 707 | int ddr_mn_window; |
| 708 | unsigned long mn_win_crb; |
| 709 | unsigned long ms_win_crb; |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 710 | |
Dhananjay Phadke | 1e2d005 | 2009-03-09 08:50:56 +0000 | [diff] [blame] | 711 | u8 cut_through; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 712 | u8 revision_id; |
Dhananjay Phadke | 1b1f789 | 2009-04-07 22:50:39 +0000 | [diff] [blame] | 713 | u8 pci_func; |
| 714 | u8 linkup; |
Dhananjay Phadke | 1e2d005 | 2009-03-09 08:50:56 +0000 | [diff] [blame] | 715 | u16 port_type; |
Dhananjay Phadke | 1b1f789 | 2009-04-07 22:50:39 +0000 | [diff] [blame] | 716 | u16 board_type; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 717 | }; |
| 718 | |
| 719 | #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */ |
| 720 | #define ETHERNET_FCS_SIZE 4 |
| 721 | |
| 722 | struct netxen_adapter_stats { |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 723 | u64 xmitcalled; |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 724 | u64 xmitfinished; |
Dhananjay Phadke | d1847a7 | 2008-03-17 19:59:51 -0700 | [diff] [blame] | 725 | u64 rxdropped; |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 726 | u64 txdropped; |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 727 | u64 csummed; |
| 728 | u64 no_rcv; |
| 729 | u64 rxbytes; |
| 730 | u64 txbytes; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 731 | }; |
| 732 | |
| 733 | /* |
| 734 | * Rcv Descriptor Context. One such per Rcv Descriptor. There may |
| 735 | * be one Rcv Descriptor for normal packets, one for jumbo and may be others. |
| 736 | */ |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 737 | struct nx_host_rds_ring { |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 738 | u32 producer; |
Dhananjay Phadke | d8b100c | 2009-03-13 14:52:05 +0000 | [diff] [blame] | 739 | u32 crb_rcv_producer; |
Dhananjay Phadke | 438627c | 2009-03-13 14:52:03 +0000 | [diff] [blame] | 740 | u32 num_desc; |
| 741 | u32 dma_size; |
| 742 | u32 skb_size; |
| 743 | u32 flags; |
Dhananjay Phadke | d8b100c | 2009-03-13 14:52:05 +0000 | [diff] [blame] | 744 | struct rcv_desc *desc_head; |
| 745 | struct netxen_rx_buffer *rx_buf_arr; |
| 746 | struct list_head free_list; |
| 747 | spinlock_t lock; |
Dhananjay Phadke | 438627c | 2009-03-13 14:52:03 +0000 | [diff] [blame] | 748 | dma_addr_t phys_addr; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 749 | }; |
| 750 | |
Dhananjay Phadke | d8b100c | 2009-03-13 14:52:05 +0000 | [diff] [blame] | 751 | struct nx_host_sds_ring { |
| 752 | u32 consumer; |
| 753 | u32 crb_sts_consumer; |
| 754 | u32 crb_intr_mask; |
| 755 | u32 num_desc; |
| 756 | |
| 757 | struct status_desc *desc_head; |
| 758 | struct netxen_adapter *adapter; |
| 759 | struct napi_struct napi; |
| 760 | struct list_head free_list[NUM_RCV_DESC_RINGS]; |
| 761 | |
Dhananjay Phadke | d8b100c | 2009-03-13 14:52:05 +0000 | [diff] [blame] | 762 | int irq; |
| 763 | |
| 764 | dma_addr_t phys_addr; |
| 765 | char name[IFNAMSIZ+4]; |
| 766 | }; |
| 767 | |
Dhananjay Phadke | d877f1e | 2009-04-07 22:50:40 +0000 | [diff] [blame] | 768 | struct nx_host_tx_ring { |
| 769 | u32 producer; |
| 770 | __le32 *hw_consumer; |
| 771 | u32 sw_consumer; |
| 772 | u32 crb_cmd_producer; |
| 773 | u32 crb_cmd_consumer; |
| 774 | u32 num_desc; |
| 775 | |
| 776 | struct netxen_cmd_buffer *cmd_buf_arr; |
| 777 | struct cmd_desc_type0 *desc_head; |
| 778 | dma_addr_t phys_addr; |
| 779 | }; |
| 780 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 781 | /* |
| 782 | * Receive context. There is one such structure per instance of the |
| 783 | * receive processing. Any state information that is relevant to |
| 784 | * the receive, and is must be in this structure. The global data may be |
| 785 | * present elsewhere. |
| 786 | */ |
| 787 | struct netxen_recv_context { |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 788 | u32 state; |
| 789 | u16 context_id; |
| 790 | u16 virt_port; |
| 791 | |
Dhananjay Phadke | 4ea528a | 2009-04-28 15:29:10 +0000 | [diff] [blame] | 792 | struct nx_host_rds_ring *rds_rings; |
Dhananjay Phadke | 71dcddb | 2009-04-07 22:50:43 +0000 | [diff] [blame] | 793 | struct nx_host_sds_ring *sds_rings; |
Dhananjay Phadke | 4ea528a | 2009-04-28 15:29:10 +0000 | [diff] [blame] | 794 | |
| 795 | struct netxen_ring_ctx *hwctx; |
| 796 | dma_addr_t phys_addr; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 797 | }; |
| 798 | |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 799 | /* New HW context creation */ |
| 800 | |
| 801 | #define NX_OS_CRB_RETRY_COUNT 4000 |
| 802 | #define NX_CDRP_SIGNATURE_MAKE(pcifn, version) \ |
| 803 | (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16)) |
| 804 | |
| 805 | #define NX_CDRP_CLEAR 0x00000000 |
| 806 | #define NX_CDRP_CMD_BIT 0x80000000 |
| 807 | |
| 808 | /* |
| 809 | * All responses must have the NX_CDRP_CMD_BIT cleared |
| 810 | * in the crb NX_CDRP_CRB_OFFSET. |
| 811 | */ |
| 812 | #define NX_CDRP_FORM_RSP(rsp) (rsp) |
| 813 | #define NX_CDRP_IS_RSP(rsp) (((rsp) & NX_CDRP_CMD_BIT) == 0) |
| 814 | |
| 815 | #define NX_CDRP_RSP_OK 0x00000001 |
| 816 | #define NX_CDRP_RSP_FAIL 0x00000002 |
| 817 | #define NX_CDRP_RSP_TIMEOUT 0x00000003 |
| 818 | |
| 819 | /* |
| 820 | * All commands must have the NX_CDRP_CMD_BIT set in |
| 821 | * the crb NX_CDRP_CRB_OFFSET. |
| 822 | */ |
| 823 | #define NX_CDRP_FORM_CMD(cmd) (NX_CDRP_CMD_BIT | (cmd)) |
| 824 | #define NX_CDRP_IS_CMD(cmd) (((cmd) & NX_CDRP_CMD_BIT) != 0) |
| 825 | |
| 826 | #define NX_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001 |
| 827 | #define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002 |
| 828 | #define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003 |
| 829 | #define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004 |
| 830 | #define NX_CDRP_CMD_READ_MAX_RX_CTX 0x00000005 |
| 831 | #define NX_CDRP_CMD_READ_MAX_TX_CTX 0x00000006 |
| 832 | #define NX_CDRP_CMD_CREATE_RX_CTX 0x00000007 |
| 833 | #define NX_CDRP_CMD_DESTROY_RX_CTX 0x00000008 |
| 834 | #define NX_CDRP_CMD_CREATE_TX_CTX 0x00000009 |
| 835 | #define NX_CDRP_CMD_DESTROY_TX_CTX 0x0000000a |
| 836 | #define NX_CDRP_CMD_SETUP_STATISTICS 0x0000000e |
| 837 | #define NX_CDRP_CMD_GET_STATISTICS 0x0000000f |
| 838 | #define NX_CDRP_CMD_DELETE_STATISTICS 0x00000010 |
| 839 | #define NX_CDRP_CMD_SET_MTU 0x00000012 |
| 840 | #define NX_CDRP_CMD_MAX 0x00000013 |
| 841 | |
| 842 | #define NX_RCODE_SUCCESS 0 |
| 843 | #define NX_RCODE_NO_HOST_MEM 1 |
| 844 | #define NX_RCODE_NO_HOST_RESOURCE 2 |
| 845 | #define NX_RCODE_NO_CARD_CRB 3 |
| 846 | #define NX_RCODE_NO_CARD_MEM 4 |
| 847 | #define NX_RCODE_NO_CARD_RESOURCE 5 |
| 848 | #define NX_RCODE_INVALID_ARGS 6 |
| 849 | #define NX_RCODE_INVALID_ACTION 7 |
| 850 | #define NX_RCODE_INVALID_STATE 8 |
| 851 | #define NX_RCODE_NOT_SUPPORTED 9 |
| 852 | #define NX_RCODE_NOT_PERMITTED 10 |
| 853 | #define NX_RCODE_NOT_READY 11 |
| 854 | #define NX_RCODE_DOES_NOT_EXIST 12 |
| 855 | #define NX_RCODE_ALREADY_EXISTS 13 |
| 856 | #define NX_RCODE_BAD_SIGNATURE 14 |
| 857 | #define NX_RCODE_CMD_NOT_IMPL 15 |
| 858 | #define NX_RCODE_CMD_INVALID 16 |
| 859 | #define NX_RCODE_TIMEOUT 17 |
| 860 | #define NX_RCODE_CMD_FAILED 18 |
| 861 | #define NX_RCODE_MAX_EXCEEDED 19 |
| 862 | #define NX_RCODE_MAX 20 |
| 863 | |
| 864 | #define NX_DESTROY_CTX_RESET 0 |
| 865 | #define NX_DESTROY_CTX_D3_RESET 1 |
| 866 | #define NX_DESTROY_CTX_MAX 2 |
| 867 | |
| 868 | /* |
| 869 | * Capabilities |
| 870 | */ |
| 871 | #define NX_CAP_BIT(class, bit) (1 << bit) |
| 872 | #define NX_CAP0_LEGACY_CONTEXT NX_CAP_BIT(0, 0) |
| 873 | #define NX_CAP0_MULTI_CONTEXT NX_CAP_BIT(0, 1) |
| 874 | #define NX_CAP0_LEGACY_MN NX_CAP_BIT(0, 2) |
| 875 | #define NX_CAP0_LEGACY_MS NX_CAP_BIT(0, 3) |
| 876 | #define NX_CAP0_CUT_THROUGH NX_CAP_BIT(0, 4) |
| 877 | #define NX_CAP0_LRO NX_CAP_BIT(0, 5) |
| 878 | #define NX_CAP0_LSO NX_CAP_BIT(0, 6) |
| 879 | #define NX_CAP0_JUMBO_CONTIGUOUS NX_CAP_BIT(0, 7) |
| 880 | #define NX_CAP0_LRO_CONTIGUOUS NX_CAP_BIT(0, 8) |
| 881 | |
| 882 | /* |
| 883 | * Context state |
| 884 | */ |
| 885 | #define NX_HOST_CTX_STATE_FREED 0 |
| 886 | #define NX_HOST_CTX_STATE_ALLOCATED 1 |
| 887 | #define NX_HOST_CTX_STATE_ACTIVE 2 |
| 888 | #define NX_HOST_CTX_STATE_DISABLED 3 |
| 889 | #define NX_HOST_CTX_STATE_QUIESCED 4 |
| 890 | #define NX_HOST_CTX_STATE_MAX 5 |
| 891 | |
| 892 | /* |
| 893 | * Rx context |
| 894 | */ |
| 895 | |
| 896 | typedef struct { |
Dhananjay Phadke | 2edbb45 | 2009-01-14 20:47:30 -0800 | [diff] [blame] | 897 | __le64 host_phys_addr; /* Ring base addr */ |
| 898 | __le32 ring_size; /* Ring entries */ |
| 899 | __le16 msi_index; |
| 900 | __le16 rsvd; /* Padding */ |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 901 | } nx_hostrq_sds_ring_t; |
| 902 | |
| 903 | typedef struct { |
Dhananjay Phadke | 2edbb45 | 2009-01-14 20:47:30 -0800 | [diff] [blame] | 904 | __le64 host_phys_addr; /* Ring base addr */ |
| 905 | __le64 buff_size; /* Packet buffer size */ |
| 906 | __le32 ring_size; /* Ring entries */ |
| 907 | __le32 ring_kind; /* Class of ring */ |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 908 | } nx_hostrq_rds_ring_t; |
| 909 | |
| 910 | typedef struct { |
Dhananjay Phadke | 2edbb45 | 2009-01-14 20:47:30 -0800 | [diff] [blame] | 911 | __le64 host_rsp_dma_addr; /* Response dma'd here */ |
| 912 | __le32 capabilities[4]; /* Flag bit vector */ |
| 913 | __le32 host_int_crb_mode; /* Interrupt crb usage */ |
| 914 | __le32 host_rds_crb_mode; /* RDS crb usage */ |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 915 | /* These ring offsets are relative to data[0] below */ |
Dhananjay Phadke | 2edbb45 | 2009-01-14 20:47:30 -0800 | [diff] [blame] | 916 | __le32 rds_ring_offset; /* Offset to RDS config */ |
| 917 | __le32 sds_ring_offset; /* Offset to SDS config */ |
| 918 | __le16 num_rds_rings; /* Count of RDS rings */ |
| 919 | __le16 num_sds_rings; /* Count of SDS rings */ |
| 920 | __le16 rsvd1; /* Padding */ |
| 921 | __le16 rsvd2; /* Padding */ |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 922 | u8 reserved[128]; /* reserve space for future expansion*/ |
| 923 | /* MUST BE 64-bit aligned. |
| 924 | The following is packed: |
| 925 | - N hostrq_rds_rings |
| 926 | - N hostrq_sds_rings */ |
| 927 | char data[0]; |
| 928 | } nx_hostrq_rx_ctx_t; |
| 929 | |
| 930 | typedef struct { |
Dhananjay Phadke | 2edbb45 | 2009-01-14 20:47:30 -0800 | [diff] [blame] | 931 | __le32 host_producer_crb; /* Crb to use */ |
| 932 | __le32 rsvd1; /* Padding */ |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 933 | } nx_cardrsp_rds_ring_t; |
| 934 | |
| 935 | typedef struct { |
Dhananjay Phadke | 2edbb45 | 2009-01-14 20:47:30 -0800 | [diff] [blame] | 936 | __le32 host_consumer_crb; /* Crb to use */ |
| 937 | __le32 interrupt_crb; /* Crb to use */ |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 938 | } nx_cardrsp_sds_ring_t; |
| 939 | |
| 940 | typedef struct { |
| 941 | /* These ring offsets are relative to data[0] below */ |
Dhananjay Phadke | 2edbb45 | 2009-01-14 20:47:30 -0800 | [diff] [blame] | 942 | __le32 rds_ring_offset; /* Offset to RDS config */ |
| 943 | __le32 sds_ring_offset; /* Offset to SDS config */ |
| 944 | __le32 host_ctx_state; /* Starting State */ |
| 945 | __le32 num_fn_per_port; /* How many PCI fn share the port */ |
| 946 | __le16 num_rds_rings; /* Count of RDS rings */ |
| 947 | __le16 num_sds_rings; /* Count of SDS rings */ |
| 948 | __le16 context_id; /* Handle for context */ |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 949 | u8 phys_port; /* Physical id of port */ |
| 950 | u8 virt_port; /* Virtual/Logical id of port */ |
| 951 | u8 reserved[128]; /* save space for future expansion */ |
| 952 | /* MUST BE 64-bit aligned. |
| 953 | The following is packed: |
| 954 | - N cardrsp_rds_rings |
| 955 | - N cardrs_sds_rings */ |
| 956 | char data[0]; |
| 957 | } nx_cardrsp_rx_ctx_t; |
| 958 | |
| 959 | #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \ |
| 960 | (sizeof(HOSTRQ_RX) + \ |
| 961 | (rds_rings)*(sizeof(nx_hostrq_rds_ring_t)) + \ |
| 962 | (sds_rings)*(sizeof(nx_hostrq_sds_ring_t))) |
| 963 | |
| 964 | #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \ |
| 965 | (sizeof(CARDRSP_RX) + \ |
| 966 | (rds_rings)*(sizeof(nx_cardrsp_rds_ring_t)) + \ |
| 967 | (sds_rings)*(sizeof(nx_cardrsp_sds_ring_t))) |
| 968 | |
| 969 | /* |
| 970 | * Tx context |
| 971 | */ |
| 972 | |
| 973 | typedef struct { |
Dhananjay Phadke | 2edbb45 | 2009-01-14 20:47:30 -0800 | [diff] [blame] | 974 | __le64 host_phys_addr; /* Ring base addr */ |
| 975 | __le32 ring_size; /* Ring entries */ |
| 976 | __le32 rsvd; /* Padding */ |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 977 | } nx_hostrq_cds_ring_t; |
| 978 | |
| 979 | typedef struct { |
Dhananjay Phadke | 2edbb45 | 2009-01-14 20:47:30 -0800 | [diff] [blame] | 980 | __le64 host_rsp_dma_addr; /* Response dma'd here */ |
| 981 | __le64 cmd_cons_dma_addr; /* */ |
| 982 | __le64 dummy_dma_addr; /* */ |
| 983 | __le32 capabilities[4]; /* Flag bit vector */ |
| 984 | __le32 host_int_crb_mode; /* Interrupt crb usage */ |
| 985 | __le32 rsvd1; /* Padding */ |
| 986 | __le16 rsvd2; /* Padding */ |
| 987 | __le16 interrupt_ctl; |
| 988 | __le16 msi_index; |
| 989 | __le16 rsvd3; /* Padding */ |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 990 | nx_hostrq_cds_ring_t cds_ring; /* Desc of cds ring */ |
| 991 | u8 reserved[128]; /* future expansion */ |
| 992 | } nx_hostrq_tx_ctx_t; |
| 993 | |
| 994 | typedef struct { |
Dhananjay Phadke | 2edbb45 | 2009-01-14 20:47:30 -0800 | [diff] [blame] | 995 | __le32 host_producer_crb; /* Crb to use */ |
| 996 | __le32 interrupt_crb; /* Crb to use */ |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 997 | } nx_cardrsp_cds_ring_t; |
| 998 | |
| 999 | typedef struct { |
Dhananjay Phadke | 2edbb45 | 2009-01-14 20:47:30 -0800 | [diff] [blame] | 1000 | __le32 host_ctx_state; /* Starting state */ |
| 1001 | __le16 context_id; /* Handle for context */ |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 1002 | u8 phys_port; /* Physical id of port */ |
| 1003 | u8 virt_port; /* Virtual/Logical id of port */ |
| 1004 | nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */ |
| 1005 | u8 reserved[128]; /* future expansion */ |
| 1006 | } nx_cardrsp_tx_ctx_t; |
| 1007 | |
| 1008 | #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX)) |
| 1009 | #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX)) |
| 1010 | |
| 1011 | /* CRB */ |
| 1012 | |
| 1013 | #define NX_HOST_RDS_CRB_MODE_UNIQUE 0 |
| 1014 | #define NX_HOST_RDS_CRB_MODE_SHARED 1 |
| 1015 | #define NX_HOST_RDS_CRB_MODE_CUSTOM 2 |
| 1016 | #define NX_HOST_RDS_CRB_MODE_MAX 3 |
| 1017 | |
| 1018 | #define NX_HOST_INT_CRB_MODE_UNIQUE 0 |
| 1019 | #define NX_HOST_INT_CRB_MODE_SHARED 1 |
| 1020 | #define NX_HOST_INT_CRB_MODE_NORX 2 |
| 1021 | #define NX_HOST_INT_CRB_MODE_NOTX 3 |
| 1022 | #define NX_HOST_INT_CRB_MODE_NORXTX 4 |
| 1023 | |
| 1024 | |
| 1025 | /* MAC */ |
| 1026 | |
| 1027 | #define MC_COUNT_P2 16 |
| 1028 | #define MC_COUNT_P3 38 |
| 1029 | |
| 1030 | #define NETXEN_MAC_NOOP 0 |
| 1031 | #define NETXEN_MAC_ADD 1 |
| 1032 | #define NETXEN_MAC_DEL 2 |
| 1033 | |
| 1034 | typedef struct nx_mac_list_s { |
Dhananjay Phadke | 5cf4d32 | 2009-05-05 19:05:07 +0000 | [diff] [blame] | 1035 | struct list_head list; |
| 1036 | uint8_t mac_addr[ETH_ALEN+2]; |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 1037 | } nx_mac_list_t; |
| 1038 | |
Dhananjay Phadke | cd1f816 | 2008-07-21 19:44:09 -0700 | [diff] [blame] | 1039 | /* |
| 1040 | * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is |
| 1041 | * adjusted based on configured MTU. |
| 1042 | */ |
| 1043 | #define NETXEN_DEFAULT_INTR_COALESCE_RX_TIME_US 3 |
| 1044 | #define NETXEN_DEFAULT_INTR_COALESCE_RX_PACKETS 256 |
| 1045 | #define NETXEN_DEFAULT_INTR_COALESCE_TX_PACKETS 64 |
| 1046 | #define NETXEN_DEFAULT_INTR_COALESCE_TX_TIME_US 4 |
| 1047 | |
| 1048 | #define NETXEN_NIC_INTR_DEFAULT 0x04 |
| 1049 | |
| 1050 | typedef union { |
| 1051 | struct { |
| 1052 | uint16_t rx_packets; |
| 1053 | uint16_t rx_time_us; |
| 1054 | uint16_t tx_packets; |
| 1055 | uint16_t tx_time_us; |
| 1056 | } data; |
| 1057 | uint64_t word; |
| 1058 | } nx_nic_intr_coalesce_data_t; |
| 1059 | |
| 1060 | typedef struct { |
| 1061 | uint16_t stats_time_us; |
| 1062 | uint16_t rate_sample_time; |
| 1063 | uint16_t flags; |
| 1064 | uint16_t rsvd_1; |
| 1065 | uint32_t low_threshold; |
| 1066 | uint32_t high_threshold; |
| 1067 | nx_nic_intr_coalesce_data_t normal; |
| 1068 | nx_nic_intr_coalesce_data_t low; |
| 1069 | nx_nic_intr_coalesce_data_t high; |
| 1070 | nx_nic_intr_coalesce_data_t irq; |
| 1071 | } nx_nic_intr_coalesce_t; |
| 1072 | |
Dhananjay Phadke | 9ad2764 | 2008-08-01 03:14:59 -0700 | [diff] [blame] | 1073 | #define NX_HOST_REQUEST 0x13 |
| 1074 | #define NX_NIC_REQUEST 0x14 |
| 1075 | |
| 1076 | #define NX_MAC_EVENT 0x1 |
| 1077 | |
Dhananjay Phadke | e98e335 | 2009-04-07 22:50:38 +0000 | [diff] [blame] | 1078 | /* |
| 1079 | * Driver --> Firmware |
| 1080 | */ |
| 1081 | #define NX_NIC_H2C_OPCODE_START 0 |
| 1082 | #define NX_NIC_H2C_OPCODE_CONFIG_RSS 1 |
| 1083 | #define NX_NIC_H2C_OPCODE_CONFIG_RSS_TBL 2 |
| 1084 | #define NX_NIC_H2C_OPCODE_CONFIG_INTR_COALESCE 3 |
| 1085 | #define NX_NIC_H2C_OPCODE_CONFIG_LED 4 |
| 1086 | #define NX_NIC_H2C_OPCODE_CONFIG_PROMISCUOUS 5 |
| 1087 | #define NX_NIC_H2C_OPCODE_CONFIG_L2_MAC 6 |
| 1088 | #define NX_NIC_H2C_OPCODE_LRO_REQUEST 7 |
| 1089 | #define NX_NIC_H2C_OPCODE_GET_SNMP_STATS 8 |
| 1090 | #define NX_NIC_H2C_OPCODE_PROXY_START_REQUEST 9 |
| 1091 | #define NX_NIC_H2C_OPCODE_PROXY_STOP_REQUEST 10 |
| 1092 | #define NX_NIC_H2C_OPCODE_PROXY_SET_MTU 11 |
| 1093 | #define NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE 12 |
| 1094 | #define NX_NIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST 13 |
| 1095 | #define NX_NIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST 14 |
| 1096 | #define NX_NIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST 15 |
| 1097 | #define NX_NIC_H2C_OPCODE_GET_NET_STATS 16 |
| 1098 | #define NX_NIC_H2C_OPCODE_PROXY_UPDATE_P2V 17 |
| 1099 | #define NX_NIC_H2C_OPCODE_CONFIG_IPADDR 18 |
| 1100 | #define NX_NIC_H2C_OPCODE_CONFIG_LOOPBACK 19 |
| 1101 | #define NX_NIC_H2C_OPCODE_PROXY_STOP_DONE 20 |
| 1102 | #define NX_NIC_H2C_OPCODE_GET_LINKEVENT 21 |
| 1103 | #define NX_NIC_C2C_OPCODE 22 |
| 1104 | #define NX_NIC_H2C_OPCODE_LAST 23 |
| 1105 | |
| 1106 | /* |
| 1107 | * Firmware --> Driver |
| 1108 | */ |
| 1109 | |
| 1110 | #define NX_NIC_C2H_OPCODE_START 128 |
| 1111 | #define NX_NIC_C2H_OPCODE_CONFIG_RSS_RESPONSE 129 |
| 1112 | #define NX_NIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE 130 |
| 1113 | #define NX_NIC_C2H_OPCODE_CONFIG_MAC_RESPONSE 131 |
| 1114 | #define NX_NIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE 132 |
| 1115 | #define NX_NIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE 133 |
| 1116 | #define NX_NIC_C2H_OPCODE_LRO_DELETE_RESPONSE 134 |
| 1117 | #define NX_NIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE 135 |
| 1118 | #define NX_NIC_C2H_OPCODE_GET_SNMP_STATS 136 |
| 1119 | #define NX_NIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY 137 |
| 1120 | #define NX_NIC_C2H_OPCODE_INSTALL_LICENSE_REPLY 138 |
| 1121 | #define NX_NIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139 |
| 1122 | #define NX_NIC_C2H_OPCODE_GET_NET_STATS_RESPONSE 140 |
| 1123 | #define NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141 |
| 1124 | #define NX_NIC_C2H_OPCODE_LAST 142 |
Dhananjay Phadke | 9ad2764 | 2008-08-01 03:14:59 -0700 | [diff] [blame] | 1125 | |
| 1126 | #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */ |
| 1127 | #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */ |
| 1128 | #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */ |
| 1129 | |
Dhananjay Phadke | 3bf26ce | 2009-04-07 22:50:42 +0000 | [diff] [blame] | 1130 | #define NX_FW_CAPABILITY_LINK_NOTIFICATION (1 << 5) |
| 1131 | #define NX_FW_CAPABILITY_SWITCHING (1 << 6) |
| 1132 | |
| 1133 | /* module types */ |
| 1134 | #define LINKEVENT_MODULE_NOT_PRESENT 1 |
| 1135 | #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2 |
| 1136 | #define LINKEVENT_MODULE_OPTICAL_SRLR 3 |
| 1137 | #define LINKEVENT_MODULE_OPTICAL_LRM 4 |
| 1138 | #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5 |
| 1139 | #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6 |
| 1140 | #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7 |
| 1141 | #define LINKEVENT_MODULE_TWINAX 8 |
| 1142 | |
| 1143 | #define LINKSPEED_10GBPS 10000 |
| 1144 | #define LINKSPEED_1GBPS 1000 |
| 1145 | #define LINKSPEED_100MBPS 100 |
| 1146 | #define LINKSPEED_10MBPS 10 |
| 1147 | |
| 1148 | #define LINKSPEED_ENCODED_10MBPS 0 |
| 1149 | #define LINKSPEED_ENCODED_100MBPS 1 |
| 1150 | #define LINKSPEED_ENCODED_1GBPS 2 |
| 1151 | |
| 1152 | #define LINKEVENT_AUTONEG_DISABLED 0 |
| 1153 | #define LINKEVENT_AUTONEG_ENABLED 1 |
| 1154 | |
| 1155 | #define LINKEVENT_HALF_DUPLEX 0 |
| 1156 | #define LINKEVENT_FULL_DUPLEX 1 |
| 1157 | |
| 1158 | #define LINKEVENT_LINKSPEED_MBPS 0 |
| 1159 | #define LINKEVENT_LINKSPEED_ENCODED 1 |
| 1160 | |
| 1161 | /* firmware response header: |
| 1162 | * 63:58 - message type |
| 1163 | * 57:56 - owner |
| 1164 | * 55:53 - desc count |
| 1165 | * 52:48 - reserved |
| 1166 | * 47:40 - completion id |
| 1167 | * 39:32 - opcode |
| 1168 | * 31:16 - error code |
| 1169 | * 15:00 - reserved |
| 1170 | */ |
| 1171 | #define netxen_get_nic_msgtype(msg_hdr) \ |
| 1172 | ((msg_hdr >> 58) & 0x3F) |
| 1173 | #define netxen_get_nic_msg_compid(msg_hdr) \ |
| 1174 | ((msg_hdr >> 40) & 0xFF) |
| 1175 | #define netxen_get_nic_msg_opcode(msg_hdr) \ |
| 1176 | ((msg_hdr >> 32) & 0xFF) |
| 1177 | #define netxen_get_nic_msg_errcode(msg_hdr) \ |
| 1178 | ((msg_hdr >> 16) & 0xFFFF) |
| 1179 | |
| 1180 | typedef struct { |
| 1181 | union { |
| 1182 | struct { |
| 1183 | u64 hdr; |
| 1184 | u64 body[7]; |
| 1185 | }; |
| 1186 | u64 words[8]; |
| 1187 | }; |
| 1188 | } nx_fw_msg_t; |
| 1189 | |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 1190 | typedef struct { |
Dhananjay Phadke | 2edbb45 | 2009-01-14 20:47:30 -0800 | [diff] [blame] | 1191 | __le64 qhdr; |
| 1192 | __le64 req_hdr; |
| 1193 | __le64 words[6]; |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 1194 | } nx_nic_req_t; |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 1195 | |
| 1196 | typedef struct { |
| 1197 | u8 op; |
| 1198 | u8 tag; |
| 1199 | u8 mac_addr[6]; |
| 1200 | } nx_mac_req_t; |
| 1201 | |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 1202 | #define MAX_PENDING_DESC_BLOCK_SIZE 64 |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 1203 | |
Dhananjay Phadke | 2956640 | 2008-07-21 19:44:04 -0700 | [diff] [blame] | 1204 | #define NETXEN_NIC_MSI_ENABLED 0x02 |
| 1205 | #define NETXEN_NIC_MSIX_ENABLED 0x04 |
| 1206 | #define NETXEN_IS_MSI_FAMILY(adapter) \ |
| 1207 | ((adapter)->flags & (NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED)) |
| 1208 | |
Dhananjay Phadke | d8b100c | 2009-03-13 14:52:05 +0000 | [diff] [blame] | 1209 | #define MSIX_ENTRIES_PER_ADAPTER NUM_STS_DESC_RINGS |
Dhananjay Phadke | 2956640 | 2008-07-21 19:44:04 -0700 | [diff] [blame] | 1210 | #define NETXEN_MSIX_TBL_SPACE 8192 |
| 1211 | #define NETXEN_PCI_REG_MSIX_TBL 0x44 |
| 1212 | |
| 1213 | #define NETXEN_DB_MAPSIZE_BYTES 0x1000 |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 1214 | |
Dhananjay Phadke | d8b100c | 2009-03-13 14:52:05 +0000 | [diff] [blame] | 1215 | #define NETXEN_NETDEV_WEIGHT 128 |
Dhananjay Phadke | cd1f816 | 2008-07-21 19:44:09 -0700 | [diff] [blame] | 1216 | #define NETXEN_ADAPTER_UP_MAGIC 777 |
| 1217 | #define NETXEN_NIC_PEG_TUNE 0 |
| 1218 | |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 1219 | struct netxen_dummy_dma { |
| 1220 | void *addr; |
| 1221 | dma_addr_t phys_addr; |
| 1222 | }; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1223 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1224 | struct netxen_adapter { |
| 1225 | struct netxen_hardware_context ahw; |
Jeff Garzik | 4790654 | 2007-11-23 21:23:36 -0500 | [diff] [blame] | 1226 | |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 1227 | struct net_device *netdev; |
| 1228 | struct pci_dev *pdev; |
Dhananjay Phadke | 5cf4d32 | 2009-05-05 19:05:07 +0000 | [diff] [blame] | 1229 | struct list_head mac_list; |
Dhananjay Phadke | 623621b | 2008-07-21 19:44:01 -0700 | [diff] [blame] | 1230 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1231 | u32 curr_window; |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1232 | u32 crb_win; |
| 1233 | rwlock_t adapter_lock; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1234 | |
Dhananjay Phadke | 1b1f789 | 2009-04-07 22:50:39 +0000 | [diff] [blame] | 1235 | spinlock_t tx_clean_lock; |
Dhananjay Phadke | ba53e6b | 2008-03-17 19:59:50 -0700 | [diff] [blame] | 1236 | |
Dhananjay Phadke | 71dcddb | 2009-04-07 22:50:43 +0000 | [diff] [blame] | 1237 | u16 num_txd; |
| 1238 | u16 num_rxd; |
| 1239 | u16 num_jumbo_rxd; |
| 1240 | u16 num_lro_rxd; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1241 | |
Dhananjay Phadke | 1b1f789 | 2009-04-07 22:50:39 +0000 | [diff] [blame] | 1242 | u8 max_rds_rings; |
| 1243 | u8 max_sds_rings; |
| 1244 | u8 driver_mismatch; |
| 1245 | u8 msix_supported; |
| 1246 | u8 rx_csum; |
| 1247 | u8 pci_using_dac; |
| 1248 | u8 portnum; |
| 1249 | u8 physical_port; |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 1250 | |
Dhananjay Phadke | 1b1f789 | 2009-04-07 22:50:39 +0000 | [diff] [blame] | 1251 | u8 mc_enabled; |
| 1252 | u8 max_mc_count; |
Dhananjay Phadke | f6d21f4 | 2009-04-07 22:50:46 +0000 | [diff] [blame] | 1253 | u8 rss_supported; |
| 1254 | u8 resv2; |
Dhananjay Phadke | 3bf26ce | 2009-04-07 22:50:42 +0000 | [diff] [blame] | 1255 | u32 resv3; |
| 1256 | |
| 1257 | u8 has_link_events; |
Dhananjay Phadke | 67c38fc | 2009-07-01 11:41:43 +0000 | [diff] [blame] | 1258 | u8 fw_type; |
Dhananjay Phadke | 1b1f789 | 2009-04-07 22:50:39 +0000 | [diff] [blame] | 1259 | u16 tx_context_id; |
| 1260 | u16 mtu; |
| 1261 | u16 is_up; |
Dhananjay Phadke | 3bf26ce | 2009-04-07 22:50:42 +0000 | [diff] [blame] | 1262 | |
Dhananjay Phadke | 1b1f789 | 2009-04-07 22:50:39 +0000 | [diff] [blame] | 1263 | u16 link_speed; |
| 1264 | u16 link_duplex; |
| 1265 | u16 link_autoneg; |
Dhananjay Phadke | 3bf26ce | 2009-04-07 22:50:42 +0000 | [diff] [blame] | 1266 | u16 module_type; |
Dhananjay Phadke | 1b1f789 | 2009-04-07 22:50:39 +0000 | [diff] [blame] | 1267 | |
Dhananjay Phadke | 3bf26ce | 2009-04-07 22:50:42 +0000 | [diff] [blame] | 1268 | u32 capabilities; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1269 | u32 flags; |
| 1270 | u32 irq; |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 1271 | u32 temp; |
Dhananjay Phadke | 2956640 | 2008-07-21 19:44:04 -0700 | [diff] [blame] | 1272 | |
Dhananjay Phadke | 7a2469c | 2009-05-08 22:02:27 +0000 | [diff] [blame] | 1273 | u32 msi_tgt_status; |
| 1274 | u32 resv4; |
| 1275 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1276 | struct netxen_adapter_stats stats; |
Jeff Garzik | 4790654 | 2007-11-23 21:23:36 -0500 | [diff] [blame] | 1277 | |
Dhananjay Phadke | becf46a | 2009-03-09 08:50:55 +0000 | [diff] [blame] | 1278 | struct netxen_recv_context recv_ctx; |
Dhananjay Phadke | 4ea528a | 2009-04-28 15:29:10 +0000 | [diff] [blame] | 1279 | struct nx_host_tx_ring *tx_ring; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1280 | |
Mithlesh Thukral | 13ba9c7 | 2007-04-20 07:53:05 -0700 | [diff] [blame] | 1281 | int (*enable_phy_interrupts) (struct netxen_adapter *); |
| 1282 | int (*disable_phy_interrupts) (struct netxen_adapter *); |
Dhananjay Phadke | 3d0a3cc | 2009-05-05 19:05:08 +0000 | [diff] [blame] | 1283 | int (*macaddr_set) (struct netxen_adapter *, u8 *); |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 1284 | int (*set_mtu) (struct netxen_adapter *, int); |
Dhananjay Phadke | 9ad2764 | 2008-08-01 03:14:59 -0700 | [diff] [blame] | 1285 | int (*set_promisc) (struct netxen_adapter *, u32); |
Dhananjay Phadke | 3d0a3cc | 2009-05-05 19:05:08 +0000 | [diff] [blame] | 1286 | void (*set_multi) (struct net_device *); |
Mithlesh Thukral | 13ba9c7 | 2007-04-20 07:53:05 -0700 | [diff] [blame] | 1287 | int (*phy_read) (struct netxen_adapter *, long reg, u32 *); |
| 1288 | int (*phy_write) (struct netxen_adapter *, long reg, u32 val); |
Amit S. Kale | 80922fb | 2006-12-04 09:18:00 -0800 | [diff] [blame] | 1289 | int (*init_port) (struct netxen_adapter *, int); |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 1290 | int (*stop_port) (struct netxen_adapter *); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1291 | |
Dhananjay Phadke | 1fbe632 | 2009-04-07 22:50:44 +0000 | [diff] [blame] | 1292 | u32 (*hw_read_wx)(struct netxen_adapter *, ulong); |
| 1293 | int (*hw_write_wx)(struct netxen_adapter *, ulong, u32); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1294 | int (*pci_mem_read)(struct netxen_adapter *, u64, void *, int); |
| 1295 | int (*pci_mem_write)(struct netxen_adapter *, u64, void *, int); |
| 1296 | int (*pci_write_immediate)(struct netxen_adapter *, u64, u32); |
| 1297 | u32 (*pci_read_immediate)(struct netxen_adapter *, u64); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1298 | unsigned long (*pci_set_window)(struct netxen_adapter *, |
| 1299 | unsigned long long); |
Dhananjay Phadke | 1b1f789 | 2009-04-07 22:50:39 +0000 | [diff] [blame] | 1300 | |
| 1301 | struct netxen_legacy_intr_set legacy_intr; |
| 1302 | |
| 1303 | struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER]; |
| 1304 | |
| 1305 | struct netxen_dummy_dma dummy_dma; |
| 1306 | |
| 1307 | struct work_struct watchdog_task; |
| 1308 | struct timer_list watchdog_timer; |
| 1309 | struct work_struct tx_timeout_task; |
| 1310 | |
| 1311 | struct net_device_stats net_stats; |
| 1312 | |
| 1313 | nx_nic_intr_coalesce_t coal; |
Dhananjay Phadke | f7185c7 | 2009-04-28 15:29:11 +0000 | [diff] [blame] | 1314 | |
| 1315 | u32 fw_major; |
| 1316 | u32 fw_version; |
| 1317 | const struct firmware *fw; |
Dhananjay Phadke | 1b1f789 | 2009-04-07 22:50:39 +0000 | [diff] [blame] | 1318 | }; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1319 | |
Dhananjay Phadke | 96acb6e | 2007-07-02 09:37:57 +0530 | [diff] [blame] | 1320 | /* |
| 1321 | * NetXen dma watchdog control structure |
| 1322 | * |
| 1323 | * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive |
| 1324 | * Bit 1 : disable_request => 1 req disable dma watchdog |
| 1325 | * Bit 2 : enable_request => 1 req enable dma watchdog |
| 1326 | * Bit 3-31 : unused |
| 1327 | */ |
| 1328 | |
| 1329 | #define netxen_set_dma_watchdog_disable_req(config_word) \ |
| 1330 | _netxen_set_bits(config_word, 1, 1, 1) |
| 1331 | #define netxen_set_dma_watchdog_enable_req(config_word) \ |
| 1332 | _netxen_set_bits(config_word, 2, 1, 1) |
| 1333 | #define netxen_get_dma_watchdog_enabled(config_word) \ |
| 1334 | ((config_word) & 0x1) |
| 1335 | #define netxen_get_dma_watchdog_disabled(config_word) \ |
| 1336 | (((config_word) >> 1) & 0x1) |
| 1337 | |
Mithlesh Thukral | 13ba9c7 | 2007-04-20 07:53:05 -0700 | [diff] [blame] | 1338 | int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter); |
| 1339 | int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter); |
| 1340 | int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter); |
| 1341 | int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter); |
Mithlesh Thukral | 13ba9c7 | 2007-04-20 07:53:05 -0700 | [diff] [blame] | 1342 | int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg, |
Al Viro | a608ab9 | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 1343 | __u32 * readval); |
Mithlesh Thukral | 13ba9c7 | 2007-04-20 07:53:05 -0700 | [diff] [blame] | 1344 | int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter, |
Al Viro | a608ab9 | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 1345 | long reg, __u32 val); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1346 | |
| 1347 | /* Functions available from netxen_nic_hw.c */ |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 1348 | int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu); |
| 1349 | int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu); |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 1350 | |
Dhananjay Phadke | 3d0a3cc | 2009-05-05 19:05:08 +0000 | [diff] [blame] | 1351 | int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr); |
| 1352 | int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr); |
| 1353 | |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 1354 | #define NXRD32(adapter, off) \ |
| 1355 | (adapter->hw_read_wx(adapter, off)) |
| 1356 | #define NXWR32(adapter, off, val) \ |
| 1357 | (adapter->hw_write_wx(adapter, off, val)) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1358 | |
| 1359 | int netxen_nic_get_board_info(struct netxen_adapter *adapter); |
Dhananjay Phadke | 1e2d005 | 2009-03-09 08:50:56 +0000 | [diff] [blame] | 1360 | void netxen_nic_get_firmware_info(struct netxen_adapter *adapter); |
Dhananjay Phadke | 0b72e65 | 2009-03-13 14:52:02 +0000 | [diff] [blame] | 1361 | int netxen_nic_wol_supported(struct netxen_adapter *adapter); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1362 | |
Dhananjay Phadke | 1fbe632 | 2009-04-07 22:50:44 +0000 | [diff] [blame] | 1363 | u32 netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1364 | int netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, |
Dhananjay Phadke | 1fbe632 | 2009-04-07 22:50:44 +0000 | [diff] [blame] | 1365 | ulong off, u32 data); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1366 | int netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter, |
| 1367 | u64 off, void *data, int size); |
| 1368 | int netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter, |
| 1369 | u64 off, void *data, int size); |
| 1370 | int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter, |
| 1371 | u64 off, u32 data); |
| 1372 | u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off); |
| 1373 | void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter, |
| 1374 | u64 off, u32 data); |
| 1375 | u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off); |
| 1376 | unsigned long netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter, |
| 1377 | unsigned long long addr); |
| 1378 | void netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter, |
| 1379 | u32 wndw); |
| 1380 | |
Dhananjay Phadke | 1fbe632 | 2009-04-07 22:50:44 +0000 | [diff] [blame] | 1381 | u32 netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1382 | int netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, |
Dhananjay Phadke | 1fbe632 | 2009-04-07 22:50:44 +0000 | [diff] [blame] | 1383 | ulong off, u32 data); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1384 | int netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter, |
| 1385 | u64 off, void *data, int size); |
| 1386 | int netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter, |
| 1387 | u64 off, void *data, int size); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1388 | int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter, |
| 1389 | u64 off, u32 data); |
| 1390 | u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off); |
| 1391 | void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter, |
| 1392 | u64 off, u32 data); |
| 1393 | u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off); |
| 1394 | unsigned long netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter, |
| 1395 | unsigned long long addr); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1396 | |
| 1397 | /* Functions from netxen_nic_init.c */ |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 1398 | void netxen_free_adapter_offload(struct netxen_adapter *adapter); |
| 1399 | int netxen_initialize_adapter_offload(struct netxen_adapter *adapter); |
Dhananjay Phadke | 96acb6e | 2007-07-02 09:37:57 +0530 | [diff] [blame] | 1400 | int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val); |
| 1401 | int netxen_load_firmware(struct netxen_adapter *adapter); |
Dhananjay Phadke | 67c38fc | 2009-07-01 11:41:43 +0000 | [diff] [blame] | 1402 | int netxen_need_fw_reset(struct netxen_adapter *adapter); |
Dhananjay Phadke | f7185c7 | 2009-04-28 15:29:11 +0000 | [diff] [blame] | 1403 | void netxen_request_firmware(struct netxen_adapter *adapter); |
| 1404 | void netxen_release_firmware(struct netxen_adapter *adapter); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1405 | int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose); |
Dhananjay Phadke | 2956640 | 2008-07-21 19:44:04 -0700 | [diff] [blame] | 1406 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1407 | int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp); |
Jeff Garzik | 4790654 | 2007-11-23 21:23:36 -0500 | [diff] [blame] | 1408 | int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr, |
Amit S. Kale | 27d2ab5 | 2007-02-05 07:40:49 -0800 | [diff] [blame] | 1409 | u8 *bytes, size_t size); |
Jeff Garzik | 4790654 | 2007-11-23 21:23:36 -0500 | [diff] [blame] | 1410 | int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr, |
Amit S. Kale | 27d2ab5 | 2007-02-05 07:40:49 -0800 | [diff] [blame] | 1411 | u8 *bytes, size_t size); |
| 1412 | int netxen_flash_unlock(struct netxen_adapter *adapter); |
| 1413 | int netxen_backup_crbinit(struct netxen_adapter *adapter); |
| 1414 | int netxen_flash_erase_secondary(struct netxen_adapter *adapter); |
| 1415 | int netxen_flash_erase_primary(struct netxen_adapter *adapter); |
Amit S. Kale | e45d9ab | 2007-02-09 05:49:08 -0800 | [diff] [blame] | 1416 | void netxen_halt_pegs(struct netxen_adapter *adapter); |
Amit S. Kale | 27d2ab5 | 2007-02-05 07:40:49 -0800 | [diff] [blame] | 1417 | |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 1418 | int netxen_rom_se(struct netxen_adapter *adapter, int addr); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1419 | |
Dhananjay Phadke | 2956640 | 2008-07-21 19:44:04 -0700 | [diff] [blame] | 1420 | int netxen_alloc_sw_resources(struct netxen_adapter *adapter); |
| 1421 | void netxen_free_sw_resources(struct netxen_adapter *adapter); |
| 1422 | |
| 1423 | int netxen_alloc_hw_resources(struct netxen_adapter *adapter); |
| 1424 | void netxen_free_hw_resources(struct netxen_adapter *adapter); |
| 1425 | |
| 1426 | void netxen_release_rx_buffers(struct netxen_adapter *adapter); |
| 1427 | void netxen_release_tx_buffers(struct netxen_adapter *adapter); |
| 1428 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1429 | void netxen_initialize_adapter_ops(struct netxen_adapter *adapter); |
| 1430 | int netxen_init_firmware(struct netxen_adapter *adapter); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1431 | void netxen_nic_clear_stats(struct netxen_adapter *adapter); |
David Howells | 6d5aefb | 2006-12-05 19:36:26 +0000 | [diff] [blame] | 1432 | void netxen_watchdog_task(struct work_struct *work); |
Dhananjay Phadke | d8b100c | 2009-03-13 14:52:05 +0000 | [diff] [blame] | 1433 | void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid, |
| 1434 | struct nx_host_rds_ring *rds_ring); |
Dhananjay Phadke | 05aaa02 | 2008-03-17 19:59:49 -0700 | [diff] [blame] | 1435 | int netxen_process_cmd_ring(struct netxen_adapter *adapter); |
Dhananjay Phadke | d8b100c | 2009-03-13 14:52:05 +0000 | [diff] [blame] | 1436 | int netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max); |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 1437 | void netxen_p2_nic_set_multi(struct net_device *netdev); |
| 1438 | void netxen_p3_nic_set_multi(struct net_device *netdev); |
Dhananjay Phadke | 06e9d9f | 2009-01-14 20:49:22 -0800 | [diff] [blame] | 1439 | void netxen_p3_free_mac_list(struct netxen_adapter *adapter); |
Dhananjay Phadke | 9ad2764 | 2008-08-01 03:14:59 -0700 | [diff] [blame] | 1440 | int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32); |
Dhananjay Phadke | cd1f816 | 2008-07-21 19:44:09 -0700 | [diff] [blame] | 1441 | int netxen_config_intr_coalesce(struct netxen_adapter *adapter); |
Dhananjay Phadke | d8b100c | 2009-03-13 14:52:05 +0000 | [diff] [blame] | 1442 | int netxen_config_rss(struct netxen_adapter *adapter, int enable); |
Dhananjay Phadke | 3bf26ce | 2009-04-07 22:50:42 +0000 | [diff] [blame] | 1443 | int netxen_linkevent_request(struct netxen_adapter *adapter, int enable); |
| 1444 | void netxen_advert_link_change(struct netxen_adapter *adapter, int linkup); |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 1445 | |
Dhananjay Phadke | 9ad2764 | 2008-08-01 03:14:59 -0700 | [diff] [blame] | 1446 | int nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1447 | int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu); |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 1448 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1449 | int netxen_nic_set_mac(struct net_device *netdev, void *p); |
| 1450 | struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev); |
| 1451 | |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 1452 | void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter, |
Dhananjay Phadke | cb2107b | 2009-06-17 17:27:25 +0000 | [diff] [blame] | 1453 | struct nx_host_tx_ring *tx_ring); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1454 | |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 1455 | /* |
| 1456 | * NetXen Board information |
| 1457 | */ |
| 1458 | |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 1459 | #define NETXEN_MAX_SHORT_NAME 32 |
Amit S. Kale | 71bd787 | 2006-12-01 05:36:22 -0800 | [diff] [blame] | 1460 | struct netxen_brdinfo { |
Dhananjay Phadke | e98e335 | 2009-04-07 22:50:38 +0000 | [diff] [blame] | 1461 | int brdtype; /* type of board */ |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 1462 | long ports; /* max no of physical ports */ |
| 1463 | char short_name[NETXEN_MAX_SHORT_NAME]; |
Amit S. Kale | 71bd787 | 2006-12-01 05:36:22 -0800 | [diff] [blame] | 1464 | }; |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 1465 | |
Amit S. Kale | 71bd787 | 2006-12-01 05:36:22 -0800 | [diff] [blame] | 1466 | static const struct netxen_brdinfo netxen_boards[] = { |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 1467 | {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"}, |
| 1468 | {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"}, |
| 1469 | {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"}, |
| 1470 | {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"}, |
| 1471 | {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"}, |
| 1472 | {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"}, |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 1473 | {NETXEN_BRDTYPE_P3_REF_QG, 4, "Reference Quad Gig "}, |
| 1474 | {NETXEN_BRDTYPE_P3_HMEZ, 2, "Dual XGb HMEZ"}, |
| 1475 | {NETXEN_BRDTYPE_P3_10G_CX4_LP, 2, "Dual XGb CX4 LP"}, |
| 1476 | {NETXEN_BRDTYPE_P3_4_GB, 4, "Quad Gig LP"}, |
| 1477 | {NETXEN_BRDTYPE_P3_IMEZ, 2, "Dual XGb IMEZ"}, |
| 1478 | {NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"}, |
| 1479 | {NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"}, |
| 1480 | {NETXEN_BRDTYPE_P3_XG_LOM, 2, "Dual XGb LOM"}, |
Dhananjay Phadke | a70f939 | 2008-08-01 03:14:56 -0700 | [diff] [blame] | 1481 | {NETXEN_BRDTYPE_P3_4_GB_MM, 4, "NX3031 Gigabit Ethernet"}, |
| 1482 | {NETXEN_BRDTYPE_P3_10G_SFP_CT, 2, "NX3031 10 Gigabit Ethernet"}, |
| 1483 | {NETXEN_BRDTYPE_P3_10G_SFP_QT, 2, "Quanta Dual XGb SFP+"}, |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 1484 | {NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"}, |
| 1485 | {NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"} |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 1486 | }; |
| 1487 | |
Denis Cheng | ff8ac60 | 2007-09-02 18:30:18 +0800 | [diff] [blame] | 1488 | #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards) |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 1489 | |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 1490 | static inline void get_brd_name_by_type(u32 type, char *name) |
| 1491 | { |
| 1492 | int i, found = 0; |
| 1493 | for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) { |
| 1494 | if (netxen_boards[i].brdtype == type) { |
| 1495 | strcpy(name, netxen_boards[i].short_name); |
| 1496 | found = 1; |
| 1497 | break; |
| 1498 | } |
| 1499 | |
| 1500 | } |
| 1501 | if (!found) |
| 1502 | name = "Unknown"; |
| 1503 | } |
| 1504 | |
Dhananjay Phadke | 96acb6e | 2007-07-02 09:37:57 +0530 | [diff] [blame] | 1505 | static inline int |
| 1506 | dma_watchdog_shutdown_request(struct netxen_adapter *adapter) |
| 1507 | { |
| 1508 | u32 ctrl; |
| 1509 | |
| 1510 | /* check if already inactive */ |
Dhananjay Phadke | 1fbe632 | 2009-04-07 22:50:44 +0000 | [diff] [blame] | 1511 | ctrl = adapter->hw_read_wx(adapter, |
| 1512 | NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL)); |
Dhananjay Phadke | 96acb6e | 2007-07-02 09:37:57 +0530 | [diff] [blame] | 1513 | |
| 1514 | if (netxen_get_dma_watchdog_enabled(ctrl) == 0) |
| 1515 | return 1; |
| 1516 | |
| 1517 | /* Send the disable request */ |
| 1518 | netxen_set_dma_watchdog_disable_req(ctrl); |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 1519 | NXWR32(adapter, NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl); |
Dhananjay Phadke | 96acb6e | 2007-07-02 09:37:57 +0530 | [diff] [blame] | 1520 | |
| 1521 | return 0; |
| 1522 | } |
| 1523 | |
| 1524 | static inline int |
| 1525 | dma_watchdog_shutdown_poll_result(struct netxen_adapter *adapter) |
| 1526 | { |
| 1527 | u32 ctrl; |
| 1528 | |
Dhananjay Phadke | 1fbe632 | 2009-04-07 22:50:44 +0000 | [diff] [blame] | 1529 | ctrl = adapter->hw_read_wx(adapter, |
| 1530 | NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL)); |
Dhananjay Phadke | 96acb6e | 2007-07-02 09:37:57 +0530 | [diff] [blame] | 1531 | |
dhananjay@netxen.com | ceded32 | 2007-07-19 14:41:09 +0530 | [diff] [blame] | 1532 | return (netxen_get_dma_watchdog_enabled(ctrl) == 0); |
Dhananjay Phadke | 96acb6e | 2007-07-02 09:37:57 +0530 | [diff] [blame] | 1533 | } |
| 1534 | |
| 1535 | static inline int |
| 1536 | dma_watchdog_wakeup(struct netxen_adapter *adapter) |
| 1537 | { |
| 1538 | u32 ctrl; |
| 1539 | |
Dhananjay Phadke | 1fbe632 | 2009-04-07 22:50:44 +0000 | [diff] [blame] | 1540 | ctrl = adapter->hw_read_wx(adapter, |
| 1541 | NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL)); |
Dhananjay Phadke | 96acb6e | 2007-07-02 09:37:57 +0530 | [diff] [blame] | 1542 | |
| 1543 | if (netxen_get_dma_watchdog_enabled(ctrl)) |
| 1544 | return 1; |
| 1545 | |
| 1546 | /* send the wakeup request */ |
| 1547 | netxen_set_dma_watchdog_enable_req(ctrl); |
| 1548 | |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 1549 | NXWR32(adapter, NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl); |
Dhananjay Phadke | 96acb6e | 2007-07-02 09:37:57 +0530 | [diff] [blame] | 1550 | |
| 1551 | return 0; |
| 1552 | } |
| 1553 | |
| 1554 | |
Dhananjay Phadke | cb2107b | 2009-06-17 17:27:25 +0000 | [diff] [blame] | 1555 | static inline u32 netxen_tx_avail(struct nx_host_tx_ring *tx_ring) |
| 1556 | { |
| 1557 | smp_mb(); |
| 1558 | return find_diff_among(tx_ring->producer, |
| 1559 | tx_ring->sw_consumer, tx_ring->num_desc); |
| 1560 | |
| 1561 | } |
| 1562 | |
Dhananjay Phadke | 9dc28ef | 2008-08-08 00:08:39 -0700 | [diff] [blame] | 1563 | int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac); |
| 1564 | int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1565 | extern void netxen_change_ringparam(struct netxen_adapter *adapter); |
| 1566 | extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, |
| 1567 | int *valp); |
| 1568 | |
| 1569 | extern struct ethtool_ops netxen_nic_ethtool_ops; |
| 1570 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1571 | #endif /* __NETXEN_NIC_H_ */ |