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Juergen Beisert07bd1a62008-07-05 10:02:49 +02001/*
2 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * Based on code from Freescale,
6 * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
20 */
21
22#include <linux/init.h>
23#include <linux/io.h>
24#include <linux/irq.h>
25#include <linux/gpio.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010026#include <mach/hardware.h>
Juergen Beisert07bd1a62008-07-05 10:02:49 +020027#include <asm-generic/bug.h>
28
29static struct mxc_gpio_port *mxc_gpio_ports;
30static int gpio_table_size;
31
Sascha Hauer494f22d2009-05-27 18:26:51 +020032#define cpu_is_mx1_mx2() (cpu_is_mx1() || cpu_is_mx2())
33
34#define GPIO_DR (cpu_is_mx1_mx2() ? 0x1c : 0x00)
35#define GPIO_GDIR (cpu_is_mx1_mx2() ? 0x00 : 0x04)
36#define GPIO_PSR (cpu_is_mx1_mx2() ? 0x24 : 0x08)
37#define GPIO_ICR1 (cpu_is_mx1_mx2() ? 0x28 : 0x0C)
38#define GPIO_ICR2 (cpu_is_mx1_mx2() ? 0x2C : 0x10)
39#define GPIO_IMR (cpu_is_mx1_mx2() ? 0x30 : 0x14)
40#define GPIO_ISR (cpu_is_mx1_mx2() ? 0x34 : 0x18)
41#define GPIO_ISR (cpu_is_mx1_mx2() ? 0x34 : 0x18)
42
43#define GPIO_INT_LOW_LEV (cpu_is_mx1_mx2() ? 0x3 : 0x0)
44#define GPIO_INT_HIGH_LEV (cpu_is_mx1_mx2() ? 0x2 : 0x1)
45#define GPIO_INT_RISE_EDGE (cpu_is_mx1_mx2() ? 0x0 : 0x2)
46#define GPIO_INT_FALL_EDGE (cpu_is_mx1_mx2() ? 0x1 : 0x3)
47#define GPIO_INT_NONE 0x4
48
Juergen Beisert07bd1a62008-07-05 10:02:49 +020049/* Note: This driver assumes 32 GPIOs are handled in one register */
50
51static void _clear_gpio_irqstatus(struct mxc_gpio_port *port, u32 index)
52{
53 __raw_writel(1 << index, port->base + GPIO_ISR);
54}
55
56static void _set_gpio_irqenable(struct mxc_gpio_port *port, u32 index,
57 int enable)
58{
59 u32 l;
60
61 l = __raw_readl(port->base + GPIO_IMR);
62 l = (l & (~(1 << index))) | (!!enable << index);
63 __raw_writel(l, port->base + GPIO_IMR);
64}
65
66static void gpio_ack_irq(u32 irq)
67{
68 u32 gpio = irq_to_gpio(irq);
69 _clear_gpio_irqstatus(&mxc_gpio_ports[gpio / 32], gpio & 0x1f);
70}
71
72static void gpio_mask_irq(u32 irq)
73{
74 u32 gpio = irq_to_gpio(irq);
75 _set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 0);
76}
77
78static void gpio_unmask_irq(u32 irq)
79{
80 u32 gpio = irq_to_gpio(irq);
81 _set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 1);
82}
83
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +010084static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset);
85
Juergen Beisert07bd1a62008-07-05 10:02:49 +020086static int gpio_set_irq_type(u32 irq, u32 type)
87{
88 u32 gpio = irq_to_gpio(irq);
89 struct mxc_gpio_port *port = &mxc_gpio_ports[gpio / 32];
90 u32 bit, val;
91 int edge;
92 void __iomem *reg = port->base;
93
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +010094 port->both_edges &= ~(1 << (gpio & 31));
Juergen Beisert07bd1a62008-07-05 10:02:49 +020095 switch (type) {
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +010096 case IRQ_TYPE_EDGE_RISING:
Juergen Beisert07bd1a62008-07-05 10:02:49 +020097 edge = GPIO_INT_RISE_EDGE;
98 break;
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +010099 case IRQ_TYPE_EDGE_FALLING:
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200100 edge = GPIO_INT_FALL_EDGE;
101 break;
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100102 case IRQ_TYPE_EDGE_BOTH:
103 val = mxc_gpio_get(&port->chip, gpio & 31);
104 if (val) {
105 edge = GPIO_INT_LOW_LEV;
106 pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
107 } else {
108 edge = GPIO_INT_HIGH_LEV;
109 pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
110 }
111 port->both_edges |= 1 << (gpio & 31);
112 break;
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100113 case IRQ_TYPE_LEVEL_LOW:
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200114 edge = GPIO_INT_LOW_LEV;
115 break;
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100116 case IRQ_TYPE_LEVEL_HIGH:
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200117 edge = GPIO_INT_HIGH_LEV;
118 break;
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100119 default:
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200120 return -EINVAL;
121 }
122
123 reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
124 bit = gpio & 0xf;
125 val = __raw_readl(reg) & ~(0x3 << (bit << 1));
126 __raw_writel(val | (edge << (bit << 1)), reg);
127 _clear_gpio_irqstatus(port, gpio & 0x1f);
128
129 return 0;
130}
131
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100132static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
133{
134 void __iomem *reg = port->base;
135 u32 bit, val;
136 int edge;
137
138 reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
139 bit = gpio & 0xf;
140 val = __raw_readl(reg);
141 edge = (val >> (bit << 1)) & 3;
142 val &= ~(0x3 << (bit << 1));
143 switch (edge) {
144 case GPIO_INT_HIGH_LEV:
145 edge = GPIO_INT_LOW_LEV;
146 pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
147 break;
148 case GPIO_INT_LOW_LEV:
149 edge = GPIO_INT_HIGH_LEV;
150 pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
151 break;
152 default:
153 pr_err("mxc: invalid configuration for GPIO %d: %x\n",
154 gpio, edge);
155 return;
156 }
157 __raw_writel(val | (edge << (bit << 1)), reg);
158}
159
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200160/* handle n interrupts in one status register */
161static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
162{
163 u32 gpio_irq_no;
164
165 gpio_irq_no = port->virtual_irq_start;
166 for (; irq_stat != 0; irq_stat >>= 1, gpio_irq_no++) {
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100167 u32 gpio = irq_to_gpio(gpio_irq_no);
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200168
169 if ((irq_stat & 1) == 0)
170 continue;
171
172 BUG_ON(!(irq_desc[gpio_irq_no].handle_irq));
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100173
174 if (port->both_edges & (1 << (gpio & 31)))
175 mxc_flip_edge(port, gpio);
176
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200177 irq_desc[gpio_irq_no].handle_irq(gpio_irq_no,
178 &irq_desc[gpio_irq_no]);
179 }
180}
181
Paulius Zaleckascfca8b52008-11-14 11:01:38 +0100182/* MX1 and MX3 has one interrupt *per* gpio port */
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200183static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
184{
185 u32 irq_stat;
186 struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq);
187
188 irq_stat = __raw_readl(port->base + GPIO_ISR) &
189 __raw_readl(port->base + GPIO_IMR);
Sascha Hauere2c97e72009-04-21 12:39:59 +0200190
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200191 mxc_gpio_irq_handler(port, irq_stat);
192}
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200193
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200194/* MX2 has one interrupt *for all* gpio ports */
195static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
196{
197 int i;
198 u32 irq_msk, irq_stat;
199 struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq);
200
201 /* walk through all interrupt status registers */
202 for (i = 0; i < gpio_table_size; i++) {
203 irq_msk = __raw_readl(port[i].base + GPIO_IMR);
204 if (!irq_msk)
205 continue;
206
207 irq_stat = __raw_readl(port[i].base + GPIO_ISR) & irq_msk;
208 if (irq_stat)
209 mxc_gpio_irq_handler(&port[i], irq_stat);
210 }
211}
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200212
213static struct irq_chip gpio_irq_chip = {
214 .ack = gpio_ack_irq,
215 .mask = gpio_mask_irq,
216 .unmask = gpio_unmask_irq,
217 .set_type = gpio_set_irq_type,
218};
219
220static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
221 int dir)
222{
223 struct mxc_gpio_port *port =
224 container_of(chip, struct mxc_gpio_port, chip);
225 u32 l;
226
227 l = __raw_readl(port->base + GPIO_GDIR);
228 if (dir)
229 l |= 1 << offset;
230 else
231 l &= ~(1 << offset);
232 __raw_writel(l, port->base + GPIO_GDIR);
233}
234
235static void mxc_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
236{
237 struct mxc_gpio_port *port =
238 container_of(chip, struct mxc_gpio_port, chip);
239 void __iomem *reg = port->base + GPIO_DR;
240 u32 l;
241
242 l = (__raw_readl(reg) & (~(1 << offset))) | (value << offset);
243 __raw_writel(l, reg);
244}
245
246static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset)
247{
248 struct mxc_gpio_port *port =
249 container_of(chip, struct mxc_gpio_port, chip);
250
Darius Augulis5cac9d62008-10-15 10:38:30 +0200251 return (__raw_readl(port->base + GPIO_PSR) >> offset) & 1;
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200252}
253
254static int mxc_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
255{
256 _set_gpio_direction(chip, offset, 0);
257 return 0;
258}
259
260static int mxc_gpio_direction_output(struct gpio_chip *chip,
261 unsigned offset, int value)
262{
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200263 mxc_gpio_set(chip, offset, value);
Guennadi Liakhovetski999981d2009-02-12 14:27:22 +0100264 _set_gpio_direction(chip, offset, 1);
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200265 return 0;
266}
267
268int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
269{
270 int i, j;
271
272 /* save for local usage */
273 mxc_gpio_ports = port;
274 gpio_table_size = cnt;
275
276 printk(KERN_INFO "MXC GPIO hardware\n");
277
278 for (i = 0; i < cnt; i++) {
279 /* disable the interrupt and clear the status */
280 __raw_writel(0, port[i].base + GPIO_IMR);
281 __raw_writel(~0, port[i].base + GPIO_ISR);
282 for (j = port[i].virtual_irq_start;
283 j < port[i].virtual_irq_start + 32; j++) {
284 set_irq_chip(j, &gpio_irq_chip);
285 set_irq_handler(j, handle_edge_irq);
286 set_irq_flags(j, IRQF_VALID);
287 }
288
289 /* register gpio chip */
290 port[i].chip.direction_input = mxc_gpio_direction_input;
291 port[i].chip.direction_output = mxc_gpio_direction_output;
292 port[i].chip.get = mxc_gpio_get;
293 port[i].chip.set = mxc_gpio_set;
294 port[i].chip.base = i * 32;
295 port[i].chip.ngpio = 32;
296
297 /* its a serious configuration bug when it fails */
298 BUG_ON( gpiochip_add(&port[i].chip) < 0 );
299
Sascha Hauer8c25c362009-06-04 11:32:12 +0200300 if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25()) {
Sascha Hauer8afaada2009-06-15 12:36:25 +0200301 /* setup one handler for each entry */
302 set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
303 set_irq_data(port[i].irq, &port[i]);
304 }
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200305 }
306
Sascha Hauer8afaada2009-06-15 12:36:25 +0200307 if (cpu_is_mx2()) {
308 /* setup one handler for all GPIO interrupts */
309 set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler);
310 set_irq_data(port[0].irq, port);
311 }
312
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200313 return 0;
314}