blob: 778ddfe57d895c5db1a4969886bd1dac6226f5f0 [file] [log] [blame]
Quinn Jensen52c543f2007-07-09 22:06:53 +01001/*
Juergen Beisert259bcaa2008-07-05 10:02:54 +02002 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
Quinn Jensen52c543f2007-07-09 22:06:53 +010018 */
19
Paulius Zaleckasd7927e12008-11-14 11:01:39 +010020#include <linux/module.h>
Juergen Beisert259bcaa2008-07-05 10:02:54 +020021#include <linux/irq.h>
Russell Kingfced80c2008-09-06 12:10:45 +010022#include <linux/io.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010023#include <mach/common.h>
Paulius Zaleckasd7927e12008-11-14 11:01:39 +010024#include <asm/mach/irq.h>
Sascha Hauera2449092008-12-18 11:51:57 +010025#include <mach/hardware.h>
Quinn Jensen52c543f2007-07-09 22:06:53 +010026
Sascha Hauer84c9fa42009-02-18 20:59:04 +010027#define AVIC_INTCNTL 0x00 /* int control reg */
28#define AVIC_NIMASK 0x04 /* int mask reg */
29#define AVIC_INTENNUM 0x08 /* int enable number reg */
30#define AVIC_INTDISNUM 0x0C /* int disable number reg */
31#define AVIC_INTENABLEH 0x10 /* int enable reg high */
32#define AVIC_INTENABLEL 0x14 /* int enable reg low */
33#define AVIC_INTTYPEH 0x18 /* int type reg high */
34#define AVIC_INTTYPEL 0x1C /* int type reg low */
35#define AVIC_NIPRIORITY(x) (0x20 + 4 * (7 - (x))) /* int priority */
36#define AVIC_NIVECSR 0x40 /* norm int vector/status */
37#define AVIC_FIVECSR 0x44 /* fast int vector/status */
38#define AVIC_INTSRCH 0x48 /* int source reg high */
39#define AVIC_INTSRCL 0x4C /* int source reg low */
40#define AVIC_INTFRCH 0x50 /* int force reg high */
41#define AVIC_INTFRCL 0x54 /* int force reg low */
42#define AVIC_NIPNDH 0x58 /* norm int pending high */
43#define AVIC_NIPNDL 0x5C /* norm int pending low */
44#define AVIC_FIPNDH 0x60 /* fast int pending high */
45#define AVIC_FIPNDL 0x64 /* fast int pending low */
46
Sascha Hauer12b8eb82009-05-25 10:50:52 +020047void __iomem *avic_base;
Juergen Beisert259bcaa2008-07-05 10:02:54 +020048
Darius Augulis3f203012009-04-08 16:17:50 +030049int imx_irq_set_priority(unsigned char irq, unsigned char prio)
Darius Augulis479c9012008-09-09 11:29:41 +020050{
Darius Augulis3f203012009-04-08 16:17:50 +030051#ifdef CONFIG_MXC_IRQ_PRIOR
Darius Augulis479c9012008-09-09 11:29:41 +020052 unsigned int temp;
53 unsigned int mask = 0x0F << irq % 8 * 4;
54
Darius Augulis3f203012009-04-08 16:17:50 +030055 if (irq >= MXC_INTERNAL_IRQS)
56 return -EINVAL;;
Darius Augulis479c9012008-09-09 11:29:41 +020057
Sascha Hauer84c9fa42009-02-18 20:59:04 +010058 temp = __raw_readl(avic_base + AVIC_NIPRIORITY(irq / 8));
Darius Augulis479c9012008-09-09 11:29:41 +020059 temp &= ~mask;
60 temp |= prio & mask;
61
Sascha Hauer84c9fa42009-02-18 20:59:04 +010062 __raw_writel(temp, avic_base + AVIC_NIPRIORITY(irq / 8));
Darius Augulis3f203012009-04-08 16:17:50 +030063
64 return 0;
65#else
66 return -ENOSYS;
67#endif
Darius Augulis479c9012008-09-09 11:29:41 +020068}
69EXPORT_SYMBOL(imx_irq_set_priority);
Darius Augulis479c9012008-09-09 11:29:41 +020070
Paulius Zaleckasd7927e12008-11-14 11:01:39 +010071#ifdef CONFIG_FIQ
72int mxc_set_irq_fiq(unsigned int irq, unsigned int type)
73{
74 unsigned int irqt;
75
Sascha Hauer9d631b82008-12-18 11:08:55 +010076 if (irq >= MXC_INTERNAL_IRQS)
Paulius Zaleckasd7927e12008-11-14 11:01:39 +010077 return -EINVAL;
78
Sascha Hauer9d631b82008-12-18 11:08:55 +010079 if (irq < MXC_INTERNAL_IRQS / 2) {
Sascha Hauer84c9fa42009-02-18 20:59:04 +010080 irqt = __raw_readl(avic_base + AVIC_INTTYPEL) & ~(1 << irq);
81 __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEL);
Paulius Zaleckasd7927e12008-11-14 11:01:39 +010082 } else {
Sascha Hauer9d631b82008-12-18 11:08:55 +010083 irq -= MXC_INTERNAL_IRQS / 2;
Sascha Hauer84c9fa42009-02-18 20:59:04 +010084 irqt = __raw_readl(avic_base + AVIC_INTTYPEH) & ~(1 << irq);
85 __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEH);
Paulius Zaleckasd7927e12008-11-14 11:01:39 +010086 }
87
88 return 0;
89}
90EXPORT_SYMBOL(mxc_set_irq_fiq);
91#endif /* CONFIG_FIQ */
92
Robert Schwebel2c130fd2008-03-28 11:02:13 +010093/* Disable interrupt number "irq" in the AVIC */
Quinn Jensen52c543f2007-07-09 22:06:53 +010094static void mxc_mask_irq(unsigned int irq)
95{
Sascha Hauer84c9fa42009-02-18 20:59:04 +010096 __raw_writel(irq, avic_base + AVIC_INTDISNUM);
Quinn Jensen52c543f2007-07-09 22:06:53 +010097}
98
Robert Schwebel2c130fd2008-03-28 11:02:13 +010099/* Enable interrupt number "irq" in the AVIC */
Quinn Jensen52c543f2007-07-09 22:06:53 +0100100static void mxc_unmask_irq(unsigned int irq)
101{
Sascha Hauer84c9fa42009-02-18 20:59:04 +0100102 __raw_writel(irq, avic_base + AVIC_INTENNUM);
Quinn Jensen52c543f2007-07-09 22:06:53 +0100103}
104
105static struct irq_chip mxc_avic_chip = {
Juergen Beisert259bcaa2008-07-05 10:02:54 +0200106 .ack = mxc_mask_irq,
Quinn Jensen52c543f2007-07-09 22:06:53 +0100107 .mask = mxc_mask_irq,
108 .unmask = mxc_unmask_irq,
109};
110
Robert Schwebel2c130fd2008-03-28 11:02:13 +0100111/*
Quinn Jensen52c543f2007-07-09 22:06:53 +0100112 * This function initializes the AVIC hardware and disables all the
113 * interrupts. It registers the interrupt enable and disable functions
114 * to the kernel for each interrupt source.
115 */
Sascha Hauerc5aa0ad2009-05-25 17:36:19 +0200116void __init mxc_init_irq(void __iomem *irqbase)
Quinn Jensen52c543f2007-07-09 22:06:53 +0100117{
118 int i;
Quinn Jensen52c543f2007-07-09 22:06:53 +0100119
Sascha Hauerc5aa0ad2009-05-25 17:36:19 +0200120 avic_base = irqbase;
Sascha Hauer84c9fa42009-02-18 20:59:04 +0100121
Quinn Jensen52c543f2007-07-09 22:06:53 +0100122 /* put the AVIC into the reset value with
123 * all interrupts disabled
124 */
Sascha Hauer84c9fa42009-02-18 20:59:04 +0100125 __raw_writel(0, avic_base + AVIC_INTCNTL);
126 __raw_writel(0x1f, avic_base + AVIC_NIMASK);
Quinn Jensen52c543f2007-07-09 22:06:53 +0100127
128 /* disable all interrupts */
Sascha Hauer84c9fa42009-02-18 20:59:04 +0100129 __raw_writel(0, avic_base + AVIC_INTENABLEH);
130 __raw_writel(0, avic_base + AVIC_INTENABLEL);
Quinn Jensen52c543f2007-07-09 22:06:53 +0100131
132 /* all IRQ no FIQ */
Sascha Hauer84c9fa42009-02-18 20:59:04 +0100133 __raw_writel(0, avic_base + AVIC_INTTYPEH);
134 __raw_writel(0, avic_base + AVIC_INTTYPEL);
Sascha Hauer9d631b82008-12-18 11:08:55 +0100135 for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
Quinn Jensen52c543f2007-07-09 22:06:53 +0100136 set_irq_chip(i, &mxc_avic_chip);
137 set_irq_handler(i, handle_level_irq);
138 set_irq_flags(i, IRQF_VALID);
139 }
140
Darius Augulis479c9012008-09-09 11:29:41 +0200141 /* Set default priority value (0) for all IRQ's */
142 for (i = 0; i < 8; i++)
Sascha Hauer84c9fa42009-02-18 20:59:04 +0100143 __raw_writel(0, avic_base + AVIC_NIPRIORITY(i));
Quinn Jensen52c543f2007-07-09 22:06:53 +0100144
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200145 /* init architectures chained interrupt handler */
146 mxc_register_gpios();
147
Paulius Zaleckasd7927e12008-11-14 11:01:39 +0100148#ifdef CONFIG_FIQ
149 /* Initialize FIQ */
150 init_FIQ();
151#endif
152
Quinn Jensen52c543f2007-07-09 22:06:53 +0100153 printk(KERN_INFO "MXC IRQ initialized\n");
154}
Sascha Hauer84c9fa42009-02-18 20:59:04 +0100155